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KVM: MMU: avoid pte_list_desc running out in kvm_mmu_pte_write
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
0fe59128
AK		 60
61#define OpBits 5 /* Width of operand field */
b1ea50b2 62#define OpMask ((1ull << OpBits) - 1)
a9945549 63
6aa8b732
AK		 64/*
65 * Opcode effective-address decode tables.
66 * Note that we only emulate instructions that have at least one memory
67 * operand (excluding implicit stack references). We assume that stack
68 * references and instruction fetches will never occur in special memory
69 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
70 * not be handled.
71 */
72
73/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 74#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 75/* Destination operand type. */
a9945549
AK		 76#define DstShift 1
77#define ImplicitOps (OpImplicit << DstShift)
78#define DstReg (OpReg << DstShift)
79#define DstMem (OpMem << DstShift)
80#define DstAcc (OpAcc << DstShift)
81#define DstDI (OpDI << DstShift)
82#define DstMem64 (OpMem64 << DstShift)
83#define DstImmUByte (OpImmUByte << DstShift)
84#define DstDX (OpDX << DstShift)
85#define DstMask (OpMask << DstShift)
6aa8b732 86/* Source operand type. */
0fe59128
AK		 87#define SrcShift 6
88#define SrcNone (OpNone << SrcShift)
89#define SrcReg (OpReg << SrcShift)
90#define SrcMem (OpMem << SrcShift)
91#define SrcMem16 (OpMem16 << SrcShift)
92#define SrcMem32 (OpMem32 << SrcShift)
93#define SrcImm (OpImm << SrcShift)
94#define SrcImmByte (OpImmByte << SrcShift)
95#define SrcOne (OpOne << SrcShift)
96#define SrcImmUByte (OpImmUByte << SrcShift)
97#define SrcImmU (OpImmU << SrcShift)
98#define SrcSI (OpSI << SrcShift)
99#define SrcImmFAddr (OpImmFAddr << SrcShift)
100#define SrcMemFAddr (OpMemFAddr << SrcShift)
101#define SrcAcc (OpAcc << SrcShift)
102#define SrcImmU16 (OpImmU16 << SrcShift)
103#define SrcDX (OpDX << SrcShift)
104#define SrcMask (OpMask << SrcShift)
221192bd
MT		 105#define BitOp (1<<11)
106#define MemAbs (1<<12) /* Memory operand is absolute displacement */
107#define String (1<<13) /* String instruction (rep capable) */
108#define Stack (1<<14) /* Stack instruction (push/pop) */
109#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
110#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
111#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
112#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
113#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
114#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 115/* Generic ModRM decode. */
116#define ModRM (1<<19)
117/* Destination is only written; never read. */
118#define Mov (1<<20)
d8769fed 119/* Misc flags */
8ea7d6ae 120#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 121#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 122#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 123#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 124#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 125#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 126#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 127#define No64 (1<<28)
0dc8d10f 128/* Source 2 operand type */
4dd6a57d
AK		 129#define Src2Shift (29)
130#define Src2None (OpNone << Src2Shift)
131#define Src2CL (OpCL << Src2Shift)
132#define Src2ImmByte (OpImmByte << Src2Shift)
133#define Src2One (OpOne << Src2Shift)
134#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 135#define Src2ES (OpES << Src2Shift)
136#define Src2CS (OpCS << Src2Shift)
137#define Src2SS (OpSS << Src2Shift)
138#define Src2DS (OpDS << Src2Shift)
139#define Src2FS (OpFS << Src2Shift)
140#define Src2GS (OpGS << Src2Shift)
4dd6a57d 141#define Src2Mask (OpMask << Src2Shift)
6aa8b732 142
d0e53325
AK		 143#define X2(x...) x, x
144#define X3(x...) X2(x), x
145#define X4(x...) X2(x), X2(x)
146#define X5(x...) X4(x), x
147#define X6(x...) X4(x), X2(x)
148#define X7(x...) X4(x), X3(x)
149#define X8(x...) X4(x), X4(x)
150#define X16(x...) X8(x), X8(x)
83babbca 151
d65b1dee 152struct opcode {
b1ea50b2
AK		 153 u64 flags : 56;
154 u64 intercept : 8;
120df890 155 union {
ef65c889 156 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 157 struct opcode *group;
158 struct group_dual *gdual;
0d7cdee8 159 struct gprefix *gprefix;
120df890 160 } u;
d09beabd 161 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 162};
163
164struct group_dual {
165 struct opcode mod012[8];
166 struct opcode mod3[8];
d65b1dee
AK		 167};
168
0d7cdee8
AK		 169struct gprefix {
170 struct opcode pfx_no;
171 struct opcode pfx_66;
172 struct opcode pfx_f2;
173 struct opcode pfx_f3;
174};
175
6aa8b732 176/* EFLAGS bit definitions. */
d4c6a154
GN		 177#define EFLG_ID (1<<21)
178#define EFLG_VIP (1<<20)
179#define EFLG_VIF (1<<19)
180#define EFLG_AC (1<<18)
b1d86143
AP		 181#define EFLG_VM (1<<17)
182#define EFLG_RF (1<<16)
d4c6a154
GN		 183#define EFLG_IOPL (3<<12)
184#define EFLG_NT (1<<14)
6aa8b732
AK		 185#define EFLG_OF (1<<11)
186#define EFLG_DF (1<<10)
b1d86143 187#define EFLG_IF (1<<9)
d4c6a154 188#define EFLG_TF (1<<8)
6aa8b732
AK		 189#define EFLG_SF (1<<7)
190#define EFLG_ZF (1<<6)
191#define EFLG_AF (1<<4)
192#define EFLG_PF (1<<2)
193#define EFLG_CF (1<<0)
194
62bd430e
MG		 195#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
196#define EFLG_RESERVED_ONE_MASK 2
197
6aa8b732
AK		 198/*
199 * Instruction emulation:
200 * Most instructions are emulated directly via a fragment of inline assembly
201 * code. This allows us to save/restore EFLAGS and thus very easily pick up
202 * any modified flags.
203 */
204
05b3e0c2 205#if defined(CONFIG_X86_64)
6aa8b732
AK		 206#define _LO32 "k" /* force 32-bit operand */
207#define _STK "%%rsp" /* stack pointer */
208#elif defined(__i386__)
209#define _LO32 "" /* force 32-bit operand */
210#define _STK "%%esp" /* stack pointer */
211#endif
212
213/*
214 * These EFLAGS bits are restored from saved value during emulation, and
215 * any changes are written back to the saved value after emulation.
216 */
217#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
218
219/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 220#define _PRE_EFLAGS(_sav, _msk, _tmp) \
221 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
222 "movl %"_sav",%"_LO32 _tmp"; " \
223 "push %"_tmp"; " \
224 "push %"_tmp"; " \
225 "movl %"_msk",%"_LO32 _tmp"; " \
226 "andl %"_LO32 _tmp",("_STK"); " \
227 "pushf; " \
228 "notl %"_LO32 _tmp"; " \
229 "andl %"_LO32 _tmp",("_STK"); " \
230 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
231 "pop %"_tmp"; " \
232 "orl %"_LO32 _tmp",("_STK"); " \
233 "popf; " \
234 "pop %"_sav"; "
6aa8b732
AK		 235
236/* After executing instruction: write-back necessary bits in EFLAGS. */
237#define _POST_EFLAGS(_sav, _msk, _tmp) \
238 /* _sav |= EFLAGS & _msk; */ \
239 "pushf; " \
240 "pop %"_tmp"; " \
241 "andl %"_msk",%"_LO32 _tmp"; " \
242 "orl %"_LO32 _tmp",%"_sav"; "
243
dda96d8f
AK		 244#ifdef CONFIG_X86_64
245#define ON64(x) x
246#else
247#define ON64(x)
248#endif
249
a31b9cea 250#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 251 do { \
252 __asm__ __volatile__ ( \
253 _PRE_EFLAGS("0", "4", "2") \
254 _op _suffix " %"_x"3,%1; " \
255 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 256 : "=m" ((ctxt)->eflags), \
257 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 258 "=&r" (_tmp) \
a31b9cea 259 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 260 } while (0)
6b7ad61f
AK		 261
262
6aa8b732 263/* Raw emulation: instruction has two explicit operands. */
a31b9cea 264#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 265 do { \
266 unsigned long _tmp; \
267 \
a31b9cea 268 switch ((ctxt)->dst.bytes) { \
6b7ad61f 269 case 2: \
a31b9cea 270 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 271 break; \
272 case 4: \
a31b9cea 273 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 274 break; \
275 case 8: \
a31b9cea 276 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 277 break; \
278 } \
6aa8b732
AK		 279 } while (0)
280
a31b9cea 281#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 282 do { \
6b7ad61f 283 unsigned long _tmp; \
a31b9cea 284 switch ((ctxt)->dst.bytes) { \
6aa8b732 285 case 1: \
a31b9cea 286 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 287 break; \
288 default: \
a31b9cea 289 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 290 _wx, _wy, _lx, _ly, _qx, _qy); \
291 break; \
292 } \
293 } while (0)
294
295/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 296#define emulate_2op_SrcB(ctxt, _op) \
297 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 298
299/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 300#define emulate_2op_SrcV(ctxt, _op) \
301 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 302
303/* Source operand is word, long or quad sized. */
a31b9cea
AK		 304#define emulate_2op_SrcV_nobyte(ctxt, _op) \
305 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 306
d175226a 307/* Instruction has three operands and one operand is stored in ECX register */
29053a60 308#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 309 do { \
310 unsigned long _tmp; \
761441b9
AK		 311 _type _clv = (ctxt)->src2.val; \
312 _type _srcv = (ctxt)->src.val; \
313 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 314 \
315 __asm__ __volatile__ ( \
316 _PRE_EFLAGS("0", "5", "2") \
317 _op _suffix " %4,%1 \n" \
318 _POST_EFLAGS("0", "5", "2") \
761441b9 319 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 320 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
321 ); \
322 \
761441b9
AK		 323 (ctxt)->src2.val = (unsigned long) _clv; \
324 (ctxt)->src2.val = (unsigned long) _srcv; \
325 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 326 } while (0)
327
761441b9 328#define emulate_2op_cl(ctxt, _op) \
7295261c 329 do { \
761441b9 330 switch ((ctxt)->dst.bytes) { \
7295261c 331 case 2: \
29053a60 332 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 333 break; \
334 case 4: \
29053a60 335 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 336 break; \
337 case 8: \
29053a60 338 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 339 break; \
340 } \
d175226a
GT		 341 } while (0)
342
d1eef45d 343#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 344 do { \
345 unsigned long _tmp; \
346 \
dda96d8f
AK		 347 __asm__ __volatile__ ( \
348 _PRE_EFLAGS("0", "3", "2") \
349 _op _suffix " %1; " \
350 _POST_EFLAGS("0", "3", "2") \
d1eef45d 351 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 352 "=&r" (_tmp) \
353 : "i" (EFLAGS_MASK)); \
354 } while (0)
355
356/* Instruction has only one explicit operand (no source operand). */
d1eef45d 357#define emulate_1op(ctxt, _op) \
dda96d8f 358 do { \
d1eef45d
AK		 359 switch ((ctxt)->dst.bytes) { \
360 case 1: __emulate_1op(ctxt, _op, "b"); break; \
361 case 2: __emulate_1op(ctxt, _op, "w"); break; \
362 case 4: __emulate_1op(ctxt, _op, "l"); break; \
363 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 364 } \
365 } while (0)
366
e8f2b1d6 367#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 368 do { \
369 unsigned long _tmp; \
e8f2b1d6
AK		 370 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
371 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 372 \
373 __asm__ __volatile__ ( \
374 _PRE_EFLAGS("0", "5", "1") \
375 "1: \n\t" \
376 _op _suffix " %6; " \
377 "2: \n\t" \
378 _POST_EFLAGS("0", "5", "1") \
379 ".pushsection .fixup,\"ax\" \n\t" \
380 "3: movb $1, %4 \n\t" \
381 "jmp 2b \n\t" \
382 ".popsection \n\t" \
383 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 384 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
385 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
386 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
387 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 388 } while (0)
389
3f9f53b0 390/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 391#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 392 do { \
e8f2b1d6 393 switch((ctxt)->src.bytes) { \
7295261c 394 case 1: \
e8f2b1d6 395 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 396 break; \
397 case 2: \
e8f2b1d6 398 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 399 break; \
400 case 4: \
e8f2b1d6 401 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 402 break; \
403 case 8: ON64( \
e8f2b1d6 404 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 405 break; \
406 } \
407 } while (0)
408
8a76d7f2
JR		 409static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
410 enum x86_intercept intercept,
411 enum x86_intercept_stage stage)
412{
413 struct x86_instruction_info info = {
414 .intercept = intercept,
9dac77fa
AK		 415 .rep_prefix = ctxt->rep_prefix,
416 .modrm_mod = ctxt->modrm_mod,
417 .modrm_reg = ctxt->modrm_reg,
418 .modrm_rm = ctxt->modrm_rm,
419 .src_val = ctxt->src.val64,
420 .src_bytes = ctxt->src.bytes,
421 .dst_bytes = ctxt->dst.bytes,
422 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 423 .next_rip = ctxt->eip,
424 };
425
2953538e 426 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 427}
428
9dac77fa 429static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 430{
9dac77fa 431 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 432}
433
6aa8b732 434/* Access/update address held in a register, based on addressing mode. */
e4706772 435static inline unsigned long
9dac77fa 436address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 437{
9dac77fa 438 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 439 return reg;
440 else
9dac77fa 441 return reg & ad_mask(ctxt);
e4706772
HH		 442}
443
444static inline unsigned long
9dac77fa 445register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 446{
9dac77fa 447 return address_mask(ctxt, reg);
e4706772
HH		 448}
449
7a957275 450static inline void
9dac77fa 451register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 452{
9dac77fa 453 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 454 *reg += inc;
455 else
9dac77fa 456 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 457}
6aa8b732 458
9dac77fa 459static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 460{
9dac77fa 461 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 462}
098c937b 463
56697687
AK		 464static u32 desc_limit_scaled(struct desc_struct *desc)
465{
466 u32 limit = get_desc_limit(desc);
467
468 return desc->g ? (limit << 12) | 0xfff : limit;
469}
470
9dac77fa 471static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 472{
9dac77fa
AK		 473 ctxt->has_seg_override = true;
474 ctxt->seg_override = seg;
7a5b56df
AK		 475}
476
7b105ca2 477static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 478{
479 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
480 return 0;
481
7b105ca2 482 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 483}
484
9dac77fa 485static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 486{
9dac77fa 487 if (!ctxt->has_seg_override)
7a5b56df
AK		 488 return 0;
489
9dac77fa 490 return ctxt->seg_override;
7a5b56df
AK		 491}
492
35d3d4a1
AK		 493static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
494 u32 error, bool valid)
54b8486f 495{
da9cb575
AK		 496 ctxt->exception.vector = vec;
497 ctxt->exception.error_code = error;
498 ctxt->exception.error_code_valid = valid;
35d3d4a1 499 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 500}
501
3b88e41a
JR		 502static int emulate_db(struct x86_emulate_ctxt *ctxt)
503{
504 return emulate_exception(ctxt, DB_VECTOR, 0, false);
505}
506
35d3d4a1 507static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 508{
35d3d4a1 509 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 510}
511
618ff15d
AK		 512static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
513{
514 return emulate_exception(ctxt, SS_VECTOR, err, true);
515}
516
35d3d4a1 517static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 518{
35d3d4a1 519 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 520}
521
35d3d4a1 522static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 523{
35d3d4a1 524 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 525}
526
34d1f490
AK		 527static int emulate_de(struct x86_emulate_ctxt *ctxt)
528{
35d3d4a1 529 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 530}
531
1253791d
AK		 532static int emulate_nm(struct x86_emulate_ctxt *ctxt)
533{
534 return emulate_exception(ctxt, NM_VECTOR, 0, false);
535}
536
1aa36616
AK		 537static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
538{
539 u16 selector;
540 struct desc_struct desc;
541
542 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
543 return selector;
544}
545
546static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
547 unsigned seg)
548{
549 u16 dummy;
550 u32 base3;
551 struct desc_struct desc;
552
553 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
554 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
555}
556
3d9b938e 557static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 558 struct segmented_address addr,
3d9b938e 559 unsigned size, bool write, bool fetch,
52fd8b44
AK		 560 ulong *linear)
561{
618ff15d
AK		 562 struct desc_struct desc;
563 bool usable;
52fd8b44 564 ulong la;
618ff15d 565 u32 lim;
1aa36616 566 u16 sel;
618ff15d 567 unsigned cpl, rpl;
52fd8b44 568
7b105ca2 569 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 570 switch (ctxt->mode) {
571 case X86EMUL_MODE_REAL:
572 break;
573 case X86EMUL_MODE_PROT64:
574 if (((signed long)la << 16) >> 16 != la)
575 return emulate_gp(ctxt, 0);
576 break;
577 default:
1aa36616
AK		 578 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
579 addr.seg);
618ff15d
AK		 580 if (!usable)
581 goto bad;
582 /* code segment or read-only data segment */
583 if (((desc.type & 8) || !(desc.type & 2)) && write)
584 goto bad;
585 /* unreadable code segment */
3d9b938e 586 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 587 goto bad;
588 lim = desc_limit_scaled(&desc);
589 if ((desc.type & 8) || !(desc.type & 4)) {
590 /* expand-up segment */
591 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
592 goto bad;
593 } else {
594 /* exapand-down segment */
595 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
596 goto bad;
597 lim = desc.d ? 0xffffffff : 0xffff;
598 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
599 goto bad;
600 }
717746e3 601 cpl = ctxt->ops->cpl(ctxt);
1aa36616 602 rpl = sel & 3;
618ff15d
AK		 603 cpl = max(cpl, rpl);
604 if (!(desc.type & 8)) {
605 /* data segment */
606 if (cpl > desc.dpl)
607 goto bad;
608 } else if ((desc.type & 8) && !(desc.type & 4)) {
609 /* nonconforming code segment */
610 if (cpl != desc.dpl)
611 goto bad;
612 } else if ((desc.type & 8) && (desc.type & 4)) {
613 /* conforming code segment */
614 if (cpl < desc.dpl)
615 goto bad;
616 }
617 break;
618 }
9dac77fa 619 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 620 la &= (u32)-1;
621 *linear = la;
622 return X86EMUL_CONTINUE;
618ff15d
AK		 623bad:
624 if (addr.seg == VCPU_SREG_SS)
625 return emulate_ss(ctxt, addr.seg);
626 else
627 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 628}
629
3d9b938e
NE		 630static int linearize(struct x86_emulate_ctxt *ctxt,
631 struct segmented_address addr,
632 unsigned size, bool write,
633 ulong *linear)
634{
635 return __linearize(ctxt, addr, size, write, false, linear);
636}
637
638
3ca3ac4d
AK		 639static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
640 struct segmented_address addr,
641 void *data,
642 unsigned size)
643{
9fa088f4
AK		 644 int rc;
645 ulong linear;
646
83b8795a 647 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 648 if (rc != X86EMUL_CONTINUE)
649 return rc;
0f65dd70 650 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 651}
652
807941b1
TY		 653/*
654 * Fetch the next byte of the instruction being emulated which is pointed to
655 * by ctxt->_eip, then increment ctxt->_eip.
656 *
657 * Also prefetch the remaining bytes of the instruction without crossing page
658 * boundary if they are not in fetch_cache yet.
659 */
660static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 661{
9dac77fa 662 struct fetch_cache *fc = &ctxt->fetch;
62266869 663 int rc;
2fb53ad8 664 int size, cur_size;
62266869 665
807941b1 666 if (ctxt->_eip == fc->end) {
3d9b938e 667 unsigned long linear;
807941b1
TY		 668 struct segmented_address addr = { .seg = VCPU_SREG_CS,
669 .ea = ctxt->_eip };
2fb53ad8 670 cur_size = fc->end - fc->start;
807941b1
TY		 671 size = min(15UL - cur_size,
672 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 673 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 674 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 675 return rc;
ef5d75cc
TY		 676 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
677 size, &ctxt->exception);
7d88bb48 678 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 679 return rc;
2fb53ad8 680 fc->end += size;
62266869 681 }
807941b1
TY		 682 *dest = fc->data[ctxt->_eip - fc->start];
683 ctxt->_eip++;
3e2815e9 684 return X86EMUL_CONTINUE;
62266869
AK		 685}
686
687static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 688 void *dest, unsigned size)
62266869 689{
3e2815e9 690 int rc;
62266869 691
eb3c79e6 692 /* x86 instructions are limited to 15 bytes. */
7d88bb48 693 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 694 return X86EMUL_UNHANDLEABLE;
62266869 695 while (size--) {
807941b1 696 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 697 if (rc != X86EMUL_CONTINUE)
62266869
AK		 698 return rc;
699 }
3e2815e9 700 return X86EMUL_CONTINUE;
62266869
AK		 701}
702
67cbc90d 703/* Fetch next part of the instruction being emulated. */
e85a1085 704#define insn_fetch(_type, _ctxt) \
67cbc90d 705({ unsigned long _x; \
e85a1085 706 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 707 if (rc != X86EMUL_CONTINUE) \
708 goto done; \
67cbc90d
TY		 709 (_type)_x; \
710})
711
807941b1
TY		 712#define insn_fetch_arr(_arr, _size, _ctxt) \
713({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 714 if (rc != X86EMUL_CONTINUE) \
715 goto done; \
67cbc90d
TY		 716})
717
1e3c5cb0
RR		 718/*
719 * Given the 'reg' portion of a ModRM byte, and a register block, return a
720 * pointer into the block that addresses the relevant register.
721 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
722 */
723static void *decode_register(u8 modrm_reg, unsigned long *regs,
724 int highbyte_regs)
6aa8b732
AK		 725{
726 void *p;
727
728 p = &regs[modrm_reg];
729 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
730 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
731 return p;
732}
733
734static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 735 struct segmented_address addr,
6aa8b732
AK		 736 u16 *size, unsigned long *address, int op_bytes)
737{
738 int rc;
739
740 if (op_bytes == 2)
741 op_bytes = 3;
742 *address = 0;
3ca3ac4d 743 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 744 if (rc != X86EMUL_CONTINUE)
6aa8b732 745 return rc;
30b31ab6 746 addr.ea += 2;
3ca3ac4d 747 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 748 return rc;
749}
750
bbe9abbd
NK		 751static int test_cc(unsigned int condition, unsigned int flags)
752{
753 int rc = 0;
754
755 switch ((condition & 15) >> 1) {
756 case 0: /* o */
757 rc |= (flags & EFLG_OF);
758 break;
759 case 1: /* b/c/nae */
760 rc |= (flags & EFLG_CF);
761 break;
762 case 2: /* z/e */
763 rc |= (flags & EFLG_ZF);
764 break;
765 case 3: /* be/na */
766 rc |= (flags & (EFLG_CF|EFLG_ZF));
767 break;
768 case 4: /* s */
769 rc |= (flags & EFLG_SF);
770 break;
771 case 5: /* p/pe */
772 rc |= (flags & EFLG_PF);
773 break;
774 case 7: /* le/ng */
775 rc |= (flags & EFLG_ZF);
776 /* fall through */
777 case 6: /* l/nge */
778 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
779 break;
780 }
781
782 /* Odd condition identifiers (lsb == 1) have inverted sense. */
783 return (!!rc ^ (condition & 1));
784}
785
91ff3cb4
AK		 786static void fetch_register_operand(struct operand *op)
787{
788 switch (op->bytes) {
789 case 1:
790 op->val = *(u8 *)op->addr.reg;
791 break;
792 case 2:
793 op->val = *(u16 *)op->addr.reg;
794 break;
795 case 4:
796 op->val = *(u32 *)op->addr.reg;
797 break;
798 case 8:
799 op->val = *(u64 *)op->addr.reg;
800 break;
801 }
802}
803
1253791d
AK		 804static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
805{
806 ctxt->ops->get_fpu(ctxt);
807 switch (reg) {
808 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
809 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
810 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
811 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
812 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
813 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
814 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
815 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
816#ifdef CONFIG_X86_64
817 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
818 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
819 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
820 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
821 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
822 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
823 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
824 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
825#endif
826 default: BUG();
827 }
828 ctxt->ops->put_fpu(ctxt);
829}
830
831static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
832 int reg)
833{
834 ctxt->ops->get_fpu(ctxt);
835 switch (reg) {
836 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
837 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
838 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
839 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
840 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
841 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
842 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
843 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
844#ifdef CONFIG_X86_64
845 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
846 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
847 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
848 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
849 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
850 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
851 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
852 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
853#endif
854 default: BUG();
855 }
856 ctxt->ops->put_fpu(ctxt);
857}
858
859static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
860 struct operand *op,
3c118e24
AK		 861 int inhibit_bytereg)
862{
9dac77fa
AK		 863 unsigned reg = ctxt->modrm_reg;
864 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 865
9dac77fa
AK		 866 if (!(ctxt->d & ModRM))
867 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 868
9dac77fa 869 if (ctxt->d & Sse) {
1253791d
AK		 870 op->type = OP_XMM;
871 op->bytes = 16;
872 op->addr.xmm = reg;
873 read_sse_reg(ctxt, &op->vec_val, reg);
874 return;
875 }
876
3c118e24 877 op->type = OP_REG;
9dac77fa
AK		 878 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
879 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 880 op->bytes = 1;
881 } else {
9dac77fa
AK		 882 op->addr.reg = decode_register(reg, ctxt->regs, 0);
883 op->bytes = ctxt->op_bytes;
3c118e24 884 }
91ff3cb4 885 fetch_register_operand(op);
3c118e24
AK		 886 op->orig_val = op->val;
887}
888
1c73ef66 889static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 890 struct operand *op)
1c73ef66 891{
1c73ef66 892 u8 sib;
f5b4edcd 893 int index_reg = 0, base_reg = 0, scale;
3e2815e9 894 int rc = X86EMUL_CONTINUE;
2dbd0dd7 895 ulong modrm_ea = 0;
1c73ef66 896
9dac77fa
AK		 897 if (ctxt->rex_prefix) {
898 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
899 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
900 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 901 }
902
e85a1085 903 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 904 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
905 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
906 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
907 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 908
9dac77fa 909 if (ctxt->modrm_mod == 3) {
2dbd0dd7 910 op->type = OP_REG;
9dac77fa
AK		 911 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
912 op->addr.reg = decode_register(ctxt->modrm_rm,
913 ctxt->regs, ctxt->d & ByteOp);
914 if (ctxt->d & Sse) {
1253791d
AK		 915 op->type = OP_XMM;
916 op->bytes = 16;
9dac77fa
AK		 917 op->addr.xmm = ctxt->modrm_rm;
918 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 919 return rc;
920 }
2dbd0dd7 921 fetch_register_operand(op);
1c73ef66
AK		 922 return rc;
923 }
924
2dbd0dd7
AK		 925 op->type = OP_MEM;
926
9dac77fa
AK		 927 if (ctxt->ad_bytes == 2) {
928 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
929 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
930 unsigned si = ctxt->regs[VCPU_REGS_RSI];
931 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 932
933 /* 16-bit ModR/M decode. */
9dac77fa 934 switch (ctxt->modrm_mod) {
1c73ef66 935 case 0:
9dac77fa 936 if (ctxt->modrm_rm == 6)
e85a1085 937 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 938 break;
939 case 1:
e85a1085 940 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 941 break;
942 case 2:
e85a1085 943 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 944 break;
945 }
9dac77fa 946 switch (ctxt->modrm_rm) {
1c73ef66 947 case 0:
2dbd0dd7 948 modrm_ea += bx + si;
1c73ef66
AK		 949 break;
950 case 1:
2dbd0dd7 951 modrm_ea += bx + di;
1c73ef66
AK		 952 break;
953 case 2:
2dbd0dd7 954 modrm_ea += bp + si;
1c73ef66
AK		 955 break;
956 case 3:
2dbd0dd7 957 modrm_ea += bp + di;
1c73ef66
AK		 958 break;
959 case 4:
2dbd0dd7 960 modrm_ea += si;
1c73ef66
AK		 961 break;
962 case 5:
2dbd0dd7 963 modrm_ea += di;
1c73ef66
AK		 964 break;
965 case 6:
9dac77fa 966 if (ctxt->modrm_mod != 0)
2dbd0dd7 967 modrm_ea += bp;
1c73ef66
AK		 968 break;
969 case 7:
2dbd0dd7 970 modrm_ea += bx;
1c73ef66
AK		 971 break;
972 }
9dac77fa
AK		 973 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
974 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
975 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 976 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 977 } else {
978 /* 32/64-bit ModR/M decode. */
9dac77fa 979 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 980 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 981 index_reg |= (sib >> 3) & 7;
982 base_reg |= sib & 7;
983 scale = sib >> 6;
984
9dac77fa 985 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 986 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 987 else
9dac77fa 988 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 989 if (index_reg != 4)
9dac77fa
AK		 990 modrm_ea += ctxt->regs[index_reg] << scale;
991 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 992 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 993 ctxt->rip_relative = 1;
84411d85 994 } else
9dac77fa
AK		 995 modrm_ea += ctxt->regs[ctxt->modrm_rm];
996 switch (ctxt->modrm_mod) {
1c73ef66 997 case 0:
9dac77fa 998 if (ctxt->modrm_rm == 5)
e85a1085 999 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1000 break;
1001 case 1:
e85a1085 1002 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1003 break;
1004 case 2:
e85a1085 1005 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1006 break;
1007 }
1008 }
90de84f5 1009 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1010done:
1011 return rc;
1012}
1013
1014static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1015 struct operand *op)
1c73ef66 1016{
3e2815e9 1017 int rc = X86EMUL_CONTINUE;
1c73ef66 1018
2dbd0dd7 1019 op->type = OP_MEM;
9dac77fa 1020 switch (ctxt->ad_bytes) {
1c73ef66 1021 case 2:
e85a1085 1022 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1023 break;
1024 case 4:
e85a1085 1025 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1026 break;
1027 case 8:
e85a1085 1028 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1029 break;
1030 }
1031done:
1032 return rc;
1033}
1034
9dac77fa 1035static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1036{
7129eeca 1037 long sv = 0, mask;
35c843c4 1038
9dac77fa
AK		 1039 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1040 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1041
9dac77fa
AK		 1042 if (ctxt->src.bytes == 2)
1043 sv = (s16)ctxt->src.val & (s16)mask;
1044 else if (ctxt->src.bytes == 4)
1045 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1046
9dac77fa 1047 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1048 }
ba7ff2b7
WY		 1049
1050 /* only subword offset */
9dac77fa 1051 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1052}
1053
dde7e6d1 1054static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1055 unsigned long addr, void *dest, unsigned size)
6aa8b732 1056{
dde7e6d1 1057 int rc;
9dac77fa 1058 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1059
dde7e6d1
AK		 1060 while (size) {
1061 int n = min(size, 8u);
1062 size -= n;
1063 if (mc->pos < mc->end)
1064 goto read_cached;
5cd21917 1065
7b105ca2
TY		 1066 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1067 &ctxt->exception);
dde7e6d1
AK		 1068 if (rc != X86EMUL_CONTINUE)
1069 return rc;
1070 mc->end += n;
6aa8b732 1071
dde7e6d1
AK		 1072 read_cached:
1073 memcpy(dest, mc->data + mc->pos, n);
1074 mc->pos += n;
1075 dest += n;
1076 addr += n;
6aa8b732 1077 }
dde7e6d1
AK		 1078 return X86EMUL_CONTINUE;
1079}
6aa8b732 1080
3ca3ac4d
AK		 1081static int segmented_read(struct x86_emulate_ctxt *ctxt,
1082 struct segmented_address addr,
1083 void *data,
1084 unsigned size)
1085{
9fa088f4
AK		 1086 int rc;
1087 ulong linear;
1088
83b8795a 1089 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1090 if (rc != X86EMUL_CONTINUE)
1091 return rc;
7b105ca2 1092 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1093}
1094
1095static int segmented_write(struct x86_emulate_ctxt *ctxt,
1096 struct segmented_address addr,
1097 const void *data,
1098 unsigned size)
1099{
9fa088f4
AK		 1100 int rc;
1101 ulong linear;
1102
83b8795a 1103 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1104 if (rc != X86EMUL_CONTINUE)
1105 return rc;
0f65dd70
AK		 1106 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1107 &ctxt->exception);
3ca3ac4d
AK		 1108}
1109
1110static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1111 struct segmented_address addr,
1112 const void *orig_data, const void *data,
1113 unsigned size)
1114{
9fa088f4
AK		 1115 int rc;
1116 ulong linear;
1117
83b8795a 1118 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1119 if (rc != X86EMUL_CONTINUE)
1120 return rc;
0f65dd70
AK		 1121 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1122 size, &ctxt->exception);
3ca3ac4d
AK		 1123}
1124
dde7e6d1 1125static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1126 unsigned int size, unsigned short port,
1127 void *dest)
1128{
9dac77fa 1129 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1130
dde7e6d1 1131 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1132 unsigned int in_page, n;
9dac77fa
AK		 1133 unsigned int count = ctxt->rep_prefix ?
1134 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1135 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1136 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1137 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1138 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1139 count);
1140 if (n == 0)
1141 n = 1;
1142 rc->pos = rc->end = 0;
7b105ca2 1143 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1144 return 0;
1145 rc->end = n * size;
6aa8b732
AK		 1146 }
1147
dde7e6d1
AK		 1148 memcpy(dest, rc->data + rc->pos, size);
1149 rc->pos += size;
1150 return 1;
1151}
6aa8b732 1152
dde7e6d1 1153static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1154 u16 selector, struct desc_ptr *dt)
1155{
7b105ca2
TY		 1156 struct x86_emulate_ops *ops = ctxt->ops;
1157
dde7e6d1
AK		 1158 if (selector & 1 << 2) {
1159 struct desc_struct desc;
1aa36616
AK		 1160 u16 sel;
1161
dde7e6d1 1162 memset (dt, 0, sizeof *dt);
1aa36616 1163 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1164 return;
e09d082c 1165
dde7e6d1
AK		 1166 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1167 dt->address = get_desc_base(&desc);
1168 } else
4bff1e86 1169 ops->get_gdt(ctxt, dt);
dde7e6d1 1170}
120df890 1171
dde7e6d1
AK		 1172/* allowed just for 8 bytes segments */
1173static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1174 u16 selector, struct desc_struct *desc)
1175{
1176 struct desc_ptr dt;
1177 u16 index = selector >> 3;
dde7e6d1 1178 ulong addr;
120df890 1179
7b105ca2 1180 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1181
35d3d4a1
AK		 1182 if (dt.size < index * 8 + 7)
1183 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1184
7b105ca2
TY		 1185 addr = dt.address + index * 8;
1186 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1187 &ctxt->exception);
dde7e6d1 1188}
ef65c889 1189
dde7e6d1
AK		 1190/* allowed just for 8 bytes segments */
1191static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1192 u16 selector, struct desc_struct *desc)
1193{
1194 struct desc_ptr dt;
1195 u16 index = selector >> 3;
dde7e6d1 1196 ulong addr;
6aa8b732 1197
7b105ca2 1198 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1199
35d3d4a1
AK		 1200 if (dt.size < index * 8 + 7)
1201 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1202
dde7e6d1 1203 addr = dt.address + index * 8;
7b105ca2
TY		 1204 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1205 &ctxt->exception);
dde7e6d1 1206}
c7e75a3d 1207
5601d05b 1208/* Does not support long mode */
dde7e6d1 1209static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1210 u16 selector, int seg)
1211{
1212 struct desc_struct seg_desc;
1213 u8 dpl, rpl, cpl;
1214 unsigned err_vec = GP_VECTOR;
1215 u32 err_code = 0;
1216 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1217 int ret;
69f55cb1 1218
dde7e6d1 1219 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1220
dde7e6d1
AK		 1221 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1222 || ctxt->mode == X86EMUL_MODE_REAL) {
1223 /* set real mode segment descriptor */
1224 set_desc_base(&seg_desc, selector << 4);
1225 set_desc_limit(&seg_desc, 0xffff);
1226 seg_desc.type = 3;
1227 seg_desc.p = 1;
1228 seg_desc.s = 1;
1229 goto load;
1230 }
1231
1232 /* NULL selector is not valid for TR, CS and SS */
1233 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1234 && null_selector)
1235 goto exception;
1236
1237 /* TR should be in GDT only */
1238 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1239 goto exception;
1240
1241 if (null_selector) /* for NULL selector skip all following checks */
1242 goto load;
1243
7b105ca2 1244 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1245 if (ret != X86EMUL_CONTINUE)
1246 return ret;
1247
1248 err_code = selector & 0xfffc;
1249 err_vec = GP_VECTOR;
1250
1251 /* can't load system descriptor into segment selecor */
1252 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1253 goto exception;
1254
1255 if (!seg_desc.p) {
1256 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1257 goto exception;
1258 }
1259
1260 rpl = selector & 3;
1261 dpl = seg_desc.dpl;
7b105ca2 1262 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1263
1264 switch (seg) {
1265 case VCPU_SREG_SS:
1266 /*
1267 * segment is not a writable data segment or segment
1268 * selector's RPL != CPL or segment selector's RPL != CPL
1269 */
1270 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1271 goto exception;
6aa8b732 1272 break;
dde7e6d1
AK		 1273 case VCPU_SREG_CS:
1274 if (!(seg_desc.type & 8))
1275 goto exception;
1276
1277 if (seg_desc.type & 4) {
1278 /* conforming */
1279 if (dpl > cpl)
1280 goto exception;
1281 } else {
1282 /* nonconforming */
1283 if (rpl > cpl || dpl != cpl)
1284 goto exception;
1285 }
1286 /* CS(RPL) <- CPL */
1287 selector = (selector & 0xfffc) | cpl;
6aa8b732 1288 break;
dde7e6d1
AK		 1289 case VCPU_SREG_TR:
1290 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1291 goto exception;
1292 break;
1293 case VCPU_SREG_LDTR:
1294 if (seg_desc.s || seg_desc.type != 2)
1295 goto exception;
1296 break;
1297 default: /* DS, ES, FS, or GS */
4e62417b 1298 /*
dde7e6d1
AK		 1299 * segment is not a data or readable code segment or
1300 * ((segment is a data or nonconforming code segment)
1301 * and (both RPL and CPL > DPL))
4e62417b 1302 */
dde7e6d1
AK		 1303 if ((seg_desc.type & 0xa) == 0x8 ||
1304 (((seg_desc.type & 0xc) != 0xc) &&
1305 (rpl > dpl && cpl > dpl)))
1306 goto exception;
6aa8b732 1307 break;
dde7e6d1
AK		 1308 }
1309
1310 if (seg_desc.s) {
1311 /* mark segment as accessed */
1312 seg_desc.type |= 1;
7b105ca2 1313 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1314 if (ret != X86EMUL_CONTINUE)
1315 return ret;
1316 }
1317load:
7b105ca2 1318 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1319 return X86EMUL_CONTINUE;
1320exception:
1321 emulate_exception(ctxt, err_vec, err_code, true);
1322 return X86EMUL_PROPAGATE_FAULT;
1323}
1324
31be40b3
WY		 1325static void write_register_operand(struct operand *op)
1326{
1327 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1328 switch (op->bytes) {
1329 case 1:
1330 *(u8 *)op->addr.reg = (u8)op->val;
1331 break;
1332 case 2:
1333 *(u16 *)op->addr.reg = (u16)op->val;
1334 break;
1335 case 4:
1336 *op->addr.reg = (u32)op->val;
1337 break; /* 64b: zero-extend */
1338 case 8:
1339 *op->addr.reg = op->val;
1340 break;
1341 }
1342}
1343
adddcecf 1344static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1345{
1346 int rc;
dde7e6d1 1347
9dac77fa 1348 switch (ctxt->dst.type) {
dde7e6d1 1349 case OP_REG:
9dac77fa 1350 write_register_operand(&ctxt->dst);
6aa8b732 1351 break;
dde7e6d1 1352 case OP_MEM:
9dac77fa 1353 if (ctxt->lock_prefix)
3ca3ac4d 1354 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1355 ctxt->dst.addr.mem,
1356 &ctxt->dst.orig_val,
1357 &ctxt->dst.val,
1358 ctxt->dst.bytes);
341de7e3 1359 else
3ca3ac4d 1360 rc = segmented_write(ctxt,
9dac77fa
AK		 1361 ctxt->dst.addr.mem,
1362 &ctxt->dst.val,
1363 ctxt->dst.bytes);
dde7e6d1
AK		 1364 if (rc != X86EMUL_CONTINUE)
1365 return rc;
a682e354 1366 break;
1253791d 1367 case OP_XMM:
9dac77fa 1368 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1369 break;
dde7e6d1
AK		 1370 case OP_NONE:
1371 /* no writeback */
414e6277 1372 break;
dde7e6d1 1373 default:
414e6277 1374 break;
6aa8b732 1375 }
dde7e6d1
AK		 1376 return X86EMUL_CONTINUE;
1377}
6aa8b732 1378
4487b3b4 1379static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1380{
4179bb02 1381 struct segmented_address addr;
0dc8d10f 1382
9dac77fa
AK		 1383 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1384 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1385 addr.seg = VCPU_SREG_SS;
1386
1387 /* Disable writeback. */
9dac77fa
AK		 1388 ctxt->dst.type = OP_NONE;
1389 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1390}
69f55cb1 1391
dde7e6d1 1392static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1393 void *dest, int len)
1394{
dde7e6d1 1395 int rc;
90de84f5 1396 struct segmented_address addr;
8b4caf66 1397
9dac77fa 1398 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1399 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1400 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1401 if (rc != X86EMUL_CONTINUE)
1402 return rc;
1403
9dac77fa 1404 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1405 return rc;
8b4caf66
LV		 1406}
1407
c54fe504
TY		 1408static int em_pop(struct x86_emulate_ctxt *ctxt)
1409{
9dac77fa 1410 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1411}
1412
dde7e6d1 1413static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1414 void *dest, int len)
9de41573
GN		 1415{
1416 int rc;
dde7e6d1
AK		 1417 unsigned long val, change_mask;
1418 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1419 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1420
3b9be3bf 1421 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1422 if (rc != X86EMUL_CONTINUE)
1423 return rc;
9de41573 1424
dde7e6d1
AK		 1425 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1426 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1427
dde7e6d1
AK		 1428 switch(ctxt->mode) {
1429 case X86EMUL_MODE_PROT64:
1430 case X86EMUL_MODE_PROT32:
1431 case X86EMUL_MODE_PROT16:
1432 if (cpl == 0)
1433 change_mask |= EFLG_IOPL;
1434 if (cpl <= iopl)
1435 change_mask |= EFLG_IF;
1436 break;
1437 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1438 if (iopl < 3)
1439 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1440 change_mask |= EFLG_IF;
1441 break;
1442 default: /* real mode */
1443 change_mask |= (EFLG_IOPL | EFLG_IF);
1444 break;
9de41573 1445 }
dde7e6d1
AK		 1446
1447 *(unsigned long *)dest =
1448 (ctxt->eflags & ~change_mask) | (val & change_mask);
1449
1450 return rc;
9de41573
GN		 1451}
1452
62aaa2f0
TY		 1453static int em_popf(struct x86_emulate_ctxt *ctxt)
1454{
9dac77fa
AK		 1455 ctxt->dst.type = OP_REG;
1456 ctxt->dst.addr.reg = &ctxt->eflags;
1457 ctxt->dst.bytes = ctxt->op_bytes;
1458 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1459}
1460
1cd196ea 1461static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1462{
1cd196ea
AK		 1463 int seg = ctxt->src2.val;
1464
9dac77fa 1465 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1466
4487b3b4 1467 return em_push(ctxt);
7b262e90
GN		 1468}
1469
1cd196ea 1470static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1471{
1cd196ea 1472 int seg = ctxt->src2.val;
dde7e6d1
AK		 1473 unsigned long selector;
1474 int rc;
38ba30ba 1475
9dac77fa 1476 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1477 if (rc != X86EMUL_CONTINUE)
1478 return rc;
1479
7b105ca2 1480 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1481 return rc;
38ba30ba
GN		 1482}
1483
b96a7fad 1484static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1485{
9dac77fa 1486 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1487 int rc = X86EMUL_CONTINUE;
1488 int reg = VCPU_REGS_RAX;
38ba30ba 1489
dde7e6d1
AK		 1490 while (reg <= VCPU_REGS_RDI) {
1491 (reg == VCPU_REGS_RSP) ?
9dac77fa 1492 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1493
4487b3b4 1494 rc = em_push(ctxt);
dde7e6d1
AK		 1495 if (rc != X86EMUL_CONTINUE)
1496 return rc;
38ba30ba 1497
dde7e6d1 1498 ++reg;
38ba30ba 1499 }
38ba30ba 1500
dde7e6d1 1501 return rc;
38ba30ba
GN		 1502}
1503
62aaa2f0
TY		 1504static int em_pushf(struct x86_emulate_ctxt *ctxt)
1505{
9dac77fa 1506 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1507 return em_push(ctxt);
1508}
1509
b96a7fad 1510static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1511{
dde7e6d1
AK		 1512 int rc = X86EMUL_CONTINUE;
1513 int reg = VCPU_REGS_RDI;
38ba30ba 1514
dde7e6d1
AK		 1515 while (reg >= VCPU_REGS_RAX) {
1516 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1517 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1518 ctxt->op_bytes);
dde7e6d1
AK		 1519 --reg;
1520 }
38ba30ba 1521
9dac77fa 1522 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1523 if (rc != X86EMUL_CONTINUE)
1524 break;
1525 --reg;
38ba30ba 1526 }
dde7e6d1 1527 return rc;
38ba30ba
GN		 1528}
1529
7b105ca2 1530int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1531{
7b105ca2 1532 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1533 int rc;
6e154e56
MG		 1534 struct desc_ptr dt;
1535 gva_t cs_addr;
1536 gva_t eip_addr;
1537 u16 cs, eip;
6e154e56
MG		 1538
1539 /* TODO: Add limit checks */
9dac77fa 1540 ctxt->src.val = ctxt->eflags;
4487b3b4 1541 rc = em_push(ctxt);
5c56e1cf
AK		 1542 if (rc != X86EMUL_CONTINUE)
1543 return rc;
6e154e56
MG		 1544
1545 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1546
9dac77fa 1547 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1548 rc = em_push(ctxt);
5c56e1cf
AK		 1549 if (rc != X86EMUL_CONTINUE)
1550 return rc;
6e154e56 1551
9dac77fa 1552 ctxt->src.val = ctxt->_eip;
4487b3b4 1553 rc = em_push(ctxt);
5c56e1cf
AK		 1554 if (rc != X86EMUL_CONTINUE)
1555 return rc;
1556
4bff1e86 1557 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1558
1559 eip_addr = dt.address + (irq << 2);
1560 cs_addr = dt.address + (irq << 2) + 2;
1561
0f65dd70 1562 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1563 if (rc != X86EMUL_CONTINUE)
1564 return rc;
1565
0f65dd70 1566 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1567 if (rc != X86EMUL_CONTINUE)
1568 return rc;
1569
7b105ca2 1570 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1571 if (rc != X86EMUL_CONTINUE)
1572 return rc;
1573
9dac77fa 1574 ctxt->_eip = eip;
6e154e56
MG		 1575
1576 return rc;
1577}
1578
7b105ca2 1579static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1580{
1581 switch(ctxt->mode) {
1582 case X86EMUL_MODE_REAL:
7b105ca2 1583 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1584 case X86EMUL_MODE_VM86:
1585 case X86EMUL_MODE_PROT16:
1586 case X86EMUL_MODE_PROT32:
1587 case X86EMUL_MODE_PROT64:
1588 default:
1589 /* Protected mode interrupts unimplemented yet */
1590 return X86EMUL_UNHANDLEABLE;
1591 }
1592}
1593
7b105ca2 1594static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1595{
dde7e6d1
AK		 1596 int rc = X86EMUL_CONTINUE;
1597 unsigned long temp_eip = 0;
1598 unsigned long temp_eflags = 0;
1599 unsigned long cs = 0;
1600 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1601 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1602 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1603 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1604
dde7e6d1 1605 /* TODO: Add stack limit check */
38ba30ba 1606
9dac77fa 1607 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1608
dde7e6d1
AK		 1609 if (rc != X86EMUL_CONTINUE)
1610 return rc;
38ba30ba 1611
35d3d4a1
AK		 1612 if (temp_eip & ~0xffff)
1613 return emulate_gp(ctxt, 0);
38ba30ba 1614
9dac77fa 1615 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1616
dde7e6d1
AK		 1617 if (rc != X86EMUL_CONTINUE)
1618 return rc;
38ba30ba 1619
9dac77fa 1620 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1621
dde7e6d1
AK		 1622 if (rc != X86EMUL_CONTINUE)
1623 return rc;
38ba30ba 1624
7b105ca2 1625 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1626
dde7e6d1
AK		 1627 if (rc != X86EMUL_CONTINUE)
1628 return rc;
38ba30ba 1629
9dac77fa 1630 ctxt->_eip = temp_eip;
38ba30ba 1631
38ba30ba 1632
9dac77fa 1633 if (ctxt->op_bytes == 4)
dde7e6d1 1634 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1635 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1636 ctxt->eflags &= ~0xffff;
1637 ctxt->eflags |= temp_eflags;
38ba30ba 1638 }
dde7e6d1
AK		 1639
1640 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1641 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1642
1643 return rc;
38ba30ba
GN		 1644}
1645
e01991e7 1646static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1647{
dde7e6d1
AK		 1648 switch(ctxt->mode) {
1649 case X86EMUL_MODE_REAL:
7b105ca2 1650 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1651 case X86EMUL_MODE_VM86:
1652 case X86EMUL_MODE_PROT16:
1653 case X86EMUL_MODE_PROT32:
1654 case X86EMUL_MODE_PROT64:
c37eda13 1655 default:
dde7e6d1
AK		 1656 /* iret from protected mode unimplemented yet */
1657 return X86EMUL_UNHANDLEABLE;
c37eda13 1658 }
c37eda13
WY		 1659}
1660
d2f62766
TY		 1661static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1662{
d2f62766
TY		 1663 int rc;
1664 unsigned short sel;
1665
9dac77fa 1666 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1667
7b105ca2 1668 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1669 if (rc != X86EMUL_CONTINUE)
1670 return rc;
1671
9dac77fa
AK		 1672 ctxt->_eip = 0;
1673 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1674 return X86EMUL_CONTINUE;
1675}
1676
51187683 1677static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1678{
9dac77fa 1679 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1680}
1681
51187683 1682static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1683{
9dac77fa 1684 switch (ctxt->modrm_reg) {
8cdbd2c9 1685 case 0: /* rol */
a31b9cea 1686 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1687 break;
1688 case 1: /* ror */
a31b9cea 1689 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1690 break;
1691 case 2: /* rcl */
a31b9cea 1692 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1693 break;
1694 case 3: /* rcr */
a31b9cea 1695 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1696 break;
1697 case 4: /* sal/shl */
1698 case 6: /* sal/shl */
a31b9cea 1699 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1700 break;
1701 case 5: /* shr */
a31b9cea 1702 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1703 break;
1704 case 7: /* sar */
a31b9cea 1705 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1706 break;
1707 }
51187683 1708 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1709}
1710
3329ece1
AK		 1711static int em_not(struct x86_emulate_ctxt *ctxt)
1712{
1713 ctxt->dst.val = ~ctxt->dst.val;
1714 return X86EMUL_CONTINUE;
1715}
1716
1717static int em_neg(struct x86_emulate_ctxt *ctxt)
1718{
1719 emulate_1op(ctxt, "neg");
1720 return X86EMUL_CONTINUE;
1721}
1722
1723static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1724{
1725 u8 ex = 0;
1726
1727 emulate_1op_rax_rdx(ctxt, "mul", ex);
1728 return X86EMUL_CONTINUE;
1729}
1730
1731static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1732{
1733 u8 ex = 0;
1734
1735 emulate_1op_rax_rdx(ctxt, "imul", ex);
1736 return X86EMUL_CONTINUE;
1737}
1738
1739static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1740{
34d1f490 1741 u8 de = 0;
8cdbd2c9 1742
3329ece1
AK		 1743 emulate_1op_rax_rdx(ctxt, "div", de);
1744 if (de)
1745 return emulate_de(ctxt);
1746 return X86EMUL_CONTINUE;
1747}
1748
1749static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1750{
1751 u8 de = 0;
1752
1753 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1754 if (de)
1755 return emulate_de(ctxt);
8c5eee30 1756 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1757}
1758
51187683 1759static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1760{
4179bb02 1761 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1762
9dac77fa 1763 switch (ctxt->modrm_reg) {
8cdbd2c9 1764 case 0: /* inc */
d1eef45d 1765 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1766 break;
1767 case 1: /* dec */
d1eef45d 1768 emulate_1op(ctxt, "dec");
8cdbd2c9 1769 break;
d19292e4
MG		 1770 case 2: /* call near abs */ {
1771 long int old_eip;
9dac77fa
AK		 1772 old_eip = ctxt->_eip;
1773 ctxt->_eip = ctxt->src.val;
1774 ctxt->src.val = old_eip;
4487b3b4 1775 rc = em_push(ctxt);
d19292e4
MG		 1776 break;
1777 }
8cdbd2c9 1778 case 4: /* jmp abs */
9dac77fa 1779 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1780 break;
d2f62766
TY		 1781 case 5: /* jmp far */
1782 rc = em_jmp_far(ctxt);
1783 break;
8cdbd2c9 1784 case 6: /* push */
4487b3b4 1785 rc = em_push(ctxt);
8cdbd2c9 1786 break;
8cdbd2c9 1787 }
4179bb02 1788 return rc;
8cdbd2c9
LV		 1789}
1790
51187683 1791static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1792{
9dac77fa 1793 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1794
9dac77fa
AK		 1795 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1796 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1797 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1798 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1799 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1800 } else {
9dac77fa
AK		 1801 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1802 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1803
05f086f8 1804 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1805 }
1b30eaa8 1806 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1807}
1808
ebda02c2
TY		 1809static int em_ret(struct x86_emulate_ctxt *ctxt)
1810{
9dac77fa
AK		 1811 ctxt->dst.type = OP_REG;
1812 ctxt->dst.addr.reg = &ctxt->_eip;
1813 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1814 return em_pop(ctxt);
1815}
1816
e01991e7 1817static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1818{
a77ab5ea
AK		 1819 int rc;
1820 unsigned long cs;
1821
9dac77fa 1822 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1823 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1824 return rc;
9dac77fa
AK		 1825 if (ctxt->op_bytes == 4)
1826 ctxt->_eip = (u32)ctxt->_eip;
1827 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1828 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1829 return rc;
7b105ca2 1830 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1831 return rc;
1832}
1833
d4b4325f 1834static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1835{
d4b4325f 1836 int seg = ctxt->src2.val;
09b5f4d3
WY		 1837 unsigned short sel;
1838 int rc;
1839
9dac77fa 1840 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1841
7b105ca2 1842 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1843 if (rc != X86EMUL_CONTINUE)
1844 return rc;
1845
9dac77fa 1846 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1847 return rc;
1848}
1849
7b105ca2 1850static void
e66bb2cc 1851setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1852 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1853{
1aa36616
AK		 1854 u16 selector;
1855
79168fd1 1856 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1857 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1858 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1859
1860 cs->l = 0; /* will be adjusted later */
79168fd1 1861 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1862 cs->g = 1; /* 4kb granularity */
79168fd1 1863 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1864 cs->type = 0x0b; /* Read, Execute, Accessed */
1865 cs->s = 1;
1866 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1867 cs->p = 1;
1868 cs->d = 1;
e66bb2cc 1869
79168fd1
GN		 1870 set_desc_base(ss, 0); /* flat segment */
1871 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1872 ss->g = 1; /* 4kb granularity */
1873 ss->s = 1;
1874 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1875 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1876 ss->dpl = 0;
79168fd1 1877 ss->p = 1;
e66bb2cc
AP		 1878}
1879
e01991e7 1880static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1881{
7b105ca2 1882 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1883 struct desc_struct cs, ss;
e66bb2cc 1884 u64 msr_data;
79168fd1 1885 u16 cs_sel, ss_sel;
c2ad2bb3 1886 u64 efer = 0;
e66bb2cc
AP		 1887
1888 /* syscall is not available in real mode */
2e901c4c 1889 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1890 ctxt->mode == X86EMUL_MODE_VM86)
1891 return emulate_ud(ctxt);
e66bb2cc 1892
c2ad2bb3 1893 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1894 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1895
717746e3 1896 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1897 msr_data >>= 32;
79168fd1
GN		 1898 cs_sel = (u16)(msr_data & 0xfffc);
1899 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1900
c2ad2bb3 1901 if (efer & EFER_LMA) {
79168fd1 1902 cs.d = 0;
e66bb2cc
AP		 1903 cs.l = 1;
1904 }
1aa36616
AK		 1905 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1906 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1907
9dac77fa 1908 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1909 if (efer & EFER_LMA) {
e66bb2cc 1910#ifdef CONFIG_X86_64
9dac77fa 1911 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1912
717746e3 1913 ops->get_msr(ctxt,
3fb1b5db
GN		 1914 ctxt->mode == X86EMUL_MODE_PROT64 ?
1915 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1916 ctxt->_eip = msr_data;
e66bb2cc 1917
717746e3 1918 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1919 ctxt->eflags &= ~(msr_data | EFLG_RF);
1920#endif
1921 } else {
1922 /* legacy mode */
717746e3 1923 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1924 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1925
1926 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1927 }
1928
e54cfa97 1929 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1930}
1931
e01991e7 1932static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1933{
7b105ca2 1934 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1935 struct desc_struct cs, ss;
8c604352 1936 u64 msr_data;
79168fd1 1937 u16 cs_sel, ss_sel;
c2ad2bb3 1938 u64 efer = 0;
8c604352 1939
7b105ca2 1940 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1941 /* inject #GP if in real mode */
35d3d4a1
AK		 1942 if (ctxt->mode == X86EMUL_MODE_REAL)
1943 return emulate_gp(ctxt, 0);
8c604352
AP		 1944
1945 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1946 * Therefore, we inject an #UD.
1947 */
35d3d4a1
AK		 1948 if (ctxt->mode == X86EMUL_MODE_PROT64)
1949 return emulate_ud(ctxt);
8c604352 1950
7b105ca2 1951 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1952
717746e3 1953 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1954 switch (ctxt->mode) {
1955 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1956 if ((msr_data & 0xfffc) == 0x0)
1957 return emulate_gp(ctxt, 0);
8c604352
AP		 1958 break;
1959 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1960 if (msr_data == 0x0)
1961 return emulate_gp(ctxt, 0);
8c604352
AP		 1962 break;
1963 }
1964
1965 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1966 cs_sel = (u16)msr_data;
1967 cs_sel &= ~SELECTOR_RPL_MASK;
1968 ss_sel = cs_sel + 8;
1969 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1970 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1971 cs.d = 0;
8c604352
AP		 1972 cs.l = 1;
1973 }
1974
1aa36616
AK		 1975 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1976 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1977
717746e3 1978 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1979 ctxt->_eip = msr_data;
8c604352 1980
717746e3 1981 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1982 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1983
e54cfa97 1984 return X86EMUL_CONTINUE;
8c604352
AP		 1985}
1986
e01991e7 1987static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1988{
7b105ca2 1989 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1990 struct desc_struct cs, ss;
4668f050
AP		 1991 u64 msr_data;
1992 int usermode;
1249b96e 1993 u16 cs_sel = 0, ss_sel = 0;
4668f050 1994
a0044755
GN		 1995 /* inject #GP if in real mode or Virtual 8086 mode */
1996 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1997 ctxt->mode == X86EMUL_MODE_VM86)
1998 return emulate_gp(ctxt, 0);
4668f050 1999
7b105ca2 2000 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2001
9dac77fa 2002 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2003 usermode = X86EMUL_MODE_PROT64;
2004 else
2005 usermode = X86EMUL_MODE_PROT32;
2006
2007 cs.dpl = 3;
2008 ss.dpl = 3;
717746e3 2009 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2010 switch (usermode) {
2011 case X86EMUL_MODE_PROT32:
79168fd1 2012 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2013 if ((msr_data & 0xfffc) == 0x0)
2014 return emulate_gp(ctxt, 0);
79168fd1 2015 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2016 break;
2017 case X86EMUL_MODE_PROT64:
79168fd1 2018 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2019 if (msr_data == 0x0)
2020 return emulate_gp(ctxt, 0);
79168fd1
GN		 2021 ss_sel = cs_sel + 8;
2022 cs.d = 0;
4668f050
AP		 2023 cs.l = 1;
2024 break;
2025 }
79168fd1
GN		 2026 cs_sel |= SELECTOR_RPL_MASK;
2027 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2028
1aa36616
AK		 2029 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2030 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2031
9dac77fa
AK		 2032 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2033 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2034
e54cfa97 2035 return X86EMUL_CONTINUE;
4668f050
AP		 2036}
2037
7b105ca2 2038static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2039{
2040 int iopl;
2041 if (ctxt->mode == X86EMUL_MODE_REAL)
2042 return false;
2043 if (ctxt->mode == X86EMUL_MODE_VM86)
2044 return true;
2045 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2046 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2047}
2048
2049static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2050 u16 port, u16 len)
2051{
7b105ca2 2052 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2053 struct desc_struct tr_seg;
5601d05b 2054 u32 base3;
f850e2e6 2055 int r;
1aa36616 2056 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2057 unsigned mask = (1 << len) - 1;
5601d05b 2058 unsigned long base;
f850e2e6 2059
1aa36616 2060 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2061 if (!tr_seg.p)
f850e2e6 2062 return false;
79168fd1 2063 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2064 return false;
5601d05b
GN		 2065 base = get_desc_base(&tr_seg);
2066#ifdef CONFIG_X86_64
2067 base |= ((u64)base3) << 32;
2068#endif
0f65dd70 2069 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2070 if (r != X86EMUL_CONTINUE)
2071 return false;
79168fd1 2072 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2073 return false;
0f65dd70 2074 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2075 if (r != X86EMUL_CONTINUE)
2076 return false;
2077 if ((perm >> bit_idx) & mask)
2078 return false;
2079 return true;
2080}
2081
2082static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2083 u16 port, u16 len)
2084{
4fc40f07
GN		 2085 if (ctxt->perm_ok)
2086 return true;
2087
7b105ca2
TY		 2088 if (emulator_bad_iopl(ctxt))
2089 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2090 return false;
4fc40f07
GN		 2091
2092 ctxt->perm_ok = true;
2093
f850e2e6
GN		 2094 return true;
2095}
2096
38ba30ba 2097static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2098 struct tss_segment_16 *tss)
2099{
9dac77fa 2100 tss->ip = ctxt->_eip;
38ba30ba 2101 tss->flag = ctxt->eflags;
9dac77fa
AK		 2102 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2103 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2104 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2105 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2106 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2107 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2108 tss->si = ctxt->regs[VCPU_REGS_RSI];
2109 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2110
1aa36616
AK		 2111 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2112 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2113 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2114 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2115 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2116}
2117
2118static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2119 struct tss_segment_16 *tss)
2120{
38ba30ba
GN		 2121 int ret;
2122
9dac77fa 2123 ctxt->_eip = tss->ip;
38ba30ba 2124 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2125 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2126 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2127 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2128 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2129 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2130 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2131 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2132 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2133
2134 /*
2135 * SDM says that segment selectors are loaded before segment
2136 * descriptors
2137 */
1aa36616
AK		 2138 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2139 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2140 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2141 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2142 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2143
2144 /*
2145 * Now load segment descriptors. If fault happenes at this stage
2146 * it is handled in a context of new task
2147 */
7b105ca2 2148 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2149 if (ret != X86EMUL_CONTINUE)
2150 return ret;
7b105ca2 2151 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2152 if (ret != X86EMUL_CONTINUE)
2153 return ret;
7b105ca2 2154 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2155 if (ret != X86EMUL_CONTINUE)
2156 return ret;
7b105ca2 2157 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2158 if (ret != X86EMUL_CONTINUE)
2159 return ret;
7b105ca2 2160 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2161 if (ret != X86EMUL_CONTINUE)
2162 return ret;
2163
2164 return X86EMUL_CONTINUE;
2165}
2166
2167static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2168 u16 tss_selector, u16 old_tss_sel,
2169 ulong old_tss_base, struct desc_struct *new_desc)
2170{
7b105ca2 2171 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2172 struct tss_segment_16 tss_seg;
2173 int ret;
bcc55cba 2174 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2175
0f65dd70 2176 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2177 &ctxt->exception);
db297e3d 2178 if (ret != X86EMUL_CONTINUE)
38ba30ba 2179 /* FIXME: need to provide precise fault address */
38ba30ba 2180 return ret;
38ba30ba 2181
7b105ca2 2182 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2183
0f65dd70 2184 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2185 &ctxt->exception);
db297e3d 2186 if (ret != X86EMUL_CONTINUE)
38ba30ba 2187 /* FIXME: need to provide precise fault address */
38ba30ba 2188 return ret;
38ba30ba 2189
0f65dd70 2190 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2191 &ctxt->exception);
db297e3d 2192 if (ret != X86EMUL_CONTINUE)
38ba30ba 2193 /* FIXME: need to provide precise fault address */
38ba30ba 2194 return ret;
38ba30ba
GN		 2195
2196 if (old_tss_sel != 0xffff) {
2197 tss_seg.prev_task_link = old_tss_sel;
2198
0f65dd70 2199 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2200 &tss_seg.prev_task_link,
2201 sizeof tss_seg.prev_task_link,
0f65dd70 2202 &ctxt->exception);
db297e3d 2203 if (ret != X86EMUL_CONTINUE)
38ba30ba 2204 /* FIXME: need to provide precise fault address */
38ba30ba 2205 return ret;
38ba30ba
GN		 2206 }
2207
7b105ca2 2208 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2209}
2210
2211static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2212 struct tss_segment_32 *tss)
2213{
7b105ca2 2214 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2215 tss->eip = ctxt->_eip;
38ba30ba 2216 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2217 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2218 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2219 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2220 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2221 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2222 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2223 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2224 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2225
1aa36616
AK		 2226 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2227 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2228 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2229 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2230 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2231 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2232 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2233}
2234
2235static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2236 struct tss_segment_32 *tss)
2237{
38ba30ba
GN		 2238 int ret;
2239
7b105ca2 2240 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2241 return emulate_gp(ctxt, 0);
9dac77fa 2242 ctxt->_eip = tss->eip;
38ba30ba 2243 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2244 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2245 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2246 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2247 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2248 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2249 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2250 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2251 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2252
2253 /*
2254 * SDM says that segment selectors are loaded before segment
2255 * descriptors
2256 */
1aa36616
AK		 2257 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2258 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2259 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2260 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2261 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2262 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2263 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2264
2265 /*
2266 * Now load segment descriptors. If fault happenes at this stage
2267 * it is handled in a context of new task
2268 */
7b105ca2 2269 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2270 if (ret != X86EMUL_CONTINUE)
2271 return ret;
7b105ca2 2272 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2273 if (ret != X86EMUL_CONTINUE)
2274 return ret;
7b105ca2 2275 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2276 if (ret != X86EMUL_CONTINUE)
2277 return ret;
7b105ca2 2278 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2279 if (ret != X86EMUL_CONTINUE)
2280 return ret;
7b105ca2 2281 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2282 if (ret != X86EMUL_CONTINUE)
2283 return ret;
7b105ca2 2284 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2285 if (ret != X86EMUL_CONTINUE)
2286 return ret;
7b105ca2 2287 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2288 if (ret != X86EMUL_CONTINUE)
2289 return ret;
2290
2291 return X86EMUL_CONTINUE;
2292}
2293
2294static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2295 u16 tss_selector, u16 old_tss_sel,
2296 ulong old_tss_base, struct desc_struct *new_desc)
2297{
7b105ca2 2298 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2299 struct tss_segment_32 tss_seg;
2300 int ret;
bcc55cba 2301 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2302
0f65dd70 2303 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2304 &ctxt->exception);
db297e3d 2305 if (ret != X86EMUL_CONTINUE)
38ba30ba 2306 /* FIXME: need to provide precise fault address */
38ba30ba 2307 return ret;
38ba30ba 2308
7b105ca2 2309 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2310
0f65dd70 2311 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2312 &ctxt->exception);
db297e3d 2313 if (ret != X86EMUL_CONTINUE)
38ba30ba 2314 /* FIXME: need to provide precise fault address */
38ba30ba 2315 return ret;
38ba30ba 2316
0f65dd70 2317 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2318 &ctxt->exception);
db297e3d 2319 if (ret != X86EMUL_CONTINUE)
38ba30ba 2320 /* FIXME: need to provide precise fault address */
38ba30ba 2321 return ret;
38ba30ba
GN		 2322
2323 if (old_tss_sel != 0xffff) {
2324 tss_seg.prev_task_link = old_tss_sel;
2325
0f65dd70 2326 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2327 &tss_seg.prev_task_link,
2328 sizeof tss_seg.prev_task_link,
0f65dd70 2329 &ctxt->exception);
db297e3d 2330 if (ret != X86EMUL_CONTINUE)
38ba30ba 2331 /* FIXME: need to provide precise fault address */
38ba30ba 2332 return ret;
38ba30ba
GN		 2333 }
2334
7b105ca2 2335 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2336}
2337
2338static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2339 u16 tss_selector, int reason,
2340 bool has_error_code, u32 error_code)
38ba30ba 2341{
7b105ca2 2342 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2343 struct desc_struct curr_tss_desc, next_tss_desc;
2344 int ret;
1aa36616 2345 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2346 ulong old_tss_base =
4bff1e86 2347 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2348 u32 desc_limit;
38ba30ba
GN		 2349
2350 /* FIXME: old_tss_base == ~0 ? */
2351
7b105ca2 2352 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2353 if (ret != X86EMUL_CONTINUE)
2354 return ret;
7b105ca2 2355 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2356 if (ret != X86EMUL_CONTINUE)
2357 return ret;
2358
2359 /* FIXME: check that next_tss_desc is tss */
2360
2361 if (reason != TASK_SWITCH_IRET) {
2362 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2363 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2364 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2365 }
2366
ceffb459
GN		 2367 desc_limit = desc_limit_scaled(&next_tss_desc);
2368 if (!next_tss_desc.p ||
2369 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2370 desc_limit < 0x2b)) {
54b8486f 2371 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2372 return X86EMUL_PROPAGATE_FAULT;
2373 }
2374
2375 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2376 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2377 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2378 }
2379
2380 if (reason == TASK_SWITCH_IRET)
2381 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2382
2383 /* set back link to prev task only if NT bit is set in eflags
2384 note that old_tss_sel is not used afetr this point */
2385 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2386 old_tss_sel = 0xffff;
2387
2388 if (next_tss_desc.type & 8)
7b105ca2 2389 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2390 old_tss_base, &next_tss_desc);
2391 else
7b105ca2 2392 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2393 old_tss_base, &next_tss_desc);
0760d448
JK		 2394 if (ret != X86EMUL_CONTINUE)
2395 return ret;
38ba30ba
GN		 2396
2397 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2398 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2399
2400 if (reason != TASK_SWITCH_IRET) {
2401 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2402 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2403 }
2404
717746e3 2405 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2406 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2407
e269fb21 2408 if (has_error_code) {
9dac77fa
AK		 2409 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2410 ctxt->lock_prefix = 0;
2411 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2412 ret = em_push(ctxt);
e269fb21
JK		 2413 }
2414
38ba30ba
GN		 2415 return ret;
2416}
2417
2418int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2419 u16 tss_selector, int reason,
2420 bool has_error_code, u32 error_code)
38ba30ba 2421{
38ba30ba
GN		 2422 int rc;
2423
9dac77fa
AK		 2424 ctxt->_eip = ctxt->eip;
2425 ctxt->dst.type = OP_NONE;
38ba30ba 2426
7b105ca2 2427 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2428 has_error_code, error_code);
38ba30ba 2429
4179bb02 2430 if (rc == X86EMUL_CONTINUE)
9dac77fa 2431 ctxt->eip = ctxt->_eip;
38ba30ba 2432
a0c0ab2f 2433 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2434}
2435
90de84f5 2436static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2437 int reg, struct operand *op)
a682e354 2438{
a682e354
GN		 2439 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2440
9dac77fa
AK		 2441 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2442 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2443 op->addr.mem.seg = seg;
a682e354
GN		 2444}
2445
7af04fc0
AK		 2446static int em_das(struct x86_emulate_ctxt *ctxt)
2447{
7af04fc0
AK		 2448 u8 al, old_al;
2449 bool af, cf, old_cf;
2450
2451 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2452 al = ctxt->dst.val;
7af04fc0
AK		 2453
2454 old_al = al;
2455 old_cf = cf;
2456 cf = false;
2457 af = ctxt->eflags & X86_EFLAGS_AF;
2458 if ((al & 0x0f) > 9 || af) {
2459 al -= 6;
2460 cf = old_cf | (al >= 250);
2461 af = true;
2462 } else {
2463 af = false;
2464 }
2465 if (old_al > 0x99 || old_cf) {
2466 al -= 0x60;
2467 cf = true;
2468 }
2469
9dac77fa 2470 ctxt->dst.val = al;
7af04fc0 2471 /* Set PF, ZF, SF */
9dac77fa
AK		 2472 ctxt->src.type = OP_IMM;
2473 ctxt->src.val = 0;
2474 ctxt->src.bytes = 1;
a31b9cea 2475 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2476 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2477 if (cf)
2478 ctxt->eflags |= X86_EFLAGS_CF;
2479 if (af)
2480 ctxt->eflags |= X86_EFLAGS_AF;
2481 return X86EMUL_CONTINUE;
2482}
2483
0ef753b8
AK		 2484static int em_call_far(struct x86_emulate_ctxt *ctxt)
2485{
0ef753b8
AK		 2486 u16 sel, old_cs;
2487 ulong old_eip;
2488 int rc;
2489
1aa36616 2490 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2491 old_eip = ctxt->_eip;
0ef753b8 2492
9dac77fa 2493 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2494 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2495 return X86EMUL_CONTINUE;
2496
9dac77fa
AK		 2497 ctxt->_eip = 0;
2498 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2499
9dac77fa 2500 ctxt->src.val = old_cs;
4487b3b4 2501 rc = em_push(ctxt);
0ef753b8
AK		 2502 if (rc != X86EMUL_CONTINUE)
2503 return rc;
2504
9dac77fa 2505 ctxt->src.val = old_eip;
4487b3b4 2506 return em_push(ctxt);
0ef753b8
AK		 2507}
2508
40ece7c7
AK		 2509static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2510{
40ece7c7
AK		 2511 int rc;
2512
9dac77fa
AK		 2513 ctxt->dst.type = OP_REG;
2514 ctxt->dst.addr.reg = &ctxt->_eip;
2515 ctxt->dst.bytes = ctxt->op_bytes;
2516 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2517 if (rc != X86EMUL_CONTINUE)
2518 return rc;
9dac77fa 2519 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2520 return X86EMUL_CONTINUE;
2521}
2522
d67fc27a
TY		 2523static int em_add(struct x86_emulate_ctxt *ctxt)
2524{
a31b9cea 2525 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2526 return X86EMUL_CONTINUE;
2527}
2528
2529static int em_or(struct x86_emulate_ctxt *ctxt)
2530{
a31b9cea 2531 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2532 return X86EMUL_CONTINUE;
2533}
2534
2535static int em_adc(struct x86_emulate_ctxt *ctxt)
2536{
a31b9cea 2537 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2538 return X86EMUL_CONTINUE;
2539}
2540
2541static int em_sbb(struct x86_emulate_ctxt *ctxt)
2542{
a31b9cea 2543 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2544 return X86EMUL_CONTINUE;
2545}
2546
2547static int em_and(struct x86_emulate_ctxt *ctxt)
2548{
a31b9cea 2549 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2550 return X86EMUL_CONTINUE;
2551}
2552
2553static int em_sub(struct x86_emulate_ctxt *ctxt)
2554{
a31b9cea 2555 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2556 return X86EMUL_CONTINUE;
2557}
2558
2559static int em_xor(struct x86_emulate_ctxt *ctxt)
2560{
a31b9cea 2561 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2562 return X86EMUL_CONTINUE;
2563}
2564
2565static int em_cmp(struct x86_emulate_ctxt *ctxt)
2566{
a31b9cea 2567 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2568 /* Disable writeback. */
9dac77fa 2569 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2570 return X86EMUL_CONTINUE;
2571}
2572
9f21ca59
TY		 2573static int em_test(struct x86_emulate_ctxt *ctxt)
2574{
a31b9cea 2575 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2576 /* Disable writeback. */
2577 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2578 return X86EMUL_CONTINUE;
2579}
2580
e4f973ae
TY		 2581static int em_xchg(struct x86_emulate_ctxt *ctxt)
2582{
e4f973ae 2583 /* Write back the register source. */
9dac77fa
AK		 2584 ctxt->src.val = ctxt->dst.val;
2585 write_register_operand(&ctxt->src);
e4f973ae
TY		 2586
2587 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2588 ctxt->dst.val = ctxt->src.orig_val;
2589 ctxt->lock_prefix = 1;
e4f973ae
TY		 2590 return X86EMUL_CONTINUE;
2591}
2592
5c82aa29 2593static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2594{
a31b9cea 2595 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2596 return X86EMUL_CONTINUE;
2597}
2598
5c82aa29
AK		 2599static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2600{
9dac77fa 2601 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2602 return em_imul(ctxt);
2603}
2604
61429142
AK		 2605static int em_cwd(struct x86_emulate_ctxt *ctxt)
2606{
9dac77fa
AK		 2607 ctxt->dst.type = OP_REG;
2608 ctxt->dst.bytes = ctxt->src.bytes;
2609 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2610 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2611
2612 return X86EMUL_CONTINUE;
2613}
2614
48bb5d3c
AK		 2615static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2616{
48bb5d3c
AK		 2617 u64 tsc = 0;
2618
717746e3 2619 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2620 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2621 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2622 return X86EMUL_CONTINUE;
2623}
2624
b9eac5f4
AK		 2625static int em_mov(struct x86_emulate_ctxt *ctxt)
2626{
9dac77fa 2627 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2628 return X86EMUL_CONTINUE;
2629}
2630
1bd5f469
TY		 2631static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2632{
9dac77fa 2633 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2634 return emulate_ud(ctxt);
2635
9dac77fa 2636 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2637 return X86EMUL_CONTINUE;
2638}
2639
2640static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2641{
9dac77fa 2642 u16 sel = ctxt->src.val;
1bd5f469 2643
9dac77fa 2644 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2645 return emulate_ud(ctxt);
2646
9dac77fa 2647 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2648 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2649
2650 /* Disable writeback. */
9dac77fa
AK		 2651 ctxt->dst.type = OP_NONE;
2652 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2653}
2654
aa97bb48
AK		 2655static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2656{
9dac77fa 2657 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2658 return X86EMUL_CONTINUE;
2659}
2660
38503911
AK		 2661static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2662{
9fa088f4
AK		 2663 int rc;
2664 ulong linear;
2665
9dac77fa 2666 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2667 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2668 ctxt->ops->invlpg(ctxt, linear);
38503911 2669 /* Disable writeback. */
9dac77fa 2670 ctxt->dst.type = OP_NONE;
38503911
AK		 2671 return X86EMUL_CONTINUE;
2672}
2673
2d04a05b
AK		 2674static int em_clts(struct x86_emulate_ctxt *ctxt)
2675{
2676 ulong cr0;
2677
2678 cr0 = ctxt->ops->get_cr(ctxt, 0);
2679 cr0 &= ~X86_CR0_TS;
2680 ctxt->ops->set_cr(ctxt, 0, cr0);
2681 return X86EMUL_CONTINUE;
2682}
2683
26d05cc7
AK		 2684static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2685{
26d05cc7
AK		 2686 int rc;
2687
9dac77fa 2688 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2689 return X86EMUL_UNHANDLEABLE;
2690
2691 rc = ctxt->ops->fix_hypercall(ctxt);
2692 if (rc != X86EMUL_CONTINUE)
2693 return rc;
2694
2695 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2696 ctxt->_eip = ctxt->eip;
26d05cc7 2697 /* Disable writeback. */
9dac77fa 2698 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2699 return X86EMUL_CONTINUE;
2700}
2701
2702static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2703{
26d05cc7
AK		 2704 struct desc_ptr desc_ptr;
2705 int rc;
2706
9dac77fa 2707 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2708 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2709 ctxt->op_bytes);
26d05cc7
AK		 2710 if (rc != X86EMUL_CONTINUE)
2711 return rc;
2712 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2713 /* Disable writeback. */
9dac77fa 2714 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2715 return X86EMUL_CONTINUE;
2716}
2717
5ef39c71 2718static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2719{
26d05cc7
AK		 2720 int rc;
2721
5ef39c71
AK		 2722 rc = ctxt->ops->fix_hypercall(ctxt);
2723
26d05cc7 2724 /* Disable writeback. */
9dac77fa 2725 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2726 return rc;
2727}
2728
2729static int em_lidt(struct x86_emulate_ctxt *ctxt)
2730{
26d05cc7
AK		 2731 struct desc_ptr desc_ptr;
2732 int rc;
2733
9dac77fa 2734 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2735 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2736 ctxt->op_bytes);
26d05cc7
AK		 2737 if (rc != X86EMUL_CONTINUE)
2738 return rc;
2739 ctxt->ops->set_idt(ctxt, &desc_ptr);
2740 /* Disable writeback. */
9dac77fa 2741 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2742 return X86EMUL_CONTINUE;
2743}
2744
2745static int em_smsw(struct x86_emulate_ctxt *ctxt)
2746{
9dac77fa
AK		 2747 ctxt->dst.bytes = 2;
2748 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2749 return X86EMUL_CONTINUE;
2750}
2751
2752static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2753{
26d05cc7 2754 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2755 | (ctxt->src.val & 0x0f));
2756 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2757 return X86EMUL_CONTINUE;
2758}
2759
d06e03ad
TY		 2760static int em_loop(struct x86_emulate_ctxt *ctxt)
2761{
9dac77fa
AK		 2762 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2763 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2764 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2765 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2766
2767 return X86EMUL_CONTINUE;
2768}
2769
2770static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2771{
9dac77fa
AK		 2772 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2773 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2774
2775 return X86EMUL_CONTINUE;
2776}
2777
f411e6cd
TY		 2778static int em_cli(struct x86_emulate_ctxt *ctxt)
2779{
2780 if (emulator_bad_iopl(ctxt))
2781 return emulate_gp(ctxt, 0);
2782
2783 ctxt->eflags &= ~X86_EFLAGS_IF;
2784 return X86EMUL_CONTINUE;
2785}
2786
2787static int em_sti(struct x86_emulate_ctxt *ctxt)
2788{
2789 if (emulator_bad_iopl(ctxt))
2790 return emulate_gp(ctxt, 0);
2791
2792 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2793 ctxt->eflags |= X86_EFLAGS_IF;
2794 return X86EMUL_CONTINUE;
2795}
2796
cfec82cb
JR		 2797static bool valid_cr(int nr)
2798{
2799 switch (nr) {
2800 case 0:
2801 case 2 ... 4:
2802 case 8:
2803 return true;
2804 default:
2805 return false;
2806 }
2807}
2808
2809static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2810{
9dac77fa 2811 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2812 return emulate_ud(ctxt);
2813
2814 return X86EMUL_CONTINUE;
2815}
2816
2817static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2818{
9dac77fa
AK		 2819 u64 new_val = ctxt->src.val64;
2820 int cr = ctxt->modrm_reg;
c2ad2bb3 2821 u64 efer = 0;
cfec82cb
JR		 2822
2823 static u64 cr_reserved_bits[] = {
2824 0xffffffff00000000ULL,
2825 0, 0, 0, /* CR3 checked later */
2826 CR4_RESERVED_BITS,
2827 0, 0, 0,
2828 CR8_RESERVED_BITS,
2829 };
2830
2831 if (!valid_cr(cr))
2832 return emulate_ud(ctxt);
2833
2834 if (new_val & cr_reserved_bits[cr])
2835 return emulate_gp(ctxt, 0);
2836
2837 switch (cr) {
2838 case 0: {
c2ad2bb3 2839 u64 cr4;
cfec82cb
JR		 2840 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2841 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2842 return emulate_gp(ctxt, 0);
2843
717746e3
AK		 2844 cr4 = ctxt->ops->get_cr(ctxt, 4);
2845 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2846
2847 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2848 !(cr4 & X86_CR4_PAE))
2849 return emulate_gp(ctxt, 0);
2850
2851 break;
2852 }
2853 case 3: {
2854 u64 rsvd = 0;
2855
c2ad2bb3
AK		 2856 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2857 if (efer & EFER_LMA)
cfec82cb 2858 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2859 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2860 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2861 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2862 rsvd = CR3_NONPAE_RESERVED_BITS;
2863
2864 if (new_val & rsvd)
2865 return emulate_gp(ctxt, 0);
2866
2867 break;
2868 }
2869 case 4: {
c2ad2bb3 2870 u64 cr4;
cfec82cb 2871
717746e3
AK		 2872 cr4 = ctxt->ops->get_cr(ctxt, 4);
2873 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2874
2875 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2876 return emulate_gp(ctxt, 0);
2877
2878 break;
2879 }
2880 }
2881
2882 return X86EMUL_CONTINUE;
2883}
2884
3b88e41a
JR		 2885static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2886{
2887 unsigned long dr7;
2888
717746e3 2889 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2890
2891 /* Check if DR7.Global_Enable is set */
2892 return dr7 & (1 << 13);
2893}
2894
2895static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2896{
9dac77fa 2897 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2898 u64 cr4;
2899
2900 if (dr > 7)
2901 return emulate_ud(ctxt);
2902
717746e3 2903 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2904 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2905 return emulate_ud(ctxt);
2906
2907 if (check_dr7_gd(ctxt))
2908 return emulate_db(ctxt);
2909
2910 return X86EMUL_CONTINUE;
2911}
2912
2913static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2914{
9dac77fa
AK		 2915 u64 new_val = ctxt->src.val64;
2916 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2917
2918 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2919 return emulate_gp(ctxt, 0);
2920
2921 return check_dr_read(ctxt);
2922}
2923
01de8b09
JR		 2924static int check_svme(struct x86_emulate_ctxt *ctxt)
2925{
2926 u64 efer;
2927
717746e3 2928 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2929
2930 if (!(efer & EFER_SVME))
2931 return emulate_ud(ctxt);
2932
2933 return X86EMUL_CONTINUE;
2934}
2935
2936static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2937{
9dac77fa 2938 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2939
2940 /* Valid physical address? */
d4224449 2941 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2942 return emulate_gp(ctxt, 0);
2943
2944 return check_svme(ctxt);
2945}
2946
d7eb8203
JR		 2947static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2948{
717746e3 2949 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2950
717746e3 2951 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2952 return emulate_ud(ctxt);
2953
2954 return X86EMUL_CONTINUE;
2955}
2956
8061252e
JR		 2957static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2958{
717746e3 2959 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2960 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2961
717746e3 2962 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2963 (rcx > 3))
2964 return emulate_gp(ctxt, 0);
2965
2966 return X86EMUL_CONTINUE;
2967}
2968
f6511935
JR		 2969static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2970{
9dac77fa
AK		 2971 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2972 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2973 return emulate_gp(ctxt, 0);
2974
2975 return X86EMUL_CONTINUE;
2976}
2977
2978static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2979{
9dac77fa
AK		 2980 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2981 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2982 return emulate_gp(ctxt, 0);
2983
2984 return X86EMUL_CONTINUE;
2985}
2986
73fba5f4 2987#define D(_y) { .flags = (_y) }
c4f035c6 2988#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2989#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2990 .check_perm = (_p) }
73fba5f4 2991#define N D(0)
01de8b09 2992#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2993#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2994#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2995#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2996#define II(_f, _e, _i) \
2997 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2998#define IIP(_f, _e, _i, _p) \
2999 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3000 .check_perm = (_p) }
aa97bb48 3001#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3002
8d8f4e9f 3003#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3004#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 3005#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3006
d67fc27a
TY		 3007#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3008 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3009 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3010
d7eb8203
JR		 3011static struct opcode group7_rm1[] = {
3012 DI(SrcNone | ModRM | Priv, monitor),
3013 DI(SrcNone | ModRM | Priv, mwait),
3014 N, N, N, N, N, N,
3015};
3016
01de8b09
JR		 3017static struct opcode group7_rm3[] = {
3018 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3019 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3020 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3021 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3022 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3023 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3024 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3025 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3026};
6230f7fc 3027
d7eb8203
JR		 3028static struct opcode group7_rm7[] = {
3029 N,
3030 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3031 N, N, N, N, N, N,
3032};
d67fc27a 3033
73fba5f4 3034static struct opcode group1[] = {
d67fc27a
TY		 3035 I(Lock, em_add),
3036 I(Lock, em_or),
3037 I(Lock, em_adc),
3038 I(Lock, em_sbb),
3039 I(Lock, em_and),
3040 I(Lock, em_sub),
3041 I(Lock, em_xor),
3042 I(0, em_cmp),
73fba5f4
AK		 3043};
3044
3045static struct opcode group1A[] = {
3046 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3047};
3048
3049static struct opcode group3[] = {
3329ece1
AK		 3050 I(DstMem | SrcImm | ModRM, em_test),
3051 I(DstMem | SrcImm | ModRM, em_test),
3052 I(DstMem | SrcNone | ModRM | Lock, em_not),
3053 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3054 I(SrcMem | ModRM, em_mul_ex),
3055 I(SrcMem | ModRM, em_imul_ex),
3056 I(SrcMem | ModRM, em_div_ex),
3057 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3058};
3059
3060static struct opcode group4[] = {
3061 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3062 N, N, N, N, N, N,
3063};
3064
3065static struct opcode group5[] = {
3066 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3067 D(SrcMem | ModRM | Stack),
3068 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3069 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3070 D(SrcMem | ModRM | Stack), N,
3071};
3072
dee6bb70
JR		 3073static struct opcode group6[] = {
3074 DI(ModRM | Prot, sldt),
3075 DI(ModRM | Prot, str),
3076 DI(ModRM | Prot | Priv, lldt),
3077 DI(ModRM | Prot | Priv, ltr),
3078 N, N, N, N,
3079};
3080
73fba5f4 3081static struct group_dual group7 = { {
dee6bb70
JR		 3082 DI(ModRM | Mov | DstMem | Priv, sgdt),
3083 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3084 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3085 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3086 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3087 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3088 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3089}, {
5ef39c71
AK		 3090 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3091 EXT(0, group7_rm1),
01de8b09 3092 N, EXT(0, group7_rm3),
5ef39c71
AK		 3093 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3094 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3095} };
3096
3097static struct opcode group8[] = {
3098 N, N, N, N,
3099 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3100 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3101};
3102
3103static struct group_dual group9 = { {
3104 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3105}, {
3106 N, N, N, N, N, N, N, N,
3107} };
3108
a4d4a7c1
AK		 3109static struct opcode group11[] = {
3110 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3111};
3112
aa97bb48
AK		 3113static struct gprefix pfx_0f_6f_0f_7f = {
3114 N, N, N, I(Sse, em_movdqu),
3115};
3116
73fba5f4
AK		 3117static struct opcode opcode_table[256] = {
3118 /* 0x00 - 0x07 */
d67fc27a 3119 I6ALU(Lock, em_add),
1cd196ea
AK		 3120 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3121 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3122 /* 0x08 - 0x0F */
d67fc27a 3123 I6ALU(Lock, em_or),
1cd196ea
AK		 3124 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3125 N,
73fba5f4 3126 /* 0x10 - 0x17 */
d67fc27a 3127 I6ALU(Lock, em_adc),
1cd196ea
AK		 3128 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3129 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3130 /* 0x18 - 0x1F */
d67fc27a 3131 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3132 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3133 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3134 /* 0x20 - 0x27 */
d67fc27a 3135 I6ALU(Lock, em_and), N, N,
73fba5f4 3136 /* 0x28 - 0x2F */
d67fc27a 3137 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3138 /* 0x30 - 0x37 */
d67fc27a 3139 I6ALU(Lock, em_xor), N, N,
73fba5f4 3140 /* 0x38 - 0x3F */
d67fc27a 3141 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3142 /* 0x40 - 0x4F */
3143 X16(D(DstReg)),
3144 /* 0x50 - 0x57 */
63540382 3145 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3146 /* 0x58 - 0x5F */
c54fe504 3147 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3148 /* 0x60 - 0x67 */
b96a7fad
TY		 3149 I(ImplicitOps | Stack | No64, em_pusha),
3150 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3151 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3152 N, N, N, N,
3153 /* 0x68 - 0x6F */
d46164db
AK		 3154 I(SrcImm | Mov | Stack, em_push),
3155 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3156 I(SrcImmByte | Mov | Stack, em_push),
3157 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3158 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3159 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3160 /* 0x70 - 0x7F */
3161 X16(D(SrcImmByte)),
3162 /* 0x80 - 0x87 */
3163 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3164 G(DstMem | SrcImm | ModRM | Group, group1),
3165 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3166 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3167 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3168 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3169 /* 0x88 - 0x8F */
b9eac5f4
AK		 3170 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3171 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3172 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3173 D(ModRM | SrcMem | NoAccess | DstReg),
3174 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3175 G(0, group1A),
73fba5f4 3176 /* 0x90 - 0x97 */
bf608f88 3177 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3178 /* 0x98 - 0x9F */
61429142 3179 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3180 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3181 II(ImplicitOps | Stack, em_pushf, pushf),
3182 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3183 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3184 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3185 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3186 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3187 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3188 /* 0xA8 - 0xAF */
9f21ca59 3189 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3190 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3191 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3192 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3193 /* 0xB0 - 0xB7 */
b9eac5f4 3194 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3195 /* 0xB8 - 0xBF */
b9eac5f4 3196 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3197 /* 0xC0 - 0xC7 */
d2c6c7ad 3198 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3199 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3200 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3201 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3202 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3203 G(ByteOp, group11), G(0, group11),
73fba5f4 3204 /* 0xC8 - 0xCF */
db5b0762 3205 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3206 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3207 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3208 /* 0xD0 - 0xD7 */
d2c6c7ad 3209 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3210 N, N, N, N,
3211 /* 0xD8 - 0xDF */
3212 N, N, N, N, N, N, N, N,
3213 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3214 X3(I(SrcImmByte, em_loop)),
3215 I(SrcImmByte, em_jcxz),
f6511935
JR		 3216 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3217 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3218 /* 0xE8 - 0xEF */
3219 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3220 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3221 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3222 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3223 /* 0xF0 - 0xF7 */
bf608f88 3224 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3225 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3226 G(ByteOp, group3), G(0, group3),
73fba5f4 3227 /* 0xF8 - 0xFF */
f411e6cd
TY		 3228 D(ImplicitOps), D(ImplicitOps),
3229 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3230 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3231};
3232
3233static struct opcode twobyte_table[256] = {
3234 /* 0x00 - 0x0F */
dee6bb70 3235 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3236 N, I(ImplicitOps | VendorSpecific, em_syscall),
3237 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3238 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3239 N, D(ImplicitOps | ModRM), N, N,
3240 /* 0x10 - 0x1F */
3241 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3242 /* 0x20 - 0x2F */
cfec82cb 3243 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3244 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3245 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3246 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3247 N, N, N, N,
3248 N, N, N, N, N, N, N, N,
3249 /* 0x30 - 0x3F */
8061252e
JR		 3250 DI(ImplicitOps | Priv, wrmsr),
3251 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3252 DI(ImplicitOps | Priv, rdmsr),
3253 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3254 I(ImplicitOps | VendorSpecific, em_sysenter),
3255 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3256 N, N,
73fba5f4
AK		 3257 N, N, N, N, N, N, N, N,
3258 /* 0x40 - 0x4F */
3259 X16(D(DstReg | SrcMem | ModRM | Mov)),
3260 /* 0x50 - 0x5F */
3261 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3262 /* 0x60 - 0x6F */
aa97bb48
AK		 3263 N, N, N, N,
3264 N, N, N, N,
3265 N, N, N, N,
3266 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3267 /* 0x70 - 0x7F */
aa97bb48
AK		 3268 N, N, N, N,
3269 N, N, N, N,
3270 N, N, N, N,
3271 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3272 /* 0x80 - 0x8F */
3273 X16(D(SrcImm)),
3274 /* 0x90 - 0x9F */
ee45b58e 3275 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3276 /* 0xA0 - 0xA7 */
1cd196ea 3277 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
8061252e 3278 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3279 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3280 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3281 /* 0xA8 - 0xAF */
1cd196ea 3282 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
8061252e 3283 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3284 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3285 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3286 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3287 /* 0xB0 - 0xB7 */
739ae406 3288 D2bv(DstMem | SrcReg | ModRM | Lock),
d4b4325f 3289 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
c191a7a0 3290 D(DstMem | SrcReg | ModRM | BitOp | Lock),
d4b4325f
AK		 3291 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3292 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
09b5f4d3 3293 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3294 /* 0xB8 - 0xBF */
3295 N, N,
ba7ff2b7 3296 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3297 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3298 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3299 /* 0xC0 - 0xCF */
739ae406 3300 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3301 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3302 N, N, N, GD(0, &group9),
3303 N, N, N, N, N, N, N, N,
3304 /* 0xD0 - 0xDF */
3305 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3306 /* 0xE0 - 0xEF */
3307 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3308 /* 0xF0 - 0xFF */
3309 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3310};
3311
3312#undef D
3313#undef N
3314#undef G
3315#undef GD
3316#undef I
aa97bb48 3317#undef GP
01de8b09 3318#undef EXT
73fba5f4 3319
8d8f4e9f 3320#undef D2bv
f6511935 3321#undef D2bvIP
8d8f4e9f 3322#undef I2bv
d67fc27a 3323#undef I6ALU
8d8f4e9f 3324
9dac77fa 3325static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3326{
3327 unsigned size;
3328
9dac77fa 3329 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3330 if (size == 8)
3331 size = 4;
3332 return size;
3333}
3334
3335static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3336 unsigned size, bool sign_extension)
3337{
39f21ee5
AK		 3338 int rc = X86EMUL_CONTINUE;
3339
3340 op->type = OP_IMM;
3341 op->bytes = size;
9dac77fa 3342 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3343 /* NB. Immediates are sign-extended as necessary. */
3344 switch (op->bytes) {
3345 case 1:
e85a1085 3346 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3347 break;
3348 case 2:
e85a1085 3349 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3350 break;
3351 case 4:
e85a1085 3352 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3353 break;
3354 }
3355 if (!sign_extension) {
3356 switch (op->bytes) {
3357 case 1:
3358 op->val &= 0xff;
3359 break;
3360 case 2:
3361 op->val &= 0xffff;
3362 break;
3363 case 4:
3364 op->val &= 0xffffffff;
3365 break;
3366 }
3367 }
3368done:
3369 return rc;
3370}
3371
a9945549
AK		 3372static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3373 unsigned d)
3374{
3375 int rc = X86EMUL_CONTINUE;
3376
3377 switch (d) {
3378 case OpReg:
3379 decode_register_operand(ctxt, op,
5217973e 3380 op == &ctxt->dst &&
a9945549
AK		 3381 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3382 break;
3383 case OpImmUByte:
608aabe3 3384 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3385 break;
3386 case OpMem:
41ddf978 3387 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3388 mem_common:
3389 *op = ctxt->memop;
3390 ctxt->memopp = op;
3391 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3392 fetch_bit_operand(ctxt);
3393 op->orig_val = op->val;
3394 break;
41ddf978
AK		 3395 case OpMem64:
3396 ctxt->memop.bytes = 8;
3397 goto mem_common;
a9945549
AK		 3398 case OpAcc:
3399 op->type = OP_REG;
3400 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3401 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3402 fetch_register_operand(op);
3403 op->orig_val = op->val;
3404 break;
3405 case OpDI:
3406 op->type = OP_MEM;
3407 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3408 op->addr.mem.ea =
3409 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3410 op->addr.mem.seg = VCPU_SREG_ES;
3411 op->val = 0;
3412 break;
3413 case OpDX:
3414 op->type = OP_REG;
3415 op->bytes = 2;
3416 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3417 fetch_register_operand(op);
3418 break;
4dd6a57d
AK		 3419 case OpCL:
3420 op->bytes = 1;
3421 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3422 break;
3423 case OpImmByte:
3424 rc = decode_imm(ctxt, op, 1, true);
3425 break;
3426 case OpOne:
3427 op->bytes = 1;
3428 op->val = 1;
3429 break;
3430 case OpImm:
3431 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3432 break;
0fe59128
AK		 3433 case OpMem16:
3434 ctxt->memop.bytes = 2;
3435 goto mem_common;
3436 case OpMem32:
3437 ctxt->memop.bytes = 4;
3438 goto mem_common;
3439 case OpImmU16:
3440 rc = decode_imm(ctxt, op, 2, false);
3441 break;
3442 case OpImmU:
3443 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3444 break;
3445 case OpSI:
3446 op->type = OP_MEM;
3447 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3448 op->addr.mem.ea =
3449 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3450 op->addr.mem.seg = seg_override(ctxt);
3451 op->val = 0;
3452 break;
3453 case OpImmFAddr:
3454 op->type = OP_IMM;
3455 op->addr.mem.ea = ctxt->_eip;
3456 op->bytes = ctxt->op_bytes + 2;
3457 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3458 break;
3459 case OpMemFAddr:
3460 ctxt->memop.bytes = ctxt->op_bytes + 2;
3461 goto mem_common;
c191a7a0
AK		 3462 case OpES:
3463 op->val = VCPU_SREG_ES;
3464 break;
3465 case OpCS:
3466 op->val = VCPU_SREG_CS;
3467 break;
3468 case OpSS:
3469 op->val = VCPU_SREG_SS;
3470 break;
3471 case OpDS:
3472 op->val = VCPU_SREG_DS;
3473 break;
3474 case OpFS:
3475 op->val = VCPU_SREG_FS;
3476 break;
3477 case OpGS:
3478 op->val = VCPU_SREG_GS;
3479 break;
a9945549
AK		 3480 case OpImplicit:
3481 /* Special instructions do their own operand decoding. */
3482 default:
3483 op->type = OP_NONE; /* Disable writeback. */
3484 break;
3485 }
3486
3487done:
3488 return rc;
3489}
3490
ef5d75cc 3491int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3492{
dde7e6d1
AK		 3493 int rc = X86EMUL_CONTINUE;
3494 int mode = ctxt->mode;
46561646 3495 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3496 bool op_prefix = false;
46561646 3497 struct opcode opcode;
dde7e6d1 3498
f09ed83e
AK		 3499 ctxt->memop.type = OP_NONE;
3500 ctxt->memopp = NULL;
9dac77fa
AK		 3501 ctxt->_eip = ctxt->eip;
3502 ctxt->fetch.start = ctxt->_eip;
3503 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3504 if (insn_len > 0)
9dac77fa 3505 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3506
3507 switch (mode) {
3508 case X86EMUL_MODE_REAL:
3509 case X86EMUL_MODE_VM86:
3510 case X86EMUL_MODE_PROT16:
3511 def_op_bytes = def_ad_bytes = 2;
3512 break;
3513 case X86EMUL_MODE_PROT32:
3514 def_op_bytes = def_ad_bytes = 4;
3515 break;
3516#ifdef CONFIG_X86_64
3517 case X86EMUL_MODE_PROT64:
3518 def_op_bytes = 4;
3519 def_ad_bytes = 8;
3520 break;
3521#endif
3522 default:
1d2887e2 3523 return EMULATION_FAILED;
dde7e6d1
AK		 3524 }
3525
9dac77fa
AK		 3526 ctxt->op_bytes = def_op_bytes;
3527 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3528
3529 /* Legacy prefixes. */
3530 for (;;) {
e85a1085 3531 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3532 case 0x66: /* operand-size override */
0d7cdee8 3533 op_prefix = true;
dde7e6d1 3534 /* switch between 2/4 bytes */
9dac77fa 3535 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3536 break;
3537 case 0x67: /* address-size override */
3538 if (mode == X86EMUL_MODE_PROT64)
3539 /* switch between 4/8 bytes */
9dac77fa 3540 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3541 else
3542 /* switch between 2/4 bytes */
9dac77fa 3543 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3544 break;
3545 case 0x26: /* ES override */
3546 case 0x2e: /* CS override */
3547 case 0x36: /* SS override */
3548 case 0x3e: /* DS override */
9dac77fa 3549 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3550 break;
3551 case 0x64: /* FS override */
3552 case 0x65: /* GS override */
9dac77fa 3553 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3554 break;
3555 case 0x40 ... 0x4f: /* REX */
3556 if (mode != X86EMUL_MODE_PROT64)
3557 goto done_prefixes;
9dac77fa 3558 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3559 continue;
3560 case 0xf0: /* LOCK */
9dac77fa 3561 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3562 break;
3563 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3564 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3565 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3566 break;
3567 default:
3568 goto done_prefixes;
3569 }
3570
3571 /* Any legacy prefix after a REX prefix nullifies its effect. */
3572
9dac77fa 3573 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3574 }
3575
3576done_prefixes:
3577
3578 /* REX prefix. */
9dac77fa
AK		 3579 if (ctxt->rex_prefix & 8)
3580 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3581
3582 /* Opcode byte(s). */
9dac77fa 3583 opcode = opcode_table[ctxt->b];
d3ad6243 3584 /* Two-byte opcode? */
9dac77fa
AK		 3585 if (ctxt->b == 0x0f) {
3586 ctxt->twobyte = 1;
e85a1085 3587 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3588 opcode = twobyte_table[ctxt->b];
dde7e6d1 3589 }
9dac77fa 3590 ctxt->d = opcode.flags;
dde7e6d1 3591
9dac77fa
AK		 3592 while (ctxt->d & GroupMask) {
3593 switch (ctxt->d & GroupMask) {
46561646 3594 case Group:
e85a1085 3595 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3596 --ctxt->_eip;
3597 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3598 opcode = opcode.u.group[goffset];
3599 break;
3600 case GroupDual:
e85a1085 3601 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3602 --ctxt->_eip;
3603 goffset = (ctxt->modrm >> 3) & 7;
3604 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3605 opcode = opcode.u.gdual->mod3[goffset];
3606 else
3607 opcode = opcode.u.gdual->mod012[goffset];
3608 break;
3609 case RMExt:
9dac77fa 3610 goffset = ctxt->modrm & 7;
01de8b09 3611 opcode = opcode.u.group[goffset];
46561646
AK		 3612 break;
3613 case Prefix:
9dac77fa 3614 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3615 return EMULATION_FAILED;
9dac77fa 3616 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3617 switch (simd_prefix) {
3618 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3619 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3620 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3621 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3622 }
3623 break;
3624 default:
1d2887e2 3625 return EMULATION_FAILED;
0d7cdee8 3626 }
46561646 3627
b1ea50b2 3628 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3629 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3630 }
3631
9dac77fa
AK		 3632 ctxt->execute = opcode.u.execute;
3633 ctxt->check_perm = opcode.check_perm;
3634 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3635
3636 /* Unrecognised? */
9dac77fa 3637 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3638 return EMULATION_FAILED;
dde7e6d1 3639
9dac77fa 3640 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3641 return EMULATION_FAILED;
d867162c 3642
9dac77fa
AK		 3643 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3644 ctxt->op_bytes = 8;
dde7e6d1 3645
9dac77fa 3646 if (ctxt->d & Op3264) {
7f9b4b75 3647 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3648 ctxt->op_bytes = 8;
7f9b4b75 3649 else
9dac77fa 3650 ctxt->op_bytes = 4;
7f9b4b75
AK		 3651 }
3652
9dac77fa
AK		 3653 if (ctxt->d & Sse)
3654 ctxt->op_bytes = 16;
1253791d 3655
dde7e6d1 3656 /* ModRM and SIB bytes. */
9dac77fa 3657 if (ctxt->d & ModRM) {
f09ed83e 3658 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3659 if (!ctxt->has_seg_override)
3660 set_seg_override(ctxt, ctxt->modrm_seg);
3661 } else if (ctxt->d & MemAbs)
f09ed83e 3662 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3663 if (rc != X86EMUL_CONTINUE)
3664 goto done;
3665
9dac77fa
AK		 3666 if (!ctxt->has_seg_override)
3667 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3668
f09ed83e 3669 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3670
f09ed83e
AK		 3671 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3672 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3673
dde7e6d1
AK		 3674 /*
3675 * Decode and fetch the source operand: register, memory
3676 * or immediate.
3677 */
0fe59128 3678 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 3679 if (rc != X86EMUL_CONTINUE)
3680 goto done;
3681
dde7e6d1
AK		 3682 /*
3683 * Decode and fetch the second source operand: register, memory
3684 * or immediate.
3685 */
4dd6a57d 3686 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3687 if (rc != X86EMUL_CONTINUE)
3688 goto done;
3689
dde7e6d1 3690 /* Decode and fetch the destination operand: register or memory. */
a9945549 3691 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3692
3693done:
f09ed83e
AK		 3694 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3695 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3696
1d2887e2 3697 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3698}
3699
3e2f65d5
GN		 3700static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3701{
3e2f65d5
GN		 3702 /* The second termination condition only applies for REPE
3703 * and REPNE. Test if the repeat string operation prefix is
3704 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3705 * corresponding termination condition according to:
3706 * - if REPE/REPZ and ZF = 0 then done
3707 * - if REPNE/REPNZ and ZF = 1 then done
3708 */
9dac77fa
AK		 3709 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3710 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3711 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3712 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3713 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3714 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3715 return true;
3716
3717 return false;
3718}
3719
7b105ca2 3720int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3721{
9aabc88f 3722 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3723 u64 msr_data;
1b30eaa8 3724 int rc = X86EMUL_CONTINUE;
9dac77fa 3725 int saved_dst_type = ctxt->dst.type;
8b4caf66 3726
9dac77fa 3727 ctxt->mem_read.pos = 0;
310b5d30 3728
9dac77fa 3729 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3730 rc = emulate_ud(ctxt);
1161624f
GN		 3731 goto done;
3732 }
3733
d380a5e4 3734 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3735 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3736 rc = emulate_ud(ctxt);
d380a5e4
GN		 3737 goto done;
3738 }
3739
9dac77fa 3740 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3741 rc = emulate_ud(ctxt);
081bca0e
AK		 3742 goto done;
3743 }
3744
9dac77fa 3745 if ((ctxt->d & Sse)
717746e3
AK		 3746 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3747 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3748 rc = emulate_ud(ctxt);
3749 goto done;
3750 }
3751
9dac77fa 3752 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3753 rc = emulate_nm(ctxt);
3754 goto done;
3755 }
3756
9dac77fa
AK		 3757 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3758 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3759 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3760 if (rc != X86EMUL_CONTINUE)
3761 goto done;
3762 }
3763
e92805ac 3764 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3765 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3766 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3767 goto done;
3768 }
3769
8ea7d6ae 3770 /* Instruction can only be executed in protected mode */
9dac77fa 3771 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3772 rc = emulate_ud(ctxt);
3773 goto done;
3774 }
3775
d09beabd 3776 /* Do instruction specific permission checks */
9dac77fa
AK		 3777 if (ctxt->check_perm) {
3778 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3779 if (rc != X86EMUL_CONTINUE)
3780 goto done;
3781 }
3782
9dac77fa
AK		 3783 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3784 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3785 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3786 if (rc != X86EMUL_CONTINUE)
3787 goto done;
3788 }
3789
9dac77fa 3790 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3791 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3792 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3793 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3794 goto done;
3795 }
b9fa9d6b
AK		 3796 }
3797
9dac77fa
AK		 3798 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3799 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3800 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3801 if (rc != X86EMUL_CONTINUE)
8b4caf66 3802 goto done;
9dac77fa 3803 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3804 }
3805
9dac77fa
AK		 3806 if (ctxt->src2.type == OP_MEM) {
3807 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3808 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3809 if (rc != X86EMUL_CONTINUE)
3810 goto done;
3811 }
3812
9dac77fa 3813 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3814 goto special_insn;
3815
3816
9dac77fa 3817 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3818 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3819 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3820 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3821 if (rc != X86EMUL_CONTINUE)
3822 goto done;
038e51de 3823 }
9dac77fa 3824 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3825
018a98db
AK		 3826special_insn:
3827
9dac77fa
AK		 3828 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3829 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3830 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3831 if (rc != X86EMUL_CONTINUE)
3832 goto done;
3833 }
3834
9dac77fa
AK		 3835 if (ctxt->execute) {
3836 rc = ctxt->execute(ctxt);
ef65c889
AK		 3837 if (rc != X86EMUL_CONTINUE)
3838 goto done;
3839 goto writeback;
3840 }
3841
9dac77fa 3842 if (ctxt->twobyte)
6aa8b732
AK		 3843 goto twobyte_insn;
3844
9dac77fa 3845 switch (ctxt->b) {
33615aa9 3846 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3847 emulate_1op(ctxt, "inc");
33615aa9
AK		 3848 break;
3849 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3850 emulate_1op(ctxt, "dec");
33615aa9 3851 break;
6aa8b732 3852 case 0x63: /* movsxd */
8b4caf66 3853 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3854 goto cannot_emulate;
9dac77fa 3855 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3856 break;
018a98db
AK		 3857 case 0x6c: /* insb */
3858 case 0x6d: /* insw/insd */
9dac77fa 3859 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3860 goto do_io_in;
018a98db
AK		 3861 case 0x6e: /* outsb */
3862 case 0x6f: /* outsw/outsd */
9dac77fa 3863 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3864 goto do_io_out;
7972995b 3865 break;
b2833e3c 3866 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3867 if (test_cc(ctxt->b, ctxt->eflags))
3868 jmp_rel(ctxt, ctxt->src.val);
018a98db 3869 break;
7e0b54b1 3870 case 0x8d: /* lea r16/r32, m */
9dac77fa 3871 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3872 break;
6aa8b732 3873 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3874 rc = em_grp1a(ctxt);
6aa8b732 3875 break;
3d9e77df 3876 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3877 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3878 break;
e4f973ae
TY		 3879 rc = em_xchg(ctxt);
3880 break;
e8b6fa70 3881 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3882 switch (ctxt->op_bytes) {
3883 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3884 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3885 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3886 }
3887 break;
018a98db 3888 case 0xc0 ... 0xc1:
51187683 3889 rc = em_grp2(ctxt);
018a98db 3890 break;
6e154e56 3891 case 0xcc: /* int3 */
5c5df76b
TY		 3892 rc = emulate_int(ctxt, 3);
3893 break;
6e154e56 3894 case 0xcd: /* int n */
9dac77fa 3895 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3896 break;
3897 case 0xce: /* into */
5c5df76b
TY		 3898 if (ctxt->eflags & EFLG_OF)
3899 rc = emulate_int(ctxt, 4);
6e154e56 3900 break;
018a98db 3901 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3902 rc = em_grp2(ctxt);
018a98db
AK		 3903 break;
3904 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3905 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3906 rc = em_grp2(ctxt);
018a98db 3907 break;
a6a3034c
MG		 3908 case 0xe4: /* inb */
3909 case 0xe5: /* in */
cf8f70bf 3910 goto do_io_in;
a6a3034c
MG		 3911 case 0xe6: /* outb */
3912 case 0xe7: /* out */
cf8f70bf 3913 goto do_io_out;
1a52e051 3914 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3915 long int rel = ctxt->src.val;
3916 ctxt->src.val = (unsigned long) ctxt->_eip;
3917 jmp_rel(ctxt, rel);
4487b3b4 3918 rc = em_push(ctxt);
8cdbd2c9 3919 break;
1a52e051
NK		 3920 }
3921 case 0xe9: /* jmp rel */
db5b0762 3922 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3923 jmp_rel(ctxt, ctxt->src.val);
3924 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3925 break;
a6a3034c
MG		 3926 case 0xec: /* in al,dx */
3927 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3928 do_io_in:
9dac77fa
AK		 3929 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3930 &ctxt->dst.val))
cf8f70bf
GN		 3931 goto done; /* IO is needed */
3932 break;
ce7a0ad3
WY		 3933 case 0xee: /* out dx,al */
3934 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3935 do_io_out:
9dac77fa
AK		 3936 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3937 &ctxt->src.val, 1);
3938 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3939 break;
111de5d6 3940 case 0xf4: /* hlt */
6c3287f7 3941 ctxt->ops->halt(ctxt);
19fdfa0d 3942 break;
111de5d6
AK		 3943 case 0xf5: /* cmc */
3944 /* complement carry flag from eflags reg */
3945 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 3946 break;
3947 case 0xf8: /* clc */
3948 ctxt->eflags &= ~EFLG_CF;
111de5d6 3949 break;
8744aa9a
MG		 3950 case 0xf9: /* stc */
3951 ctxt->eflags |= EFLG_CF;
3952 break;
fb4616f4
MG		 3953 case 0xfc: /* cld */
3954 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3955 break;
3956 case 0xfd: /* std */
3957 ctxt->eflags |= EFLG_DF;
fb4616f4 3958 break;
ea79849d 3959 case 0xfe: /* Grp4 */
51187683 3960 rc = em_grp45(ctxt);
018a98db 3961 break;
ea79849d 3962 case 0xff: /* Grp5 */
51187683
TY		 3963 rc = em_grp45(ctxt);
3964 break;
91269b8f
AK		 3965 default:
3966 goto cannot_emulate;
6aa8b732 3967 }
018a98db 3968
7d9ddaed
AK		 3969 if (rc != X86EMUL_CONTINUE)
3970 goto done;
3971
018a98db 3972writeback:
adddcecf 3973 rc = writeback(ctxt);
1b30eaa8 3974 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3975 goto done;
3976
5cd21917
GN		 3977 /*
3978 * restore dst type in case the decoding will be reused
3979 * (happens for string instruction )
3980 */
9dac77fa 3981 ctxt->dst.type = saved_dst_type;
5cd21917 3982
9dac77fa
AK		 3983 if ((ctxt->d & SrcMask) == SrcSI)
3984 string_addr_inc(ctxt, seg_override(ctxt),
3985 VCPU_REGS_RSI, &ctxt->src);
a682e354 3986
9dac77fa 3987 if ((ctxt->d & DstMask) == DstDI)
90de84f5 3988 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 3989 &ctxt->dst);
d9271123 3990
9dac77fa
AK		 3991 if (ctxt->rep_prefix && (ctxt->d & String)) {
3992 struct read_cache *r = &ctxt->io_read;
3993 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3994
d2ddd1c4
GN		 3995 if (!string_insn_completed(ctxt)) {
3996 /*
3997 * Re-enter guest when pio read ahead buffer is empty
3998 * or, if it is not used, after each 1024 iteration.
3999 */
9dac77fa 4000 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4001 (r->end == 0 || r->end != r->pos)) {
4002 /*
4003 * Reset read cache. Usually happens before
4004 * decode, but since instruction is restarted
4005 * we have to do it here.
4006 */
9dac77fa 4007 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4008 return EMULATION_RESTART;
4009 }
4010 goto done; /* skip rip writeback */
0fa6ccbd 4011 }
5cd21917 4012 }
d2ddd1c4 4013
9dac77fa 4014 ctxt->eip = ctxt->_eip;
018a98db
AK		 4015
4016done:
da9cb575
AK		 4017 if (rc == X86EMUL_PROPAGATE_FAULT)
4018 ctxt->have_exception = true;
775fde86
JR		 4019 if (rc == X86EMUL_INTERCEPTED)
4020 return EMULATION_INTERCEPTED;
4021
d2ddd1c4 4022 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4023
4024twobyte_insn:
9dac77fa 4025 switch (ctxt->b) {
018a98db 4026 case 0x09: /* wbinvd */
cfb22375 4027 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4028 break;
4029 case 0x08: /* invd */
018a98db
AK		 4030 case 0x0d: /* GrpP (prefetch) */
4031 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4032 break;
4033 case 0x20: /* mov cr, reg */
9dac77fa 4034 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4035 break;
6aa8b732 4036 case 0x21: /* mov from dr to reg */
9dac77fa 4037 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4038 break;
018a98db 4039 case 0x22: /* mov reg, cr */
9dac77fa 4040 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4041 emulate_gp(ctxt, 0);
da9cb575 4042 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4043 goto done;
4044 }
9dac77fa 4045 ctxt->dst.type = OP_NONE;
018a98db 4046 break;
6aa8b732 4047 case 0x23: /* mov from reg to dr */
9dac77fa 4048 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4049 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4050 ~0ULL : ~0U)) < 0) {
338dbc97 4051 /* #UD condition is already handled by the code above */
54b8486f 4052 emulate_gp(ctxt, 0);
da9cb575 4053 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4054 goto done;
4055 }
4056
9dac77fa 4057 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4058 break;
018a98db
AK		 4059 case 0x30:
4060 /* wrmsr */
9dac77fa
AK		 4061 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4062 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4063 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4064 emulate_gp(ctxt, 0);
da9cb575 4065 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4066 goto done;
018a98db
AK		 4067 }
4068 rc = X86EMUL_CONTINUE;
018a98db
AK		 4069 break;
4070 case 0x32:
4071 /* rdmsr */
9dac77fa 4072 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4073 emulate_gp(ctxt, 0);
da9cb575 4074 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4075 goto done;
018a98db 4076 } else {
9dac77fa
AK		 4077 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4078 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4079 }
4080 rc = X86EMUL_CONTINUE;
018a98db 4081 break;
6aa8b732 4082 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4083 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4084 if (!test_cc(ctxt->b, ctxt->eflags))
4085 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4086 break;
b2833e3c 4087 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4088 if (test_cc(ctxt->b, ctxt->eflags))
4089 jmp_rel(ctxt, ctxt->src.val);
018a98db 4090 break;
ee45b58e 4091 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4092 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4093 break;
7de75248
NK		 4094 case 0xa3:
4095 bt: /* bt */
9dac77fa 4096 ctxt->dst.type = OP_NONE;
e4e03ded 4097 /* only subword offset */
9dac77fa 4098 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4099 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4100 break;
9bf8ea42
GT		 4101 case 0xa4: /* shld imm8, r, r/m */
4102 case 0xa5: /* shld cl, r, r/m */
761441b9 4103 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4104 break;
7de75248
NK		 4105 case 0xab:
4106 bts: /* bts */
a31b9cea 4107 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4108 break;
9bf8ea42
GT		 4109 case 0xac: /* shrd imm8, r, r/m */
4110 case 0xad: /* shrd cl, r, r/m */
761441b9 4111 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4112 break;
2a7c5b8b
GC		 4113 case 0xae: /* clflush */
4114 break;
6aa8b732
AK		 4115 case 0xb0 ... 0xb1: /* cmpxchg */
4116 /*
4117 * Save real source value, then compare EAX against
4118 * destination.
4119 */
9dac77fa
AK		 4120 ctxt->src.orig_val = ctxt->src.val;
4121 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4122 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4123 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4124 /* Success: write back to memory. */
9dac77fa 4125 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4126 } else {
4127 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4128 ctxt->dst.type = OP_REG;
4129 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4130 }
4131 break;
6aa8b732
AK		 4132 case 0xb3:
4133 btr: /* btr */
a31b9cea 4134 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4135 break;
6aa8b732 4136 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4137 ctxt->dst.bytes = ctxt->op_bytes;
4138 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4139 : (u16) ctxt->src.val;
6aa8b732 4140 break;
6aa8b732 4141 case 0xba: /* Grp8 */
9dac77fa 4142 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4143 case 0:
4144 goto bt;
4145 case 1:
4146 goto bts;
4147 case 2:
4148 goto btr;
4149 case 3:
4150 goto btc;
4151 }
4152 break;
7de75248
NK		 4153 case 0xbb:
4154 btc: /* btc */
a31b9cea 4155 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4156 break;
d9574a25
WY		 4157 case 0xbc: { /* bsf */
4158 u8 zf;
4159 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4160 : "=r"(ctxt->dst.val), "=q"(zf)
4161 : "r"(ctxt->src.val));
d9574a25
WY		 4162 ctxt->eflags &= ~X86_EFLAGS_ZF;
4163 if (zf) {
4164 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4165 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4166 }
4167 break;
4168 }
4169 case 0xbd: { /* bsr */
4170 u8 zf;
4171 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4172 : "=r"(ctxt->dst.val), "=q"(zf)
4173 : "r"(ctxt->src.val));
d9574a25
WY		 4174 ctxt->eflags &= ~X86_EFLAGS_ZF;
4175 if (zf) {
4176 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4177 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4178 }
4179 break;
4180 }
6aa8b732 4181 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4182 ctxt->dst.bytes = ctxt->op_bytes;
4183 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4184 (s16) ctxt->src.val;
6aa8b732 4185 break;
92f738a5 4186 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4187 emulate_2op_SrcV(ctxt, "add");
92f738a5 4188 /* Write back the register source. */
9dac77fa
AK		 4189 ctxt->src.val = ctxt->dst.orig_val;
4190 write_register_operand(&ctxt->src);
92f738a5 4191 break;
a012e65a 4192 case 0xc3: /* movnti */
9dac77fa
AK		 4193 ctxt->dst.bytes = ctxt->op_bytes;
4194 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4195 (u64) ctxt->src.val;
a012e65a 4196 break;
6aa8b732 4197 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4198 rc = em_grp9(ctxt);
8cdbd2c9 4199 break;
91269b8f
AK		 4200 default:
4201 goto cannot_emulate;
6aa8b732 4202 }
7d9ddaed
AK		 4203
4204 if (rc != X86EMUL_CONTINUE)
4205 goto done;
4206
6aa8b732
AK		 4207 goto writeback;
4208
4209cannot_emulate:
a0c0ab2f 4210 return EMULATION_FAILED;
6aa8b732 4211}
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