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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
0fe59128
AK		 64
65#define OpBits 5 /* Width of operand field */
b1ea50b2 66#define OpMask ((1ull << OpBits) - 1)
a9945549 67
6aa8b732
AK		 68/*
69 * Opcode effective-address decode tables.
70 * Note that we only emulate instructions that have at least one memory
71 * operand (excluding implicit stack references). We assume that stack
72 * references and instruction fetches will never occur in special memory
73 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
74 * not be handled.
75 */
76
77/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 78#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 79/* Destination operand type. */
a9945549
AK		 80#define DstShift 1
81#define ImplicitOps (OpImplicit << DstShift)
82#define DstReg (OpReg << DstShift)
83#define DstMem (OpMem << DstShift)
84#define DstAcc (OpAcc << DstShift)
85#define DstDI (OpDI << DstShift)
86#define DstMem64 (OpMem64 << DstShift)
87#define DstImmUByte (OpImmUByte << DstShift)
88#define DstDX (OpDX << DstShift)
89#define DstMask (OpMask << DstShift)
6aa8b732 90/* Source operand type. */
0fe59128
AK		 91#define SrcShift 6
92#define SrcNone (OpNone << SrcShift)
93#define SrcReg (OpReg << SrcShift)
94#define SrcMem (OpMem << SrcShift)
95#define SrcMem16 (OpMem16 << SrcShift)
96#define SrcMem32 (OpMem32 << SrcShift)
97#define SrcImm (OpImm << SrcShift)
98#define SrcImmByte (OpImmByte << SrcShift)
99#define SrcOne (OpOne << SrcShift)
100#define SrcImmUByte (OpImmUByte << SrcShift)
101#define SrcImmU (OpImmU << SrcShift)
102#define SrcSI (OpSI << SrcShift)
7fa57952 103#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 104#define SrcImmFAddr (OpImmFAddr << SrcShift)
105#define SrcMemFAddr (OpMemFAddr << SrcShift)
106#define SrcAcc (OpAcc << SrcShift)
107#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 108#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 109#define SrcDX (OpDX << SrcShift)
28867cee 110#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 111#define SrcMask (OpMask << SrcShift)
221192bd
MT		 112#define BitOp (1<<11)
113#define MemAbs (1<<12) /* Memory operand is absolute displacement */
114#define String (1<<13) /* String instruction (rep capable) */
115#define Stack (1<<14) /* Stack instruction (push/pop) */
116#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
117#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
118#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
119#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
120#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 121#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 122#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 123/* Generic ModRM decode. */
124#define ModRM (1<<19)
125/* Destination is only written; never read. */
126#define Mov (1<<20)
d8769fed 127/* Misc flags */
8ea7d6ae 128#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 129#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 130#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 131#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 132#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 133#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 134#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 135#define No64 (1<<28)
d5ae7ce8 136#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 137#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 138/* Source 2 operand type */
0b789eee 139#define Src2Shift (31)
4dd6a57d
AK		 140#define Src2None (OpNone << Src2Shift)
141#define Src2CL (OpCL << Src2Shift)
142#define Src2ImmByte (OpImmByte << Src2Shift)
143#define Src2One (OpOne << Src2Shift)
144#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 145#define Src2ES (OpES << Src2Shift)
146#define Src2CS (OpCS << Src2Shift)
147#define Src2SS (OpSS << Src2Shift)
148#define Src2DS (OpDS << Src2Shift)
149#define Src2FS (OpFS << Src2Shift)
150#define Src2GS (OpGS << Src2Shift)
4dd6a57d 151#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 152#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 153#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
154#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
155#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 156#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 157#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 158
d0e53325
AK		 159#define X2(x...) x, x
160#define X3(x...) X2(x), x
161#define X4(x...) X2(x), X2(x)
162#define X5(x...) X4(x), x
163#define X6(x...) X4(x), X2(x)
164#define X7(x...) X4(x), X3(x)
165#define X8(x...) X4(x), X4(x)
166#define X16(x...) X8(x), X8(x)
83babbca 167
e28bbd44
AK		 168#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
169#define FASTOP_SIZE 8
170
171/*
172 * fastop functions have a special calling convention:
173 *
174 * dst: [rdx]:rax (in/out)
175 * src: rbx (in/out)
176 * src2: rcx (in)
177 * flags: rflags (in/out)
178 *
179 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
180 * different operand sizes can be reached by calculation, rather than a jump
181 * table (which would be bigger than the code).
182 *
183 * fastop functions are declared as taking a never-defined fastop parameter,
184 * so they can't be called from C directly.
185 */
186
187struct fastop;
188
d65b1dee 189struct opcode {
b1ea50b2
AK		 190 u64 flags : 56;
191 u64 intercept : 8;
120df890 192 union {
ef65c889 193 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 194 const struct opcode *group;
195 const struct group_dual *gdual;
196 const struct gprefix *gprefix;
045a282c 197 const struct escape *esc;
e28bbd44 198 void (*fastop)(struct fastop *fake);
120df890 199 } u;
d09beabd 200 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 201};
202
203struct group_dual {
204 struct opcode mod012[8];
205 struct opcode mod3[8];
d65b1dee
AK		 206};
207
0d7cdee8
AK		 208struct gprefix {
209 struct opcode pfx_no;
210 struct opcode pfx_66;
211 struct opcode pfx_f2;
212 struct opcode pfx_f3;
213};
214
045a282c
GN		 215struct escape {
216 struct opcode op[8];
217 struct opcode high[64];
218};
219
6aa8b732 220/* EFLAGS bit definitions. */
d4c6a154
GN		 221#define EFLG_ID (1<<21)
222#define EFLG_VIP (1<<20)
223#define EFLG_VIF (1<<19)
224#define EFLG_AC (1<<18)
b1d86143
AP		 225#define EFLG_VM (1<<17)
226#define EFLG_RF (1<<16)
d4c6a154
GN		 227#define EFLG_IOPL (3<<12)
228#define EFLG_NT (1<<14)
6aa8b732
AK		 229#define EFLG_OF (1<<11)
230#define EFLG_DF (1<<10)
b1d86143 231#define EFLG_IF (1<<9)
d4c6a154 232#define EFLG_TF (1<<8)
6aa8b732
AK		 233#define EFLG_SF (1<<7)
234#define EFLG_ZF (1<<6)
235#define EFLG_AF (1<<4)
236#define EFLG_PF (1<<2)
237#define EFLG_CF (1<<0)
238
62bd430e
MG		 239#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
240#define EFLG_RESERVED_ONE_MASK 2
241
dd856efa
AK		 242static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
243{
244 if (!(ctxt->regs_valid & (1 << nr))) {
245 ctxt->regs_valid |= 1 << nr;
246 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
247 }
248 return ctxt->_regs[nr];
249}
250
251static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
252{
253 ctxt->regs_valid |= 1 << nr;
254 ctxt->regs_dirty |= 1 << nr;
255 return &ctxt->_regs[nr];
256}
257
258static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
259{
260 reg_read(ctxt, nr);
261 return reg_write(ctxt, nr);
262}
263
264static void writeback_registers(struct x86_emulate_ctxt *ctxt)
265{
266 unsigned reg;
267
268 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
269 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
270}
271
272static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
273{
274 ctxt->regs_dirty = 0;
275 ctxt->regs_valid = 0;
276}
277
6aa8b732
AK		 278/*
279 * Instruction emulation:
280 * Most instructions are emulated directly via a fragment of inline assembly
281 * code. This allows us to save/restore EFLAGS and thus very easily pick up
282 * any modified flags.
283 */
284
05b3e0c2 285#if defined(CONFIG_X86_64)
6aa8b732
AK		 286#define _LO32 "k" /* force 32-bit operand */
287#define _STK "%%rsp" /* stack pointer */
288#elif defined(__i386__)
289#define _LO32 "" /* force 32-bit operand */
290#define _STK "%%esp" /* stack pointer */
291#endif
292
293/*
294 * These EFLAGS bits are restored from saved value during emulation, and
295 * any changes are written back to the saved value after emulation.
296 */
297#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
298
299/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 300#define _PRE_EFLAGS(_sav, _msk, _tmp) \
301 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
302 "movl %"_sav",%"_LO32 _tmp"; " \
303 "push %"_tmp"; " \
304 "push %"_tmp"; " \
305 "movl %"_msk",%"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "pushf; " \
308 "notl %"_LO32 _tmp"; " \
309 "andl %"_LO32 _tmp",("_STK"); " \
310 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
311 "pop %"_tmp"; " \
312 "orl %"_LO32 _tmp",("_STK"); " \
313 "popf; " \
314 "pop %"_sav"; "
6aa8b732
AK		 315
316/* After executing instruction: write-back necessary bits in EFLAGS. */
317#define _POST_EFLAGS(_sav, _msk, _tmp) \
318 /* _sav |= EFLAGS & _msk; */ \
319 "pushf; " \
320 "pop %"_tmp"; " \
321 "andl %"_msk",%"_LO32 _tmp"; " \
322 "orl %"_LO32 _tmp",%"_sav"; "
323
dda96d8f
AK		 324#ifdef CONFIG_X86_64
325#define ON64(x) x
326#else
327#define ON64(x)
328#endif
329
a31b9cea 330#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 331 do { \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "2") \
334 _op _suffix " %"_x"3,%1; " \
335 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 336 : "=m" ((ctxt)->eflags), \
337 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 338 "=&r" (_tmp) \
a31b9cea 339 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 340 } while (0)
6b7ad61f
AK		 341
342
6aa8b732 343/* Raw emulation: instruction has two explicit operands. */
a31b9cea 344#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 345 do { \
346 unsigned long _tmp; \
347 \
a31b9cea 348 switch ((ctxt)->dst.bytes) { \
6b7ad61f 349 case 2: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 351 break; \
352 case 4: \
a31b9cea 353 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 354 break; \
355 case 8: \
a31b9cea 356 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 357 break; \
358 } \
6aa8b732
AK		 359 } while (0)
360
a31b9cea 361#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 362 do { \
6b7ad61f 363 unsigned long _tmp; \
a31b9cea 364 switch ((ctxt)->dst.bytes) { \
6aa8b732 365 case 1: \
a31b9cea 366 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 367 break; \
368 default: \
a31b9cea 369 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 370 _wx, _wy, _lx, _ly, _qx, _qy); \
371 break; \
372 } \
373 } while (0)
374
375/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 376#define emulate_2op_SrcB(ctxt, _op) \
377 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 378
379/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 380#define emulate_2op_SrcV(ctxt, _op) \
381 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 382
383/* Source operand is word, long or quad sized. */
a31b9cea
AK		 384#define emulate_2op_SrcV_nobyte(ctxt, _op) \
385 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 386
d175226a 387/* Instruction has three operands and one operand is stored in ECX register */
29053a60 388#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 389 do { \
390 unsigned long _tmp; \
761441b9
AK		 391 _type _clv = (ctxt)->src2.val; \
392 _type _srcv = (ctxt)->src.val; \
393 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 394 \
395 __asm__ __volatile__ ( \
396 _PRE_EFLAGS("0", "5", "2") \
397 _op _suffix " %4,%1 \n" \
398 _POST_EFLAGS("0", "5", "2") \
761441b9 399 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 400 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
401 ); \
402 \
761441b9
AK		 403 (ctxt)->src2.val = (unsigned long) _clv; \
404 (ctxt)->src2.val = (unsigned long) _srcv; \
405 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 406 } while (0)
407
761441b9 408#define emulate_2op_cl(ctxt, _op) \
7295261c 409 do { \
761441b9 410 switch ((ctxt)->dst.bytes) { \
7295261c 411 case 2: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 413 break; \
414 case 4: \
29053a60 415 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 416 break; \
417 case 8: \
29053a60 418 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 419 break; \
420 } \
d175226a
GT		 421 } while (0)
422
d1eef45d 423#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 424 do { \
425 unsigned long _tmp; \
426 \
dda96d8f
AK		 427 __asm__ __volatile__ ( \
428 _PRE_EFLAGS("0", "3", "2") \
429 _op _suffix " %1; " \
430 _POST_EFLAGS("0", "3", "2") \
d1eef45d 431 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 432 "=&r" (_tmp) \
433 : "i" (EFLAGS_MASK)); \
434 } while (0)
435
436/* Instruction has only one explicit operand (no source operand). */
d1eef45d 437#define emulate_1op(ctxt, _op) \
dda96d8f 438 do { \
d1eef45d
AK		 439 switch ((ctxt)->dst.bytes) { \
440 case 1: __emulate_1op(ctxt, _op, "b"); break; \
441 case 2: __emulate_1op(ctxt, _op, "w"); break; \
442 case 4: __emulate_1op(ctxt, _op, "l"); break; \
443 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 444 } \
445 } while (0)
446
4d758349
AK		 447static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
448
b7d491e7
AK		 449#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
450#define FOP_RET "ret \n\t"
451
452#define FOP_START(op) \
453 extern void em_##op(struct fastop *fake); \
454 asm(".pushsection .text, \"ax\" \n\t" \
455 ".global em_" #op " \n\t" \
456 FOP_ALIGN \
457 "em_" #op ": \n\t"
458
459#define FOP_END \
460 ".popsection")
461
0bdea068
AK		 462#define FOPNOP() FOP_ALIGN FOP_RET
463
b7d491e7
AK		 464#define FOP1E(op, dst) \
465 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
466
467#define FASTOP1(op) \
468 FOP_START(op) \
469 FOP1E(op##b, al) \
470 FOP1E(op##w, ax) \
471 FOP1E(op##l, eax) \
472 ON64(FOP1E(op##q, rax)) \
473 FOP_END
474
f7857f35
AK		 475#define FOP2E(op, dst, src) \
476 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
477
478#define FASTOP2(op) \
479 FOP_START(op) \
480 FOP2E(op##b, al, bl) \
481 FOP2E(op##w, ax, bx) \
482 FOP2E(op##l, eax, ebx) \
483 ON64(FOP2E(op##q, rax, rbx)) \
484 FOP_END
485
11c363ba
AK		 486/* 2 operand, word only */
487#define FASTOP2W(op) \
488 FOP_START(op) \
489 FOPNOP() \
490 FOP2E(op##w, ax, bx) \
491 FOP2E(op##l, eax, ebx) \
492 ON64(FOP2E(op##q, rax, rbx)) \
493 FOP_END
494
007a3b54
AK		 495/* 2 operand, src is CL */
496#define FASTOP2CL(op) \
497 FOP_START(op) \
498 FOP2E(op##b, al, cl) \
499 FOP2E(op##w, ax, cl) \
500 FOP2E(op##l, eax, cl) \
501 ON64(FOP2E(op##q, rax, cl)) \
502 FOP_END
503
0bdea068
AK		 504#define FOP3E(op, dst, src, src2) \
505 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
506
507/* 3-operand, word-only, src2=cl */
508#define FASTOP3WCL(op) \
509 FOP_START(op) \
510 FOPNOP() \
511 FOP3E(op##w, ax, bx, cl) \
512 FOP3E(op##l, eax, ebx, cl) \
513 ON64(FOP3E(op##q, rax, rbx, cl)) \
514 FOP_END
515
9ae9feba
AK		 516/* Special case for SETcc - 1 instruction per cc */
517#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
518
519FOP_START(setcc)
520FOP_SETCC(seto)
521FOP_SETCC(setno)
522FOP_SETCC(setc)
523FOP_SETCC(setnc)
524FOP_SETCC(setz)
525FOP_SETCC(setnz)
526FOP_SETCC(setbe)
527FOP_SETCC(setnbe)
528FOP_SETCC(sets)
529FOP_SETCC(setns)
530FOP_SETCC(setp)
531FOP_SETCC(setnp)
532FOP_SETCC(setl)
533FOP_SETCC(setnl)
534FOP_SETCC(setle)
535FOP_SETCC(setnle)
536FOP_END;
537
326f578f
PB		 538FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
539FOP_END;
540
e8f2b1d6 541#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 542 do { \
543 unsigned long _tmp; \
dd856efa
AK		 544 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
545 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 546 \
547 __asm__ __volatile__ ( \
548 _PRE_EFLAGS("0", "5", "1") \
549 "1: \n\t" \
550 _op _suffix " %6; " \
551 "2: \n\t" \
552 _POST_EFLAGS("0", "5", "1") \
553 ".pushsection .fixup,\"ax\" \n\t" \
554 "3: movb $1, %4 \n\t" \
555 "jmp 2b \n\t" \
556 ".popsection \n\t" \
557 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 558 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
559 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 560 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 561 } while (0)
562
3f9f53b0 563/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 564#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 565 do { \
e8f2b1d6 566 switch((ctxt)->src.bytes) { \
7295261c 567 case 1: \
e8f2b1d6 568 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 569 break; \
570 case 2: \
e8f2b1d6 571 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 572 break; \
573 case 4: \
e8f2b1d6 574 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 575 break; \
576 case 8: ON64( \
e8f2b1d6 577 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 578 break; \
579 } \
580 } while (0)
581
8a76d7f2
JR		 582static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
583 enum x86_intercept intercept,
584 enum x86_intercept_stage stage)
585{
586 struct x86_instruction_info info = {
587 .intercept = intercept,
9dac77fa
AK		 588 .rep_prefix = ctxt->rep_prefix,
589 .modrm_mod = ctxt->modrm_mod,
590 .modrm_reg = ctxt->modrm_reg,
591 .modrm_rm = ctxt->modrm_rm,
592 .src_val = ctxt->src.val64,
593 .src_bytes = ctxt->src.bytes,
594 .dst_bytes = ctxt->dst.bytes,
595 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 596 .next_rip = ctxt->eip,
597 };
598
2953538e 599 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 600}
601
f47cfa31
AK		 602static void assign_masked(ulong *dest, ulong src, ulong mask)
603{
604 *dest = (*dest & ~mask) | (src & mask);
605}
606
9dac77fa 607static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 608{
9dac77fa 609 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 610}
611
f47cfa31
AK		 612static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
613{
614 u16 sel;
615 struct desc_struct ss;
616
617 if (ctxt->mode == X86EMUL_MODE_PROT64)
618 return ~0UL;
619 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
620 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
621}
622
612e89f0
AK		 623static int stack_size(struct x86_emulate_ctxt *ctxt)
624{
625 return (__fls(stack_mask(ctxt)) + 1) >> 3;
626}
627
6aa8b732 628/* Access/update address held in a register, based on addressing mode. */
e4706772 629static inline unsigned long
9dac77fa 630address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 631{
9dac77fa 632 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 633 return reg;
634 else
9dac77fa 635 return reg & ad_mask(ctxt);
e4706772
HH		 636}
637
638static inline unsigned long
9dac77fa 639register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 640{
9dac77fa 641 return address_mask(ctxt, reg);
e4706772
HH		 642}
643
5ad105e5
AK		 644static void masked_increment(ulong *reg, ulong mask, int inc)
645{
646 assign_masked(reg, *reg + inc, mask);
647}
648
7a957275 649static inline void
9dac77fa 650register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 651{
5ad105e5
AK		 652 ulong mask;
653
9dac77fa 654 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 655 mask = ~0UL;
7a957275 656 else
5ad105e5
AK		 657 mask = ad_mask(ctxt);
658 masked_increment(reg, mask, inc);
659}
660
661static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
662{
dd856efa 663 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 664}
6aa8b732 665
9dac77fa 666static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 667{
9dac77fa 668 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 669}
098c937b 670
56697687
AK		 671static u32 desc_limit_scaled(struct desc_struct *desc)
672{
673 u32 limit = get_desc_limit(desc);
674
675 return desc->g ? (limit << 12) | 0xfff : limit;
676}
677
9dac77fa 678static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 679{
9dac77fa
AK		 680 ctxt->has_seg_override = true;
681 ctxt->seg_override = seg;
7a5b56df
AK		 682}
683
7b105ca2 684static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 685{
686 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
687 return 0;
688
7b105ca2 689 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 690}
691
9dac77fa 692static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 693{
9dac77fa 694 if (!ctxt->has_seg_override)
7a5b56df
AK		 695 return 0;
696
9dac77fa 697 return ctxt->seg_override;
7a5b56df
AK		 698}
699
35d3d4a1
AK		 700static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
701 u32 error, bool valid)
54b8486f 702{
da9cb575
AK		 703 ctxt->exception.vector = vec;
704 ctxt->exception.error_code = error;
705 ctxt->exception.error_code_valid = valid;
35d3d4a1 706 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 707}
708
3b88e41a
JR		 709static int emulate_db(struct x86_emulate_ctxt *ctxt)
710{
711 return emulate_exception(ctxt, DB_VECTOR, 0, false);
712}
713
35d3d4a1 714static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 715{
35d3d4a1 716 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 717}
718
618ff15d
AK		 719static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
720{
721 return emulate_exception(ctxt, SS_VECTOR, err, true);
722}
723
35d3d4a1 724static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 725{
35d3d4a1 726 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 727}
728
35d3d4a1 729static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 730{
35d3d4a1 731 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 732}
733
34d1f490
AK		 734static int emulate_de(struct x86_emulate_ctxt *ctxt)
735{
35d3d4a1 736 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 737}
738
1253791d
AK		 739static int emulate_nm(struct x86_emulate_ctxt *ctxt)
740{
741 return emulate_exception(ctxt, NM_VECTOR, 0, false);
742}
743
1aa36616
AK		 744static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
745{
746 u16 selector;
747 struct desc_struct desc;
748
749 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
750 return selector;
751}
752
753static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
754 unsigned seg)
755{
756 u16 dummy;
757 u32 base3;
758 struct desc_struct desc;
759
760 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
761 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
762}
763
1c11b376
AK		 764/*
765 * x86 defines three classes of vector instructions: explicitly
766 * aligned, explicitly unaligned, and the rest, which change behaviour
767 * depending on whether they're AVX encoded or not.
768 *
769 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
770 * subject to the same check.
771 */
772static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
773{
774 if (likely(size < 16))
775 return false;
776
777 if (ctxt->d & Aligned)
778 return true;
779 else if (ctxt->d & Unaligned)
780 return false;
781 else if (ctxt->d & Avx)
782 return false;
783 else
784 return true;
785}
786
3d9b938e 787static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 788 struct segmented_address addr,
3d9b938e 789 unsigned size, bool write, bool fetch,
52fd8b44
AK		 790 ulong *linear)
791{
618ff15d
AK		 792 struct desc_struct desc;
793 bool usable;
52fd8b44 794 ulong la;
618ff15d 795 u32 lim;
1aa36616 796 u16 sel;
3a78a4f4 797 unsigned cpl;
52fd8b44 798
7b105ca2 799 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 800 switch (ctxt->mode) {
618ff15d
AK		 801 case X86EMUL_MODE_PROT64:
802 if (((signed long)la << 16) >> 16 != la)
803 return emulate_gp(ctxt, 0);
804 break;
805 default:
1aa36616
AK		 806 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
807 addr.seg);
618ff15d
AK		 808 if (!usable)
809 goto bad;
58b7825b
GN		 810 /* code segment in protected mode or read-only data segment */
811 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
812 || !(desc.type & 2)) && write)
618ff15d
AK		 813 goto bad;
814 /* unreadable code segment */
3d9b938e 815 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 816 goto bad;
817 lim = desc_limit_scaled(&desc);
818 if ((desc.type & 8) || !(desc.type & 4)) {
819 /* expand-up segment */
820 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
821 goto bad;
822 } else {
fc058680 823 /* expand-down segment */
618ff15d
AK		 824 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
825 goto bad;
826 lim = desc.d ? 0xffffffff : 0xffff;
827 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
828 goto bad;
829 }
717746e3 830 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 831 if (!(desc.type & 8)) {
832 /* data segment */
833 if (cpl > desc.dpl)
834 goto bad;
835 } else if ((desc.type & 8) && !(desc.type & 4)) {
836 /* nonconforming code segment */
837 if (cpl != desc.dpl)
838 goto bad;
839 } else if ((desc.type & 8) && (desc.type & 4)) {
840 /* conforming code segment */
841 if (cpl < desc.dpl)
842 goto bad;
843 }
844 break;
845 }
9dac77fa 846 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 847 la &= (u32)-1;
1c11b376
AK		 848 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
849 return emulate_gp(ctxt, 0);
52fd8b44
AK		 850 *linear = la;
851 return X86EMUL_CONTINUE;
618ff15d
AK		 852bad:
853 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 854 return emulate_ss(ctxt, sel);
618ff15d 855 else
0afbe2f8 856 return emulate_gp(ctxt, sel);
52fd8b44
AK		 857}
858
3d9b938e
NE		 859static int linearize(struct x86_emulate_ctxt *ctxt,
860 struct segmented_address addr,
861 unsigned size, bool write,
862 ulong *linear)
863{
864 return __linearize(ctxt, addr, size, write, false, linear);
865}
866
867
3ca3ac4d
AK		 868static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
869 struct segmented_address addr,
870 void *data,
871 unsigned size)
872{
9fa088f4
AK		 873 int rc;
874 ulong linear;
875
83b8795a 876 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 877 if (rc != X86EMUL_CONTINUE)
878 return rc;
0f65dd70 879 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 880}
881
807941b1
TY		 882/*
883 * Fetch the next byte of the instruction being emulated which is pointed to
884 * by ctxt->_eip, then increment ctxt->_eip.
885 *
886 * Also prefetch the remaining bytes of the instruction without crossing page
887 * boundary if they are not in fetch_cache yet.
888 */
889static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 890{
9dac77fa 891 struct fetch_cache *fc = &ctxt->fetch;
62266869 892 int rc;
2fb53ad8 893 int size, cur_size;
62266869 894
807941b1 895 if (ctxt->_eip == fc->end) {
3d9b938e 896 unsigned long linear;
807941b1
TY		 897 struct segmented_address addr = { .seg = VCPU_SREG_CS,
898 .ea = ctxt->_eip };
2fb53ad8 899 cur_size = fc->end - fc->start;
807941b1
TY		 900 size = min(15UL - cur_size,
901 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 902 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 903 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 904 return rc;
ef5d75cc
TY		 905 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
906 size, &ctxt->exception);
7d88bb48 907 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 908 return rc;
2fb53ad8 909 fc->end += size;
62266869 910 }
807941b1
TY		 911 *dest = fc->data[ctxt->_eip - fc->start];
912 ctxt->_eip++;
3e2815e9 913 return X86EMUL_CONTINUE;
62266869
AK		 914}
915
916static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 917 void *dest, unsigned size)
62266869 918{
3e2815e9 919 int rc;
62266869 920
eb3c79e6 921 /* x86 instructions are limited to 15 bytes. */
7d88bb48 922 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 923 return X86EMUL_UNHANDLEABLE;
62266869 924 while (size--) {
807941b1 925 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 926 if (rc != X86EMUL_CONTINUE)
62266869
AK		 927 return rc;
928 }
3e2815e9 929 return X86EMUL_CONTINUE;
62266869
AK		 930}
931
67cbc90d 932/* Fetch next part of the instruction being emulated. */
e85a1085 933#define insn_fetch(_type, _ctxt) \
67cbc90d 934({ unsigned long _x; \
e85a1085 935 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 936 if (rc != X86EMUL_CONTINUE) \
937 goto done; \
67cbc90d
TY		 938 (_type)_x; \
939})
940
807941b1
TY		 941#define insn_fetch_arr(_arr, _size, _ctxt) \
942({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 943 if (rc != X86EMUL_CONTINUE) \
944 goto done; \
67cbc90d
TY		 945})
946
1e3c5cb0
RR		 947/*
948 * Given the 'reg' portion of a ModRM byte, and a register block, return a
949 * pointer into the block that addresses the relevant register.
950 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
951 */
dd856efa 952static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 953 int highbyte_regs)
6aa8b732
AK		 954{
955 void *p;
956
6aa8b732 957 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 958 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
959 else
960 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 961 return p;
962}
963
964static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 965 struct segmented_address addr,
6aa8b732
AK		 966 u16 *size, unsigned long *address, int op_bytes)
967{
968 int rc;
969
970 if (op_bytes == 2)
971 op_bytes = 3;
972 *address = 0;
3ca3ac4d 973 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 974 if (rc != X86EMUL_CONTINUE)
6aa8b732 975 return rc;
30b31ab6 976 addr.ea += 2;
3ca3ac4d 977 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 978 return rc;
979}
980
34b77652
AK		 981FASTOP2(add);
982FASTOP2(or);
983FASTOP2(adc);
984FASTOP2(sbb);
985FASTOP2(and);
986FASTOP2(sub);
987FASTOP2(xor);
988FASTOP2(cmp);
989FASTOP2(test);
990
991FASTOP3WCL(shld);
992FASTOP3WCL(shrd);
993
994FASTOP2W(imul);
995
996FASTOP1(not);
997FASTOP1(neg);
998FASTOP1(inc);
999FASTOP1(dec);
1000
1001FASTOP2CL(rol);
1002FASTOP2CL(ror);
1003FASTOP2CL(rcl);
1004FASTOP2CL(rcr);
1005FASTOP2CL(shl);
1006FASTOP2CL(shr);
1007FASTOP2CL(sar);
1008
1009FASTOP2W(bsf);
1010FASTOP2W(bsr);
1011FASTOP2W(bt);
1012FASTOP2W(bts);
1013FASTOP2W(btr);
1014FASTOP2W(btc);
1015
9ae9feba 1016static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1017{
9ae9feba
AK		 1018 u8 rc;
1019 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1020
9ae9feba 1021 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1022 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1023 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1024 return rc;
bbe9abbd
NK		 1025}
1026
91ff3cb4
AK		 1027static void fetch_register_operand(struct operand *op)
1028{
1029 switch (op->bytes) {
1030 case 1:
1031 op->val = *(u8 *)op->addr.reg;
1032 break;
1033 case 2:
1034 op->val = *(u16 *)op->addr.reg;
1035 break;
1036 case 4:
1037 op->val = *(u32 *)op->addr.reg;
1038 break;
1039 case 8:
1040 op->val = *(u64 *)op->addr.reg;
1041 break;
1042 }
1043}
1044
1253791d
AK		 1045static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1046{
1047 ctxt->ops->get_fpu(ctxt);
1048 switch (reg) {
89a87c67
MK		 1049 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1050 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1051 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1052 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1053 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1054 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1055 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1056 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1057#ifdef CONFIG_X86_64
89a87c67
MK		 1058 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1059 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1060 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1061 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1062 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1063 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1064 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1065 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1066#endif
1067 default: BUG();
1068 }
1069 ctxt->ops->put_fpu(ctxt);
1070}
1071
1072static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1073 int reg)
1074{
1075 ctxt->ops->get_fpu(ctxt);
1076 switch (reg) {
89a87c67
MK		 1077 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1078 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1079 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1080 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1081 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1082 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1083 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1084 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1085#ifdef CONFIG_X86_64
89a87c67
MK		 1086 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1087 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1088 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1089 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1090 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1091 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1092 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1093 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1094#endif
1095 default: BUG();
1096 }
1097 ctxt->ops->put_fpu(ctxt);
1098}
1099
cbe2c9d3
AK		 1100static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1101{
1102 ctxt->ops->get_fpu(ctxt);
1103 switch (reg) {
1104 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1105 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1106 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1107 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1108 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1109 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1110 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1111 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1112 default: BUG();
1113 }
1114 ctxt->ops->put_fpu(ctxt);
1115}
1116
1117static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1118{
1119 ctxt->ops->get_fpu(ctxt);
1120 switch (reg) {
1121 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1122 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1123 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1124 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1125 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1126 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1127 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1128 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1129 default: BUG();
1130 }
1131 ctxt->ops->put_fpu(ctxt);
1132}
1133
045a282c
GN		 1134static int em_fninit(struct x86_emulate_ctxt *ctxt)
1135{
1136 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1137 return emulate_nm(ctxt);
1138
1139 ctxt->ops->get_fpu(ctxt);
1140 asm volatile("fninit");
1141 ctxt->ops->put_fpu(ctxt);
1142 return X86EMUL_CONTINUE;
1143}
1144
1145static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1146{
1147 u16 fcw;
1148
1149 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1150 return emulate_nm(ctxt);
1151
1152 ctxt->ops->get_fpu(ctxt);
1153 asm volatile("fnstcw %0": "+m"(fcw));
1154 ctxt->ops->put_fpu(ctxt);
1155
1156 /* force 2 byte destination */
1157 ctxt->dst.bytes = 2;
1158 ctxt->dst.val = fcw;
1159
1160 return X86EMUL_CONTINUE;
1161}
1162
1163static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1164{
1165 u16 fsw;
1166
1167 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1168 return emulate_nm(ctxt);
1169
1170 ctxt->ops->get_fpu(ctxt);
1171 asm volatile("fnstsw %0": "+m"(fsw));
1172 ctxt->ops->put_fpu(ctxt);
1173
1174 /* force 2 byte destination */
1175 ctxt->dst.bytes = 2;
1176 ctxt->dst.val = fsw;
1177
1178 return X86EMUL_CONTINUE;
1179}
1180
1253791d 1181static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1182 struct operand *op)
3c118e24 1183{
9dac77fa
AK		 1184 unsigned reg = ctxt->modrm_reg;
1185 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1186
9dac77fa
AK		 1187 if (!(ctxt->d & ModRM))
1188 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1189
9dac77fa 1190 if (ctxt->d & Sse) {
1253791d
AK		 1191 op->type = OP_XMM;
1192 op->bytes = 16;
1193 op->addr.xmm = reg;
1194 read_sse_reg(ctxt, &op->vec_val, reg);
1195 return;
1196 }
cbe2c9d3
AK		 1197 if (ctxt->d & Mmx) {
1198 reg &= 7;
1199 op->type = OP_MM;
1200 op->bytes = 8;
1201 op->addr.mm = reg;
1202 return;
1203 }
1253791d 1204
3c118e24 1205 op->type = OP_REG;
2adb5ad9 1206 if (ctxt->d & ByteOp) {
dd856efa 1207 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1208 op->bytes = 1;
1209 } else {
dd856efa 1210 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1211 op->bytes = ctxt->op_bytes;
3c118e24 1212 }
91ff3cb4 1213 fetch_register_operand(op);
3c118e24
AK		 1214 op->orig_val = op->val;
1215}
1216
a6e3407b
AK		 1217static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1218{
1219 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1220 ctxt->modrm_seg = VCPU_SREG_SS;
1221}
1222
1c73ef66 1223static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1224 struct operand *op)
1c73ef66 1225{
1c73ef66 1226 u8 sib;
f5b4edcd 1227 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1228 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1229 ulong modrm_ea = 0;
1c73ef66 1230
9dac77fa
AK		 1231 if (ctxt->rex_prefix) {
1232 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1233 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1234 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1235 }
1236
9dac77fa
AK		 1237 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1238 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1239 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1240 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1241
9dac77fa 1242 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1243 op->type = OP_REG;
9dac77fa 1244 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1245 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1246 if (ctxt->d & Sse) {
1253791d
AK		 1247 op->type = OP_XMM;
1248 op->bytes = 16;
9dac77fa
AK		 1249 op->addr.xmm = ctxt->modrm_rm;
1250 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1251 return rc;
1252 }
cbe2c9d3
AK		 1253 if (ctxt->d & Mmx) {
1254 op->type = OP_MM;
1255 op->bytes = 8;
1256 op->addr.xmm = ctxt->modrm_rm & 7;
1257 return rc;
1258 }
2dbd0dd7 1259 fetch_register_operand(op);
1c73ef66
AK		 1260 return rc;
1261 }
1262
2dbd0dd7
AK		 1263 op->type = OP_MEM;
1264
9dac77fa 1265 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1266 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1267 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1268 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1269 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1270
1271 /* 16-bit ModR/M decode. */
9dac77fa 1272 switch (ctxt->modrm_mod) {
1c73ef66 1273 case 0:
9dac77fa 1274 if (ctxt->modrm_rm == 6)
e85a1085 1275 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1276 break;
1277 case 1:
e85a1085 1278 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1279 break;
1280 case 2:
e85a1085 1281 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1282 break;
1283 }
9dac77fa 1284 switch (ctxt->modrm_rm) {
1c73ef66 1285 case 0:
2dbd0dd7 1286 modrm_ea += bx + si;
1c73ef66
AK		 1287 break;
1288 case 1:
2dbd0dd7 1289 modrm_ea += bx + di;
1c73ef66
AK		 1290 break;
1291 case 2:
2dbd0dd7 1292 modrm_ea += bp + si;
1c73ef66
AK		 1293 break;
1294 case 3:
2dbd0dd7 1295 modrm_ea += bp + di;
1c73ef66
AK		 1296 break;
1297 case 4:
2dbd0dd7 1298 modrm_ea += si;
1c73ef66
AK		 1299 break;
1300 case 5:
2dbd0dd7 1301 modrm_ea += di;
1c73ef66
AK		 1302 break;
1303 case 6:
9dac77fa 1304 if (ctxt->modrm_mod != 0)
2dbd0dd7 1305 modrm_ea += bp;
1c73ef66
AK		 1306 break;
1307 case 7:
2dbd0dd7 1308 modrm_ea += bx;
1c73ef66
AK		 1309 break;
1310 }
9dac77fa
AK		 1311 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1312 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1313 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1314 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1315 } else {
1316 /* 32/64-bit ModR/M decode. */
9dac77fa 1317 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1318 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1319 index_reg |= (sib >> 3) & 7;
1320 base_reg |= sib & 7;
1321 scale = sib >> 6;
1322
9dac77fa 1323 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1324 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1325 else {
dd856efa 1326 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1327 adjust_modrm_seg(ctxt, base_reg);
1328 }
dc71d0f1 1329 if (index_reg != 4)
dd856efa 1330 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1331 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1332 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1333 ctxt->rip_relative = 1;
a6e3407b
AK		 1334 } else {
1335 base_reg = ctxt->modrm_rm;
dd856efa 1336 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1337 adjust_modrm_seg(ctxt, base_reg);
1338 }
9dac77fa 1339 switch (ctxt->modrm_mod) {
1c73ef66 1340 case 0:
9dac77fa 1341 if (ctxt->modrm_rm == 5)
e85a1085 1342 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1343 break;
1344 case 1:
e85a1085 1345 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1346 break;
1347 case 2:
e85a1085 1348 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1349 break;
1350 }
1351 }
90de84f5 1352 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1353done:
1354 return rc;
1355}
1356
1357static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1358 struct operand *op)
1c73ef66 1359{
3e2815e9 1360 int rc = X86EMUL_CONTINUE;
1c73ef66 1361
2dbd0dd7 1362 op->type = OP_MEM;
9dac77fa 1363 switch (ctxt->ad_bytes) {
1c73ef66 1364 case 2:
e85a1085 1365 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1366 break;
1367 case 4:
e85a1085 1368 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1369 break;
1370 case 8:
e85a1085 1371 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1372 break;
1373 }
1374done:
1375 return rc;
1376}
1377
9dac77fa 1378static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1379{
7129eeca 1380 long sv = 0, mask;
35c843c4 1381
9dac77fa
AK		 1382 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1383 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1384
9dac77fa
AK		 1385 if (ctxt->src.bytes == 2)
1386 sv = (s16)ctxt->src.val & (s16)mask;
1387 else if (ctxt->src.bytes == 4)
1388 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1389
9dac77fa 1390 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1391 }
ba7ff2b7
WY		 1392
1393 /* only subword offset */
9dac77fa 1394 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1395}
1396
dde7e6d1 1397static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1398 unsigned long addr, void *dest, unsigned size)
6aa8b732 1399{
dde7e6d1 1400 int rc;
9dac77fa 1401 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1402
f23b070e
XG		 1403 if (mc->pos < mc->end)
1404 goto read_cached;
6aa8b732 1405
f23b070e
XG		 1406 WARN_ON((mc->end + size) >= sizeof(mc->data));
1407
1408 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1409 &ctxt->exception);
1410 if (rc != X86EMUL_CONTINUE)
1411 return rc;
1412
1413 mc->end += size;
1414
1415read_cached:
1416 memcpy(dest, mc->data + mc->pos, size);
1417 mc->pos += size;
dde7e6d1
AK		 1418 return X86EMUL_CONTINUE;
1419}
6aa8b732 1420
3ca3ac4d
AK		 1421static int segmented_read(struct x86_emulate_ctxt *ctxt,
1422 struct segmented_address addr,
1423 void *data,
1424 unsigned size)
1425{
9fa088f4
AK		 1426 int rc;
1427 ulong linear;
1428
83b8795a 1429 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1430 if (rc != X86EMUL_CONTINUE)
1431 return rc;
7b105ca2 1432 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1433}
1434
1435static int segmented_write(struct x86_emulate_ctxt *ctxt,
1436 struct segmented_address addr,
1437 const void *data,
1438 unsigned size)
1439{
9fa088f4
AK		 1440 int rc;
1441 ulong linear;
1442
83b8795a 1443 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1444 if (rc != X86EMUL_CONTINUE)
1445 return rc;
0f65dd70
AK		 1446 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1447 &ctxt->exception);
3ca3ac4d
AK		 1448}
1449
1450static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1451 struct segmented_address addr,
1452 const void *orig_data, const void *data,
1453 unsigned size)
1454{
9fa088f4
AK		 1455 int rc;
1456 ulong linear;
1457
83b8795a 1458 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1459 if (rc != X86EMUL_CONTINUE)
1460 return rc;
0f65dd70
AK		 1461 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1462 size, &ctxt->exception);
3ca3ac4d
AK		 1463}
1464
dde7e6d1 1465static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1466 unsigned int size, unsigned short port,
1467 void *dest)
1468{
9dac77fa 1469 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1470
dde7e6d1 1471 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1472 unsigned int in_page, n;
9dac77fa 1473 unsigned int count = ctxt->rep_prefix ?
dd856efa 1474 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1475 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1476 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1477 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1478 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1479 count);
1480 if (n == 0)
1481 n = 1;
1482 rc->pos = rc->end = 0;
7b105ca2 1483 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1484 return 0;
1485 rc->end = n * size;
6aa8b732
AK		 1486 }
1487
b3356bf0
GN		 1488 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1489 ctxt->dst.data = rc->data + rc->pos;
1490 ctxt->dst.type = OP_MEM_STR;
1491 ctxt->dst.count = (rc->end - rc->pos) / size;
1492 rc->pos = rc->end;
1493 } else {
1494 memcpy(dest, rc->data + rc->pos, size);
1495 rc->pos += size;
1496 }
dde7e6d1
AK		 1497 return 1;
1498}
6aa8b732 1499
7f3d35fd
KW		 1500static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1501 u16 index, struct desc_struct *desc)
1502{
1503 struct desc_ptr dt;
1504 ulong addr;
1505
1506 ctxt->ops->get_idt(ctxt, &dt);
1507
1508 if (dt.size < index * 8 + 7)
1509 return emulate_gp(ctxt, index << 3 | 0x2);
1510
1511 addr = dt.address + index * 8;
1512 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1513 &ctxt->exception);
1514}
1515
dde7e6d1 1516static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1517 u16 selector, struct desc_ptr *dt)
1518{
0225fb50 1519 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1520
dde7e6d1
AK		 1521 if (selector & 1 << 2) {
1522 struct desc_struct desc;
1aa36616
AK		 1523 u16 sel;
1524
dde7e6d1 1525 memset (dt, 0, sizeof *dt);
1aa36616 1526 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1527 return;
e09d082c 1528
dde7e6d1
AK		 1529 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1530 dt->address = get_desc_base(&desc);
1531 } else
4bff1e86 1532 ops->get_gdt(ctxt, dt);
dde7e6d1 1533}
120df890 1534
dde7e6d1
AK		 1535/* allowed just for 8 bytes segments */
1536static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1537 u16 selector, struct desc_struct *desc,
1538 ulong *desc_addr_p)
dde7e6d1
AK		 1539{
1540 struct desc_ptr dt;
1541 u16 index = selector >> 3;
dde7e6d1 1542 ulong addr;
120df890 1543
7b105ca2 1544 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1545
35d3d4a1
AK		 1546 if (dt.size < index * 8 + 7)
1547 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1548
e919464b 1549 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1550 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1551 &ctxt->exception);
dde7e6d1 1552}
ef65c889 1553
dde7e6d1
AK		 1554/* allowed just for 8 bytes segments */
1555static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1556 u16 selector, struct desc_struct *desc)
1557{
1558 struct desc_ptr dt;
1559 u16 index = selector >> 3;
dde7e6d1 1560 ulong addr;
6aa8b732 1561
7b105ca2 1562 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1563
35d3d4a1
AK		 1564 if (dt.size < index * 8 + 7)
1565 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1566
dde7e6d1 1567 addr = dt.address + index * 8;
7b105ca2
TY		 1568 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1569 &ctxt->exception);
dde7e6d1 1570}
c7e75a3d 1571
5601d05b 1572/* Does not support long mode */
dde7e6d1 1573static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1574 u16 selector, int seg)
1575{
869be99c 1576 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1577 u8 dpl, rpl, cpl;
1578 unsigned err_vec = GP_VECTOR;
1579 u32 err_code = 0;
1580 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1581 ulong desc_addr;
dde7e6d1 1582 int ret;
03ebebeb 1583 u16 dummy;
69f55cb1 1584
dde7e6d1 1585 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1586
f8da94e9
KW		 1587 if (ctxt->mode == X86EMUL_MODE_REAL) {
1588 /* set real mode segment descriptor (keep limit etc. for
1589 * unreal mode) */
03ebebeb 1590 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1591 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1592 goto load;
f8da94e9
KW		 1593 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1594 /* VM86 needs a clean new segment descriptor */
1595 set_desc_base(&seg_desc, selector << 4);
1596 set_desc_limit(&seg_desc, 0xffff);
1597 seg_desc.type = 3;
1598 seg_desc.p = 1;
1599 seg_desc.s = 1;
1600 seg_desc.dpl = 3;
1601 goto load;
dde7e6d1
AK		 1602 }
1603
79d5b4c3
AK		 1604 rpl = selector & 3;
1605 cpl = ctxt->ops->cpl(ctxt);
1606
1607 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1608 if ((seg == VCPU_SREG_CS
1609 || (seg == VCPU_SREG_SS
1610 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1611 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1612 && null_selector)
1613 goto exception;
1614
1615 /* TR should be in GDT only */
1616 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1617 goto exception;
1618
1619 if (null_selector) /* for NULL selector skip all following checks */
1620 goto load;
1621
e919464b 1622 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1623 if (ret != X86EMUL_CONTINUE)
1624 return ret;
1625
1626 err_code = selector & 0xfffc;
1627 err_vec = GP_VECTOR;
1628
fc058680 1629 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1630 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1631 goto exception;
1632
1633 if (!seg_desc.p) {
1634 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1635 goto exception;
1636 }
1637
dde7e6d1 1638 dpl = seg_desc.dpl;
dde7e6d1
AK		 1639
1640 switch (seg) {
1641 case VCPU_SREG_SS:
1642 /*
1643 * segment is not a writable data segment or segment
1644 * selector's RPL != CPL or segment selector's RPL != CPL
1645 */
1646 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1647 goto exception;
6aa8b732 1648 break;
dde7e6d1
AK		 1649 case VCPU_SREG_CS:
1650 if (!(seg_desc.type & 8))
1651 goto exception;
1652
1653 if (seg_desc.type & 4) {
1654 /* conforming */
1655 if (dpl > cpl)
1656 goto exception;
1657 } else {
1658 /* nonconforming */
1659 if (rpl > cpl || dpl != cpl)
1660 goto exception;
1661 }
1662 /* CS(RPL) <- CPL */
1663 selector = (selector & 0xfffc) | cpl;
6aa8b732 1664 break;
dde7e6d1
AK		 1665 case VCPU_SREG_TR:
1666 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1667 goto exception;
869be99c
AK		 1668 old_desc = seg_desc;
1669 seg_desc.type |= 2; /* busy */
1670 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1671 sizeof(seg_desc), &ctxt->exception);
1672 if (ret != X86EMUL_CONTINUE)
1673 return ret;
dde7e6d1
AK		 1674 break;
1675 case VCPU_SREG_LDTR:
1676 if (seg_desc.s || seg_desc.type != 2)
1677 goto exception;
1678 break;
1679 default: /* DS, ES, FS, or GS */
4e62417b 1680 /*
dde7e6d1
AK		 1681 * segment is not a data or readable code segment or
1682 * ((segment is a data or nonconforming code segment)
1683 * and (both RPL and CPL > DPL))
4e62417b 1684 */
dde7e6d1
AK		 1685 if ((seg_desc.type & 0xa) == 0x8 ||
1686 (((seg_desc.type & 0xc) != 0xc) &&
1687 (rpl > dpl && cpl > dpl)))
1688 goto exception;
6aa8b732 1689 break;
dde7e6d1
AK		 1690 }
1691
1692 if (seg_desc.s) {
1693 /* mark segment as accessed */
1694 seg_desc.type |= 1;
7b105ca2 1695 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1696 if (ret != X86EMUL_CONTINUE)
1697 return ret;
1698 }
1699load:
7b105ca2 1700 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1701 return X86EMUL_CONTINUE;
1702exception:
1703 emulate_exception(ctxt, err_vec, err_code, true);
1704 return X86EMUL_PROPAGATE_FAULT;
1705}
1706
31be40b3
WY		 1707static void write_register_operand(struct operand *op)
1708{
1709 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1710 switch (op->bytes) {
1711 case 1:
1712 *(u8 *)op->addr.reg = (u8)op->val;
1713 break;
1714 case 2:
1715 *(u16 *)op->addr.reg = (u16)op->val;
1716 break;
1717 case 4:
1718 *op->addr.reg = (u32)op->val;
1719 break; /* 64b: zero-extend */
1720 case 8:
1721 *op->addr.reg = op->val;
1722 break;
1723 }
1724}
1725
adddcecf 1726static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1727{
1728 int rc;
dde7e6d1 1729
b6744dc3
AK		 1730 if (ctxt->d & NoWrite)
1731 return X86EMUL_CONTINUE;
1732
9dac77fa 1733 switch (ctxt->dst.type) {
dde7e6d1 1734 case OP_REG:
9dac77fa 1735 write_register_operand(&ctxt->dst);
6aa8b732 1736 break;
dde7e6d1 1737 case OP_MEM:
9dac77fa 1738 if (ctxt->lock_prefix)
3ca3ac4d 1739 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1740 ctxt->dst.addr.mem,
1741 &ctxt->dst.orig_val,
1742 &ctxt->dst.val,
1743 ctxt->dst.bytes);
341de7e3 1744 else
3ca3ac4d 1745 rc = segmented_write(ctxt,
9dac77fa
AK		 1746 ctxt->dst.addr.mem,
1747 &ctxt->dst.val,
1748 ctxt->dst.bytes);
dde7e6d1
AK		 1749 if (rc != X86EMUL_CONTINUE)
1750 return rc;
a682e354 1751 break;
b3356bf0
GN		 1752 case OP_MEM_STR:
1753 rc = segmented_write(ctxt,
1754 ctxt->dst.addr.mem,
1755 ctxt->dst.data,
1756 ctxt->dst.bytes * ctxt->dst.count);
1757 if (rc != X86EMUL_CONTINUE)
1758 return rc;
1759 break;
1253791d 1760 case OP_XMM:
9dac77fa 1761 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1762 break;
cbe2c9d3
AK		 1763 case OP_MM:
1764 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1765 break;
dde7e6d1
AK		 1766 case OP_NONE:
1767 /* no writeback */
414e6277 1768 break;
dde7e6d1 1769 default:
414e6277 1770 break;
6aa8b732 1771 }
dde7e6d1
AK		 1772 return X86EMUL_CONTINUE;
1773}
6aa8b732 1774
51ddff50 1775static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1776{
4179bb02 1777 struct segmented_address addr;
0dc8d10f 1778
5ad105e5 1779 rsp_increment(ctxt, -bytes);
dd856efa 1780 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1781 addr.seg = VCPU_SREG_SS;
1782
51ddff50
AK		 1783 return segmented_write(ctxt, addr, data, bytes);
1784}
1785
1786static int em_push(struct x86_emulate_ctxt *ctxt)
1787{
4179bb02 1788 /* Disable writeback. */
9dac77fa 1789 ctxt->dst.type = OP_NONE;
51ddff50 1790 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1791}
69f55cb1 1792
dde7e6d1 1793static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1794 void *dest, int len)
1795{
dde7e6d1 1796 int rc;
90de84f5 1797 struct segmented_address addr;
8b4caf66 1798
dd856efa 1799 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1800 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1801 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1802 if (rc != X86EMUL_CONTINUE)
1803 return rc;
1804
5ad105e5 1805 rsp_increment(ctxt, len);
dde7e6d1 1806 return rc;
8b4caf66
LV		 1807}
1808
c54fe504
TY		 1809static int em_pop(struct x86_emulate_ctxt *ctxt)
1810{
9dac77fa 1811 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1812}
1813
dde7e6d1 1814static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1815 void *dest, int len)
9de41573
GN		 1816{
1817 int rc;
dde7e6d1
AK		 1818 unsigned long val, change_mask;
1819 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1820 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1821
3b9be3bf 1822 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1823 if (rc != X86EMUL_CONTINUE)
1824 return rc;
9de41573 1825
dde7e6d1
AK		 1826 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1827 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1828
dde7e6d1
AK		 1829 switch(ctxt->mode) {
1830 case X86EMUL_MODE_PROT64:
1831 case X86EMUL_MODE_PROT32:
1832 case X86EMUL_MODE_PROT16:
1833 if (cpl == 0)
1834 change_mask |= EFLG_IOPL;
1835 if (cpl <= iopl)
1836 change_mask |= EFLG_IF;
1837 break;
1838 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1839 if (iopl < 3)
1840 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1841 change_mask |= EFLG_IF;
1842 break;
1843 default: /* real mode */
1844 change_mask |= (EFLG_IOPL | EFLG_IF);
1845 break;
9de41573 1846 }
dde7e6d1
AK		 1847
1848 *(unsigned long *)dest =
1849 (ctxt->eflags & ~change_mask) | (val & change_mask);
1850
1851 return rc;
9de41573
GN		 1852}
1853
62aaa2f0
TY		 1854static int em_popf(struct x86_emulate_ctxt *ctxt)
1855{
9dac77fa
AK		 1856 ctxt->dst.type = OP_REG;
1857 ctxt->dst.addr.reg = &ctxt->eflags;
1858 ctxt->dst.bytes = ctxt->op_bytes;
1859 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1860}
1861
612e89f0
AK		 1862static int em_enter(struct x86_emulate_ctxt *ctxt)
1863{
1864 int rc;
1865 unsigned frame_size = ctxt->src.val;
1866 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1867 ulong rbp;
612e89f0
AK		 1868
1869 if (nesting_level)
1870 return X86EMUL_UNHANDLEABLE;
1871
dd856efa
AK		 1872 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1873 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1874 if (rc != X86EMUL_CONTINUE)
1875 return rc;
dd856efa 1876 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1877 stack_mask(ctxt));
dd856efa
AK		 1878 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1879 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1880 stack_mask(ctxt));
1881 return X86EMUL_CONTINUE;
1882}
1883
f47cfa31
AK		 1884static int em_leave(struct x86_emulate_ctxt *ctxt)
1885{
dd856efa 1886 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1887 stack_mask(ctxt));
dd856efa 1888 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1889}
1890
1cd196ea 1891static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1892{
1cd196ea
AK		 1893 int seg = ctxt->src2.val;
1894
9dac77fa 1895 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1896
4487b3b4 1897 return em_push(ctxt);
7b262e90
GN		 1898}
1899
1cd196ea 1900static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1901{
1cd196ea 1902 int seg = ctxt->src2.val;
dde7e6d1
AK		 1903 unsigned long selector;
1904 int rc;
38ba30ba 1905
9dac77fa 1906 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1907 if (rc != X86EMUL_CONTINUE)
1908 return rc;
1909
7b105ca2 1910 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1911 return rc;
38ba30ba
GN		 1912}
1913
b96a7fad 1914static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1915{
dd856efa 1916 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1917 int rc = X86EMUL_CONTINUE;
1918 int reg = VCPU_REGS_RAX;
38ba30ba 1919
dde7e6d1
AK		 1920 while (reg <= VCPU_REGS_RDI) {
1921 (reg == VCPU_REGS_RSP) ?
dd856efa 1922 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1923
4487b3b4 1924 rc = em_push(ctxt);
dde7e6d1
AK		 1925 if (rc != X86EMUL_CONTINUE)
1926 return rc;
38ba30ba 1927
dde7e6d1 1928 ++reg;
38ba30ba 1929 }
38ba30ba 1930
dde7e6d1 1931 return rc;
38ba30ba
GN		 1932}
1933
62aaa2f0
TY		 1934static int em_pushf(struct x86_emulate_ctxt *ctxt)
1935{
9dac77fa 1936 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1937 return em_push(ctxt);
1938}
1939
b96a7fad 1940static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1941{
dde7e6d1
AK		 1942 int rc = X86EMUL_CONTINUE;
1943 int reg = VCPU_REGS_RDI;
38ba30ba 1944
dde7e6d1
AK		 1945 while (reg >= VCPU_REGS_RAX) {
1946 if (reg == VCPU_REGS_RSP) {
5ad105e5 1947 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1948 --reg;
1949 }
38ba30ba 1950
dd856efa 1951 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1952 if (rc != X86EMUL_CONTINUE)
1953 break;
1954 --reg;
38ba30ba 1955 }
dde7e6d1 1956 return rc;
38ba30ba
GN		 1957}
1958
dd856efa 1959static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1960{
0225fb50 1961 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1962 int rc;
6e154e56
MG		 1963 struct desc_ptr dt;
1964 gva_t cs_addr;
1965 gva_t eip_addr;
1966 u16 cs, eip;
6e154e56
MG		 1967
1968 /* TODO: Add limit checks */
9dac77fa 1969 ctxt->src.val = ctxt->eflags;
4487b3b4 1970 rc = em_push(ctxt);
5c56e1cf
AK		 1971 if (rc != X86EMUL_CONTINUE)
1972 return rc;
6e154e56
MG		 1973
1974 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1975
9dac77fa 1976 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1977 rc = em_push(ctxt);
5c56e1cf
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 return rc;
6e154e56 1980
9dac77fa 1981 ctxt->src.val = ctxt->_eip;
4487b3b4 1982 rc = em_push(ctxt);
5c56e1cf
AK		 1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
1985
4bff1e86 1986 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1987
1988 eip_addr = dt.address + (irq << 2);
1989 cs_addr = dt.address + (irq << 2) + 2;
1990
0f65dd70 1991 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
1994
0f65dd70 1995 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1996 if (rc != X86EMUL_CONTINUE)
1997 return rc;
1998
7b105ca2 1999 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2000 if (rc != X86EMUL_CONTINUE)
2001 return rc;
2002
9dac77fa 2003 ctxt->_eip = eip;
6e154e56
MG		 2004
2005 return rc;
2006}
2007
dd856efa
AK		 2008int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2009{
2010 int rc;
2011
2012 invalidate_registers(ctxt);
2013 rc = __emulate_int_real(ctxt, irq);
2014 if (rc == X86EMUL_CONTINUE)
2015 writeback_registers(ctxt);
2016 return rc;
2017}
2018
7b105ca2 2019static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2020{
2021 switch(ctxt->mode) {
2022 case X86EMUL_MODE_REAL:
dd856efa 2023 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2024 case X86EMUL_MODE_VM86:
2025 case X86EMUL_MODE_PROT16:
2026 case X86EMUL_MODE_PROT32:
2027 case X86EMUL_MODE_PROT64:
2028 default:
2029 /* Protected mode interrupts unimplemented yet */
2030 return X86EMUL_UNHANDLEABLE;
2031 }
2032}
2033
7b105ca2 2034static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2035{
dde7e6d1
AK		 2036 int rc = X86EMUL_CONTINUE;
2037 unsigned long temp_eip = 0;
2038 unsigned long temp_eflags = 0;
2039 unsigned long cs = 0;
2040 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2041 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2042 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2043 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2044
dde7e6d1 2045 /* TODO: Add stack limit check */
38ba30ba 2046
9dac77fa 2047 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2048
dde7e6d1
AK		 2049 if (rc != X86EMUL_CONTINUE)
2050 return rc;
38ba30ba 2051
35d3d4a1
AK		 2052 if (temp_eip & ~0xffff)
2053 return emulate_gp(ctxt, 0);
38ba30ba 2054
9dac77fa 2055 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2056
dde7e6d1
AK		 2057 if (rc != X86EMUL_CONTINUE)
2058 return rc;
38ba30ba 2059
9dac77fa 2060 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2061
dde7e6d1
AK		 2062 if (rc != X86EMUL_CONTINUE)
2063 return rc;
38ba30ba 2064
7b105ca2 2065 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2066
dde7e6d1
AK		 2067 if (rc != X86EMUL_CONTINUE)
2068 return rc;
38ba30ba 2069
9dac77fa 2070 ctxt->_eip = temp_eip;
38ba30ba 2071
38ba30ba 2072
9dac77fa 2073 if (ctxt->op_bytes == 4)
dde7e6d1 2074 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2075 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2076 ctxt->eflags &= ~0xffff;
2077 ctxt->eflags |= temp_eflags;
38ba30ba 2078 }
dde7e6d1
AK		 2079
2080 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2081 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2082
2083 return rc;
38ba30ba
GN		 2084}
2085
e01991e7 2086static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2087{
dde7e6d1
AK		 2088 switch(ctxt->mode) {
2089 case X86EMUL_MODE_REAL:
7b105ca2 2090 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2091 case X86EMUL_MODE_VM86:
2092 case X86EMUL_MODE_PROT16:
2093 case X86EMUL_MODE_PROT32:
2094 case X86EMUL_MODE_PROT64:
c37eda13 2095 default:
dde7e6d1
AK		 2096 /* iret from protected mode unimplemented yet */
2097 return X86EMUL_UNHANDLEABLE;
c37eda13 2098 }
c37eda13
WY		 2099}
2100
d2f62766
TY		 2101static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2102{
d2f62766
TY		 2103 int rc;
2104 unsigned short sel;
2105
9dac77fa 2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2107
7b105ca2 2108 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2109 if (rc != X86EMUL_CONTINUE)
2110 return rc;
2111
9dac77fa
AK		 2112 ctxt->_eip = 0;
2113 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2114 return X86EMUL_CONTINUE;
2115}
2116
3329ece1
AK		 2117static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2118{
2119 u8 ex = 0;
2120
2121 emulate_1op_rax_rdx(ctxt, "mul", ex);
2122 return X86EMUL_CONTINUE;
2123}
2124
2125static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2126{
2127 u8 ex = 0;
2128
2129 emulate_1op_rax_rdx(ctxt, "imul", ex);
2130 return X86EMUL_CONTINUE;
2131}
2132
2133static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2134{
34d1f490 2135 u8 de = 0;
8cdbd2c9 2136
3329ece1
AK		 2137 emulate_1op_rax_rdx(ctxt, "div", de);
2138 if (de)
2139 return emulate_de(ctxt);
2140 return X86EMUL_CONTINUE;
2141}
2142
2143static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2144{
2145 u8 de = 0;
2146
2147 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2148 if (de)
2149 return emulate_de(ctxt);
8c5eee30 2150 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2151}
2152
51187683 2153static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2154{
4179bb02 2155 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2156
9dac77fa 2157 switch (ctxt->modrm_reg) {
d19292e4
MG		 2158 case 2: /* call near abs */ {
2159 long int old_eip;
9dac77fa
AK		 2160 old_eip = ctxt->_eip;
2161 ctxt->_eip = ctxt->src.val;
2162 ctxt->src.val = old_eip;
4487b3b4 2163 rc = em_push(ctxt);
d19292e4
MG		 2164 break;
2165 }
8cdbd2c9 2166 case 4: /* jmp abs */
9dac77fa 2167 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2168 break;
d2f62766
TY		 2169 case 5: /* jmp far */
2170 rc = em_jmp_far(ctxt);
2171 break;
8cdbd2c9 2172 case 6: /* push */
4487b3b4 2173 rc = em_push(ctxt);
8cdbd2c9 2174 break;
8cdbd2c9 2175 }
4179bb02 2176 return rc;
8cdbd2c9
LV		 2177}
2178
e0dac408 2179static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2180{
9dac77fa 2181 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2182
dd856efa
AK		 2183 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2184 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2185 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2186 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2187 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2188 } else {
dd856efa
AK		 2189 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2190 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2191
05f086f8 2192 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2193 }
1b30eaa8 2194 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2195}
2196
ebda02c2
TY		 2197static int em_ret(struct x86_emulate_ctxt *ctxt)
2198{
9dac77fa
AK		 2199 ctxt->dst.type = OP_REG;
2200 ctxt->dst.addr.reg = &ctxt->_eip;
2201 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2202 return em_pop(ctxt);
2203}
2204
e01991e7 2205static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2206{
a77ab5ea
AK		 2207 int rc;
2208 unsigned long cs;
2209
9dac77fa 2210 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2211 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2212 return rc;
9dac77fa
AK		 2213 if (ctxt->op_bytes == 4)
2214 ctxt->_eip = (u32)ctxt->_eip;
2215 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2216 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2217 return rc;
7b105ca2 2218 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2219 return rc;
2220}
2221
e940b5c2
TY		 2222static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2223{
2224 /* Save real source value, then compare EAX against destination. */
2225 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2226 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2227 fastop(ctxt, em_cmp);
e940b5c2
TY		 2228
2229 if (ctxt->eflags & EFLG_ZF) {
2230 /* Success: write back to memory. */
2231 ctxt->dst.val = ctxt->src.orig_val;
2232 } else {
2233 /* Failure: write the value we saw to EAX. */
2234 ctxt->dst.type = OP_REG;
dd856efa 2235 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2236 }
2237 return X86EMUL_CONTINUE;
2238}
2239
d4b4325f 2240static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2241{
d4b4325f 2242 int seg = ctxt->src2.val;
09b5f4d3
WY		 2243 unsigned short sel;
2244 int rc;
2245
9dac77fa 2246 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2247
7b105ca2 2248 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2249 if (rc != X86EMUL_CONTINUE)
2250 return rc;
2251
9dac77fa 2252 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2253 return rc;
2254}
2255
7b105ca2 2256static void
e66bb2cc 2257setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2258 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2259{
e66bb2cc 2260 cs->l = 0; /* will be adjusted later */
79168fd1 2261 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2262 cs->g = 1; /* 4kb granularity */
79168fd1 2263 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2264 cs->type = 0x0b; /* Read, Execute, Accessed */
2265 cs->s = 1;
2266 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2267 cs->p = 1;
2268 cs->d = 1;
99245b50 2269 cs->avl = 0;
e66bb2cc 2270
79168fd1
GN		 2271 set_desc_base(ss, 0); /* flat segment */
2272 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2273 ss->g = 1; /* 4kb granularity */
2274 ss->s = 1;
2275 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2276 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2277 ss->dpl = 0;
79168fd1 2278 ss->p = 1;
99245b50
GN		 2279 ss->l = 0;
2280 ss->avl = 0;
e66bb2cc
AP		 2281}
2282
1a18a69b
AK		 2283static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2284{
2285 u32 eax, ebx, ecx, edx;
2286
2287 eax = ecx = 0;
0017f93a
AK		 2288 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2289 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2290 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2291 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2292}
2293
c2226fc9
SB		 2294static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2295{
0225fb50 2296 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2297 u32 eax, ebx, ecx, edx;
2298
2299 /*
2300 * syscall should always be enabled in longmode - so only become
2301 * vendor specific (cpuid) if other modes are active...
2302 */
2303 if (ctxt->mode == X86EMUL_MODE_PROT64)
2304 return true;
2305
2306 eax = 0x00000000;
2307 ecx = 0x00000000;
0017f93a
AK		 2308 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2309 /*
2310 * Intel ("GenuineIntel")
2311 * remark: Intel CPUs only support "syscall" in 64bit
2312 * longmode. Also an 64bit guest with a
2313 * 32bit compat-app running will #UD !! While this
2314 * behaviour can be fixed (by emulating) into AMD
2315 * response - CPUs of AMD can't behave like Intel.
2316 */
2317 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2318 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2319 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2320 return false;
2321
2322 /* AMD ("AuthenticAMD") */
2323 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2324 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2325 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2326 return true;
2327
2328 /* AMD ("AMDisbetter!") */
2329 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2330 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2331 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2332 return true;
c2226fc9
SB		 2333
2334 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2335 return false;
2336}
2337
e01991e7 2338static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2339{
0225fb50 2340 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2341 struct desc_struct cs, ss;
e66bb2cc 2342 u64 msr_data;
79168fd1 2343 u16 cs_sel, ss_sel;
c2ad2bb3 2344 u64 efer = 0;
e66bb2cc
AP		 2345
2346 /* syscall is not available in real mode */
2e901c4c 2347 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2348 ctxt->mode == X86EMUL_MODE_VM86)
2349 return emulate_ud(ctxt);
e66bb2cc 2350
c2226fc9
SB		 2351 if (!(em_syscall_is_enabled(ctxt)))
2352 return emulate_ud(ctxt);
2353
c2ad2bb3 2354 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2355 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2356
c2226fc9
SB		 2357 if (!(efer & EFER_SCE))
2358 return emulate_ud(ctxt);
2359
717746e3 2360 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2361 msr_data >>= 32;
79168fd1
GN		 2362 cs_sel = (u16)(msr_data & 0xfffc);
2363 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2364
c2ad2bb3 2365 if (efer & EFER_LMA) {
79168fd1 2366 cs.d = 0;
e66bb2cc
AP		 2367 cs.l = 1;
2368 }
1aa36616
AK		 2369 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2370 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2371
dd856efa 2372 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2373 if (efer & EFER_LMA) {
e66bb2cc 2374#ifdef CONFIG_X86_64
dd856efa 2375 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2376
717746e3 2377 ops->get_msr(ctxt,
3fb1b5db
GN		 2378 ctxt->mode == X86EMUL_MODE_PROT64 ?
2379 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2380 ctxt->_eip = msr_data;
e66bb2cc 2381
717746e3 2382 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2383 ctxt->eflags &= ~(msr_data | EFLG_RF);
2384#endif
2385 } else {
2386 /* legacy mode */
717746e3 2387 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2388 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2389
2390 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2391 }
2392
e54cfa97 2393 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2394}
2395
e01991e7 2396static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2397{
0225fb50 2398 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2399 struct desc_struct cs, ss;
8c604352 2400 u64 msr_data;
79168fd1 2401 u16 cs_sel, ss_sel;
c2ad2bb3 2402 u64 efer = 0;
8c604352 2403
7b105ca2 2404 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2405 /* inject #GP if in real mode */
35d3d4a1
AK		 2406 if (ctxt->mode == X86EMUL_MODE_REAL)
2407 return emulate_gp(ctxt, 0);
8c604352 2408
1a18a69b
AK		 2409 /*
2410 * Not recognized on AMD in compat mode (but is recognized in legacy
2411 * mode).
2412 */
2413 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2414 && !vendor_intel(ctxt))
2415 return emulate_ud(ctxt);
2416
8c604352
AP		 2417 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2418 * Therefore, we inject an #UD.
2419 */
35d3d4a1
AK		 2420 if (ctxt->mode == X86EMUL_MODE_PROT64)
2421 return emulate_ud(ctxt);
8c604352 2422
7b105ca2 2423 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2424
717746e3 2425 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2426 switch (ctxt->mode) {
2427 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2428 if ((msr_data & 0xfffc) == 0x0)
2429 return emulate_gp(ctxt, 0);
8c604352
AP		 2430 break;
2431 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2432 if (msr_data == 0x0)
2433 return emulate_gp(ctxt, 0);
8c604352 2434 break;
9d1b39a9
GN		 2435 default:
2436 break;
8c604352
AP		 2437 }
2438
2439 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2440 cs_sel = (u16)msr_data;
2441 cs_sel &= ~SELECTOR_RPL_MASK;
2442 ss_sel = cs_sel + 8;
2443 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2444 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2445 cs.d = 0;
8c604352
AP		 2446 cs.l = 1;
2447 }
2448
1aa36616
AK		 2449 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2450 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2451
717746e3 2452 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2453 ctxt->_eip = msr_data;
8c604352 2454
717746e3 2455 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2456 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2457
e54cfa97 2458 return X86EMUL_CONTINUE;
8c604352
AP		 2459}
2460
e01991e7 2461static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2462{
0225fb50 2463 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2464 struct desc_struct cs, ss;
4668f050
AP		 2465 u64 msr_data;
2466 int usermode;
1249b96e 2467 u16 cs_sel = 0, ss_sel = 0;
4668f050 2468
a0044755
GN		 2469 /* inject #GP if in real mode or Virtual 8086 mode */
2470 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2471 ctxt->mode == X86EMUL_MODE_VM86)
2472 return emulate_gp(ctxt, 0);
4668f050 2473
7b105ca2 2474 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2475
9dac77fa 2476 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2477 usermode = X86EMUL_MODE_PROT64;
2478 else
2479 usermode = X86EMUL_MODE_PROT32;
2480
2481 cs.dpl = 3;
2482 ss.dpl = 3;
717746e3 2483 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2484 switch (usermode) {
2485 case X86EMUL_MODE_PROT32:
79168fd1 2486 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2487 if ((msr_data & 0xfffc) == 0x0)
2488 return emulate_gp(ctxt, 0);
79168fd1 2489 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2490 break;
2491 case X86EMUL_MODE_PROT64:
79168fd1 2492 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2493 if (msr_data == 0x0)
2494 return emulate_gp(ctxt, 0);
79168fd1
GN		 2495 ss_sel = cs_sel + 8;
2496 cs.d = 0;
4668f050
AP		 2497 cs.l = 1;
2498 break;
2499 }
79168fd1
GN		 2500 cs_sel |= SELECTOR_RPL_MASK;
2501 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2502
1aa36616
AK		 2503 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2504 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2505
dd856efa
AK		 2506 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2507 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2508
e54cfa97 2509 return X86EMUL_CONTINUE;
4668f050
AP		 2510}
2511
7b105ca2 2512static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2513{
2514 int iopl;
2515 if (ctxt->mode == X86EMUL_MODE_REAL)
2516 return false;
2517 if (ctxt->mode == X86EMUL_MODE_VM86)
2518 return true;
2519 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2520 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2521}
2522
2523static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2524 u16 port, u16 len)
2525{
0225fb50 2526 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2527 struct desc_struct tr_seg;
5601d05b 2528 u32 base3;
f850e2e6 2529 int r;
1aa36616 2530 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2531 unsigned mask = (1 << len) - 1;
5601d05b 2532 unsigned long base;
f850e2e6 2533
1aa36616 2534 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2535 if (!tr_seg.p)
f850e2e6 2536 return false;
79168fd1 2537 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2538 return false;
5601d05b
GN		 2539 base = get_desc_base(&tr_seg);
2540#ifdef CONFIG_X86_64
2541 base |= ((u64)base3) << 32;
2542#endif
0f65dd70 2543 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2544 if (r != X86EMUL_CONTINUE)
2545 return false;
79168fd1 2546 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2547 return false;
0f65dd70 2548 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2549 if (r != X86EMUL_CONTINUE)
2550 return false;
2551 if ((perm >> bit_idx) & mask)
2552 return false;
2553 return true;
2554}
2555
2556static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2557 u16 port, u16 len)
2558{
4fc40f07
GN		 2559 if (ctxt->perm_ok)
2560 return true;
2561
7b105ca2
TY		 2562 if (emulator_bad_iopl(ctxt))
2563 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2564 return false;
4fc40f07
GN		 2565
2566 ctxt->perm_ok = true;
2567
f850e2e6
GN		 2568 return true;
2569}
2570
38ba30ba 2571static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2572 struct tss_segment_16 *tss)
2573{
9dac77fa 2574 tss->ip = ctxt->_eip;
38ba30ba 2575 tss->flag = ctxt->eflags;
dd856efa
AK		 2576 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2577 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2578 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2579 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2580 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2581 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2582 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2583 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2584
1aa36616
AK		 2585 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2586 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2587 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2588 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2589 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2590}
2591
2592static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2593 struct tss_segment_16 *tss)
2594{
38ba30ba
GN		 2595 int ret;
2596
9dac77fa 2597 ctxt->_eip = tss->ip;
38ba30ba 2598 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2599 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2600 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2601 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2602 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2603 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2604 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2605 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2606 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2607
2608 /*
2609 * SDM says that segment selectors are loaded before segment
2610 * descriptors
2611 */
1aa36616
AK		 2612 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2613 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2614 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2615 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2616 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2617
2618 /*
fc058680 2619 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2620 * it is handled in a context of new task
2621 */
7b105ca2 2622 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2623 if (ret != X86EMUL_CONTINUE)
2624 return ret;
7b105ca2 2625 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2626 if (ret != X86EMUL_CONTINUE)
2627 return ret;
7b105ca2 2628 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2629 if (ret != X86EMUL_CONTINUE)
2630 return ret;
7b105ca2 2631 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2632 if (ret != X86EMUL_CONTINUE)
2633 return ret;
7b105ca2 2634 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2635 if (ret != X86EMUL_CONTINUE)
2636 return ret;
2637
2638 return X86EMUL_CONTINUE;
2639}
2640
2641static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2642 u16 tss_selector, u16 old_tss_sel,
2643 ulong old_tss_base, struct desc_struct *new_desc)
2644{
0225fb50 2645 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2646 struct tss_segment_16 tss_seg;
2647 int ret;
bcc55cba 2648 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2649
0f65dd70 2650 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2651 &ctxt->exception);
db297e3d 2652 if (ret != X86EMUL_CONTINUE)
38ba30ba 2653 /* FIXME: need to provide precise fault address */
38ba30ba 2654 return ret;
38ba30ba 2655
7b105ca2 2656 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2657
0f65dd70 2658 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2659 &ctxt->exception);
db297e3d 2660 if (ret != X86EMUL_CONTINUE)
38ba30ba 2661 /* FIXME: need to provide precise fault address */
38ba30ba 2662 return ret;
38ba30ba 2663
0f65dd70 2664 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2665 &ctxt->exception);
db297e3d 2666 if (ret != X86EMUL_CONTINUE)
38ba30ba 2667 /* FIXME: need to provide precise fault address */
38ba30ba 2668 return ret;
38ba30ba
GN		 2669
2670 if (old_tss_sel != 0xffff) {
2671 tss_seg.prev_task_link = old_tss_sel;
2672
0f65dd70 2673 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2674 &tss_seg.prev_task_link,
2675 sizeof tss_seg.prev_task_link,
0f65dd70 2676 &ctxt->exception);
db297e3d 2677 if (ret != X86EMUL_CONTINUE)
38ba30ba 2678 /* FIXME: need to provide precise fault address */
38ba30ba 2679 return ret;
38ba30ba
GN		 2680 }
2681
7b105ca2 2682 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2683}
2684
2685static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2686 struct tss_segment_32 *tss)
2687{
7b105ca2 2688 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2689 tss->eip = ctxt->_eip;
38ba30ba 2690 tss->eflags = ctxt->eflags;
dd856efa
AK		 2691 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2692 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2693 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2694 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2695 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2696 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2697 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2698 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2699
1aa36616
AK		 2700 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2701 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2702 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2703 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2704 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2705 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2706 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2707}
2708
2709static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2710 struct tss_segment_32 *tss)
2711{
38ba30ba
GN		 2712 int ret;
2713
7b105ca2 2714 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2715 return emulate_gp(ctxt, 0);
9dac77fa 2716 ctxt->_eip = tss->eip;
38ba30ba 2717 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2718
2719 /* General purpose registers */
dd856efa
AK		 2720 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2721 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2722 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2723 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2724 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2725 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2726 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2727 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2728
2729 /*
2730 * SDM says that segment selectors are loaded before segment
2731 * descriptors
2732 */
1aa36616
AK		 2733 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2734 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2735 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2736 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2737 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2738 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2739 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2740
4cee4798
KW		 2741 /*
2742 * If we're switching between Protected Mode and VM86, we need to make
2743 * sure to update the mode before loading the segment descriptors so
2744 * that the selectors are interpreted correctly.
2745 *
2746 * Need to get rflags to the vcpu struct immediately because it
2747 * influences the CPL which is checked at least when loading the segment
2748 * descriptors and when pushing an error code to the new kernel stack.
2749 *
2750 * TODO Introduce a separate ctxt->ops->set_cpl callback
2751 */
2752 if (ctxt->eflags & X86_EFLAGS_VM)
2753 ctxt->mode = X86EMUL_MODE_VM86;
2754 else
2755 ctxt->mode = X86EMUL_MODE_PROT32;
2756
2757 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2758
38ba30ba
GN		 2759 /*
2760 * Now load segment descriptors. If fault happenes at this stage
2761 * it is handled in a context of new task
2762 */
7b105ca2 2763 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2764 if (ret != X86EMUL_CONTINUE)
2765 return ret;
7b105ca2 2766 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2767 if (ret != X86EMUL_CONTINUE)
2768 return ret;
7b105ca2 2769 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2770 if (ret != X86EMUL_CONTINUE)
2771 return ret;
7b105ca2 2772 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2773 if (ret != X86EMUL_CONTINUE)
2774 return ret;
7b105ca2 2775 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2776 if (ret != X86EMUL_CONTINUE)
2777 return ret;
7b105ca2 2778 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2779 if (ret != X86EMUL_CONTINUE)
2780 return ret;
7b105ca2 2781 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2782 if (ret != X86EMUL_CONTINUE)
2783 return ret;
2784
2785 return X86EMUL_CONTINUE;
2786}
2787
2788static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2789 u16 tss_selector, u16 old_tss_sel,
2790 ulong old_tss_base, struct desc_struct *new_desc)
2791{
0225fb50 2792 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2793 struct tss_segment_32 tss_seg;
2794 int ret;
bcc55cba 2795 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2796
0f65dd70 2797 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2798 &ctxt->exception);
db297e3d 2799 if (ret != X86EMUL_CONTINUE)
38ba30ba 2800 /* FIXME: need to provide precise fault address */
38ba30ba 2801 return ret;
38ba30ba 2802
7b105ca2 2803 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2804
0f65dd70 2805 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2806 &ctxt->exception);
db297e3d 2807 if (ret != X86EMUL_CONTINUE)
38ba30ba 2808 /* FIXME: need to provide precise fault address */
38ba30ba 2809 return ret;
38ba30ba 2810
0f65dd70 2811 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2812 &ctxt->exception);
db297e3d 2813 if (ret != X86EMUL_CONTINUE)
38ba30ba 2814 /* FIXME: need to provide precise fault address */
38ba30ba 2815 return ret;
38ba30ba
GN		 2816
2817 if (old_tss_sel != 0xffff) {
2818 tss_seg.prev_task_link = old_tss_sel;
2819
0f65dd70 2820 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2821 &tss_seg.prev_task_link,
2822 sizeof tss_seg.prev_task_link,
0f65dd70 2823 &ctxt->exception);
db297e3d 2824 if (ret != X86EMUL_CONTINUE)
38ba30ba 2825 /* FIXME: need to provide precise fault address */
38ba30ba 2826 return ret;
38ba30ba
GN		 2827 }
2828
7b105ca2 2829 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2830}
2831
2832static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2833 u16 tss_selector, int idt_index, int reason,
e269fb21 2834 bool has_error_code, u32 error_code)
38ba30ba 2835{
0225fb50 2836 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2837 struct desc_struct curr_tss_desc, next_tss_desc;
2838 int ret;
1aa36616 2839 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2840 ulong old_tss_base =
4bff1e86 2841 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2842 u32 desc_limit;
e919464b 2843 ulong desc_addr;
38ba30ba
GN		 2844
2845 /* FIXME: old_tss_base == ~0 ? */
2846
e919464b 2847 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2848 if (ret != X86EMUL_CONTINUE)
2849 return ret;
e919464b 2850 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2851 if (ret != X86EMUL_CONTINUE)
2852 return ret;
2853
2854 /* FIXME: check that next_tss_desc is tss */
2855
7f3d35fd
KW		 2856 /*
2857 * Check privileges. The three cases are task switch caused by...
2858 *
2859 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2860 * 2. Exception/IRQ/iret: No check is performed
fc058680 2861 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2862 */
2863 if (reason == TASK_SWITCH_GATE) {
2864 if (idt_index != -1) {
2865 /* Software interrupts */
2866 struct desc_struct task_gate_desc;
2867 int dpl;
2868
2869 ret = read_interrupt_descriptor(ctxt, idt_index,
2870 &task_gate_desc);
2871 if (ret != X86EMUL_CONTINUE)
2872 return ret;
2873
2874 dpl = task_gate_desc.dpl;
2875 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2876 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2877 }
2878 } else if (reason != TASK_SWITCH_IRET) {
2879 int dpl = next_tss_desc.dpl;
2880 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2881 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2882 }
2883
7f3d35fd 2884
ceffb459
GN		 2885 desc_limit = desc_limit_scaled(&next_tss_desc);
2886 if (!next_tss_desc.p ||
2887 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2888 desc_limit < 0x2b)) {
54b8486f 2889 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2890 return X86EMUL_PROPAGATE_FAULT;
2891 }
2892
2893 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2894 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2895 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2896 }
2897
2898 if (reason == TASK_SWITCH_IRET)
2899 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2900
2901 /* set back link to prev task only if NT bit is set in eflags
fc058680 2902 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2903 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2904 old_tss_sel = 0xffff;
2905
2906 if (next_tss_desc.type & 8)
7b105ca2 2907 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2908 old_tss_base, &next_tss_desc);
2909 else
7b105ca2 2910 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2911 old_tss_base, &next_tss_desc);
0760d448
JK		 2912 if (ret != X86EMUL_CONTINUE)
2913 return ret;
38ba30ba
GN		 2914
2915 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2916 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2917
2918 if (reason != TASK_SWITCH_IRET) {
2919 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2920 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2921 }
2922
717746e3 2923 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2924 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2925
e269fb21 2926 if (has_error_code) {
9dac77fa
AK		 2927 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2928 ctxt->lock_prefix = 0;
2929 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2930 ret = em_push(ctxt);
e269fb21
JK		 2931 }
2932
38ba30ba
GN		 2933 return ret;
2934}
2935
2936int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2937 u16 tss_selector, int idt_index, int reason,
e269fb21 2938 bool has_error_code, u32 error_code)
38ba30ba 2939{
38ba30ba
GN		 2940 int rc;
2941
dd856efa 2942 invalidate_registers(ctxt);
9dac77fa
AK		 2943 ctxt->_eip = ctxt->eip;
2944 ctxt->dst.type = OP_NONE;
38ba30ba 2945
7f3d35fd 2946 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2947 has_error_code, error_code);
38ba30ba 2948
dd856efa 2949 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2950 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2951 writeback_registers(ctxt);
2952 }
38ba30ba 2953
a0c0ab2f 2954 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2955}
2956
f3bd64c6
GN		 2957static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2958 struct operand *op)
a682e354 2959{
b3356bf0 2960 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2961
dd856efa
AK		 2962 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2963 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2964}
2965
7af04fc0
AK		 2966static int em_das(struct x86_emulate_ctxt *ctxt)
2967{
7af04fc0
AK		 2968 u8 al, old_al;
2969 bool af, cf, old_cf;
2970
2971 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2972 al = ctxt->dst.val;
7af04fc0
AK		 2973
2974 old_al = al;
2975 old_cf = cf;
2976 cf = false;
2977 af = ctxt->eflags & X86_EFLAGS_AF;
2978 if ((al & 0x0f) > 9 || af) {
2979 al -= 6;
2980 cf = old_cf | (al >= 250);
2981 af = true;
2982 } else {
2983 af = false;
2984 }
2985 if (old_al > 0x99 || old_cf) {
2986 al -= 0x60;
2987 cf = true;
2988 }
2989
9dac77fa 2990 ctxt->dst.val = al;
7af04fc0 2991 /* Set PF, ZF, SF */
9dac77fa
AK		 2992 ctxt->src.type = OP_IMM;
2993 ctxt->src.val = 0;
2994 ctxt->src.bytes = 1;
158de57f 2995 fastop(ctxt, em_or);
7af04fc0
AK		 2996 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2997 if (cf)
2998 ctxt->eflags |= X86_EFLAGS_CF;
2999 if (af)
3000 ctxt->eflags |= X86_EFLAGS_AF;
3001 return X86EMUL_CONTINUE;
3002}
3003
a035d5c6
PB		 3004static int em_aam(struct x86_emulate_ctxt *ctxt)
3005{
3006 u8 al, ah;
3007
3008 if (ctxt->src.val == 0)
3009 return emulate_de(ctxt);
3010
3011 al = ctxt->dst.val & 0xff;
3012 ah = al / ctxt->src.val;
3013 al %= ctxt->src.val;
3014
3015 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3016
3017 /* Set PF, ZF, SF */
3018 ctxt->src.type = OP_IMM;
3019 ctxt->src.val = 0;
3020 ctxt->src.bytes = 1;
3021 fastop(ctxt, em_or);
3022
3023 return X86EMUL_CONTINUE;
3024}
3025
7f662273
GN		 3026static int em_aad(struct x86_emulate_ctxt *ctxt)
3027{
3028 u8 al = ctxt->dst.val & 0xff;
3029 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3030
3031 al = (al + (ah * ctxt->src.val)) & 0xff;
3032
3033 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3034
f583c29b
GN		 3035 /* Set PF, ZF, SF */
3036 ctxt->src.type = OP_IMM;
3037 ctxt->src.val = 0;
3038 ctxt->src.bytes = 1;
3039 fastop(ctxt, em_or);
7f662273
GN		 3040
3041 return X86EMUL_CONTINUE;
3042}
3043
d4ddafcd
TY		 3044static int em_call(struct x86_emulate_ctxt *ctxt)
3045{
3046 long rel = ctxt->src.val;
3047
3048 ctxt->src.val = (unsigned long)ctxt->_eip;
3049 jmp_rel(ctxt, rel);
3050 return em_push(ctxt);
3051}
3052
0ef753b8
AK		 3053static int em_call_far(struct x86_emulate_ctxt *ctxt)
3054{
0ef753b8
AK		 3055 u16 sel, old_cs;
3056 ulong old_eip;
3057 int rc;
3058
1aa36616 3059 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3060 old_eip = ctxt->_eip;
0ef753b8 3061
9dac77fa 3062 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3063 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3064 return X86EMUL_CONTINUE;
3065
9dac77fa
AK		 3066 ctxt->_eip = 0;
3067 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3068
9dac77fa 3069 ctxt->src.val = old_cs;
4487b3b4 3070 rc = em_push(ctxt);
0ef753b8
AK		 3071 if (rc != X86EMUL_CONTINUE)
3072 return rc;
3073
9dac77fa 3074 ctxt->src.val = old_eip;
4487b3b4 3075 return em_push(ctxt);
0ef753b8
AK		 3076}
3077
40ece7c7
AK		 3078static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3079{
40ece7c7
AK		 3080 int rc;
3081
9dac77fa
AK		 3082 ctxt->dst.type = OP_REG;
3083 ctxt->dst.addr.reg = &ctxt->_eip;
3084 ctxt->dst.bytes = ctxt->op_bytes;
3085 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3086 if (rc != X86EMUL_CONTINUE)
3087 return rc;
5ad105e5 3088 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3089 return X86EMUL_CONTINUE;
3090}
3091
e4f973ae
TY		 3092static int em_xchg(struct x86_emulate_ctxt *ctxt)
3093{
e4f973ae 3094 /* Write back the register source. */
9dac77fa
AK		 3095 ctxt->src.val = ctxt->dst.val;
3096 write_register_operand(&ctxt->src);
e4f973ae
TY		 3097
3098 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3099 ctxt->dst.val = ctxt->src.orig_val;
3100 ctxt->lock_prefix = 1;
e4f973ae
TY		 3101 return X86EMUL_CONTINUE;
3102}
3103
5c82aa29
AK		 3104static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3105{
9dac77fa 3106 ctxt->dst.val = ctxt->src2.val;
4d758349 3107 return fastop(ctxt, em_imul);
5c82aa29
AK		 3108}
3109
61429142
AK		 3110static int em_cwd(struct x86_emulate_ctxt *ctxt)
3111{
9dac77fa
AK		 3112 ctxt->dst.type = OP_REG;
3113 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3114 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3115 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3116
3117 return X86EMUL_CONTINUE;
3118}
3119
48bb5d3c
AK		 3120static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3121{
48bb5d3c
AK		 3122 u64 tsc = 0;
3123
717746e3 3124 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3125 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3126 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3127 return X86EMUL_CONTINUE;
3128}
3129
222d21aa
AK		 3130static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3131{
3132 u64 pmc;
3133
dd856efa 3134 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3135 return emulate_gp(ctxt, 0);
dd856efa
AK		 3136 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3137 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3138 return X86EMUL_CONTINUE;
3139}
3140
b9eac5f4
AK		 3141static int em_mov(struct x86_emulate_ctxt *ctxt)
3142{
49597d81 3143 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3144 return X86EMUL_CONTINUE;
3145}
3146
bc00f8d2
TY		 3147static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3148{
3149 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3150 return emulate_gp(ctxt, 0);
3151
3152 /* Disable writeback. */
3153 ctxt->dst.type = OP_NONE;
3154 return X86EMUL_CONTINUE;
3155}
3156
3157static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3158{
3159 unsigned long val;
3160
3161 if (ctxt->mode == X86EMUL_MODE_PROT64)
3162 val = ctxt->src.val & ~0ULL;
3163 else
3164 val = ctxt->src.val & ~0U;
3165
3166 /* #UD condition is already handled. */
3167 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3168 return emulate_gp(ctxt, 0);
3169
3170 /* Disable writeback. */
3171 ctxt->dst.type = OP_NONE;
3172 return X86EMUL_CONTINUE;
3173}
3174
e1e210b0
TY		 3175static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3176{
3177 u64 msr_data;
3178
dd856efa
AK		 3179 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3180 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3181 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3182 return emulate_gp(ctxt, 0);
3183
3184 return X86EMUL_CONTINUE;
3185}
3186
3187static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3188{
3189 u64 msr_data;
3190
dd856efa 3191 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3192 return emulate_gp(ctxt, 0);
3193
dd856efa
AK		 3194 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3195 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3196 return X86EMUL_CONTINUE;
3197}
3198
1bd5f469
TY		 3199static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3200{
9dac77fa 3201 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3202 return emulate_ud(ctxt);
3203
9dac77fa 3204 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3205 return X86EMUL_CONTINUE;
3206}
3207
3208static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3209{
9dac77fa 3210 u16 sel = ctxt->src.val;
1bd5f469 3211
9dac77fa 3212 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3213 return emulate_ud(ctxt);
3214
9dac77fa 3215 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3216 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3217
3218 /* Disable writeback. */
9dac77fa
AK		 3219 ctxt->dst.type = OP_NONE;
3220 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3221}
3222
a14e579f
AK		 3223static int em_lldt(struct x86_emulate_ctxt *ctxt)
3224{
3225 u16 sel = ctxt->src.val;
3226
3227 /* Disable writeback. */
3228 ctxt->dst.type = OP_NONE;
3229 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3230}
3231
80890006
AK		 3232static int em_ltr(struct x86_emulate_ctxt *ctxt)
3233{
3234 u16 sel = ctxt->src.val;
3235
3236 /* Disable writeback. */
3237 ctxt->dst.type = OP_NONE;
3238 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3239}
3240
38503911
AK		 3241static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3242{
9fa088f4
AK		 3243 int rc;
3244 ulong linear;
3245
9dac77fa 3246 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3247 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3248 ctxt->ops->invlpg(ctxt, linear);
38503911 3249 /* Disable writeback. */
9dac77fa 3250 ctxt->dst.type = OP_NONE;
38503911
AK		 3251 return X86EMUL_CONTINUE;
3252}
3253
2d04a05b
AK		 3254static int em_clts(struct x86_emulate_ctxt *ctxt)
3255{
3256 ulong cr0;
3257
3258 cr0 = ctxt->ops->get_cr(ctxt, 0);
3259 cr0 &= ~X86_CR0_TS;
3260 ctxt->ops->set_cr(ctxt, 0, cr0);
3261 return X86EMUL_CONTINUE;
3262}
3263
26d05cc7
AK		 3264static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3265{
26d05cc7
AK		 3266 int rc;
3267
9dac77fa 3268 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3269 return X86EMUL_UNHANDLEABLE;
3270
3271 rc = ctxt->ops->fix_hypercall(ctxt);
3272 if (rc != X86EMUL_CONTINUE)
3273 return rc;
3274
3275 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3276 ctxt->_eip = ctxt->eip;
26d05cc7 3277 /* Disable writeback. */
9dac77fa 3278 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3279 return X86EMUL_CONTINUE;
3280}
3281
96051572
AK		 3282static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3283 void (*get)(struct x86_emulate_ctxt *ctxt,
3284 struct desc_ptr *ptr))
3285{
3286 struct desc_ptr desc_ptr;
3287
3288 if (ctxt->mode == X86EMUL_MODE_PROT64)
3289 ctxt->op_bytes = 8;
3290 get(ctxt, &desc_ptr);
3291 if (ctxt->op_bytes == 2) {
3292 ctxt->op_bytes = 4;
3293 desc_ptr.address &= 0x00ffffff;
3294 }
3295 /* Disable writeback. */
3296 ctxt->dst.type = OP_NONE;
3297 return segmented_write(ctxt, ctxt->dst.addr.mem,
3298 &desc_ptr, 2 + ctxt->op_bytes);
3299}
3300
3301static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3302{
3303 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3304}
3305
3306static int em_sidt(struct x86_emulate_ctxt *ctxt)
3307{
3308 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3309}
3310
26d05cc7
AK		 3311static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3312{
26d05cc7
AK		 3313 struct desc_ptr desc_ptr;
3314 int rc;
3315
510425ff
AK		 3316 if (ctxt->mode == X86EMUL_MODE_PROT64)
3317 ctxt->op_bytes = 8;
9dac77fa 3318 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3319 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3320 ctxt->op_bytes);
26d05cc7
AK		 3321 if (rc != X86EMUL_CONTINUE)
3322 return rc;
3323 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3324 /* Disable writeback. */
9dac77fa 3325 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3326 return X86EMUL_CONTINUE;
3327}
3328
5ef39c71 3329static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3330{
26d05cc7
AK		 3331 int rc;
3332
5ef39c71
AK		 3333 rc = ctxt->ops->fix_hypercall(ctxt);
3334
26d05cc7 3335 /* Disable writeback. */
9dac77fa 3336 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3337 return rc;
3338}
3339
3340static int em_lidt(struct x86_emulate_ctxt *ctxt)
3341{
26d05cc7
AK		 3342 struct desc_ptr desc_ptr;
3343 int rc;
3344
510425ff
AK		 3345 if (ctxt->mode == X86EMUL_MODE_PROT64)
3346 ctxt->op_bytes = 8;
9dac77fa 3347 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3348 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3349 ctxt->op_bytes);
26d05cc7
AK		 3350 if (rc != X86EMUL_CONTINUE)
3351 return rc;
3352 ctxt->ops->set_idt(ctxt, &desc_ptr);
3353 /* Disable writeback. */
9dac77fa 3354 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3355 return X86EMUL_CONTINUE;
3356}
3357
3358static int em_smsw(struct x86_emulate_ctxt *ctxt)
3359{
9dac77fa
AK		 3360 ctxt->dst.bytes = 2;
3361 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3362 return X86EMUL_CONTINUE;
3363}
3364
3365static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3366{
26d05cc7 3367 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3368 | (ctxt->src.val & 0x0f));
3369 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3370 return X86EMUL_CONTINUE;
3371}
3372
d06e03ad
TY		 3373static int em_loop(struct x86_emulate_ctxt *ctxt)
3374{
dd856efa
AK		 3375 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3376 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3377 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3378 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3379
3380 return X86EMUL_CONTINUE;
3381}
3382
3383static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3384{
dd856efa 3385 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3386 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3387
3388 return X86EMUL_CONTINUE;
3389}
3390
d7841a4b
TY		 3391static int em_in(struct x86_emulate_ctxt *ctxt)
3392{
3393 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3394 &ctxt->dst.val))
3395 return X86EMUL_IO_NEEDED;
3396
3397 return X86EMUL_CONTINUE;
3398}
3399
3400static int em_out(struct x86_emulate_ctxt *ctxt)
3401{
3402 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3403 &ctxt->src.val, 1);
3404 /* Disable writeback. */
3405 ctxt->dst.type = OP_NONE;
3406 return X86EMUL_CONTINUE;
3407}
3408
f411e6cd
TY		 3409static int em_cli(struct x86_emulate_ctxt *ctxt)
3410{
3411 if (emulator_bad_iopl(ctxt))
3412 return emulate_gp(ctxt, 0);
3413
3414 ctxt->eflags &= ~X86_EFLAGS_IF;
3415 return X86EMUL_CONTINUE;
3416}
3417
3418static int em_sti(struct x86_emulate_ctxt *ctxt)
3419{
3420 if (emulator_bad_iopl(ctxt))
3421 return emulate_gp(ctxt, 0);
3422
3423 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3424 ctxt->eflags |= X86_EFLAGS_IF;
3425 return X86EMUL_CONTINUE;
3426}
3427
6d6eede4
AK		 3428static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3429{
3430 u32 eax, ebx, ecx, edx;
3431
dd856efa
AK		 3432 eax = reg_read(ctxt, VCPU_REGS_RAX);
3433 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3434 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3435 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3436 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3437 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3438 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3439 return X86EMUL_CONTINUE;
3440}
3441
2dd7caa0
AK		 3442static int em_lahf(struct x86_emulate_ctxt *ctxt)
3443{
dd856efa
AK		 3444 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3445 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3446 return X86EMUL_CONTINUE;
3447}
3448
9299836e
AK		 3449static int em_bswap(struct x86_emulate_ctxt *ctxt)
3450{
3451 switch (ctxt->op_bytes) {
3452#ifdef CONFIG_X86_64
3453 case 8:
3454 asm("bswap %0" : "+r"(ctxt->dst.val));
3455 break;
3456#endif
3457 default:
3458 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3459 break;
3460 }
3461 return X86EMUL_CONTINUE;
3462}
3463
cfec82cb
JR		 3464static bool valid_cr(int nr)
3465{
3466 switch (nr) {
3467 case 0:
3468 case 2 ... 4:
3469 case 8:
3470 return true;
3471 default:
3472 return false;
3473 }
3474}
3475
3476static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3477{
9dac77fa 3478 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3479 return emulate_ud(ctxt);
3480
3481 return X86EMUL_CONTINUE;
3482}
3483
3484static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3485{
9dac77fa
AK		 3486 u64 new_val = ctxt->src.val64;
3487 int cr = ctxt->modrm_reg;
c2ad2bb3 3488 u64 efer = 0;
cfec82cb
JR		 3489
3490 static u64 cr_reserved_bits[] = {
3491 0xffffffff00000000ULL,
3492 0, 0, 0, /* CR3 checked later */
3493 CR4_RESERVED_BITS,
3494 0, 0, 0,
3495 CR8_RESERVED_BITS,
3496 };
3497
3498 if (!valid_cr(cr))
3499 return emulate_ud(ctxt);
3500
3501 if (new_val & cr_reserved_bits[cr])
3502 return emulate_gp(ctxt, 0);
3503
3504 switch (cr) {
3505 case 0: {
c2ad2bb3 3506 u64 cr4;
cfec82cb
JR		 3507 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3508 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3509 return emulate_gp(ctxt, 0);
3510
717746e3
AK		 3511 cr4 = ctxt->ops->get_cr(ctxt, 4);
3512 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3513
3514 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3515 !(cr4 & X86_CR4_PAE))
3516 return emulate_gp(ctxt, 0);
3517
3518 break;
3519 }
3520 case 3: {
3521 u64 rsvd = 0;
3522
c2ad2bb3
AK		 3523 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3524 if (efer & EFER_LMA)
cfec82cb 3525 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3526 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3527 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3528 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3529 rsvd = CR3_NONPAE_RESERVED_BITS;
3530
3531 if (new_val & rsvd)
3532 return emulate_gp(ctxt, 0);
3533
3534 break;
3535 }
3536 case 4: {
717746e3 3537 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3538
3539 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3540 return emulate_gp(ctxt, 0);
3541
3542 break;
3543 }
3544 }
3545
3546 return X86EMUL_CONTINUE;
3547}
3548
3b88e41a
JR		 3549static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3550{
3551 unsigned long dr7;
3552
717746e3 3553 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3554
3555 /* Check if DR7.Global_Enable is set */
3556 return dr7 & (1 << 13);
3557}
3558
3559static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3560{
9dac77fa 3561 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3562 u64 cr4;
3563
3564 if (dr > 7)
3565 return emulate_ud(ctxt);
3566
717746e3 3567 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3568 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3569 return emulate_ud(ctxt);
3570
3571 if (check_dr7_gd(ctxt))
3572 return emulate_db(ctxt);
3573
3574 return X86EMUL_CONTINUE;
3575}
3576
3577static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3578{
9dac77fa
AK		 3579 u64 new_val = ctxt->src.val64;
3580 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3581
3582 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3583 return emulate_gp(ctxt, 0);
3584
3585 return check_dr_read(ctxt);
3586}
3587
01de8b09
JR		 3588static int check_svme(struct x86_emulate_ctxt *ctxt)
3589{
3590 u64 efer;
3591
717746e3 3592 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3593
3594 if (!(efer & EFER_SVME))
3595 return emulate_ud(ctxt);
3596
3597 return X86EMUL_CONTINUE;
3598}
3599
3600static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3601{
dd856efa 3602 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3603
3604 /* Valid physical address? */
d4224449 3605 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3606 return emulate_gp(ctxt, 0);
3607
3608 return check_svme(ctxt);
3609}
3610
d7eb8203
JR		 3611static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3612{
717746e3 3613 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3614
717746e3 3615 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3616 return emulate_ud(ctxt);
3617
3618 return X86EMUL_CONTINUE;
3619}
3620
8061252e
JR		 3621static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3622{
717746e3 3623 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3624 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3625
717746e3 3626 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3627 (rcx > 3))
3628 return emulate_gp(ctxt, 0);
3629
3630 return X86EMUL_CONTINUE;
3631}
3632
f6511935
JR		 3633static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3634{
9dac77fa
AK		 3635 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3636 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3637 return emulate_gp(ctxt, 0);
3638
3639 return X86EMUL_CONTINUE;
3640}
3641
3642static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3643{
9dac77fa
AK		 3644 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3645 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3646 return emulate_gp(ctxt, 0);
3647
3648 return X86EMUL_CONTINUE;
3649}
3650
73fba5f4 3651#define D(_y) { .flags = (_y) }
c4f035c6 3652#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3653#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3654 .check_perm = (_p) }
0b789eee 3655#define N D(NotImpl)
01de8b09 3656#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3657#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3658#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3659#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3660#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3661#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3662#define II(_f, _e, _i) \
3663 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3664#define IIP(_f, _e, _i, _p) \
3665 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3666 .check_perm = (_p) }
aa97bb48 3667#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3668
8d8f4e9f 3669#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3670#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3671#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3672#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3673#define I2bvIP(_f, _e, _i, _p) \
3674 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3675
fb864fbc
AK		 3676#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3677 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3678 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3679
fd0a0d82 3680static const struct opcode group7_rm1[] = {
1c2545be
TY		 3681 DI(SrcNone | Priv, monitor),
3682 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3683 N, N, N, N, N, N,
3684};
3685
fd0a0d82 3686static const struct opcode group7_rm3[] = {
1c2545be
TY		 3687 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3688 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3689 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3690 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3691 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3692 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3693 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3694 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3695};
6230f7fc 3696
fd0a0d82 3697static const struct opcode group7_rm7[] = {
d7eb8203 3698 N,
1c2545be 3699 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3700 N, N, N, N, N, N,
3701};
d67fc27a 3702
fd0a0d82 3703static const struct opcode group1[] = {
fb864fbc
AK		 3704 F(Lock, em_add),
3705 F(Lock | PageTable, em_or),
3706 F(Lock, em_adc),
3707 F(Lock, em_sbb),
3708 F(Lock | PageTable, em_and),
3709 F(Lock, em_sub),
3710 F(Lock, em_xor),
3711 F(NoWrite, em_cmp),
73fba5f4
AK		 3712};
3713
fd0a0d82 3714static const struct opcode group1A[] = {
1c2545be 3715 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3716};
3717
007a3b54
AK		 3718static const struct opcode group2[] = {
3719 F(DstMem | ModRM, em_rol),
3720 F(DstMem | ModRM, em_ror),
3721 F(DstMem | ModRM, em_rcl),
3722 F(DstMem | ModRM, em_rcr),
3723 F(DstMem | ModRM, em_shl),
3724 F(DstMem | ModRM, em_shr),
3725 F(DstMem | ModRM, em_shl),
3726 F(DstMem | ModRM, em_sar),
3727};
3728
fd0a0d82 3729static const struct opcode group3[] = {
fb864fbc
AK		 3730 F(DstMem | SrcImm | NoWrite, em_test),
3731 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3732 F(DstMem | SrcNone | Lock, em_not),
3733 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3734 I(SrcMem, em_mul_ex),
3735 I(SrcMem, em_imul_ex),
3736 I(SrcMem, em_div_ex),
3737 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3738};
3739
fd0a0d82 3740static const struct opcode group4[] = {
95413dc4
AK		 3741 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3742 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3743 N, N, N, N, N, N,
3744};
3745
fd0a0d82 3746static const struct opcode group5[] = {
95413dc4
AK		 3747 F(DstMem | SrcNone | Lock, em_inc),
3748 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3749 I(SrcMem | Stack, em_grp45),
3750 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3751 I(SrcMem | Stack, em_grp45),
3752 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3753 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3754};
3755
fd0a0d82 3756static const struct opcode group6[] = {
1c2545be
TY		 3757 DI(Prot, sldt),
3758 DI(Prot, str),
a14e579f 3759 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3760 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3761 N, N, N, N,
3762};
3763
fd0a0d82 3764static const struct group_dual group7 = { {
96051572
AK		 3765 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3766 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3767 II(SrcMem | Priv, em_lgdt, lgdt),
3768 II(SrcMem | Priv, em_lidt, lidt),
3769 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3770 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3771 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3772}, {
1c2545be 3773 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3774 EXT(0, group7_rm1),
01de8b09 3775 N, EXT(0, group7_rm3),
1c2545be
TY		 3776 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3777 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3778 EXT(0, group7_rm7),
73fba5f4
AK		 3779} };
3780
fd0a0d82 3781static const struct opcode group8[] = {
73fba5f4 3782 N, N, N, N,
11c363ba
AK		 3783 F(DstMem | SrcImmByte | NoWrite, em_bt),
3784 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3785 F(DstMem | SrcImmByte | Lock, em_btr),
3786 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3787};
3788
fd0a0d82 3789static const struct group_dual group9 = { {
1c2545be 3790 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3791}, {
3792 N, N, N, N, N, N, N, N,
3793} };
3794
fd0a0d82 3795static const struct opcode group11[] = {
1c2545be 3796 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3797 X7(D(Undefined)),
a4d4a7c1
AK		 3798};
3799
fd0a0d82 3800static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3801 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3802};
3803
fd0a0d82 3804static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3805 I(0, em_mov), N, N, N,
3806};
3807
045a282c
GN		 3808static const struct escape escape_d9 = { {
3809 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3810}, {
3811 /* 0xC0 - 0xC7 */
3812 N, N, N, N, N, N, N, N,
3813 /* 0xC8 - 0xCF */
3814 N, N, N, N, N, N, N, N,
3815 /* 0xD0 - 0xC7 */
3816 N, N, N, N, N, N, N, N,
3817 /* 0xD8 - 0xDF */
3818 N, N, N, N, N, N, N, N,
3819 /* 0xE0 - 0xE7 */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xE8 - 0xEF */
3822 N, N, N, N, N, N, N, N,
3823 /* 0xF0 - 0xF7 */
3824 N, N, N, N, N, N, N, N,
3825 /* 0xF8 - 0xFF */
3826 N, N, N, N, N, N, N, N,
3827} };
3828
3829static const struct escape escape_db = { {
3830 N, N, N, N, N, N, N, N,
3831}, {
3832 /* 0xC0 - 0xC7 */
3833 N, N, N, N, N, N, N, N,
3834 /* 0xC8 - 0xCF */
3835 N, N, N, N, N, N, N, N,
3836 /* 0xD0 - 0xC7 */
3837 N, N, N, N, N, N, N, N,
3838 /* 0xD8 - 0xDF */
3839 N, N, N, N, N, N, N, N,
3840 /* 0xE0 - 0xE7 */
3841 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3842 /* 0xE8 - 0xEF */
3843 N, N, N, N, N, N, N, N,
3844 /* 0xF0 - 0xF7 */
3845 N, N, N, N, N, N, N, N,
3846 /* 0xF8 - 0xFF */
3847 N, N, N, N, N, N, N, N,
3848} };
3849
3850static const struct escape escape_dd = { {
3851 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3852}, {
3853 /* 0xC0 - 0xC7 */
3854 N, N, N, N, N, N, N, N,
3855 /* 0xC8 - 0xCF */
3856 N, N, N, N, N, N, N, N,
3857 /* 0xD0 - 0xC7 */
3858 N, N, N, N, N, N, N, N,
3859 /* 0xD8 - 0xDF */
3860 N, N, N, N, N, N, N, N,
3861 /* 0xE0 - 0xE7 */
3862 N, N, N, N, N, N, N, N,
3863 /* 0xE8 - 0xEF */
3864 N, N, N, N, N, N, N, N,
3865 /* 0xF0 - 0xF7 */
3866 N, N, N, N, N, N, N, N,
3867 /* 0xF8 - 0xFF */
3868 N, N, N, N, N, N, N, N,
3869} };
3870
fd0a0d82 3871static const struct opcode opcode_table[256] = {
73fba5f4 3872 /* 0x00 - 0x07 */
fb864fbc 3873 F6ALU(Lock, em_add),
1cd196ea
AK		 3874 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3875 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3876 /* 0x08 - 0x0F */
fb864fbc 3877 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3878 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3879 N,
73fba5f4 3880 /* 0x10 - 0x17 */
fb864fbc 3881 F6ALU(Lock, em_adc),
1cd196ea
AK		 3882 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3883 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3884 /* 0x18 - 0x1F */
fb864fbc 3885 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3886 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3887 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3888 /* 0x20 - 0x27 */
fb864fbc 3889 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3890 /* 0x28 - 0x2F */
fb864fbc 3891 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3892 /* 0x30 - 0x37 */
fb864fbc 3893 F6ALU(Lock, em_xor), N, N,
73fba5f4 3894 /* 0x38 - 0x3F */
fb864fbc 3895 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3896 /* 0x40 - 0x4F */
95413dc4 3897 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3898 /* 0x50 - 0x57 */
63540382 3899 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3900 /* 0x58 - 0x5F */
c54fe504 3901 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3902 /* 0x60 - 0x67 */
b96a7fad
TY		 3903 I(ImplicitOps | Stack | No64, em_pusha),
3904 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3905 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3906 N, N, N, N,
3907 /* 0x68 - 0x6F */
d46164db
AK		 3908 I(SrcImm | Mov | Stack, em_push),
3909 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3910 I(SrcImmByte | Mov | Stack, em_push),
3911 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3912 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3913 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3914 /* 0x70 - 0x7F */
3915 X16(D(SrcImmByte)),
3916 /* 0x80 - 0x87 */
1c2545be
TY		 3917 G(ByteOp | DstMem | SrcImm, group1),
3918 G(DstMem | SrcImm, group1),
3919 G(ByteOp | DstMem | SrcImm | No64, group1),
3920 G(DstMem | SrcImmByte, group1),
fb864fbc 3921 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3922 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3923 /* 0x88 - 0x8F */
d5ae7ce8 3924 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3925 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3926 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3927 D(ModRM | SrcMem | NoAccess | DstReg),
3928 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3929 G(0, group1A),
73fba5f4 3930 /* 0x90 - 0x97 */
bf608f88 3931 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3932 /* 0x98 - 0x9F */
61429142 3933 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3934 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3935 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3936 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3937 /* 0xA0 - 0xA7 */
b9eac5f4 3938 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3939 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3940 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3941 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3942 /* 0xA8 - 0xAF */
fb864fbc 3943 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3944 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3945 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3946 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3947 /* 0xB0 - 0xB7 */
b9eac5f4 3948 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3949 /* 0xB8 - 0xBF */
5e2c6883 3950 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3951 /* 0xC0 - 0xC7 */
007a3b54 3952 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3953 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3954 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3955 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3956 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3957 G(ByteOp, group11), G(0, group11),
73fba5f4 3958 /* 0xC8 - 0xCF */
612e89f0
AK		 3959 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3960 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3961 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3962 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3963 /* 0xD0 - 0xD7 */
007a3b54
AK		 3964 G(Src2One | ByteOp, group2), G(Src2One, group2),
3965 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3966 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3967 I(DstAcc | SrcImmUByte | No64, em_aad),
3968 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3969 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3970 /* 0xD8 - 0xDF */
045a282c 3971 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3972 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3973 X3(I(SrcImmByte, em_loop)),
3974 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3975 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3976 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3977 /* 0xE8 - 0xEF */
d4ddafcd 3978 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3979 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3980 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3981 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3982 /* 0xF0 - 0xF7 */
bf608f88 3983 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3984 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3985 G(ByteOp, group3), G(0, group3),
73fba5f4 3986 /* 0xF8 - 0xFF */
f411e6cd
TY		 3987 D(ImplicitOps), D(ImplicitOps),
3988 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3989 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3990};
3991
fd0a0d82 3992static const struct opcode twobyte_table[256] = {
73fba5f4 3993 /* 0x00 - 0x0F */
dee6bb70 3994 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3995 N, I(ImplicitOps | VendorSpecific, em_syscall),
3996 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3997 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3998 N, D(ImplicitOps | ModRM), N, N,
3999 /* 0x10 - 0x1F */
4000 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
4001 /* 0x20 - 0x2F */
cfec82cb 4002 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 4003 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4004 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4005 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4006 N, N, N, N,
3e114eb4
AK		 4007 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4008 N, N, N, N,
73fba5f4 4009 /* 0x30 - 0x3F */
e1e210b0 4010 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4011 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4012 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4013 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4014 I(ImplicitOps | VendorSpecific, em_sysenter),
4015 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4016 N, N,
73fba5f4
AK		 4017 N, N, N, N, N, N, N, N,
4018 /* 0x40 - 0x4F */
4019 X16(D(DstReg | SrcMem | ModRM | Mov)),
4020 /* 0x50 - 0x5F */
4021 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4022 /* 0x60 - 0x6F */
aa97bb48
AK		 4023 N, N, N, N,
4024 N, N, N, N,
4025 N, N, N, N,
4026 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4027 /* 0x70 - 0x7F */
aa97bb48
AK		 4028 N, N, N, N,
4029 N, N, N, N,
4030 N, N, N, N,
4031 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4032 /* 0x80 - 0x8F */
4033 X16(D(SrcImm)),
4034 /* 0x90 - 0x9F */
ee45b58e 4035 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4036 /* 0xA0 - 0xA7 */
1cd196ea 4037 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4038 II(ImplicitOps, em_cpuid, cpuid),
4039 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4040 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4041 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4042 /* 0xA8 - 0xAF */
1cd196ea 4043 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4044 DI(ImplicitOps, rsm),
11c363ba 4045 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4046 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4047 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4048 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4049 /* 0xB0 - 0xB7 */
e940b5c2 4050 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4051 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4052 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4053 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4054 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4055 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4056 /* 0xB8 - 0xBF */
4057 N, N,
ce7faab2 4058 G(BitOp, group8),
11c363ba
AK		 4059 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4060 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4061 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4062 /* 0xC0 - 0xC7 */
739ae406 4063 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4064 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4065 N, N, N, GD(0, &group9),
9299836e
AK		 4066 /* 0xC8 - 0xCF */
4067 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4068 /* 0xD0 - 0xDF */
4069 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4070 /* 0xE0 - 0xEF */
4071 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4072 /* 0xF0 - 0xFF */
4073 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4074};
4075
4076#undef D
4077#undef N
4078#undef G
4079#undef GD
4080#undef I
aa97bb48 4081#undef GP
01de8b09 4082#undef EXT
73fba5f4 4083
8d8f4e9f 4084#undef D2bv
f6511935 4085#undef D2bvIP
8d8f4e9f 4086#undef I2bv
d7841a4b 4087#undef I2bvIP
d67fc27a 4088#undef I6ALU
8d8f4e9f 4089
9dac77fa 4090static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4091{
4092 unsigned size;
4093
9dac77fa 4094 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4095 if (size == 8)
4096 size = 4;
4097 return size;
4098}
4099
4100static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4101 unsigned size, bool sign_extension)
4102{
39f21ee5
AK		 4103 int rc = X86EMUL_CONTINUE;
4104
4105 op->type = OP_IMM;
4106 op->bytes = size;
9dac77fa 4107 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4108 /* NB. Immediates are sign-extended as necessary. */
4109 switch (op->bytes) {
4110 case 1:
e85a1085 4111 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4112 break;
4113 case 2:
e85a1085 4114 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4115 break;
4116 case 4:
e85a1085 4117 op->val = insn_fetch(s32, ctxt);
39f21ee5 4118 break;
5e2c6883
NA		 4119 case 8:
4120 op->val = insn_fetch(s64, ctxt);
4121 break;
39f21ee5
AK		 4122 }
4123 if (!sign_extension) {
4124 switch (op->bytes) {
4125 case 1:
4126 op->val &= 0xff;
4127 break;
4128 case 2:
4129 op->val &= 0xffff;
4130 break;
4131 case 4:
4132 op->val &= 0xffffffff;
4133 break;
4134 }
4135 }
4136done:
4137 return rc;
4138}
4139
a9945549
AK		 4140static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4141 unsigned d)
4142{
4143 int rc = X86EMUL_CONTINUE;
4144
4145 switch (d) {
4146 case OpReg:
2adb5ad9 4147 decode_register_operand(ctxt, op);
a9945549
AK		 4148 break;
4149 case OpImmUByte:
608aabe3 4150 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4151 break;
4152 case OpMem:
41ddf978 4153 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4154 mem_common:
4155 *op = ctxt->memop;
4156 ctxt->memopp = op;
4157 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4158 fetch_bit_operand(ctxt);
4159 op->orig_val = op->val;
4160 break;
41ddf978
AK		 4161 case OpMem64:
4162 ctxt->memop.bytes = 8;
4163 goto mem_common;
a9945549
AK		 4164 case OpAcc:
4165 op->type = OP_REG;
4166 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4167 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4168 fetch_register_operand(op);
4169 op->orig_val = op->val;
4170 break;
4171 case OpDI:
4172 op->type = OP_MEM;
4173 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4174 op->addr.mem.ea =
dd856efa 4175 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4176 op->addr.mem.seg = VCPU_SREG_ES;
4177 op->val = 0;
b3356bf0 4178 op->count = 1;
a9945549
AK		 4179 break;
4180 case OpDX:
4181 op->type = OP_REG;
4182 op->bytes = 2;
dd856efa 4183 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4184 fetch_register_operand(op);
4185 break;
4dd6a57d
AK		 4186 case OpCL:
4187 op->bytes = 1;
dd856efa 4188 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4189 break;
4190 case OpImmByte:
4191 rc = decode_imm(ctxt, op, 1, true);
4192 break;
4193 case OpOne:
4194 op->bytes = 1;
4195 op->val = 1;
4196 break;
4197 case OpImm:
4198 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4199 break;
5e2c6883
NA		 4200 case OpImm64:
4201 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4202 break;
28867cee
AK		 4203 case OpMem8:
4204 ctxt->memop.bytes = 1;
660696d1
GN		 4205 if (ctxt->memop.type == OP_REG) {
4206 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4207 fetch_register_operand(&ctxt->memop);
4208 }
28867cee 4209 goto mem_common;
0fe59128
AK		 4210 case OpMem16:
4211 ctxt->memop.bytes = 2;
4212 goto mem_common;
4213 case OpMem32:
4214 ctxt->memop.bytes = 4;
4215 goto mem_common;
4216 case OpImmU16:
4217 rc = decode_imm(ctxt, op, 2, false);
4218 break;
4219 case OpImmU:
4220 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4221 break;
4222 case OpSI:
4223 op->type = OP_MEM;
4224 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4225 op->addr.mem.ea =
dd856efa 4226 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4227 op->addr.mem.seg = seg_override(ctxt);
4228 op->val = 0;
b3356bf0 4229 op->count = 1;
0fe59128 4230 break;
7fa57952
PB		 4231 case OpXLat:
4232 op->type = OP_MEM;
4233 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4234 op->addr.mem.ea =
4235 register_address(ctxt,
4236 reg_read(ctxt, VCPU_REGS_RBX) +
4237 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4238 op->addr.mem.seg = seg_override(ctxt);
4239 op->val = 0;
4240 break;
0fe59128
AK		 4241 case OpImmFAddr:
4242 op->type = OP_IMM;
4243 op->addr.mem.ea = ctxt->_eip;
4244 op->bytes = ctxt->op_bytes + 2;
4245 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4246 break;
4247 case OpMemFAddr:
4248 ctxt->memop.bytes = ctxt->op_bytes + 2;
4249 goto mem_common;
c191a7a0
AK		 4250 case OpES:
4251 op->val = VCPU_SREG_ES;
4252 break;
4253 case OpCS:
4254 op->val = VCPU_SREG_CS;
4255 break;
4256 case OpSS:
4257 op->val = VCPU_SREG_SS;
4258 break;
4259 case OpDS:
4260 op->val = VCPU_SREG_DS;
4261 break;
4262 case OpFS:
4263 op->val = VCPU_SREG_FS;
4264 break;
4265 case OpGS:
4266 op->val = VCPU_SREG_GS;
4267 break;
a9945549
AK		 4268 case OpImplicit:
4269 /* Special instructions do their own operand decoding. */
4270 default:
4271 op->type = OP_NONE; /* Disable writeback. */
4272 break;
4273 }
4274
4275done:
4276 return rc;
4277}
4278
ef5d75cc 4279int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4280{
dde7e6d1
AK		 4281 int rc = X86EMUL_CONTINUE;
4282 int mode = ctxt->mode;
46561646 4283 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4284 bool op_prefix = false;
46561646 4285 struct opcode opcode;
dde7e6d1 4286
f09ed83e
AK		 4287 ctxt->memop.type = OP_NONE;
4288 ctxt->memopp = NULL;
9dac77fa
AK		 4289 ctxt->_eip = ctxt->eip;
4290 ctxt->fetch.start = ctxt->_eip;
4291 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4292 if (insn_len > 0)
9dac77fa 4293 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4294
4295 switch (mode) {
4296 case X86EMUL_MODE_REAL:
4297 case X86EMUL_MODE_VM86:
4298 case X86EMUL_MODE_PROT16:
4299 def_op_bytes = def_ad_bytes = 2;
4300 break;
4301 case X86EMUL_MODE_PROT32:
4302 def_op_bytes = def_ad_bytes = 4;
4303 break;
4304#ifdef CONFIG_X86_64
4305 case X86EMUL_MODE_PROT64:
4306 def_op_bytes = 4;
4307 def_ad_bytes = 8;
4308 break;
4309#endif
4310 default:
1d2887e2 4311 return EMULATION_FAILED;
dde7e6d1
AK		 4312 }
4313
9dac77fa
AK		 4314 ctxt->op_bytes = def_op_bytes;
4315 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4316
4317 /* Legacy prefixes. */
4318 for (;;) {
e85a1085 4319 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4320 case 0x66: /* operand-size override */
0d7cdee8 4321 op_prefix = true;
dde7e6d1 4322 /* switch between 2/4 bytes */
9dac77fa 4323 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4324 break;
4325 case 0x67: /* address-size override */
4326 if (mode == X86EMUL_MODE_PROT64)
4327 /* switch between 4/8 bytes */
9dac77fa 4328 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4329 else
4330 /* switch between 2/4 bytes */
9dac77fa 4331 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4332 break;
4333 case 0x26: /* ES override */
4334 case 0x2e: /* CS override */
4335 case 0x36: /* SS override */
4336 case 0x3e: /* DS override */
9dac77fa 4337 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4338 break;
4339 case 0x64: /* FS override */
4340 case 0x65: /* GS override */
9dac77fa 4341 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4342 break;
4343 case 0x40 ... 0x4f: /* REX */
4344 if (mode != X86EMUL_MODE_PROT64)
4345 goto done_prefixes;
9dac77fa 4346 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4347 continue;
4348 case 0xf0: /* LOCK */
9dac77fa 4349 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4350 break;
4351 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4352 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4353 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4354 break;
4355 default:
4356 goto done_prefixes;
4357 }
4358
4359 /* Any legacy prefix after a REX prefix nullifies its effect. */
4360
9dac77fa 4361 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4362 }
4363
4364done_prefixes:
4365
4366 /* REX prefix. */
9dac77fa
AK		 4367 if (ctxt->rex_prefix & 8)
4368 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4369
4370 /* Opcode byte(s). */
9dac77fa 4371 opcode = opcode_table[ctxt->b];
d3ad6243 4372 /* Two-byte opcode? */
9dac77fa
AK		 4373 if (ctxt->b == 0x0f) {
4374 ctxt->twobyte = 1;
e85a1085 4375 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4376 opcode = twobyte_table[ctxt->b];
dde7e6d1 4377 }
9dac77fa 4378 ctxt->d = opcode.flags;
dde7e6d1 4379
9f4260e7
TY		 4380 if (ctxt->d & ModRM)
4381 ctxt->modrm = insn_fetch(u8, ctxt);
4382
9dac77fa
AK		 4383 while (ctxt->d & GroupMask) {
4384 switch (ctxt->d & GroupMask) {
46561646 4385 case Group:
9dac77fa 4386 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4387 opcode = opcode.u.group[goffset];
4388 break;
4389 case GroupDual:
9dac77fa
AK		 4390 goffset = (ctxt->modrm >> 3) & 7;
4391 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4392 opcode = opcode.u.gdual->mod3[goffset];
4393 else
4394 opcode = opcode.u.gdual->mod012[goffset];
4395 break;
4396 case RMExt:
9dac77fa 4397 goffset = ctxt->modrm & 7;
01de8b09 4398 opcode = opcode.u.group[goffset];
46561646
AK		 4399 break;
4400 case Prefix:
9dac77fa 4401 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4402 return EMULATION_FAILED;
9dac77fa 4403 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4404 switch (simd_prefix) {
4405 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4406 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4407 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4408 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4409 }
4410 break;
045a282c
GN		 4411 case Escape:
4412 if (ctxt->modrm > 0xbf)
4413 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4414 else
4415 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4416 break;
46561646 4417 default:
1d2887e2 4418 return EMULATION_FAILED;
0d7cdee8 4419 }
46561646 4420
b1ea50b2 4421 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4422 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4423 }
4424
9dac77fa
AK		 4425 ctxt->execute = opcode.u.execute;
4426 ctxt->check_perm = opcode.check_perm;
4427 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4428
4429 /* Unrecognised? */
1146a78b 4430 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4431 return EMULATION_FAILED;
dde7e6d1 4432
9dac77fa 4433 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4434 return EMULATION_FAILED;
d867162c 4435
9dac77fa
AK		 4436 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4437 ctxt->op_bytes = 8;
dde7e6d1 4438
9dac77fa 4439 if (ctxt->d & Op3264) {
7f9b4b75 4440 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4441 ctxt->op_bytes = 8;
7f9b4b75 4442 else
9dac77fa 4443 ctxt->op_bytes = 4;
7f9b4b75
AK		 4444 }
4445
9dac77fa
AK		 4446 if (ctxt->d & Sse)
4447 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4448 else if (ctxt->d & Mmx)
4449 ctxt->op_bytes = 8;
1253791d 4450
dde7e6d1 4451 /* ModRM and SIB bytes. */
9dac77fa 4452 if (ctxt->d & ModRM) {
f09ed83e 4453 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4454 if (!ctxt->has_seg_override)
4455 set_seg_override(ctxt, ctxt->modrm_seg);
4456 } else if (ctxt->d & MemAbs)
f09ed83e 4457 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4458 if (rc != X86EMUL_CONTINUE)
4459 goto done;
4460
9dac77fa
AK		 4461 if (!ctxt->has_seg_override)
4462 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4463
f09ed83e 4464 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4465
f09ed83e
AK		 4466 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4467 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4468
dde7e6d1
AK		 4469 /*
4470 * Decode and fetch the source operand: register, memory
4471 * or immediate.
4472 */
0fe59128 4473 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4474 if (rc != X86EMUL_CONTINUE)
4475 goto done;
4476
dde7e6d1
AK		 4477 /*
4478 * Decode and fetch the second source operand: register, memory
4479 * or immediate.
4480 */
4dd6a57d 4481 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4482 if (rc != X86EMUL_CONTINUE)
4483 goto done;
4484
dde7e6d1 4485 /* Decode and fetch the destination operand: register or memory. */
a9945549 4486 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4487
4488done:
f09ed83e
AK		 4489 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4490 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4491
1d2887e2 4492 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4493}
4494
1cb3f3ae
XG		 4495bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4496{
4497 return ctxt->d & PageTable;
4498}
4499
3e2f65d5
GN		 4500static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4501{
3e2f65d5
GN		 4502 /* The second termination condition only applies for REPE
4503 * and REPNE. Test if the repeat string operation prefix is
4504 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4505 * corresponding termination condition according to:
4506 * - if REPE/REPZ and ZF = 0 then done
4507 * - if REPNE/REPNZ and ZF = 1 then done
4508 */
9dac77fa
AK		 4509 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4510 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4511 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4512 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4513 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4514 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4515 return true;
4516
4517 return false;
4518}
4519
cbe2c9d3
AK		 4520static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4521{
4522 bool fault = false;
4523
4524 ctxt->ops->get_fpu(ctxt);
4525 asm volatile("1: fwait \n\t"
4526 "2: \n\t"
4527 ".pushsection .fixup,\"ax\" \n\t"
4528 "3: \n\t"
4529 "movb $1, %[fault] \n\t"
4530 "jmp 2b \n\t"
4531 ".popsection \n\t"
4532 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4533 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4534 ctxt->ops->put_fpu(ctxt);
4535
4536 if (unlikely(fault))
4537 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4538
4539 return X86EMUL_CONTINUE;
4540}
4541
4542static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4543 struct operand *op)
4544{
4545 if (op->type == OP_MM)
4546 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4547}
4548
e28bbd44
AK		 4549static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4550{
4551 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4552 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4553 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4554 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4555 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4556 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4557 return X86EMUL_CONTINUE;
4558}
dd856efa 4559
7b105ca2 4560int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4561{
0225fb50 4562 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4563 int rc = X86EMUL_CONTINUE;
9dac77fa 4564 int saved_dst_type = ctxt->dst.type;
8b4caf66 4565
9dac77fa 4566 ctxt->mem_read.pos = 0;
310b5d30 4567
1146a78b
GN		 4568 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4569 (ctxt->d & Undefined)) {
35d3d4a1 4570 rc = emulate_ud(ctxt);
1161624f
GN		 4571 goto done;
4572 }
4573
d380a5e4 4574 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4575 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4576 rc = emulate_ud(ctxt);
d380a5e4
GN		 4577 goto done;
4578 }
4579
9dac77fa 4580 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4581 rc = emulate_ud(ctxt);
081bca0e
AK		 4582 goto done;
4583 }
4584
cbe2c9d3
AK		 4585 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4586 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4587 rc = emulate_ud(ctxt);
4588 goto done;
4589 }
4590
cbe2c9d3 4591 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4592 rc = emulate_nm(ctxt);
4593 goto done;
4594 }
4595
cbe2c9d3
AK		 4596 if (ctxt->d & Mmx) {
4597 rc = flush_pending_x87_faults(ctxt);
4598 if (rc != X86EMUL_CONTINUE)
4599 goto done;
4600 /*
4601 * Now that we know the fpu is exception safe, we can fetch
4602 * operands from it.
4603 */
4604 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4605 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4606 if (!(ctxt->d & Mov))
4607 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4608 }
4609
9dac77fa
AK		 4610 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4611 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4612 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4613 if (rc != X86EMUL_CONTINUE)
4614 goto done;
4615 }
4616
e92805ac 4617 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4618 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4619 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4620 goto done;
4621 }
4622
8ea7d6ae 4623 /* Instruction can only be executed in protected mode */
9d1b39a9 4624 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4625 rc = emulate_ud(ctxt);
4626 goto done;
4627 }
4628
d09beabd 4629 /* Do instruction specific permission checks */
9dac77fa
AK		 4630 if (ctxt->check_perm) {
4631 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4632 if (rc != X86EMUL_CONTINUE)
4633 goto done;
4634 }
4635
9dac77fa
AK		 4636 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4637 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4638 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4639 if (rc != X86EMUL_CONTINUE)
4640 goto done;
4641 }
4642
9dac77fa 4643 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4644 /* All REP prefixes have the same first termination condition */
dd856efa 4645 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4646 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4647 goto done;
4648 }
b9fa9d6b
AK		 4649 }
4650
9dac77fa
AK		 4651 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4652 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4653 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4654 if (rc != X86EMUL_CONTINUE)
8b4caf66 4655 goto done;
9dac77fa 4656 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4657 }
4658
9dac77fa
AK		 4659 if (ctxt->src2.type == OP_MEM) {
4660 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4661 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4662 if (rc != X86EMUL_CONTINUE)
4663 goto done;
4664 }
4665
9dac77fa 4666 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4667 goto special_insn;
4668
4669
9dac77fa 4670 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4671 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4672 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4673 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4674 if (rc != X86EMUL_CONTINUE)
4675 goto done;
038e51de 4676 }
9dac77fa 4677 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4678
018a98db
AK		 4679special_insn:
4680
9dac77fa
AK		 4681 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4682 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4683 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4684 if (rc != X86EMUL_CONTINUE)
4685 goto done;
4686 }
4687
9dac77fa 4688 if (ctxt->execute) {
e28bbd44
AK		 4689 if (ctxt->d & Fastop) {
4690 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4691 rc = fastop(ctxt, fop);
4692 if (rc != X86EMUL_CONTINUE)
4693 goto done;
4694 goto writeback;
4695 }
9dac77fa 4696 rc = ctxt->execute(ctxt);
ef65c889
AK		 4697 if (rc != X86EMUL_CONTINUE)
4698 goto done;
4699 goto writeback;
4700 }
4701
9dac77fa 4702 if (ctxt->twobyte)
6aa8b732
AK		 4703 goto twobyte_insn;
4704
9dac77fa 4705 switch (ctxt->b) {
6aa8b732 4706 case 0x63: /* movsxd */
8b4caf66 4707 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4708 goto cannot_emulate;
9dac77fa 4709 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4710 break;
b2833e3c 4711 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4712 if (test_cc(ctxt->b, ctxt->eflags))
4713 jmp_rel(ctxt, ctxt->src.val);
018a98db 4714 break;
7e0b54b1 4715 case 0x8d: /* lea r16/r32, m */
9dac77fa 4716 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4717 break;
3d9e77df 4718 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4719 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4720 break;
e4f973ae
TY		 4721 rc = em_xchg(ctxt);
4722 break;
e8b6fa70 4723 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4724 switch (ctxt->op_bytes) {
4725 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4726 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4727 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4728 }
4729 break;
6e154e56 4730 case 0xcc: /* int3 */
5c5df76b
TY		 4731 rc = emulate_int(ctxt, 3);
4732 break;
6e154e56 4733 case 0xcd: /* int n */
9dac77fa 4734 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4735 break;
4736 case 0xce: /* into */
5c5df76b
TY		 4737 if (ctxt->eflags & EFLG_OF)
4738 rc = emulate_int(ctxt, 4);
6e154e56 4739 break;
1a52e051 4740 case 0xe9: /* jmp rel */
db5b0762 4741 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4742 jmp_rel(ctxt, ctxt->src.val);
4743 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4744 break;
111de5d6 4745 case 0xf4: /* hlt */
6c3287f7 4746 ctxt->ops->halt(ctxt);
19fdfa0d 4747 break;
111de5d6
AK		 4748 case 0xf5: /* cmc */
4749 /* complement carry flag from eflags reg */
4750 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4751 break;
4752 case 0xf8: /* clc */
4753 ctxt->eflags &= ~EFLG_CF;
111de5d6 4754 break;
8744aa9a
MG		 4755 case 0xf9: /* stc */
4756 ctxt->eflags |= EFLG_CF;
4757 break;
fb4616f4
MG		 4758 case 0xfc: /* cld */
4759 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4760 break;
4761 case 0xfd: /* std */
4762 ctxt->eflags |= EFLG_DF;
fb4616f4 4763 break;
91269b8f
AK		 4764 default:
4765 goto cannot_emulate;
6aa8b732 4766 }
018a98db 4767
7d9ddaed
AK		 4768 if (rc != X86EMUL_CONTINUE)
4769 goto done;
4770
018a98db 4771writeback:
adddcecf 4772 rc = writeback(ctxt);
1b30eaa8 4773 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4774 goto done;
4775
5cd21917
GN		 4776 /*
4777 * restore dst type in case the decoding will be reused
4778 * (happens for string instruction )
4779 */
9dac77fa 4780 ctxt->dst.type = saved_dst_type;
5cd21917 4781
9dac77fa 4782 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4783 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4784
9dac77fa 4785 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4786 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4787
9dac77fa 4788 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4789 unsigned int count;
9dac77fa 4790 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4791 if ((ctxt->d & SrcMask) == SrcSI)
4792 count = ctxt->src.count;
4793 else
4794 count = ctxt->dst.count;
4795 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4796 -count);
3e2f65d5 4797
d2ddd1c4
GN		 4798 if (!string_insn_completed(ctxt)) {
4799 /*
4800 * Re-enter guest when pio read ahead buffer is empty
4801 * or, if it is not used, after each 1024 iteration.
4802 */
dd856efa 4803 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4804 (r->end == 0 || r->end != r->pos)) {
4805 /*
4806 * Reset read cache. Usually happens before
4807 * decode, but since instruction is restarted
4808 * we have to do it here.
4809 */
9dac77fa 4810 ctxt->mem_read.end = 0;
dd856efa 4811 writeback_registers(ctxt);
d2ddd1c4
GN		 4812 return EMULATION_RESTART;
4813 }
4814 goto done; /* skip rip writeback */
0fa6ccbd 4815 }
5cd21917 4816 }
d2ddd1c4 4817
9dac77fa 4818 ctxt->eip = ctxt->_eip;
018a98db
AK		 4819
4820done:
da9cb575
AK		 4821 if (rc == X86EMUL_PROPAGATE_FAULT)
4822 ctxt->have_exception = true;
775fde86
JR		 4823 if (rc == X86EMUL_INTERCEPTED)
4824 return EMULATION_INTERCEPTED;
4825
dd856efa
AK		 4826 if (rc == X86EMUL_CONTINUE)
4827 writeback_registers(ctxt);
4828
d2ddd1c4 4829 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4830
4831twobyte_insn:
9dac77fa 4832 switch (ctxt->b) {
018a98db 4833 case 0x09: /* wbinvd */
cfb22375 4834 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4835 break;
4836 case 0x08: /* invd */
018a98db
AK		 4837 case 0x0d: /* GrpP (prefetch) */
4838 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4839 break;
4840 case 0x20: /* mov cr, reg */
9dac77fa 4841 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4842 break;
6aa8b732 4843 case 0x21: /* mov from dr to reg */
9dac77fa 4844 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4845 break;
6aa8b732 4846 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4847 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4848 if (!test_cc(ctxt->b, ctxt->eflags))
4849 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4850 break;
b2833e3c 4851 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4852 if (test_cc(ctxt->b, ctxt->eflags))
4853 jmp_rel(ctxt, ctxt->src.val);
018a98db 4854 break;
ee45b58e 4855 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4856 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4857 break;
2a7c5b8b
GC		 4858 case 0xae: /* clflush */
4859 break;
6aa8b732 4860 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4861 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4862 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4863 : (u16) ctxt->src.val;
6aa8b732 4864 break;
6aa8b732 4865 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4866 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4867 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4868 (s16) ctxt->src.val;
6aa8b732 4869 break;
92f738a5 4870 case 0xc0 ... 0xc1: /* xadd */
158de57f 4871 fastop(ctxt, em_add);
92f738a5 4872 /* Write back the register source. */
9dac77fa
AK		 4873 ctxt->src.val = ctxt->dst.orig_val;
4874 write_register_operand(&ctxt->src);
92f738a5 4875 break;
a012e65a 4876 case 0xc3: /* movnti */
9dac77fa
AK		 4877 ctxt->dst.bytes = ctxt->op_bytes;
4878 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4879 (u64) ctxt->src.val;
a012e65a 4880 break;
91269b8f
AK		 4881 default:
4882 goto cannot_emulate;
6aa8b732 4883 }
7d9ddaed
AK		 4884
4885 if (rc != X86EMUL_CONTINUE)
4886 goto done;
4887
6aa8b732
AK		 4888 goto writeback;
4889
4890cannot_emulate:
a0c0ab2f 4891 return EMULATION_FAILED;
6aa8b732 4892}
dd856efa
AK		 4893
4894void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4895{
4896 invalidate_registers(ctxt);
4897}
4898
4899void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4900{
4901 writeback_registers(ctxt);
4902}
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