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85f455f7 ED |
1 | /* |
2 | * 8259 interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2007 Intel Corporation | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | * Authors: | |
25 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
26 | * Port from Qemu. | |
27 | */ | |
28 | #include <linux/mm.h> | |
29 | #include "irq.h" | |
edf88417 AK |
30 | |
31 | #include <linux/kvm_host.h> | |
85f455f7 | 32 | |
7edd0ce0 AK |
33 | static void pic_clear_isr(struct kvm_kpic_state *s, int irq) |
34 | { | |
35 | s->isr &= ~(1 << irq); | |
e4825800 MT |
36 | s->isr_ack |= (1 << irq); |
37 | } | |
38 | ||
39 | void kvm_pic_clear_isr_ack(struct kvm *kvm) | |
40 | { | |
41 | struct kvm_pic *s = pic_irqchip(kvm); | |
42 | s->pics[0].isr_ack = 0xff; | |
43 | s->pics[1].isr_ack = 0xff; | |
7edd0ce0 AK |
44 | } |
45 | ||
85f455f7 ED |
46 | /* |
47 | * set irq level. If an edge is detected, then the IRR is set to 1 | |
48 | */ | |
49 | static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) | |
50 | { | |
51 | int mask; | |
52 | mask = 1 << irq; | |
53 | if (s->elcr & mask) /* level triggered */ | |
54 | if (level) { | |
55 | s->irr |= mask; | |
56 | s->last_irr |= mask; | |
57 | } else { | |
58 | s->irr &= ~mask; | |
59 | s->last_irr &= ~mask; | |
60 | } | |
61 | else /* edge triggered */ | |
62 | if (level) { | |
63 | if ((s->last_irr & mask) == 0) | |
64 | s->irr |= mask; | |
65 | s->last_irr |= mask; | |
66 | } else | |
67 | s->last_irr &= ~mask; | |
68 | } | |
69 | ||
70 | /* | |
71 | * return the highest priority found in mask (highest = smallest | |
72 | * number). Return 8 if no irq | |
73 | */ | |
74 | static inline int get_priority(struct kvm_kpic_state *s, int mask) | |
75 | { | |
76 | int priority; | |
77 | if (mask == 0) | |
78 | return 8; | |
79 | priority = 0; | |
80 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
81 | priority++; | |
82 | return priority; | |
83 | } | |
84 | ||
85 | /* | |
86 | * return the pic wanted interrupt. return -1 if none | |
87 | */ | |
88 | static int pic_get_irq(struct kvm_kpic_state *s) | |
89 | { | |
90 | int mask, cur_priority, priority; | |
91 | ||
92 | mask = s->irr & ~s->imr; | |
93 | priority = get_priority(s, mask); | |
94 | if (priority == 8) | |
95 | return -1; | |
96 | /* | |
97 | * compute current priority. If special fully nested mode on the | |
98 | * master, the IRQ coming from the slave is not taken into account | |
99 | * for the priority computation. | |
100 | */ | |
101 | mask = s->isr; | |
102 | if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) | |
103 | mask &= ~(1 << 2); | |
104 | cur_priority = get_priority(s, mask); | |
105 | if (priority < cur_priority) | |
106 | /* | |
107 | * higher priority found: an irq should be generated | |
108 | */ | |
109 | return (priority + s->priority_add) & 7; | |
110 | else | |
111 | return -1; | |
112 | } | |
113 | ||
114 | /* | |
115 | * raise irq to CPU if necessary. must be called every time the active | |
116 | * irq may change | |
117 | */ | |
118 | static void pic_update_irq(struct kvm_pic *s) | |
119 | { | |
120 | int irq2, irq; | |
121 | ||
122 | irq2 = pic_get_irq(&s->pics[1]); | |
123 | if (irq2 >= 0) { | |
124 | /* | |
125 | * if irq request by slave pic, signal master PIC | |
126 | */ | |
127 | pic_set_irq1(&s->pics[0], 2, 1); | |
128 | pic_set_irq1(&s->pics[0], 2, 0); | |
129 | } | |
130 | irq = pic_get_irq(&s->pics[0]); | |
131 | if (irq >= 0) | |
132 | s->irq_request(s->irq_request_opaque, 1); | |
133 | else | |
134 | s->irq_request(s->irq_request_opaque, 0); | |
135 | } | |
136 | ||
6ceb9d79 HQ |
137 | void kvm_pic_update_irq(struct kvm_pic *s) |
138 | { | |
139 | pic_update_irq(s); | |
140 | } | |
141 | ||
85f455f7 ED |
142 | void kvm_pic_set_irq(void *opaque, int irq, int level) |
143 | { | |
144 | struct kvm_pic *s = opaque; | |
145 | ||
c65bbfa1 BAY |
146 | if (irq >= 0 && irq < PIC_NUM_PINS) { |
147 | pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); | |
148 | pic_update_irq(s); | |
149 | } | |
85f455f7 ED |
150 | } |
151 | ||
152 | /* | |
153 | * acknowledge interrupt 'irq' | |
154 | */ | |
155 | static inline void pic_intack(struct kvm_kpic_state *s, int irq) | |
156 | { | |
7edd0ce0 | 157 | s->isr |= 1 << irq; |
85f455f7 ED |
158 | if (s->auto_eoi) { |
159 | if (s->rotate_on_auto_eoi) | |
160 | s->priority_add = (irq + 1) & 7; | |
7edd0ce0 AK |
161 | pic_clear_isr(s, irq); |
162 | } | |
85f455f7 ED |
163 | /* |
164 | * We don't clear a level sensitive interrupt here | |
165 | */ | |
166 | if (!(s->elcr & (1 << irq))) | |
167 | s->irr &= ~(1 << irq); | |
168 | } | |
169 | ||
f5244726 | 170 | int kvm_pic_read_irq(struct kvm *kvm) |
85f455f7 ED |
171 | { |
172 | int irq, irq2, intno; | |
f5244726 | 173 | struct kvm_pic *s = pic_irqchip(kvm); |
85f455f7 ED |
174 | |
175 | irq = pic_get_irq(&s->pics[0]); | |
176 | if (irq >= 0) { | |
177 | pic_intack(&s->pics[0], irq); | |
178 | if (irq == 2) { | |
179 | irq2 = pic_get_irq(&s->pics[1]); | |
180 | if (irq2 >= 0) | |
181 | pic_intack(&s->pics[1], irq2); | |
182 | else | |
183 | /* | |
184 | * spurious IRQ on slave controller | |
185 | */ | |
186 | irq2 = 7; | |
187 | intno = s->pics[1].irq_base + irq2; | |
188 | irq = irq2 + 8; | |
189 | } else | |
190 | intno = s->pics[0].irq_base + irq; | |
191 | } else { | |
192 | /* | |
193 | * spurious IRQ on host controller | |
194 | */ | |
195 | irq = 7; | |
196 | intno = s->pics[0].irq_base + irq; | |
197 | } | |
198 | pic_update_irq(s); | |
f5244726 | 199 | kvm_notify_acked_irq(kvm, irq); |
85f455f7 ED |
200 | |
201 | return intno; | |
202 | } | |
203 | ||
2fcceae1 | 204 | void kvm_pic_reset(struct kvm_kpic_state *s) |
85f455f7 | 205 | { |
85428ac7 | 206 | int irq, irqbase; |
f5244726 | 207 | struct kvm *kvm = s->pics_state->irq_request_opaque; |
85428ac7 | 208 | struct kvm_vcpu *vcpu0 = kvm->vcpus[0]; |
f5244726 | 209 | |
85428ac7 MT |
210 | if (s == &s->pics_state->pics[0]) |
211 | irqbase = 0; | |
212 | else | |
213 | irqbase = 8; | |
214 | ||
215 | for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { | |
216 | if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) | |
217 | if (s->irr & (1 << irq) || s->isr & (1 << irq)) | |
218 | kvm_notify_acked_irq(kvm, irq+irqbase); | |
f5244726 | 219 | } |
85f455f7 ED |
220 | s->last_irr = 0; |
221 | s->irr = 0; | |
222 | s->imr = 0; | |
223 | s->isr = 0; | |
e4825800 | 224 | s->isr_ack = 0xff; |
85f455f7 ED |
225 | s->priority_add = 0; |
226 | s->irq_base = 0; | |
227 | s->read_reg_select = 0; | |
228 | s->poll = 0; | |
229 | s->special_mask = 0; | |
230 | s->init_state = 0; | |
231 | s->auto_eoi = 0; | |
232 | s->rotate_on_auto_eoi = 0; | |
233 | s->special_fully_nested_mode = 0; | |
234 | s->init4 = 0; | |
235 | } | |
236 | ||
237 | static void pic_ioport_write(void *opaque, u32 addr, u32 val) | |
238 | { | |
239 | struct kvm_kpic_state *s = opaque; | |
240 | int priority, cmd, irq; | |
241 | ||
242 | addr &= 1; | |
243 | if (addr == 0) { | |
244 | if (val & 0x10) { | |
2fcceae1 | 245 | kvm_pic_reset(s); /* init */ |
85f455f7 ED |
246 | /* |
247 | * deassert a pending interrupt | |
248 | */ | |
249 | s->pics_state->irq_request(s->pics_state-> | |
250 | irq_request_opaque, 0); | |
251 | s->init_state = 1; | |
252 | s->init4 = val & 1; | |
253 | if (val & 0x02) | |
254 | printk(KERN_ERR "single mode not supported"); | |
255 | if (val & 0x08) | |
256 | printk(KERN_ERR | |
257 | "level sensitive irq not supported"); | |
258 | } else if (val & 0x08) { | |
259 | if (val & 0x04) | |
260 | s->poll = 1; | |
261 | if (val & 0x02) | |
262 | s->read_reg_select = val & 1; | |
263 | if (val & 0x40) | |
264 | s->special_mask = (val >> 5) & 1; | |
265 | } else { | |
266 | cmd = val >> 5; | |
267 | switch (cmd) { | |
268 | case 0: | |
269 | case 4: | |
270 | s->rotate_on_auto_eoi = cmd >> 2; | |
271 | break; | |
272 | case 1: /* end of interrupt */ | |
273 | case 5: | |
274 | priority = get_priority(s, s->isr); | |
275 | if (priority != 8) { | |
276 | irq = (priority + s->priority_add) & 7; | |
7edd0ce0 | 277 | pic_clear_isr(s, irq); |
85f455f7 ED |
278 | if (cmd == 5) |
279 | s->priority_add = (irq + 1) & 7; | |
280 | pic_update_irq(s->pics_state); | |
281 | } | |
282 | break; | |
283 | case 3: | |
284 | irq = val & 7; | |
7edd0ce0 | 285 | pic_clear_isr(s, irq); |
85f455f7 ED |
286 | pic_update_irq(s->pics_state); |
287 | break; | |
288 | case 6: | |
289 | s->priority_add = (val + 1) & 7; | |
290 | pic_update_irq(s->pics_state); | |
291 | break; | |
292 | case 7: | |
293 | irq = val & 7; | |
85f455f7 | 294 | s->priority_add = (irq + 1) & 7; |
7edd0ce0 | 295 | pic_clear_isr(s, irq); |
85f455f7 ED |
296 | pic_update_irq(s->pics_state); |
297 | break; | |
298 | default: | |
299 | break; /* no operation */ | |
300 | } | |
301 | } | |
302 | } else | |
303 | switch (s->init_state) { | |
304 | case 0: /* normal mode */ | |
305 | s->imr = val; | |
306 | pic_update_irq(s->pics_state); | |
307 | break; | |
308 | case 1: | |
309 | s->irq_base = val & 0xf8; | |
310 | s->init_state = 2; | |
311 | break; | |
312 | case 2: | |
313 | if (s->init4) | |
314 | s->init_state = 3; | |
315 | else | |
316 | s->init_state = 0; | |
317 | break; | |
318 | case 3: | |
319 | s->special_fully_nested_mode = (val >> 4) & 1; | |
320 | s->auto_eoi = (val >> 1) & 1; | |
321 | s->init_state = 0; | |
322 | break; | |
323 | } | |
324 | } | |
325 | ||
326 | static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) | |
327 | { | |
328 | int ret; | |
329 | ||
330 | ret = pic_get_irq(s); | |
331 | if (ret >= 0) { | |
332 | if (addr1 >> 7) { | |
333 | s->pics_state->pics[0].isr &= ~(1 << 2); | |
334 | s->pics_state->pics[0].irr &= ~(1 << 2); | |
335 | } | |
336 | s->irr &= ~(1 << ret); | |
7edd0ce0 | 337 | pic_clear_isr(s, ret); |
85f455f7 ED |
338 | if (addr1 >> 7 || ret != 2) |
339 | pic_update_irq(s->pics_state); | |
340 | } else { | |
341 | ret = 0x07; | |
342 | pic_update_irq(s->pics_state); | |
343 | } | |
344 | ||
345 | return ret; | |
346 | } | |
347 | ||
348 | static u32 pic_ioport_read(void *opaque, u32 addr1) | |
349 | { | |
350 | struct kvm_kpic_state *s = opaque; | |
351 | unsigned int addr; | |
352 | int ret; | |
353 | ||
354 | addr = addr1; | |
355 | addr &= 1; | |
356 | if (s->poll) { | |
357 | ret = pic_poll_read(s, addr1); | |
358 | s->poll = 0; | |
359 | } else | |
360 | if (addr == 0) | |
361 | if (s->read_reg_select) | |
362 | ret = s->isr; | |
363 | else | |
364 | ret = s->irr; | |
365 | else | |
366 | ret = s->imr; | |
367 | return ret; | |
368 | } | |
369 | ||
370 | static void elcr_ioport_write(void *opaque, u32 addr, u32 val) | |
371 | { | |
372 | struct kvm_kpic_state *s = opaque; | |
373 | s->elcr = val & s->elcr_mask; | |
374 | } | |
375 | ||
376 | static u32 elcr_ioport_read(void *opaque, u32 addr1) | |
377 | { | |
378 | struct kvm_kpic_state *s = opaque; | |
379 | return s->elcr; | |
380 | } | |
381 | ||
92760499 LV |
382 | static int picdev_in_range(struct kvm_io_device *this, gpa_t addr, |
383 | int len, int is_write) | |
85f455f7 ED |
384 | { |
385 | switch (addr) { | |
386 | case 0x20: | |
387 | case 0x21: | |
388 | case 0xa0: | |
389 | case 0xa1: | |
390 | case 0x4d0: | |
391 | case 0x4d1: | |
392 | return 1; | |
393 | default: | |
394 | return 0; | |
395 | } | |
396 | } | |
397 | ||
398 | static void picdev_write(struct kvm_io_device *this, | |
399 | gpa_t addr, int len, const void *val) | |
400 | { | |
401 | struct kvm_pic *s = this->private; | |
402 | unsigned char data = *(unsigned char *)val; | |
403 | ||
404 | if (len != 1) { | |
405 | if (printk_ratelimit()) | |
406 | printk(KERN_ERR "PIC: non byte write\n"); | |
407 | return; | |
408 | } | |
409 | switch (addr) { | |
410 | case 0x20: | |
411 | case 0x21: | |
412 | case 0xa0: | |
413 | case 0xa1: | |
414 | pic_ioport_write(&s->pics[addr >> 7], addr, data); | |
415 | break; | |
416 | case 0x4d0: | |
417 | case 0x4d1: | |
418 | elcr_ioport_write(&s->pics[addr & 1], addr, data); | |
419 | break; | |
420 | } | |
421 | } | |
422 | ||
423 | static void picdev_read(struct kvm_io_device *this, | |
424 | gpa_t addr, int len, void *val) | |
425 | { | |
426 | struct kvm_pic *s = this->private; | |
427 | unsigned char data = 0; | |
428 | ||
429 | if (len != 1) { | |
430 | if (printk_ratelimit()) | |
431 | printk(KERN_ERR "PIC: non byte read\n"); | |
432 | return; | |
433 | } | |
434 | switch (addr) { | |
435 | case 0x20: | |
436 | case 0x21: | |
437 | case 0xa0: | |
438 | case 0xa1: | |
439 | data = pic_ioport_read(&s->pics[addr >> 7], addr); | |
440 | break; | |
441 | case 0x4d0: | |
442 | case 0x4d1: | |
443 | data = elcr_ioport_read(&s->pics[addr & 1], addr); | |
444 | break; | |
445 | } | |
446 | *(unsigned char *)val = data; | |
447 | } | |
448 | ||
449 | /* | |
450 | * callback when PIC0 irq status changed | |
451 | */ | |
452 | static void pic_irq_request(void *opaque, int level) | |
453 | { | |
454 | struct kvm *kvm = opaque; | |
b6958ce4 | 455 | struct kvm_vcpu *vcpu = kvm->vcpus[0]; |
e4825800 MT |
456 | struct kvm_pic *s = pic_irqchip(kvm); |
457 | int irq = pic_get_irq(&s->pics[0]); | |
85f455f7 | 458 | |
e4825800 MT |
459 | s->output = level; |
460 | if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { | |
461 | s->pics[0].isr_ack &= ~(1 << irq); | |
b6958ce4 | 462 | kvm_vcpu_kick(vcpu); |
e4825800 | 463 | } |
85f455f7 ED |
464 | } |
465 | ||
466 | struct kvm_pic *kvm_create_pic(struct kvm *kvm) | |
467 | { | |
468 | struct kvm_pic *s; | |
469 | s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); | |
470 | if (!s) | |
471 | return NULL; | |
472 | s->pics[0].elcr_mask = 0xf8; | |
473 | s->pics[1].elcr_mask = 0xde; | |
474 | s->irq_request = pic_irq_request; | |
475 | s->irq_request_opaque = kvm; | |
476 | s->pics[0].pics_state = s; | |
477 | s->pics[1].pics_state = s; | |
478 | ||
479 | /* | |
480 | * Initialize PIO device | |
481 | */ | |
482 | s->dev.read = picdev_read; | |
483 | s->dev.write = picdev_write; | |
484 | s->dev.in_range = picdev_in_range; | |
485 | s->dev.private = s; | |
486 | kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev); | |
487 | return s; | |
488 | } |