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Commit | Line | Data |
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85f455f7 ED |
1 | /* |
2 | * 8259 interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2007 Intel Corporation | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | * Authors: | |
25 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
26 | * Port from Qemu. | |
27 | */ | |
28 | #include <linux/mm.h> | |
3f353858 | 29 | #include <linux/bitops.h> |
85f455f7 | 30 | #include "irq.h" |
edf88417 AK |
31 | |
32 | #include <linux/kvm_host.h> | |
1000ff8d | 33 | #include "trace.h" |
85f455f7 | 34 | |
3f353858 | 35 | static void pic_lock(struct kvm_pic *s) |
d7364a29 | 36 | __acquires(&s->lock) |
3f353858 AK |
37 | { |
38 | spin_lock(&s->lock); | |
39 | } | |
40 | ||
41 | static void pic_unlock(struct kvm_pic *s) | |
d7364a29 | 42 | __releases(&s->lock) |
3f353858 AK |
43 | { |
44 | struct kvm *kvm = s->kvm; | |
45 | unsigned acks = s->pending_acks; | |
3f353858 AK |
46 | struct kvm_vcpu *vcpu; |
47 | ||
48 | s->pending_acks = 0; | |
3f353858 AK |
49 | |
50 | spin_unlock(&s->lock); | |
51 | ||
52 | while (acks) { | |
44882eed MT |
53 | kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)), |
54 | __ffs(acks)); | |
3f353858 AK |
55 | acks &= acks - 1; |
56 | } | |
3f353858 AK |
57 | } |
58 | ||
7edd0ce0 AK |
59 | static void pic_clear_isr(struct kvm_kpic_state *s, int irq) |
60 | { | |
61 | s->isr &= ~(1 << irq); | |
e4825800 MT |
62 | s->isr_ack |= (1 << irq); |
63 | } | |
64 | ||
65 | void kvm_pic_clear_isr_ack(struct kvm *kvm) | |
66 | { | |
67 | struct kvm_pic *s = pic_irqchip(kvm); | |
9f4cc127 | 68 | pic_lock(s); |
e4825800 MT |
69 | s->pics[0].isr_ack = 0xff; |
70 | s->pics[1].isr_ack = 0xff; | |
9f4cc127 | 71 | pic_unlock(s); |
7edd0ce0 AK |
72 | } |
73 | ||
85f455f7 ED |
74 | /* |
75 | * set irq level. If an edge is detected, then the IRR is set to 1 | |
76 | */ | |
4925663a | 77 | static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) |
85f455f7 | 78 | { |
4925663a | 79 | int mask, ret = 1; |
85f455f7 ED |
80 | mask = 1 << irq; |
81 | if (s->elcr & mask) /* level triggered */ | |
82 | if (level) { | |
4925663a | 83 | ret = !(s->irr & mask); |
85f455f7 ED |
84 | s->irr |= mask; |
85 | s->last_irr |= mask; | |
86 | } else { | |
87 | s->irr &= ~mask; | |
88 | s->last_irr &= ~mask; | |
89 | } | |
90 | else /* edge triggered */ | |
91 | if (level) { | |
4925663a GN |
92 | if ((s->last_irr & mask) == 0) { |
93 | ret = !(s->irr & mask); | |
85f455f7 | 94 | s->irr |= mask; |
4925663a | 95 | } |
85f455f7 ED |
96 | s->last_irr |= mask; |
97 | } else | |
98 | s->last_irr &= ~mask; | |
4925663a GN |
99 | |
100 | return (s->imr & mask) ? -1 : ret; | |
85f455f7 ED |
101 | } |
102 | ||
103 | /* | |
104 | * return the highest priority found in mask (highest = smallest | |
105 | * number). Return 8 if no irq | |
106 | */ | |
107 | static inline int get_priority(struct kvm_kpic_state *s, int mask) | |
108 | { | |
109 | int priority; | |
110 | if (mask == 0) | |
111 | return 8; | |
112 | priority = 0; | |
113 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
114 | priority++; | |
115 | return priority; | |
116 | } | |
117 | ||
118 | /* | |
119 | * return the pic wanted interrupt. return -1 if none | |
120 | */ | |
121 | static int pic_get_irq(struct kvm_kpic_state *s) | |
122 | { | |
123 | int mask, cur_priority, priority; | |
124 | ||
125 | mask = s->irr & ~s->imr; | |
126 | priority = get_priority(s, mask); | |
127 | if (priority == 8) | |
128 | return -1; | |
129 | /* | |
130 | * compute current priority. If special fully nested mode on the | |
131 | * master, the IRQ coming from the slave is not taken into account | |
132 | * for the priority computation. | |
133 | */ | |
134 | mask = s->isr; | |
135 | if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) | |
136 | mask &= ~(1 << 2); | |
137 | cur_priority = get_priority(s, mask); | |
138 | if (priority < cur_priority) | |
139 | /* | |
140 | * higher priority found: an irq should be generated | |
141 | */ | |
142 | return (priority + s->priority_add) & 7; | |
143 | else | |
144 | return -1; | |
145 | } | |
146 | ||
147 | /* | |
148 | * raise irq to CPU if necessary. must be called every time the active | |
149 | * irq may change | |
150 | */ | |
151 | static void pic_update_irq(struct kvm_pic *s) | |
152 | { | |
153 | int irq2, irq; | |
154 | ||
155 | irq2 = pic_get_irq(&s->pics[1]); | |
156 | if (irq2 >= 0) { | |
157 | /* | |
158 | * if irq request by slave pic, signal master PIC | |
159 | */ | |
160 | pic_set_irq1(&s->pics[0], 2, 1); | |
161 | pic_set_irq1(&s->pics[0], 2, 0); | |
162 | } | |
163 | irq = pic_get_irq(&s->pics[0]); | |
164 | if (irq >= 0) | |
165 | s->irq_request(s->irq_request_opaque, 1); | |
166 | else | |
167 | s->irq_request(s->irq_request_opaque, 0); | |
168 | } | |
169 | ||
6ceb9d79 HQ |
170 | void kvm_pic_update_irq(struct kvm_pic *s) |
171 | { | |
3f353858 | 172 | pic_lock(s); |
6ceb9d79 | 173 | pic_update_irq(s); |
3f353858 | 174 | pic_unlock(s); |
6ceb9d79 HQ |
175 | } |
176 | ||
4925663a | 177 | int kvm_pic_set_irq(void *opaque, int irq, int level) |
85f455f7 ED |
178 | { |
179 | struct kvm_pic *s = opaque; | |
4925663a | 180 | int ret = -1; |
85f455f7 | 181 | |
3f353858 | 182 | pic_lock(s); |
c65bbfa1 | 183 | if (irq >= 0 && irq < PIC_NUM_PINS) { |
4925663a | 184 | ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); |
c65bbfa1 | 185 | pic_update_irq(s); |
1000ff8d GN |
186 | trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, |
187 | s->pics[irq >> 3].imr, ret == 0); | |
c65bbfa1 | 188 | } |
3f353858 | 189 | pic_unlock(s); |
4925663a GN |
190 | |
191 | return ret; | |
85f455f7 ED |
192 | } |
193 | ||
194 | /* | |
195 | * acknowledge interrupt 'irq' | |
196 | */ | |
197 | static inline void pic_intack(struct kvm_kpic_state *s, int irq) | |
198 | { | |
7edd0ce0 | 199 | s->isr |= 1 << irq; |
85f455f7 ED |
200 | if (s->auto_eoi) { |
201 | if (s->rotate_on_auto_eoi) | |
202 | s->priority_add = (irq + 1) & 7; | |
7edd0ce0 AK |
203 | pic_clear_isr(s, irq); |
204 | } | |
85f455f7 ED |
205 | /* |
206 | * We don't clear a level sensitive interrupt here | |
207 | */ | |
208 | if (!(s->elcr & (1 << irq))) | |
209 | s->irr &= ~(1 << irq); | |
210 | } | |
211 | ||
f5244726 | 212 | int kvm_pic_read_irq(struct kvm *kvm) |
85f455f7 ED |
213 | { |
214 | int irq, irq2, intno; | |
f5244726 | 215 | struct kvm_pic *s = pic_irqchip(kvm); |
85f455f7 | 216 | |
3f353858 | 217 | pic_lock(s); |
85f455f7 ED |
218 | irq = pic_get_irq(&s->pics[0]); |
219 | if (irq >= 0) { | |
220 | pic_intack(&s->pics[0], irq); | |
221 | if (irq == 2) { | |
222 | irq2 = pic_get_irq(&s->pics[1]); | |
223 | if (irq2 >= 0) | |
224 | pic_intack(&s->pics[1], irq2); | |
225 | else | |
226 | /* | |
227 | * spurious IRQ on slave controller | |
228 | */ | |
229 | irq2 = 7; | |
230 | intno = s->pics[1].irq_base + irq2; | |
231 | irq = irq2 + 8; | |
232 | } else | |
233 | intno = s->pics[0].irq_base + irq; | |
234 | } else { | |
235 | /* | |
236 | * spurious IRQ on host controller | |
237 | */ | |
238 | irq = 7; | |
239 | intno = s->pics[0].irq_base + irq; | |
240 | } | |
241 | pic_update_irq(s); | |
3f353858 | 242 | pic_unlock(s); |
44882eed | 243 | kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq); |
85f455f7 ED |
244 | |
245 | return intno; | |
246 | } | |
247 | ||
2fcceae1 | 248 | void kvm_pic_reset(struct kvm_kpic_state *s) |
85f455f7 | 249 | { |
3f353858 | 250 | int irq, irqbase, n; |
f5244726 | 251 | struct kvm *kvm = s->pics_state->irq_request_opaque; |
c5af89b6 | 252 | struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu; |
f5244726 | 253 | |
85428ac7 MT |
254 | if (s == &s->pics_state->pics[0]) |
255 | irqbase = 0; | |
256 | else | |
257 | irqbase = 8; | |
258 | ||
259 | for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { | |
260 | if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) | |
3f353858 AK |
261 | if (s->irr & (1 << irq) || s->isr & (1 << irq)) { |
262 | n = irq + irqbase; | |
263 | s->pics_state->pending_acks |= 1 << n; | |
264 | } | |
f5244726 | 265 | } |
85f455f7 ED |
266 | s->last_irr = 0; |
267 | s->irr = 0; | |
268 | s->imr = 0; | |
269 | s->isr = 0; | |
e4825800 | 270 | s->isr_ack = 0xff; |
85f455f7 ED |
271 | s->priority_add = 0; |
272 | s->irq_base = 0; | |
273 | s->read_reg_select = 0; | |
274 | s->poll = 0; | |
275 | s->special_mask = 0; | |
276 | s->init_state = 0; | |
277 | s->auto_eoi = 0; | |
278 | s->rotate_on_auto_eoi = 0; | |
279 | s->special_fully_nested_mode = 0; | |
280 | s->init4 = 0; | |
281 | } | |
282 | ||
283 | static void pic_ioport_write(void *opaque, u32 addr, u32 val) | |
284 | { | |
285 | struct kvm_kpic_state *s = opaque; | |
286 | int priority, cmd, irq; | |
287 | ||
288 | addr &= 1; | |
289 | if (addr == 0) { | |
290 | if (val & 0x10) { | |
2fcceae1 | 291 | kvm_pic_reset(s); /* init */ |
85f455f7 ED |
292 | /* |
293 | * deassert a pending interrupt | |
294 | */ | |
295 | s->pics_state->irq_request(s->pics_state-> | |
296 | irq_request_opaque, 0); | |
297 | s->init_state = 1; | |
298 | s->init4 = val & 1; | |
299 | if (val & 0x02) | |
300 | printk(KERN_ERR "single mode not supported"); | |
301 | if (val & 0x08) | |
302 | printk(KERN_ERR | |
303 | "level sensitive irq not supported"); | |
304 | } else if (val & 0x08) { | |
305 | if (val & 0x04) | |
306 | s->poll = 1; | |
307 | if (val & 0x02) | |
308 | s->read_reg_select = val & 1; | |
309 | if (val & 0x40) | |
310 | s->special_mask = (val >> 5) & 1; | |
311 | } else { | |
312 | cmd = val >> 5; | |
313 | switch (cmd) { | |
314 | case 0: | |
315 | case 4: | |
316 | s->rotate_on_auto_eoi = cmd >> 2; | |
317 | break; | |
318 | case 1: /* end of interrupt */ | |
319 | case 5: | |
320 | priority = get_priority(s, s->isr); | |
321 | if (priority != 8) { | |
322 | irq = (priority + s->priority_add) & 7; | |
7edd0ce0 | 323 | pic_clear_isr(s, irq); |
85f455f7 ED |
324 | if (cmd == 5) |
325 | s->priority_add = (irq + 1) & 7; | |
326 | pic_update_irq(s->pics_state); | |
327 | } | |
328 | break; | |
329 | case 3: | |
330 | irq = val & 7; | |
7edd0ce0 | 331 | pic_clear_isr(s, irq); |
85f455f7 ED |
332 | pic_update_irq(s->pics_state); |
333 | break; | |
334 | case 6: | |
335 | s->priority_add = (val + 1) & 7; | |
336 | pic_update_irq(s->pics_state); | |
337 | break; | |
338 | case 7: | |
339 | irq = val & 7; | |
85f455f7 | 340 | s->priority_add = (irq + 1) & 7; |
7edd0ce0 | 341 | pic_clear_isr(s, irq); |
85f455f7 ED |
342 | pic_update_irq(s->pics_state); |
343 | break; | |
344 | default: | |
345 | break; /* no operation */ | |
346 | } | |
347 | } | |
348 | } else | |
349 | switch (s->init_state) { | |
350 | case 0: /* normal mode */ | |
351 | s->imr = val; | |
352 | pic_update_irq(s->pics_state); | |
353 | break; | |
354 | case 1: | |
355 | s->irq_base = val & 0xf8; | |
356 | s->init_state = 2; | |
357 | break; | |
358 | case 2: | |
359 | if (s->init4) | |
360 | s->init_state = 3; | |
361 | else | |
362 | s->init_state = 0; | |
363 | break; | |
364 | case 3: | |
365 | s->special_fully_nested_mode = (val >> 4) & 1; | |
366 | s->auto_eoi = (val >> 1) & 1; | |
367 | s->init_state = 0; | |
368 | break; | |
369 | } | |
370 | } | |
371 | ||
372 | static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) | |
373 | { | |
374 | int ret; | |
375 | ||
376 | ret = pic_get_irq(s); | |
377 | if (ret >= 0) { | |
378 | if (addr1 >> 7) { | |
379 | s->pics_state->pics[0].isr &= ~(1 << 2); | |
380 | s->pics_state->pics[0].irr &= ~(1 << 2); | |
381 | } | |
382 | s->irr &= ~(1 << ret); | |
7edd0ce0 | 383 | pic_clear_isr(s, ret); |
85f455f7 ED |
384 | if (addr1 >> 7 || ret != 2) |
385 | pic_update_irq(s->pics_state); | |
386 | } else { | |
387 | ret = 0x07; | |
388 | pic_update_irq(s->pics_state); | |
389 | } | |
390 | ||
391 | return ret; | |
392 | } | |
393 | ||
394 | static u32 pic_ioport_read(void *opaque, u32 addr1) | |
395 | { | |
396 | struct kvm_kpic_state *s = opaque; | |
397 | unsigned int addr; | |
398 | int ret; | |
399 | ||
400 | addr = addr1; | |
401 | addr &= 1; | |
402 | if (s->poll) { | |
403 | ret = pic_poll_read(s, addr1); | |
404 | s->poll = 0; | |
405 | } else | |
406 | if (addr == 0) | |
407 | if (s->read_reg_select) | |
408 | ret = s->isr; | |
409 | else | |
410 | ret = s->irr; | |
411 | else | |
412 | ret = s->imr; | |
413 | return ret; | |
414 | } | |
415 | ||
416 | static void elcr_ioport_write(void *opaque, u32 addr, u32 val) | |
417 | { | |
418 | struct kvm_kpic_state *s = opaque; | |
419 | s->elcr = val & s->elcr_mask; | |
420 | } | |
421 | ||
422 | static u32 elcr_ioport_read(void *opaque, u32 addr1) | |
423 | { | |
424 | struct kvm_kpic_state *s = opaque; | |
425 | return s->elcr; | |
426 | } | |
427 | ||
bda9020e | 428 | static int picdev_in_range(gpa_t addr) |
85f455f7 ED |
429 | { |
430 | switch (addr) { | |
431 | case 0x20: | |
432 | case 0x21: | |
433 | case 0xa0: | |
434 | case 0xa1: | |
435 | case 0x4d0: | |
436 | case 0x4d1: | |
437 | return 1; | |
438 | default: | |
439 | return 0; | |
440 | } | |
441 | } | |
442 | ||
d76685c4 GH |
443 | static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) |
444 | { | |
445 | return container_of(dev, struct kvm_pic, dev); | |
446 | } | |
447 | ||
bda9020e | 448 | static int picdev_write(struct kvm_io_device *this, |
85f455f7 ED |
449 | gpa_t addr, int len, const void *val) |
450 | { | |
d76685c4 | 451 | struct kvm_pic *s = to_pic(this); |
85f455f7 | 452 | unsigned char data = *(unsigned char *)val; |
bda9020e MT |
453 | if (!picdev_in_range(addr)) |
454 | return -EOPNOTSUPP; | |
85f455f7 ED |
455 | |
456 | if (len != 1) { | |
457 | if (printk_ratelimit()) | |
458 | printk(KERN_ERR "PIC: non byte write\n"); | |
bda9020e | 459 | return 0; |
85f455f7 | 460 | } |
3f353858 | 461 | pic_lock(s); |
85f455f7 ED |
462 | switch (addr) { |
463 | case 0x20: | |
464 | case 0x21: | |
465 | case 0xa0: | |
466 | case 0xa1: | |
467 | pic_ioport_write(&s->pics[addr >> 7], addr, data); | |
468 | break; | |
469 | case 0x4d0: | |
470 | case 0x4d1: | |
471 | elcr_ioport_write(&s->pics[addr & 1], addr, data); | |
472 | break; | |
473 | } | |
3f353858 | 474 | pic_unlock(s); |
bda9020e | 475 | return 0; |
85f455f7 ED |
476 | } |
477 | ||
bda9020e MT |
478 | static int picdev_read(struct kvm_io_device *this, |
479 | gpa_t addr, int len, void *val) | |
85f455f7 | 480 | { |
d76685c4 | 481 | struct kvm_pic *s = to_pic(this); |
85f455f7 | 482 | unsigned char data = 0; |
bda9020e MT |
483 | if (!picdev_in_range(addr)) |
484 | return -EOPNOTSUPP; | |
85f455f7 ED |
485 | |
486 | if (len != 1) { | |
487 | if (printk_ratelimit()) | |
488 | printk(KERN_ERR "PIC: non byte read\n"); | |
bda9020e | 489 | return 0; |
85f455f7 | 490 | } |
3f353858 | 491 | pic_lock(s); |
85f455f7 ED |
492 | switch (addr) { |
493 | case 0x20: | |
494 | case 0x21: | |
495 | case 0xa0: | |
496 | case 0xa1: | |
497 | data = pic_ioport_read(&s->pics[addr >> 7], addr); | |
498 | break; | |
499 | case 0x4d0: | |
500 | case 0x4d1: | |
501 | data = elcr_ioport_read(&s->pics[addr & 1], addr); | |
502 | break; | |
503 | } | |
504 | *(unsigned char *)val = data; | |
3f353858 | 505 | pic_unlock(s); |
bda9020e | 506 | return 0; |
85f455f7 ED |
507 | } |
508 | ||
509 | /* | |
510 | * callback when PIC0 irq status changed | |
511 | */ | |
512 | static void pic_irq_request(void *opaque, int level) | |
513 | { | |
514 | struct kvm *kvm = opaque; | |
c5af89b6 | 515 | struct kvm_vcpu *vcpu = kvm->bsp_vcpu; |
e4825800 MT |
516 | struct kvm_pic *s = pic_irqchip(kvm); |
517 | int irq = pic_get_irq(&s->pics[0]); | |
85f455f7 | 518 | |
e4825800 MT |
519 | s->output = level; |
520 | if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { | |
521 | s->pics[0].isr_ack &= ~(1 << irq); | |
956f97cf | 522 | kvm_vcpu_kick(vcpu); |
e4825800 | 523 | } |
85f455f7 ED |
524 | } |
525 | ||
d76685c4 GH |
526 | static const struct kvm_io_device_ops picdev_ops = { |
527 | .read = picdev_read, | |
528 | .write = picdev_write, | |
d76685c4 GH |
529 | }; |
530 | ||
85f455f7 ED |
531 | struct kvm_pic *kvm_create_pic(struct kvm *kvm) |
532 | { | |
533 | struct kvm_pic *s; | |
090b7aff GH |
534 | int ret; |
535 | ||
85f455f7 ED |
536 | s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); |
537 | if (!s) | |
538 | return NULL; | |
3f353858 AK |
539 | spin_lock_init(&s->lock); |
540 | s->kvm = kvm; | |
85f455f7 ED |
541 | s->pics[0].elcr_mask = 0xf8; |
542 | s->pics[1].elcr_mask = 0xde; | |
543 | s->irq_request = pic_irq_request; | |
544 | s->irq_request_opaque = kvm; | |
545 | s->pics[0].pics_state = s; | |
546 | s->pics[1].pics_state = s; | |
547 | ||
548 | /* | |
549 | * Initialize PIO device | |
550 | */ | |
d76685c4 | 551 | kvm_iodevice_init(&s->dev, &picdev_ops); |
090b7aff GH |
552 | ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev); |
553 | if (ret < 0) { | |
554 | kfree(s); | |
555 | return NULL; | |
556 | } | |
557 | ||
85f455f7 ED |
558 | return s; |
559 | } |