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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
29 | ||
edf88417 | 30 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
31 | #include <linux/kvm.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/hrtimer.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c7c9c56c | 38 | #include <linux/export.h> |
1fd4f2a5 | 39 | #include <asm/processor.h> |
1fd4f2a5 ED |
40 | #include <asm/page.h> |
41 | #include <asm/current.h> | |
1000ff8d | 42 | #include <trace/events/kvm.h> |
82470196 ZX |
43 | |
44 | #include "ioapic.h" | |
45 | #include "lapic.h" | |
f5244726 | 46 | #include "irq.h" |
82470196 | 47 | |
0b10a1c8 | 48 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 49 | bool line_status); |
1fd4f2a5 ED |
50 | |
51 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
52 | unsigned long addr, | |
53 | unsigned long length) | |
54 | { | |
55 | unsigned long result = 0; | |
56 | ||
57 | switch (ioapic->ioregsel) { | |
58 | case IOAPIC_REG_VERSION: | |
59 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
60 | | (IOAPIC_VERSION_ID & 0xff)); | |
61 | break; | |
62 | ||
63 | case IOAPIC_REG_APIC_ID: | |
64 | case IOAPIC_REG_ARB_ID: | |
65 | result = ((ioapic->id & 0xf) << 24); | |
66 | break; | |
67 | ||
68 | default: | |
69 | { | |
70 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
71 | u64 redir_content; | |
72 | ||
a2c118bf AH |
73 | if (redir_index < IOAPIC_NUM_PINS) |
74 | redir_content = | |
75 | ioapic->redirtbl[redir_index].bits; | |
76 | else | |
77 | redir_content = ~0ULL; | |
1fd4f2a5 | 78 | |
1fd4f2a5 ED |
79 | result = (ioapic->ioregsel & 0x1) ? |
80 | (redir_content >> 32) & 0xffffffff : | |
81 | redir_content & 0xffffffff; | |
82 | break; | |
83 | } | |
84 | } | |
85 | ||
86 | return result; | |
87 | } | |
88 | ||
10606919 YZ |
89 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
90 | { | |
91 | ioapic->rtc_status.pending_eoi = 0; | |
81cdb259 | 92 | bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID); |
10606919 YZ |
93 | } |
94 | ||
4009b249 PB |
95 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
96 | ||
97 | static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) | |
98 | { | |
99 | if (WARN_ON(ioapic->rtc_status.pending_eoi < 0)) | |
100 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
101 | } | |
102 | ||
10606919 YZ |
103 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) |
104 | { | |
105 | bool new_val, old_val; | |
106 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
b0eaf450 | 107 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
10606919 YZ |
108 | union kvm_ioapic_redirect_entry *e; |
109 | ||
110 | e = &ioapic->redirtbl[RTC_GSI]; | |
111 | if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id, | |
112 | e->fields.dest_mode)) | |
113 | return; | |
114 | ||
115 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
b0eaf450 | 116 | old_val = test_bit(vcpu->vcpu_id, dest_map->map); |
10606919 YZ |
117 | |
118 | if (new_val == old_val) | |
119 | return; | |
120 | ||
121 | if (new_val) { | |
b0eaf450 PB |
122 | __set_bit(vcpu->vcpu_id, dest_map->map); |
123 | dest_map->vectors[vcpu->vcpu_id] = e->fields.vector; | |
10606919 YZ |
124 | ioapic->rtc_status.pending_eoi++; |
125 | } else { | |
b0eaf450 | 126 | __clear_bit(vcpu->vcpu_id, dest_map->map); |
10606919 | 127 | ioapic->rtc_status.pending_eoi--; |
4009b249 | 128 | rtc_status_pending_eoi_check_valid(ioapic); |
10606919 | 129 | } |
10606919 YZ |
130 | } |
131 | ||
132 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
133 | { | |
134 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
135 | ||
136 | spin_lock(&ioapic->lock); | |
137 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
138 | spin_unlock(&ioapic->lock); | |
139 | } | |
140 | ||
141 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
142 | { | |
143 | struct kvm_vcpu *vcpu; | |
144 | int i; | |
145 | ||
146 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
147 | return; | |
148 | ||
149 | rtc_irq_eoi_tracking_reset(ioapic); | |
150 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
151 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
152 | } | |
153 | ||
2c2bf011 YZ |
154 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu) |
155 | { | |
9e4aabe2 JR |
156 | if (test_and_clear_bit(vcpu->vcpu_id, |
157 | ioapic->rtc_status.dest_map.map)) { | |
2c2bf011 | 158 | --ioapic->rtc_status.pending_eoi; |
4009b249 PB |
159 | rtc_status_pending_eoi_check_valid(ioapic); |
160 | } | |
2c2bf011 YZ |
161 | } |
162 | ||
163 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
164 | { | |
165 | if (ioapic->rtc_status.pending_eoi > 0) | |
166 | return true; /* coalesced */ | |
167 | ||
168 | return false; | |
169 | } | |
170 | ||
44847dea PB |
171 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
172 | int irq_level, bool line_status) | |
173 | { | |
174 | union kvm_ioapic_redirect_entry entry; | |
175 | u32 mask = 1 << irq; | |
176 | u32 old_irr; | |
177 | int edge, ret; | |
178 | ||
179 | entry = ioapic->redirtbl[irq]; | |
180 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
181 | ||
182 | if (!irq_level) { | |
183 | ioapic->irr &= ~mask; | |
184 | ret = 1; | |
185 | goto out; | |
186 | } | |
187 | ||
188 | /* | |
189 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
190 | * this only happens if a previous edge has not been delivered due | |
191 | * do masking. For level interrupts, the remote_irr field tells | |
192 | * us if the interrupt is waiting for an EOI. | |
193 | * | |
194 | * RTC is special: it is edge-triggered, but userspace likes to know | |
195 | * if it has been already ack-ed via EOI because coalesced RTC | |
196 | * interrupts lead to time drift in Windows guests. So we track | |
197 | * EOI manually for the RTC interrupt. | |
198 | */ | |
199 | if (irq == RTC_GSI && line_status && | |
200 | rtc_irq_check_coalesced(ioapic)) { | |
201 | ret = 0; | |
202 | goto out; | |
203 | } | |
204 | ||
205 | old_irr = ioapic->irr; | |
206 | ioapic->irr |= mask; | |
7d225368 | 207 | if (edge) { |
5bda6eed | 208 | ioapic->irr_delivered &= ~mask; |
7d225368 NL |
209 | if (old_irr == ioapic->irr) { |
210 | ret = 0; | |
211 | goto out; | |
212 | } | |
44847dea PB |
213 | } |
214 | ||
215 | ret = ioapic_service(ioapic, irq, line_status); | |
216 | ||
217 | out: | |
218 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
219 | return ret; | |
220 | } | |
221 | ||
673f7b42 PB |
222 | static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) |
223 | { | |
224 | u32 idx; | |
225 | ||
226 | rtc_irq_eoi_tracking_reset(ioapic); | |
227 | for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) | |
228 | ioapic_set_irq(ioapic, idx, 1, true); | |
229 | ||
230 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
231 | } | |
232 | ||
233 | ||
6308630b | 234 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors) |
c7c9c56c YZ |
235 | { |
236 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
4d99ba89 | 237 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
c7c9c56c | 238 | union kvm_ioapic_redirect_entry *e; |
c7c9c56c YZ |
239 | int index; |
240 | ||
241 | spin_lock(&ioapic->lock); | |
4d99ba89 JR |
242 | |
243 | /* Make sure we see any missing RTC EOI */ | |
244 | if (test_bit(vcpu->vcpu_id, dest_map->map)) | |
245 | __set_bit(dest_map->vectors[vcpu->vcpu_id], | |
246 | ioapic_handled_vectors); | |
247 | ||
c7c9c56c YZ |
248 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
249 | e = &ioapic->redirtbl[index]; | |
0f6c0a74 PB |
250 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || |
251 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) || | |
252 | index == RTC_GSI) { | |
44944d4d | 253 | if (kvm_apic_match_dest(vcpu, NULL, 0, |
db2bdcbb | 254 | e->fields.dest_id, e->fields.dest_mode) || |
0fc5a36d | 255 | kvm_apic_pending_eoi(vcpu, e->fields.vector)) |
cf9e65b7 | 256 | __set_bit(e->fields.vector, |
6308630b | 257 | ioapic_handled_vectors); |
c7c9c56c YZ |
258 | } |
259 | } | |
260 | spin_unlock(&ioapic->lock); | |
261 | } | |
c7c9c56c | 262 | |
993225ad | 263 | void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm) |
c7c9c56c | 264 | { |
0bceb15a | 265 | if (!ioapic_in_kernel(kvm)) |
c7c9c56c | 266 | return; |
3d81bc7e | 267 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c YZ |
268 | } |
269 | ||
1fd4f2a5 ED |
270 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
271 | { | |
272 | unsigned index; | |
75858a84 | 273 | bool mask_before, mask_after; |
b200dded | 274 | int old_remote_irr, old_delivery_status; |
70f93dae | 275 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
276 | |
277 | switch (ioapic->ioregsel) { | |
278 | case IOAPIC_REG_VERSION: | |
279 | /* Writes are ignored. */ | |
280 | break; | |
281 | ||
282 | case IOAPIC_REG_APIC_ID: | |
283 | ioapic->id = (val >> 24) & 0xf; | |
284 | break; | |
285 | ||
286 | case IOAPIC_REG_ARB_ID: | |
287 | break; | |
288 | ||
289 | default: | |
290 | index = (ioapic->ioregsel - 0x10) >> 1; | |
291 | ||
1fd4f2a5 ED |
292 | if (index >= IOAPIC_NUM_PINS) |
293 | return; | |
70f93dae GN |
294 | e = &ioapic->redirtbl[index]; |
295 | mask_before = e->fields.mask; | |
b200dded NL |
296 | /* Preserve read-only fields */ |
297 | old_remote_irr = e->fields.remote_irr; | |
298 | old_delivery_status = e->fields.delivery_status; | |
1fd4f2a5 | 299 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
300 | e->bits &= 0xffffffff; |
301 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 302 | } else { |
70f93dae GN |
303 | e->bits &= ~0xffffffffULL; |
304 | e->bits |= (u32) val; | |
1fd4f2a5 | 305 | } |
b200dded NL |
306 | e->fields.remote_irr = old_remote_irr; |
307 | e->fields.delivery_status = old_delivery_status; | |
a8bfec29 NL |
308 | |
309 | /* | |
310 | * Some OSes (Linux, Xen) assume that Remote IRR bit will | |
311 | * be cleared by IOAPIC hardware when the entry is configured | |
312 | * as edge-triggered. This behavior is used to simulate an | |
313 | * explicit EOI on IOAPICs that don't have the EOI register. | |
314 | */ | |
315 | if (e->fields.trig_mode == IOAPIC_EDGE_TRIG) | |
316 | e->fields.remote_irr = 0; | |
317 | ||
70f93dae | 318 | mask_after = e->fields.mask; |
75858a84 | 319 | if (mask_before != mask_after) |
4a994358 | 320 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
70f93dae | 321 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 322 | && ioapic->irr & (1 << index)) |
aa2fbe6d | 323 | ioapic_service(ioapic, index, false); |
ca8ab3f8 | 324 | kvm_make_scan_ioapic_request(ioapic->kvm); |
1fd4f2a5 ED |
325 | break; |
326 | } | |
327 | } | |
328 | ||
0b10a1c8 | 329 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 330 | { |
58c2dde1 GN |
331 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
332 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 333 | int ret; |
a53c17d2 | 334 | |
da3fe7bd NL |
335 | if (entry->fields.mask || |
336 | (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG && | |
337 | entry->fields.remote_irr)) | |
0b10a1c8 PB |
338 | return -1; |
339 | ||
58c2dde1 GN |
340 | irqe.dest_id = entry->fields.dest_id; |
341 | irqe.vector = entry->fields.vector; | |
342 | irqe.dest_mode = entry->fields.dest_mode; | |
343 | irqe.trig_mode = entry->fields.trig_mode; | |
344 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
345 | irqe.level = 1; | |
346 | irqe.shorthand = 0; | |
93bbf0b8 | 347 | irqe.msi_redir_hint = false; |
a53c17d2 | 348 | |
0bc830b0 | 349 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
5bda6eed | 350 | ioapic->irr_delivered |= 1 << irq; |
0bc830b0 | 351 | |
2c2bf011 | 352 | if (irq == RTC_GSI && line_status) { |
4009b249 PB |
353 | /* |
354 | * pending_eoi cannot ever become negative (see | |
355 | * rtc_status_pending_eoi_check_valid) and the caller | |
356 | * ensures that it is only called if it is >= zero, namely | |
357 | * if rtc_irq_check_coalesced returns false). | |
358 | */ | |
2c2bf011 YZ |
359 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); |
360 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
9e4aabe2 | 361 | &ioapic->rtc_status.dest_map); |
5678de3f | 362 | ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); |
2c2bf011 YZ |
363 | } else |
364 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
365 | ||
0b10a1c8 PB |
366 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
367 | entry->fields.remote_irr = 1; | |
368 | ||
2c2bf011 | 369 | return ret; |
a53c17d2 GN |
370 | } |
371 | ||
1a577b72 | 372 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 373 | int level, bool line_status) |
1fd4f2a5 | 374 | { |
28a6fdab MT |
375 | int ret, irq_level; |
376 | ||
377 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 378 | |
46a47b1e | 379 | spin_lock(&ioapic->lock); |
28a6fdab MT |
380 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
381 | irq_source_id, level); | |
44847dea | 382 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 383 | |
46a47b1e | 384 | spin_unlock(&ioapic->lock); |
eba0226b | 385 | |
4925663a | 386 | return ret; |
1fd4f2a5 ED |
387 | } |
388 | ||
1a577b72 MT |
389 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
390 | { | |
391 | int i; | |
392 | ||
393 | spin_lock(&ioapic->lock); | |
394 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
395 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
396 | spin_unlock(&ioapic->lock); | |
397 | } | |
398 | ||
184564ef ZH |
399 | static void kvm_ioapic_eoi_inject_work(struct work_struct *work) |
400 | { | |
401 | int i; | |
402 | struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic, | |
403 | eoi_inject.work); | |
404 | spin_lock(&ioapic->lock); | |
405 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
406 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
407 | ||
408 | if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG) | |
409 | continue; | |
410 | ||
411 | if (ioapic->irr & (1 << i) && !ent->fields.remote_irr) | |
412 | ioapic_service(ioapic, i, false); | |
413 | } | |
414 | spin_unlock(&ioapic->lock); | |
415 | } | |
416 | ||
417 | #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000 | |
418 | ||
1fcc7890 YZ |
419 | static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, |
420 | struct kvm_ioapic *ioapic, int vector, int trigger_mode) | |
1fd4f2a5 | 421 | { |
4d99ba89 | 422 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
c806a6ad | 423 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d99ba89 JR |
424 | int i; |
425 | ||
426 | /* RTC special handling */ | |
427 | if (test_bit(vcpu->vcpu_id, dest_map->map) && | |
428 | vector == dest_map->vectors[vcpu->vcpu_id]) | |
429 | rtc_irq_eoi(ioapic, vcpu); | |
eba0226b GN |
430 | |
431 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
432 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 433 | |
eba0226b GN |
434 | if (ent->fields.vector != vector) |
435 | continue; | |
1fd4f2a5 | 436 | |
eba0226b GN |
437 | /* |
438 | * We are dropping lock while calling ack notifiers because ack | |
439 | * notifier callbacks for assigned devices call into IOAPIC | |
440 | * recursively. Since remote_irr is cleared only after call | |
441 | * to notifiers if the same vector will be delivered while lock | |
442 | * is dropped it will be put into irr and will be delivered | |
443 | * after ack notifier returns. | |
444 | */ | |
46a47b1e | 445 | spin_unlock(&ioapic->lock); |
eba0226b | 446 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 447 | spin_lock(&ioapic->lock); |
eba0226b | 448 | |
c806a6ad | 449 | if (trigger_mode != IOAPIC_LEVEL_TRIG || |
dfb95954 | 450 | kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) |
eba0226b | 451 | continue; |
f5244726 | 452 | |
f5244726 MT |
453 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
454 | ent->fields.remote_irr = 0; | |
184564ef ZH |
455 | if (!ent->fields.mask && (ioapic->irr & (1 << i))) { |
456 | ++ioapic->irq_eoi[i]; | |
457 | if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) { | |
458 | /* | |
459 | * Real hardware does not deliver the interrupt | |
460 | * immediately during eoi broadcast, and this | |
461 | * lets a buggy guest make slow progress | |
462 | * even if it does not correctly handle a | |
463 | * level-triggered interrupt. Emulate this | |
464 | * behavior if we detect an interrupt storm. | |
465 | */ | |
466 | schedule_delayed_work(&ioapic->eoi_inject, HZ / 100); | |
467 | ioapic->irq_eoi[i] = 0; | |
468 | trace_kvm_ioapic_delayed_eoi_inj(ent->bits); | |
469 | } else { | |
470 | ioapic_service(ioapic, i, false); | |
471 | } | |
472 | } else { | |
473 | ioapic->irq_eoi[i] = 0; | |
474 | } | |
f5244726 | 475 | } |
1fd4f2a5 ED |
476 | } |
477 | ||
1fcc7890 | 478 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 479 | { |
1fcc7890 | 480 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 481 | |
46a47b1e | 482 | spin_lock(&ioapic->lock); |
1fcc7890 | 483 | __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode); |
46a47b1e | 484 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
485 | } |
486 | ||
d76685c4 GH |
487 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
488 | { | |
489 | return container_of(dev, struct kvm_ioapic, dev); | |
490 | } | |
491 | ||
bda9020e | 492 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 493 | { |
1fd4f2a5 ED |
494 | return ((addr >= ioapic->base_address && |
495 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
496 | } | |
497 | ||
e32edf4f NN |
498 | static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
499 | gpa_t addr, int len, void *val) | |
1fd4f2a5 | 500 | { |
d76685c4 | 501 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 502 | u32 result; |
bda9020e MT |
503 | if (!ioapic_in_range(ioapic, addr)) |
504 | return -EOPNOTSUPP; | |
1fd4f2a5 | 505 | |
1fd4f2a5 ED |
506 | ASSERT(!(addr & 0xf)); /* check alignment */ |
507 | ||
508 | addr &= 0xff; | |
46a47b1e | 509 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
510 | switch (addr) { |
511 | case IOAPIC_REG_SELECT: | |
512 | result = ioapic->ioregsel; | |
513 | break; | |
514 | ||
515 | case IOAPIC_REG_WINDOW: | |
516 | result = ioapic_read_indirect(ioapic, addr, len); | |
517 | break; | |
518 | ||
519 | default: | |
520 | result = 0; | |
521 | break; | |
522 | } | |
46a47b1e | 523 | spin_unlock(&ioapic->lock); |
eba0226b | 524 | |
1fd4f2a5 ED |
525 | switch (len) { |
526 | case 8: | |
527 | *(u64 *) val = result; | |
528 | break; | |
529 | case 1: | |
530 | case 2: | |
531 | case 4: | |
532 | memcpy(val, (char *)&result, len); | |
533 | break; | |
534 | default: | |
535 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
536 | } | |
bda9020e | 537 | return 0; |
1fd4f2a5 ED |
538 | } |
539 | ||
e32edf4f NN |
540 | static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
541 | gpa_t addr, int len, const void *val) | |
1fd4f2a5 | 542 | { |
d76685c4 | 543 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 544 | u32 data; |
bda9020e MT |
545 | if (!ioapic_in_range(ioapic, addr)) |
546 | return -EOPNOTSUPP; | |
1fd4f2a5 | 547 | |
1fd4f2a5 | 548 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 549 | |
d77fe635 JS |
550 | switch (len) { |
551 | case 8: | |
552 | case 4: | |
1fd4f2a5 | 553 | data = *(u32 *) val; |
d77fe635 JS |
554 | break; |
555 | case 2: | |
556 | data = *(u16 *) val; | |
557 | break; | |
558 | case 1: | |
559 | data = *(u8 *) val; | |
560 | break; | |
561 | default: | |
1fd4f2a5 | 562 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 563 | return 0; |
1fd4f2a5 ED |
564 | } |
565 | ||
566 | addr &= 0xff; | |
46a47b1e | 567 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
568 | switch (addr) { |
569 | case IOAPIC_REG_SELECT: | |
d77fe635 | 570 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
571 | break; |
572 | ||
573 | case IOAPIC_REG_WINDOW: | |
574 | ioapic_write_indirect(ioapic, data); | |
575 | break; | |
576 | ||
577 | default: | |
578 | break; | |
579 | } | |
46a47b1e | 580 | spin_unlock(&ioapic->lock); |
bda9020e | 581 | return 0; |
1fd4f2a5 ED |
582 | } |
583 | ||
7940876e | 584 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
585 | { |
586 | int i; | |
587 | ||
184564ef | 588 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
8c392696 ED |
589 | for (i = 0; i < IOAPIC_NUM_PINS; i++) |
590 | ioapic->redirtbl[i].fields.mask = 1; | |
591 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
592 | ioapic->ioregsel = 0; | |
593 | ioapic->irr = 0; | |
5bda6eed | 594 | ioapic->irr_delivered = 0; |
8c392696 | 595 | ioapic->id = 0; |
8678654e | 596 | memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi)); |
10606919 | 597 | rtc_irq_eoi_tracking_reset(ioapic); |
8c392696 ED |
598 | } |
599 | ||
d76685c4 GH |
600 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
601 | .read = ioapic_mmio_read, | |
602 | .write = ioapic_mmio_write, | |
d76685c4 GH |
603 | }; |
604 | ||
1fd4f2a5 ED |
605 | int kvm_ioapic_init(struct kvm *kvm) |
606 | { | |
607 | struct kvm_ioapic *ioapic; | |
090b7aff | 608 | int ret; |
1fd4f2a5 | 609 | |
254272ce | 610 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT); |
1fd4f2a5 ED |
611 | if (!ioapic) |
612 | return -ENOMEM; | |
46a47b1e | 613 | spin_lock_init(&ioapic->lock); |
184564ef | 614 | INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work); |
d7deeeb0 | 615 | kvm->arch.vioapic = ioapic; |
8c392696 | 616 | kvm_ioapic_reset(ioapic); |
d76685c4 | 617 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 618 | ioapic->kvm = kvm; |
79fac95e | 619 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
620 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
621 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 622 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
623 | if (ret < 0) { |
624 | kvm->arch.vioapic = NULL; | |
090b7aff | 625 | kfree(ioapic); |
1ae77bad | 626 | } |
090b7aff GH |
627 | |
628 | return ret; | |
1fd4f2a5 | 629 | } |
75858a84 | 630 | |
72bb2fcd WY |
631 | void kvm_ioapic_destroy(struct kvm *kvm) |
632 | { | |
633 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
634 | ||
950712eb PX |
635 | if (!ioapic) |
636 | return; | |
637 | ||
184564ef | 638 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
49f520b9 | 639 | mutex_lock(&kvm->slots_lock); |
d90e3a35 | 640 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); |
49f520b9 | 641 | mutex_unlock(&kvm->slots_lock); |
d90e3a35 JL |
642 | kvm->arch.vioapic = NULL; |
643 | kfree(ioapic); | |
72bb2fcd WY |
644 | } |
645 | ||
33392b49 | 646 | void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
eba0226b | 647 | { |
0191e92d | 648 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
eba0226b | 649 | |
46a47b1e | 650 | spin_lock(&ioapic->lock); |
eba0226b | 651 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
5bda6eed | 652 | state->irr &= ~ioapic->irr_delivered; |
46a47b1e | 653 | spin_unlock(&ioapic->lock); |
eba0226b GN |
654 | } |
655 | ||
33392b49 | 656 | void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
eba0226b | 657 | { |
0191e92d | 658 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
eba0226b | 659 | |
46a47b1e | 660 | spin_lock(&ioapic->lock); |
eba0226b | 661 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
673f7b42 | 662 | ioapic->irr = 0; |
5bda6eed | 663 | ioapic->irr_delivered = 0; |
ca8ab3f8 | 664 | kvm_make_scan_ioapic_request(kvm); |
673f7b42 | 665 | kvm_ioapic_inject_all(ioapic, state->irr); |
46a47b1e | 666 | spin_unlock(&ioapic->lock); |
eba0226b | 667 | } |