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Commit | Line | Data |
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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
29 | ||
edf88417 | 30 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
31 | #include <linux/kvm.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/hrtimer.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c7c9c56c | 38 | #include <linux/export.h> |
1fd4f2a5 | 39 | #include <asm/processor.h> |
1fd4f2a5 ED |
40 | #include <asm/page.h> |
41 | #include <asm/current.h> | |
1000ff8d | 42 | #include <trace/events/kvm.h> |
82470196 ZX |
43 | |
44 | #include "ioapic.h" | |
45 | #include "lapic.h" | |
f5244726 | 46 | #include "irq.h" |
82470196 | 47 | |
e25e3ed5 LV |
48 | #if 0 |
49 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
50 | #else | |
1fd4f2a5 | 51 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 52 | #endif |
0b10a1c8 | 53 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 54 | bool line_status); |
1fd4f2a5 ED |
55 | |
56 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
57 | unsigned long addr, | |
58 | unsigned long length) | |
59 | { | |
60 | unsigned long result = 0; | |
61 | ||
62 | switch (ioapic->ioregsel) { | |
63 | case IOAPIC_REG_VERSION: | |
64 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
65 | | (IOAPIC_VERSION_ID & 0xff)); | |
66 | break; | |
67 | ||
68 | case IOAPIC_REG_APIC_ID: | |
69 | case IOAPIC_REG_ARB_ID: | |
70 | result = ((ioapic->id & 0xf) << 24); | |
71 | break; | |
72 | ||
73 | default: | |
74 | { | |
75 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
76 | u64 redir_content; | |
77 | ||
a2c118bf AH |
78 | if (redir_index < IOAPIC_NUM_PINS) |
79 | redir_content = | |
80 | ioapic->redirtbl[redir_index].bits; | |
81 | else | |
82 | redir_content = ~0ULL; | |
1fd4f2a5 | 83 | |
1fd4f2a5 ED |
84 | result = (ioapic->ioregsel & 0x1) ? |
85 | (redir_content >> 32) & 0xffffffff : | |
86 | redir_content & 0xffffffff; | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | return result; | |
92 | } | |
93 | ||
10606919 YZ |
94 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
95 | { | |
96 | ioapic->rtc_status.pending_eoi = 0; | |
81cdb259 | 97 | bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID); |
10606919 YZ |
98 | } |
99 | ||
4009b249 PB |
100 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
101 | ||
102 | static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) | |
103 | { | |
104 | if (WARN_ON(ioapic->rtc_status.pending_eoi < 0)) | |
105 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
106 | } | |
107 | ||
10606919 YZ |
108 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) |
109 | { | |
110 | bool new_val, old_val; | |
111 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
b0eaf450 | 112 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
10606919 YZ |
113 | union kvm_ioapic_redirect_entry *e; |
114 | ||
115 | e = &ioapic->redirtbl[RTC_GSI]; | |
116 | if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id, | |
117 | e->fields.dest_mode)) | |
118 | return; | |
119 | ||
120 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
b0eaf450 | 121 | old_val = test_bit(vcpu->vcpu_id, dest_map->map); |
10606919 YZ |
122 | |
123 | if (new_val == old_val) | |
124 | return; | |
125 | ||
126 | if (new_val) { | |
b0eaf450 PB |
127 | __set_bit(vcpu->vcpu_id, dest_map->map); |
128 | dest_map->vectors[vcpu->vcpu_id] = e->fields.vector; | |
10606919 YZ |
129 | ioapic->rtc_status.pending_eoi++; |
130 | } else { | |
b0eaf450 | 131 | __clear_bit(vcpu->vcpu_id, dest_map->map); |
10606919 | 132 | ioapic->rtc_status.pending_eoi--; |
4009b249 | 133 | rtc_status_pending_eoi_check_valid(ioapic); |
10606919 | 134 | } |
10606919 YZ |
135 | } |
136 | ||
137 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
138 | { | |
139 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
140 | ||
141 | spin_lock(&ioapic->lock); | |
142 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
143 | spin_unlock(&ioapic->lock); | |
144 | } | |
145 | ||
146 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
147 | { | |
148 | struct kvm_vcpu *vcpu; | |
149 | int i; | |
150 | ||
151 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
152 | return; | |
153 | ||
154 | rtc_irq_eoi_tracking_reset(ioapic); | |
155 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
156 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
157 | } | |
158 | ||
2c2bf011 YZ |
159 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu) |
160 | { | |
9e4aabe2 JR |
161 | if (test_and_clear_bit(vcpu->vcpu_id, |
162 | ioapic->rtc_status.dest_map.map)) { | |
2c2bf011 | 163 | --ioapic->rtc_status.pending_eoi; |
4009b249 PB |
164 | rtc_status_pending_eoi_check_valid(ioapic); |
165 | } | |
2c2bf011 YZ |
166 | } |
167 | ||
168 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
169 | { | |
170 | if (ioapic->rtc_status.pending_eoi > 0) | |
171 | return true; /* coalesced */ | |
172 | ||
173 | return false; | |
174 | } | |
175 | ||
44847dea PB |
176 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
177 | int irq_level, bool line_status) | |
178 | { | |
179 | union kvm_ioapic_redirect_entry entry; | |
180 | u32 mask = 1 << irq; | |
181 | u32 old_irr; | |
182 | int edge, ret; | |
183 | ||
184 | entry = ioapic->redirtbl[irq]; | |
185 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
186 | ||
187 | if (!irq_level) { | |
188 | ioapic->irr &= ~mask; | |
189 | ret = 1; | |
190 | goto out; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
195 | * this only happens if a previous edge has not been delivered due | |
196 | * do masking. For level interrupts, the remote_irr field tells | |
197 | * us if the interrupt is waiting for an EOI. | |
198 | * | |
199 | * RTC is special: it is edge-triggered, but userspace likes to know | |
200 | * if it has been already ack-ed via EOI because coalesced RTC | |
201 | * interrupts lead to time drift in Windows guests. So we track | |
202 | * EOI manually for the RTC interrupt. | |
203 | */ | |
204 | if (irq == RTC_GSI && line_status && | |
205 | rtc_irq_check_coalesced(ioapic)) { | |
206 | ret = 0; | |
207 | goto out; | |
208 | } | |
209 | ||
210 | old_irr = ioapic->irr; | |
211 | ioapic->irr |= mask; | |
5bda6eed WV |
212 | if (edge) |
213 | ioapic->irr_delivered &= ~mask; | |
44847dea PB |
214 | if ((edge && old_irr == ioapic->irr) || |
215 | (!edge && entry.fields.remote_irr)) { | |
216 | ret = 0; | |
217 | goto out; | |
218 | } | |
219 | ||
220 | ret = ioapic_service(ioapic, irq, line_status); | |
221 | ||
222 | out: | |
223 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
224 | return ret; | |
225 | } | |
226 | ||
673f7b42 PB |
227 | static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) |
228 | { | |
229 | u32 idx; | |
230 | ||
231 | rtc_irq_eoi_tracking_reset(ioapic); | |
232 | for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) | |
233 | ioapic_set_irq(ioapic, idx, 1, true); | |
234 | ||
235 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
236 | } | |
237 | ||
238 | ||
6308630b | 239 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors) |
c7c9c56c YZ |
240 | { |
241 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
4d99ba89 | 242 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
c7c9c56c | 243 | union kvm_ioapic_redirect_entry *e; |
c7c9c56c YZ |
244 | int index; |
245 | ||
246 | spin_lock(&ioapic->lock); | |
4d99ba89 JR |
247 | |
248 | /* Make sure we see any missing RTC EOI */ | |
249 | if (test_bit(vcpu->vcpu_id, dest_map->map)) | |
250 | __set_bit(dest_map->vectors[vcpu->vcpu_id], | |
251 | ioapic_handled_vectors); | |
252 | ||
c7c9c56c YZ |
253 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
254 | e = &ioapic->redirtbl[index]; | |
0f6c0a74 PB |
255 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || |
256 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) || | |
257 | index == RTC_GSI) { | |
44944d4d | 258 | if (kvm_apic_match_dest(vcpu, NULL, 0, |
db2bdcbb RK |
259 | e->fields.dest_id, e->fields.dest_mode) || |
260 | (e->fields.trig_mode == IOAPIC_EDGE_TRIG && | |
261 | kvm_apic_pending_eoi(vcpu, e->fields.vector))) | |
cf9e65b7 | 262 | __set_bit(e->fields.vector, |
6308630b | 263 | ioapic_handled_vectors); |
c7c9c56c YZ |
264 | } |
265 | } | |
266 | spin_unlock(&ioapic->lock); | |
267 | } | |
c7c9c56c | 268 | |
3d81bc7e | 269 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) |
c7c9c56c YZ |
270 | { |
271 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
272 | ||
3d81bc7e | 273 | if (!ioapic) |
c7c9c56c | 274 | return; |
3d81bc7e | 275 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c YZ |
276 | } |
277 | ||
1fd4f2a5 ED |
278 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
279 | { | |
280 | unsigned index; | |
75858a84 | 281 | bool mask_before, mask_after; |
70f93dae | 282 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
283 | |
284 | switch (ioapic->ioregsel) { | |
285 | case IOAPIC_REG_VERSION: | |
286 | /* Writes are ignored. */ | |
287 | break; | |
288 | ||
289 | case IOAPIC_REG_APIC_ID: | |
290 | ioapic->id = (val >> 24) & 0xf; | |
291 | break; | |
292 | ||
293 | case IOAPIC_REG_ARB_ID: | |
294 | break; | |
295 | ||
296 | default: | |
297 | index = (ioapic->ioregsel - 0x10) >> 1; | |
298 | ||
e25e3ed5 | 299 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
300 | if (index >= IOAPIC_NUM_PINS) |
301 | return; | |
70f93dae GN |
302 | e = &ioapic->redirtbl[index]; |
303 | mask_before = e->fields.mask; | |
1fd4f2a5 | 304 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
305 | e->bits &= 0xffffffff; |
306 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 307 | } else { |
70f93dae GN |
308 | e->bits &= ~0xffffffffULL; |
309 | e->bits |= (u32) val; | |
310 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 311 | } |
70f93dae | 312 | mask_after = e->fields.mask; |
75858a84 | 313 | if (mask_before != mask_after) |
4a994358 | 314 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
70f93dae | 315 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 316 | && ioapic->irr & (1 << index)) |
aa2fbe6d | 317 | ioapic_service(ioapic, index, false); |
3d81bc7e | 318 | kvm_vcpu_request_scan_ioapic(ioapic->kvm); |
1fd4f2a5 ED |
319 | break; |
320 | } | |
321 | } | |
322 | ||
0b10a1c8 | 323 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 324 | { |
58c2dde1 GN |
325 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
326 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 327 | int ret; |
a53c17d2 | 328 | |
0b10a1c8 PB |
329 | if (entry->fields.mask) |
330 | return -1; | |
331 | ||
a53c17d2 GN |
332 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " |
333 | "vector=%x trig_mode=%x\n", | |
a38f84ca | 334 | entry->fields.dest_id, entry->fields.dest_mode, |
58c2dde1 GN |
335 | entry->fields.delivery_mode, entry->fields.vector, |
336 | entry->fields.trig_mode); | |
337 | ||
338 | irqe.dest_id = entry->fields.dest_id; | |
339 | irqe.vector = entry->fields.vector; | |
340 | irqe.dest_mode = entry->fields.dest_mode; | |
341 | irqe.trig_mode = entry->fields.trig_mode; | |
342 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
343 | irqe.level = 1; | |
344 | irqe.shorthand = 0; | |
93bbf0b8 | 345 | irqe.msi_redir_hint = false; |
a53c17d2 | 346 | |
0bc830b0 | 347 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
5bda6eed | 348 | ioapic->irr_delivered |= 1 << irq; |
0bc830b0 | 349 | |
2c2bf011 | 350 | if (irq == RTC_GSI && line_status) { |
4009b249 PB |
351 | /* |
352 | * pending_eoi cannot ever become negative (see | |
353 | * rtc_status_pending_eoi_check_valid) and the caller | |
354 | * ensures that it is only called if it is >= zero, namely | |
355 | * if rtc_irq_check_coalesced returns false). | |
356 | */ | |
2c2bf011 YZ |
357 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); |
358 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
9e4aabe2 | 359 | &ioapic->rtc_status.dest_map); |
5678de3f | 360 | ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); |
2c2bf011 YZ |
361 | } else |
362 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
363 | ||
0b10a1c8 PB |
364 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
365 | entry->fields.remote_irr = 1; | |
366 | ||
2c2bf011 | 367 | return ret; |
a53c17d2 GN |
368 | } |
369 | ||
1a577b72 | 370 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 371 | int level, bool line_status) |
1fd4f2a5 | 372 | { |
28a6fdab MT |
373 | int ret, irq_level; |
374 | ||
375 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 376 | |
46a47b1e | 377 | spin_lock(&ioapic->lock); |
28a6fdab MT |
378 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
379 | irq_source_id, level); | |
44847dea | 380 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 381 | |
46a47b1e | 382 | spin_unlock(&ioapic->lock); |
eba0226b | 383 | |
4925663a | 384 | return ret; |
1fd4f2a5 ED |
385 | } |
386 | ||
1a577b72 MT |
387 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
388 | { | |
389 | int i; | |
390 | ||
391 | spin_lock(&ioapic->lock); | |
392 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
393 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
394 | spin_unlock(&ioapic->lock); | |
395 | } | |
396 | ||
184564ef ZH |
397 | static void kvm_ioapic_eoi_inject_work(struct work_struct *work) |
398 | { | |
399 | int i; | |
400 | struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic, | |
401 | eoi_inject.work); | |
402 | spin_lock(&ioapic->lock); | |
403 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
404 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
405 | ||
406 | if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG) | |
407 | continue; | |
408 | ||
409 | if (ioapic->irr & (1 << i) && !ent->fields.remote_irr) | |
410 | ioapic_service(ioapic, i, false); | |
411 | } | |
412 | spin_unlock(&ioapic->lock); | |
413 | } | |
414 | ||
415 | #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000 | |
416 | ||
1fcc7890 YZ |
417 | static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, |
418 | struct kvm_ioapic *ioapic, int vector, int trigger_mode) | |
1fd4f2a5 | 419 | { |
4d99ba89 | 420 | struct dest_map *dest_map = &ioapic->rtc_status.dest_map; |
c806a6ad | 421 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d99ba89 JR |
422 | int i; |
423 | ||
424 | /* RTC special handling */ | |
425 | if (test_bit(vcpu->vcpu_id, dest_map->map) && | |
426 | vector == dest_map->vectors[vcpu->vcpu_id]) | |
427 | rtc_irq_eoi(ioapic, vcpu); | |
eba0226b GN |
428 | |
429 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
430 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 431 | |
eba0226b GN |
432 | if (ent->fields.vector != vector) |
433 | continue; | |
1fd4f2a5 | 434 | |
eba0226b GN |
435 | /* |
436 | * We are dropping lock while calling ack notifiers because ack | |
437 | * notifier callbacks for assigned devices call into IOAPIC | |
438 | * recursively. Since remote_irr is cleared only after call | |
439 | * to notifiers if the same vector will be delivered while lock | |
440 | * is dropped it will be put into irr and will be delivered | |
441 | * after ack notifier returns. | |
442 | */ | |
46a47b1e | 443 | spin_unlock(&ioapic->lock); |
eba0226b | 444 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 445 | spin_lock(&ioapic->lock); |
eba0226b | 446 | |
c806a6ad | 447 | if (trigger_mode != IOAPIC_LEVEL_TRIG || |
dfb95954 | 448 | kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) |
eba0226b | 449 | continue; |
f5244726 | 450 | |
f5244726 MT |
451 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
452 | ent->fields.remote_irr = 0; | |
184564ef ZH |
453 | if (!ent->fields.mask && (ioapic->irr & (1 << i))) { |
454 | ++ioapic->irq_eoi[i]; | |
455 | if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) { | |
456 | /* | |
457 | * Real hardware does not deliver the interrupt | |
458 | * immediately during eoi broadcast, and this | |
459 | * lets a buggy guest make slow progress | |
460 | * even if it does not correctly handle a | |
461 | * level-triggered interrupt. Emulate this | |
462 | * behavior if we detect an interrupt storm. | |
463 | */ | |
464 | schedule_delayed_work(&ioapic->eoi_inject, HZ / 100); | |
465 | ioapic->irq_eoi[i] = 0; | |
466 | trace_kvm_ioapic_delayed_eoi_inj(ent->bits); | |
467 | } else { | |
468 | ioapic_service(ioapic, i, false); | |
469 | } | |
470 | } else { | |
471 | ioapic->irq_eoi[i] = 0; | |
472 | } | |
f5244726 | 473 | } |
1fd4f2a5 ED |
474 | } |
475 | ||
1fcc7890 | 476 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 477 | { |
1fcc7890 | 478 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 479 | |
46a47b1e | 480 | spin_lock(&ioapic->lock); |
1fcc7890 | 481 | __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode); |
46a47b1e | 482 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
483 | } |
484 | ||
d76685c4 GH |
485 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
486 | { | |
487 | return container_of(dev, struct kvm_ioapic, dev); | |
488 | } | |
489 | ||
bda9020e | 490 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 491 | { |
1fd4f2a5 ED |
492 | return ((addr >= ioapic->base_address && |
493 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
494 | } | |
495 | ||
e32edf4f NN |
496 | static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
497 | gpa_t addr, int len, void *val) | |
1fd4f2a5 | 498 | { |
d76685c4 | 499 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 500 | u32 result; |
bda9020e MT |
501 | if (!ioapic_in_range(ioapic, addr)) |
502 | return -EOPNOTSUPP; | |
1fd4f2a5 | 503 | |
e25e3ed5 | 504 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
505 | ASSERT(!(addr & 0xf)); /* check alignment */ |
506 | ||
507 | addr &= 0xff; | |
46a47b1e | 508 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
509 | switch (addr) { |
510 | case IOAPIC_REG_SELECT: | |
511 | result = ioapic->ioregsel; | |
512 | break; | |
513 | ||
514 | case IOAPIC_REG_WINDOW: | |
515 | result = ioapic_read_indirect(ioapic, addr, len); | |
516 | break; | |
517 | ||
518 | default: | |
519 | result = 0; | |
520 | break; | |
521 | } | |
46a47b1e | 522 | spin_unlock(&ioapic->lock); |
eba0226b | 523 | |
1fd4f2a5 ED |
524 | switch (len) { |
525 | case 8: | |
526 | *(u64 *) val = result; | |
527 | break; | |
528 | case 1: | |
529 | case 2: | |
530 | case 4: | |
531 | memcpy(val, (char *)&result, len); | |
532 | break; | |
533 | default: | |
534 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
535 | } | |
bda9020e | 536 | return 0; |
1fd4f2a5 ED |
537 | } |
538 | ||
e32edf4f NN |
539 | static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
540 | gpa_t addr, int len, const void *val) | |
1fd4f2a5 | 541 | { |
d76685c4 | 542 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 543 | u32 data; |
bda9020e MT |
544 | if (!ioapic_in_range(ioapic, addr)) |
545 | return -EOPNOTSUPP; | |
1fd4f2a5 | 546 | |
e25e3ed5 LV |
547 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
548 | (void*)addr, len, val); | |
1fd4f2a5 | 549 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 550 | |
d77fe635 JS |
551 | switch (len) { |
552 | case 8: | |
553 | case 4: | |
1fd4f2a5 | 554 | data = *(u32 *) val; |
d77fe635 JS |
555 | break; |
556 | case 2: | |
557 | data = *(u16 *) val; | |
558 | break; | |
559 | case 1: | |
560 | data = *(u8 *) val; | |
561 | break; | |
562 | default: | |
1fd4f2a5 | 563 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 564 | return 0; |
1fd4f2a5 ED |
565 | } |
566 | ||
567 | addr &= 0xff; | |
46a47b1e | 568 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
569 | switch (addr) { |
570 | case IOAPIC_REG_SELECT: | |
d77fe635 | 571 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
572 | break; |
573 | ||
574 | case IOAPIC_REG_WINDOW: | |
575 | ioapic_write_indirect(ioapic, data); | |
576 | break; | |
577 | ||
578 | default: | |
579 | break; | |
580 | } | |
46a47b1e | 581 | spin_unlock(&ioapic->lock); |
bda9020e | 582 | return 0; |
1fd4f2a5 ED |
583 | } |
584 | ||
7940876e | 585 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
586 | { |
587 | int i; | |
588 | ||
184564ef | 589 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
8c392696 ED |
590 | for (i = 0; i < IOAPIC_NUM_PINS; i++) |
591 | ioapic->redirtbl[i].fields.mask = 1; | |
592 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
593 | ioapic->ioregsel = 0; | |
594 | ioapic->irr = 0; | |
5bda6eed | 595 | ioapic->irr_delivered = 0; |
8c392696 | 596 | ioapic->id = 0; |
8678654e | 597 | memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi)); |
10606919 | 598 | rtc_irq_eoi_tracking_reset(ioapic); |
8c392696 ED |
599 | } |
600 | ||
d76685c4 GH |
601 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
602 | .read = ioapic_mmio_read, | |
603 | .write = ioapic_mmio_write, | |
d76685c4 GH |
604 | }; |
605 | ||
1fd4f2a5 ED |
606 | int kvm_ioapic_init(struct kvm *kvm) |
607 | { | |
608 | struct kvm_ioapic *ioapic; | |
090b7aff | 609 | int ret; |
1fd4f2a5 ED |
610 | |
611 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
612 | if (!ioapic) | |
613 | return -ENOMEM; | |
46a47b1e | 614 | spin_lock_init(&ioapic->lock); |
184564ef | 615 | INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work); |
d7deeeb0 | 616 | kvm->arch.vioapic = ioapic; |
8c392696 | 617 | kvm_ioapic_reset(ioapic); |
d76685c4 | 618 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 619 | ioapic->kvm = kvm; |
79fac95e | 620 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
621 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
622 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 623 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
624 | if (ret < 0) { |
625 | kvm->arch.vioapic = NULL; | |
090b7aff | 626 | kfree(ioapic); |
3bb345f3 | 627 | return ret; |
1ae77bad | 628 | } |
090b7aff | 629 | |
3bb345f3 | 630 | kvm_vcpu_request_scan_ioapic(kvm); |
090b7aff | 631 | return ret; |
1fd4f2a5 | 632 | } |
75858a84 | 633 | |
72bb2fcd WY |
634 | void kvm_ioapic_destroy(struct kvm *kvm) |
635 | { | |
636 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
637 | ||
950712eb PX |
638 | if (!ioapic) |
639 | return; | |
640 | ||
184564ef | 641 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
d90e3a35 JL |
642 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); |
643 | kvm->arch.vioapic = NULL; | |
644 | kfree(ioapic); | |
72bb2fcd WY |
645 | } |
646 | ||
eba0226b GN |
647 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
648 | { | |
649 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
650 | if (!ioapic) | |
651 | return -EINVAL; | |
652 | ||
46a47b1e | 653 | spin_lock(&ioapic->lock); |
eba0226b | 654 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
5bda6eed | 655 | state->irr &= ~ioapic->irr_delivered; |
46a47b1e | 656 | spin_unlock(&ioapic->lock); |
eba0226b GN |
657 | return 0; |
658 | } | |
659 | ||
660 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
661 | { | |
662 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
663 | if (!ioapic) | |
664 | return -EINVAL; | |
665 | ||
46a47b1e | 666 | spin_lock(&ioapic->lock); |
eba0226b | 667 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
673f7b42 | 668 | ioapic->irr = 0; |
5bda6eed | 669 | ioapic->irr_delivered = 0; |
3d81bc7e | 670 | kvm_vcpu_request_scan_ioapic(kvm); |
673f7b42 | 671 | kvm_ioapic_inject_all(ioapic, state->irr); |
46a47b1e | 672 | spin_unlock(&ioapic->lock); |
eba0226b GN |
673 | return 0; |
674 | } |