[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / irq_comm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * irq_comm.c: Common API for in kernel interrupt controller
 * Copyright (c) 2007, Intel Corporation.
 *
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 */

#include <linux/kvm_host.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/rculist.h>

#include <trace/events/kvm.h>

#include <asm/msidef.h>

#include "irq.h"

#include "ioapic.h"

#include "lapic.h"

#include "hyperv.h"
#include "x86.h"

static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
			   struct kvm *kvm, int irq_source_id, int level,
			   bool line_status)
{
	struct kvm_pic *pic = kvm->arch.vpic;
	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
}

static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level,
			      bool line_status)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
				line_status);
}

int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, struct dest_map *dest_map)
{
	int i, r = -1;
	struct kvm_vcpu *vcpu, *lowest = NULL;
	unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)];
	unsigned int dest_vcpus = 0;

	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
		return r;

	if (irq->dest_mode == APIC_DEST_PHYSICAL &&
	    irq->dest_id == 0xff && kvm_lowest_prio_delivery(irq)) {
		printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
		irq->delivery_mode = APIC_DM_FIXED;
	}

	memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap));

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (!kvm_lowest_prio_delivery(irq)) {
			if (r < 0)
				r = 0;
			r += kvm_apic_set_irq(vcpu, irq, dest_map);
		} else if (kvm_apic_sw_enabled(vcpu->arch.apic)) {
			if (!kvm_vector_hashing_enabled()) {
				if (!lowest)
					lowest = vcpu;
				else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
					lowest = vcpu;
			} else {
				__set_bit(i, dest_vcpu_bitmap);
				dest_vcpus++;
			}
		}
	}

	if (dest_vcpus != 0) {
		int idx = kvm_vector_to_index(irq->vector, dest_vcpus,
					dest_vcpu_bitmap, KVM_MAX_VCPUS);

		lowest = kvm_get_vcpu(kvm, idx);
	}

	if (lowest)
		r = kvm_apic_set_irq(lowest, irq, dest_map);

	return r;
}

void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
		     struct kvm_lapic_irq *irq)
{
	trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ?
	                                     (u64)e->msi.address_hi << 32 : 0),
	                      e->msi.data);

	irq->dest_id = (e->msi.address_lo &
			MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	if (kvm->arch.x2apic_format)
		irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi);
	irq->vector = (e->msi.data &
			MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	irq->dest_mode = kvm_lapic_irq_dest_mode(
	    !!((1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo));
	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	irq->delivery_mode = e->msi.data & 0x700;
	irq->msi_redir_hint = ((e->msi.address_lo
		& MSI_ADDR_REDIRECTION_LOWPRI) > 0);
	irq->level = 1;
	irq->shorthand = APIC_DEST_NOSHORT;
}
EXPORT_SYMBOL_GPL(kvm_set_msi_irq);

static inline bool kvm_msi_route_invalid(struct kvm *kvm,
		struct kvm_kernel_irq_routing_entry *e)
{
	return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff);
}

int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
		struct kvm *kvm, int irq_source_id, int level, bool line_status)
{
	struct kvm_lapic_irq irq;

	if (kvm_msi_route_invalid(kvm, e))
		return -EINVAL;

	if (!level)
		return -1;

	kvm_set_msi_irq(kvm, e, &irq);

	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
}


static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
		    struct kvm *kvm, int irq_source_id, int level,
		    bool line_status)
{
	if (!level)
		return -1;

	return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
}

int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level,
			      bool line_status)
{
	struct kvm_lapic_irq irq;
	int r;

	switch (e->type) {
	case KVM_IRQ_ROUTING_HV_SINT:
		return kvm_hv_set_sint(e, kvm, irq_source_id, level,
				       line_status);

	case KVM_IRQ_ROUTING_MSI:
		if (kvm_msi_route_invalid(kvm, e))
			return -EINVAL;

		kvm_set_msi_irq(kvm, e, &irq);

		if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
			return r;
		break;

	default:
		break;
	}

	return -EWOULDBLOCK;
}

int kvm_request_irq_source_id(struct kvm *kvm)
{
	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
	int irq_source_id;

	mutex_lock(&kvm->irq_lock);
	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);

	if (irq_source_id >= BITS_PER_LONG) {
		printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
		irq_source_id = -EFAULT;
		goto unlock;
	}

	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
	set_bit(irq_source_id, bitmap);
unlock:
	mutex_unlock(&kvm->irq_lock);

	return irq_source_id;
}

void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
{
	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);

	mutex_lock(&kvm->irq_lock);
	if (irq_source_id < 0 ||
	    irq_source_id >= BITS_PER_LONG) {
		printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
		goto unlock;
	}
	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
	if (!irqchip_kernel(kvm))
		goto unlock;

	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
	kvm_pic_clear_all(kvm->arch.vpic, irq_source_id);
unlock:
	mutex_unlock(&kvm->irq_lock);
}

void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
				    struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	kimn->irq = irq;
	hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
				      struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	hlist_del_rcu(&kimn->link);
	mutex_unlock(&kvm->irq_lock);
	synchronize_srcu(&kvm->irq_srcu);
}

void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
			     bool mask)
{
	struct kvm_irq_mask_notifier *kimn;
	int idx, gsi;

	idx = srcu_read_lock(&kvm->irq_srcu);
	gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
	if (gsi != -1)
		hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
			if (kimn->irq == gsi)
				kimn->func(kimn, mask);
	srcu_read_unlock(&kvm->irq_srcu, idx);
}

bool kvm_arch_can_set_irq_routing(struct kvm *kvm)
{
	return irqchip_in_kernel(kvm);
}

int kvm_set_routing_entry(struct kvm *kvm,
			  struct kvm_kernel_irq_routing_entry *e,
			  const struct kvm_irq_routing_entry *ue)
{
	/* We can't check irqchip_in_kernel() here as some callers are
	 * currently inititalizing the irqchip. Other callers should therefore
	 * check kvm_arch_can_set_irq_routing() before calling this function.
	 */
	switch (ue->type) {
	case KVM_IRQ_ROUTING_IRQCHIP:
		if (irqchip_split(kvm))
			return -EINVAL;
		e->irqchip.pin = ue->u.irqchip.pin;
		switch (ue->u.irqchip.irqchip) {
		case KVM_IRQCHIP_PIC_SLAVE:
			e->irqchip.pin += PIC_NUM_PINS / 2;
			fallthrough;
		case KVM_IRQCHIP_PIC_MASTER:
			if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2)
				return -EINVAL;
			e->set = kvm_set_pic_irq;
			break;
		case KVM_IRQCHIP_IOAPIC:
			if (ue->u.irqchip.pin >= KVM_IOAPIC_NUM_PINS)
				return -EINVAL;
			e->set = kvm_set_ioapic_irq;
			break;
		default:
			return -EINVAL;
		}
		e->irqchip.irqchip = ue->u.irqchip.irqchip;
		break;
	case KVM_IRQ_ROUTING_MSI:
		e->set = kvm_set_msi;
		e->msi.address_lo = ue->u.msi.address_lo;
		e->msi.address_hi = ue->u.msi.address_hi;
		e->msi.data = ue->u.msi.data;

		if (kvm_msi_route_invalid(kvm, e))
			return -EINVAL;
		break;
	case KVM_IRQ_ROUTING_HV_SINT:
		e->set = kvm_hv_set_sint;
		e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
		e->hv_sint.sint = ue->u.hv_sint.sint;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
			     struct kvm_vcpu **dest_vcpu)
{
	int i, r = 0;
	struct kvm_vcpu *vcpu;

	if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
		return true;

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (++r == 2)
			return false;

		*dest_vcpu = vcpu;
	}

	return r == 1;
}
EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);

#define IOAPIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)

#define PIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
#define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)

static const struct kvm_irq_routing_entry default_routing[] = {
	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
};

int kvm_setup_default_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, default_routing,
				   ARRAY_SIZE(default_routing), 0);
}

static const struct kvm_irq_routing_entry empty_routing[] = {};

int kvm_setup_empty_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
}

void kvm_arch_post_irq_routing_update(struct kvm *kvm)
{
	if (!irqchip_split(kvm))
		return;
	kvm_make_scan_ioapic_request(kvm);
}

void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
			    ulong *ioapic_handled_vectors)
{
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kernel_irq_routing_entry *entry;
	struct kvm_irq_routing_table *table;
	u32 i, nr_ioapic_pins;
	int idx;

	idx = srcu_read_lock(&kvm->irq_srcu);
	table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
	nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
			       kvm->arch.nr_reserved_ioapic_pins);
	for (i = 0; i < nr_ioapic_pins; ++i) {
		hlist_for_each_entry(entry, &table->map[i], link) {
			struct kvm_lapic_irq irq;

			if (entry->type != KVM_IRQ_ROUTING_MSI)
				continue;

			kvm_set_msi_irq(vcpu->kvm, entry, &irq);

			if (irq.trig_mode &&
			    kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
						irq.dest_id, irq.dest_mode))
				__set_bit(irq.vector, ioapic_handled_vectors);
		}
	}
	srcu_read_unlock(&kvm->irq_srcu, idx);
}

void kvm_arch_irq_routing_update(struct kvm *kvm)
{
	kvm_hv_irq_routing_update(kvm);
}
Commit	Line	Data
3b20eb23	1	// SPDX-License-Identifier: GPL-2.0-only
3de42dc0 XZ	2	/*
	3	* irq_comm.c: Common API for in kernel interrupt controller
	4	* Copyright (c) 2007, Intel Corporation.
	5	*
3de42dc0 XZ	6	* Authors:
	7	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	8	*
9611c187	9	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
3de42dc0 XZ	10	*/
	11
	12	#include <linux/kvm_host.h>
5a0e3ad6	13	#include <linux/slab.h>
c7c9c56c	14	#include <linux/export.h>
b2d09103 IM	15	#include <linux/rculist.h>
b2d09103 IM	16
229456fc	17	#include <trace/events/kvm.h>
79950e10	18
79950e10	19	#include <asm/msidef.h>
79950e10	20
3de42dc0 XZ	21	#include "irq.h"
	22
	23	#include "ioapic.h"
	24
d1ebdbf9 JS	25	#include "lapic.h"
d1ebdbf9 JS	26
5c919412	27	#include "hyperv.h"
52004014	28	#include "x86.h"
5c919412	29
4925663a	30	static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	31	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	32	bool line_status)
399ec807	33	{
90bca052	34	struct kvm_pic *pic = kvm->arch.vpic;
1a577b72	35	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
399ec807 AK	36	}
399ec807 AK	37
4925663a	38	static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	39	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	40	bool line_status)
399ec807	41	{
1a6e4a8c	42	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
aa2fbe6d YZ	43	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
aa2fbe6d YZ	44	line_status);
399ec807 AK	45	}
399ec807 AK	46
58c2dde1	47	int kvm_irq_delivery_to_apic(struct kvm kvm, struct kvm_lapic src,
9e4aabe2	48	struct kvm_lapic_irq irq, struct dest_map dest_map)
58c2dde1 GN	49	{
	50	int i, r = -1;
	51	struct kvm_vcpu vcpu, lowest = NULL;
52004014 FW	52	unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)];
52004014 FW	53	unsigned int dest_vcpus = 0;
58c2dde1	54
dfd146fc WL	55	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
	56	return r;
	57
c96001c5 PX	58	if (irq->dest_mode == APIC_DEST_PHYSICAL &&
c96001c5 PX	59	irq->dest_id == 0xff && kvm_lowest_prio_delivery(irq)) {
343f94fe	60	printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
1e08ec4a GN	61	irq->delivery_mode = APIC_DM_FIXED;
	62	}
	63
52004014 FW	64	memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap));
52004014 FW	65
988a2cae GN	66	kvm_for_each_vcpu(i, vcpu, kvm) {
988a2cae GN	67	if (!kvm_apic_present(vcpu))
343f94fe GN	68	continue;
343f94fe GN	69
58c2dde1 GN	70	if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
58c2dde1 GN	71	irq->dest_id, irq->dest_mode))
343f94fe GN	72	continue;
343f94fe GN	73
d1ebdbf9	74	if (!kvm_lowest_prio_delivery(irq)) {
58c2dde1 GN	75	if (r < 0)
58c2dde1 GN	76	r = 0;
b4f2225c	77	r += kvm_apic_set_irq(vcpu, irq, dest_map);
7d2296bf	78	} else if (kvm_apic_sw_enabled(vcpu->arch.apic)) {
52004014 FW	79	if (!kvm_vector_hashing_enabled()) {
	80	if (!lowest)
	81	lowest = vcpu;
	82	else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
	83	lowest = vcpu;
	84	} else {
	85	__set_bit(i, dest_vcpu_bitmap);
	86	dest_vcpus++;
	87	}
e1035715	88	}
343f94fe GN	89	}
343f94fe GN	90
52004014 FW	91	if (dest_vcpus != 0) {
	92	int idx = kvm_vector_to_index(irq->vector, dest_vcpus,
	93	dest_vcpu_bitmap, KVM_MAX_VCPUS);
	94
	95	lowest = kvm_get_vcpu(kvm, idx);
	96	}
	97
58c2dde1	98	if (lowest)
b4f2225c	99	r = kvm_apic_set_irq(lowest, irq, dest_map);
58c2dde1 GN	100
58c2dde1 GN	101	return r;
116191b6 SY	102	}
116191b6 SY	103
37131313	104	void kvm_set_msi_irq(struct kvm kvm, struct kvm_kernel_irq_routing_entry e,
d84f1e07	105	struct kvm_lapic_irq *irq)
01f21880	106	{
37131313 RK	107	trace_kvm_msi_set_irq(e->msi.address_lo \| (kvm->arch.x2apic_format ?
	108	(u64)e->msi.address_hi << 32 : 0),
	109	e->msi.data);
01f21880 MT	110
	111	irq->dest_id = (e->msi.address_lo &
	112	MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
37131313 RK	113	if (kvm->arch.x2apic_format)
37131313 RK	114	irq->dest_id \|= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi);
01f21880 MT	115	irq->vector = (e->msi.data &
01f21880 MT	116	MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
c96001c5 PX	117	irq->dest_mode = kvm_lapic_irq_dest_mode(
c96001c5 PX	118	!!((1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo));
01f21880 MT	119	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
01f21880 MT	120	irq->delivery_mode = e->msi.data & 0x700;
93bbf0b8 JS	121	irq->msi_redir_hint = ((e->msi.address_lo
93bbf0b8 JS	122	& MSI_ADDR_REDIRECTION_LOWPRI) > 0);
01f21880	123	irq->level = 1;
150a84fe	124	irq->shorthand = APIC_DEST_NOSHORT;
01f21880	125	}
d84f1e07	126	EXPORT_SYMBOL_GPL(kvm_set_msi_irq);
01f21880	127
37131313 RK	128	static inline bool kvm_msi_route_invalid(struct kvm *kvm,
	129	struct kvm_kernel_irq_routing_entry *e)
	130	{
	131	return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff);
	132	}
	133
bd2b53b2	134	int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d	135	struct kvm *kvm, int irq_source_id, int level, bool line_status)
79950e10	136	{
58c2dde1	137	struct kvm_lapic_irq irq;
79950e10	138
37131313 RK	139	if (kvm_msi_route_invalid(kvm, e))
	140	return -EINVAL;
	141
1a6e4a8c GN	142	if (!level)
	143	return -1;
	144
37131313	145	kvm_set_msi_irq(kvm, e, &irq);
116191b6	146
b4f2225c	147	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
79950e10 SY	148	}
79950e10 SY	149
01f21880	150
a2b07739 PB	151	static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
	152	struct kvm *kvm, int irq_source_id, int level,
	153	bool line_status)
	154	{
	155	if (!level)
	156	return -1;
	157
	158	return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
	159	}
	160
b97e6de9 PB	161	int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
	162	struct kvm *kvm, int irq_source_id, int level,
	163	bool line_status)
01f21880 MT	164	{
	165	struct kvm_lapic_irq irq;
	166	int r;
	167
a2b07739 PB	168	switch (e->type) {
	169	case KVM_IRQ_ROUTING_HV_SINT:
	170	return kvm_hv_set_sint(e, kvm, irq_source_id, level,
	171	line_status);
b97e6de9	172
a2b07739 PB	173	case KVM_IRQ_ROUTING_MSI:
	174	if (kvm_msi_route_invalid(kvm, e))
	175	return -EINVAL;
37131313	176
a2b07739	177	kvm_set_msi_irq(kvm, e, &irq);
01f21880	178
a2b07739 PB	179	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
	180	return r;
	181	break;
	182
	183	default:
	184	break;
	185	}
	186
	187	return -EWOULDBLOCK;
01f21880 MT	188	}
01f21880 MT	189
5550af4d SY	190	int kvm_request_irq_source_id(struct kvm *kvm)
	191	{
	192	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
fa40a821 MT	193	int irq_source_id;
	194
	195	mutex_lock(&kvm->irq_lock);
cd5a2685	196	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
61552367	197
cd5a2685	198	if (irq_source_id >= BITS_PER_LONG) {
5550af4d	199	printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
0c6ddceb JS	200	irq_source_id = -EFAULT;
0c6ddceb JS	201	goto unlock;
61552367 MM	202	}
	203
	204	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a	205	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
61552367	206	set_bit(irq_source_id, bitmap);
0c6ddceb	207	unlock:
fa40a821	208	mutex_unlock(&kvm->irq_lock);
61552367	209
5550af4d SY	210	return irq_source_id;
	211	}
	212
	213	void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
	214	{
61552367	215	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a	216	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
61552367	217
fa40a821	218	mutex_lock(&kvm->irq_lock);
61552367	219	if (irq_source_id < 0 \|\|
cd5a2685	220	irq_source_id >= BITS_PER_LONG) {
5550af4d	221	printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
0c6ddceb	222	goto unlock;
5550af4d	223	}
e50212bb	224	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
900ab14c	225	if (!irqchip_kernel(kvm))
e50212bb MT	226	goto unlock;
e50212bb MT	227
1a577b72	228	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
90bca052	229	kvm_pic_clear_all(kvm->arch.vpic, irq_source_id);
0c6ddceb	230	unlock:
fa40a821	231	mutex_unlock(&kvm->irq_lock);
5550af4d	232	}
75858a84 AK	233
	234	void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
	235	struct kvm_irq_mask_notifier *kimn)
	236	{
fa40a821	237	mutex_lock(&kvm->irq_lock);
75858a84	238	kimn->irq = irq;
6ef768fa	239	hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
fa40a821	240	mutex_unlock(&kvm->irq_lock);
75858a84 AK	241	}
	242
	243	void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
	244	struct kvm_irq_mask_notifier *kimn)
	245	{
fa40a821	246	mutex_lock(&kvm->irq_lock);
280aa177	247	hlist_del_rcu(&kimn->link);
fa40a821	248	mutex_unlock(&kvm->irq_lock);
719d93cd	249	synchronize_srcu(&kvm->irq_srcu);
75858a84 AK	250	}
75858a84 AK	251
4a994358 GN	252	void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
4a994358 GN	253	bool mask)
75858a84 AK	254	{
75858a84 AK	255	struct kvm_irq_mask_notifier *kimn;
719d93cd	256	int idx, gsi;
75858a84	257
719d93cd	258	idx = srcu_read_lock(&kvm->irq_srcu);
9957c86d	259	gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
4a994358	260	if (gsi != -1)
6ef768fa	261	hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
4a994358 GN	262	if (kimn->irq == gsi)
4a994358 GN	263	kimn->func(kimn, mask);
719d93cd	264	srcu_read_unlock(&kvm->irq_srcu, idx);
75858a84 AK	265	}
75858a84 AK	266
5c0aea0e DH	267	bool kvm_arch_can_set_irq_routing(struct kvm *kvm)
	268	{
	269	return irqchip_in_kernel(kvm);
	270	}
	271
c63cf538 RK	272	int kvm_set_routing_entry(struct kvm *kvm,
c63cf538 RK	273	struct kvm_kernel_irq_routing_entry *e,
e8cde093	274	const struct kvm_irq_routing_entry *ue)
399ec807	275	{
5c0aea0e DH	276	/* We can't check irqchip_in_kernel() here as some callers are
	277	* currently inititalizing the irqchip. Other callers should therefore
	278	* check kvm_arch_can_set_irq_routing() before calling this function.
	279	*/
399ec807 AK	280	switch (ue->type) {
399ec807 AK	281	case KVM_IRQ_ROUTING_IRQCHIP:
8bf463f3	282	if (irqchip_split(kvm))
43ae312c	283	return -EINVAL;
445ee82d	284	e->irqchip.pin = ue->u.irqchip.pin;
399ec807	285	switch (ue->u.irqchip.irqchip) {
399ec807	286	case KVM_IRQCHIP_PIC_SLAVE:
445ee82d	287	e->irqchip.pin += PIC_NUM_PINS / 2;
df561f66	288	fallthrough;
e5dc4877	289	case KVM_IRQCHIP_PIC_MASTER:
445ee82d	290	if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2)
43ae312c	291	return -EINVAL;
4925663a	292	e->set = kvm_set_pic_irq;
399ec807 AK	293	break;
399ec807 AK	294	case KVM_IRQCHIP_IOAPIC:
445ee82d	295	if (ue->u.irqchip.pin >= KVM_IOAPIC_NUM_PINS)
43ae312c	296	return -EINVAL;
efbc100c	297	e->set = kvm_set_ioapic_irq;
399ec807 AK	298	break;
399ec807 AK	299	default:
43ae312c	300	return -EINVAL;
399ec807 AK	301	}
399ec807 AK	302	e->irqchip.irqchip = ue->u.irqchip.irqchip;
399ec807	303	break;
79950e10 SY	304	case KVM_IRQ_ROUTING_MSI:
	305	e->set = kvm_set_msi;
	306	e->msi.address_lo = ue->u.msi.address_lo;
	307	e->msi.address_hi = ue->u.msi.address_hi;
	308	e->msi.data = ue->u.msi.data;
37131313 RK	309
37131313 RK	310	if (kvm_msi_route_invalid(kvm, e))
43ae312c	311	return -EINVAL;
79950e10	312	break;
5c919412 AS	313	case KVM_IRQ_ROUTING_HV_SINT:
	314	e->set = kvm_hv_set_sint;
	315	e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
	316	e->hv_sint.sint = ue->u.hv_sint.sint;
	317	break;
399ec807	318	default:
43ae312c	319	return -EINVAL;
399ec807	320	}
46e624b9	321
43ae312c	322	return 0;
399ec807 AK	323	}
399ec807 AK	324
8feb4a04 FW	325	bool kvm_intr_is_single_vcpu(struct kvm kvm, struct kvm_lapic_irq irq,
	326	struct kvm_vcpu **dest_vcpu)
	327	{
	328	int i, r = 0;
	329	struct kvm_vcpu *vcpu;
	330
	331	if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
	332	return true;
	333
	334	kvm_for_each_vcpu(i, vcpu, kvm) {
	335	if (!kvm_apic_present(vcpu))
	336	continue;
	337
	338	if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
	339	irq->dest_id, irq->dest_mode))
	340	continue;
	341
	342	if (++r == 2)
	343	return false;
	344
	345	*dest_vcpu = vcpu;
	346	}
	347
	348	return r == 1;
	349	}
	350	EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);
	351
399ec807 AK	352	#define IOAPIC_ROUTING_ENTRY(irq) \
399ec807 AK	353	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
25f97ff4	354	.u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
399ec807 AK	355	#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
399ec807 AK	356
3bf58e9a	357	#define PIC_ROUTING_ENTRY(irq) \
399ec807	358	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
25f97ff4	359	.u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
3bf58e9a	360	#define ROUTING_ENTRY2(irq) \
399ec807	361	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
399ec807 AK	362
	363	static const struct kvm_irq_routing_entry default_routing[] = {
	364	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	365	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	366	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	367	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	368	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	369	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	370	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	371	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	372	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	373	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	374	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	375	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
399ec807 AK	376	};
	377
	378	int kvm_setup_default_irq_routing(struct kvm *kvm)
	379	{
	380	return kvm_set_irq_routing(kvm, default_routing,
	381	ARRAY_SIZE(default_routing), 0);
	382	}
49df6397 SR	383
	384	static const struct kvm_irq_routing_entry empty_routing[] = {};
	385
	386	int kvm_setup_empty_irq_routing(struct kvm *kvm)
	387	{
	388	return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
	389	}
b053b2ae	390
abdb080f	391	void kvm_arch_post_irq_routing_update(struct kvm *kvm)
b053b2ae	392	{
826da321	393	if (!irqchip_split(kvm))
b053b2ae SR	394	return;
	395	kvm_make_scan_ioapic_request(kvm);
	396	}
	397
6308630b AS	398	void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
6308630b AS	399	ulong *ioapic_handled_vectors)
b053b2ae SR	400	{
	401	struct kvm *kvm = vcpu->kvm;
	402	struct kvm_kernel_irq_routing_entry *entry;
	403	struct kvm_irq_routing_table *table;
	404	u32 i, nr_ioapic_pins;
	405	int idx;
	406
b053b2ae SR	407	idx = srcu_read_lock(&kvm->irq_srcu);
	408	table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
	409	nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
	410	kvm->arch.nr_reserved_ioapic_pins);
	411	for (i = 0; i < nr_ioapic_pins; ++i) {
	412	hlist_for_each_entry(entry, &table->map[i], link) {
3159d36a	413	struct kvm_lapic_irq irq;
b053b2ae SR	414
	415	if (entry->type != KVM_IRQ_ROUTING_MSI)
	416	continue;
3159d36a	417
37131313	418	kvm_set_msi_irq(vcpu->kvm, entry, &irq);
3159d36a	419
7455a832	420	if (irq.trig_mode &&
5c69d5c1	421	kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
3159d36a RK	422	irq.dest_id, irq.dest_mode))
3159d36a RK	423	__set_bit(irq.vector, ioapic_handled_vectors);
b053b2ae SR	424	}
	425	}
	426	srcu_read_unlock(&kvm->irq_srcu, idx);
	427	}
5c919412	428
5c919412 AS	429	void kvm_arch_irq_routing_update(struct kvm *kvm)
	430	{
	431	kvm_hv_irq_routing_update(kvm);
	432	}