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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
36#include <asm/atomic.h>
5fdbf976 37#include "kvm_cache_regs.h"
97222cc8 38#include "irq.h"
229456fc 39#include "trace.h"
fc61b800 40#include "x86.h"
97222cc8 41
b682b814
MT		 42#ifndef CONFIG_X86_64
43#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
44#else
45#define mod_64(x, y) ((x) % (y))
46#endif
47
97222cc8
ED		 48#define PRId64 "d"
49#define PRIx64 "llx"
50#define PRIu64 "u"
51#define PRIo64 "o"
52
53#define APIC_BUS_CYCLE_NS 1
54
55/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56#define apic_debug(fmt, arg...)
57
58#define APIC_LVT_NUM 6
59/* 14 is the version for Xeon and Pentium 8.4.8*/
60#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61#define LAPIC_MMIO_LENGTH (1 << 12)
62/* followed define is not in apicdef.h */
63#define APIC_SHORT_MASK 0xc0000
64#define APIC_DEST_NOSHORT 0x0
65#define APIC_DEST_MASK 0x800
66#define MAX_APIC_VECTOR 256
67
68#define VEC_POS(v) ((v) & (32 - 1))
69#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 70
97222cc8
ED		 71static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
72{
73 return *((u32 *) (apic->regs + reg_off));
74}
75
76static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
77{
78 *((u32 *) (apic->regs + reg_off)) = val;
79}
80
81static inline int apic_test_and_set_vector(int vec, void *bitmap)
82{
83 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
84}
85
86static inline int apic_test_and_clear_vector(int vec, void *bitmap)
87{
88 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
91static inline void apic_set_vector(int vec, void *bitmap)
92{
93 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94}
95
96static inline void apic_clear_vector(int vec, void *bitmap)
97{
98 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline int apic_hw_enabled(struct kvm_lapic *apic)
102{
ad312c7c 103 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 104}
105
106static inline int apic_sw_enabled(struct kvm_lapic *apic)
107{
108 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
109}
110
111static inline int apic_enabled(struct kvm_lapic *apic)
112{
113 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
114}
115
116#define LVT_MASK \
117 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
118
119#define LINT_MASK \
120 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
121 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
122
123static inline int kvm_apic_id(struct kvm_lapic *apic)
124{
125 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
126}
127
128static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
129{
130 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
131}
132
133static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
134{
135 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
136}
137
138static inline int apic_lvtt_period(struct kvm_lapic *apic)
139{
140 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
141}
142
cc6e462c
JK		 143static inline int apic_lvt_nmi_mode(u32 lvt_val)
144{
145 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
146}
147
fc61b800
GN		 148void kvm_apic_set_version(struct kvm_vcpu *vcpu)
149{
150 struct kvm_lapic *apic = vcpu->arch.apic;
151 struct kvm_cpuid_entry2 *feat;
152 u32 v = APIC_VERSION;
153
154 if (!irqchip_in_kernel(vcpu->kvm))
155 return;
156
157 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
158 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
159 v |= APIC_LVR_DIRECTED_EOI;
160 apic_set_reg(apic, APIC_LVR, v);
161}
162
0105d1a5
GN		 163static inline int apic_x2apic_mode(struct kvm_lapic *apic)
164{
165 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
166}
167
97222cc8
ED		 168static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
169 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
170 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
171 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
172 LINT_MASK, LINT_MASK, /* LVT0-1 */
173 LVT_MASK /* LVTERR */
174};
175
176static int find_highest_vector(void *bitmap)
177{
178 u32 *word = bitmap;
179 int word_offset = MAX_APIC_VECTOR >> 5;
180
181 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
182 continue;
183
184 if (likely(!word_offset && !word[0]))
185 return -1;
186 else
187 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
188}
189
190static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
191{
33e4c686 192 apic->irr_pending = true;
97222cc8
ED		 193 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
194}
195
33e4c686 196static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 197{
33e4c686 198 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 199}
200
201static inline int apic_find_highest_irr(struct kvm_lapic *apic)
202{
203 int result;
204
33e4c686
GN		 205 if (!apic->irr_pending)
206 return -1;
207
208 result = apic_search_irr(apic);
97222cc8
ED		 209 ASSERT(result == -1 || result >= 16);
210
211 return result;
212}
213
33e4c686
GN		 214static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
215{
216 apic->irr_pending = false;
217 apic_clear_vector(vec, apic->regs + APIC_IRR);
218 if (apic_search_irr(apic) != -1)
219 apic->irr_pending = true;
220}
221
6e5d865c
YS		 222int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
223{
ad312c7c 224 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 225 int highest_irr;
226
33e4c686
GN		 227 /* This may race with setting of irr in __apic_accept_irq() and
228 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
229 * will cause vmexit immediately and the value will be recalculated
230 * on the next vmentry.
231 */
6e5d865c
YS		 232 if (!apic)
233 return 0;
234 highest_irr = apic_find_highest_irr(apic);
235
236 return highest_irr;
237}
6e5d865c 238
6da7e3f6
GN		 239static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
240 int vector, int level, int trig_mode);
241
58c2dde1 242int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 243{
ad312c7c 244 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 245
58c2dde1
GN		 246 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
247 irq->level, irq->trig_mode);
97222cc8
ED		 248}
249
250static inline int apic_find_highest_isr(struct kvm_lapic *apic)
251{
252 int result;
253
254 result = find_highest_vector(apic->regs + APIC_ISR);
255 ASSERT(result == -1 || result >= 16);
256
257 return result;
258}
259
260static void apic_update_ppr(struct kvm_lapic *apic)
261{
3842d135 262 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 263 int isr;
264
3842d135 265 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
97222cc8
ED		 266 tpr = apic_get_reg(apic, APIC_TASKPRI);
267 isr = apic_find_highest_isr(apic);
268 isrv = (isr != -1) ? isr : 0;
269
270 if ((tpr & 0xf0) >= (isrv & 0xf0))
271 ppr = tpr & 0xff;
272 else
273 ppr = isrv & 0xf0;
274
275 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
276 apic, ppr, isr, isrv);
277
3842d135
AK		 278 if (old_ppr != ppr) {
279 apic_set_reg(apic, APIC_PROCPRI, ppr);
280 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
281 }
97222cc8
ED		 282}
283
284static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
285{
286 apic_set_reg(apic, APIC_TASKPRI, tpr);
287 apic_update_ppr(apic);
288}
289
290int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
291{
343f94fe 292 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 293}
294
295int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
296{
297 int result = 0;
0105d1a5
GN		 298 u32 logical_id;
299
300 if (apic_x2apic_mode(apic)) {
301 logical_id = apic_get_reg(apic, APIC_LDR);
302 return logical_id & mda;
303 }
97222cc8
ED		 304
305 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
306
307 switch (apic_get_reg(apic, APIC_DFR)) {
308 case APIC_DFR_FLAT:
309 if (logical_id & mda)
310 result = 1;
311 break;
312 case APIC_DFR_CLUSTER:
313 if (((logical_id >> 4) == (mda >> 0x4))
314 && (logical_id & mda & 0xf))
315 result = 1;
316 break;
317 default:
318 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
319 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
320 break;
321 }
322
323 return result;
324}
325
343f94fe 326int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 327 int short_hand, int dest, int dest_mode)
328{
329 int result = 0;
ad312c7c 330 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 331
332 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 333 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 334 target, source, dest, dest_mode, short_hand);
335
bd371396 336 ASSERT(target);
97222cc8
ED		 337 switch (short_hand) {
338 case APIC_DEST_NOSHORT:
343f94fe 339 if (dest_mode == 0)
97222cc8 340 /* Physical mode. */
343f94fe
GN		 341 result = kvm_apic_match_physical_addr(target, dest);
342 else
97222cc8
ED		 343 /* Logical mode. */
344 result = kvm_apic_match_logical_addr(target, dest);
345 break;
346 case APIC_DEST_SELF:
343f94fe 347 result = (target == source);
97222cc8
ED		 348 break;
349 case APIC_DEST_ALLINC:
350 result = 1;
351 break;
352 case APIC_DEST_ALLBUT:
343f94fe 353 result = (target != source);
97222cc8
ED		 354 break;
355 default:
356 printk(KERN_WARNING "Bad dest shorthand value %x\n",
357 short_hand);
358 break;
359 }
360
361 return result;
362}
363
364/*
365 * Add a pending IRQ into lapic.
366 * Return 1 if successfully added and 0 if discarded.
367 */
368static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
369 int vector, int level, int trig_mode)
370{
6da7e3f6 371 int result = 0;
c5ec1534 372 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 373
374 switch (delivery_mode) {
97222cc8 375 case APIC_DM_LOWEST:
e1035715
GN		 376 vcpu->arch.apic_arb_prio++;
377 case APIC_DM_FIXED:
97222cc8
ED		 378 /* FIXME add logic for vcpu on reset */
379 if (unlikely(!apic_enabled(apic)))
380 break;
381
a5d36f82
AK		 382 if (trig_mode) {
383 apic_debug("level trig mode for vector %d", vector);
384 apic_set_vector(vector, apic->regs + APIC_TMR);
385 } else
386 apic_clear_vector(vector, apic->regs + APIC_TMR);
387
6da7e3f6 388 result = !apic_test_and_set_irr(vector, apic);
1000ff8d 389 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
4da74896 390 trig_mode, vector, !result);
6da7e3f6
GN		 391 if (!result) {
392 if (trig_mode)
393 apic_debug("level trig mode repeatedly for "
394 "vector %d", vector);
97222cc8
ED		 395 break;
396 }
397
3842d135 398 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 399 kvm_vcpu_kick(vcpu);
97222cc8
ED		 400 break;
401
402 case APIC_DM_REMRD:
403 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
404 break;
405
406 case APIC_DM_SMI:
407 printk(KERN_DEBUG "Ignoring guest SMI\n");
408 break;
3419ffc8 409
97222cc8 410 case APIC_DM_NMI:
6da7e3f6 411 result = 1;
3419ffc8 412 kvm_inject_nmi(vcpu);
26df99c6 413 kvm_vcpu_kick(vcpu);
97222cc8
ED		 414 break;
415
416 case APIC_DM_INIT:
c5ec1534 417 if (level) {
6da7e3f6 418 result = 1;
a4535290 419 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 420 printk(KERN_DEBUG
421 "INIT on a runnable vcpu %d\n",
422 vcpu->vcpu_id);
a4535290 423 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3842d135 424 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 425 kvm_vcpu_kick(vcpu);
426 } else {
1b10bf31
JK		 427 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
428 vcpu->vcpu_id);
c5ec1534 429 }
97222cc8
ED		 430 break;
431
432 case APIC_DM_STARTUP:
1b10bf31
JK		 433 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
434 vcpu->vcpu_id, vector);
a4535290 435 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 436 result = 1;
ad312c7c 437 vcpu->arch.sipi_vector = vector;
a4535290 438 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
3842d135 439 kvm_make_request(KVM_REQ_EVENT, vcpu);
d7690175 440 kvm_vcpu_kick(vcpu);
c5ec1534 441 }
97222cc8
ED		 442 break;
443
23930f95
JK		 444 case APIC_DM_EXTINT:
445 /*
446 * Should only be called by kvm_apic_local_deliver() with LVT0,
447 * before NMI watchdog was enabled. Already handled by
448 * kvm_apic_accept_pic_intr().
449 */
450 break;
451
97222cc8
ED		 452 default:
453 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
454 delivery_mode);
455 break;
456 }
457 return result;
458}
459
e1035715 460int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 461{
e1035715 462 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 463}
464
97222cc8
ED		 465static void apic_set_eoi(struct kvm_lapic *apic)
466{
467 int vector = apic_find_highest_isr(apic);
f5244726 468 int trigger_mode;
97222cc8
ED		 469 /*
470 * Not every write EOI will has corresponding ISR,
471 * one example is when Kernel check timer on setup_IO_APIC
472 */
473 if (vector == -1)
474 return;
475
476 apic_clear_vector(vector, apic->regs + APIC_ISR);
477 apic_update_ppr(apic);
478
479 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 480 trigger_mode = IOAPIC_LEVEL_TRIG;
481 else
482 trigger_mode = IOAPIC_EDGE_TRIG;
eba0226b 483 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
fc61b800 484 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
3842d135 485 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 486}
487
488static void apic_send_ipi(struct kvm_lapic *apic)
489{
490 u32 icr_low = apic_get_reg(apic, APIC_ICR);
491 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 492 struct kvm_lapic_irq irq;
97222cc8 493
58c2dde1
GN		 494 irq.vector = icr_low & APIC_VECTOR_MASK;
495 irq.delivery_mode = icr_low & APIC_MODE_MASK;
496 irq.dest_mode = icr_low & APIC_DEST_MASK;
497 irq.level = icr_low & APIC_INT_ASSERT;
498 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
499 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 500 if (apic_x2apic_mode(apic))
501 irq.dest_id = icr_high;
502 else
503 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 504
1000ff8d
GN		 505 trace_kvm_apic_ipi(icr_low, irq.dest_id);
506
97222cc8
ED		 507 apic_debug("icr_high 0x%x, icr_low 0x%x, "
508 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
509 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 510 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 511 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
512 irq.vector);
513
514 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
97222cc8
ED		 515}
516
517static u32 apic_get_tmcct(struct kvm_lapic *apic)
518{
b682b814
MT		 519 ktime_t remaining;
520 s64 ns;
9da8f4e8 521 u32 tmcct;
97222cc8
ED		 522
523 ASSERT(apic != NULL);
524
9da8f4e8 525 /* if initial count is 0, current count should also be 0 */
b682b814 526 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 527 return 0;
528
ace15464 529 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 530 if (ktime_to_ns(remaining) < 0)
531 remaining = ktime_set(0, 0);
532
d3c7b77d
MT		 533 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
534 tmcct = div64_u64(ns,
535 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 536
537 return tmcct;
538}
539
b209749f
AK		 540static void __report_tpr_access(struct kvm_lapic *apic, bool write)
541{
542 struct kvm_vcpu *vcpu = apic->vcpu;
543 struct kvm_run *run = vcpu->run;
544
a8eeb04a 545 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 546 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 547 run->tpr_access.is_write = write;
548}
549
550static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
551{
552 if (apic->vcpu->arch.tpr_access_reporting)
553 __report_tpr_access(apic, write);
554}
555
97222cc8
ED		 556static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
557{
558 u32 val = 0;
559
560 if (offset >= LAPIC_MMIO_LENGTH)
561 return 0;
562
563 switch (offset) {
0105d1a5
GN		 564 case APIC_ID:
565 if (apic_x2apic_mode(apic))
566 val = kvm_apic_id(apic);
567 else
568 val = kvm_apic_id(apic) << 24;
569 break;
97222cc8
ED		 570 case APIC_ARBPRI:
571 printk(KERN_WARNING "Access APIC ARBPRI register "
572 "which is for P6\n");
573 break;
574
575 case APIC_TMCCT: /* Timer CCR */
576 val = apic_get_tmcct(apic);
577 break;
578
b209749f
AK		 579 case APIC_TASKPRI:
580 report_tpr_access(apic, false);
581 /* fall thru */
97222cc8 582 default:
6e5d865c 583 apic_update_ppr(apic);
97222cc8
ED		 584 val = apic_get_reg(apic, offset);
585 break;
586 }
587
588 return val;
589}
590
d76685c4
GH		 591static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
592{
593 return container_of(dev, struct kvm_lapic, dev);
594}
595
0105d1a5
GN		 596static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
597 void *data)
97222cc8 598{
97222cc8
ED		 599 unsigned char alignment = offset & 0xf;
600 u32 result;
0105d1a5
GN		 601 /* this bitmask has a bit cleared for each reserver register */
602 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 603
604 if ((alignment + len) > 4) {
4088bb3c
GN		 605 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
606 offset, len);
0105d1a5 607 return 1;
97222cc8 608 }
0105d1a5
GN		 609
610 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 611 apic_debug("KVM_APIC_READ: read reserved register %x\n",
612 offset);
0105d1a5
GN		 613 return 1;
614 }
615
97222cc8
ED		 616 result = __apic_read(apic, offset & ~0xf);
617
229456fc
MT		 618 trace_kvm_apic_read(offset, result);
619
97222cc8
ED		 620 switch (len) {
621 case 1:
622 case 2:
623 case 4:
624 memcpy(data, (char *)&result + alignment, len);
625 break;
626 default:
627 printk(KERN_ERR "Local APIC read with len = %x, "
628 "should be 1,2, or 4 instead\n", len);
629 break;
630 }
bda9020e 631 return 0;
97222cc8
ED		 632}
633
0105d1a5
GN		 634static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
635{
636 return apic_hw_enabled(apic) &&
637 addr >= apic->base_address &&
638 addr < apic->base_address + LAPIC_MMIO_LENGTH;
639}
640
641static int apic_mmio_read(struct kvm_io_device *this,
642 gpa_t address, int len, void *data)
643{
644 struct kvm_lapic *apic = to_lapic(this);
645 u32 offset = address - apic->base_address;
646
647 if (!apic_mmio_in_range(apic, address))
648 return -EOPNOTSUPP;
649
650 apic_reg_read(apic, offset, len, data);
651
652 return 0;
653}
654
97222cc8
ED		 655static void update_divide_count(struct kvm_lapic *apic)
656{
657 u32 tmp1, tmp2, tdcr;
658
659 tdcr = apic_get_reg(apic, APIC_TDCR);
660 tmp1 = tdcr & 0xf;
661 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 662 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 663
664 apic_debug("timer divide count is 0x%x\n",
9b5843dd 665 apic->divide_count);
97222cc8
ED		 666}
667
668static void start_apic_timer(struct kvm_lapic *apic)
669{
d3c7b77d 670 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 671
b2d83cfa 672 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
d3c7b77d
MT		 673 APIC_BUS_CYCLE_NS * apic->divide_count;
674 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 675
d3c7b77d 676 if (!apic->lapic_timer.period)
0b975a3c 677 return;
1444885a
MT		 678 /*
679 * Do not allow the guest to program periodic timers with small
680 * interval, since the hrtimers are not throttled by the host
681 * scheduler.
682 */
683 if (apic_lvtt_period(apic)) {
684 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
685 apic->lapic_timer.period = NSEC_PER_MSEC/2;
686 }
0b975a3c 687
d3c7b77d
MT		 688 hrtimer_start(&apic->lapic_timer.timer,
689 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 690 HRTIMER_MODE_ABS);
691
692 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
693 PRIx64 ", "
694 "timer initial count 0x%x, period %lldns, "
b8688d51 695 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 696 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
697 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 698 apic->lapic_timer.period,
97222cc8 699 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 700 apic->lapic_timer.period)));
97222cc8
ED		 701}
702
cc6e462c
JK		 703static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
704{
705 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
706
707 if (apic_lvt_nmi_mode(lvt0_val)) {
708 if (!nmi_wd_enabled) {
709 apic_debug("Receive NMI setting on APIC_LVT0 "
710 "for cpu %d\n", apic->vcpu->vcpu_id);
711 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
712 }
713 } else if (nmi_wd_enabled)
714 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
715}
716
0105d1a5 717static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 718{
0105d1a5 719 int ret = 0;
97222cc8 720
0105d1a5 721 trace_kvm_apic_write(reg, val);
97222cc8 722
0105d1a5 723 switch (reg) {
97222cc8 724 case APIC_ID: /* Local APIC ID */
0105d1a5
GN		 725 if (!apic_x2apic_mode(apic))
726 apic_set_reg(apic, APIC_ID, val);
727 else
728 ret = 1;
97222cc8
ED		 729 break;
730
731 case APIC_TASKPRI:
b209749f 732 report_tpr_access(apic, true);
97222cc8
ED		 733 apic_set_tpr(apic, val & 0xff);
734 break;
735
736 case APIC_EOI:
737 apic_set_eoi(apic);
738 break;
739
740 case APIC_LDR:
0105d1a5
GN		 741 if (!apic_x2apic_mode(apic))
742 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
743 else
744 ret = 1;
97222cc8
ED		 745 break;
746
747 case APIC_DFR:
0105d1a5
GN		 748 if (!apic_x2apic_mode(apic))
749 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
750 else
751 ret = 1;
97222cc8
ED		 752 break;
753
fc61b800
GN		 754 case APIC_SPIV: {
755 u32 mask = 0x3ff;
756 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
757 mask |= APIC_SPIV_DIRECTED_EOI;
758 apic_set_reg(apic, APIC_SPIV, val & mask);
97222cc8
ED		 759 if (!(val & APIC_SPIV_APIC_ENABLED)) {
760 int i;
761 u32 lvt_val;
762
763 for (i = 0; i < APIC_LVT_NUM; i++) {
764 lvt_val = apic_get_reg(apic,
765 APIC_LVTT + 0x10 * i);
766 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
767 lvt_val | APIC_LVT_MASKED);
768 }
d3c7b77d 769 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 770
771 }
772 break;
fc61b800 773 }
97222cc8
ED		 774 case APIC_ICR:
775 /* No delay here, so we always clear the pending bit */
776 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
777 apic_send_ipi(apic);
778 break;
779
780 case APIC_ICR2:
0105d1a5
GN		 781 if (!apic_x2apic_mode(apic))
782 val &= 0xff000000;
783 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 784 break;
785
23930f95 786 case APIC_LVT0:
cc6e462c 787 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 788 case APIC_LVTT:
789 case APIC_LVTTHMR:
790 case APIC_LVTPC:
97222cc8
ED		 791 case APIC_LVT1:
792 case APIC_LVTERR:
793 /* TODO: Check vector */
794 if (!apic_sw_enabled(apic))
795 val |= APIC_LVT_MASKED;
796
0105d1a5
GN		 797 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
798 apic_set_reg(apic, reg, val);
97222cc8
ED		 799
800 break;
801
802 case APIC_TMICT:
d3c7b77d 803 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 804 apic_set_reg(apic, APIC_TMICT, val);
805 start_apic_timer(apic);
0105d1a5 806 break;
97222cc8
ED		 807
808 case APIC_TDCR:
809 if (val & 4)
810 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
811 apic_set_reg(apic, APIC_TDCR, val);
812 update_divide_count(apic);
813 break;
814
0105d1a5
GN		 815 case APIC_ESR:
816 if (apic_x2apic_mode(apic) && val != 0) {
817 printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
818 ret = 1;
819 }
820 break;
821
822 case APIC_SELF_IPI:
823 if (apic_x2apic_mode(apic)) {
824 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
825 } else
826 ret = 1;
827 break;
97222cc8 828 default:
0105d1a5 829 ret = 1;
97222cc8
ED		 830 break;
831 }
0105d1a5
GN		 832 if (ret)
833 apic_debug("Local APIC Write to read-only register %x\n", reg);
834 return ret;
835}
836
837static int apic_mmio_write(struct kvm_io_device *this,
838 gpa_t address, int len, const void *data)
839{
840 struct kvm_lapic *apic = to_lapic(this);
841 unsigned int offset = address - apic->base_address;
842 u32 val;
843
844 if (!apic_mmio_in_range(apic, address))
845 return -EOPNOTSUPP;
846
847 /*
848 * APIC register must be aligned on 128-bits boundary.
849 * 32/64/128 bits registers must be accessed thru 32 bits.
850 * Refer SDM 8.4.1
851 */
852 if (len != 4 || (offset & 0xf)) {
853 /* Don't shout loud, $infamous_os would cause only noise. */
854 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 855 return 0;
0105d1a5
GN		 856 }
857
858 val = *(u32*)data;
859
860 /* too common printing */
861 if (offset != APIC_EOI)
862 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
863 "0x%x\n", __func__, offset, len, val);
864
865 apic_reg_write(apic, offset & 0xff0, val);
866
bda9020e 867 return 0;
97222cc8
ED		 868}
869
d589444e 870void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 871{
ad312c7c 872 if (!vcpu->arch.apic)
97222cc8
ED		 873 return;
874
d3c7b77d 875 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 876
ad312c7c
ZX		 877 if (vcpu->arch.apic->regs_page)
878 __free_page(vcpu->arch.apic->regs_page);
97222cc8 879
ad312c7c 880 kfree(vcpu->arch.apic);
97222cc8
ED		 881}
882
883/*
884 *----------------------------------------------------------------------
885 * LAPIC interface
886 *----------------------------------------------------------------------
887 */
888
889void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
890{
ad312c7c 891 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 892
893 if (!apic)
894 return;
b93463aa
AK		 895 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
896 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 897}
898
899u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
900{
ad312c7c 901 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 902 u64 tpr;
903
904 if (!apic)
905 return 0;
906 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
907
908 return (tpr & 0xf0) >> 4;
909}
910
911void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
912{
ad312c7c 913 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 914
915 if (!apic) {
916 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 917 vcpu->arch.apic_base = value;
97222cc8
ED		 918 return;
919 }
c5af89b6
GN		 920
921 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 922 value &= ~MSR_IA32_APICBASE_BSP;
923
ad312c7c 924 vcpu->arch.apic_base = value;
0105d1a5
GN		 925 if (apic_x2apic_mode(apic)) {
926 u32 id = kvm_apic_id(apic);
927 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
928 apic_set_reg(apic, APIC_LDR, ldr);
929 }
ad312c7c 930 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 931 MSR_IA32_APICBASE_BASE;
932
933 /* with FSB delivery interrupt, we can restart APIC functionality */
934 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 935 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 936
937}
938
c5ec1534 939void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 940{
941 struct kvm_lapic *apic;
942 int i;
943
b8688d51 944 apic_debug("%s\n", __func__);
97222cc8
ED		 945
946 ASSERT(vcpu);
ad312c7c 947 apic = vcpu->arch.apic;
97222cc8
ED		 948 ASSERT(apic != NULL);
949
950 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 951 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 952
953 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
fc61b800 954 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 955
956 for (i = 0; i < APIC_LVT_NUM; i++)
957 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 958 apic_set_reg(apic, APIC_LVT0,
959 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 960
961 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
962 apic_set_reg(apic, APIC_SPIV, 0xff);
963 apic_set_reg(apic, APIC_TASKPRI, 0);
964 apic_set_reg(apic, APIC_LDR, 0);
965 apic_set_reg(apic, APIC_ESR, 0);
966 apic_set_reg(apic, APIC_ICR, 0);
967 apic_set_reg(apic, APIC_ICR2, 0);
968 apic_set_reg(apic, APIC_TDCR, 0);
969 apic_set_reg(apic, APIC_TMICT, 0);
970 for (i = 0; i < 8; i++) {
971 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
972 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
973 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
974 }
33e4c686 975 apic->irr_pending = false;
b33ac88b 976 update_divide_count(apic);
d3c7b77d 977 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 978 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 979 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 980 apic_update_ppr(apic);
981
e1035715
GN		 982 vcpu->arch.apic_arb_prio = 0;
983
97222cc8 984 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 985 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 986 vcpu, kvm_apic_id(apic),
ad312c7c 987 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 988}
989
343f94fe 990bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 991{
343f94fe
GN		 992 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
993}
97222cc8 994
343f94fe
GN		 995int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
996{
997 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 998}
999
1000/*
1001 *----------------------------------------------------------------------
1002 * timer interface
1003 *----------------------------------------------------------------------
1004 */
1b9778da 1005
d3c7b77d 1006static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 1007{
d3c7b77d
MT		 1008 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1009 lapic_timer);
1010 return apic_lvtt_period(apic);
97222cc8
ED		 1011}
1012
3d80840d
MT		 1013int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1014{
1015 struct kvm_lapic *lapic = vcpu->arch.apic;
1016
54aaacee 1017 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 1018 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 1019
1020 return 0;
1021}
1022
8fdb2351 1023static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1024{
8fdb2351 1025 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 1026 int vector, mode, trig_mode;
23930f95 1027
8fdb2351 1028 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1029 vector = reg & APIC_VECTOR_MASK;
1030 mode = reg & APIC_MODE_MASK;
1031 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1032 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1033 }
1034 return 0;
1035}
1b9778da 1036
8fdb2351 1037void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1038{
8fdb2351
JK		 1039 struct kvm_lapic *apic = vcpu->arch.apic;
1040
1041 if (apic)
1042 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1043}
1044
386eb6e8 1045static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 1046 .is_periodic = lapic_is_periodic,
1047};
97222cc8 1048
d76685c4
GH		 1049static const struct kvm_io_device_ops apic_mmio_ops = {
1050 .read = apic_mmio_read,
1051 .write = apic_mmio_write,
d76685c4
GH		 1052};
1053
97222cc8
ED		 1054int kvm_create_lapic(struct kvm_vcpu *vcpu)
1055{
1056 struct kvm_lapic *apic;
1057
1058 ASSERT(vcpu != NULL);
1059 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1060
1061 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1062 if (!apic)
1063 goto nomem;
1064
ad312c7c 1065 vcpu->arch.apic = apic;
97222cc8 1066
234bb549 1067 apic->regs_page = alloc_page(GFP_KERNEL|__GFP_ZERO);
97222cc8
ED		 1068 if (apic->regs_page == NULL) {
1069 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1070 vcpu->vcpu_id);
d589444e 1071 goto nomem_free_apic;
97222cc8
ED		 1072 }
1073 apic->regs = page_address(apic->regs_page);
97222cc8
ED		 1074 apic->vcpu = vcpu;
1075
d3c7b77d
MT		 1076 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1077 HRTIMER_MODE_ABS);
1078 apic->lapic_timer.timer.function = kvm_timer_fn;
1079 apic->lapic_timer.t_ops = &lapic_timer_ops;
1080 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 1081 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 1082
97222cc8 1083 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1084 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1085
c5ec1534 1086 kvm_lapic_reset(vcpu);
d76685c4 1087 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1088
1089 return 0;
d589444e
RR		 1090nomem_free_apic:
1091 kfree(apic);
97222cc8 1092nomem:
97222cc8
ED		 1093 return -ENOMEM;
1094}
97222cc8
ED		 1095
1096int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1097{
ad312c7c 1098 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1099 int highest_irr;
1100
1101 if (!apic || !apic_enabled(apic))
1102 return -1;
1103
6e5d865c 1104 apic_update_ppr(apic);
97222cc8
ED		 1105 highest_irr = apic_find_highest_irr(apic);
1106 if ((highest_irr == -1) ||
1107 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1108 return -1;
1109 return highest_irr;
1110}
1111
40487c68
QH		 1112int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1113{
ad312c7c 1114 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1115 int r = 0;
1116
e7dca5c0
CL		 1117 if (!apic_hw_enabled(vcpu->arch.apic))
1118 r = 1;
1119 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1120 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1121 r = 1;
40487c68
QH		 1122 return r;
1123}
1124
1b9778da
ED		 1125void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1126{
ad312c7c 1127 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1128
d3c7b77d 1129 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1130 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1131 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1132 }
1133}
1134
97222cc8
ED		 1135int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1136{
1137 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1138 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1139
1140 if (vector == -1)
1141 return -1;
1142
1143 apic_set_vector(vector, apic->regs + APIC_ISR);
1144 apic_update_ppr(apic);
1145 apic_clear_irr(vector, apic);
1146 return vector;
1147}
96ad2cc6
ED		 1148
1149void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1150{
ad312c7c 1151 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1152
ad312c7c 1153 apic->base_address = vcpu->arch.apic_base &
96ad2cc6 1154 MSR_IA32_APICBASE_BASE;
fc61b800
GN		 1155 kvm_apic_set_version(vcpu);
1156
96ad2cc6 1157 apic_update_ppr(apic);
d3c7b77d 1158 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1159 update_divide_count(apic);
1160 start_apic_timer(apic);
6e24a6ef 1161 apic->irr_pending = true;
3842d135 1162 kvm_make_request(KVM_REQ_EVENT, vcpu);
96ad2cc6 1163}
a3d7f85f 1164
2f52d58c 1165void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1166{
ad312c7c 1167 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1168 struct hrtimer *timer;
1169
1170 if (!apic)
1171 return;
1172
d3c7b77d 1173 timer = &apic->lapic_timer.timer;
a3d7f85f 1174 if (hrtimer_cancel(timer))
beb20d52 1175 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1176}
b93463aa
AK		 1177
1178void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1179{
1180 u32 data;
1181 void *vapic;
1182
1183 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1184 return;
1185
1186 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1187 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1188 kunmap_atomic(vapic, KM_USER0);
1189
1190 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1191}
1192
1193void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1194{
1195 u32 data, tpr;
1196 int max_irr, max_isr;
1197 struct kvm_lapic *apic;
1198 void *vapic;
1199
1200 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1201 return;
1202
1203 apic = vcpu->arch.apic;
1204 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1205 max_irr = apic_find_highest_irr(apic);
1206 if (max_irr < 0)
1207 max_irr = 0;
1208 max_isr = apic_find_highest_isr(apic);
1209 if (max_isr < 0)
1210 max_isr = 0;
1211 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1212
1213 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1214 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1215 kunmap_atomic(vapic, KM_USER0);
1216}
1217
1218void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1219{
1220 if (!irqchip_in_kernel(vcpu->kvm))
1221 return;
1222
1223 vcpu->arch.apic->vapic_addr = vapic_addr;
1224}
0105d1a5
GN		 1225
1226int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1227{
1228 struct kvm_lapic *apic = vcpu->arch.apic;
1229 u32 reg = (msr - APIC_BASE_MSR) << 4;
1230
1231 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1232 return 1;
1233
1234 /* if this is ICR write vector before command */
1235 if (msr == 0x830)
1236 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1237 return apic_reg_write(apic, reg, (u32)data);
1238}
1239
1240int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1241{
1242 struct kvm_lapic *apic = vcpu->arch.apic;
1243 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1244
1245 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1246 return 1;
1247
1248 if (apic_reg_read(apic, reg, 4, &low))
1249 return 1;
1250 if (msr == 0x830)
1251 apic_reg_read(apic, APIC_ICR2, 4, &high);
1252
1253 *data = (((u64)high) << 32) | low;
1254
1255 return 0;
1256}
10388a07
GN		 1257
1258int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1259{
1260 struct kvm_lapic *apic = vcpu->arch.apic;
1261
1262 if (!irqchip_in_kernel(vcpu->kvm))
1263 return 1;
1264
1265 /* if this is ICR write vector before command */
1266 if (reg == APIC_ICR)
1267 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1268 return apic_reg_write(apic, reg, (u32)data);
1269}
1270
1271int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1272{
1273 struct kvm_lapic *apic = vcpu->arch.apic;
1274 u32 low, high = 0;
1275
1276 if (!irqchip_in_kernel(vcpu->kvm))
1277 return 1;
1278
1279 if (apic_reg_read(apic, reg, 4, &low))
1280 return 1;
1281 if (reg == APIC_ICR)
1282 apic_reg_read(apic, APIC_ICR2, 4, &high);
1283
1284 *data = (((u64)high) << 32) | low;
1285
1286 return 0;
1287}
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