]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/lapic.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: use MDA for interrupt matching
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
1e08ec4a
GN		 136static void recalculate_apic_map(struct kvm *kvm)
137{
138 struct kvm_apic_map *new, *old = NULL;
139 struct kvm_vcpu *vcpu;
140 int i;
141
142 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
143
144 mutex_lock(&kvm->arch.apic_map_lock);
145
146 if (!new)
147 goto out;
148
149 new->ldr_bits = 8;
150 /* flat mode is default */
151 new->cid_shift = 8;
152 new->cid_mask = 0;
153 new->lid_mask = 0xff;
394457a9 154 new->broadcast = APIC_BROADCAST;
1e08ec4a
GN		 155
156 kvm_for_each_vcpu(i, vcpu, kvm) {
157 struct kvm_lapic *apic = vcpu->arch.apic;
1e08ec4a
GN		 158
159 if (!kvm_apic_present(vcpu))
160 continue;
161
1e08ec4a
GN		 162 if (apic_x2apic_mode(apic)) {
163 new->ldr_bits = 32;
164 new->cid_shift = 16;
45c3094a 165 new->cid_mask = new->lid_mask = 0xffff;
394457a9 166 new->broadcast = X2APIC_BROADCAST;
a3e339e1 167 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
173beedc
NA		 168 if (kvm_apic_get_reg(apic, APIC_DFR) ==
169 APIC_DFR_CLUSTER) {
170 new->cid_shift = 4;
171 new->cid_mask = 0xf;
172 new->lid_mask = 0xf;
a3e339e1
PB		 173 } else {
174 new->cid_shift = 8;
175 new->cid_mask = 0;
176 new->lid_mask = 0xff;
173beedc 177 }
1e08ec4a 178 }
a3e339e1
PB		 179
180 /*
181 * All APICs have to be configured in the same mode by an OS.
182 * We take advatage of this while building logical id loockup
183 * table. After reset APICs are in software disabled mode, so if
184 * we find apic with different setting we assume this is the mode
185 * OS wants all apics to be in; build lookup table accordingly.
186 */
187 if (kvm_apic_sw_enabled(apic))
188 break;
173beedc
NA		 189 }
190
191 kvm_for_each_vcpu(i, vcpu, kvm) {
192 struct kvm_lapic *apic = vcpu->arch.apic;
193 u16 cid, lid;
25995e5b 194 u32 ldr, aid;
1e08ec4a 195
df04d1d1
RK		 196 if (!kvm_apic_present(vcpu))
197 continue;
198
25995e5b 199 aid = kvm_apic_id(apic);
1e08ec4a
GN		 200 ldr = kvm_apic_get_reg(apic, APIC_LDR);
201 cid = apic_cluster_id(new, ldr);
202 lid = apic_logical_id(new, ldr);
203
25995e5b
RK		 204 if (aid < ARRAY_SIZE(new->phys_map))
205 new->phys_map[aid] = apic;
206 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 207 new->logical_map[cid][ffs(lid) - 1] = apic;
208 }
209out:
210 old = rcu_dereference_protected(kvm->arch.apic_map,
211 lockdep_is_held(&kvm->arch.apic_map_lock));
212 rcu_assign_pointer(kvm->arch.apic_map, new);
213 mutex_unlock(&kvm->arch.apic_map_lock);
214
215 if (old)
216 kfree_rcu(old, rcu);
c7c9c56c 217
3d81bc7e 218 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 219}
220
1e1b6c26
NA		 221static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
222{
e462755c 223 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 224
225 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 226
227 if (enabled != apic->sw_enabled) {
228 apic->sw_enabled = enabled;
229 if (enabled) {
1e1b6c26
NA		 230 static_key_slow_dec_deferred(&apic_sw_disabled);
231 recalculate_apic_map(apic->vcpu->kvm);
232 } else
233 static_key_slow_inc(&apic_sw_disabled.key);
234 }
235}
236
1e08ec4a
GN		 237static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
238{
239 apic_set_reg(apic, APIC_ID, id << 24);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
243static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
244{
245 apic_set_reg(apic, APIC_LDR, id);
246 recalculate_apic_map(apic->vcpu->kvm);
247}
248
97222cc8
ED		 249static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
250{
c48f1496 251 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 252}
253
254static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
255{
c48f1496 256 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 257}
258
a3e06bbe
LJ		 259static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
260{
f30ebc31 261 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 262}
263
97222cc8
ED		 264static inline int apic_lvtt_period(struct kvm_lapic *apic)
265{
f30ebc31 266 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 267}
268
269static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
270{
f30ebc31 271 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 272}
273
cc6e462c
JK		 274static inline int apic_lvt_nmi_mode(u32 lvt_val)
275{
276 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
277}
278
fc61b800
GN		 279void kvm_apic_set_version(struct kvm_vcpu *vcpu)
280{
281 struct kvm_lapic *apic = vcpu->arch.apic;
282 struct kvm_cpuid_entry2 *feat;
283 u32 v = APIC_VERSION;
284
c48f1496 285 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 286 return;
287
288 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
289 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
290 v |= APIC_LVR_DIRECTED_EOI;
291 apic_set_reg(apic, APIC_LVR, v);
292}
293
f1d24831 294static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 295 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 296 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
297 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
298 LINT_MASK, LINT_MASK, /* LVT0-1 */
299 LVT_MASK /* LVTERR */
300};
301
302static int find_highest_vector(void *bitmap)
303{
ecba9a52
TY		 304 int vec;
305 u32 *reg;
97222cc8 306
ecba9a52
TY		 307 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
308 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
309 reg = bitmap + REG_POS(vec);
310 if (*reg)
311 return fls(*reg) - 1 + vec;
312 }
97222cc8 313
ecba9a52 314 return -1;
97222cc8
ED		 315}
316
8680b94b
MT		 317static u8 count_vectors(void *bitmap)
318{
ecba9a52
TY		 319 int vec;
320 u32 *reg;
8680b94b 321 u8 count = 0;
ecba9a52
TY		 322
323 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
324 reg = bitmap + REG_POS(vec);
325 count += hweight32(*reg);
326 }
327
8680b94b
MT		 328 return count;
329}
330
705699a1 331void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 332{
333 u32 i, pir_val;
a20ed54d
YZ		 334
335 for (i = 0; i <= 7; i++) {
336 pir_val = xchg(&pir[i], 0);
337 if (pir_val)
705699a1 338 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 339 }
340}
705699a1
WV		 341EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
342
343void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
344{
345 struct kvm_lapic *apic = vcpu->arch.apic;
346
347 __kvm_apic_update_irr(pir, apic->regs);
348}
a20ed54d
YZ		 349EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
350
11f5cc05 351static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 352{
11f5cc05 353 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 354 /*
355 * irr_pending must be true if any interrupt is pending; set it after
356 * APIC_IRR to avoid race with apic_clear_irr
357 */
358 apic->irr_pending = true;
97222cc8
ED		 359}
360
33e4c686 361static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 362{
33e4c686 363 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 364}
365
366static inline int apic_find_highest_irr(struct kvm_lapic *apic)
367{
368 int result;
369
c7c9c56c
YZ		 370 /*
371 * Note that irr_pending is just a hint. It will be always
372 * true with virtual interrupt delivery enabled.
373 */
33e4c686
GN		 374 if (!apic->irr_pending)
375 return -1;
376
5a71785d 377 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 378 result = apic_search_irr(apic);
97222cc8
ED		 379 ASSERT(result == -1 || result >= 16);
380
381 return result;
382}
383
33e4c686
GN		 384static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
385{
56cc2406
WL		 386 struct kvm_vcpu *vcpu;
387
388 vcpu = apic->vcpu;
389
f210f757 390 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 391 /* try to update RVI */
f210f757 392 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 393 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 394 } else {
395 apic->irr_pending = false;
396 apic_clear_vector(vec, apic->regs + APIC_IRR);
397 if (apic_search_irr(apic) != -1)
398 apic->irr_pending = true;
56cc2406 399 }
33e4c686
GN		 400}
401
8680b94b
MT		 402static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
403{
56cc2406
WL		 404 struct kvm_vcpu *vcpu;
405
406 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
407 return;
408
409 vcpu = apic->vcpu;
fc57ac2c 410
8680b94b 411 /*
56cc2406
WL		 412 * With APIC virtualization enabled, all caching is disabled
413 * because the processor can modify ISR under the hood. Instead
414 * just set SVI.
8680b94b 415 */
b4eef9b3 416 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 417 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
418 else {
419 ++apic->isr_count;
420 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
421 /*
422 * ISR (in service register) bit is set when injecting an interrupt.
423 * The highest vector is injected. Thus the latest bit set matches
424 * the highest bit in ISR.
425 */
426 apic->highest_isr_cache = vec;
427 }
8680b94b
MT		 428}
429
fc57ac2c
PB		 430static inline int apic_find_highest_isr(struct kvm_lapic *apic)
431{
432 int result;
433
434 /*
435 * Note that isr_count is always 1, and highest_isr_cache
436 * is always -1, with APIC virtualization enabled.
437 */
438 if (!apic->isr_count)
439 return -1;
440 if (likely(apic->highest_isr_cache != -1))
441 return apic->highest_isr_cache;
442
443 result = find_highest_vector(apic->regs + APIC_ISR);
444 ASSERT(result == -1 || result >= 16);
445
446 return result;
447}
448
8680b94b
MT		 449static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
450{
fc57ac2c
PB		 451 struct kvm_vcpu *vcpu;
452 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
453 return;
454
455 vcpu = apic->vcpu;
456
457 /*
458 * We do get here for APIC virtualization enabled if the guest
459 * uses the Hyper-V APIC enlightenment. In this case we may need
460 * to trigger a new interrupt delivery by writing the SVI field;
461 * on the other hand isr_count and highest_isr_cache are unused
462 * and must be left alone.
463 */
b4eef9b3 464 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 465 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
466 apic_find_highest_isr(apic));
467 else {
8680b94b 468 --apic->isr_count;
fc57ac2c
PB		 469 BUG_ON(apic->isr_count < 0);
470 apic->highest_isr_cache = -1;
471 }
8680b94b
MT		 472}
473
6e5d865c
YS		 474int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
475{
6e5d865c
YS		 476 int highest_irr;
477
33e4c686
GN		 478 /* This may race with setting of irr in __apic_accept_irq() and
479 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
480 * will cause vmexit immediately and the value will be recalculated
481 * on the next vmentry.
482 */
c48f1496 483 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 484 return 0;
54e9818f 485 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 486
487 return highest_irr;
488}
6e5d865c 489
6da7e3f6 490static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 491 int vector, int level, int trig_mode,
492 unsigned long *dest_map);
6da7e3f6 493
b4f2225c
YZ		 494int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
495 unsigned long *dest_map)
97222cc8 496{
ad312c7c 497 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 498
58c2dde1 499 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 500 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 501}
502
ae7a2a3f
MT		 503static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
504{
505
506 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
507 sizeof(val));
508}
509
510static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
511{
512
513 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
514 sizeof(*val));
515}
516
517static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
518{
519 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
520}
521
522static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
523{
524 u8 val;
525 if (pv_eoi_get_user(vcpu, &val) < 0)
526 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 527 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 528 return val & 0x1;
529}
530
531static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
532{
533 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
534 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 535 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 536 return;
537 }
538 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
539}
540
541static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
542{
543 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
544 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 545 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 546 return;
547 }
548 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
549}
550
cf9e65b7
YZ		 551void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
552{
553 struct kvm_lapic *apic = vcpu->arch.apic;
554 int i;
555
556 for (i = 0; i < 8; i++)
557 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
558}
559
97222cc8
ED		 560static void apic_update_ppr(struct kvm_lapic *apic)
561{
3842d135 562 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 563 int isr;
564
c48f1496
GN		 565 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
566 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 567 isr = apic_find_highest_isr(apic);
568 isrv = (isr != -1) ? isr : 0;
569
570 if ((tpr & 0xf0) >= (isrv & 0xf0))
571 ppr = tpr & 0xff;
572 else
573 ppr = isrv & 0xf0;
574
575 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
576 apic, ppr, isr, isrv);
577
3842d135
AK		 578 if (old_ppr != ppr) {
579 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 580 if (ppr < old_ppr)
581 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 582 }
97222cc8
ED		 583}
584
585static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
586{
587 apic_set_reg(apic, APIC_TASKPRI, tpr);
588 apic_update_ppr(apic);
589}
590
03d2249e 591static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 592{
03d2249e
RK		 593 if (apic_x2apic_mode(apic))
594 return mda == X2APIC_BROADCAST;
595
596 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 597}
598
03d2249e 599static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 600{
03d2249e
RK		 601 if (kvm_apic_broadcast(apic, mda))
602 return true;
603
604 if (apic_x2apic_mode(apic))
605 return mda == kvm_apic_id(apic);
606
607 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 608}
609
52c233a4 610static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 611{
0105d1a5
GN		 612 u32 logical_id;
613
394457a9 614 if (kvm_apic_broadcast(apic, mda))
9368b567 615 return true;
394457a9 616
9368b567 617 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 618
9368b567 619 if (apic_x2apic_mode(apic))
8a395363
RK		 620 return ((logical_id >> 16) == (mda >> 16))
621 && (logical_id & mda & 0xffff) != 0;
97222cc8 622
9368b567 623 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 624 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 625
c48f1496 626 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 627 case APIC_DFR_FLAT:
9368b567 628 return (logical_id & mda) != 0;
97222cc8 629 case APIC_DFR_CLUSTER:
9368b567
RK		 630 return ((logical_id >> 4) == (mda >> 4))
631 && (logical_id & mda & 0xf) != 0;
97222cc8 632 default:
7712de87 633 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 634 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 635 return false;
97222cc8 636 }
97222cc8
ED		 637}
638
03d2249e
RK		 639/* KVM APIC implementation has two quirks
640 * - dest always begins at 0 while xAPIC MDA has offset 24,
641 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
642 */
643static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
644 struct kvm_lapic *target)
645{
646 bool ipi = source != NULL;
647 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
648
649 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
650 return X2APIC_BROADCAST;
651
652 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
653}
654
52c233a4 655bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 656 int short_hand, unsigned int dest, int dest_mode)
97222cc8 657{
ad312c7c 658 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 659 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 660
661 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 662 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 663 target, source, dest, dest_mode, short_hand);
664
bd371396 665 ASSERT(target);
97222cc8
ED		 666 switch (short_hand) {
667 case APIC_DEST_NOSHORT:
3697f302 668 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 669 return kvm_apic_match_physical_addr(target, mda);
343f94fe 670 else
03d2249e 671 return kvm_apic_match_logical_addr(target, mda);
97222cc8 672 case APIC_DEST_SELF:
9368b567 673 return target == source;
97222cc8 674 case APIC_DEST_ALLINC:
9368b567 675 return true;
97222cc8 676 case APIC_DEST_ALLBUT:
9368b567 677 return target != source;
97222cc8 678 default:
7712de87
JK		 679 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
680 short_hand);
9368b567 681 return false;
97222cc8 682 }
97222cc8
ED		 683}
684
1e08ec4a 685bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 686 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 687{
688 struct kvm_apic_map *map;
689 unsigned long bitmap = 1;
690 struct kvm_lapic **dst;
691 int i;
692 bool ret = false;
693
694 *r = -1;
695
696 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 697 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 698 return true;
699 }
700
701 if (irq->shorthand)
702 return false;
703
704 rcu_read_lock();
705 map = rcu_dereference(kvm->arch.apic_map);
706
707 if (!map)
708 goto out;
709
394457a9
NA		 710 if (irq->dest_id == map->broadcast)
711 goto out;
712
698f9755
RK		 713 ret = true;
714
3697f302 715 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 716 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
717 goto out;
718
719 dst = &map->phys_map[irq->dest_id];
1e08ec4a
GN		 720 } else {
721 u32 mda = irq->dest_id << (32 - map->ldr_bits);
45c3094a
RK		 722 u16 cid = apic_cluster_id(map, mda);
723
724 if (cid >= ARRAY_SIZE(map->logical_map))
725 goto out;
1e08ec4a 726
45c3094a 727 dst = map->logical_map[cid];
1e08ec4a
GN		 728
729 bitmap = apic_logical_id(map, mda);
730
731 if (irq->delivery_mode == APIC_DM_LOWEST) {
732 int l = -1;
733 for_each_set_bit(i, &bitmap, 16) {
734 if (!dst[i])
735 continue;
736 if (l < 0)
737 l = i;
738 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
739 l = i;
740 }
741
742 bitmap = (l >= 0) ? 1 << l : 0;
743 }
744 }
745
746 for_each_set_bit(i, &bitmap, 16) {
747 if (!dst[i])
748 continue;
749 if (*r < 0)
750 *r = 0;
b4f2225c 751 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 752 }
1e08ec4a
GN		 753out:
754 rcu_read_unlock();
755 return ret;
756}
757
97222cc8
ED		 758/*
759 * Add a pending IRQ into lapic.
760 * Return 1 if successfully added and 0 if discarded.
761 */
762static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 763 int vector, int level, int trig_mode,
764 unsigned long *dest_map)
97222cc8 765{
6da7e3f6 766 int result = 0;
c5ec1534 767 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 768
a183b638
PB		 769 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
770 trig_mode, vector);
97222cc8 771 switch (delivery_mode) {
97222cc8 772 case APIC_DM_LOWEST:
e1035715
GN		 773 vcpu->arch.apic_arb_prio++;
774 case APIC_DM_FIXED:
97222cc8
ED		 775 /* FIXME add logic for vcpu on reset */
776 if (unlikely(!apic_enabled(apic)))
777 break;
778
11f5cc05
JK		 779 result = 1;
780
b4f2225c
YZ		 781 if (dest_map)
782 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 783
11f5cc05 784 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 785 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 786 else {
787 apic_set_irr(vector, apic);
5a71785d
YZ		 788
789 kvm_make_request(KVM_REQ_EVENT, vcpu);
790 kvm_vcpu_kick(vcpu);
791 }
97222cc8
ED		 792 break;
793
794 case APIC_DM_REMRD:
24d2166b
R		 795 result = 1;
796 vcpu->arch.pv.pv_unhalted = 1;
797 kvm_make_request(KVM_REQ_EVENT, vcpu);
798 kvm_vcpu_kick(vcpu);
97222cc8
ED		 799 break;
800
801 case APIC_DM_SMI:
7712de87 802 apic_debug("Ignoring guest SMI\n");
97222cc8 803 break;
3419ffc8 804
97222cc8 805 case APIC_DM_NMI:
6da7e3f6 806 result = 1;
3419ffc8 807 kvm_inject_nmi(vcpu);
26df99c6 808 kvm_vcpu_kick(vcpu);
97222cc8
ED		 809 break;
810
811 case APIC_DM_INIT:
a52315e1 812 if (!trig_mode || level) {
6da7e3f6 813 result = 1;
66450a21
JK		 814 /* assumes that there are only KVM_APIC_INIT/SIPI */
815 apic->pending_events = (1UL << KVM_APIC_INIT);
816 /* make sure pending_events is visible before sending
817 * the request */
818 smp_wmb();
3842d135 819 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 820 kvm_vcpu_kick(vcpu);
821 } else {
1b10bf31
JK		 822 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
823 vcpu->vcpu_id);
c5ec1534 824 }
97222cc8
ED		 825 break;
826
827 case APIC_DM_STARTUP:
1b10bf31
JK		 828 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
829 vcpu->vcpu_id, vector);
66450a21
JK		 830 result = 1;
831 apic->sipi_vector = vector;
832 /* make sure sipi_vector is visible for the receiver */
833 smp_wmb();
834 set_bit(KVM_APIC_SIPI, &apic->pending_events);
835 kvm_make_request(KVM_REQ_EVENT, vcpu);
836 kvm_vcpu_kick(vcpu);
97222cc8
ED		 837 break;
838
23930f95
JK		 839 case APIC_DM_EXTINT:
840 /*
841 * Should only be called by kvm_apic_local_deliver() with LVT0,
842 * before NMI watchdog was enabled. Already handled by
843 * kvm_apic_accept_pic_intr().
844 */
845 break;
846
97222cc8
ED		 847 default:
848 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
849 delivery_mode);
850 break;
851 }
852 return result;
853}
854
e1035715 855int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 856{
e1035715 857 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 858}
859
c7c9c56c
YZ		 860static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
861{
862 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
863 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
864 int trigger_mode;
865 if (apic_test_vector(vector, apic->regs + APIC_TMR))
866 trigger_mode = IOAPIC_LEVEL_TRIG;
867 else
868 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 869 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 870 }
871}
872
ae7a2a3f 873static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 874{
875 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 876
877 trace_kvm_eoi(apic, vector);
878
97222cc8
ED		 879 /*
880 * Not every write EOI will has corresponding ISR,
881 * one example is when Kernel check timer on setup_IO_APIC
882 */
883 if (vector == -1)
ae7a2a3f 884 return vector;
97222cc8 885
8680b94b 886 apic_clear_isr(vector, apic);
97222cc8
ED		 887 apic_update_ppr(apic);
888
c7c9c56c 889 kvm_ioapic_send_eoi(apic, vector);
3842d135 890 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 891 return vector;
97222cc8
ED		 892}
893
c7c9c56c
YZ		 894/*
895 * this interface assumes a trap-like exit, which has already finished
896 * desired side effect including vISR and vPPR update.
897 */
898void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
899{
900 struct kvm_lapic *apic = vcpu->arch.apic;
901
902 trace_kvm_eoi(apic, vector);
903
904 kvm_ioapic_send_eoi(apic, vector);
905 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
906}
907EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
908
97222cc8
ED		 909static void apic_send_ipi(struct kvm_lapic *apic)
910{
c48f1496
GN		 911 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
912 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 913 struct kvm_lapic_irq irq;
97222cc8 914
58c2dde1
GN		 915 irq.vector = icr_low & APIC_VECTOR_MASK;
916 irq.delivery_mode = icr_low & APIC_MODE_MASK;
917 irq.dest_mode = icr_low & APIC_DEST_MASK;
918 irq.level = icr_low & APIC_INT_ASSERT;
919 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
920 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 921 if (apic_x2apic_mode(apic))
922 irq.dest_id = icr_high;
923 else
924 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 925
1000ff8d
GN		 926 trace_kvm_apic_ipi(icr_low, irq.dest_id);
927
97222cc8
ED		 928 apic_debug("icr_high 0x%x, icr_low 0x%x, "
929 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
930 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 931 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 932 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
933 irq.vector);
934
b4f2225c 935 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 936}
937
938static u32 apic_get_tmcct(struct kvm_lapic *apic)
939{
b682b814
MT		 940 ktime_t remaining;
941 s64 ns;
9da8f4e8 942 u32 tmcct;
97222cc8
ED		 943
944 ASSERT(apic != NULL);
945
9da8f4e8 946 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 947 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
948 apic->lapic_timer.period == 0)
9da8f4e8
KP		 949 return 0;
950
ace15464 951 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 952 if (ktime_to_ns(remaining) < 0)
953 remaining = ktime_set(0, 0);
954
d3c7b77d
MT		 955 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
956 tmcct = div64_u64(ns,
957 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 958
959 return tmcct;
960}
961
b209749f
AK		 962static void __report_tpr_access(struct kvm_lapic *apic, bool write)
963{
964 struct kvm_vcpu *vcpu = apic->vcpu;
965 struct kvm_run *run = vcpu->run;
966
a8eeb04a 967 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 968 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 969 run->tpr_access.is_write = write;
970}
971
972static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
973{
974 if (apic->vcpu->arch.tpr_access_reporting)
975 __report_tpr_access(apic, write);
976}
977
97222cc8
ED		 978static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
979{
980 u32 val = 0;
981
982 if (offset >= LAPIC_MMIO_LENGTH)
983 return 0;
984
985 switch (offset) {
0105d1a5
GN		 986 case APIC_ID:
987 if (apic_x2apic_mode(apic))
988 val = kvm_apic_id(apic);
989 else
990 val = kvm_apic_id(apic) << 24;
991 break;
97222cc8 992 case APIC_ARBPRI:
7712de87 993 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 994 break;
995
996 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 997 if (apic_lvtt_tscdeadline(apic))
998 return 0;
999
97222cc8
ED		 1000 val = apic_get_tmcct(apic);
1001 break;
4a4541a4
AK		 1002 case APIC_PROCPRI:
1003 apic_update_ppr(apic);
c48f1496 1004 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1005 break;
b209749f
AK		 1006 case APIC_TASKPRI:
1007 report_tpr_access(apic, false);
1008 /* fall thru */
97222cc8 1009 default:
c48f1496 1010 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1011 break;
1012 }
1013
1014 return val;
1015}
1016
d76685c4
GH		 1017static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1018{
1019 return container_of(dev, struct kvm_lapic, dev);
1020}
1021
0105d1a5
GN		 1022static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1023 void *data)
97222cc8 1024{
97222cc8
ED		 1025 unsigned char alignment = offset & 0xf;
1026 u32 result;
d5b0b5b1 1027 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1028 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1029
1030 if ((alignment + len) > 4) {
4088bb3c
GN		 1031 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1032 offset, len);
0105d1a5 1033 return 1;
97222cc8 1034 }
0105d1a5
GN		 1035
1036 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1037 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1038 offset);
0105d1a5
GN		 1039 return 1;
1040 }
1041
97222cc8
ED		 1042 result = __apic_read(apic, offset & ~0xf);
1043
229456fc
MT		 1044 trace_kvm_apic_read(offset, result);
1045
97222cc8
ED		 1046 switch (len) {
1047 case 1:
1048 case 2:
1049 case 4:
1050 memcpy(data, (char *)&result + alignment, len);
1051 break;
1052 default:
1053 printk(KERN_ERR "Local APIC read with len = %x, "
1054 "should be 1,2, or 4 instead\n", len);
1055 break;
1056 }
bda9020e 1057 return 0;
97222cc8
ED		 1058}
1059
0105d1a5
GN		 1060static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1061{
c48f1496 1062 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1063 addr >= apic->base_address &&
1064 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1065}
1066
e32edf4f 1067static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1068 gpa_t address, int len, void *data)
1069{
1070 struct kvm_lapic *apic = to_lapic(this);
1071 u32 offset = address - apic->base_address;
1072
1073 if (!apic_mmio_in_range(apic, address))
1074 return -EOPNOTSUPP;
1075
1076 apic_reg_read(apic, offset, len, data);
1077
1078 return 0;
1079}
1080
97222cc8
ED		 1081static void update_divide_count(struct kvm_lapic *apic)
1082{
1083 u32 tmp1, tmp2, tdcr;
1084
c48f1496 1085 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1086 tmp1 = tdcr & 0xf;
1087 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1088 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1089
1090 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1091 apic->divide_count);
97222cc8
ED		 1092}
1093
5d87db71
RK		 1094static void apic_timer_expired(struct kvm_lapic *apic)
1095{
1096 struct kvm_vcpu *vcpu = apic->vcpu;
1097 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1098 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1099
5d87db71
RK		 1100 if (atomic_read(&apic->lapic_timer.pending))
1101 return;
1102
1103 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1104 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1105
1106 if (waitqueue_active(q))
1107 wake_up_interruptible(q);
d0659d94
MT		 1108
1109 if (apic_lvtt_tscdeadline(apic))
1110 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1111}
1112
1113/*
1114 * On APICv, this test will cause a busy wait
1115 * during a higher-priority task.
1116 */
1117
1118static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1119{
1120 struct kvm_lapic *apic = vcpu->arch.apic;
1121 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1122
1123 if (kvm_apic_hw_enabled(apic)) {
1124 int vec = reg & APIC_VECTOR_MASK;
f9339860 1125 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1126
f9339860
MT		 1127 if (kvm_x86_ops->deliver_posted_interrupt)
1128 bitmap = apic->regs + APIC_IRR;
1129
1130 if (apic_test_vector(vec, bitmap))
1131 return true;
d0659d94
MT		 1132 }
1133 return false;
1134}
1135
1136void wait_lapic_expire(struct kvm_vcpu *vcpu)
1137{
1138 struct kvm_lapic *apic = vcpu->arch.apic;
1139 u64 guest_tsc, tsc_deadline;
1140
1141 if (!kvm_vcpu_has_lapic(vcpu))
1142 return;
1143
1144 if (apic->lapic_timer.expired_tscdeadline == 0)
1145 return;
1146
1147 if (!lapic_timer_int_injected(vcpu))
1148 return;
1149
1150 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1151 apic->lapic_timer.expired_tscdeadline = 0;
1152 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
6c19b753 1153 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1154
1155 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1156 if (guest_tsc < tsc_deadline)
1157 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1158}
1159
97222cc8
ED		 1160static void start_apic_timer(struct kvm_lapic *apic)
1161{
a3e06bbe 1162 ktime_t now;
d0659d94 1163
d3c7b77d 1164 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1165
a3e06bbe 1166 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1167 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1168 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1169 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1170 * APIC_BUS_CYCLE_NS * apic->divide_count;
1171
1172 if (!apic->lapic_timer.period)
1173 return;
1174 /*
1175 * Do not allow the guest to program periodic timers with small
1176 * interval, since the hrtimers are not throttled by the host
1177 * scheduler.
1178 */
1179 if (apic_lvtt_period(apic)) {
1180 s64 min_period = min_timer_period_us * 1000LL;
1181
1182 if (apic->lapic_timer.period < min_period) {
1183 pr_info_ratelimited(
1184 "kvm: vcpu %i: requested %lld ns "
1185 "lapic timer period limited to %lld ns\n",
1186 apic->vcpu->vcpu_id,
1187 apic->lapic_timer.period, min_period);
1188 apic->lapic_timer.period = min_period;
1189 }
9bc5791d 1190 }
0b975a3c 1191
a3e06bbe
LJ		 1192 hrtimer_start(&apic->lapic_timer.timer,
1193 ktime_add_ns(now, apic->lapic_timer.period),
1194 HRTIMER_MODE_ABS);
97222cc8 1195
a3e06bbe 1196 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1197 PRIx64 ", "
1198 "timer initial count 0x%x, period %lldns, "
b8688d51 1199 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1200 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1201 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1202 apic->lapic_timer.period,
97222cc8 1203 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1204 apic->lapic_timer.period)));
a3e06bbe
LJ		 1205 } else if (apic_lvtt_tscdeadline(apic)) {
1206 /* lapic timer in tsc deadline mode */
1207 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1208 u64 ns = 0;
d0659d94 1209 ktime_t expire;
a3e06bbe 1210 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1211 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1212 unsigned long flags;
1213
1214 if (unlikely(!tscdeadline || !this_tsc_khz))
1215 return;
1216
1217 local_irq_save(flags);
1218
1219 now = apic->lapic_timer.timer.base->get_time();
886b470c 1220 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1221 if (likely(tscdeadline > guest_tsc)) {
1222 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1223 do_div(ns, this_tsc_khz);
d0659d94
MT		 1224 expire = ktime_add_ns(now, ns);
1225 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1226 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1227 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1228 } else
1229 apic_timer_expired(apic);
a3e06bbe
LJ		 1230
1231 local_irq_restore(flags);
1232 }
97222cc8
ED		 1233}
1234
cc6e462c
JK		 1235static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1236{
c48f1496 1237 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1238
1239 if (apic_lvt_nmi_mode(lvt0_val)) {
1240 if (!nmi_wd_enabled) {
1241 apic_debug("Receive NMI setting on APIC_LVT0 "
1242 "for cpu %d\n", apic->vcpu->vcpu_id);
1243 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1244 }
1245 } else if (nmi_wd_enabled)
1246 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1247}
1248
0105d1a5 1249static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1250{
0105d1a5 1251 int ret = 0;
97222cc8 1252
0105d1a5 1253 trace_kvm_apic_write(reg, val);
97222cc8 1254
0105d1a5 1255 switch (reg) {
97222cc8 1256 case APIC_ID: /* Local APIC ID */
0105d1a5 1257 if (!apic_x2apic_mode(apic))
1e08ec4a 1258 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1259 else
1260 ret = 1;
97222cc8
ED		 1261 break;
1262
1263 case APIC_TASKPRI:
b209749f 1264 report_tpr_access(apic, true);
97222cc8
ED		 1265 apic_set_tpr(apic, val & 0xff);
1266 break;
1267
1268 case APIC_EOI:
1269 apic_set_eoi(apic);
1270 break;
1271
1272 case APIC_LDR:
0105d1a5 1273 if (!apic_x2apic_mode(apic))
1e08ec4a 1274 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1275 else
1276 ret = 1;
97222cc8
ED		 1277 break;
1278
1279 case APIC_DFR:
1e08ec4a 1280 if (!apic_x2apic_mode(apic)) {
0105d1a5 1281 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1282 recalculate_apic_map(apic->vcpu->kvm);
1283 } else
0105d1a5 1284 ret = 1;
97222cc8
ED		 1285 break;
1286
fc61b800
GN		 1287 case APIC_SPIV: {
1288 u32 mask = 0x3ff;
c48f1496 1289 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1290 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1291 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1292 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1293 int i;
1294 u32 lvt_val;
1295
1296 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1297 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1298 APIC_LVTT + 0x10 * i);
1299 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1300 lvt_val | APIC_LVT_MASKED);
1301 }
d3c7b77d 1302 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1303
1304 }
1305 break;
fc61b800 1306 }
97222cc8
ED		 1307 case APIC_ICR:
1308 /* No delay here, so we always clear the pending bit */
1309 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1310 apic_send_ipi(apic);
1311 break;
1312
1313 case APIC_ICR2:
0105d1a5
GN		 1314 if (!apic_x2apic_mode(apic))
1315 val &= 0xff000000;
1316 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1317 break;
1318
23930f95 1319 case APIC_LVT0:
cc6e462c 1320 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1321 case APIC_LVTTHMR:
1322 case APIC_LVTPC:
97222cc8
ED		 1323 case APIC_LVT1:
1324 case APIC_LVTERR:
1325 /* TODO: Check vector */
c48f1496 1326 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1327 val |= APIC_LVT_MASKED;
1328
0105d1a5
GN		 1329 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1330 apic_set_reg(apic, reg, val);
97222cc8
ED		 1331
1332 break;
1333
a323b409
RK		 1334 case APIC_LVTT: {
1335 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1336
1337 if (apic->lapic_timer.timer_mode != timer_mode) {
1338 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1339 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1340 }
a3e06bbe 1341
c48f1496 1342 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1343 val |= APIC_LVT_MASKED;
1344 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1345 apic_set_reg(apic, APIC_LVTT, val);
1346 break;
a323b409 1347 }
a3e06bbe 1348
97222cc8 1349 case APIC_TMICT:
a3e06bbe
LJ		 1350 if (apic_lvtt_tscdeadline(apic))
1351 break;
1352
d3c7b77d 1353 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1354 apic_set_reg(apic, APIC_TMICT, val);
1355 start_apic_timer(apic);
0105d1a5 1356 break;
97222cc8
ED		 1357
1358 case APIC_TDCR:
1359 if (val & 4)
7712de87 1360 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1361 apic_set_reg(apic, APIC_TDCR, val);
1362 update_divide_count(apic);
1363 break;
1364
0105d1a5
GN		 1365 case APIC_ESR:
1366 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1367 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1368 ret = 1;
1369 }
1370 break;
1371
1372 case APIC_SELF_IPI:
1373 if (apic_x2apic_mode(apic)) {
1374 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1375 } else
1376 ret = 1;
1377 break;
97222cc8 1378 default:
0105d1a5 1379 ret = 1;
97222cc8
ED		 1380 break;
1381 }
0105d1a5
GN		 1382 if (ret)
1383 apic_debug("Local APIC Write to read-only register %x\n", reg);
1384 return ret;
1385}
1386
e32edf4f 1387static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1388 gpa_t address, int len, const void *data)
1389{
1390 struct kvm_lapic *apic = to_lapic(this);
1391 unsigned int offset = address - apic->base_address;
1392 u32 val;
1393
1394 if (!apic_mmio_in_range(apic, address))
1395 return -EOPNOTSUPP;
1396
1397 /*
1398 * APIC register must be aligned on 128-bits boundary.
1399 * 32/64/128 bits registers must be accessed thru 32 bits.
1400 * Refer SDM 8.4.1
1401 */
1402 if (len != 4 || (offset & 0xf)) {
1403 /* Don't shout loud, $infamous_os would cause only noise. */
1404 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1405 return 0;
0105d1a5
GN		 1406 }
1407
1408 val = *(u32*)data;
1409
1410 /* too common printing */
1411 if (offset != APIC_EOI)
1412 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1413 "0x%x\n", __func__, offset, len, val);
1414
1415 apic_reg_write(apic, offset & 0xff0, val);
1416
bda9020e 1417 return 0;
97222cc8
ED		 1418}
1419
58fbbf26
KT		 1420void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1421{
c48f1496 1422 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1423 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1424}
1425EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1426
83d4c286
YZ		 1427/* emulate APIC access in a trap manner */
1428void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1429{
1430 u32 val = 0;
1431
1432 /* hw has done the conditional check and inst decode */
1433 offset &= 0xff0;
1434
1435 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1436
1437 /* TODO: optimize to just emulate side effect w/o one more write */
1438 apic_reg_write(vcpu->arch.apic, offset, val);
1439}
1440EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1441
d589444e 1442void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1443{
f8c1ea10
GN		 1444 struct kvm_lapic *apic = vcpu->arch.apic;
1445
ad312c7c 1446 if (!vcpu->arch.apic)
97222cc8
ED		 1447 return;
1448
f8c1ea10 1449 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1450
c5cc421b
GN		 1451 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1452 static_key_slow_dec_deferred(&apic_hw_disabled);
1453
e462755c 1454 if (!apic->sw_enabled)
f8c1ea10 1455 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1456
f8c1ea10
GN		 1457 if (apic->regs)
1458 free_page((unsigned long)apic->regs);
1459
1460 kfree(apic);
97222cc8
ED		 1461}
1462
1463/*
1464 *----------------------------------------------------------------------
1465 * LAPIC interface
1466 *----------------------------------------------------------------------
1467 */
1468
a3e06bbe
LJ		 1469u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1470{
1471 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1472
c48f1496 1473 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1474 apic_lvtt_period(apic))
a3e06bbe
LJ		 1475 return 0;
1476
1477 return apic->lapic_timer.tscdeadline;
1478}
1479
1480void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1481{
1482 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1483
c48f1496 1484 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1485 apic_lvtt_period(apic))
a3e06bbe
LJ		 1486 return;
1487
1488 hrtimer_cancel(&apic->lapic_timer.timer);
1489 apic->lapic_timer.tscdeadline = data;
1490 start_apic_timer(apic);
1491}
1492
97222cc8
ED		 1493void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1494{
ad312c7c 1495 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1496
c48f1496 1497 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1498 return;
54e9818f 1499
b93463aa 1500 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1501 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1502}
1503
1504u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1505{
97222cc8
ED		 1506 u64 tpr;
1507
c48f1496 1508 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1509 return 0;
54e9818f 1510
c48f1496 1511 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1512
1513 return (tpr & 0xf0) >> 4;
1514}
1515
1516void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1517{
8d14695f 1518 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1519 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1520
1521 if (!apic) {
1522 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1523 vcpu->arch.apic_base = value;
97222cc8
ED		 1524 return;
1525 }
c5af89b6 1526
e66d2ae7
JK		 1527 if (!kvm_vcpu_is_bsp(apic->vcpu))
1528 value &= ~MSR_IA32_APICBASE_BSP;
1529 vcpu->arch.apic_base = value;
1530
c5cc421b 1531 /* update jump label if enable bit changes */
0dce7cd6 1532 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1533 if (value & MSR_IA32_APICBASE_ENABLE)
1534 static_key_slow_dec_deferred(&apic_hw_disabled);
1535 else
1536 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1537 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1538 }
1539
8d14695f
YZ		 1540 if ((old_value ^ value) & X2APIC_ENABLE) {
1541 if (value & X2APIC_ENABLE) {
1542 u32 id = kvm_apic_id(apic);
1543 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1544 kvm_apic_set_ldr(apic, ldr);
1545 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1546 } else
1547 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1548 }
8d14695f 1549
ad312c7c 1550 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1551 MSR_IA32_APICBASE_BASE;
1552
db324fe6
NA		 1553 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1554 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1555 pr_warn_once("APIC base relocation is unsupported by KVM");
1556
97222cc8
ED		 1557 /* with FSB delivery interrupt, we can restart APIC functionality */
1558 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1559 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1560
1561}
1562
c5ec1534 1563void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 1564{
1565 struct kvm_lapic *apic;
1566 int i;
1567
b8688d51 1568 apic_debug("%s\n", __func__);
97222cc8
ED		 1569
1570 ASSERT(vcpu);
ad312c7c 1571 apic = vcpu->arch.apic;
97222cc8
ED		 1572 ASSERT(apic != NULL);
1573
1574 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1575 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1576
1e08ec4a 1577 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1578 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1579
1580 for (i = 0; i < APIC_LVT_NUM; i++)
1581 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1582 apic->lapic_timer.timer_mode = 0;
40487c68
QH		 1583 apic_set_reg(apic, APIC_LVT0,
1584 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1585
1586 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1587 apic_set_spiv(apic, 0xff);
97222cc8 1588 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1589 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1590 apic_set_reg(apic, APIC_ESR, 0);
1591 apic_set_reg(apic, APIC_ICR, 0);
1592 apic_set_reg(apic, APIC_ICR2, 0);
1593 apic_set_reg(apic, APIC_TDCR, 0);
1594 apic_set_reg(apic, APIC_TMICT, 0);
1595 for (i = 0; i < 8; i++) {
1596 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1597 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1598 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1599 }
c7c9c56c 1600 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
f563db4b 1601 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1602 apic->highest_isr_cache = -1;
b33ac88b 1603 update_divide_count(apic);
d3c7b77d 1604 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1605 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1606 kvm_lapic_set_base(vcpu,
1607 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1608 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1609 apic_update_ppr(apic);
1610
e1035715 1611 vcpu->arch.apic_arb_prio = 0;
41383771 1612 vcpu->arch.apic_attention = 0;
e1035715 1613
98eff52a 1614 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1615 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1616 vcpu, kvm_apic_id(apic),
ad312c7c 1617 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1618}
1619
97222cc8
ED		 1620/*
1621 *----------------------------------------------------------------------
1622 * timer interface
1623 *----------------------------------------------------------------------
1624 */
1b9778da 1625
2a6eac96 1626static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1627{
d3c7b77d 1628 return apic_lvtt_period(apic);
97222cc8
ED		 1629}
1630
3d80840d
MT		 1631int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1632{
54e9818f 1633 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1634
c48f1496 1635 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1636 apic_lvt_enabled(apic, APIC_LVTT))
1637 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1638
1639 return 0;
1640}
1641
89342082 1642int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1643{
c48f1496 1644 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1645 int vector, mode, trig_mode;
23930f95 1646
c48f1496 1647 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1648 vector = reg & APIC_VECTOR_MASK;
1649 mode = reg & APIC_MODE_MASK;
1650 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1651 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1652 NULL);
23930f95
JK		 1653 }
1654 return 0;
1655}
1b9778da 1656
8fdb2351 1657void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1658{
8fdb2351
JK		 1659 struct kvm_lapic *apic = vcpu->arch.apic;
1660
1661 if (apic)
1662 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1663}
1664
d76685c4
GH		 1665static const struct kvm_io_device_ops apic_mmio_ops = {
1666 .read = apic_mmio_read,
1667 .write = apic_mmio_write,
d76685c4
GH		 1668};
1669
e9d90d47
AK		 1670static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1671{
1672 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1673 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1674
5d87db71 1675 apic_timer_expired(apic);
e9d90d47 1676
2a6eac96 1677 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1678 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1679 return HRTIMER_RESTART;
1680 } else
1681 return HRTIMER_NORESTART;
1682}
1683
97222cc8
ED		 1684int kvm_create_lapic(struct kvm_vcpu *vcpu)
1685{
1686 struct kvm_lapic *apic;
1687
1688 ASSERT(vcpu != NULL);
1689 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1690
1691 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1692 if (!apic)
1693 goto nomem;
1694
ad312c7c 1695 vcpu->arch.apic = apic;
97222cc8 1696
afc20184
TY		 1697 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1698 if (!apic->regs) {
97222cc8
ED		 1699 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1700 vcpu->vcpu_id);
d589444e 1701 goto nomem_free_apic;
97222cc8 1702 }
97222cc8
ED		 1703 apic->vcpu = vcpu;
1704
d3c7b77d
MT		 1705 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1706 HRTIMER_MODE_ABS);
e9d90d47 1707 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1708
c5cc421b
GN		 1709 /*
1710 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1711 * thinking that APIC satet has changed.
1712 */
1713 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1714 kvm_lapic_set_base(vcpu,
1715 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1716
f8c1ea10 1717 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
c5ec1534 1718 kvm_lapic_reset(vcpu);
d76685c4 1719 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1720
1721 return 0;
d589444e
RR		 1722nomem_free_apic:
1723 kfree(apic);
97222cc8 1724nomem:
97222cc8
ED		 1725 return -ENOMEM;
1726}
97222cc8
ED		 1727
1728int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1729{
ad312c7c 1730 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1731 int highest_irr;
1732
c48f1496 1733 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1734 return -1;
1735
6e5d865c 1736 apic_update_ppr(apic);
97222cc8
ED		 1737 highest_irr = apic_find_highest_irr(apic);
1738 if ((highest_irr == -1) ||
c48f1496 1739 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1740 return -1;
1741 return highest_irr;
1742}
1743
40487c68
QH		 1744int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1745{
c48f1496 1746 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1747 int r = 0;
1748
c48f1496 1749 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1750 r = 1;
1751 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1752 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1753 r = 1;
40487c68
QH		 1754 return r;
1755}
1756
1b9778da
ED		 1757void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1758{
ad312c7c 1759 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1760
c48f1496 1761 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1762 return;
1763
1764 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1765 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1766 if (apic_lvtt_tscdeadline(apic))
1767 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1768 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1769 }
1770}
1771
97222cc8
ED		 1772int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1773{
1774 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1775 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1776
1777 if (vector == -1)
1778 return -1;
1779
56cc2406
WL		 1780 /*
1781 * We get here even with APIC virtualization enabled, if doing
1782 * nested virtualization and L1 runs with the "acknowledge interrupt
1783 * on exit" mode. Then we cannot inject the interrupt via RVI,
1784 * because the process would deliver it through the IDT.
1785 */
1786
8680b94b 1787 apic_set_isr(vector, apic);
97222cc8
ED		 1788 apic_update_ppr(apic);
1789 apic_clear_irr(vector, apic);
1790 return vector;
1791}
96ad2cc6 1792
64eb0620
GN		 1793void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1794 struct kvm_lapic_state *s)
96ad2cc6 1795{
ad312c7c 1796 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1797
5dbc8f3f 1798 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1799 /* set SPIV separately to get count of SW disabled APICs right */
1800 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1801 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1802 /* call kvm_apic_set_id() to put apic into apic_map */
1803 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1804 kvm_apic_set_version(vcpu);
1805
96ad2cc6 1806 apic_update_ppr(apic);
d3c7b77d 1807 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1808 update_divide_count(apic);
1809 start_apic_timer(apic);
6e24a6ef 1810 apic->irr_pending = true;
f563db4b 1811 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1812 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1813 apic->highest_isr_cache = -1;
4114c27d
WW		 1814 if (kvm_x86_ops->hwapic_irr_update)
1815 kvm_x86_ops->hwapic_irr_update(vcpu,
1816 apic_find_highest_irr(apic));
b4eef9b3
TC		 1817 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1818 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1819 apic_find_highest_isr(apic));
3842d135 1820 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1821 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1822}
a3d7f85f 1823
2f52d58c 1824void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1825{
a3d7f85f
ED		 1826 struct hrtimer *timer;
1827
c48f1496 1828 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1829 return;
1830
54e9818f 1831 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1832 if (hrtimer_cancel(timer))
beb20d52 1833 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1834}
b93463aa 1835
ae7a2a3f
MT		 1836/*
1837 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1838 *
1839 * Detect whether guest triggered PV EOI since the
1840 * last entry. If yes, set EOI on guests's behalf.
1841 * Clear PV EOI in guest memory in any case.
1842 */
1843static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1844 struct kvm_lapic *apic)
1845{
1846 bool pending;
1847 int vector;
1848 /*
1849 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1850 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1851 *
1852 * KVM_APIC_PV_EOI_PENDING is unset:
1853 * -> host disabled PV EOI.
1854 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1855 * -> host enabled PV EOI, guest did not execute EOI yet.
1856 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1857 * -> host enabled PV EOI, guest executed EOI.
1858 */
1859 BUG_ON(!pv_eoi_enabled(vcpu));
1860 pending = pv_eoi_get_pending(vcpu);
1861 /*
1862 * Clear pending bit in any case: it will be set again on vmentry.
1863 * While this might not be ideal from performance point of view,
1864 * this makes sure pv eoi is only enabled when we know it's safe.
1865 */
1866 pv_eoi_clr_pending(vcpu);
1867 if (pending)
1868 return;
1869 vector = apic_set_eoi(apic);
1870 trace_kvm_pv_eoi(apic, vector);
1871}
1872
b93463aa
AK		 1873void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1874{
1875 u32 data;
b93463aa 1876
ae7a2a3f
MT		 1877 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1878 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1879
41383771 1880 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1881 return;
1882
fda4e2e8
AH		 1883 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1884 sizeof(u32));
b93463aa
AK		 1885
1886 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1887}
1888
ae7a2a3f
MT		 1889/*
1890 * apic_sync_pv_eoi_to_guest - called before vmentry
1891 *
1892 * Detect whether it's safe to enable PV EOI and
1893 * if yes do so.
1894 */
1895static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1896 struct kvm_lapic *apic)
1897{
1898 if (!pv_eoi_enabled(vcpu) ||
1899 /* IRR set or many bits in ISR: could be nested. */
1900 apic->irr_pending ||
1901 /* Cache not set: could be safe but we don't bother. */
1902 apic->highest_isr_cache == -1 ||
1903 /* Need EOI to update ioapic. */
1904 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1905 /*
1906 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1907 * so we need not do anything here.
1908 */
1909 return;
1910 }
1911
1912 pv_eoi_set_pending(apic->vcpu);
1913}
1914
b93463aa
AK		 1915void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1916{
1917 u32 data, tpr;
1918 int max_irr, max_isr;
ae7a2a3f 1919 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1920
ae7a2a3f
MT		 1921 apic_sync_pv_eoi_to_guest(vcpu, apic);
1922
41383771 1923 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1924 return;
1925
c48f1496 1926 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1927 max_irr = apic_find_highest_irr(apic);
1928 if (max_irr < 0)
1929 max_irr = 0;
1930 max_isr = apic_find_highest_isr(apic);
1931 if (max_isr < 0)
1932 max_isr = 0;
1933 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1934
fda4e2e8
AH		 1935 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1936 sizeof(u32));
b93463aa
AK		 1937}
1938
fda4e2e8 1939int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1940{
fda4e2e8
AH		 1941 if (vapic_addr) {
1942 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1943 &vcpu->arch.apic->vapic_cache,
1944 vapic_addr, sizeof(u32)))
1945 return -EINVAL;
41383771 1946 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1947 } else {
41383771 1948 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1949 }
1950
1951 vcpu->arch.apic->vapic_addr = vapic_addr;
1952 return 0;
b93463aa 1953}
0105d1a5
GN		 1954
1955int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1956{
1957 struct kvm_lapic *apic = vcpu->arch.apic;
1958 u32 reg = (msr - APIC_BASE_MSR) << 4;
1959
1960 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1961 return 1;
1962
c69d3d9b
NA		 1963 if (reg == APIC_ICR2)
1964 return 1;
1965
0105d1a5 1966 /* if this is ICR write vector before command */
decdc283 1967 if (reg == APIC_ICR)
0105d1a5
GN		 1968 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1969 return apic_reg_write(apic, reg, (u32)data);
1970}
1971
1972int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1973{
1974 struct kvm_lapic *apic = vcpu->arch.apic;
1975 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1976
1977 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1978 return 1;
1979
c69d3d9b
NA		 1980 if (reg == APIC_DFR || reg == APIC_ICR2) {
1981 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1982 reg);
1983 return 1;
1984 }
1985
0105d1a5
GN		 1986 if (apic_reg_read(apic, reg, 4, &low))
1987 return 1;
decdc283 1988 if (reg == APIC_ICR)
0105d1a5
GN		 1989 apic_reg_read(apic, APIC_ICR2, 4, &high);
1990
1991 *data = (((u64)high) << 32) | low;
1992
1993 return 0;
1994}
10388a07
GN		 1995
1996int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1997{
1998 struct kvm_lapic *apic = vcpu->arch.apic;
1999
c48f1496 2000 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2001 return 1;
2002
2003 /* if this is ICR write vector before command */
2004 if (reg == APIC_ICR)
2005 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2006 return apic_reg_write(apic, reg, (u32)data);
2007}
2008
2009int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2010{
2011 struct kvm_lapic *apic = vcpu->arch.apic;
2012 u32 low, high = 0;
2013
c48f1496 2014 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2015 return 1;
2016
2017 if (apic_reg_read(apic, reg, 4, &low))
2018 return 1;
2019 if (reg == APIC_ICR)
2020 apic_reg_read(apic, APIC_ICR2, 4, &high);
2021
2022 *data = (((u64)high) << 32) | low;
2023
2024 return 0;
2025}
ae7a2a3f
MT		 2026
2027int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2028{
2029 u64 addr = data & ~KVM_MSR_ENABLED;
2030 if (!IS_ALIGNED(addr, 4))
2031 return 1;
2032
2033 vcpu->arch.pv_eoi.msr_val = data;
2034 if (!pv_eoi_enabled(vcpu))
2035 return 0;
2036 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2037 addr, sizeof(u8));
ae7a2a3f 2038}
c5cc421b 2039
66450a21
JK		 2040void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2041{
2042 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2043 u8 sipi_vector;
299018f4 2044 unsigned long pe;
66450a21 2045
299018f4 2046 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2047 return;
2048
299018f4
GN		 2049 pe = xchg(&apic->pending_events, 0);
2050
2051 if (test_bit(KVM_APIC_INIT, &pe)) {
66450a21
JK		 2052 kvm_lapic_reset(vcpu);
2053 kvm_vcpu_reset(vcpu);
2054 if (kvm_vcpu_is_bsp(apic->vcpu))
2055 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2056 else
2057 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2058 }
299018f4 2059 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2060 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2061 /* evaluate pending_events before reading the vector */
2062 smp_rmb();
2063 sipi_vector = apic->sipi_vector;
98eff52a 2064 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2065 vcpu->vcpu_id, sipi_vector);
2066 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2067 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2068 }
2069}
2070
c5cc421b
GN		 2071void kvm_lapic_init(void)
2072{
2073 /* do not patch jump label more than once per second */
2074 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2075 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2076}
ubuntu-bionic-kernel mirror