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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
57 | #define APIC_BUS_CYCLE_NS 1 | |
58 | ||
59 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
60 | #define apic_debug(fmt, arg...) | |
61 | ||
97222cc8 | 62 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 63 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
64 | #define LAPIC_MMIO_LENGTH (1 << 12) |
65 | /* followed define is not in apicdef.h */ | |
66 | #define APIC_SHORT_MASK 0xc0000 | |
67 | #define APIC_DEST_NOSHORT 0x0 | |
68 | #define APIC_DEST_MASK 0x800 | |
69 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 70 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 71 | |
394457a9 NA |
72 | #define APIC_BROADCAST 0xFF |
73 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
74 | ||
a0c9a822 MT |
75 | static inline int apic_test_vector(int vec, void *bitmap) |
76 | { | |
77 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
78 | } | |
79 | ||
10606919 YZ |
80 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
81 | { | |
82 | struct kvm_lapic *apic = vcpu->arch.apic; | |
83 | ||
84 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
85 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
86 | } | |
87 | ||
97222cc8 ED |
88 | static inline void apic_clear_vector(int vec, void *bitmap) |
89 | { | |
90 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
91 | } | |
92 | ||
8680b94b MT |
93 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
94 | { | |
95 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
96 | } | |
97 | ||
98 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
99 | { | |
100 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
101 | } | |
102 | ||
c5cc421b | 103 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
104 | struct static_key_deferred apic_sw_disabled __read_mostly; |
105 | ||
97222cc8 ED |
106 | static inline int apic_enabled(struct kvm_lapic *apic) |
107 | { | |
c48f1496 | 108 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
109 | } |
110 | ||
97222cc8 ED |
111 | #define LVT_MASK \ |
112 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
113 | ||
114 | #define LINT_MASK \ | |
115 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
116 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
117 | ||
e45115b6 RK |
118 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
119 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
120 | switch (map->mode) { | |
121 | case KVM_APIC_MODE_X2APIC: { | |
122 | u32 offset = (dest_id >> 16) * 16; | |
0ca52e7b | 123 | u32 max_apic_id = map->max_apic_id; |
e45115b6 RK |
124 | |
125 | if (offset <= max_apic_id) { | |
126 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
127 | ||
128 | *cluster = &map->phys_map[offset]; | |
129 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
130 | } else { | |
131 | *mask = 0; | |
132 | } | |
3b5a5ffa | 133 | |
e45115b6 RK |
134 | return true; |
135 | } | |
136 | case KVM_APIC_MODE_XAPIC_FLAT: | |
137 | *cluster = map->xapic_flat_map; | |
138 | *mask = dest_id & 0xff; | |
139 | return true; | |
140 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
141 | *cluster = map->xapic_cluster_map[dest_id >> 4]; | |
142 | *mask = dest_id & 0xf; | |
143 | return true; | |
144 | default: | |
145 | /* Not optimized. */ | |
146 | return false; | |
147 | } | |
3b5a5ffa RK |
148 | } |
149 | ||
1e08ec4a GN |
150 | static void recalculate_apic_map(struct kvm *kvm) |
151 | { | |
152 | struct kvm_apic_map *new, *old = NULL; | |
153 | struct kvm_vcpu *vcpu; | |
154 | int i; | |
0ca52e7b | 155 | u32 max_id = 255; |
1e08ec4a GN |
156 | |
157 | mutex_lock(&kvm->arch.apic_map_lock); | |
158 | ||
0ca52e7b RK |
159 | kvm_for_each_vcpu(i, vcpu, kvm) |
160 | if (kvm_apic_present(vcpu)) | |
161 | max_id = max(max_id, kvm_apic_id(vcpu->arch.apic)); | |
162 | ||
163 | new = kzalloc(sizeof(struct kvm_apic_map) + | |
164 | sizeof(struct kvm_lapic *) * (max_id + 1), GFP_KERNEL); | |
165 | ||
1e08ec4a GN |
166 | if (!new) |
167 | goto out; | |
168 | ||
0ca52e7b RK |
169 | new->max_apic_id = max_id; |
170 | ||
173beedc NA |
171 | kvm_for_each_vcpu(i, vcpu, kvm) { |
172 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
173 | struct kvm_lapic **cluster; |
174 | u16 mask; | |
25995e5b | 175 | u32 ldr, aid; |
1e08ec4a | 176 | |
df04d1d1 RK |
177 | if (!kvm_apic_present(vcpu)) |
178 | continue; | |
179 | ||
25995e5b | 180 | aid = kvm_apic_id(apic); |
dfb95954 | 181 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
1e08ec4a | 182 | |
0ca52e7b | 183 | if (aid <= new->max_apic_id) |
25995e5b | 184 | new->phys_map[aid] = apic; |
3548a259 | 185 | |
3b5a5ffa RK |
186 | if (apic_x2apic_mode(apic)) { |
187 | new->mode |= KVM_APIC_MODE_X2APIC; | |
188 | } else if (ldr) { | |
189 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 190 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
191 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
192 | else | |
193 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
194 | } | |
195 | ||
e45115b6 | 196 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
197 | continue; |
198 | ||
e45115b6 RK |
199 | if (mask) |
200 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
201 | } |
202 | out: | |
203 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
204 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
205 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
206 | mutex_unlock(&kvm->arch.apic_map_lock); | |
207 | ||
208 | if (old) | |
209 | kfree_rcu(old, rcu); | |
c7c9c56c | 210 | |
b053b2ae | 211 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
212 | } |
213 | ||
1e1b6c26 NA |
214 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
215 | { | |
e462755c | 216 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 217 | |
1e6e2755 | 218 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
219 | |
220 | if (enabled != apic->sw_enabled) { | |
221 | apic->sw_enabled = enabled; | |
222 | if (enabled) { | |
1e1b6c26 NA |
223 | static_key_slow_dec_deferred(&apic_sw_disabled); |
224 | recalculate_apic_map(apic->vcpu->kvm); | |
225 | } else | |
226 | static_key_slow_inc(&apic_sw_disabled.key); | |
227 | } | |
228 | } | |
229 | ||
1e08ec4a GN |
230 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
231 | { | |
1e6e2755 | 232 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
233 | recalculate_apic_map(apic->vcpu->kvm); |
234 | } | |
235 | ||
236 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
237 | { | |
1e6e2755 | 238 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
239 | recalculate_apic_map(apic->vcpu->kvm); |
240 | } | |
241 | ||
257b9a5f RK |
242 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id) |
243 | { | |
244 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
245 | ||
1e6e2755 SS |
246 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
247 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); | |
257b9a5f RK |
248 | recalculate_apic_map(apic->vcpu->kvm); |
249 | } | |
250 | ||
97222cc8 ED |
251 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
252 | { | |
dfb95954 | 253 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
254 | } |
255 | ||
256 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
257 | { | |
dfb95954 | 258 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
259 | } |
260 | ||
a3e06bbe LJ |
261 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
262 | { | |
f30ebc31 | 263 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
264 | } |
265 | ||
97222cc8 ED |
266 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
267 | { | |
f30ebc31 | 268 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
269 | } |
270 | ||
271 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
272 | { | |
f30ebc31 | 273 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
274 | } |
275 | ||
cc6e462c JK |
276 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
277 | { | |
278 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
279 | } | |
280 | ||
fc61b800 GN |
281 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
282 | { | |
283 | struct kvm_lapic *apic = vcpu->arch.apic; | |
284 | struct kvm_cpuid_entry2 *feat; | |
285 | u32 v = APIC_VERSION; | |
286 | ||
bce87cce | 287 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
288 | return; |
289 | ||
290 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
291 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
292 | v |= APIC_LVR_DIRECTED_EOI; | |
1e6e2755 | 293 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
294 | } |
295 | ||
1e6e2755 | 296 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 297 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
298 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
299 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
300 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
301 | LVT_MASK /* LVTERR */ | |
302 | }; | |
303 | ||
304 | static int find_highest_vector(void *bitmap) | |
305 | { | |
ecba9a52 TY |
306 | int vec; |
307 | u32 *reg; | |
97222cc8 | 308 | |
ecba9a52 TY |
309 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
310 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
311 | reg = bitmap + REG_POS(vec); | |
312 | if (*reg) | |
313 | return fls(*reg) - 1 + vec; | |
314 | } | |
97222cc8 | 315 | |
ecba9a52 | 316 | return -1; |
97222cc8 ED |
317 | } |
318 | ||
8680b94b MT |
319 | static u8 count_vectors(void *bitmap) |
320 | { | |
ecba9a52 TY |
321 | int vec; |
322 | u32 *reg; | |
8680b94b | 323 | u8 count = 0; |
ecba9a52 TY |
324 | |
325 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
326 | reg = bitmap + REG_POS(vec); | |
327 | count += hweight32(*reg); | |
328 | } | |
329 | ||
8680b94b MT |
330 | return count; |
331 | } | |
332 | ||
705699a1 | 333 | void __kvm_apic_update_irr(u32 *pir, void *regs) |
a20ed54d YZ |
334 | { |
335 | u32 i, pir_val; | |
a20ed54d YZ |
336 | |
337 | for (i = 0; i <= 7; i++) { | |
338 | pir_val = xchg(&pir[i], 0); | |
339 | if (pir_val) | |
705699a1 | 340 | *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val; |
a20ed54d YZ |
341 | } |
342 | } | |
705699a1 WV |
343 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
344 | ||
345 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) | |
346 | { | |
347 | struct kvm_lapic *apic = vcpu->arch.apic; | |
348 | ||
349 | __kvm_apic_update_irr(pir, apic->regs); | |
c77f3fab RK |
350 | |
351 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
705699a1 | 352 | } |
a20ed54d YZ |
353 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
354 | ||
33e4c686 | 355 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 356 | { |
33e4c686 | 357 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
358 | } |
359 | ||
360 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
361 | { | |
362 | int result; | |
363 | ||
c7c9c56c YZ |
364 | /* |
365 | * Note that irr_pending is just a hint. It will be always | |
366 | * true with virtual interrupt delivery enabled. | |
367 | */ | |
33e4c686 GN |
368 | if (!apic->irr_pending) |
369 | return -1; | |
370 | ||
d62caabb AS |
371 | if (apic->vcpu->arch.apicv_active) |
372 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); | |
33e4c686 | 373 | result = apic_search_irr(apic); |
97222cc8 ED |
374 | ASSERT(result == -1 || result >= 16); |
375 | ||
376 | return result; | |
377 | } | |
378 | ||
33e4c686 GN |
379 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
380 | { | |
56cc2406 WL |
381 | struct kvm_vcpu *vcpu; |
382 | ||
383 | vcpu = apic->vcpu; | |
384 | ||
d62caabb | 385 | if (unlikely(vcpu->arch.apicv_active)) { |
56cc2406 | 386 | /* try to update RVI */ |
f210f757 | 387 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 388 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
389 | } else { |
390 | apic->irr_pending = false; | |
391 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
392 | if (apic_search_irr(apic) != -1) | |
393 | apic->irr_pending = true; | |
56cc2406 | 394 | } |
33e4c686 GN |
395 | } |
396 | ||
8680b94b MT |
397 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
398 | { | |
56cc2406 WL |
399 | struct kvm_vcpu *vcpu; |
400 | ||
401 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
402 | return; | |
403 | ||
404 | vcpu = apic->vcpu; | |
fc57ac2c | 405 | |
8680b94b | 406 | /* |
56cc2406 WL |
407 | * With APIC virtualization enabled, all caching is disabled |
408 | * because the processor can modify ISR under the hood. Instead | |
409 | * just set SVI. | |
8680b94b | 410 | */ |
d62caabb | 411 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 412 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
413 | else { |
414 | ++apic->isr_count; | |
415 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
416 | /* | |
417 | * ISR (in service register) bit is set when injecting an interrupt. | |
418 | * The highest vector is injected. Thus the latest bit set matches | |
419 | * the highest bit in ISR. | |
420 | */ | |
421 | apic->highest_isr_cache = vec; | |
422 | } | |
8680b94b MT |
423 | } |
424 | ||
fc57ac2c PB |
425 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
426 | { | |
427 | int result; | |
428 | ||
429 | /* | |
430 | * Note that isr_count is always 1, and highest_isr_cache | |
431 | * is always -1, with APIC virtualization enabled. | |
432 | */ | |
433 | if (!apic->isr_count) | |
434 | return -1; | |
435 | if (likely(apic->highest_isr_cache != -1)) | |
436 | return apic->highest_isr_cache; | |
437 | ||
438 | result = find_highest_vector(apic->regs + APIC_ISR); | |
439 | ASSERT(result == -1 || result >= 16); | |
440 | ||
441 | return result; | |
442 | } | |
443 | ||
8680b94b MT |
444 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
445 | { | |
fc57ac2c PB |
446 | struct kvm_vcpu *vcpu; |
447 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
448 | return; | |
449 | ||
450 | vcpu = apic->vcpu; | |
451 | ||
452 | /* | |
453 | * We do get here for APIC virtualization enabled if the guest | |
454 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
455 | * to trigger a new interrupt delivery by writing the SVI field; | |
456 | * on the other hand isr_count and highest_isr_cache are unused | |
457 | * and must be left alone. | |
458 | */ | |
d62caabb | 459 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 460 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
461 | apic_find_highest_isr(apic)); |
462 | else { | |
8680b94b | 463 | --apic->isr_count; |
fc57ac2c PB |
464 | BUG_ON(apic->isr_count < 0); |
465 | apic->highest_isr_cache = -1; | |
466 | } | |
8680b94b MT |
467 | } |
468 | ||
6e5d865c YS |
469 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
470 | { | |
33e4c686 GN |
471 | /* This may race with setting of irr in __apic_accept_irq() and |
472 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
473 | * will cause vmexit immediately and the value will be recalculated | |
474 | * on the next vmentry. | |
475 | */ | |
f8543d6a | 476 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 477 | } |
6e5d865c | 478 | |
6da7e3f6 | 479 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 480 | int vector, int level, int trig_mode, |
9e4aabe2 | 481 | struct dest_map *dest_map); |
6da7e3f6 | 482 | |
b4f2225c | 483 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 484 | struct dest_map *dest_map) |
97222cc8 | 485 | { |
ad312c7c | 486 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 487 | |
58c2dde1 | 488 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 489 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
490 | } |
491 | ||
ae7a2a3f MT |
492 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
493 | { | |
494 | ||
495 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
496 | sizeof(val)); | |
497 | } | |
498 | ||
499 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
500 | { | |
501 | ||
502 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
503 | sizeof(*val)); | |
504 | } | |
505 | ||
506 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
507 | { | |
508 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
509 | } | |
510 | ||
511 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
512 | { | |
513 | u8 val; | |
514 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
515 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 516 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
517 | return val & 0x1; |
518 | } | |
519 | ||
520 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
521 | { | |
522 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
523 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 524 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
525 | return; |
526 | } | |
527 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
528 | } | |
529 | ||
530 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
531 | { | |
532 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
533 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 534 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
535 | return; |
536 | } | |
537 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
538 | } | |
539 | ||
97222cc8 ED |
540 | static void apic_update_ppr(struct kvm_lapic *apic) |
541 | { | |
3842d135 | 542 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
543 | int isr; |
544 | ||
dfb95954 SS |
545 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
546 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
547 | isr = apic_find_highest_isr(apic); |
548 | isrv = (isr != -1) ? isr : 0; | |
549 | ||
550 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
551 | ppr = tpr & 0xff; | |
552 | else | |
553 | ppr = isrv & 0xf0; | |
554 | ||
555 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
556 | apic, ppr, isr, isrv); | |
557 | ||
3842d135 | 558 | if (old_ppr != ppr) { |
1e6e2755 | 559 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
83bcacb1 AK |
560 | if (ppr < old_ppr) |
561 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 562 | } |
97222cc8 ED |
563 | } |
564 | ||
565 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
566 | { | |
1e6e2755 | 567 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
568 | apic_update_ppr(apic); |
569 | } | |
570 | ||
03d2249e | 571 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 572 | { |
03d2249e RK |
573 | if (apic_x2apic_mode(apic)) |
574 | return mda == X2APIC_BROADCAST; | |
575 | ||
576 | return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST; | |
394457a9 NA |
577 | } |
578 | ||
03d2249e | 579 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 580 | { |
03d2249e RK |
581 | if (kvm_apic_broadcast(apic, mda)) |
582 | return true; | |
583 | ||
584 | if (apic_x2apic_mode(apic)) | |
585 | return mda == kvm_apic_id(apic); | |
586 | ||
587 | return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic)); | |
97222cc8 ED |
588 | } |
589 | ||
52c233a4 | 590 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 591 | { |
0105d1a5 GN |
592 | u32 logical_id; |
593 | ||
394457a9 | 594 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 595 | return true; |
394457a9 | 596 | |
dfb95954 | 597 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 598 | |
9368b567 | 599 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
600 | return ((logical_id >> 16) == (mda >> 16)) |
601 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 602 | |
9368b567 | 603 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
03d2249e | 604 | mda = GET_APIC_DEST_FIELD(mda); |
97222cc8 | 605 | |
dfb95954 | 606 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 607 | case APIC_DFR_FLAT: |
9368b567 | 608 | return (logical_id & mda) != 0; |
97222cc8 | 609 | case APIC_DFR_CLUSTER: |
9368b567 RK |
610 | return ((logical_id >> 4) == (mda >> 4)) |
611 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 612 | default: |
7712de87 | 613 | apic_debug("Bad DFR vcpu %d: %08x\n", |
dfb95954 | 614 | apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); |
9368b567 | 615 | return false; |
97222cc8 | 616 | } |
97222cc8 ED |
617 | } |
618 | ||
03d2249e RK |
619 | /* KVM APIC implementation has two quirks |
620 | * - dest always begins at 0 while xAPIC MDA has offset 24, | |
621 | * - IOxAPIC messages have to be delivered (directly) to x2APIC. | |
622 | */ | |
623 | static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source, | |
624 | struct kvm_lapic *target) | |
625 | { | |
626 | bool ipi = source != NULL; | |
627 | bool x2apic_mda = apic_x2apic_mode(ipi ? source : target); | |
628 | ||
629 | if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda) | |
630 | return X2APIC_BROADCAST; | |
631 | ||
632 | return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id); | |
633 | } | |
634 | ||
52c233a4 | 635 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 636 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 637 | { |
ad312c7c | 638 | struct kvm_lapic *target = vcpu->arch.apic; |
03d2249e | 639 | u32 mda = kvm_apic_mda(dest, source, target); |
97222cc8 ED |
640 | |
641 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 642 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
643 | target, source, dest, dest_mode, short_hand); |
644 | ||
bd371396 | 645 | ASSERT(target); |
97222cc8 ED |
646 | switch (short_hand) { |
647 | case APIC_DEST_NOSHORT: | |
3697f302 | 648 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 649 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 650 | else |
03d2249e | 651 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 652 | case APIC_DEST_SELF: |
9368b567 | 653 | return target == source; |
97222cc8 | 654 | case APIC_DEST_ALLINC: |
9368b567 | 655 | return true; |
97222cc8 | 656 | case APIC_DEST_ALLBUT: |
9368b567 | 657 | return target != source; |
97222cc8 | 658 | default: |
7712de87 JK |
659 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
660 | short_hand); | |
9368b567 | 661 | return false; |
97222cc8 | 662 | } |
97222cc8 | 663 | } |
1e6e2755 | 664 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 665 | |
52004014 FW |
666 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
667 | const unsigned long *bitmap, u32 bitmap_size) | |
668 | { | |
669 | u32 mod; | |
670 | int i, idx = -1; | |
671 | ||
672 | mod = vector % dest_vcpus; | |
673 | ||
674 | for (i = 0; i <= mod; i++) { | |
675 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
676 | BUG_ON(idx == bitmap_size); | |
677 | } | |
678 | ||
679 | return idx; | |
680 | } | |
681 | ||
4efd805f RK |
682 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
683 | { | |
684 | if (!kvm->arch.disabled_lapic_found) { | |
685 | kvm->arch.disabled_lapic_found = true; | |
686 | printk(KERN_INFO | |
687 | "Disabled LAPIC found during irq injection\n"); | |
688 | } | |
689 | } | |
690 | ||
64aa47bf RK |
691 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
692 | * for valid destinations in *dst array. | |
693 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
694 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
695 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
696 | * zero and *dst undefined. | |
697 | */ | |
698 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
699 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
700 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
701 | unsigned long *bitmap) | |
702 | { | |
703 | int i, lowest; | |
704 | bool x2apic_ipi; | |
64aa47bf RK |
705 | |
706 | if (irq->shorthand == APIC_DEST_SELF && src) { | |
707 | *dst = src; | |
708 | *bitmap = 1; | |
709 | return true; | |
710 | } else if (irq->shorthand) | |
711 | return false; | |
1e08ec4a | 712 | |
64aa47bf RK |
713 | x2apic_ipi = src && *src && apic_x2apic_mode(*src); |
714 | if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST)) | |
715 | return false; | |
1e08ec4a | 716 | |
64aa47bf RK |
717 | if (!map) |
718 | return false; | |
719 | ||
720 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { | |
0ca52e7b | 721 | if (irq->dest_id > map->max_apic_id) { |
64aa47bf RK |
722 | *bitmap = 0; |
723 | } else { | |
724 | *dst = &map->phys_map[irq->dest_id]; | |
725 | *bitmap = 1; | |
726 | } | |
1e08ec4a GN |
727 | return true; |
728 | } | |
729 | ||
e45115b6 RK |
730 | *bitmap = 0; |
731 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
732 | (u16 *)bitmap)) | |
1e08ec4a GN |
733 | return false; |
734 | ||
64aa47bf RK |
735 | if (!kvm_lowest_prio_delivery(irq)) |
736 | return true; | |
3548a259 | 737 | |
64aa47bf RK |
738 | if (!kvm_vector_hashing_enabled()) { |
739 | lowest = -1; | |
740 | for_each_set_bit(i, bitmap, 16) { | |
741 | if (!(*dst)[i]) | |
742 | continue; | |
743 | if (lowest < 0) | |
744 | lowest = i; | |
745 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
746 | (*dst)[lowest]->vcpu) < 0) | |
747 | lowest = i; | |
3548a259 | 748 | } |
64aa47bf RK |
749 | } else { |
750 | if (!*bitmap) | |
751 | return true; | |
3548a259 | 752 | |
64aa47bf RK |
753 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
754 | bitmap, 16); | |
45c3094a | 755 | |
64aa47bf RK |
756 | if (!(*dst)[lowest]) { |
757 | kvm_apic_disabled_lapic_found(kvm); | |
758 | *bitmap = 0; | |
759 | return true; | |
760 | } | |
761 | } | |
1e08ec4a | 762 | |
64aa47bf | 763 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 764 | |
64aa47bf RK |
765 | return true; |
766 | } | |
52004014 | 767 | |
64aa47bf RK |
768 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
769 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
770 | { | |
771 | struct kvm_apic_map *map; | |
772 | unsigned long bitmap; | |
773 | struct kvm_lapic **dst = NULL; | |
774 | int i; | |
775 | bool ret; | |
52004014 | 776 | |
64aa47bf | 777 | *r = -1; |
52004014 | 778 | |
64aa47bf RK |
779 | if (irq->shorthand == APIC_DEST_SELF) { |
780 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
781 | return true; | |
782 | } | |
52004014 | 783 | |
64aa47bf RK |
784 | rcu_read_lock(); |
785 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 786 | |
64aa47bf RK |
787 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
788 | if (ret) | |
789 | for_each_set_bit(i, &bitmap, 16) { | |
790 | if (!dst[i]) | |
791 | continue; | |
792 | if (*r < 0) | |
793 | *r = 0; | |
794 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); | |
1e08ec4a | 795 | } |
1e08ec4a | 796 | |
1e08ec4a GN |
797 | rcu_read_unlock(); |
798 | return ret; | |
799 | } | |
800 | ||
6228a0da FW |
801 | /* |
802 | * This routine tries to handler interrupts in posted mode, here is how | |
803 | * it deals with different cases: | |
804 | * - For single-destination interrupts, handle it in posted mode | |
805 | * - Else if vector hashing is enabled and it is a lowest-priority | |
806 | * interrupt, handle it in posted mode and use the following mechanism | |
807 | * to find the destinaiton vCPU. | |
808 | * 1. For lowest-priority interrupts, store all the possible | |
809 | * destination vCPUs in an array. | |
810 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
811 | * the right destination vCPU in the array for the lowest-priority | |
812 | * interrupt. | |
813 | * - Otherwise, use remapped mode to inject the interrupt. | |
814 | */ | |
8feb4a04 FW |
815 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
816 | struct kvm_vcpu **dest_vcpu) | |
817 | { | |
818 | struct kvm_apic_map *map; | |
64aa47bf RK |
819 | unsigned long bitmap; |
820 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 821 | bool ret = false; |
8feb4a04 FW |
822 | |
823 | if (irq->shorthand) | |
824 | return false; | |
825 | ||
826 | rcu_read_lock(); | |
827 | map = rcu_dereference(kvm->arch.apic_map); | |
828 | ||
64aa47bf RK |
829 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
830 | hweight16(bitmap) == 1) { | |
831 | unsigned long i = find_first_bit(&bitmap, 16); | |
8feb4a04 | 832 | |
64aa47bf RK |
833 | if (dst[i]) { |
834 | *dest_vcpu = dst[i]->vcpu; | |
835 | ret = true; | |
6228a0da | 836 | } |
8feb4a04 FW |
837 | } |
838 | ||
8feb4a04 FW |
839 | rcu_read_unlock(); |
840 | return ret; | |
841 | } | |
842 | ||
97222cc8 ED |
843 | /* |
844 | * Add a pending IRQ into lapic. | |
845 | * Return 1 if successfully added and 0 if discarded. | |
846 | */ | |
847 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 848 | int vector, int level, int trig_mode, |
9e4aabe2 | 849 | struct dest_map *dest_map) |
97222cc8 | 850 | { |
6da7e3f6 | 851 | int result = 0; |
c5ec1534 | 852 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 853 | |
a183b638 PB |
854 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
855 | trig_mode, vector); | |
97222cc8 | 856 | switch (delivery_mode) { |
97222cc8 | 857 | case APIC_DM_LOWEST: |
e1035715 GN |
858 | vcpu->arch.apic_arb_prio++; |
859 | case APIC_DM_FIXED: | |
bdaffe1d PB |
860 | if (unlikely(trig_mode && !level)) |
861 | break; | |
862 | ||
97222cc8 ED |
863 | /* FIXME add logic for vcpu on reset */ |
864 | if (unlikely(!apic_enabled(apic))) | |
865 | break; | |
866 | ||
11f5cc05 JK |
867 | result = 1; |
868 | ||
9daa5007 | 869 | if (dest_map) { |
9e4aabe2 | 870 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
871 | dest_map->vectors[vcpu->vcpu_id] = vector; |
872 | } | |
a5d36f82 | 873 | |
bdaffe1d PB |
874 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
875 | if (trig_mode) | |
1e6e2755 | 876 | kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); |
bdaffe1d PB |
877 | else |
878 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
879 | } | |
880 | ||
d62caabb | 881 | if (vcpu->arch.apicv_active) |
5a71785d | 882 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 883 | else { |
1e6e2755 | 884 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
885 | |
886 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
887 | kvm_vcpu_kick(vcpu); | |
888 | } | |
97222cc8 ED |
889 | break; |
890 | ||
891 | case APIC_DM_REMRD: | |
24d2166b R |
892 | result = 1; |
893 | vcpu->arch.pv.pv_unhalted = 1; | |
894 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
895 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
896 | break; |
897 | ||
898 | case APIC_DM_SMI: | |
64d60670 PB |
899 | result = 1; |
900 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
901 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 902 | break; |
3419ffc8 | 903 | |
97222cc8 | 904 | case APIC_DM_NMI: |
6da7e3f6 | 905 | result = 1; |
3419ffc8 | 906 | kvm_inject_nmi(vcpu); |
26df99c6 | 907 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
908 | break; |
909 | ||
910 | case APIC_DM_INIT: | |
a52315e1 | 911 | if (!trig_mode || level) { |
6da7e3f6 | 912 | result = 1; |
66450a21 JK |
913 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
914 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
915 | /* make sure pending_events is visible before sending | |
916 | * the request */ | |
917 | smp_wmb(); | |
3842d135 | 918 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
919 | kvm_vcpu_kick(vcpu); |
920 | } else { | |
1b10bf31 JK |
921 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
922 | vcpu->vcpu_id); | |
c5ec1534 | 923 | } |
97222cc8 ED |
924 | break; |
925 | ||
926 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
927 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
928 | vcpu->vcpu_id, vector); | |
66450a21 JK |
929 | result = 1; |
930 | apic->sipi_vector = vector; | |
931 | /* make sure sipi_vector is visible for the receiver */ | |
932 | smp_wmb(); | |
933 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
934 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
935 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
936 | break; |
937 | ||
23930f95 JK |
938 | case APIC_DM_EXTINT: |
939 | /* | |
940 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
941 | * before NMI watchdog was enabled. Already handled by | |
942 | * kvm_apic_accept_pic_intr(). | |
943 | */ | |
944 | break; | |
945 | ||
97222cc8 ED |
946 | default: |
947 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
948 | delivery_mode); | |
949 | break; | |
950 | } | |
951 | return result; | |
952 | } | |
953 | ||
e1035715 | 954 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 955 | { |
e1035715 | 956 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
957 | } |
958 | ||
3bb345f3 PB |
959 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
960 | { | |
6308630b | 961 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
962 | } |
963 | ||
c7c9c56c YZ |
964 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
965 | { | |
7543a635 SR |
966 | int trigger_mode; |
967 | ||
968 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
969 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
970 | return; | |
3bb345f3 | 971 | |
7543a635 SR |
972 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
973 | if (irqchip_split(apic->vcpu->kvm)) { | |
974 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
975 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
976 | return; | |
c7c9c56c | 977 | } |
7543a635 SR |
978 | |
979 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
980 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
981 | else | |
982 | trigger_mode = IOAPIC_EDGE_TRIG; | |
983 | ||
984 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
985 | } |
986 | ||
ae7a2a3f | 987 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
988 | { |
989 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
990 | |
991 | trace_kvm_eoi(apic, vector); | |
992 | ||
97222cc8 ED |
993 | /* |
994 | * Not every write EOI will has corresponding ISR, | |
995 | * one example is when Kernel check timer on setup_IO_APIC | |
996 | */ | |
997 | if (vector == -1) | |
ae7a2a3f | 998 | return vector; |
97222cc8 | 999 | |
8680b94b | 1000 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1001 | apic_update_ppr(apic); |
1002 | ||
5c919412 AS |
1003 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
1004 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
1005 | ||
c7c9c56c | 1006 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1007 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1008 | return vector; |
97222cc8 ED |
1009 | } |
1010 | ||
c7c9c56c YZ |
1011 | /* |
1012 | * this interface assumes a trap-like exit, which has already finished | |
1013 | * desired side effect including vISR and vPPR update. | |
1014 | */ | |
1015 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1016 | { | |
1017 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1018 | ||
1019 | trace_kvm_eoi(apic, vector); | |
1020 | ||
1021 | kvm_ioapic_send_eoi(apic, vector); | |
1022 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1023 | } | |
1024 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1025 | ||
97222cc8 ED |
1026 | static void apic_send_ipi(struct kvm_lapic *apic) |
1027 | { | |
dfb95954 SS |
1028 | u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); |
1029 | u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1030 | struct kvm_lapic_irq irq; |
97222cc8 | 1031 | |
58c2dde1 GN |
1032 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1033 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1034 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1035 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1036 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1037 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1038 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1039 | if (apic_x2apic_mode(apic)) |
1040 | irq.dest_id = icr_high; | |
1041 | else | |
1042 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1043 | |
1000ff8d GN |
1044 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1045 | ||
97222cc8 ED |
1046 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1047 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1048 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1049 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1050 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1051 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1052 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1053 | |
b4f2225c | 1054 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1055 | } |
1056 | ||
1057 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1058 | { | |
b682b814 MT |
1059 | ktime_t remaining; |
1060 | s64 ns; | |
9da8f4e8 | 1061 | u32 tmcct; |
97222cc8 ED |
1062 | |
1063 | ASSERT(apic != NULL); | |
1064 | ||
9da8f4e8 | 1065 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1066 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1067 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1068 | return 0; |
1069 | ||
ace15464 | 1070 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
1071 | if (ktime_to_ns(remaining) < 0) |
1072 | remaining = ktime_set(0, 0); | |
1073 | ||
d3c7b77d MT |
1074 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1075 | tmcct = div64_u64(ns, | |
1076 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1077 | |
1078 | return tmcct; | |
1079 | } | |
1080 | ||
b209749f AK |
1081 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1082 | { | |
1083 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1084 | struct kvm_run *run = vcpu->run; | |
1085 | ||
a8eeb04a | 1086 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1087 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1088 | run->tpr_access.is_write = write; |
1089 | } | |
1090 | ||
1091 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1092 | { | |
1093 | if (apic->vcpu->arch.tpr_access_reporting) | |
1094 | __report_tpr_access(apic, write); | |
1095 | } | |
1096 | ||
97222cc8 ED |
1097 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1098 | { | |
1099 | u32 val = 0; | |
1100 | ||
1101 | if (offset >= LAPIC_MMIO_LENGTH) | |
1102 | return 0; | |
1103 | ||
1104 | switch (offset) { | |
0105d1a5 GN |
1105 | case APIC_ID: |
1106 | if (apic_x2apic_mode(apic)) | |
1107 | val = kvm_apic_id(apic); | |
1108 | else | |
1109 | val = kvm_apic_id(apic) << 24; | |
1110 | break; | |
97222cc8 | 1111 | case APIC_ARBPRI: |
7712de87 | 1112 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1113 | break; |
1114 | ||
1115 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1116 | if (apic_lvtt_tscdeadline(apic)) |
1117 | return 0; | |
1118 | ||
97222cc8 ED |
1119 | val = apic_get_tmcct(apic); |
1120 | break; | |
4a4541a4 AK |
1121 | case APIC_PROCPRI: |
1122 | apic_update_ppr(apic); | |
dfb95954 | 1123 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1124 | break; |
b209749f AK |
1125 | case APIC_TASKPRI: |
1126 | report_tpr_access(apic, false); | |
1127 | /* fall thru */ | |
97222cc8 | 1128 | default: |
dfb95954 | 1129 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1130 | break; |
1131 | } | |
1132 | ||
1133 | return val; | |
1134 | } | |
1135 | ||
d76685c4 GH |
1136 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1137 | { | |
1138 | return container_of(dev, struct kvm_lapic, dev); | |
1139 | } | |
1140 | ||
1e6e2755 | 1141 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1142 | void *data) |
97222cc8 | 1143 | { |
97222cc8 ED |
1144 | unsigned char alignment = offset & 0xf; |
1145 | u32 result; | |
d5b0b5b1 | 1146 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1147 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1148 | |
1149 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1150 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1151 | offset, len); | |
0105d1a5 | 1152 | return 1; |
97222cc8 | 1153 | } |
0105d1a5 GN |
1154 | |
1155 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1156 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1157 | offset); | |
0105d1a5 GN |
1158 | return 1; |
1159 | } | |
1160 | ||
97222cc8 ED |
1161 | result = __apic_read(apic, offset & ~0xf); |
1162 | ||
229456fc MT |
1163 | trace_kvm_apic_read(offset, result); |
1164 | ||
97222cc8 ED |
1165 | switch (len) { |
1166 | case 1: | |
1167 | case 2: | |
1168 | case 4: | |
1169 | memcpy(data, (char *)&result + alignment, len); | |
1170 | break; | |
1171 | default: | |
1172 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1173 | "should be 1,2, or 4 instead\n", len); | |
1174 | break; | |
1175 | } | |
bda9020e | 1176 | return 0; |
97222cc8 | 1177 | } |
1e6e2755 | 1178 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1179 | |
0105d1a5 GN |
1180 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1181 | { | |
c48f1496 | 1182 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1183 | addr >= apic->base_address && |
1184 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1185 | } | |
1186 | ||
e32edf4f | 1187 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1188 | gpa_t address, int len, void *data) |
1189 | { | |
1190 | struct kvm_lapic *apic = to_lapic(this); | |
1191 | u32 offset = address - apic->base_address; | |
1192 | ||
1193 | if (!apic_mmio_in_range(apic, address)) | |
1194 | return -EOPNOTSUPP; | |
1195 | ||
1e6e2755 | 1196 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1197 | |
1198 | return 0; | |
1199 | } | |
1200 | ||
97222cc8 ED |
1201 | static void update_divide_count(struct kvm_lapic *apic) |
1202 | { | |
1203 | u32 tmp1, tmp2, tdcr; | |
1204 | ||
dfb95954 | 1205 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1206 | tmp1 = tdcr & 0xf; |
1207 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1208 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1209 | |
1210 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1211 | apic->divide_count); |
97222cc8 ED |
1212 | } |
1213 | ||
b6ac0695 RK |
1214 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1215 | { | |
dfb95954 | 1216 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1217 | apic->lapic_timer.timer_mode_mask; |
1218 | ||
1219 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1220 | apic->lapic_timer.timer_mode = timer_mode; | |
1221 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1222 | } | |
1223 | } | |
1224 | ||
5d87db71 RK |
1225 | static void apic_timer_expired(struct kvm_lapic *apic) |
1226 | { | |
1227 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1228 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1229 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1230 | |
5d87db71 RK |
1231 | if (atomic_read(&apic->lapic_timer.pending)) |
1232 | return; | |
1233 | ||
1234 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1235 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1236 | |
8577370f MT |
1237 | if (swait_active(q)) |
1238 | swake_up(q); | |
d0659d94 MT |
1239 | |
1240 | if (apic_lvtt_tscdeadline(apic)) | |
1241 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * On APICv, this test will cause a busy wait | |
1246 | * during a higher-priority task. | |
1247 | */ | |
1248 | ||
1249 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1250 | { | |
1251 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1252 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1253 | |
1254 | if (kvm_apic_hw_enabled(apic)) { | |
1255 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1256 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1257 | |
d62caabb | 1258 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1259 | bitmap = apic->regs + APIC_IRR; |
1260 | ||
1261 | if (apic_test_vector(vec, bitmap)) | |
1262 | return true; | |
d0659d94 MT |
1263 | } |
1264 | return false; | |
1265 | } | |
1266 | ||
1267 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1268 | { | |
1269 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1270 | u64 guest_tsc, tsc_deadline; | |
1271 | ||
bce87cce | 1272 | if (!lapic_in_kernel(vcpu)) |
d0659d94 MT |
1273 | return; |
1274 | ||
1275 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1276 | return; | |
1277 | ||
1278 | if (!lapic_timer_int_injected(vcpu)) | |
1279 | return; | |
1280 | ||
1281 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1282 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1283 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1284 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1285 | |
1286 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1287 | if (guest_tsc < tsc_deadline) | |
1288 | __delay(tsc_deadline - guest_tsc); | |
5d87db71 RK |
1289 | } |
1290 | ||
53f9eedf YJ |
1291 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1292 | { | |
1293 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1294 | u64 ns = 0; | |
1295 | ktime_t expire; | |
1296 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1297 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1298 | unsigned long flags; | |
1299 | ktime_t now; | |
1300 | ||
1301 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1302 | return; | |
1303 | ||
1304 | local_irq_save(flags); | |
1305 | ||
1306 | now = apic->lapic_timer.timer.base->get_time(); | |
1307 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); | |
1308 | if (likely(tscdeadline > guest_tsc)) { | |
1309 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1310 | do_div(ns, this_tsc_khz); | |
1311 | expire = ktime_add_ns(now, ns); | |
1312 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1313 | hrtimer_start(&apic->lapic_timer.timer, | |
1314 | expire, HRTIMER_MODE_ABS_PINNED); | |
1315 | } else | |
1316 | apic_timer_expired(apic); | |
1317 | ||
1318 | local_irq_restore(flags); | |
1319 | } | |
1320 | ||
ce7a058a YJ |
1321 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1322 | { | |
1323 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; | |
1324 | } | |
1325 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1326 | ||
bd97ad0e WL |
1327 | static void cancel_hv_tscdeadline(struct kvm_lapic *apic) |
1328 | { | |
1329 | kvm_x86_ops->cancel_hv_timer(apic->vcpu); | |
1330 | apic->lapic_timer.hv_timer_in_use = false; | |
1331 | } | |
1332 | ||
ce7a058a YJ |
1333 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1334 | { | |
1335 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1336 | ||
1337 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); | |
1338 | WARN_ON(swait_active(&vcpu->wq)); | |
bd97ad0e | 1339 | cancel_hv_tscdeadline(apic); |
ce7a058a YJ |
1340 | apic_timer_expired(apic); |
1341 | } | |
1342 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1343 | ||
196f20ca WL |
1344 | static bool start_hv_tscdeadline(struct kvm_lapic *apic) |
1345 | { | |
1346 | u64 tscdeadline = apic->lapic_timer.tscdeadline; | |
1347 | ||
1348 | if (atomic_read(&apic->lapic_timer.pending) || | |
1349 | kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) { | |
1350 | if (apic->lapic_timer.hv_timer_in_use) | |
1351 | cancel_hv_tscdeadline(apic); | |
1352 | } else { | |
1353 | apic->lapic_timer.hv_timer_in_use = true; | |
1354 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1355 | ||
1356 | /* In case the sw timer triggered in the window */ | |
1357 | if (atomic_read(&apic->lapic_timer.pending)) | |
1358 | cancel_hv_tscdeadline(apic); | |
1359 | } | |
1360 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, | |
1361 | apic->lapic_timer.hv_timer_in_use); | |
1362 | return apic->lapic_timer.hv_timer_in_use; | |
1363 | } | |
1364 | ||
ce7a058a YJ |
1365 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1366 | { | |
1367 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1368 | ||
1369 | WARN_ON(apic->lapic_timer.hv_timer_in_use); | |
1370 | ||
196f20ca WL |
1371 | if (apic_lvtt_tscdeadline(apic)) |
1372 | start_hv_tscdeadline(apic); | |
ce7a058a YJ |
1373 | } |
1374 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1375 | ||
1376 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1377 | { | |
1378 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1379 | ||
1380 | /* Possibly the TSC deadline timer is not enabled yet */ | |
1381 | if (!apic->lapic_timer.hv_timer_in_use) | |
1382 | return; | |
1383 | ||
bd97ad0e | 1384 | cancel_hv_tscdeadline(apic); |
ce7a058a YJ |
1385 | |
1386 | if (atomic_read(&apic->lapic_timer.pending)) | |
1387 | return; | |
1388 | ||
1389 | start_sw_tscdeadline(apic); | |
1390 | } | |
1391 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
1392 | ||
97222cc8 ED |
1393 | static void start_apic_timer(struct kvm_lapic *apic) |
1394 | { | |
a3e06bbe | 1395 | ktime_t now; |
d0659d94 | 1396 | |
d3c7b77d | 1397 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1398 | |
a3e06bbe | 1399 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1400 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1401 | now = apic->lapic_timer.timer.base->get_time(); |
dfb95954 | 1402 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1403 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1404 | ||
1405 | if (!apic->lapic_timer.period) | |
1406 | return; | |
1407 | /* | |
1408 | * Do not allow the guest to program periodic timers with small | |
1409 | * interval, since the hrtimers are not throttled by the host | |
1410 | * scheduler. | |
1411 | */ | |
1412 | if (apic_lvtt_period(apic)) { | |
1413 | s64 min_period = min_timer_period_us * 1000LL; | |
1414 | ||
1415 | if (apic->lapic_timer.period < min_period) { | |
1416 | pr_info_ratelimited( | |
1417 | "kvm: vcpu %i: requested %lld ns " | |
1418 | "lapic timer period limited to %lld ns\n", | |
1419 | apic->vcpu->vcpu_id, | |
1420 | apic->lapic_timer.period, min_period); | |
1421 | apic->lapic_timer.period = min_period; | |
1422 | } | |
9bc5791d | 1423 | } |
0b975a3c | 1424 | |
a3e06bbe LJ |
1425 | hrtimer_start(&apic->lapic_timer.timer, |
1426 | ktime_add_ns(now, apic->lapic_timer.period), | |
61abdbe0 | 1427 | HRTIMER_MODE_ABS_PINNED); |
97222cc8 | 1428 | |
a3e06bbe | 1429 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1430 | PRIx64 ", " |
1431 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1432 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1433 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
dfb95954 | 1434 | kvm_lapic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1435 | apic->lapic_timer.period, |
97222cc8 | 1436 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1437 | apic->lapic_timer.period))); |
a3e06bbe | 1438 | } else if (apic_lvtt_tscdeadline(apic)) { |
196f20ca | 1439 | if (!(kvm_x86_ops->set_hv_timer && start_hv_tscdeadline(apic))) |
ce7a058a | 1440 | start_sw_tscdeadline(apic); |
a3e06bbe | 1441 | } |
97222cc8 ED |
1442 | } |
1443 | ||
cc6e462c JK |
1444 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1445 | { | |
59fd1323 | 1446 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1447 | |
59fd1323 RK |
1448 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1449 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1450 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1451 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1452 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1453 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1454 | } else |
1455 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1456 | } | |
cc6e462c JK |
1457 | } |
1458 | ||
1e6e2755 | 1459 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1460 | { |
0105d1a5 | 1461 | int ret = 0; |
97222cc8 | 1462 | |
0105d1a5 | 1463 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1464 | |
0105d1a5 | 1465 | switch (reg) { |
97222cc8 | 1466 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1467 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1468 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1469 | else |
1470 | ret = 1; | |
97222cc8 ED |
1471 | break; |
1472 | ||
1473 | case APIC_TASKPRI: | |
b209749f | 1474 | report_tpr_access(apic, true); |
97222cc8 ED |
1475 | apic_set_tpr(apic, val & 0xff); |
1476 | break; | |
1477 | ||
1478 | case APIC_EOI: | |
1479 | apic_set_eoi(apic); | |
1480 | break; | |
1481 | ||
1482 | case APIC_LDR: | |
0105d1a5 | 1483 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1484 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1485 | else |
1486 | ret = 1; | |
97222cc8 ED |
1487 | break; |
1488 | ||
1489 | case APIC_DFR: | |
1e08ec4a | 1490 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1491 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1492 | recalculate_apic_map(apic->vcpu->kvm); |
1493 | } else | |
0105d1a5 | 1494 | ret = 1; |
97222cc8 ED |
1495 | break; |
1496 | ||
fc61b800 GN |
1497 | case APIC_SPIV: { |
1498 | u32 mask = 0x3ff; | |
dfb95954 | 1499 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1500 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1501 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1502 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1503 | int i; | |
1504 | u32 lvt_val; | |
1505 | ||
1e6e2755 | 1506 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1507 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1508 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1509 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1510 | lvt_val | APIC_LVT_MASKED); |
1511 | } | |
b6ac0695 | 1512 | apic_update_lvtt(apic); |
d3c7b77d | 1513 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1514 | |
1515 | } | |
1516 | break; | |
fc61b800 | 1517 | } |
97222cc8 ED |
1518 | case APIC_ICR: |
1519 | /* No delay here, so we always clear the pending bit */ | |
1e6e2755 | 1520 | kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); |
97222cc8 ED |
1521 | apic_send_ipi(apic); |
1522 | break; | |
1523 | ||
1524 | case APIC_ICR2: | |
0105d1a5 GN |
1525 | if (!apic_x2apic_mode(apic)) |
1526 | val &= 0xff000000; | |
1e6e2755 | 1527 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1528 | break; |
1529 | ||
23930f95 | 1530 | case APIC_LVT0: |
cc6e462c | 1531 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1532 | case APIC_LVTTHMR: |
1533 | case APIC_LVTPC: | |
97222cc8 ED |
1534 | case APIC_LVT1: |
1535 | case APIC_LVTERR: | |
1536 | /* TODO: Check vector */ | |
c48f1496 | 1537 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1538 | val |= APIC_LVT_MASKED; |
1539 | ||
0105d1a5 | 1540 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1541 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1542 | |
1543 | break; | |
1544 | ||
b6ac0695 | 1545 | case APIC_LVTT: |
c48f1496 | 1546 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1547 | val |= APIC_LVT_MASKED; |
1548 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1549 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1550 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1551 | break; |
1552 | ||
97222cc8 | 1553 | case APIC_TMICT: |
a3e06bbe LJ |
1554 | if (apic_lvtt_tscdeadline(apic)) |
1555 | break; | |
1556 | ||
d3c7b77d | 1557 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1558 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1559 | start_apic_timer(apic); |
0105d1a5 | 1560 | break; |
97222cc8 ED |
1561 | |
1562 | case APIC_TDCR: | |
1563 | if (val & 4) | |
7712de87 | 1564 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
1e6e2755 | 1565 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 ED |
1566 | update_divide_count(apic); |
1567 | break; | |
1568 | ||
0105d1a5 GN |
1569 | case APIC_ESR: |
1570 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1571 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1572 | ret = 1; |
1573 | } | |
1574 | break; | |
1575 | ||
1576 | case APIC_SELF_IPI: | |
1577 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 1578 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
1579 | } else |
1580 | ret = 1; | |
1581 | break; | |
97222cc8 | 1582 | default: |
0105d1a5 | 1583 | ret = 1; |
97222cc8 ED |
1584 | break; |
1585 | } | |
0105d1a5 GN |
1586 | if (ret) |
1587 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1588 | return ret; | |
1589 | } | |
1e6e2755 | 1590 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 1591 | |
e32edf4f | 1592 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1593 | gpa_t address, int len, const void *data) |
1594 | { | |
1595 | struct kvm_lapic *apic = to_lapic(this); | |
1596 | unsigned int offset = address - apic->base_address; | |
1597 | u32 val; | |
1598 | ||
1599 | if (!apic_mmio_in_range(apic, address)) | |
1600 | return -EOPNOTSUPP; | |
1601 | ||
1602 | /* | |
1603 | * APIC register must be aligned on 128-bits boundary. | |
1604 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1605 | * Refer SDM 8.4.1 | |
1606 | */ | |
1607 | if (len != 4 || (offset & 0xf)) { | |
1608 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1609 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1610 | return 0; |
0105d1a5 GN |
1611 | } |
1612 | ||
1613 | val = *(u32*)data; | |
1614 | ||
1615 | /* too common printing */ | |
1616 | if (offset != APIC_EOI) | |
1617 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1618 | "0x%x\n", __func__, offset, len, val); | |
1619 | ||
1e6e2755 | 1620 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 1621 | |
bda9020e | 1622 | return 0; |
97222cc8 ED |
1623 | } |
1624 | ||
58fbbf26 KT |
1625 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1626 | { | |
1e6e2755 | 1627 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
1628 | } |
1629 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1630 | ||
83d4c286 YZ |
1631 | /* emulate APIC access in a trap manner */ |
1632 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1633 | { | |
1634 | u32 val = 0; | |
1635 | ||
1636 | /* hw has done the conditional check and inst decode */ | |
1637 | offset &= 0xff0; | |
1638 | ||
1e6e2755 | 1639 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
1640 | |
1641 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 1642 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
1643 | } |
1644 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1645 | ||
d589444e | 1646 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1647 | { |
f8c1ea10 GN |
1648 | struct kvm_lapic *apic = vcpu->arch.apic; |
1649 | ||
ad312c7c | 1650 | if (!vcpu->arch.apic) |
97222cc8 ED |
1651 | return; |
1652 | ||
f8c1ea10 | 1653 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1654 | |
c5cc421b GN |
1655 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1656 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1657 | ||
e462755c | 1658 | if (!apic->sw_enabled) |
f8c1ea10 | 1659 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1660 | |
f8c1ea10 GN |
1661 | if (apic->regs) |
1662 | free_page((unsigned long)apic->regs); | |
1663 | ||
1664 | kfree(apic); | |
97222cc8 ED |
1665 | } |
1666 | ||
1667 | /* | |
1668 | *---------------------------------------------------------------------- | |
1669 | * LAPIC interface | |
1670 | *---------------------------------------------------------------------- | |
1671 | */ | |
1672 | ||
a3e06bbe LJ |
1673 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1674 | { | |
1675 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1676 | |
bce87cce | 1677 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1678 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1679 | return 0; |
1680 | ||
1681 | return apic->lapic_timer.tscdeadline; | |
1682 | } | |
1683 | ||
1684 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1685 | { | |
1686 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1687 | |
bce87cce | 1688 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1689 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1690 | return; |
1691 | ||
1692 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1693 | apic->lapic_timer.tscdeadline = data; | |
1694 | start_apic_timer(apic); | |
1695 | } | |
1696 | ||
97222cc8 ED |
1697 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1698 | { | |
ad312c7c | 1699 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1700 | |
b93463aa | 1701 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 1702 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1703 | } |
1704 | ||
1705 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1706 | { | |
97222cc8 ED |
1707 | u64 tpr; |
1708 | ||
dfb95954 | 1709 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1710 | |
1711 | return (tpr & 0xf0) >> 4; | |
1712 | } | |
1713 | ||
1714 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1715 | { | |
8d14695f | 1716 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1717 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1718 | |
1719 | if (!apic) { | |
1720 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1721 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1722 | return; |
1723 | } | |
c5af89b6 | 1724 | |
e66d2ae7 JK |
1725 | vcpu->arch.apic_base = value; |
1726 | ||
c5cc421b | 1727 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1728 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1729 | if (value & MSR_IA32_APICBASE_ENABLE) |
1730 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1731 | else | |
1732 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1733 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1734 | } |
1735 | ||
8d14695f YZ |
1736 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1737 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1738 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1739 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1740 | } else | |
1741 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1742 | } |
8d14695f | 1743 | |
ad312c7c | 1744 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1745 | MSR_IA32_APICBASE_BASE; |
1746 | ||
db324fe6 NA |
1747 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1748 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1749 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1750 | ||
97222cc8 ED |
1751 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1752 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1753 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1754 | |
1755 | } | |
1756 | ||
d28bc9dd | 1757 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
1758 | { |
1759 | struct kvm_lapic *apic; | |
1760 | int i; | |
1761 | ||
b8688d51 | 1762 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1763 | |
1764 | ASSERT(vcpu); | |
ad312c7c | 1765 | apic = vcpu->arch.apic; |
97222cc8 ED |
1766 | ASSERT(apic != NULL); |
1767 | ||
1768 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1769 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1770 | |
d28bc9dd NA |
1771 | if (!init_event) |
1772 | kvm_apic_set_id(apic, vcpu->vcpu_id); | |
fc61b800 | 1773 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 1774 | |
1e6e2755 SS |
1775 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
1776 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 1777 | apic_update_lvtt(apic); |
0da029ed | 1778 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) |
1e6e2755 | 1779 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 1780 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 1781 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 1782 | |
1e6e2755 | 1783 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 1784 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 1785 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
1786 | if (!apic_x2apic_mode(apic)) |
1787 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
1788 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
1789 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
1790 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
1791 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
1792 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 1793 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
1794 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
1795 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1796 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 1797 | } |
d62caabb AS |
1798 | apic->irr_pending = vcpu->arch.apicv_active; |
1799 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 1800 | apic->highest_isr_cache = -1; |
b33ac88b | 1801 | update_divide_count(apic); |
d3c7b77d | 1802 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1803 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1804 | kvm_lapic_set_base(vcpu, |
1805 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1806 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1807 | apic_update_ppr(apic); |
1808 | ||
e1035715 | 1809 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1810 | vcpu->arch.apic_attention = 0; |
e1035715 | 1811 | |
98eff52a | 1812 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1813 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1814 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1815 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1816 | } |
1817 | ||
97222cc8 ED |
1818 | /* |
1819 | *---------------------------------------------------------------------- | |
1820 | * timer interface | |
1821 | *---------------------------------------------------------------------- | |
1822 | */ | |
1b9778da | 1823 | |
2a6eac96 | 1824 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1825 | { |
d3c7b77d | 1826 | return apic_lvtt_period(apic); |
97222cc8 ED |
1827 | } |
1828 | ||
3d80840d MT |
1829 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1830 | { | |
54e9818f | 1831 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1832 | |
1e3161b4 | 1833 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 1834 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
1835 | |
1836 | return 0; | |
1837 | } | |
1838 | ||
89342082 | 1839 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1840 | { |
dfb95954 | 1841 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 1842 | int vector, mode, trig_mode; |
23930f95 | 1843 | |
c48f1496 | 1844 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1845 | vector = reg & APIC_VECTOR_MASK; |
1846 | mode = reg & APIC_MODE_MASK; | |
1847 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1848 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1849 | NULL); | |
23930f95 JK |
1850 | } |
1851 | return 0; | |
1852 | } | |
1b9778da | 1853 | |
8fdb2351 | 1854 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1855 | { |
8fdb2351 JK |
1856 | struct kvm_lapic *apic = vcpu->arch.apic; |
1857 | ||
1858 | if (apic) | |
1859 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1860 | } |
1861 | ||
d76685c4 GH |
1862 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1863 | .read = apic_mmio_read, | |
1864 | .write = apic_mmio_write, | |
d76685c4 GH |
1865 | }; |
1866 | ||
e9d90d47 AK |
1867 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1868 | { | |
1869 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1870 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1871 | |
5d87db71 | 1872 | apic_timer_expired(apic); |
e9d90d47 | 1873 | |
2a6eac96 | 1874 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1875 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1876 | return HRTIMER_RESTART; | |
1877 | } else | |
1878 | return HRTIMER_NORESTART; | |
1879 | } | |
1880 | ||
97222cc8 ED |
1881 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1882 | { | |
1883 | struct kvm_lapic *apic; | |
1884 | ||
1885 | ASSERT(vcpu != NULL); | |
1886 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1887 | ||
1888 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1889 | if (!apic) | |
1890 | goto nomem; | |
1891 | ||
ad312c7c | 1892 | vcpu->arch.apic = apic; |
97222cc8 | 1893 | |
afc20184 TY |
1894 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1895 | if (!apic->regs) { | |
97222cc8 ED |
1896 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1897 | vcpu->vcpu_id); | |
d589444e | 1898 | goto nomem_free_apic; |
97222cc8 | 1899 | } |
97222cc8 ED |
1900 | apic->vcpu = vcpu; |
1901 | ||
d3c7b77d | 1902 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
61abdbe0 | 1903 | HRTIMER_MODE_ABS_PINNED); |
e9d90d47 | 1904 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1905 | |
c5cc421b GN |
1906 | /* |
1907 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1908 | * thinking that APIC satet has changed. | |
1909 | */ | |
1910 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1911 | kvm_lapic_set_base(vcpu, |
1912 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1913 | |
f8c1ea10 | 1914 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d28bc9dd | 1915 | kvm_lapic_reset(vcpu, false); |
d76685c4 | 1916 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1917 | |
1918 | return 0; | |
d589444e RR |
1919 | nomem_free_apic: |
1920 | kfree(apic); | |
97222cc8 | 1921 | nomem: |
97222cc8 ED |
1922 | return -ENOMEM; |
1923 | } | |
97222cc8 ED |
1924 | |
1925 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1926 | { | |
ad312c7c | 1927 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1928 | int highest_irr; |
1929 | ||
f8543d6a | 1930 | if (!apic_enabled(apic)) |
97222cc8 ED |
1931 | return -1; |
1932 | ||
6e5d865c | 1933 | apic_update_ppr(apic); |
97222cc8 ED |
1934 | highest_irr = apic_find_highest_irr(apic); |
1935 | if ((highest_irr == -1) || | |
dfb95954 | 1936 | ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1937 | return -1; |
1938 | return highest_irr; | |
1939 | } | |
1940 | ||
40487c68 QH |
1941 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1942 | { | |
dfb95954 | 1943 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1944 | int r = 0; |
1945 | ||
c48f1496 | 1946 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1947 | r = 1; |
1948 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1949 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1950 | r = 1; | |
40487c68 QH |
1951 | return r; |
1952 | } | |
1953 | ||
1b9778da ED |
1954 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1955 | { | |
ad312c7c | 1956 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1957 | |
54e9818f | 1958 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
f1ed0450 | 1959 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1960 | if (apic_lvtt_tscdeadline(apic)) |
1961 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1962 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1963 | } |
1964 | } | |
1965 | ||
97222cc8 ED |
1966 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1967 | { | |
1968 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1969 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1970 | |
1971 | if (vector == -1) | |
1972 | return -1; | |
1973 | ||
56cc2406 WL |
1974 | /* |
1975 | * We get here even with APIC virtualization enabled, if doing | |
1976 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1977 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1978 | * because the process would deliver it through the IDT. | |
1979 | */ | |
1980 | ||
8680b94b | 1981 | apic_set_isr(vector, apic); |
97222cc8 ED |
1982 | apic_update_ppr(apic); |
1983 | apic_clear_irr(vector, apic); | |
5c919412 AS |
1984 | |
1985 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { | |
1986 | apic_clear_isr(vector, apic); | |
1987 | apic_update_ppr(apic); | |
1988 | } | |
1989 | ||
97222cc8 ED |
1990 | return vector; |
1991 | } | |
96ad2cc6 | 1992 | |
64eb0620 GN |
1993 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1994 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1995 | { |
ad312c7c | 1996 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1997 | |
5dbc8f3f | 1998 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1999 | /* set SPIV separately to get count of SW disabled APICs right */ |
2000 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
2001 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
2002 | /* call kvm_apic_set_id() to put apic into apic_map */ |
2003 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
2004 | kvm_apic_set_version(vcpu); |
2005 | ||
96ad2cc6 | 2006 | apic_update_ppr(apic); |
d3c7b77d | 2007 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 2008 | apic_update_lvtt(apic); |
dfb95954 | 2009 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
2010 | update_divide_count(apic); |
2011 | start_apic_timer(apic); | |
6e24a6ef | 2012 | apic->irr_pending = true; |
d62caabb | 2013 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 2014 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 2015 | apic->highest_isr_cache = -1; |
d62caabb | 2016 | if (vcpu->arch.apicv_active) { |
be8ca170 SS |
2017 | if (kvm_x86_ops->apicv_post_state_restore) |
2018 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
4114c27d WW |
2019 | kvm_x86_ops->hwapic_irr_update(vcpu, |
2020 | apic_find_highest_irr(apic)); | |
67c9dddc | 2021 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 2022 | apic_find_highest_isr(apic)); |
d62caabb | 2023 | } |
3842d135 | 2024 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2025 | if (ioapic_in_kernel(vcpu->kvm)) |
2026 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2027 | |
2028 | vcpu->arch.apic_arb_prio = 0; | |
96ad2cc6 | 2029 | } |
a3d7f85f | 2030 | |
2f52d58c | 2031 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2032 | { |
a3d7f85f ED |
2033 | struct hrtimer *timer; |
2034 | ||
bce87cce | 2035 | if (!lapic_in_kernel(vcpu)) |
a3d7f85f ED |
2036 | return; |
2037 | ||
54e9818f | 2038 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2039 | if (hrtimer_cancel(timer)) |
61abdbe0 | 2040 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); |
a3d7f85f | 2041 | } |
b93463aa | 2042 | |
ae7a2a3f MT |
2043 | /* |
2044 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2045 | * | |
2046 | * Detect whether guest triggered PV EOI since the | |
2047 | * last entry. If yes, set EOI on guests's behalf. | |
2048 | * Clear PV EOI in guest memory in any case. | |
2049 | */ | |
2050 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2051 | struct kvm_lapic *apic) | |
2052 | { | |
2053 | bool pending; | |
2054 | int vector; | |
2055 | /* | |
2056 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2057 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2058 | * | |
2059 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2060 | * -> host disabled PV EOI. | |
2061 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2062 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2063 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2064 | * -> host enabled PV EOI, guest executed EOI. | |
2065 | */ | |
2066 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2067 | pending = pv_eoi_get_pending(vcpu); | |
2068 | /* | |
2069 | * Clear pending bit in any case: it will be set again on vmentry. | |
2070 | * While this might not be ideal from performance point of view, | |
2071 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2072 | */ | |
2073 | pv_eoi_clr_pending(vcpu); | |
2074 | if (pending) | |
2075 | return; | |
2076 | vector = apic_set_eoi(apic); | |
2077 | trace_kvm_pv_eoi(apic, vector); | |
2078 | } | |
2079 | ||
b93463aa AK |
2080 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2081 | { | |
2082 | u32 data; | |
b93463aa | 2083 | |
ae7a2a3f MT |
2084 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2085 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2086 | ||
41383771 | 2087 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2088 | return; |
2089 | ||
603242a8 NK |
2090 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2091 | sizeof(u32))) | |
2092 | return; | |
b93463aa AK |
2093 | |
2094 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2095 | } | |
2096 | ||
ae7a2a3f MT |
2097 | /* |
2098 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2099 | * | |
2100 | * Detect whether it's safe to enable PV EOI and | |
2101 | * if yes do so. | |
2102 | */ | |
2103 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2104 | struct kvm_lapic *apic) | |
2105 | { | |
2106 | if (!pv_eoi_enabled(vcpu) || | |
2107 | /* IRR set or many bits in ISR: could be nested. */ | |
2108 | apic->irr_pending || | |
2109 | /* Cache not set: could be safe but we don't bother. */ | |
2110 | apic->highest_isr_cache == -1 || | |
2111 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2112 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2113 | /* |
2114 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2115 | * so we need not do anything here. | |
2116 | */ | |
2117 | return; | |
2118 | } | |
2119 | ||
2120 | pv_eoi_set_pending(apic->vcpu); | |
2121 | } | |
2122 | ||
b93463aa AK |
2123 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2124 | { | |
2125 | u32 data, tpr; | |
2126 | int max_irr, max_isr; | |
ae7a2a3f | 2127 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2128 | |
ae7a2a3f MT |
2129 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2130 | ||
41383771 | 2131 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2132 | return; |
2133 | ||
dfb95954 | 2134 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2135 | max_irr = apic_find_highest_irr(apic); |
2136 | if (max_irr < 0) | |
2137 | max_irr = 0; | |
2138 | max_isr = apic_find_highest_isr(apic); | |
2139 | if (max_isr < 0) | |
2140 | max_isr = 0; | |
2141 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2142 | ||
fda4e2e8 AH |
2143 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2144 | sizeof(u32)); | |
b93463aa AK |
2145 | } |
2146 | ||
fda4e2e8 | 2147 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2148 | { |
fda4e2e8 AH |
2149 | if (vapic_addr) { |
2150 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2151 | &vcpu->arch.apic->vapic_cache, | |
2152 | vapic_addr, sizeof(u32))) | |
2153 | return -EINVAL; | |
41383771 | 2154 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2155 | } else { |
41383771 | 2156 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2157 | } |
2158 | ||
2159 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2160 | return 0; | |
b93463aa | 2161 | } |
0105d1a5 GN |
2162 | |
2163 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2164 | { | |
2165 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2166 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2167 | ||
35754c98 | 2168 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2169 | return 1; |
2170 | ||
c69d3d9b NA |
2171 | if (reg == APIC_ICR2) |
2172 | return 1; | |
2173 | ||
0105d1a5 | 2174 | /* if this is ICR write vector before command */ |
decdc283 | 2175 | if (reg == APIC_ICR) |
1e6e2755 SS |
2176 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2177 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2178 | } |
2179 | ||
2180 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2181 | { | |
2182 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2183 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2184 | ||
35754c98 | 2185 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2186 | return 1; |
2187 | ||
c69d3d9b NA |
2188 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2189 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2190 | reg); | |
2191 | return 1; | |
2192 | } | |
2193 | ||
1e6e2755 | 2194 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2195 | return 1; |
decdc283 | 2196 | if (reg == APIC_ICR) |
1e6e2755 | 2197 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2198 | |
2199 | *data = (((u64)high) << 32) | low; | |
2200 | ||
2201 | return 0; | |
2202 | } | |
10388a07 GN |
2203 | |
2204 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2205 | { | |
2206 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2207 | ||
bce87cce | 2208 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2209 | return 1; |
2210 | ||
2211 | /* if this is ICR write vector before command */ | |
2212 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2213 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2214 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2215 | } |
2216 | ||
2217 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2218 | { | |
2219 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2220 | u32 low, high = 0; | |
2221 | ||
bce87cce | 2222 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2223 | return 1; |
2224 | ||
1e6e2755 | 2225 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2226 | return 1; |
2227 | if (reg == APIC_ICR) | |
1e6e2755 | 2228 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2229 | |
2230 | *data = (((u64)high) << 32) | low; | |
2231 | ||
2232 | return 0; | |
2233 | } | |
ae7a2a3f MT |
2234 | |
2235 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2236 | { | |
2237 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2238 | if (!IS_ALIGNED(addr, 4)) | |
2239 | return 1; | |
2240 | ||
2241 | vcpu->arch.pv_eoi.msr_val = data; | |
2242 | if (!pv_eoi_enabled(vcpu)) | |
2243 | return 0; | |
2244 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2245 | addr, sizeof(u8)); |
ae7a2a3f | 2246 | } |
c5cc421b | 2247 | |
66450a21 JK |
2248 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2249 | { | |
2250 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2251 | u8 sipi_vector; |
299018f4 | 2252 | unsigned long pe; |
66450a21 | 2253 | |
bce87cce | 2254 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2255 | return; |
2256 | ||
cd7764fe PB |
2257 | /* |
2258 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2259 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2260 | * and delay processing of INIT until the next RSM. | |
2261 | */ | |
2262 | if (is_smm(vcpu)) { | |
2263 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2264 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2265 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2266 | return; | |
2267 | } | |
299018f4 | 2268 | |
cd7764fe | 2269 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2270 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2271 | kvm_lapic_reset(vcpu, true); |
2272 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2273 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2274 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2275 | else | |
2276 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2277 | } | |
299018f4 | 2278 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2279 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2280 | /* evaluate pending_events before reading the vector */ | |
2281 | smp_rmb(); | |
2282 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2283 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2284 | vcpu->vcpu_id, sipi_vector); |
2285 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2286 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2287 | } | |
2288 | } | |
2289 | ||
c5cc421b GN |
2290 | void kvm_lapic_init(void) |
2291 | { | |
2292 | /* do not patch jump label more than once per second */ | |
2293 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2294 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2295 | } |