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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
1767e931 | 28 | #include <linux/export.h> |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
97222cc8 ED |
57 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ |
58 | #define apic_debug(fmt, arg...) | |
59 | ||
97222cc8 | 60 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 61 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
62 | #define LAPIC_MMIO_LENGTH (1 << 12) |
63 | /* followed define is not in apicdef.h */ | |
64 | #define APIC_SHORT_MASK 0xc0000 | |
65 | #define APIC_DEST_NOSHORT 0x0 | |
66 | #define APIC_DEST_MASK 0x800 | |
67 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 68 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 69 | |
394457a9 NA |
70 | #define APIC_BROADCAST 0xFF |
71 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
72 | ||
a0c9a822 MT |
73 | static inline int apic_test_vector(int vec, void *bitmap) |
74 | { | |
75 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
76 | } | |
77 | ||
10606919 YZ |
78 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
79 | { | |
80 | struct kvm_lapic *apic = vcpu->arch.apic; | |
81 | ||
82 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
83 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
84 | } | |
85 | ||
97222cc8 ED |
86 | static inline void apic_clear_vector(int vec, void *bitmap) |
87 | { | |
88 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
89 | } | |
90 | ||
8680b94b MT |
91 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
92 | { | |
93 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
94 | } | |
95 | ||
96 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
97 | { | |
98 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
99 | } | |
100 | ||
c5cc421b | 101 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
102 | struct static_key_deferred apic_sw_disabled __read_mostly; |
103 | ||
97222cc8 ED |
104 | static inline int apic_enabled(struct kvm_lapic *apic) |
105 | { | |
c48f1496 | 106 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
107 | } |
108 | ||
97222cc8 ED |
109 | #define LVT_MASK \ |
110 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
111 | ||
112 | #define LINT_MASK \ | |
113 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
114 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
115 | ||
6e500439 RK |
116 | static inline u8 kvm_xapic_id(struct kvm_lapic *apic) |
117 | { | |
118 | return kvm_lapic_get_reg(apic, APIC_ID) >> 24; | |
119 | } | |
120 | ||
121 | static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) | |
122 | { | |
123 | return apic->vcpu->vcpu_id; | |
124 | } | |
125 | ||
e45115b6 RK |
126 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
127 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
128 | switch (map->mode) { | |
129 | case KVM_APIC_MODE_X2APIC: { | |
130 | u32 offset = (dest_id >> 16) * 16; | |
0ca52e7b | 131 | u32 max_apic_id = map->max_apic_id; |
e45115b6 RK |
132 | |
133 | if (offset <= max_apic_id) { | |
134 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
135 | ||
136 | *cluster = &map->phys_map[offset]; | |
137 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
138 | } else { | |
139 | *mask = 0; | |
140 | } | |
3b5a5ffa | 141 | |
e45115b6 RK |
142 | return true; |
143 | } | |
144 | case KVM_APIC_MODE_XAPIC_FLAT: | |
145 | *cluster = map->xapic_flat_map; | |
146 | *mask = dest_id & 0xff; | |
147 | return true; | |
148 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
444fdad8 | 149 | *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; |
e45115b6 RK |
150 | *mask = dest_id & 0xf; |
151 | return true; | |
152 | default: | |
153 | /* Not optimized. */ | |
154 | return false; | |
155 | } | |
3548a259 RK |
156 | } |
157 | ||
af1bae54 | 158 | static void kvm_apic_map_free(struct rcu_head *rcu) |
3b5a5ffa | 159 | { |
af1bae54 | 160 | struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu); |
3b5a5ffa | 161 | |
af1bae54 | 162 | kvfree(map); |
3b5a5ffa RK |
163 | } |
164 | ||
1e08ec4a GN |
165 | static void recalculate_apic_map(struct kvm *kvm) |
166 | { | |
167 | struct kvm_apic_map *new, *old = NULL; | |
168 | struct kvm_vcpu *vcpu; | |
169 | int i; | |
6e500439 | 170 | u32 max_id = 255; /* enough space for any xAPIC ID */ |
1e08ec4a GN |
171 | |
172 | mutex_lock(&kvm->arch.apic_map_lock); | |
173 | ||
0ca52e7b RK |
174 | kvm_for_each_vcpu(i, vcpu, kvm) |
175 | if (kvm_apic_present(vcpu)) | |
6e500439 | 176 | max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); |
0ca52e7b | 177 | |
a7c3e901 MH |
178 | new = kvzalloc(sizeof(struct kvm_apic_map) + |
179 | sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL); | |
0ca52e7b | 180 | |
1e08ec4a GN |
181 | if (!new) |
182 | goto out; | |
183 | ||
0ca52e7b RK |
184 | new->max_apic_id = max_id; |
185 | ||
173beedc NA |
186 | kvm_for_each_vcpu(i, vcpu, kvm) { |
187 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
188 | struct kvm_lapic **cluster; |
189 | u16 mask; | |
5bd5db38 RK |
190 | u32 ldr; |
191 | u8 xapic_id; | |
192 | u32 x2apic_id; | |
1e08ec4a | 193 | |
df04d1d1 RK |
194 | if (!kvm_apic_present(vcpu)) |
195 | continue; | |
196 | ||
5bd5db38 RK |
197 | xapic_id = kvm_xapic_id(apic); |
198 | x2apic_id = kvm_x2apic_id(apic); | |
199 | ||
200 | /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */ | |
201 | if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && | |
202 | x2apic_id <= new->max_apic_id) | |
203 | new->phys_map[x2apic_id] = apic; | |
204 | /* | |
205 | * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, | |
206 | * prevent them from masking VCPUs with APIC ID <= 0xff. | |
207 | */ | |
208 | if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) | |
209 | new->phys_map[xapic_id] = apic; | |
3548a259 | 210 | |
6e500439 RK |
211 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
212 | ||
3b5a5ffa RK |
213 | if (apic_x2apic_mode(apic)) { |
214 | new->mode |= KVM_APIC_MODE_X2APIC; | |
215 | } else if (ldr) { | |
216 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 217 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
218 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
219 | else | |
220 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
221 | } | |
222 | ||
e45115b6 | 223 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
224 | continue; |
225 | ||
e45115b6 RK |
226 | if (mask) |
227 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
228 | } |
229 | out: | |
230 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
231 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
232 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
233 | mutex_unlock(&kvm->arch.apic_map_lock); | |
234 | ||
235 | if (old) | |
af1bae54 | 236 | call_rcu(&old->rcu, kvm_apic_map_free); |
c7c9c56c | 237 | |
b053b2ae | 238 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
239 | } |
240 | ||
1e1b6c26 NA |
241 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
242 | { | |
e462755c | 243 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 244 | |
1e6e2755 | 245 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
246 | |
247 | if (enabled != apic->sw_enabled) { | |
248 | apic->sw_enabled = enabled; | |
249 | if (enabled) { | |
1e1b6c26 NA |
250 | static_key_slow_dec_deferred(&apic_sw_disabled); |
251 | recalculate_apic_map(apic->vcpu->kvm); | |
252 | } else | |
253 | static_key_slow_inc(&apic_sw_disabled.key); | |
254 | } | |
255 | } | |
256 | ||
a92e2543 | 257 | static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) |
1e08ec4a | 258 | { |
1e6e2755 | 259 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
260 | recalculate_apic_map(apic->vcpu->kvm); |
261 | } | |
262 | ||
263 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
264 | { | |
1e6e2755 | 265 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
266 | recalculate_apic_map(apic->vcpu->kvm); |
267 | } | |
268 | ||
e872fa94 DDAG |
269 | static inline u32 kvm_apic_calc_x2apic_ldr(u32 id) |
270 | { | |
271 | return ((id >> 4) << 16) | (1 << (id & 0xf)); | |
272 | } | |
273 | ||
a92e2543 | 274 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) |
257b9a5f | 275 | { |
e872fa94 | 276 | u32 ldr = kvm_apic_calc_x2apic_ldr(id); |
257b9a5f | 277 | |
6e500439 RK |
278 | WARN_ON_ONCE(id != apic->vcpu->vcpu_id); |
279 | ||
a92e2543 | 280 | kvm_lapic_set_reg(apic, APIC_ID, id); |
1e6e2755 | 281 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); |
257b9a5f RK |
282 | recalculate_apic_map(apic->vcpu->kvm); |
283 | } | |
284 | ||
97222cc8 ED |
285 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
286 | { | |
dfb95954 | 287 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
288 | } |
289 | ||
290 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
291 | { | |
dfb95954 | 292 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
293 | } |
294 | ||
a3e06bbe LJ |
295 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
296 | { | |
f30ebc31 | 297 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
298 | } |
299 | ||
97222cc8 ED |
300 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
301 | { | |
f30ebc31 | 302 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
303 | } |
304 | ||
305 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
306 | { | |
f30ebc31 | 307 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
308 | } |
309 | ||
cc6e462c JK |
310 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
311 | { | |
312 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
313 | } | |
314 | ||
fc61b800 GN |
315 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
316 | { | |
317 | struct kvm_lapic *apic = vcpu->arch.apic; | |
318 | struct kvm_cpuid_entry2 *feat; | |
319 | u32 v = APIC_VERSION; | |
320 | ||
bce87cce | 321 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
322 | return; |
323 | ||
324 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
325 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
326 | v |= APIC_LVR_DIRECTED_EOI; | |
1e6e2755 | 327 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
328 | } |
329 | ||
1e6e2755 | 330 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 331 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
332 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
333 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
334 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
335 | LVT_MASK /* LVTERR */ | |
336 | }; | |
337 | ||
338 | static int find_highest_vector(void *bitmap) | |
339 | { | |
ecba9a52 TY |
340 | int vec; |
341 | u32 *reg; | |
97222cc8 | 342 | |
ecba9a52 TY |
343 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
344 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
345 | reg = bitmap + REG_POS(vec); | |
346 | if (*reg) | |
810e6def | 347 | return __fls(*reg) + vec; |
ecba9a52 | 348 | } |
97222cc8 | 349 | |
ecba9a52 | 350 | return -1; |
97222cc8 ED |
351 | } |
352 | ||
8680b94b MT |
353 | static u8 count_vectors(void *bitmap) |
354 | { | |
ecba9a52 TY |
355 | int vec; |
356 | u32 *reg; | |
8680b94b | 357 | u8 count = 0; |
ecba9a52 TY |
358 | |
359 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
360 | reg = bitmap + REG_POS(vec); | |
361 | count += hweight32(*reg); | |
362 | } | |
363 | ||
8680b94b MT |
364 | return count; |
365 | } | |
366 | ||
e7387b0e | 367 | bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) |
a20ed54d | 368 | { |
810e6def | 369 | u32 i, vec; |
e7387b0e LA |
370 | u32 pir_val, irr_val, prev_irr_val; |
371 | int max_updated_irr; | |
372 | ||
373 | max_updated_irr = -1; | |
374 | *max_irr = -1; | |
a20ed54d | 375 | |
810e6def | 376 | for (i = vec = 0; i <= 7; i++, vec += 32) { |
ad361091 | 377 | pir_val = READ_ONCE(pir[i]); |
810e6def | 378 | irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10)); |
ad361091 | 379 | if (pir_val) { |
e7387b0e | 380 | prev_irr_val = irr_val; |
810e6def PB |
381 | irr_val |= xchg(&pir[i], 0); |
382 | *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val; | |
e7387b0e LA |
383 | if (prev_irr_val != irr_val) { |
384 | max_updated_irr = | |
385 | __fls(irr_val ^ prev_irr_val) + vec; | |
386 | } | |
ad361091 | 387 | } |
810e6def | 388 | if (irr_val) |
e7387b0e | 389 | *max_irr = __fls(irr_val) + vec; |
a20ed54d | 390 | } |
810e6def | 391 | |
e7387b0e LA |
392 | return ((max_updated_irr != -1) && |
393 | (max_updated_irr == *max_irr)); | |
a20ed54d | 394 | } |
705699a1 WV |
395 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
396 | ||
e7387b0e | 397 | bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr) |
705699a1 WV |
398 | { |
399 | struct kvm_lapic *apic = vcpu->arch.apic; | |
400 | ||
e7387b0e | 401 | return __kvm_apic_update_irr(pir, apic->regs, max_irr); |
705699a1 | 402 | } |
a20ed54d YZ |
403 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
404 | ||
33e4c686 | 405 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 406 | { |
33e4c686 | 407 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
408 | } |
409 | ||
410 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
411 | { | |
412 | int result; | |
413 | ||
c7c9c56c YZ |
414 | /* |
415 | * Note that irr_pending is just a hint. It will be always | |
416 | * true with virtual interrupt delivery enabled. | |
417 | */ | |
33e4c686 GN |
418 | if (!apic->irr_pending) |
419 | return -1; | |
420 | ||
421 | result = apic_search_irr(apic); | |
97222cc8 ED |
422 | ASSERT(result == -1 || result >= 16); |
423 | ||
424 | return result; | |
425 | } | |
426 | ||
33e4c686 GN |
427 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
428 | { | |
56cc2406 WL |
429 | struct kvm_vcpu *vcpu; |
430 | ||
431 | vcpu = apic->vcpu; | |
432 | ||
d62caabb | 433 | if (unlikely(vcpu->arch.apicv_active)) { |
b95234c8 | 434 | /* need to update RVI */ |
f210f757 | 435 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
b95234c8 PB |
436 | kvm_x86_ops->hwapic_irr_update(vcpu, |
437 | apic_find_highest_irr(apic)); | |
f210f757 NA |
438 | } else { |
439 | apic->irr_pending = false; | |
440 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
441 | if (apic_search_irr(apic) != -1) | |
442 | apic->irr_pending = true; | |
56cc2406 | 443 | } |
33e4c686 GN |
444 | } |
445 | ||
8680b94b MT |
446 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
447 | { | |
56cc2406 WL |
448 | struct kvm_vcpu *vcpu; |
449 | ||
450 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
451 | return; | |
452 | ||
453 | vcpu = apic->vcpu; | |
fc57ac2c | 454 | |
8680b94b | 455 | /* |
56cc2406 WL |
456 | * With APIC virtualization enabled, all caching is disabled |
457 | * because the processor can modify ISR under the hood. Instead | |
458 | * just set SVI. | |
8680b94b | 459 | */ |
d62caabb | 460 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 461 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
462 | else { |
463 | ++apic->isr_count; | |
464 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
465 | /* | |
466 | * ISR (in service register) bit is set when injecting an interrupt. | |
467 | * The highest vector is injected. Thus the latest bit set matches | |
468 | * the highest bit in ISR. | |
469 | */ | |
470 | apic->highest_isr_cache = vec; | |
471 | } | |
8680b94b MT |
472 | } |
473 | ||
fc57ac2c PB |
474 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
475 | { | |
476 | int result; | |
477 | ||
478 | /* | |
479 | * Note that isr_count is always 1, and highest_isr_cache | |
480 | * is always -1, with APIC virtualization enabled. | |
481 | */ | |
482 | if (!apic->isr_count) | |
483 | return -1; | |
484 | if (likely(apic->highest_isr_cache != -1)) | |
485 | return apic->highest_isr_cache; | |
486 | ||
487 | result = find_highest_vector(apic->regs + APIC_ISR); | |
488 | ASSERT(result == -1 || result >= 16); | |
489 | ||
490 | return result; | |
491 | } | |
492 | ||
8680b94b MT |
493 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
494 | { | |
fc57ac2c PB |
495 | struct kvm_vcpu *vcpu; |
496 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
497 | return; | |
498 | ||
499 | vcpu = apic->vcpu; | |
500 | ||
501 | /* | |
502 | * We do get here for APIC virtualization enabled if the guest | |
503 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
504 | * to trigger a new interrupt delivery by writing the SVI field; | |
505 | * on the other hand isr_count and highest_isr_cache are unused | |
506 | * and must be left alone. | |
507 | */ | |
d62caabb | 508 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 509 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
510 | apic_find_highest_isr(apic)); |
511 | else { | |
8680b94b | 512 | --apic->isr_count; |
fc57ac2c PB |
513 | BUG_ON(apic->isr_count < 0); |
514 | apic->highest_isr_cache = -1; | |
515 | } | |
8680b94b MT |
516 | } |
517 | ||
6e5d865c YS |
518 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
519 | { | |
33e4c686 GN |
520 | /* This may race with setting of irr in __apic_accept_irq() and |
521 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
522 | * will cause vmexit immediately and the value will be recalculated | |
523 | * on the next vmentry. | |
524 | */ | |
f8543d6a | 525 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 526 | } |
76dfafd5 | 527 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); |
6e5d865c | 528 | |
6da7e3f6 | 529 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 530 | int vector, int level, int trig_mode, |
9e4aabe2 | 531 | struct dest_map *dest_map); |
6da7e3f6 | 532 | |
b4f2225c | 533 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 534 | struct dest_map *dest_map) |
97222cc8 | 535 | { |
ad312c7c | 536 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 537 | |
58c2dde1 | 538 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 539 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
540 | } |
541 | ||
ae7a2a3f MT |
542 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
543 | { | |
4e335d9e PB |
544 | |
545 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
546 | sizeof(val)); | |
ae7a2a3f MT |
547 | } |
548 | ||
549 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
550 | { | |
4e335d9e PB |
551 | |
552 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
553 | sizeof(*val)); | |
ae7a2a3f MT |
554 | } |
555 | ||
556 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
557 | { | |
558 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
559 | } | |
560 | ||
561 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
562 | { | |
563 | u8 val; | |
564 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
565 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 566 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
567 | return val & 0x1; |
568 | } | |
569 | ||
570 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
571 | { | |
572 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
573 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 574 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
575 | return; |
576 | } | |
577 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
578 | } | |
579 | ||
580 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
581 | { | |
582 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
583 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 584 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
585 | return; |
586 | } | |
587 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
588 | } | |
589 | ||
b3c045d3 PB |
590 | static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) |
591 | { | |
3d92789f | 592 | int highest_irr; |
fa59cc00 | 593 | if (apic->vcpu->arch.apicv_active) |
76dfafd5 PB |
594 | highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu); |
595 | else | |
596 | highest_irr = apic_find_highest_irr(apic); | |
b3c045d3 PB |
597 | if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) |
598 | return -1; | |
599 | return highest_irr; | |
600 | } | |
601 | ||
602 | static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) | |
97222cc8 | 603 | { |
3842d135 | 604 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
605 | int isr; |
606 | ||
dfb95954 SS |
607 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
608 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
609 | isr = apic_find_highest_isr(apic); |
610 | isrv = (isr != -1) ? isr : 0; | |
611 | ||
612 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
613 | ppr = tpr & 0xff; | |
614 | else | |
615 | ppr = isrv & 0xf0; | |
616 | ||
617 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
618 | apic, ppr, isr, isrv); | |
619 | ||
b3c045d3 PB |
620 | *new_ppr = ppr; |
621 | if (old_ppr != ppr) | |
1e6e2755 | 622 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
b3c045d3 PB |
623 | |
624 | return ppr < old_ppr; | |
625 | } | |
626 | ||
627 | static void apic_update_ppr(struct kvm_lapic *apic) | |
628 | { | |
629 | u32 ppr; | |
630 | ||
26fbbee5 PB |
631 | if (__apic_update_ppr(apic, &ppr) && |
632 | apic_has_interrupt_for_ppr(apic, ppr) != -1) | |
b3c045d3 | 633 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
97222cc8 ED |
634 | } |
635 | ||
eb90f341 PB |
636 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu) |
637 | { | |
638 | apic_update_ppr(vcpu->arch.apic); | |
639 | } | |
640 | EXPORT_SYMBOL_GPL(kvm_apic_update_ppr); | |
641 | ||
97222cc8 ED |
642 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) |
643 | { | |
1e6e2755 | 644 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
645 | apic_update_ppr(apic); |
646 | } | |
647 | ||
03d2249e | 648 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 649 | { |
b4535b58 RK |
650 | return mda == (apic_x2apic_mode(apic) ? |
651 | X2APIC_BROADCAST : APIC_BROADCAST); | |
394457a9 NA |
652 | } |
653 | ||
03d2249e | 654 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 655 | { |
03d2249e RK |
656 | if (kvm_apic_broadcast(apic, mda)) |
657 | return true; | |
658 | ||
659 | if (apic_x2apic_mode(apic)) | |
6e500439 | 660 | return mda == kvm_x2apic_id(apic); |
03d2249e | 661 | |
5bd5db38 RK |
662 | /* |
663 | * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if | |
664 | * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and | |
665 | * this allows unique addressing of VCPUs with APIC ID over 0xff. | |
666 | * The 0xff condition is needed because writeable xAPIC ID. | |
667 | */ | |
668 | if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) | |
669 | return true; | |
670 | ||
b4535b58 | 671 | return mda == kvm_xapic_id(apic); |
97222cc8 ED |
672 | } |
673 | ||
52c233a4 | 674 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 675 | { |
0105d1a5 GN |
676 | u32 logical_id; |
677 | ||
394457a9 | 678 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 679 | return true; |
394457a9 | 680 | |
dfb95954 | 681 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 682 | |
9368b567 | 683 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
684 | return ((logical_id >> 16) == (mda >> 16)) |
685 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 686 | |
9368b567 | 687 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
97222cc8 | 688 | |
dfb95954 | 689 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 690 | case APIC_DFR_FLAT: |
9368b567 | 691 | return (logical_id & mda) != 0; |
97222cc8 | 692 | case APIC_DFR_CLUSTER: |
9368b567 RK |
693 | return ((logical_id >> 4) == (mda >> 4)) |
694 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 695 | default: |
7712de87 | 696 | apic_debug("Bad DFR vcpu %d: %08x\n", |
dfb95954 | 697 | apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); |
9368b567 | 698 | return false; |
97222cc8 | 699 | } |
97222cc8 ED |
700 | } |
701 | ||
c519265f RK |
702 | /* The KVM local APIC implementation has two quirks: |
703 | * | |
b4535b58 RK |
704 | * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs |
705 | * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID. | |
706 | * KVM doesn't do that aliasing. | |
c519265f RK |
707 | * |
708 | * - in-kernel IOAPIC messages have to be delivered directly to | |
709 | * x2APIC, because the kernel does not support interrupt remapping. | |
710 | * In order to support broadcast without interrupt remapping, x2APIC | |
711 | * rewrites the destination of non-IPI messages from APIC_BROADCAST | |
712 | * to X2APIC_BROADCAST. | |
713 | * | |
714 | * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is | |
715 | * important when userspace wants to use x2APIC-format MSIs, because | |
716 | * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7". | |
03d2249e | 717 | */ |
c519265f RK |
718 | static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id, |
719 | struct kvm_lapic *source, struct kvm_lapic *target) | |
03d2249e RK |
720 | { |
721 | bool ipi = source != NULL; | |
03d2249e | 722 | |
c519265f | 723 | if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && |
b4535b58 | 724 | !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) |
03d2249e RK |
725 | return X2APIC_BROADCAST; |
726 | ||
b4535b58 | 727 | return dest_id; |
03d2249e RK |
728 | } |
729 | ||
52c233a4 | 730 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 731 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 732 | { |
ad312c7c | 733 | struct kvm_lapic *target = vcpu->arch.apic; |
c519265f | 734 | u32 mda = kvm_apic_mda(vcpu, dest, source, target); |
97222cc8 ED |
735 | |
736 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 737 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
738 | target, source, dest, dest_mode, short_hand); |
739 | ||
bd371396 | 740 | ASSERT(target); |
97222cc8 ED |
741 | switch (short_hand) { |
742 | case APIC_DEST_NOSHORT: | |
3697f302 | 743 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 744 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 745 | else |
03d2249e | 746 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 747 | case APIC_DEST_SELF: |
9368b567 | 748 | return target == source; |
97222cc8 | 749 | case APIC_DEST_ALLINC: |
9368b567 | 750 | return true; |
97222cc8 | 751 | case APIC_DEST_ALLBUT: |
9368b567 | 752 | return target != source; |
97222cc8 | 753 | default: |
7712de87 JK |
754 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
755 | short_hand); | |
9368b567 | 756 | return false; |
97222cc8 | 757 | } |
97222cc8 | 758 | } |
1e6e2755 | 759 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 760 | |
52004014 FW |
761 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
762 | const unsigned long *bitmap, u32 bitmap_size) | |
763 | { | |
764 | u32 mod; | |
765 | int i, idx = -1; | |
766 | ||
767 | mod = vector % dest_vcpus; | |
768 | ||
769 | for (i = 0; i <= mod; i++) { | |
770 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
771 | BUG_ON(idx == bitmap_size); | |
772 | } | |
773 | ||
774 | return idx; | |
775 | } | |
776 | ||
4efd805f RK |
777 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
778 | { | |
779 | if (!kvm->arch.disabled_lapic_found) { | |
780 | kvm->arch.disabled_lapic_found = true; | |
781 | printk(KERN_INFO | |
782 | "Disabled LAPIC found during irq injection\n"); | |
783 | } | |
784 | } | |
785 | ||
c519265f RK |
786 | static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src, |
787 | struct kvm_lapic_irq *irq, struct kvm_apic_map *map) | |
1e08ec4a | 788 | { |
c519265f RK |
789 | if (kvm->arch.x2apic_broadcast_quirk_disabled) { |
790 | if ((irq->dest_id == APIC_BROADCAST && | |
791 | map->mode != KVM_APIC_MODE_X2APIC)) | |
792 | return true; | |
793 | if (irq->dest_id == X2APIC_BROADCAST) | |
794 | return true; | |
795 | } else { | |
796 | bool x2apic_ipi = src && *src && apic_x2apic_mode(*src); | |
797 | if (irq->dest_id == (x2apic_ipi ? | |
798 | X2APIC_BROADCAST : APIC_BROADCAST)) | |
799 | return true; | |
800 | } | |
1e08ec4a | 801 | |
c519265f RK |
802 | return false; |
803 | } | |
1e08ec4a | 804 | |
64aa47bf RK |
805 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
806 | * for valid destinations in *dst array. | |
807 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
808 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
809 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
810 | * zero and *dst undefined. | |
811 | */ | |
812 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
813 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
814 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
815 | unsigned long *bitmap) | |
816 | { | |
817 | int i, lowest; | |
1e08ec4a | 818 | |
64aa47bf RK |
819 | if (irq->shorthand == APIC_DEST_SELF && src) { |
820 | *dst = src; | |
821 | *bitmap = 1; | |
822 | return true; | |
823 | } else if (irq->shorthand) | |
1e08ec4a GN |
824 | return false; |
825 | ||
c519265f | 826 | if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map)) |
9ea369b0 RK |
827 | return false; |
828 | ||
64aa47bf | 829 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
0ca52e7b | 830 | if (irq->dest_id > map->max_apic_id) { |
64aa47bf RK |
831 | *bitmap = 0; |
832 | } else { | |
833 | *dst = &map->phys_map[irq->dest_id]; | |
834 | *bitmap = 1; | |
835 | } | |
1e08ec4a | 836 | return true; |
bea15428 | 837 | } |
698f9755 | 838 | |
e45115b6 RK |
839 | *bitmap = 0; |
840 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
841 | (u16 *)bitmap)) | |
1e08ec4a | 842 | return false; |
fa834e91 | 843 | |
64aa47bf RK |
844 | if (!kvm_lowest_prio_delivery(irq)) |
845 | return true; | |
3548a259 | 846 | |
64aa47bf RK |
847 | if (!kvm_vector_hashing_enabled()) { |
848 | lowest = -1; | |
849 | for_each_set_bit(i, bitmap, 16) { | |
850 | if (!(*dst)[i]) | |
851 | continue; | |
852 | if (lowest < 0) | |
853 | lowest = i; | |
854 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
855 | (*dst)[lowest]->vcpu) < 0) | |
856 | lowest = i; | |
3548a259 | 857 | } |
64aa47bf RK |
858 | } else { |
859 | if (!*bitmap) | |
860 | return true; | |
3548a259 | 861 | |
64aa47bf RK |
862 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
863 | bitmap, 16); | |
45c3094a | 864 | |
64aa47bf RK |
865 | if (!(*dst)[lowest]) { |
866 | kvm_apic_disabled_lapic_found(kvm); | |
867 | *bitmap = 0; | |
868 | return true; | |
869 | } | |
870 | } | |
1e08ec4a | 871 | |
64aa47bf | 872 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 873 | |
64aa47bf RK |
874 | return true; |
875 | } | |
52004014 | 876 | |
64aa47bf RK |
877 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
878 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
879 | { | |
880 | struct kvm_apic_map *map; | |
881 | unsigned long bitmap; | |
882 | struct kvm_lapic **dst = NULL; | |
883 | int i; | |
884 | bool ret; | |
52004014 | 885 | |
64aa47bf | 886 | *r = -1; |
52004014 | 887 | |
64aa47bf RK |
888 | if (irq->shorthand == APIC_DEST_SELF) { |
889 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
890 | return true; | |
891 | } | |
52004014 | 892 | |
64aa47bf RK |
893 | rcu_read_lock(); |
894 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 895 | |
64aa47bf RK |
896 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
897 | if (ret) | |
898 | for_each_set_bit(i, &bitmap, 16) { | |
899 | if (!dst[i]) | |
900 | continue; | |
901 | if (*r < 0) | |
902 | *r = 0; | |
903 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); | |
1e08ec4a | 904 | } |
1e08ec4a | 905 | |
1e08ec4a GN |
906 | rcu_read_unlock(); |
907 | return ret; | |
908 | } | |
909 | ||
6228a0da FW |
910 | /* |
911 | * This routine tries to handler interrupts in posted mode, here is how | |
912 | * it deals with different cases: | |
913 | * - For single-destination interrupts, handle it in posted mode | |
914 | * - Else if vector hashing is enabled and it is a lowest-priority | |
915 | * interrupt, handle it in posted mode and use the following mechanism | |
916 | * to find the destinaiton vCPU. | |
917 | * 1. For lowest-priority interrupts, store all the possible | |
918 | * destination vCPUs in an array. | |
919 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
920 | * the right destination vCPU in the array for the lowest-priority | |
921 | * interrupt. | |
922 | * - Otherwise, use remapped mode to inject the interrupt. | |
923 | */ | |
8feb4a04 FW |
924 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
925 | struct kvm_vcpu **dest_vcpu) | |
926 | { | |
927 | struct kvm_apic_map *map; | |
64aa47bf RK |
928 | unsigned long bitmap; |
929 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 930 | bool ret = false; |
8feb4a04 FW |
931 | |
932 | if (irq->shorthand) | |
933 | return false; | |
934 | ||
935 | rcu_read_lock(); | |
936 | map = rcu_dereference(kvm->arch.apic_map); | |
937 | ||
64aa47bf RK |
938 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
939 | hweight16(bitmap) == 1) { | |
940 | unsigned long i = find_first_bit(&bitmap, 16); | |
6228a0da | 941 | |
64aa47bf RK |
942 | if (dst[i]) { |
943 | *dest_vcpu = dst[i]->vcpu; | |
944 | ret = true; | |
6228a0da | 945 | } |
8feb4a04 FW |
946 | } |
947 | ||
8feb4a04 FW |
948 | rcu_read_unlock(); |
949 | return ret; | |
950 | } | |
951 | ||
97222cc8 ED |
952 | /* |
953 | * Add a pending IRQ into lapic. | |
954 | * Return 1 if successfully added and 0 if discarded. | |
955 | */ | |
956 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 957 | int vector, int level, int trig_mode, |
9e4aabe2 | 958 | struct dest_map *dest_map) |
97222cc8 | 959 | { |
6da7e3f6 | 960 | int result = 0; |
c5ec1534 | 961 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 962 | |
a183b638 PB |
963 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
964 | trig_mode, vector); | |
97222cc8 | 965 | switch (delivery_mode) { |
97222cc8 | 966 | case APIC_DM_LOWEST: |
e1035715 GN |
967 | vcpu->arch.apic_arb_prio++; |
968 | case APIC_DM_FIXED: | |
bdaffe1d PB |
969 | if (unlikely(trig_mode && !level)) |
970 | break; | |
971 | ||
97222cc8 ED |
972 | /* FIXME add logic for vcpu on reset */ |
973 | if (unlikely(!apic_enabled(apic))) | |
974 | break; | |
975 | ||
11f5cc05 JK |
976 | result = 1; |
977 | ||
9daa5007 | 978 | if (dest_map) { |
9e4aabe2 | 979 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
980 | dest_map->vectors[vcpu->vcpu_id] = vector; |
981 | } | |
a5d36f82 | 982 | |
bdaffe1d PB |
983 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
984 | if (trig_mode) | |
1e6e2755 | 985 | kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); |
bdaffe1d PB |
986 | else |
987 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
988 | } | |
989 | ||
d62caabb | 990 | if (vcpu->arch.apicv_active) |
5a71785d | 991 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 992 | else { |
1e6e2755 | 993 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
994 | |
995 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
996 | kvm_vcpu_kick(vcpu); | |
997 | } | |
97222cc8 ED |
998 | break; |
999 | ||
1000 | case APIC_DM_REMRD: | |
24d2166b R |
1001 | result = 1; |
1002 | vcpu->arch.pv.pv_unhalted = 1; | |
1003 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1004 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1005 | break; |
1006 | ||
1007 | case APIC_DM_SMI: | |
64d60670 PB |
1008 | result = 1; |
1009 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
1010 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 1011 | break; |
3419ffc8 | 1012 | |
97222cc8 | 1013 | case APIC_DM_NMI: |
6da7e3f6 | 1014 | result = 1; |
3419ffc8 | 1015 | kvm_inject_nmi(vcpu); |
26df99c6 | 1016 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
1017 | break; |
1018 | ||
1019 | case APIC_DM_INIT: | |
a52315e1 | 1020 | if (!trig_mode || level) { |
6da7e3f6 | 1021 | result = 1; |
66450a21 JK |
1022 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
1023 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
1024 | /* make sure pending_events is visible before sending | |
1025 | * the request */ | |
1026 | smp_wmb(); | |
3842d135 | 1027 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
1028 | kvm_vcpu_kick(vcpu); |
1029 | } else { | |
1b10bf31 JK |
1030 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
1031 | vcpu->vcpu_id); | |
c5ec1534 | 1032 | } |
97222cc8 ED |
1033 | break; |
1034 | ||
1035 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
1036 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
1037 | vcpu->vcpu_id, vector); | |
66450a21 JK |
1038 | result = 1; |
1039 | apic->sipi_vector = vector; | |
1040 | /* make sure sipi_vector is visible for the receiver */ | |
1041 | smp_wmb(); | |
1042 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
1043 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1044 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1045 | break; |
1046 | ||
23930f95 JK |
1047 | case APIC_DM_EXTINT: |
1048 | /* | |
1049 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
1050 | * before NMI watchdog was enabled. Already handled by | |
1051 | * kvm_apic_accept_pic_intr(). | |
1052 | */ | |
1053 | break; | |
1054 | ||
97222cc8 ED |
1055 | default: |
1056 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
1057 | delivery_mode); | |
1058 | break; | |
1059 | } | |
1060 | return result; | |
1061 | } | |
1062 | ||
e1035715 | 1063 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 1064 | { |
e1035715 | 1065 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
1066 | } |
1067 | ||
3bb345f3 PB |
1068 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
1069 | { | |
6308630b | 1070 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
1071 | } |
1072 | ||
c7c9c56c YZ |
1073 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
1074 | { | |
7543a635 SR |
1075 | int trigger_mode; |
1076 | ||
1077 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
1078 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
1079 | return; | |
3bb345f3 | 1080 | |
7543a635 SR |
1081 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
1082 | if (irqchip_split(apic->vcpu->kvm)) { | |
1083 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
1084 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
1085 | return; | |
c7c9c56c | 1086 | } |
7543a635 SR |
1087 | |
1088 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
1089 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
1090 | else | |
1091 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1092 | ||
1093 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
1094 | } |
1095 | ||
ae7a2a3f | 1096 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
1097 | { |
1098 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
1099 | |
1100 | trace_kvm_eoi(apic, vector); | |
1101 | ||
97222cc8 ED |
1102 | /* |
1103 | * Not every write EOI will has corresponding ISR, | |
1104 | * one example is when Kernel check timer on setup_IO_APIC | |
1105 | */ | |
1106 | if (vector == -1) | |
ae7a2a3f | 1107 | return vector; |
97222cc8 | 1108 | |
8680b94b | 1109 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1110 | apic_update_ppr(apic); |
1111 | ||
5c919412 AS |
1112 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
1113 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
1114 | ||
c7c9c56c | 1115 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1116 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1117 | return vector; |
97222cc8 ED |
1118 | } |
1119 | ||
c7c9c56c YZ |
1120 | /* |
1121 | * this interface assumes a trap-like exit, which has already finished | |
1122 | * desired side effect including vISR and vPPR update. | |
1123 | */ | |
1124 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1125 | { | |
1126 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1127 | ||
1128 | trace_kvm_eoi(apic, vector); | |
1129 | ||
1130 | kvm_ioapic_send_eoi(apic, vector); | |
1131 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1132 | } | |
1133 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1134 | ||
97222cc8 ED |
1135 | static void apic_send_ipi(struct kvm_lapic *apic) |
1136 | { | |
dfb95954 SS |
1137 | u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); |
1138 | u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1139 | struct kvm_lapic_irq irq; |
97222cc8 | 1140 | |
58c2dde1 GN |
1141 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1142 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1143 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1144 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1145 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1146 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1147 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1148 | if (apic_x2apic_mode(apic)) |
1149 | irq.dest_id = icr_high; | |
1150 | else | |
1151 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1152 | |
1000ff8d GN |
1153 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1154 | ||
97222cc8 ED |
1155 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1156 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1157 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1158 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1159 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1160 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1161 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1162 | |
b4f2225c | 1163 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1164 | } |
1165 | ||
1166 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1167 | { | |
8003c9ae | 1168 | ktime_t remaining, now; |
b682b814 | 1169 | s64 ns; |
9da8f4e8 | 1170 | u32 tmcct; |
97222cc8 ED |
1171 | |
1172 | ASSERT(apic != NULL); | |
1173 | ||
9da8f4e8 | 1174 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1175 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1176 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1177 | return 0; |
1178 | ||
5587859f | 1179 | now = ktime_get(); |
8003c9ae | 1180 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); |
b682b814 | 1181 | if (ktime_to_ns(remaining) < 0) |
8b0e1953 | 1182 | remaining = 0; |
b682b814 | 1183 | |
d3c7b77d MT |
1184 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1185 | tmcct = div64_u64(ns, | |
1186 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1187 | |
1188 | return tmcct; | |
1189 | } | |
1190 | ||
b209749f AK |
1191 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1192 | { | |
1193 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1194 | struct kvm_run *run = vcpu->run; | |
1195 | ||
a8eeb04a | 1196 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1197 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1198 | run->tpr_access.is_write = write; |
1199 | } | |
1200 | ||
1201 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1202 | { | |
1203 | if (apic->vcpu->arch.tpr_access_reporting) | |
1204 | __report_tpr_access(apic, write); | |
1205 | } | |
1206 | ||
97222cc8 ED |
1207 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1208 | { | |
1209 | u32 val = 0; | |
1210 | ||
1211 | if (offset >= LAPIC_MMIO_LENGTH) | |
1212 | return 0; | |
1213 | ||
1214 | switch (offset) { | |
1215 | case APIC_ARBPRI: | |
7712de87 | 1216 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1217 | break; |
1218 | ||
1219 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1220 | if (apic_lvtt_tscdeadline(apic)) |
1221 | return 0; | |
1222 | ||
97222cc8 ED |
1223 | val = apic_get_tmcct(apic); |
1224 | break; | |
4a4541a4 AK |
1225 | case APIC_PROCPRI: |
1226 | apic_update_ppr(apic); | |
dfb95954 | 1227 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1228 | break; |
b209749f AK |
1229 | case APIC_TASKPRI: |
1230 | report_tpr_access(apic, false); | |
1231 | /* fall thru */ | |
97222cc8 | 1232 | default: |
dfb95954 | 1233 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1234 | break; |
1235 | } | |
1236 | ||
1237 | return val; | |
1238 | } | |
1239 | ||
d76685c4 GH |
1240 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1241 | { | |
1242 | return container_of(dev, struct kvm_lapic, dev); | |
1243 | } | |
1244 | ||
1e6e2755 | 1245 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1246 | void *data) |
97222cc8 | 1247 | { |
97222cc8 ED |
1248 | unsigned char alignment = offset & 0xf; |
1249 | u32 result; | |
d5b0b5b1 | 1250 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1251 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1252 | |
1253 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1254 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1255 | offset, len); | |
0105d1a5 | 1256 | return 1; |
97222cc8 | 1257 | } |
0105d1a5 GN |
1258 | |
1259 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1260 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1261 | offset); | |
0105d1a5 GN |
1262 | return 1; |
1263 | } | |
1264 | ||
97222cc8 ED |
1265 | result = __apic_read(apic, offset & ~0xf); |
1266 | ||
229456fc MT |
1267 | trace_kvm_apic_read(offset, result); |
1268 | ||
97222cc8 ED |
1269 | switch (len) { |
1270 | case 1: | |
1271 | case 2: | |
1272 | case 4: | |
1273 | memcpy(data, (char *)&result + alignment, len); | |
1274 | break; | |
1275 | default: | |
1276 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1277 | "should be 1,2, or 4 instead\n", len); | |
1278 | break; | |
1279 | } | |
bda9020e | 1280 | return 0; |
97222cc8 | 1281 | } |
1e6e2755 | 1282 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1283 | |
0105d1a5 GN |
1284 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1285 | { | |
c48f1496 | 1286 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1287 | addr >= apic->base_address && |
1288 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1289 | } | |
1290 | ||
e32edf4f | 1291 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1292 | gpa_t address, int len, void *data) |
1293 | { | |
1294 | struct kvm_lapic *apic = to_lapic(this); | |
1295 | u32 offset = address - apic->base_address; | |
1296 | ||
1297 | if (!apic_mmio_in_range(apic, address)) | |
1298 | return -EOPNOTSUPP; | |
1299 | ||
1e6e2755 | 1300 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1301 | |
1302 | return 0; | |
1303 | } | |
1304 | ||
97222cc8 ED |
1305 | static void update_divide_count(struct kvm_lapic *apic) |
1306 | { | |
1307 | u32 tmp1, tmp2, tdcr; | |
1308 | ||
dfb95954 | 1309 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1310 | tmp1 = tdcr & 0xf; |
1311 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1312 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1313 | |
1314 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1315 | apic->divide_count); |
97222cc8 ED |
1316 | } |
1317 | ||
ccbfa1d3 WL |
1318 | static void limit_periodic_timer_frequency(struct kvm_lapic *apic) |
1319 | { | |
1320 | /* | |
1321 | * Do not allow the guest to program periodic timers with small | |
1322 | * interval, since the hrtimers are not throttled by the host | |
1323 | * scheduler. | |
1324 | */ | |
dedf9c5e | 1325 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { |
ccbfa1d3 WL |
1326 | s64 min_period = min_timer_period_us * 1000LL; |
1327 | ||
1328 | if (apic->lapic_timer.period < min_period) { | |
1329 | pr_info_ratelimited( | |
1330 | "kvm: vcpu %i: requested %lld ns " | |
1331 | "lapic timer period limited to %lld ns\n", | |
1332 | apic->vcpu->vcpu_id, | |
1333 | apic->lapic_timer.period, min_period); | |
1334 | apic->lapic_timer.period = min_period; | |
1335 | } | |
1336 | } | |
1337 | } | |
1338 | ||
b6ac0695 RK |
1339 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1340 | { | |
dfb95954 | 1341 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1342 | apic->lapic_timer.timer_mode_mask; |
1343 | ||
1344 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
c69518c8 | 1345 | if (apic_lvtt_tscdeadline(apic) != (timer_mode == |
dedf9c5e | 1346 | APIC_LVT_TIMER_TSCDEADLINE)) { |
dedf9c5e | 1347 | hrtimer_cancel(&apic->lapic_timer.timer); |
44275932 RK |
1348 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); |
1349 | apic->lapic_timer.period = 0; | |
1350 | apic->lapic_timer.tscdeadline = 0; | |
dedf9c5e | 1351 | } |
b6ac0695 | 1352 | apic->lapic_timer.timer_mode = timer_mode; |
dedf9c5e | 1353 | limit_periodic_timer_frequency(apic); |
b6ac0695 RK |
1354 | } |
1355 | } | |
1356 | ||
5d87db71 RK |
1357 | static void apic_timer_expired(struct kvm_lapic *apic) |
1358 | { | |
1359 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1360 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1361 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1362 | |
5d87db71 RK |
1363 | if (atomic_read(&apic->lapic_timer.pending)) |
1364 | return; | |
1365 | ||
1366 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1367 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1368 | |
cc1b4680 DB |
1369 | /* |
1370 | * For x86, the atomic_inc() is serialized, thus | |
1371 | * using swait_active() is safe. | |
1372 | */ | |
8577370f MT |
1373 | if (swait_active(q)) |
1374 | swake_up(q); | |
d0659d94 MT |
1375 | |
1376 | if (apic_lvtt_tscdeadline(apic)) | |
1377 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1378 | } | |
1379 | ||
1380 | /* | |
1381 | * On APICv, this test will cause a busy wait | |
1382 | * during a higher-priority task. | |
1383 | */ | |
1384 | ||
1385 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1386 | { | |
1387 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1388 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1389 | |
1390 | if (kvm_apic_hw_enabled(apic)) { | |
1391 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1392 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1393 | |
d62caabb | 1394 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1395 | bitmap = apic->regs + APIC_IRR; |
1396 | ||
1397 | if (apic_test_vector(vec, bitmap)) | |
1398 | return true; | |
d0659d94 MT |
1399 | } |
1400 | return false; | |
1401 | } | |
1402 | ||
1403 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1404 | { | |
1405 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1406 | u64 guest_tsc, tsc_deadline; | |
1407 | ||
bce87cce | 1408 | if (!lapic_in_kernel(vcpu)) |
d0659d94 MT |
1409 | return; |
1410 | ||
1411 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1412 | return; | |
1413 | ||
1414 | if (!lapic_timer_int_injected(vcpu)) | |
1415 | return; | |
1416 | ||
1417 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1418 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1419 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1420 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1421 | |
1422 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1423 | if (guest_tsc < tsc_deadline) | |
b606f189 MT |
1424 | __delay(min(tsc_deadline - guest_tsc, |
1425 | nsec_to_cycles(vcpu, lapic_timer_advance_ns))); | |
5d87db71 RK |
1426 | } |
1427 | ||
53f9eedf YJ |
1428 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1429 | { | |
1430 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1431 | u64 ns = 0; | |
1432 | ktime_t expire; | |
1433 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1434 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1435 | unsigned long flags; | |
1436 | ktime_t now; | |
1437 | ||
1438 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1439 | return; | |
1440 | ||
1441 | local_irq_save(flags); | |
1442 | ||
5587859f | 1443 | now = ktime_get(); |
53f9eedf YJ |
1444 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1445 | if (likely(tscdeadline > guest_tsc)) { | |
1446 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1447 | do_div(ns, this_tsc_khz); | |
1448 | expire = ktime_add_ns(now, ns); | |
1449 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1450 | hrtimer_start(&apic->lapic_timer.timer, | |
1451 | expire, HRTIMER_MODE_ABS_PINNED); | |
1452 | } else | |
1453 | apic_timer_expired(apic); | |
1454 | ||
1455 | local_irq_restore(flags); | |
1456 | } | |
1457 | ||
7d7f7da2 | 1458 | static void start_sw_period(struct kvm_lapic *apic) |
8003c9ae WL |
1459 | { |
1460 | if (!apic->lapic_timer.period) | |
1461 | return; | |
1462 | ||
1463 | if (apic_lvtt_oneshot(apic) && | |
5587859f | 1464 | ktime_after(ktime_get(), |
8003c9ae WL |
1465 | apic->lapic_timer.target_expiration)) { |
1466 | apic_timer_expired(apic); | |
1467 | return; | |
1468 | } | |
1469 | ||
1470 | hrtimer_start(&apic->lapic_timer.timer, | |
1471 | apic->lapic_timer.target_expiration, | |
1472 | HRTIMER_MODE_ABS_PINNED); | |
1473 | } | |
1474 | ||
c301b909 WL |
1475 | static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) |
1476 | { | |
1477 | ktime_t now, remaining; | |
1478 | u64 ns_remaining_old, ns_remaining_new; | |
1479 | ||
1480 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) | |
1481 | * APIC_BUS_CYCLE_NS * apic->divide_count; | |
1482 | limit_periodic_timer_frequency(apic); | |
1483 | ||
1484 | now = ktime_get(); | |
1485 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); | |
1486 | if (ktime_to_ns(remaining) < 0) | |
1487 | remaining = 0; | |
1488 | ||
1489 | ns_remaining_old = ktime_to_ns(remaining); | |
1490 | ns_remaining_new = mul_u64_u32_div(ns_remaining_old, | |
1491 | apic->divide_count, old_divisor); | |
1492 | ||
1493 | apic->lapic_timer.tscdeadline += | |
1494 | nsec_to_cycles(apic->vcpu, ns_remaining_new) - | |
1495 | nsec_to_cycles(apic->vcpu, ns_remaining_old); | |
1496 | apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); | |
1497 | } | |
1498 | ||
8003c9ae | 1499 | static bool set_target_expiration(struct kvm_lapic *apic) |
7d7f7da2 WL |
1500 | { |
1501 | ktime_t now; | |
8003c9ae | 1502 | u64 tscl = rdtsc(); |
7d7f7da2 | 1503 | |
5587859f | 1504 | now = ktime_get(); |
7d7f7da2 | 1505 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
8003c9ae | 1506 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
7d7f7da2 | 1507 | |
5d74a699 RK |
1508 | if (!apic->lapic_timer.period) { |
1509 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae | 1510 | return false; |
7d7f7da2 WL |
1511 | } |
1512 | ||
ccbfa1d3 | 1513 | limit_periodic_timer_frequency(apic); |
7d7f7da2 | 1514 | |
7d7f7da2 WL |
1515 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
1516 | PRIx64 ", " | |
1517 | "timer initial count 0x%x, period %lldns, " | |
1518 | "expire @ 0x%016" PRIx64 ".\n", __func__, | |
1519 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), | |
1520 | kvm_lapic_get_reg(apic, APIC_TMICT), | |
1521 | apic->lapic_timer.period, | |
1522 | ktime_to_ns(ktime_add_ns(now, | |
1523 | apic->lapic_timer.period))); | |
8003c9ae WL |
1524 | |
1525 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + | |
1526 | nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); | |
1527 | apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); | |
1528 | ||
1529 | return true; | |
1530 | } | |
1531 | ||
1532 | static void advance_periodic_target_expiration(struct kvm_lapic *apic) | |
1533 | { | |
1534 | apic->lapic_timer.tscdeadline += | |
1535 | nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); | |
1536 | apic->lapic_timer.target_expiration = | |
1537 | ktime_add_ns(apic->lapic_timer.target_expiration, | |
1538 | apic->lapic_timer.period); | |
7d7f7da2 WL |
1539 | } |
1540 | ||
ce7a058a YJ |
1541 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1542 | { | |
91005300 WL |
1543 | if (!lapic_in_kernel(vcpu)) |
1544 | return false; | |
1545 | ||
ce7a058a YJ |
1546 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; |
1547 | } | |
1548 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1549 | ||
7e810a38 | 1550 | static void cancel_hv_timer(struct kvm_lapic *apic) |
bd97ad0e | 1551 | { |
1d518c68 | 1552 | WARN_ON(preemptible()); |
a749e247 | 1553 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
bd97ad0e WL |
1554 | kvm_x86_ops->cancel_hv_timer(apic->vcpu); |
1555 | apic->lapic_timer.hv_timer_in_use = false; | |
1556 | } | |
1557 | ||
a749e247 | 1558 | static bool start_hv_timer(struct kvm_lapic *apic) |
196f20ca | 1559 | { |
35ee9e48 PB |
1560 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1561 | int r; | |
196f20ca | 1562 | |
1d518c68 | 1563 | WARN_ON(preemptible()); |
a749e247 PB |
1564 | if (!kvm_x86_ops->set_hv_timer) |
1565 | return false; | |
1566 | ||
35ee9e48 PB |
1567 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) |
1568 | return false; | |
1569 | ||
86bbc1e6 RK |
1570 | if (!ktimer->tscdeadline) |
1571 | return false; | |
1572 | ||
35ee9e48 PB |
1573 | r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline); |
1574 | if (r < 0) | |
1575 | return false; | |
1576 | ||
1577 | ktimer->hv_timer_in_use = true; | |
1578 | hrtimer_cancel(&ktimer->timer); | |
196f20ca | 1579 | |
35ee9e48 PB |
1580 | /* |
1581 | * Also recheck ktimer->pending, in case the sw timer triggered in | |
1582 | * the window. For periodic timer, leave the hv timer running for | |
1583 | * simplicity, and the deadline will be recomputed on the next vmexit. | |
1584 | */ | |
c8533544 WL |
1585 | if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) { |
1586 | if (r) | |
1587 | apic_timer_expired(apic); | |
35ee9e48 | 1588 | return false; |
c8533544 | 1589 | } |
a749e247 PB |
1590 | |
1591 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true); | |
35ee9e48 PB |
1592 | return true; |
1593 | } | |
1594 | ||
a749e247 | 1595 | static void start_sw_timer(struct kvm_lapic *apic) |
35ee9e48 | 1596 | { |
a749e247 | 1597 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1d518c68 WL |
1598 | |
1599 | WARN_ON(preemptible()); | |
a749e247 PB |
1600 | if (apic->lapic_timer.hv_timer_in_use) |
1601 | cancel_hv_timer(apic); | |
1602 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) | |
1603 | return; | |
1604 | ||
1605 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) | |
1606 | start_sw_period(apic); | |
1607 | else if (apic_lvtt_tscdeadline(apic)) | |
1608 | start_sw_tscdeadline(apic); | |
1609 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); | |
1610 | } | |
35ee9e48 | 1611 | |
a749e247 PB |
1612 | static void restart_apic_timer(struct kvm_lapic *apic) |
1613 | { | |
1d518c68 | 1614 | preempt_disable(); |
a749e247 PB |
1615 | if (!start_hv_timer(apic)) |
1616 | start_sw_timer(apic); | |
1d518c68 | 1617 | preempt_enable(); |
196f20ca WL |
1618 | } |
1619 | ||
8003c9ae WL |
1620 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1621 | { | |
1622 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1623 | ||
1d518c68 WL |
1624 | preempt_disable(); |
1625 | /* If the preempt notifier has already run, it also called apic_timer_expired */ | |
1626 | if (!apic->lapic_timer.hv_timer_in_use) | |
1627 | goto out; | |
8003c9ae WL |
1628 | WARN_ON(swait_active(&vcpu->wq)); |
1629 | cancel_hv_timer(apic); | |
1630 | apic_timer_expired(apic); | |
1631 | ||
1632 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { | |
1633 | advance_periodic_target_expiration(apic); | |
a749e247 | 1634 | restart_apic_timer(apic); |
8003c9ae | 1635 | } |
1d518c68 WL |
1636 | out: |
1637 | preempt_enable(); | |
8003c9ae WL |
1638 | } |
1639 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1640 | ||
ce7a058a YJ |
1641 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1642 | { | |
a749e247 | 1643 | restart_apic_timer(vcpu->arch.apic); |
ce7a058a YJ |
1644 | } |
1645 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1646 | ||
1647 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1648 | { | |
1649 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1650 | ||
1d518c68 | 1651 | preempt_disable(); |
ce7a058a | 1652 | /* Possibly the TSC deadline timer is not enabled yet */ |
a749e247 PB |
1653 | if (apic->lapic_timer.hv_timer_in_use) |
1654 | start_sw_timer(apic); | |
1d518c68 | 1655 | preempt_enable(); |
a749e247 PB |
1656 | } |
1657 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
ce7a058a | 1658 | |
a749e247 PB |
1659 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) |
1660 | { | |
1661 | struct kvm_lapic *apic = vcpu->arch.apic; | |
ce7a058a | 1662 | |
a749e247 PB |
1663 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
1664 | restart_apic_timer(apic); | |
ce7a058a | 1665 | } |
ce7a058a | 1666 | |
97222cc8 ED |
1667 | static void start_apic_timer(struct kvm_lapic *apic) |
1668 | { | |
d3c7b77d | 1669 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1670 | |
a749e247 PB |
1671 | if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) |
1672 | && !set_target_expiration(apic)) | |
1673 | return; | |
1674 | ||
1675 | restart_apic_timer(apic); | |
97222cc8 ED |
1676 | } |
1677 | ||
cc6e462c JK |
1678 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1679 | { | |
59fd1323 | 1680 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1681 | |
59fd1323 RK |
1682 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1683 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1684 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1685 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1686 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1687 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1688 | } else |
1689 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1690 | } | |
cc6e462c JK |
1691 | } |
1692 | ||
1e6e2755 | 1693 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1694 | { |
0105d1a5 | 1695 | int ret = 0; |
97222cc8 | 1696 | |
0105d1a5 | 1697 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1698 | |
0105d1a5 | 1699 | switch (reg) { |
97222cc8 | 1700 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1701 | if (!apic_x2apic_mode(apic)) |
a92e2543 | 1702 | kvm_apic_set_xapic_id(apic, val >> 24); |
0105d1a5 GN |
1703 | else |
1704 | ret = 1; | |
97222cc8 ED |
1705 | break; |
1706 | ||
1707 | case APIC_TASKPRI: | |
b209749f | 1708 | report_tpr_access(apic, true); |
97222cc8 ED |
1709 | apic_set_tpr(apic, val & 0xff); |
1710 | break; | |
1711 | ||
1712 | case APIC_EOI: | |
1713 | apic_set_eoi(apic); | |
1714 | break; | |
1715 | ||
1716 | case APIC_LDR: | |
0105d1a5 | 1717 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1718 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1719 | else |
1720 | ret = 1; | |
97222cc8 ED |
1721 | break; |
1722 | ||
1723 | case APIC_DFR: | |
1e08ec4a | 1724 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1725 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1726 | recalculate_apic_map(apic->vcpu->kvm); |
1727 | } else | |
0105d1a5 | 1728 | ret = 1; |
97222cc8 ED |
1729 | break; |
1730 | ||
fc61b800 GN |
1731 | case APIC_SPIV: { |
1732 | u32 mask = 0x3ff; | |
dfb95954 | 1733 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1734 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1735 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1736 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1737 | int i; | |
1738 | u32 lvt_val; | |
1739 | ||
1e6e2755 | 1740 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1741 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1742 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1743 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1744 | lvt_val | APIC_LVT_MASKED); |
1745 | } | |
b6ac0695 | 1746 | apic_update_lvtt(apic); |
d3c7b77d | 1747 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1748 | |
1749 | } | |
1750 | break; | |
fc61b800 | 1751 | } |
97222cc8 ED |
1752 | case APIC_ICR: |
1753 | /* No delay here, so we always clear the pending bit */ | |
1e6e2755 | 1754 | kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); |
97222cc8 ED |
1755 | apic_send_ipi(apic); |
1756 | break; | |
1757 | ||
1758 | case APIC_ICR2: | |
0105d1a5 GN |
1759 | if (!apic_x2apic_mode(apic)) |
1760 | val &= 0xff000000; | |
1e6e2755 | 1761 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1762 | break; |
1763 | ||
23930f95 | 1764 | case APIC_LVT0: |
cc6e462c | 1765 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1766 | case APIC_LVTTHMR: |
1767 | case APIC_LVTPC: | |
97222cc8 ED |
1768 | case APIC_LVT1: |
1769 | case APIC_LVTERR: | |
1770 | /* TODO: Check vector */ | |
c48f1496 | 1771 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1772 | val |= APIC_LVT_MASKED; |
1773 | ||
0105d1a5 | 1774 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1775 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1776 | |
1777 | break; | |
1778 | ||
b6ac0695 | 1779 | case APIC_LVTT: |
c48f1496 | 1780 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1781 | val |= APIC_LVT_MASKED; |
1782 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1783 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1784 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1785 | break; |
1786 | ||
97222cc8 | 1787 | case APIC_TMICT: |
a3e06bbe LJ |
1788 | if (apic_lvtt_tscdeadline(apic)) |
1789 | break; | |
1790 | ||
d3c7b77d | 1791 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1792 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1793 | start_apic_timer(apic); |
0105d1a5 | 1794 | break; |
97222cc8 | 1795 | |
c301b909 WL |
1796 | case APIC_TDCR: { |
1797 | uint32_t old_divisor = apic->divide_count; | |
1798 | ||
97222cc8 | 1799 | if (val & 4) |
7712de87 | 1800 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
1e6e2755 | 1801 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 | 1802 | update_divide_count(apic); |
c301b909 WL |
1803 | if (apic->divide_count != old_divisor && |
1804 | apic->lapic_timer.period) { | |
1805 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1806 | update_target_expiration(apic, old_divisor); | |
1807 | restart_apic_timer(apic); | |
1808 | } | |
97222cc8 | 1809 | break; |
c301b909 | 1810 | } |
0105d1a5 GN |
1811 | case APIC_ESR: |
1812 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1813 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1814 | ret = 1; |
1815 | } | |
1816 | break; | |
1817 | ||
1818 | case APIC_SELF_IPI: | |
1819 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 1820 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
1821 | } else |
1822 | ret = 1; | |
1823 | break; | |
97222cc8 | 1824 | default: |
0105d1a5 | 1825 | ret = 1; |
97222cc8 ED |
1826 | break; |
1827 | } | |
0105d1a5 GN |
1828 | if (ret) |
1829 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1830 | return ret; | |
1831 | } | |
1e6e2755 | 1832 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 1833 | |
e32edf4f | 1834 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1835 | gpa_t address, int len, const void *data) |
1836 | { | |
1837 | struct kvm_lapic *apic = to_lapic(this); | |
1838 | unsigned int offset = address - apic->base_address; | |
1839 | u32 val; | |
1840 | ||
1841 | if (!apic_mmio_in_range(apic, address)) | |
1842 | return -EOPNOTSUPP; | |
1843 | ||
1844 | /* | |
1845 | * APIC register must be aligned on 128-bits boundary. | |
1846 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1847 | * Refer SDM 8.4.1 | |
1848 | */ | |
1849 | if (len != 4 || (offset & 0xf)) { | |
1850 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1851 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1852 | return 0; |
0105d1a5 GN |
1853 | } |
1854 | ||
1855 | val = *(u32*)data; | |
1856 | ||
1857 | /* too common printing */ | |
1858 | if (offset != APIC_EOI) | |
1859 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1860 | "0x%x\n", __func__, offset, len, val); | |
1861 | ||
1e6e2755 | 1862 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 1863 | |
bda9020e | 1864 | return 0; |
97222cc8 ED |
1865 | } |
1866 | ||
58fbbf26 KT |
1867 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1868 | { | |
1e6e2755 | 1869 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
1870 | } |
1871 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1872 | ||
83d4c286 YZ |
1873 | /* emulate APIC access in a trap manner */ |
1874 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1875 | { | |
1876 | u32 val = 0; | |
1877 | ||
1878 | /* hw has done the conditional check and inst decode */ | |
1879 | offset &= 0xff0; | |
1880 | ||
1e6e2755 | 1881 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
1882 | |
1883 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 1884 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
1885 | } |
1886 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1887 | ||
d589444e | 1888 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1889 | { |
f8c1ea10 GN |
1890 | struct kvm_lapic *apic = vcpu->arch.apic; |
1891 | ||
ad312c7c | 1892 | if (!vcpu->arch.apic) |
97222cc8 ED |
1893 | return; |
1894 | ||
f8c1ea10 | 1895 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1896 | |
c5cc421b GN |
1897 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1898 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1899 | ||
e462755c | 1900 | if (!apic->sw_enabled) |
f8c1ea10 | 1901 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1902 | |
f8c1ea10 GN |
1903 | if (apic->regs) |
1904 | free_page((unsigned long)apic->regs); | |
1905 | ||
1906 | kfree(apic); | |
97222cc8 ED |
1907 | } |
1908 | ||
1909 | /* | |
1910 | *---------------------------------------------------------------------- | |
1911 | * LAPIC interface | |
1912 | *---------------------------------------------------------------------- | |
1913 | */ | |
a3e06bbe LJ |
1914 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1915 | { | |
1916 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1917 | |
a10388e1 WL |
1918 | if (!lapic_in_kernel(vcpu) || |
1919 | !apic_lvtt_tscdeadline(apic)) | |
a3e06bbe LJ |
1920 | return 0; |
1921 | ||
1922 | return apic->lapic_timer.tscdeadline; | |
1923 | } | |
1924 | ||
1925 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1926 | { | |
1927 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1928 | |
bce87cce | 1929 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1930 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1931 | return; |
1932 | ||
1933 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1934 | apic->lapic_timer.tscdeadline = data; | |
1935 | start_apic_timer(apic); | |
1936 | } | |
1937 | ||
97222cc8 ED |
1938 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1939 | { | |
ad312c7c | 1940 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1941 | |
b93463aa | 1942 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 1943 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1944 | } |
1945 | ||
1946 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1947 | { | |
97222cc8 ED |
1948 | u64 tpr; |
1949 | ||
dfb95954 | 1950 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1951 | |
1952 | return (tpr & 0xf0) >> 4; | |
1953 | } | |
1954 | ||
1955 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1956 | { | |
8d14695f | 1957 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1958 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1959 | |
c7dd15b3 | 1960 | if (!apic) |
97222cc8 | 1961 | value |= MSR_IA32_APICBASE_BSP; |
c5af89b6 | 1962 | |
e66d2ae7 JK |
1963 | vcpu->arch.apic_base = value; |
1964 | ||
c7dd15b3 JM |
1965 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) |
1966 | kvm_update_cpuid(vcpu); | |
1967 | ||
1968 | if (!apic) | |
1969 | return; | |
1970 | ||
c5cc421b | 1971 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1972 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
49bd29ba RK |
1973 | if (value & MSR_IA32_APICBASE_ENABLE) { |
1974 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); | |
c5cc421b | 1975 | static_key_slow_dec_deferred(&apic_hw_disabled); |
187ca84b | 1976 | } else { |
c5cc421b | 1977 | static_key_slow_inc(&apic_hw_disabled.key); |
187ca84b WL |
1978 | recalculate_apic_map(vcpu->kvm); |
1979 | } | |
c5cc421b GN |
1980 | } |
1981 | ||
8d14695f YZ |
1982 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1983 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1984 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1985 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1986 | } else | |
1987 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1988 | } |
8d14695f | 1989 | |
ad312c7c | 1990 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1991 | MSR_IA32_APICBASE_BASE; |
1992 | ||
db324fe6 NA |
1993 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1994 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1995 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1996 | ||
97222cc8 ED |
1997 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1998 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1999 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
2000 | |
2001 | } | |
2002 | ||
d28bc9dd | 2003 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
2004 | { |
2005 | struct kvm_lapic *apic; | |
2006 | int i; | |
2007 | ||
b8688d51 | 2008 | apic_debug("%s\n", __func__); |
97222cc8 ED |
2009 | |
2010 | ASSERT(vcpu); | |
ad312c7c | 2011 | apic = vcpu->arch.apic; |
97222cc8 ED |
2012 | ASSERT(apic != NULL); |
2013 | ||
2014 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 2015 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2016 | |
4d8e772b RK |
2017 | if (!init_event) { |
2018 | kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | | |
2019 | MSR_IA32_APICBASE_ENABLE); | |
a92e2543 | 2020 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); |
4d8e772b | 2021 | } |
fc61b800 | 2022 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 2023 | |
1e6e2755 SS |
2024 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
2025 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 2026 | apic_update_lvtt(apic); |
52b54190 JS |
2027 | if (kvm_vcpu_is_reset_bsp(vcpu) && |
2028 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) | |
1e6e2755 | 2029 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 2030 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 2031 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 2032 | |
1e6e2755 | 2033 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 2034 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 2035 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
2036 | if (!apic_x2apic_mode(apic)) |
2037 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
2038 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
2039 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
2040 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
2041 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
2042 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 2043 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
2044 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
2045 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
2046 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 2047 | } |
d62caabb AS |
2048 | apic->irr_pending = vcpu->arch.apicv_active; |
2049 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 2050 | apic->highest_isr_cache = -1; |
b33ac88b | 2051 | update_divide_count(apic); |
d3c7b77d | 2052 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 2053 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
2054 | kvm_lapic_set_base(vcpu, |
2055 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 2056 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 | 2057 | apic_update_ppr(apic); |
4191db26 JS |
2058 | if (vcpu->arch.apicv_active) { |
2059 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
2060 | kvm_x86_ops->hwapic_irr_update(vcpu, -1); | |
2061 | kvm_x86_ops->hwapic_isr_update(vcpu, -1); | |
2062 | } | |
97222cc8 | 2063 | |
e1035715 | 2064 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 2065 | vcpu->arch.apic_attention = 0; |
e1035715 | 2066 | |
6e500439 | 2067 | apic_debug("%s: vcpu=%p, id=0x%x, base_msr=" |
b8688d51 | 2068 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
6e500439 | 2069 | vcpu, kvm_lapic_get_reg(apic, APIC_ID), |
ad312c7c | 2070 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
2071 | } |
2072 | ||
97222cc8 ED |
2073 | /* |
2074 | *---------------------------------------------------------------------- | |
2075 | * timer interface | |
2076 | *---------------------------------------------------------------------- | |
2077 | */ | |
1b9778da | 2078 | |
2a6eac96 | 2079 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 2080 | { |
d3c7b77d | 2081 | return apic_lvtt_period(apic); |
97222cc8 ED |
2082 | } |
2083 | ||
3d80840d MT |
2084 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
2085 | { | |
54e9818f | 2086 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 2087 | |
1e3161b4 | 2088 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 2089 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
2090 | |
2091 | return 0; | |
2092 | } | |
2093 | ||
89342082 | 2094 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 2095 | { |
dfb95954 | 2096 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 2097 | int vector, mode, trig_mode; |
23930f95 | 2098 | |
c48f1496 | 2099 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
2100 | vector = reg & APIC_VECTOR_MASK; |
2101 | mode = reg & APIC_MODE_MASK; | |
2102 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
2103 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
2104 | NULL); | |
23930f95 JK |
2105 | } |
2106 | return 0; | |
2107 | } | |
1b9778da | 2108 | |
8fdb2351 | 2109 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 2110 | { |
8fdb2351 JK |
2111 | struct kvm_lapic *apic = vcpu->arch.apic; |
2112 | ||
2113 | if (apic) | |
2114 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
2115 | } |
2116 | ||
d76685c4 GH |
2117 | static const struct kvm_io_device_ops apic_mmio_ops = { |
2118 | .read = apic_mmio_read, | |
2119 | .write = apic_mmio_write, | |
d76685c4 GH |
2120 | }; |
2121 | ||
e9d90d47 AK |
2122 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
2123 | { | |
2124 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 2125 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 2126 | |
5d87db71 | 2127 | apic_timer_expired(apic); |
e9d90d47 | 2128 | |
2a6eac96 | 2129 | if (lapic_is_periodic(apic)) { |
8003c9ae | 2130 | advance_periodic_target_expiration(apic); |
e9d90d47 AK |
2131 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
2132 | return HRTIMER_RESTART; | |
2133 | } else | |
2134 | return HRTIMER_NORESTART; | |
2135 | } | |
2136 | ||
97222cc8 ED |
2137 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
2138 | { | |
2139 | struct kvm_lapic *apic; | |
2140 | ||
2141 | ASSERT(vcpu != NULL); | |
2142 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
2143 | ||
2144 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
2145 | if (!apic) | |
2146 | goto nomem; | |
2147 | ||
ad312c7c | 2148 | vcpu->arch.apic = apic; |
97222cc8 | 2149 | |
afc20184 TY |
2150 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
2151 | if (!apic->regs) { | |
97222cc8 ED |
2152 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
2153 | vcpu->vcpu_id); | |
d589444e | 2154 | goto nomem_free_apic; |
97222cc8 | 2155 | } |
97222cc8 ED |
2156 | apic->vcpu = vcpu; |
2157 | ||
d3c7b77d | 2158 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
61abdbe0 | 2159 | HRTIMER_MODE_ABS_PINNED); |
e9d90d47 | 2160 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 2161 | |
c5cc421b GN |
2162 | /* |
2163 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
2164 | * thinking that APIC satet has changed. | |
2165 | */ | |
2166 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
f8c1ea10 | 2167 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d76685c4 | 2168 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
2169 | |
2170 | return 0; | |
d589444e RR |
2171 | nomem_free_apic: |
2172 | kfree(apic); | |
97222cc8 | 2173 | nomem: |
97222cc8 ED |
2174 | return -ENOMEM; |
2175 | } | |
97222cc8 ED |
2176 | |
2177 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
2178 | { | |
ad312c7c | 2179 | struct kvm_lapic *apic = vcpu->arch.apic; |
b3c045d3 | 2180 | u32 ppr; |
97222cc8 | 2181 | |
f8543d6a | 2182 | if (!apic_enabled(apic)) |
97222cc8 ED |
2183 | return -1; |
2184 | ||
b3c045d3 PB |
2185 | __apic_update_ppr(apic, &ppr); |
2186 | return apic_has_interrupt_for_ppr(apic, ppr); | |
97222cc8 ED |
2187 | } |
2188 | ||
40487c68 QH |
2189 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
2190 | { | |
dfb95954 | 2191 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
2192 | int r = 0; |
2193 | ||
c48f1496 | 2194 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
2195 | r = 1; |
2196 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
2197 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
2198 | r = 1; | |
40487c68 QH |
2199 | return r; |
2200 | } | |
2201 | ||
1b9778da ED |
2202 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
2203 | { | |
ad312c7c | 2204 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 2205 | |
54e9818f | 2206 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
f1ed0450 | 2207 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
2208 | if (apic_lvtt_tscdeadline(apic)) |
2209 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae WL |
2210 | if (apic_lvtt_oneshot(apic)) { |
2211 | apic->lapic_timer.tscdeadline = 0; | |
8b0e1953 | 2212 | apic->lapic_timer.target_expiration = 0; |
8003c9ae | 2213 | } |
f1ed0450 | 2214 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
2215 | } |
2216 | } | |
2217 | ||
97222cc8 ED |
2218 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
2219 | { | |
2220 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 2221 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d82d12b | 2222 | u32 ppr; |
97222cc8 ED |
2223 | |
2224 | if (vector == -1) | |
2225 | return -1; | |
2226 | ||
56cc2406 WL |
2227 | /* |
2228 | * We get here even with APIC virtualization enabled, if doing | |
2229 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
2230 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
2231 | * because the process would deliver it through the IDT. | |
2232 | */ | |
2233 | ||
97222cc8 | 2234 | apic_clear_irr(vector, apic); |
5c919412 | 2235 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { |
4d82d12b PB |
2236 | /* |
2237 | * For auto-EOI interrupts, there might be another pending | |
2238 | * interrupt above PPR, so check whether to raise another | |
2239 | * KVM_REQ_EVENT. | |
2240 | */ | |
5c919412 | 2241 | apic_update_ppr(apic); |
4d82d12b PB |
2242 | } else { |
2243 | /* | |
2244 | * For normal interrupts, PPR has been raised and there cannot | |
2245 | * be a higher-priority pending interrupt---except if there was | |
2246 | * a concurrent interrupt injection, but that would have | |
2247 | * triggered KVM_REQ_EVENT already. | |
2248 | */ | |
2249 | apic_set_isr(vector, apic); | |
2250 | __apic_update_ppr(apic, &ppr); | |
5c919412 AS |
2251 | } |
2252 | ||
97222cc8 ED |
2253 | return vector; |
2254 | } | |
96ad2cc6 | 2255 | |
a92e2543 RK |
2256 | static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, |
2257 | struct kvm_lapic_state *s, bool set) | |
2258 | { | |
2259 | if (apic_x2apic_mode(vcpu->arch.apic)) { | |
2260 | u32 *id = (u32 *)(s->regs + APIC_ID); | |
12806ba9 | 2261 | u32 *ldr = (u32 *)(s->regs + APIC_LDR); |
a92e2543 | 2262 | |
37131313 RK |
2263 | if (vcpu->kvm->arch.x2apic_format) { |
2264 | if (*id != vcpu->vcpu_id) | |
2265 | return -EINVAL; | |
2266 | } else { | |
2267 | if (set) | |
2268 | *id >>= 24; | |
2269 | else | |
2270 | *id <<= 24; | |
2271 | } | |
12806ba9 DDAG |
2272 | |
2273 | /* In x2APIC mode, the LDR is fixed and based on the id */ | |
2274 | if (set) | |
2275 | *ldr = kvm_apic_calc_x2apic_ldr(*id); | |
a92e2543 RK |
2276 | } |
2277 | ||
2278 | return 0; | |
2279 | } | |
2280 | ||
2281 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
2282 | { | |
2283 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); | |
2284 | return kvm_apic_state_fixup(vcpu, s, false); | |
2285 | } | |
2286 | ||
2287 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
96ad2cc6 | 2288 | { |
ad312c7c | 2289 | struct kvm_lapic *apic = vcpu->arch.apic; |
a92e2543 RK |
2290 | int r; |
2291 | ||
96ad2cc6 | 2292 | |
5dbc8f3f | 2293 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
2294 | /* set SPIV separately to get count of SW disabled APICs right */ |
2295 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
a92e2543 RK |
2296 | |
2297 | r = kvm_apic_state_fixup(vcpu, s, true); | |
2298 | if (r) | |
2299 | return r; | |
64eb0620 | 2300 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
a92e2543 RK |
2301 | |
2302 | recalculate_apic_map(vcpu->kvm); | |
fc61b800 GN |
2303 | kvm_apic_set_version(vcpu); |
2304 | ||
96ad2cc6 | 2305 | apic_update_ppr(apic); |
d3c7b77d | 2306 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 2307 | apic_update_lvtt(apic); |
dfb95954 | 2308 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
2309 | update_divide_count(apic); |
2310 | start_apic_timer(apic); | |
6e24a6ef | 2311 | apic->irr_pending = true; |
d62caabb | 2312 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 2313 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 2314 | apic->highest_isr_cache = -1; |
d62caabb | 2315 | if (vcpu->arch.apicv_active) { |
967235d3 | 2316 | kvm_x86_ops->apicv_post_state_restore(vcpu); |
4114c27d WW |
2317 | kvm_x86_ops->hwapic_irr_update(vcpu, |
2318 | apic_find_highest_irr(apic)); | |
67c9dddc | 2319 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 2320 | apic_find_highest_isr(apic)); |
d62caabb | 2321 | } |
3842d135 | 2322 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2323 | if (ioapic_in_kernel(vcpu->kvm)) |
2324 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2325 | |
2326 | vcpu->arch.apic_arb_prio = 0; | |
a92e2543 RK |
2327 | |
2328 | return 0; | |
96ad2cc6 | 2329 | } |
a3d7f85f | 2330 | |
2f52d58c | 2331 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2332 | { |
a3d7f85f ED |
2333 | struct hrtimer *timer; |
2334 | ||
bce87cce | 2335 | if (!lapic_in_kernel(vcpu)) |
a3d7f85f ED |
2336 | return; |
2337 | ||
54e9818f | 2338 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2339 | if (hrtimer_cancel(timer)) |
61abdbe0 | 2340 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); |
a3d7f85f | 2341 | } |
b93463aa | 2342 | |
ae7a2a3f MT |
2343 | /* |
2344 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2345 | * | |
2346 | * Detect whether guest triggered PV EOI since the | |
2347 | * last entry. If yes, set EOI on guests's behalf. | |
2348 | * Clear PV EOI in guest memory in any case. | |
2349 | */ | |
2350 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2351 | struct kvm_lapic *apic) | |
2352 | { | |
2353 | bool pending; | |
2354 | int vector; | |
2355 | /* | |
2356 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2357 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2358 | * | |
2359 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2360 | * -> host disabled PV EOI. | |
2361 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2362 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2363 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2364 | * -> host enabled PV EOI, guest executed EOI. | |
2365 | */ | |
2366 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2367 | pending = pv_eoi_get_pending(vcpu); | |
2368 | /* | |
2369 | * Clear pending bit in any case: it will be set again on vmentry. | |
2370 | * While this might not be ideal from performance point of view, | |
2371 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2372 | */ | |
2373 | pv_eoi_clr_pending(vcpu); | |
2374 | if (pending) | |
2375 | return; | |
2376 | vector = apic_set_eoi(apic); | |
2377 | trace_kvm_pv_eoi(apic, vector); | |
2378 | } | |
2379 | ||
b93463aa AK |
2380 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2381 | { | |
2382 | u32 data; | |
b93463aa | 2383 | |
ae7a2a3f MT |
2384 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2385 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2386 | ||
41383771 | 2387 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2388 | return; |
2389 | ||
4e335d9e PB |
2390 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2391 | sizeof(u32))) | |
603242a8 | 2392 | return; |
b93463aa AK |
2393 | |
2394 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2395 | } | |
2396 | ||
ae7a2a3f MT |
2397 | /* |
2398 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2399 | * | |
2400 | * Detect whether it's safe to enable PV EOI and | |
2401 | * if yes do so. | |
2402 | */ | |
2403 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2404 | struct kvm_lapic *apic) | |
2405 | { | |
2406 | if (!pv_eoi_enabled(vcpu) || | |
2407 | /* IRR set or many bits in ISR: could be nested. */ | |
2408 | apic->irr_pending || | |
2409 | /* Cache not set: could be safe but we don't bother. */ | |
2410 | apic->highest_isr_cache == -1 || | |
2411 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2412 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2413 | /* |
2414 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2415 | * so we need not do anything here. | |
2416 | */ | |
2417 | return; | |
2418 | } | |
2419 | ||
2420 | pv_eoi_set_pending(apic->vcpu); | |
2421 | } | |
2422 | ||
b93463aa AK |
2423 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2424 | { | |
2425 | u32 data, tpr; | |
2426 | int max_irr, max_isr; | |
ae7a2a3f | 2427 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2428 | |
ae7a2a3f MT |
2429 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2430 | ||
41383771 | 2431 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2432 | return; |
2433 | ||
dfb95954 | 2434 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2435 | max_irr = apic_find_highest_irr(apic); |
2436 | if (max_irr < 0) | |
2437 | max_irr = 0; | |
2438 | max_isr = apic_find_highest_isr(apic); | |
2439 | if (max_isr < 0) | |
2440 | max_isr = 0; | |
2441 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2442 | ||
4e335d9e PB |
2443 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2444 | sizeof(u32)); | |
b93463aa AK |
2445 | } |
2446 | ||
fda4e2e8 | 2447 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2448 | { |
fda4e2e8 | 2449 | if (vapic_addr) { |
4e335d9e | 2450 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
fda4e2e8 AH |
2451 | &vcpu->arch.apic->vapic_cache, |
2452 | vapic_addr, sizeof(u32))) | |
2453 | return -EINVAL; | |
41383771 | 2454 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2455 | } else { |
41383771 | 2456 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2457 | } |
2458 | ||
2459 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2460 | return 0; | |
b93463aa | 2461 | } |
0105d1a5 GN |
2462 | |
2463 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2464 | { | |
2465 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2466 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2467 | ||
35754c98 | 2468 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2469 | return 1; |
2470 | ||
c69d3d9b NA |
2471 | if (reg == APIC_ICR2) |
2472 | return 1; | |
2473 | ||
0105d1a5 | 2474 | /* if this is ICR write vector before command */ |
decdc283 | 2475 | if (reg == APIC_ICR) |
1e6e2755 SS |
2476 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2477 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2478 | } |
2479 | ||
2480 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2481 | { | |
2482 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2483 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2484 | ||
35754c98 | 2485 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2486 | return 1; |
2487 | ||
c69d3d9b NA |
2488 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2489 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2490 | reg); | |
2491 | return 1; | |
2492 | } | |
2493 | ||
1e6e2755 | 2494 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2495 | return 1; |
decdc283 | 2496 | if (reg == APIC_ICR) |
1e6e2755 | 2497 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2498 | |
2499 | *data = (((u64)high) << 32) | low; | |
2500 | ||
2501 | return 0; | |
2502 | } | |
10388a07 GN |
2503 | |
2504 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2505 | { | |
2506 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2507 | ||
bce87cce | 2508 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2509 | return 1; |
2510 | ||
2511 | /* if this is ICR write vector before command */ | |
2512 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2513 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2514 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2515 | } |
2516 | ||
2517 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2518 | { | |
2519 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2520 | u32 low, high = 0; | |
2521 | ||
bce87cce | 2522 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2523 | return 1; |
2524 | ||
1e6e2755 | 2525 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2526 | return 1; |
2527 | if (reg == APIC_ICR) | |
1e6e2755 | 2528 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2529 | |
2530 | *data = (((u64)high) << 32) | low; | |
2531 | ||
2532 | return 0; | |
2533 | } | |
ae7a2a3f MT |
2534 | |
2535 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2536 | { | |
2537 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2538 | if (!IS_ALIGNED(addr, 4)) | |
2539 | return 1; | |
2540 | ||
2541 | vcpu->arch.pv_eoi.msr_val = data; | |
2542 | if (!pv_eoi_enabled(vcpu)) | |
2543 | return 0; | |
4e335d9e | 2544 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, |
8f964525 | 2545 | addr, sizeof(u8)); |
ae7a2a3f | 2546 | } |
c5cc421b | 2547 | |
66450a21 JK |
2548 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2549 | { | |
2550 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2551 | u8 sipi_vector; |
299018f4 | 2552 | unsigned long pe; |
66450a21 | 2553 | |
bce87cce | 2554 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2555 | return; |
2556 | ||
cd7764fe PB |
2557 | /* |
2558 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2559 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2560 | * and delay processing of INIT until the next RSM. | |
2561 | */ | |
2562 | if (is_smm(vcpu)) { | |
2563 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2564 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2565 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2566 | return; | |
2567 | } | |
299018f4 | 2568 | |
cd7764fe | 2569 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2570 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2571 | kvm_lapic_reset(vcpu, true); |
2572 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2573 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2574 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2575 | else | |
2576 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2577 | } | |
299018f4 | 2578 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2579 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2580 | /* evaluate pending_events before reading the vector */ | |
2581 | smp_rmb(); | |
2582 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2583 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2584 | vcpu->vcpu_id, sipi_vector); |
2585 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2586 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2587 | } | |
2588 | } | |
2589 | ||
c5cc421b GN |
2590 | void kvm_lapic_init(void) |
2591 | { | |
2592 | /* do not patch jump label more than once per second */ | |
2593 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2594 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2595 | } |
cef84c30 DM |
2596 | |
2597 | void kvm_lapic_exit(void) | |
2598 | { | |
2599 | static_key_deferred_flush(&apic_hw_disabled); | |
2600 | static_key_deferred_flush(&apic_sw_disabled); | |
2601 | } |