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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
97222cc8 ED |
2 | |
3 | /* | |
4 | * Local APIC virtualization | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * Copyright (C) 2007 Novell | |
8 | * Copyright (C) 2007 Intel | |
9611c187 | 9 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
10 | * |
11 | * Authors: | |
12 | * Dor Laor <dor.laor@qumranet.com> | |
13 | * Gregory Haskins <ghaskins@novell.com> | |
14 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
15 | * | |
16 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
97222cc8 ED |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
97222cc8 ED |
20 | #include <linux/kvm.h> |
21 | #include <linux/mm.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/hrtimer.h> | |
25 | #include <linux/io.h> | |
1767e931 | 26 | #include <linux/export.h> |
6f6d6a1a | 27 | #include <linux/math64.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
97222cc8 ED |
29 | #include <asm/processor.h> |
30 | #include <asm/msr.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/current.h> | |
33 | #include <asm/apicdef.h> | |
d0659d94 | 34 | #include <asm/delay.h> |
60063497 | 35 | #include <linux/atomic.h> |
c5cc421b | 36 | #include <linux/jump_label.h> |
5fdbf976 | 37 | #include "kvm_cache_regs.h" |
97222cc8 | 38 | #include "irq.h" |
88197e6a | 39 | #include "ioapic.h" |
229456fc | 40 | #include "trace.h" |
fc61b800 | 41 | #include "x86.h" |
00b27a3e | 42 | #include "cpuid.h" |
5c919412 | 43 | #include "hyperv.h" |
97222cc8 | 44 | |
b682b814 MT |
45 | #ifndef CONFIG_X86_64 |
46 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
47 | #else | |
48 | #define mod_64(x, y) ((x) % (y)) | |
49 | #endif | |
50 | ||
97222cc8 ED |
51 | #define PRId64 "d" |
52 | #define PRIx64 "llx" | |
53 | #define PRIu64 "u" | |
54 | #define PRIo64 "o" | |
55 | ||
97222cc8 | 56 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 57 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
58 | #define LAPIC_MMIO_LENGTH (1 << 12) |
59 | /* followed define is not in apicdef.h */ | |
97222cc8 | 60 | #define MAX_APIC_VECTOR 256 |
ecba9a52 | 61 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 62 | |
d0f5a86a | 63 | static bool lapic_timer_advance_dynamic __read_mostly; |
a0f0037e WL |
64 | #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */ |
65 | #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */ | |
66 | #define LAPIC_TIMER_ADVANCE_NS_INIT 1000 | |
67 | #define LAPIC_TIMER_ADVANCE_NS_MAX 5000 | |
3b8a5df6 WL |
68 | /* step-by-step approximation to mitigate fluctuation */ |
69 | #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8 | |
70 | ||
a0c9a822 MT |
71 | static inline int apic_test_vector(int vec, void *bitmap) |
72 | { | |
73 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
74 | } | |
75 | ||
10606919 YZ |
76 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
77 | { | |
78 | struct kvm_lapic *apic = vcpu->arch.apic; | |
79 | ||
80 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
81 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
82 | } | |
83 | ||
8680b94b MT |
84 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
85 | { | |
86 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
87 | } | |
88 | ||
89 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
90 | { | |
91 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
92 | } | |
93 | ||
6e4e3b4d CL |
94 | __read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_hw_disabled, HZ); |
95 | __read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_sw_disabled, HZ); | |
f8c1ea10 | 96 | |
97222cc8 ED |
97 | static inline int apic_enabled(struct kvm_lapic *apic) |
98 | { | |
c48f1496 | 99 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
100 | } |
101 | ||
97222cc8 ED |
102 | #define LVT_MASK \ |
103 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
104 | ||
105 | #define LINT_MASK \ | |
106 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
107 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
108 | ||
6e500439 RK |
109 | static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) |
110 | { | |
111 | return apic->vcpu->vcpu_id; | |
112 | } | |
113 | ||
199a8b84 | 114 | static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu) |
0c5f81da WL |
115 | { |
116 | return pi_inject_timer && kvm_vcpu_apicv_active(vcpu); | |
117 | } | |
199a8b84 PB |
118 | |
119 | bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu) | |
120 | { | |
121 | return kvm_x86_ops.set_hv_timer | |
122 | && !(kvm_mwait_in_guest(vcpu->kvm) || | |
123 | kvm_can_post_timer_interrupt(vcpu)); | |
124 | } | |
125 | EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer); | |
0c5f81da WL |
126 | |
127 | static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu) | |
128 | { | |
129 | return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; | |
130 | } | |
131 | ||
e45115b6 RK |
132 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
133 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
134 | switch (map->mode) { | |
135 | case KVM_APIC_MODE_X2APIC: { | |
136 | u32 offset = (dest_id >> 16) * 16; | |
0ca52e7b | 137 | u32 max_apic_id = map->max_apic_id; |
e45115b6 RK |
138 | |
139 | if (offset <= max_apic_id) { | |
140 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
141 | ||
1d487e9b | 142 | offset = array_index_nospec(offset, map->max_apic_id + 1); |
e45115b6 RK |
143 | *cluster = &map->phys_map[offset]; |
144 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
145 | } else { | |
146 | *mask = 0; | |
147 | } | |
3b5a5ffa | 148 | |
e45115b6 RK |
149 | return true; |
150 | } | |
151 | case KVM_APIC_MODE_XAPIC_FLAT: | |
152 | *cluster = map->xapic_flat_map; | |
153 | *mask = dest_id & 0xff; | |
154 | return true; | |
155 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
444fdad8 | 156 | *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; |
e45115b6 RK |
157 | *mask = dest_id & 0xf; |
158 | return true; | |
159 | default: | |
160 | /* Not optimized. */ | |
161 | return false; | |
162 | } | |
3548a259 RK |
163 | } |
164 | ||
af1bae54 | 165 | static void kvm_apic_map_free(struct rcu_head *rcu) |
3b5a5ffa | 166 | { |
af1bae54 | 167 | struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu); |
3b5a5ffa | 168 | |
af1bae54 | 169 | kvfree(map); |
3b5a5ffa RK |
170 | } |
171 | ||
44d52717 PB |
172 | /* |
173 | * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock. | |
174 | * | |
175 | * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with | |
176 | * apic_map_lock_held. | |
177 | */ | |
178 | enum { | |
179 | CLEAN, | |
180 | UPDATE_IN_PROGRESS, | |
181 | DIRTY | |
182 | }; | |
183 | ||
4abaffce | 184 | void kvm_recalculate_apic_map(struct kvm *kvm) |
1e08ec4a GN |
185 | { |
186 | struct kvm_apic_map *new, *old = NULL; | |
187 | struct kvm_vcpu *vcpu; | |
188 | int i; | |
6e500439 | 189 | u32 max_id = 255; /* enough space for any xAPIC ID */ |
1e08ec4a | 190 | |
44d52717 PB |
191 | /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */ |
192 | if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN) | |
4abaffce | 193 | return; |
4abaffce | 194 | |
1e08ec4a | 195 | mutex_lock(&kvm->arch.apic_map_lock); |
44d52717 PB |
196 | /* |
197 | * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map | |
198 | * (if clean) or the APIC registers (if dirty). | |
199 | */ | |
200 | if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty, | |
201 | DIRTY, UPDATE_IN_PROGRESS) == CLEAN) { | |
4abaffce WL |
202 | /* Someone else has updated the map. */ |
203 | mutex_unlock(&kvm->arch.apic_map_lock); | |
204 | return; | |
205 | } | |
1e08ec4a | 206 | |
0ca52e7b RK |
207 | kvm_for_each_vcpu(i, vcpu, kvm) |
208 | if (kvm_apic_present(vcpu)) | |
6e500439 | 209 | max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); |
0ca52e7b | 210 | |
a7c3e901 | 211 | new = kvzalloc(sizeof(struct kvm_apic_map) + |
254272ce BG |
212 | sizeof(struct kvm_lapic *) * ((u64)max_id + 1), |
213 | GFP_KERNEL_ACCOUNT); | |
0ca52e7b | 214 | |
1e08ec4a GN |
215 | if (!new) |
216 | goto out; | |
217 | ||
0ca52e7b RK |
218 | new->max_apic_id = max_id; |
219 | ||
173beedc NA |
220 | kvm_for_each_vcpu(i, vcpu, kvm) { |
221 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
222 | struct kvm_lapic **cluster; |
223 | u16 mask; | |
5bd5db38 RK |
224 | u32 ldr; |
225 | u8 xapic_id; | |
226 | u32 x2apic_id; | |
1e08ec4a | 227 | |
df04d1d1 RK |
228 | if (!kvm_apic_present(vcpu)) |
229 | continue; | |
230 | ||
5bd5db38 RK |
231 | xapic_id = kvm_xapic_id(apic); |
232 | x2apic_id = kvm_x2apic_id(apic); | |
233 | ||
234 | /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */ | |
235 | if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && | |
236 | x2apic_id <= new->max_apic_id) | |
237 | new->phys_map[x2apic_id] = apic; | |
238 | /* | |
239 | * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, | |
240 | * prevent them from masking VCPUs with APIC ID <= 0xff. | |
241 | */ | |
242 | if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) | |
243 | new->phys_map[xapic_id] = apic; | |
3548a259 | 244 | |
b14c876b RK |
245 | if (!kvm_apic_sw_enabled(apic)) |
246 | continue; | |
247 | ||
6e500439 RK |
248 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
249 | ||
3b5a5ffa RK |
250 | if (apic_x2apic_mode(apic)) { |
251 | new->mode |= KVM_APIC_MODE_X2APIC; | |
252 | } else if (ldr) { | |
253 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 254 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
255 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
256 | else | |
257 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
258 | } | |
259 | ||
e45115b6 | 260 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
261 | continue; |
262 | ||
e45115b6 RK |
263 | if (mask) |
264 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
265 | } |
266 | out: | |
267 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
268 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
269 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
4abaffce | 270 | /* |
44d52717 PB |
271 | * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. |
272 | * If another update has come in, leave it DIRTY. | |
4abaffce | 273 | */ |
44d52717 PB |
274 | atomic_cmpxchg_release(&kvm->arch.apic_map_dirty, |
275 | UPDATE_IN_PROGRESS, CLEAN); | |
1e08ec4a GN |
276 | mutex_unlock(&kvm->arch.apic_map_lock); |
277 | ||
278 | if (old) | |
af1bae54 | 279 | call_rcu(&old->rcu, kvm_apic_map_free); |
c7c9c56c | 280 | |
b053b2ae | 281 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
282 | } |
283 | ||
1e1b6c26 NA |
284 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
285 | { | |
e462755c | 286 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 287 | |
1e6e2755 | 288 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
289 | |
290 | if (enabled != apic->sw_enabled) { | |
291 | apic->sw_enabled = enabled; | |
eb1ff0a9 | 292 | if (enabled) |
6e4e3b4d | 293 | static_branch_slow_dec_deferred(&apic_sw_disabled); |
eb1ff0a9 | 294 | else |
6e4e3b4d | 295 | static_branch_inc(&apic_sw_disabled.key); |
b14c876b | 296 | |
44d52717 | 297 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
1e1b6c26 NA |
298 | } |
299 | } | |
300 | ||
a92e2543 | 301 | static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) |
1e08ec4a | 302 | { |
1e6e2755 | 303 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
44d52717 | 304 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
1e08ec4a GN |
305 | } |
306 | ||
307 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
308 | { | |
1e6e2755 | 309 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
44d52717 | 310 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
1e08ec4a GN |
311 | } |
312 | ||
ae6f2496 WL |
313 | static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val) |
314 | { | |
315 | kvm_lapic_set_reg(apic, APIC_DFR, val); | |
316 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); | |
317 | } | |
318 | ||
e872fa94 DDAG |
319 | static inline u32 kvm_apic_calc_x2apic_ldr(u32 id) |
320 | { | |
321 | return ((id >> 4) << 16) | (1 << (id & 0xf)); | |
322 | } | |
323 | ||
a92e2543 | 324 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) |
257b9a5f | 325 | { |
e872fa94 | 326 | u32 ldr = kvm_apic_calc_x2apic_ldr(id); |
257b9a5f | 327 | |
6e500439 RK |
328 | WARN_ON_ONCE(id != apic->vcpu->vcpu_id); |
329 | ||
a92e2543 | 330 | kvm_lapic_set_reg(apic, APIC_ID, id); |
1e6e2755 | 331 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); |
44d52717 | 332 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
257b9a5f RK |
333 | } |
334 | ||
97222cc8 ED |
335 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
336 | { | |
dfb95954 | 337 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
338 | } |
339 | ||
a3e06bbe LJ |
340 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
341 | { | |
f30ebc31 | 342 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
343 | } |
344 | ||
97222cc8 ED |
345 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
346 | { | |
f30ebc31 | 347 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
348 | } |
349 | ||
350 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
351 | { | |
f30ebc31 | 352 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
353 | } |
354 | ||
cc6e462c JK |
355 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
356 | { | |
357 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
358 | } | |
359 | ||
fc61b800 GN |
360 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
361 | { | |
362 | struct kvm_lapic *apic = vcpu->arch.apic; | |
fc61b800 GN |
363 | u32 v = APIC_VERSION; |
364 | ||
bce87cce | 365 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
366 | return; |
367 | ||
0bcc3fb9 VK |
368 | /* |
369 | * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) | |
370 | * which doesn't have EOI register; Some buggy OSes (e.g. Windows with | |
371 | * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC | |
372 | * version first and level-triggered interrupts never get EOIed in | |
373 | * IOAPIC. | |
374 | */ | |
565b7820 | 375 | if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) && |
0bcc3fb9 | 376 | !ioapic_in_kernel(vcpu->kvm)) |
fc61b800 | 377 | v |= APIC_LVR_DIRECTED_EOI; |
1e6e2755 | 378 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
379 | } |
380 | ||
1e6e2755 | 381 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 382 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
383 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
384 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
385 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
386 | LVT_MASK /* LVTERR */ | |
387 | }; | |
388 | ||
389 | static int find_highest_vector(void *bitmap) | |
390 | { | |
ecba9a52 TY |
391 | int vec; |
392 | u32 *reg; | |
97222cc8 | 393 | |
ecba9a52 TY |
394 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
395 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
396 | reg = bitmap + REG_POS(vec); | |
397 | if (*reg) | |
810e6def | 398 | return __fls(*reg) + vec; |
ecba9a52 | 399 | } |
97222cc8 | 400 | |
ecba9a52 | 401 | return -1; |
97222cc8 ED |
402 | } |
403 | ||
8680b94b MT |
404 | static u8 count_vectors(void *bitmap) |
405 | { | |
ecba9a52 TY |
406 | int vec; |
407 | u32 *reg; | |
8680b94b | 408 | u8 count = 0; |
ecba9a52 TY |
409 | |
410 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
411 | reg = bitmap + REG_POS(vec); | |
412 | count += hweight32(*reg); | |
413 | } | |
414 | ||
8680b94b MT |
415 | return count; |
416 | } | |
417 | ||
e7387b0e | 418 | bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) |
a20ed54d | 419 | { |
810e6def | 420 | u32 i, vec; |
e7387b0e LA |
421 | u32 pir_val, irr_val, prev_irr_val; |
422 | int max_updated_irr; | |
423 | ||
424 | max_updated_irr = -1; | |
425 | *max_irr = -1; | |
a20ed54d | 426 | |
810e6def | 427 | for (i = vec = 0; i <= 7; i++, vec += 32) { |
ad361091 | 428 | pir_val = READ_ONCE(pir[i]); |
810e6def | 429 | irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10)); |
ad361091 | 430 | if (pir_val) { |
e7387b0e | 431 | prev_irr_val = irr_val; |
810e6def PB |
432 | irr_val |= xchg(&pir[i], 0); |
433 | *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val; | |
e7387b0e LA |
434 | if (prev_irr_val != irr_val) { |
435 | max_updated_irr = | |
436 | __fls(irr_val ^ prev_irr_val) + vec; | |
437 | } | |
ad361091 | 438 | } |
810e6def | 439 | if (irr_val) |
e7387b0e | 440 | *max_irr = __fls(irr_val) + vec; |
a20ed54d | 441 | } |
810e6def | 442 | |
e7387b0e LA |
443 | return ((max_updated_irr != -1) && |
444 | (max_updated_irr == *max_irr)); | |
a20ed54d | 445 | } |
705699a1 WV |
446 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
447 | ||
e7387b0e | 448 | bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr) |
705699a1 WV |
449 | { |
450 | struct kvm_lapic *apic = vcpu->arch.apic; | |
451 | ||
e7387b0e | 452 | return __kvm_apic_update_irr(pir, apic->regs, max_irr); |
705699a1 | 453 | } |
a20ed54d YZ |
454 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
455 | ||
33e4c686 | 456 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 457 | { |
33e4c686 | 458 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
459 | } |
460 | ||
461 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
462 | { | |
463 | int result; | |
464 | ||
c7c9c56c YZ |
465 | /* |
466 | * Note that irr_pending is just a hint. It will be always | |
467 | * true with virtual interrupt delivery enabled. | |
468 | */ | |
33e4c686 GN |
469 | if (!apic->irr_pending) |
470 | return -1; | |
471 | ||
472 | result = apic_search_irr(apic); | |
97222cc8 ED |
473 | ASSERT(result == -1 || result >= 16); |
474 | ||
475 | return result; | |
476 | } | |
477 | ||
33e4c686 GN |
478 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
479 | { | |
56cc2406 WL |
480 | struct kvm_vcpu *vcpu; |
481 | ||
482 | vcpu = apic->vcpu; | |
483 | ||
d62caabb | 484 | if (unlikely(vcpu->arch.apicv_active)) { |
b95234c8 | 485 | /* need to update RVI */ |
ee171d2f | 486 | kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); |
b3646477 | 487 | static_call(kvm_x86_hwapic_irr_update)(vcpu, |
b95234c8 | 488 | apic_find_highest_irr(apic)); |
f210f757 NA |
489 | } else { |
490 | apic->irr_pending = false; | |
ee171d2f | 491 | kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); |
f210f757 NA |
492 | if (apic_search_irr(apic) != -1) |
493 | apic->irr_pending = true; | |
56cc2406 | 494 | } |
33e4c686 GN |
495 | } |
496 | ||
25bb2cf9 SC |
497 | void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec) |
498 | { | |
499 | apic_clear_irr(vec, vcpu->arch.apic); | |
500 | } | |
501 | EXPORT_SYMBOL_GPL(kvm_apic_clear_irr); | |
502 | ||
8680b94b MT |
503 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
504 | { | |
56cc2406 WL |
505 | struct kvm_vcpu *vcpu; |
506 | ||
507 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
508 | return; | |
509 | ||
510 | vcpu = apic->vcpu; | |
fc57ac2c | 511 | |
8680b94b | 512 | /* |
56cc2406 WL |
513 | * With APIC virtualization enabled, all caching is disabled |
514 | * because the processor can modify ISR under the hood. Instead | |
515 | * just set SVI. | |
8680b94b | 516 | */ |
d62caabb | 517 | if (unlikely(vcpu->arch.apicv_active)) |
b3646477 | 518 | static_call(kvm_x86_hwapic_isr_update)(vcpu, vec); |
56cc2406 WL |
519 | else { |
520 | ++apic->isr_count; | |
521 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
522 | /* | |
523 | * ISR (in service register) bit is set when injecting an interrupt. | |
524 | * The highest vector is injected. Thus the latest bit set matches | |
525 | * the highest bit in ISR. | |
526 | */ | |
527 | apic->highest_isr_cache = vec; | |
528 | } | |
8680b94b MT |
529 | } |
530 | ||
fc57ac2c PB |
531 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
532 | { | |
533 | int result; | |
534 | ||
535 | /* | |
536 | * Note that isr_count is always 1, and highest_isr_cache | |
537 | * is always -1, with APIC virtualization enabled. | |
538 | */ | |
539 | if (!apic->isr_count) | |
540 | return -1; | |
541 | if (likely(apic->highest_isr_cache != -1)) | |
542 | return apic->highest_isr_cache; | |
543 | ||
544 | result = find_highest_vector(apic->regs + APIC_ISR); | |
545 | ASSERT(result == -1 || result >= 16); | |
546 | ||
547 | return result; | |
548 | } | |
549 | ||
8680b94b MT |
550 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
551 | { | |
fc57ac2c PB |
552 | struct kvm_vcpu *vcpu; |
553 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
554 | return; | |
555 | ||
556 | vcpu = apic->vcpu; | |
557 | ||
558 | /* | |
559 | * We do get here for APIC virtualization enabled if the guest | |
560 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
561 | * to trigger a new interrupt delivery by writing the SVI field; | |
562 | * on the other hand isr_count and highest_isr_cache are unused | |
563 | * and must be left alone. | |
564 | */ | |
d62caabb | 565 | if (unlikely(vcpu->arch.apicv_active)) |
b3646477 JB |
566 | static_call(kvm_x86_hwapic_isr_update)(vcpu, |
567 | apic_find_highest_isr(apic)); | |
fc57ac2c | 568 | else { |
8680b94b | 569 | --apic->isr_count; |
fc57ac2c PB |
570 | BUG_ON(apic->isr_count < 0); |
571 | apic->highest_isr_cache = -1; | |
572 | } | |
8680b94b MT |
573 | } |
574 | ||
6e5d865c YS |
575 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
576 | { | |
33e4c686 GN |
577 | /* This may race with setting of irr in __apic_accept_irq() and |
578 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
579 | * will cause vmexit immediately and the value will be recalculated | |
580 | * on the next vmentry. | |
581 | */ | |
f8543d6a | 582 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 583 | } |
76dfafd5 | 584 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); |
6e5d865c | 585 | |
6da7e3f6 | 586 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 587 | int vector, int level, int trig_mode, |
9e4aabe2 | 588 | struct dest_map *dest_map); |
6da7e3f6 | 589 | |
b4f2225c | 590 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 591 | struct dest_map *dest_map) |
97222cc8 | 592 | { |
ad312c7c | 593 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 594 | |
58c2dde1 | 595 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 596 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
597 | } |
598 | ||
1a686237 ML |
599 | static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map, |
600 | struct kvm_lapic_irq *irq, u32 min) | |
601 | { | |
602 | int i, count = 0; | |
603 | struct kvm_vcpu *vcpu; | |
604 | ||
605 | if (min > map->max_apic_id) | |
606 | return 0; | |
607 | ||
608 | for_each_set_bit(i, ipi_bitmap, | |
609 | min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { | |
610 | if (map->phys_map[min + i]) { | |
611 | vcpu = map->phys_map[min + i]->vcpu; | |
612 | count += kvm_apic_set_irq(vcpu, irq, NULL); | |
613 | } | |
614 | } | |
615 | ||
616 | return count; | |
617 | } | |
618 | ||
4180bf1b | 619 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 620 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
621 | unsigned long icr, int op_64_bit) |
622 | { | |
4180bf1b | 623 | struct kvm_apic_map *map; |
4180bf1b WL |
624 | struct kvm_lapic_irq irq = {0}; |
625 | int cluster_size = op_64_bit ? 64 : 32; | |
1a686237 ML |
626 | int count; |
627 | ||
628 | if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK)) | |
629 | return -KVM_EINVAL; | |
4180bf1b WL |
630 | |
631 | irq.vector = icr & APIC_VECTOR_MASK; | |
632 | irq.delivery_mode = icr & APIC_MODE_MASK; | |
633 | irq.level = (icr & APIC_INT_ASSERT) != 0; | |
634 | irq.trig_mode = icr & APIC_INT_LEVELTRIG; | |
635 | ||
4180bf1b WL |
636 | rcu_read_lock(); |
637 | map = rcu_dereference(kvm->arch.apic_map); | |
638 | ||
1a686237 ML |
639 | count = -EOPNOTSUPP; |
640 | if (likely(map)) { | |
641 | count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min); | |
642 | min += cluster_size; | |
643 | count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min); | |
4180bf1b WL |
644 | } |
645 | ||
646 | rcu_read_unlock(); | |
647 | return count; | |
648 | } | |
649 | ||
ae7a2a3f MT |
650 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
651 | { | |
4e335d9e PB |
652 | |
653 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
654 | sizeof(val)); | |
ae7a2a3f MT |
655 | } |
656 | ||
657 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
658 | { | |
4e335d9e PB |
659 | |
660 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
661 | sizeof(*val)); | |
ae7a2a3f MT |
662 | } |
663 | ||
664 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
665 | { | |
666 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
667 | } | |
668 | ||
669 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
670 | { | |
671 | u8 val; | |
23520b2d | 672 | if (pv_eoi_get_user(vcpu, &val) < 0) { |
0d88800d | 673 | printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n", |
96893977 | 674 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
23520b2d ML |
675 | return false; |
676 | } | |
de7860c8 | 677 | return val & KVM_PV_EOI_ENABLED; |
ae7a2a3f MT |
678 | } |
679 | ||
680 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
681 | { | |
682 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
0d88800d | 683 | printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n", |
96893977 | 684 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
685 | return; |
686 | } | |
687 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
688 | } | |
689 | ||
690 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
691 | { | |
692 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
0d88800d | 693 | printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n", |
96893977 | 694 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
695 | return; |
696 | } | |
697 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
698 | } | |
699 | ||
b3c045d3 PB |
700 | static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) |
701 | { | |
3d92789f | 702 | int highest_irr; |
fa59cc00 | 703 | if (apic->vcpu->arch.apicv_active) |
b3646477 | 704 | highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); |
76dfafd5 PB |
705 | else |
706 | highest_irr = apic_find_highest_irr(apic); | |
b3c045d3 PB |
707 | if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) |
708 | return -1; | |
709 | return highest_irr; | |
710 | } | |
711 | ||
712 | static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) | |
97222cc8 | 713 | { |
3842d135 | 714 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
715 | int isr; |
716 | ||
dfb95954 SS |
717 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
718 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
719 | isr = apic_find_highest_isr(apic); |
720 | isrv = (isr != -1) ? isr : 0; | |
721 | ||
722 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
723 | ppr = tpr & 0xff; | |
724 | else | |
725 | ppr = isrv & 0xf0; | |
726 | ||
b3c045d3 PB |
727 | *new_ppr = ppr; |
728 | if (old_ppr != ppr) | |
1e6e2755 | 729 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
b3c045d3 PB |
730 | |
731 | return ppr < old_ppr; | |
732 | } | |
733 | ||
734 | static void apic_update_ppr(struct kvm_lapic *apic) | |
735 | { | |
736 | u32 ppr; | |
737 | ||
26fbbee5 PB |
738 | if (__apic_update_ppr(apic, &ppr) && |
739 | apic_has_interrupt_for_ppr(apic, ppr) != -1) | |
b3c045d3 | 740 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
97222cc8 ED |
741 | } |
742 | ||
eb90f341 PB |
743 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu) |
744 | { | |
745 | apic_update_ppr(vcpu->arch.apic); | |
746 | } | |
747 | EXPORT_SYMBOL_GPL(kvm_apic_update_ppr); | |
748 | ||
97222cc8 ED |
749 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) |
750 | { | |
1e6e2755 | 751 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
752 | apic_update_ppr(apic); |
753 | } | |
754 | ||
03d2249e | 755 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 756 | { |
b4535b58 RK |
757 | return mda == (apic_x2apic_mode(apic) ? |
758 | X2APIC_BROADCAST : APIC_BROADCAST); | |
394457a9 NA |
759 | } |
760 | ||
03d2249e | 761 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 762 | { |
03d2249e RK |
763 | if (kvm_apic_broadcast(apic, mda)) |
764 | return true; | |
765 | ||
766 | if (apic_x2apic_mode(apic)) | |
6e500439 | 767 | return mda == kvm_x2apic_id(apic); |
03d2249e | 768 | |
5bd5db38 RK |
769 | /* |
770 | * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if | |
771 | * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and | |
772 | * this allows unique addressing of VCPUs with APIC ID over 0xff. | |
773 | * The 0xff condition is needed because writeable xAPIC ID. | |
774 | */ | |
775 | if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) | |
776 | return true; | |
777 | ||
b4535b58 | 778 | return mda == kvm_xapic_id(apic); |
97222cc8 ED |
779 | } |
780 | ||
52c233a4 | 781 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 782 | { |
0105d1a5 GN |
783 | u32 logical_id; |
784 | ||
394457a9 | 785 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 786 | return true; |
394457a9 | 787 | |
dfb95954 | 788 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 789 | |
9368b567 | 790 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
791 | return ((logical_id >> 16) == (mda >> 16)) |
792 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 793 | |
9368b567 | 794 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
97222cc8 | 795 | |
dfb95954 | 796 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 797 | case APIC_DFR_FLAT: |
9368b567 | 798 | return (logical_id & mda) != 0; |
97222cc8 | 799 | case APIC_DFR_CLUSTER: |
9368b567 RK |
800 | return ((logical_id >> 4) == (mda >> 4)) |
801 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 802 | default: |
9368b567 | 803 | return false; |
97222cc8 | 804 | } |
97222cc8 ED |
805 | } |
806 | ||
c519265f RK |
807 | /* The KVM local APIC implementation has two quirks: |
808 | * | |
b4535b58 RK |
809 | * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs |
810 | * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID. | |
811 | * KVM doesn't do that aliasing. | |
c519265f RK |
812 | * |
813 | * - in-kernel IOAPIC messages have to be delivered directly to | |
814 | * x2APIC, because the kernel does not support interrupt remapping. | |
815 | * In order to support broadcast without interrupt remapping, x2APIC | |
816 | * rewrites the destination of non-IPI messages from APIC_BROADCAST | |
817 | * to X2APIC_BROADCAST. | |
818 | * | |
819 | * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is | |
820 | * important when userspace wants to use x2APIC-format MSIs, because | |
821 | * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7". | |
03d2249e | 822 | */ |
c519265f RK |
823 | static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id, |
824 | struct kvm_lapic *source, struct kvm_lapic *target) | |
03d2249e RK |
825 | { |
826 | bool ipi = source != NULL; | |
03d2249e | 827 | |
c519265f | 828 | if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && |
b4535b58 | 829 | !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) |
03d2249e RK |
830 | return X2APIC_BROADCAST; |
831 | ||
b4535b58 | 832 | return dest_id; |
03d2249e RK |
833 | } |
834 | ||
52c233a4 | 835 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
5c69d5c1 | 836 | int shorthand, unsigned int dest, int dest_mode) |
97222cc8 | 837 | { |
ad312c7c | 838 | struct kvm_lapic *target = vcpu->arch.apic; |
c519265f | 839 | u32 mda = kvm_apic_mda(vcpu, dest, source, target); |
97222cc8 | 840 | |
bd371396 | 841 | ASSERT(target); |
5c69d5c1 | 842 | switch (shorthand) { |
97222cc8 | 843 | case APIC_DEST_NOSHORT: |
3697f302 | 844 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 845 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 846 | else |
03d2249e | 847 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 848 | case APIC_DEST_SELF: |
9368b567 | 849 | return target == source; |
97222cc8 | 850 | case APIC_DEST_ALLINC: |
9368b567 | 851 | return true; |
97222cc8 | 852 | case APIC_DEST_ALLBUT: |
9368b567 | 853 | return target != source; |
97222cc8 | 854 | default: |
9368b567 | 855 | return false; |
97222cc8 | 856 | } |
97222cc8 | 857 | } |
1e6e2755 | 858 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 859 | |
52004014 FW |
860 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
861 | const unsigned long *bitmap, u32 bitmap_size) | |
862 | { | |
863 | u32 mod; | |
864 | int i, idx = -1; | |
865 | ||
866 | mod = vector % dest_vcpus; | |
867 | ||
868 | for (i = 0; i <= mod; i++) { | |
869 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
870 | BUG_ON(idx == bitmap_size); | |
871 | } | |
872 | ||
873 | return idx; | |
874 | } | |
875 | ||
4efd805f RK |
876 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
877 | { | |
878 | if (!kvm->arch.disabled_lapic_found) { | |
879 | kvm->arch.disabled_lapic_found = true; | |
880 | printk(KERN_INFO | |
881 | "Disabled LAPIC found during irq injection\n"); | |
882 | } | |
883 | } | |
884 | ||
c519265f RK |
885 | static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src, |
886 | struct kvm_lapic_irq *irq, struct kvm_apic_map *map) | |
1e08ec4a | 887 | { |
c519265f RK |
888 | if (kvm->arch.x2apic_broadcast_quirk_disabled) { |
889 | if ((irq->dest_id == APIC_BROADCAST && | |
890 | map->mode != KVM_APIC_MODE_X2APIC)) | |
891 | return true; | |
892 | if (irq->dest_id == X2APIC_BROADCAST) | |
893 | return true; | |
894 | } else { | |
895 | bool x2apic_ipi = src && *src && apic_x2apic_mode(*src); | |
896 | if (irq->dest_id == (x2apic_ipi ? | |
897 | X2APIC_BROADCAST : APIC_BROADCAST)) | |
898 | return true; | |
899 | } | |
1e08ec4a | 900 | |
c519265f RK |
901 | return false; |
902 | } | |
1e08ec4a | 903 | |
64aa47bf RK |
904 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
905 | * for valid destinations in *dst array. | |
906 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
907 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
908 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
909 | * zero and *dst undefined. | |
910 | */ | |
911 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
912 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
913 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
914 | unsigned long *bitmap) | |
915 | { | |
916 | int i, lowest; | |
1e08ec4a | 917 | |
64aa47bf RK |
918 | if (irq->shorthand == APIC_DEST_SELF && src) { |
919 | *dst = src; | |
920 | *bitmap = 1; | |
921 | return true; | |
922 | } else if (irq->shorthand) | |
1e08ec4a GN |
923 | return false; |
924 | ||
c519265f | 925 | if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map)) |
9ea369b0 RK |
926 | return false; |
927 | ||
64aa47bf | 928 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
0ca52e7b | 929 | if (irq->dest_id > map->max_apic_id) { |
64aa47bf RK |
930 | *bitmap = 0; |
931 | } else { | |
1d487e9b PB |
932 | u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1); |
933 | *dst = &map->phys_map[dest_id]; | |
64aa47bf RK |
934 | *bitmap = 1; |
935 | } | |
1e08ec4a | 936 | return true; |
bea15428 | 937 | } |
698f9755 | 938 | |
e45115b6 RK |
939 | *bitmap = 0; |
940 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
941 | (u16 *)bitmap)) | |
1e08ec4a | 942 | return false; |
fa834e91 | 943 | |
64aa47bf RK |
944 | if (!kvm_lowest_prio_delivery(irq)) |
945 | return true; | |
3548a259 | 946 | |
64aa47bf RK |
947 | if (!kvm_vector_hashing_enabled()) { |
948 | lowest = -1; | |
949 | for_each_set_bit(i, bitmap, 16) { | |
950 | if (!(*dst)[i]) | |
951 | continue; | |
952 | if (lowest < 0) | |
953 | lowest = i; | |
954 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
955 | (*dst)[lowest]->vcpu) < 0) | |
956 | lowest = i; | |
3548a259 | 957 | } |
64aa47bf RK |
958 | } else { |
959 | if (!*bitmap) | |
960 | return true; | |
3548a259 | 961 | |
64aa47bf RK |
962 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
963 | bitmap, 16); | |
45c3094a | 964 | |
64aa47bf RK |
965 | if (!(*dst)[lowest]) { |
966 | kvm_apic_disabled_lapic_found(kvm); | |
967 | *bitmap = 0; | |
968 | return true; | |
969 | } | |
970 | } | |
1e08ec4a | 971 | |
64aa47bf | 972 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 973 | |
64aa47bf RK |
974 | return true; |
975 | } | |
52004014 | 976 | |
64aa47bf RK |
977 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
978 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
979 | { | |
980 | struct kvm_apic_map *map; | |
981 | unsigned long bitmap; | |
982 | struct kvm_lapic **dst = NULL; | |
983 | int i; | |
984 | bool ret; | |
52004014 | 985 | |
64aa47bf | 986 | *r = -1; |
52004014 | 987 | |
64aa47bf RK |
988 | if (irq->shorthand == APIC_DEST_SELF) { |
989 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
990 | return true; | |
991 | } | |
52004014 | 992 | |
64aa47bf RK |
993 | rcu_read_lock(); |
994 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 995 | |
64aa47bf | 996 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
0624fca9 PB |
997 | if (ret) { |
998 | *r = 0; | |
64aa47bf RK |
999 | for_each_set_bit(i, &bitmap, 16) { |
1000 | if (!dst[i]) | |
1001 | continue; | |
64aa47bf | 1002 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 1003 | } |
0624fca9 | 1004 | } |
1e08ec4a | 1005 | |
1e08ec4a GN |
1006 | rcu_read_unlock(); |
1007 | return ret; | |
1008 | } | |
1009 | ||
6228a0da | 1010 | /* |
00116795 | 1011 | * This routine tries to handle interrupts in posted mode, here is how |
6228a0da FW |
1012 | * it deals with different cases: |
1013 | * - For single-destination interrupts, handle it in posted mode | |
1014 | * - Else if vector hashing is enabled and it is a lowest-priority | |
1015 | * interrupt, handle it in posted mode and use the following mechanism | |
67b0ae43 | 1016 | * to find the destination vCPU. |
6228a0da FW |
1017 | * 1. For lowest-priority interrupts, store all the possible |
1018 | * destination vCPUs in an array. | |
1019 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
1020 | * the right destination vCPU in the array for the lowest-priority | |
1021 | * interrupt. | |
1022 | * - Otherwise, use remapped mode to inject the interrupt. | |
1023 | */ | |
8feb4a04 FW |
1024 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1025 | struct kvm_vcpu **dest_vcpu) | |
1026 | { | |
1027 | struct kvm_apic_map *map; | |
64aa47bf RK |
1028 | unsigned long bitmap; |
1029 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 1030 | bool ret = false; |
8feb4a04 FW |
1031 | |
1032 | if (irq->shorthand) | |
1033 | return false; | |
1034 | ||
1035 | rcu_read_lock(); | |
1036 | map = rcu_dereference(kvm->arch.apic_map); | |
1037 | ||
64aa47bf RK |
1038 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
1039 | hweight16(bitmap) == 1) { | |
1040 | unsigned long i = find_first_bit(&bitmap, 16); | |
6228a0da | 1041 | |
64aa47bf RK |
1042 | if (dst[i]) { |
1043 | *dest_vcpu = dst[i]->vcpu; | |
1044 | ret = true; | |
6228a0da | 1045 | } |
8feb4a04 FW |
1046 | } |
1047 | ||
8feb4a04 FW |
1048 | rcu_read_unlock(); |
1049 | return ret; | |
1050 | } | |
1051 | ||
97222cc8 ED |
1052 | /* |
1053 | * Add a pending IRQ into lapic. | |
1054 | * Return 1 if successfully added and 0 if discarded. | |
1055 | */ | |
1056 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 1057 | int vector, int level, int trig_mode, |
9e4aabe2 | 1058 | struct dest_map *dest_map) |
97222cc8 | 1059 | { |
6da7e3f6 | 1060 | int result = 0; |
c5ec1534 | 1061 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 1062 | |
a183b638 PB |
1063 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
1064 | trig_mode, vector); | |
97222cc8 | 1065 | switch (delivery_mode) { |
97222cc8 | 1066 | case APIC_DM_LOWEST: |
e1035715 | 1067 | vcpu->arch.apic_arb_prio++; |
df561f66 | 1068 | fallthrough; |
e1035715 | 1069 | case APIC_DM_FIXED: |
bdaffe1d PB |
1070 | if (unlikely(trig_mode && !level)) |
1071 | break; | |
1072 | ||
97222cc8 ED |
1073 | /* FIXME add logic for vcpu on reset */ |
1074 | if (unlikely(!apic_enabled(apic))) | |
1075 | break; | |
1076 | ||
11f5cc05 JK |
1077 | result = 1; |
1078 | ||
9daa5007 | 1079 | if (dest_map) { |
9e4aabe2 | 1080 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
1081 | dest_map->vectors[vcpu->vcpu_id] = vector; |
1082 | } | |
a5d36f82 | 1083 | |
bdaffe1d PB |
1084 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
1085 | if (trig_mode) | |
ee171d2f WY |
1086 | kvm_lapic_set_vector(vector, |
1087 | apic->regs + APIC_TMR); | |
bdaffe1d | 1088 | else |
ee171d2f WY |
1089 | kvm_lapic_clear_vector(vector, |
1090 | apic->regs + APIC_TMR); | |
bdaffe1d PB |
1091 | } |
1092 | ||
b3646477 | 1093 | if (static_call(kvm_x86_deliver_posted_interrupt)(vcpu, vector)) { |
1e6e2755 | 1094 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
1095 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
1096 | kvm_vcpu_kick(vcpu); | |
1097 | } | |
97222cc8 ED |
1098 | break; |
1099 | ||
1100 | case APIC_DM_REMRD: | |
24d2166b R |
1101 | result = 1; |
1102 | vcpu->arch.pv.pv_unhalted = 1; | |
1103 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1104 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1105 | break; |
1106 | ||
1107 | case APIC_DM_SMI: | |
64d60670 PB |
1108 | result = 1; |
1109 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
1110 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 1111 | break; |
3419ffc8 | 1112 | |
97222cc8 | 1113 | case APIC_DM_NMI: |
6da7e3f6 | 1114 | result = 1; |
3419ffc8 | 1115 | kvm_inject_nmi(vcpu); |
26df99c6 | 1116 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
1117 | break; |
1118 | ||
1119 | case APIC_DM_INIT: | |
a52315e1 | 1120 | if (!trig_mode || level) { |
6da7e3f6 | 1121 | result = 1; |
66450a21 JK |
1122 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
1123 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
3842d135 | 1124 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 | 1125 | kvm_vcpu_kick(vcpu); |
c5ec1534 | 1126 | } |
97222cc8 ED |
1127 | break; |
1128 | ||
1129 | case APIC_DM_STARTUP: | |
66450a21 JK |
1130 | result = 1; |
1131 | apic->sipi_vector = vector; | |
1132 | /* make sure sipi_vector is visible for the receiver */ | |
1133 | smp_wmb(); | |
1134 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
1135 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1136 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1137 | break; |
1138 | ||
23930f95 JK |
1139 | case APIC_DM_EXTINT: |
1140 | /* | |
1141 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
1142 | * before NMI watchdog was enabled. Already handled by | |
1143 | * kvm_apic_accept_pic_intr(). | |
1144 | */ | |
1145 | break; | |
1146 | ||
97222cc8 ED |
1147 | default: |
1148 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
1149 | delivery_mode); | |
1150 | break; | |
1151 | } | |
1152 | return result; | |
1153 | } | |
1154 | ||
7ee30bc1 NNL |
1155 | /* |
1156 | * This routine identifies the destination vcpus mask meant to receive the | |
1157 | * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find | |
1158 | * out the destination vcpus array and set the bitmap or it traverses to | |
1159 | * each available vcpu to identify the same. | |
1160 | */ | |
1161 | void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, | |
1162 | unsigned long *vcpu_bitmap) | |
1163 | { | |
1164 | struct kvm_lapic **dest_vcpu = NULL; | |
1165 | struct kvm_lapic *src = NULL; | |
1166 | struct kvm_apic_map *map; | |
1167 | struct kvm_vcpu *vcpu; | |
1168 | unsigned long bitmap; | |
1169 | int i, vcpu_idx; | |
1170 | bool ret; | |
1171 | ||
1172 | rcu_read_lock(); | |
1173 | map = rcu_dereference(kvm->arch.apic_map); | |
1174 | ||
1175 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu, | |
1176 | &bitmap); | |
1177 | if (ret) { | |
1178 | for_each_set_bit(i, &bitmap, 16) { | |
1179 | if (!dest_vcpu[i]) | |
1180 | continue; | |
1181 | vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx; | |
1182 | __set_bit(vcpu_idx, vcpu_bitmap); | |
1183 | } | |
1184 | } else { | |
1185 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1186 | if (!kvm_apic_present(vcpu)) | |
1187 | continue; | |
1188 | if (!kvm_apic_match_dest(vcpu, NULL, | |
b4b29636 | 1189 | irq->shorthand, |
7ee30bc1 NNL |
1190 | irq->dest_id, |
1191 | irq->dest_mode)) | |
1192 | continue; | |
1193 | __set_bit(i, vcpu_bitmap); | |
1194 | } | |
1195 | } | |
1196 | rcu_read_unlock(); | |
1197 | } | |
1198 | ||
e1035715 | 1199 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 1200 | { |
e1035715 | 1201 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
1202 | } |
1203 | ||
3bb345f3 PB |
1204 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
1205 | { | |
6308630b | 1206 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
1207 | } |
1208 | ||
c7c9c56c YZ |
1209 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
1210 | { | |
7543a635 SR |
1211 | int trigger_mode; |
1212 | ||
1213 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
1214 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
1215 | return; | |
3bb345f3 | 1216 | |
7543a635 SR |
1217 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
1218 | if (irqchip_split(apic->vcpu->kvm)) { | |
1219 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
1220 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
1221 | return; | |
c7c9c56c | 1222 | } |
7543a635 SR |
1223 | |
1224 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
1225 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
1226 | else | |
1227 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1228 | ||
1229 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
1230 | } |
1231 | ||
ae7a2a3f | 1232 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
1233 | { |
1234 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
1235 | |
1236 | trace_kvm_eoi(apic, vector); | |
1237 | ||
97222cc8 ED |
1238 | /* |
1239 | * Not every write EOI will has corresponding ISR, | |
1240 | * one example is when Kernel check timer on setup_IO_APIC | |
1241 | */ | |
1242 | if (vector == -1) | |
ae7a2a3f | 1243 | return vector; |
97222cc8 | 1244 | |
8680b94b | 1245 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1246 | apic_update_ppr(apic); |
1247 | ||
f2bc14b6 VK |
1248 | if (to_hv_vcpu(apic->vcpu) && |
1249 | test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) | |
5c919412 AS |
1250 | kvm_hv_synic_send_eoi(apic->vcpu, vector); |
1251 | ||
c7c9c56c | 1252 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1253 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1254 | return vector; |
97222cc8 ED |
1255 | } |
1256 | ||
c7c9c56c YZ |
1257 | /* |
1258 | * this interface assumes a trap-like exit, which has already finished | |
1259 | * desired side effect including vISR and vPPR update. | |
1260 | */ | |
1261 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1262 | { | |
1263 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1264 | ||
1265 | trace_kvm_eoi(apic, vector); | |
1266 | ||
1267 | kvm_ioapic_send_eoi(apic, vector); | |
1268 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1269 | } | |
1270 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1271 | ||
d5361678 | 1272 | void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) |
97222cc8 | 1273 | { |
58c2dde1 | 1274 | struct kvm_lapic_irq irq; |
97222cc8 | 1275 | |
58c2dde1 GN |
1276 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1277 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1278 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1279 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1280 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1281 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1282 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1283 | if (apic_x2apic_mode(apic)) |
1284 | irq.dest_id = icr_high; | |
1285 | else | |
1286 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1287 | |
1000ff8d GN |
1288 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1289 | ||
b4f2225c | 1290 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1291 | } |
1292 | ||
1293 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1294 | { | |
8003c9ae | 1295 | ktime_t remaining, now; |
b682b814 | 1296 | s64 ns; |
9da8f4e8 | 1297 | u32 tmcct; |
97222cc8 ED |
1298 | |
1299 | ASSERT(apic != NULL); | |
1300 | ||
9da8f4e8 | 1301 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1302 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1303 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1304 | return 0; |
1305 | ||
5587859f | 1306 | now = ktime_get(); |
8003c9ae | 1307 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); |
b682b814 | 1308 | if (ktime_to_ns(remaining) < 0) |
8b0e1953 | 1309 | remaining = 0; |
b682b814 | 1310 | |
d3c7b77d MT |
1311 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1312 | tmcct = div64_u64(ns, | |
1313 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1314 | |
1315 | return tmcct; | |
1316 | } | |
1317 | ||
b209749f AK |
1318 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1319 | { | |
1320 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1321 | struct kvm_run *run = vcpu->run; | |
1322 | ||
a8eeb04a | 1323 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1324 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1325 | run->tpr_access.is_write = write; |
1326 | } | |
1327 | ||
1328 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1329 | { | |
1330 | if (apic->vcpu->arch.tpr_access_reporting) | |
1331 | __report_tpr_access(apic, write); | |
1332 | } | |
1333 | ||
97222cc8 ED |
1334 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1335 | { | |
1336 | u32 val = 0; | |
1337 | ||
1338 | if (offset >= LAPIC_MMIO_LENGTH) | |
1339 | return 0; | |
1340 | ||
1341 | switch (offset) { | |
1342 | case APIC_ARBPRI: | |
97222cc8 ED |
1343 | break; |
1344 | ||
1345 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1346 | if (apic_lvtt_tscdeadline(apic)) |
1347 | return 0; | |
1348 | ||
97222cc8 ED |
1349 | val = apic_get_tmcct(apic); |
1350 | break; | |
4a4541a4 AK |
1351 | case APIC_PROCPRI: |
1352 | apic_update_ppr(apic); | |
dfb95954 | 1353 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1354 | break; |
b209749f AK |
1355 | case APIC_TASKPRI: |
1356 | report_tpr_access(apic, false); | |
df561f66 | 1357 | fallthrough; |
97222cc8 | 1358 | default: |
dfb95954 | 1359 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1360 | break; |
1361 | } | |
1362 | ||
1363 | return val; | |
1364 | } | |
1365 | ||
d76685c4 GH |
1366 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1367 | { | |
1368 | return container_of(dev, struct kvm_lapic, dev); | |
1369 | } | |
1370 | ||
01402cf8 PB |
1371 | #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4)) |
1372 | #define APIC_REGS_MASK(first, count) \ | |
1373 | (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) | |
1374 | ||
1e6e2755 | 1375 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1376 | void *data) |
97222cc8 | 1377 | { |
97222cc8 ED |
1378 | unsigned char alignment = offset & 0xf; |
1379 | u32 result; | |
d5b0b5b1 | 1380 | /* this bitmask has a bit cleared for each reserved register */ |
01402cf8 PB |
1381 | u64 valid_reg_mask = |
1382 | APIC_REG_MASK(APIC_ID) | | |
1383 | APIC_REG_MASK(APIC_LVR) | | |
1384 | APIC_REG_MASK(APIC_TASKPRI) | | |
1385 | APIC_REG_MASK(APIC_PROCPRI) | | |
1386 | APIC_REG_MASK(APIC_LDR) | | |
1387 | APIC_REG_MASK(APIC_DFR) | | |
1388 | APIC_REG_MASK(APIC_SPIV) | | |
1389 | APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) | | |
1390 | APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) | | |
1391 | APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) | | |
1392 | APIC_REG_MASK(APIC_ESR) | | |
1393 | APIC_REG_MASK(APIC_ICR) | | |
1394 | APIC_REG_MASK(APIC_ICR2) | | |
1395 | APIC_REG_MASK(APIC_LVTT) | | |
1396 | APIC_REG_MASK(APIC_LVTTHMR) | | |
1397 | APIC_REG_MASK(APIC_LVTPC) | | |
1398 | APIC_REG_MASK(APIC_LVT0) | | |
1399 | APIC_REG_MASK(APIC_LVT1) | | |
1400 | APIC_REG_MASK(APIC_LVTERR) | | |
1401 | APIC_REG_MASK(APIC_TMICT) | | |
1402 | APIC_REG_MASK(APIC_TMCCT) | | |
1403 | APIC_REG_MASK(APIC_TDCR); | |
1404 | ||
1405 | /* ARBPRI is not valid on x2APIC */ | |
1406 | if (!apic_x2apic_mode(apic)) | |
1407 | valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI); | |
0105d1a5 | 1408 | |
0d88800d | 1409 | if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) |
0105d1a5 | 1410 | return 1; |
0105d1a5 | 1411 | |
97222cc8 ED |
1412 | result = __apic_read(apic, offset & ~0xf); |
1413 | ||
229456fc MT |
1414 | trace_kvm_apic_read(offset, result); |
1415 | ||
97222cc8 ED |
1416 | switch (len) { |
1417 | case 1: | |
1418 | case 2: | |
1419 | case 4: | |
1420 | memcpy(data, (char *)&result + alignment, len); | |
1421 | break; | |
1422 | default: | |
1423 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1424 | "should be 1,2, or 4 instead\n", len); | |
1425 | break; | |
1426 | } | |
bda9020e | 1427 | return 0; |
97222cc8 | 1428 | } |
1e6e2755 | 1429 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1430 | |
0105d1a5 GN |
1431 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1432 | { | |
d1766202 VK |
1433 | return addr >= apic->base_address && |
1434 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
0105d1a5 GN |
1435 | } |
1436 | ||
e32edf4f | 1437 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1438 | gpa_t address, int len, void *data) |
1439 | { | |
1440 | struct kvm_lapic *apic = to_lapic(this); | |
1441 | u32 offset = address - apic->base_address; | |
1442 | ||
1443 | if (!apic_mmio_in_range(apic, address)) | |
1444 | return -EOPNOTSUPP; | |
1445 | ||
d1766202 VK |
1446 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
1447 | if (!kvm_check_has_quirk(vcpu->kvm, | |
1448 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
1449 | return -EOPNOTSUPP; | |
1450 | ||
1451 | memset(data, 0xff, len); | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1e6e2755 | 1455 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | ||
97222cc8 ED |
1460 | static void update_divide_count(struct kvm_lapic *apic) |
1461 | { | |
1462 | u32 tmp1, tmp2, tdcr; | |
1463 | ||
dfb95954 | 1464 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1465 | tmp1 = tdcr & 0xf; |
1466 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1467 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1468 | } |
1469 | ||
ccbfa1d3 WL |
1470 | static void limit_periodic_timer_frequency(struct kvm_lapic *apic) |
1471 | { | |
1472 | /* | |
1473 | * Do not allow the guest to program periodic timers with small | |
1474 | * interval, since the hrtimers are not throttled by the host | |
1475 | * scheduler. | |
1476 | */ | |
dedf9c5e | 1477 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { |
ccbfa1d3 WL |
1478 | s64 min_period = min_timer_period_us * 1000LL; |
1479 | ||
1480 | if (apic->lapic_timer.period < min_period) { | |
1481 | pr_info_ratelimited( | |
1482 | "kvm: vcpu %i: requested %lld ns " | |
1483 | "lapic timer period limited to %lld ns\n", | |
1484 | apic->vcpu->vcpu_id, | |
1485 | apic->lapic_timer.period, min_period); | |
1486 | apic->lapic_timer.period = min_period; | |
1487 | } | |
1488 | } | |
1489 | } | |
1490 | ||
94be4b85 WL |
1491 | static void cancel_hv_timer(struct kvm_lapic *apic); |
1492 | ||
b6ac0695 RK |
1493 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1494 | { | |
dfb95954 | 1495 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1496 | apic->lapic_timer.timer_mode_mask; |
1497 | ||
1498 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
c69518c8 | 1499 | if (apic_lvtt_tscdeadline(apic) != (timer_mode == |
dedf9c5e | 1500 | APIC_LVT_TIMER_TSCDEADLINE)) { |
dedf9c5e | 1501 | hrtimer_cancel(&apic->lapic_timer.timer); |
94be4b85 WL |
1502 | preempt_disable(); |
1503 | if (apic->lapic_timer.hv_timer_in_use) | |
1504 | cancel_hv_timer(apic); | |
1505 | preempt_enable(); | |
44275932 RK |
1506 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); |
1507 | apic->lapic_timer.period = 0; | |
1508 | apic->lapic_timer.tscdeadline = 0; | |
dedf9c5e | 1509 | } |
b6ac0695 | 1510 | apic->lapic_timer.timer_mode = timer_mode; |
dedf9c5e | 1511 | limit_periodic_timer_frequency(apic); |
b6ac0695 RK |
1512 | } |
1513 | } | |
1514 | ||
d0659d94 MT |
1515 | /* |
1516 | * On APICv, this test will cause a busy wait | |
1517 | * during a higher-priority task. | |
1518 | */ | |
1519 | ||
1520 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1521 | { | |
1522 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1523 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1524 | |
1525 | if (kvm_apic_hw_enabled(apic)) { | |
1526 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1527 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1528 | |
d62caabb | 1529 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1530 | bitmap = apic->regs + APIC_IRR; |
1531 | ||
1532 | if (apic_test_vector(vec, bitmap)) | |
1533 | return true; | |
d0659d94 MT |
1534 | } |
1535 | return false; | |
1536 | } | |
1537 | ||
b6aa57c6 SC |
1538 | static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles) |
1539 | { | |
1540 | u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; | |
1541 | ||
1542 | /* | |
1543 | * If the guest TSC is running at a different ratio than the host, then | |
1544 | * convert the delay to nanoseconds to achieve an accurate delay. Note | |
1545 | * that __delay() uses delay_tsc whenever the hardware has TSC, thus | |
1546 | * always for VMX enabled hardware. | |
1547 | */ | |
1548 | if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) { | |
1549 | __delay(min(guest_cycles, | |
1550 | nsec_to_cycles(vcpu, timer_advance_ns))); | |
1551 | } else { | |
1552 | u64 delay_ns = guest_cycles * 1000000ULL; | |
1553 | do_div(delay_ns, vcpu->arch.virtual_tsc_khz); | |
1554 | ndelay(min_t(u32, delay_ns, timer_advance_ns)); | |
1555 | } | |
1556 | } | |
1557 | ||
84ea3aca | 1558 | static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu, |
ec0671d5 | 1559 | s64 advance_expire_delta) |
d0659d94 MT |
1560 | { |
1561 | struct kvm_lapic *apic = vcpu->arch.apic; | |
39497d76 | 1562 | u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; |
84ea3aca WL |
1563 | u64 ns; |
1564 | ||
d0f5a86a WL |
1565 | /* Do not adjust for tiny fluctuations or large random spikes. */ |
1566 | if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX || | |
1567 | abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN) | |
1568 | return; | |
1569 | ||
84ea3aca | 1570 | /* too early */ |
ec0671d5 WL |
1571 | if (advance_expire_delta < 0) { |
1572 | ns = -advance_expire_delta * 1000000ULL; | |
84ea3aca | 1573 | do_div(ns, vcpu->arch.virtual_tsc_khz); |
d0f5a86a | 1574 | timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; |
84ea3aca WL |
1575 | } else { |
1576 | /* too late */ | |
ec0671d5 | 1577 | ns = advance_expire_delta * 1000000ULL; |
84ea3aca | 1578 | do_div(ns, vcpu->arch.virtual_tsc_khz); |
d0f5a86a | 1579 | timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; |
84ea3aca WL |
1580 | } |
1581 | ||
a0f0037e WL |
1582 | if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX)) |
1583 | timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; | |
84ea3aca WL |
1584 | apic->lapic_timer.timer_advance_ns = timer_advance_ns; |
1585 | } | |
1586 | ||
0c5f81da | 1587 | static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) |
84ea3aca WL |
1588 | { |
1589 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1590 | u64 guest_tsc, tsc_deadline; | |
d0659d94 | 1591 | |
d0659d94 MT |
1592 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; |
1593 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1594 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
ec0671d5 | 1595 | apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline; |
d0659d94 | 1596 | |
d0659d94 | 1597 | if (guest_tsc < tsc_deadline) |
b6aa57c6 | 1598 | __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc); |
3b8a5df6 | 1599 | |
d0f5a86a | 1600 | if (lapic_timer_advance_dynamic) |
ec0671d5 | 1601 | adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta); |
5d87db71 | 1602 | } |
0c5f81da WL |
1603 | |
1604 | void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1605 | { | |
010fd37f WL |
1606 | if (lapic_in_kernel(vcpu) && |
1607 | vcpu->arch.apic->lapic_timer.expired_tscdeadline && | |
1608 | vcpu->arch.apic->lapic_timer.timer_advance_ns && | |
1609 | lapic_timer_int_injected(vcpu)) | |
0c5f81da WL |
1610 | __kvm_wait_lapic_expire(vcpu); |
1611 | } | |
b6c4bc65 | 1612 | EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire); |
5d87db71 | 1613 | |
0c5f81da WL |
1614 | static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) |
1615 | { | |
1616 | struct kvm_timer *ktimer = &apic->lapic_timer; | |
1617 | ||
1618 | kvm_apic_local_deliver(apic, APIC_LVTT); | |
17ac43a8 | 1619 | if (apic_lvtt_tscdeadline(apic)) { |
0c5f81da | 1620 | ktimer->tscdeadline = 0; |
17ac43a8 | 1621 | } else if (apic_lvtt_oneshot(apic)) { |
0c5f81da WL |
1622 | ktimer->tscdeadline = 0; |
1623 | ktimer->target_expiration = 0; | |
1624 | } | |
1625 | } | |
1626 | ||
ae95f566 | 1627 | static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) |
0c5f81da WL |
1628 | { |
1629 | struct kvm_vcpu *vcpu = apic->vcpu; | |
0c5f81da WL |
1630 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1631 | ||
1632 | if (atomic_read(&apic->lapic_timer.pending)) | |
1633 | return; | |
1634 | ||
1635 | if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) | |
1636 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1637 | ||
ae95f566 WL |
1638 | if (!from_timer_fn && vcpu->arch.apicv_active) { |
1639 | WARN_ON(kvm_get_running_vcpu() != vcpu); | |
1640 | kvm_apic_inject_pending_timer_irqs(apic); | |
1641 | return; | |
1642 | } | |
1643 | ||
0c5f81da | 1644 | if (kvm_use_posted_timer_interrupt(apic->vcpu)) { |
beda4301 SC |
1645 | /* |
1646 | * Ensure the guest's timer has truly expired before posting an | |
1647 | * interrupt. Open code the relevant checks to avoid querying | |
1648 | * lapic_timer_int_injected(), which will be false since the | |
1649 | * interrupt isn't yet injected. Waiting until after injecting | |
1650 | * is not an option since that won't help a posted interrupt. | |
1651 | */ | |
1652 | if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && | |
1653 | vcpu->arch.apic->lapic_timer.timer_advance_ns) | |
1654 | __kvm_wait_lapic_expire(vcpu); | |
0c5f81da WL |
1655 | kvm_apic_inject_pending_timer_irqs(apic); |
1656 | return; | |
1657 | } | |
1658 | ||
1659 | atomic_inc(&apic->lapic_timer.pending); | |
68ca7663 WL |
1660 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); |
1661 | if (from_timer_fn) | |
1662 | kvm_vcpu_kick(vcpu); | |
0c5f81da WL |
1663 | } |
1664 | ||
53f9eedf YJ |
1665 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1666 | { | |
39497d76 SC |
1667 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1668 | u64 guest_tsc, tscdeadline = ktimer->tscdeadline; | |
53f9eedf YJ |
1669 | u64 ns = 0; |
1670 | ktime_t expire; | |
1671 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1672 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1673 | unsigned long flags; | |
1674 | ktime_t now; | |
1675 | ||
1676 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1677 | return; | |
1678 | ||
1679 | local_irq_save(flags); | |
1680 | ||
5587859f | 1681 | now = ktime_get(); |
53f9eedf | 1682 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
c09d65d9 LA |
1683 | |
1684 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1685 | do_div(ns, this_tsc_khz); | |
1686 | ||
1687 | if (likely(tscdeadline > guest_tsc) && | |
39497d76 | 1688 | likely(ns > apic->lapic_timer.timer_advance_ns)) { |
53f9eedf | 1689 | expire = ktime_add_ns(now, ns); |
39497d76 | 1690 | expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); |
2c0d278f | 1691 | hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD); |
53f9eedf | 1692 | } else |
ae95f566 | 1693 | apic_timer_expired(apic, false); |
53f9eedf YJ |
1694 | |
1695 | local_irq_restore(flags); | |
1696 | } | |
1697 | ||
24647e0a PS |
1698 | static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict) |
1699 | { | |
1700 | return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; | |
1701 | } | |
1702 | ||
c301b909 WL |
1703 | static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) |
1704 | { | |
1705 | ktime_t now, remaining; | |
1706 | u64 ns_remaining_old, ns_remaining_new; | |
1707 | ||
24647e0a PS |
1708 | apic->lapic_timer.period = |
1709 | tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); | |
c301b909 WL |
1710 | limit_periodic_timer_frequency(apic); |
1711 | ||
1712 | now = ktime_get(); | |
1713 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); | |
1714 | if (ktime_to_ns(remaining) < 0) | |
1715 | remaining = 0; | |
1716 | ||
1717 | ns_remaining_old = ktime_to_ns(remaining); | |
1718 | ns_remaining_new = mul_u64_u32_div(ns_remaining_old, | |
1719 | apic->divide_count, old_divisor); | |
1720 | ||
1721 | apic->lapic_timer.tscdeadline += | |
1722 | nsec_to_cycles(apic->vcpu, ns_remaining_new) - | |
1723 | nsec_to_cycles(apic->vcpu, ns_remaining_old); | |
1724 | apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); | |
1725 | } | |
1726 | ||
24647e0a | 1727 | static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg) |
7d7f7da2 WL |
1728 | { |
1729 | ktime_t now; | |
8003c9ae | 1730 | u64 tscl = rdtsc(); |
24647e0a | 1731 | s64 deadline; |
7d7f7da2 | 1732 | |
5587859f | 1733 | now = ktime_get(); |
24647e0a PS |
1734 | apic->lapic_timer.period = |
1735 | tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); | |
7d7f7da2 | 1736 | |
5d74a699 RK |
1737 | if (!apic->lapic_timer.period) { |
1738 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae | 1739 | return false; |
7d7f7da2 WL |
1740 | } |
1741 | ||
ccbfa1d3 | 1742 | limit_periodic_timer_frequency(apic); |
24647e0a PS |
1743 | deadline = apic->lapic_timer.period; |
1744 | ||
1745 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { | |
1746 | if (unlikely(count_reg != APIC_TMICT)) { | |
1747 | deadline = tmict_to_ns(apic, | |
1748 | kvm_lapic_get_reg(apic, count_reg)); | |
1749 | if (unlikely(deadline <= 0)) | |
1750 | deadline = apic->lapic_timer.period; | |
1751 | else if (unlikely(deadline > apic->lapic_timer.period)) { | |
1752 | pr_info_ratelimited( | |
1753 | "kvm: vcpu %i: requested lapic timer restore with " | |
1754 | "starting count register %#x=%u (%lld ns) > initial count (%lld ns). " | |
1755 | "Using initial count to start timer.\n", | |
1756 | apic->vcpu->vcpu_id, | |
1757 | count_reg, | |
1758 | kvm_lapic_get_reg(apic, count_reg), | |
1759 | deadline, apic->lapic_timer.period); | |
1760 | kvm_lapic_set_reg(apic, count_reg, 0); | |
1761 | deadline = apic->lapic_timer.period; | |
1762 | } | |
1763 | } | |
1764 | } | |
7d7f7da2 | 1765 | |
8003c9ae | 1766 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + |
24647e0a PS |
1767 | nsec_to_cycles(apic->vcpu, deadline); |
1768 | apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); | |
8003c9ae WL |
1769 | |
1770 | return true; | |
1771 | } | |
1772 | ||
1773 | static void advance_periodic_target_expiration(struct kvm_lapic *apic) | |
1774 | { | |
d8f2f498 DV |
1775 | ktime_t now = ktime_get(); |
1776 | u64 tscl = rdtsc(); | |
1777 | ktime_t delta; | |
1778 | ||
1779 | /* | |
1780 | * Synchronize both deadlines to the same time source or | |
1781 | * differences in the periods (caused by differences in the | |
1782 | * underlying clocks or numerical approximation errors) will | |
1783 | * cause the two to drift apart over time as the errors | |
1784 | * accumulate. | |
1785 | */ | |
8003c9ae WL |
1786 | apic->lapic_timer.target_expiration = |
1787 | ktime_add_ns(apic->lapic_timer.target_expiration, | |
1788 | apic->lapic_timer.period); | |
d8f2f498 DV |
1789 | delta = ktime_sub(apic->lapic_timer.target_expiration, now); |
1790 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + | |
1791 | nsec_to_cycles(apic->vcpu, delta); | |
7d7f7da2 WL |
1792 | } |
1793 | ||
ecf08dad AB |
1794 | static void start_sw_period(struct kvm_lapic *apic) |
1795 | { | |
1796 | if (!apic->lapic_timer.period) | |
1797 | return; | |
1798 | ||
1799 | if (ktime_after(ktime_get(), | |
1800 | apic->lapic_timer.target_expiration)) { | |
ae95f566 | 1801 | apic_timer_expired(apic, false); |
ecf08dad AB |
1802 | |
1803 | if (apic_lvtt_oneshot(apic)) | |
1804 | return; | |
1805 | ||
1806 | advance_periodic_target_expiration(apic); | |
1807 | } | |
1808 | ||
1809 | hrtimer_start(&apic->lapic_timer.timer, | |
1810 | apic->lapic_timer.target_expiration, | |
edec6e01 | 1811 | HRTIMER_MODE_ABS_HARD); |
ecf08dad AB |
1812 | } |
1813 | ||
ce7a058a YJ |
1814 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1815 | { | |
91005300 WL |
1816 | if (!lapic_in_kernel(vcpu)) |
1817 | return false; | |
1818 | ||
ce7a058a YJ |
1819 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; |
1820 | } | |
1821 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1822 | ||
7e810a38 | 1823 | static void cancel_hv_timer(struct kvm_lapic *apic) |
bd97ad0e | 1824 | { |
1d518c68 | 1825 | WARN_ON(preemptible()); |
a749e247 | 1826 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
b3646477 | 1827 | static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); |
bd97ad0e WL |
1828 | apic->lapic_timer.hv_timer_in_use = false; |
1829 | } | |
1830 | ||
a749e247 | 1831 | static bool start_hv_timer(struct kvm_lapic *apic) |
196f20ca | 1832 | { |
35ee9e48 | 1833 | struct kvm_timer *ktimer = &apic->lapic_timer; |
f9927982 SC |
1834 | struct kvm_vcpu *vcpu = apic->vcpu; |
1835 | bool expired; | |
196f20ca | 1836 | |
1d518c68 | 1837 | WARN_ON(preemptible()); |
199a8b84 | 1838 | if (!kvm_can_use_hv_timer(vcpu)) |
a749e247 PB |
1839 | return false; |
1840 | ||
86bbc1e6 RK |
1841 | if (!ktimer->tscdeadline) |
1842 | return false; | |
1843 | ||
b3646477 | 1844 | if (static_call(kvm_x86_set_hv_timer)(vcpu, ktimer->tscdeadline, &expired)) |
35ee9e48 PB |
1845 | return false; |
1846 | ||
1847 | ktimer->hv_timer_in_use = true; | |
1848 | hrtimer_cancel(&ktimer->timer); | |
196f20ca | 1849 | |
35ee9e48 | 1850 | /* |
f1ba5cfb SC |
1851 | * To simplify handling the periodic timer, leave the hv timer running |
1852 | * even if the deadline timer has expired, i.e. rely on the resulting | |
1853 | * VM-Exit to recompute the periodic timer's target expiration. | |
35ee9e48 | 1854 | */ |
f1ba5cfb SC |
1855 | if (!apic_lvtt_period(apic)) { |
1856 | /* | |
1857 | * Cancel the hv timer if the sw timer fired while the hv timer | |
1858 | * was being programmed, or if the hv timer itself expired. | |
1859 | */ | |
1860 | if (atomic_read(&ktimer->pending)) { | |
1861 | cancel_hv_timer(apic); | |
f9927982 | 1862 | } else if (expired) { |
ae95f566 | 1863 | apic_timer_expired(apic, false); |
f1ba5cfb SC |
1864 | cancel_hv_timer(apic); |
1865 | } | |
c8533544 | 1866 | } |
a749e247 | 1867 | |
f9927982 | 1868 | trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use); |
f1ba5cfb | 1869 | |
35ee9e48 PB |
1870 | return true; |
1871 | } | |
1872 | ||
a749e247 | 1873 | static void start_sw_timer(struct kvm_lapic *apic) |
35ee9e48 | 1874 | { |
a749e247 | 1875 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1d518c68 WL |
1876 | |
1877 | WARN_ON(preemptible()); | |
a749e247 PB |
1878 | if (apic->lapic_timer.hv_timer_in_use) |
1879 | cancel_hv_timer(apic); | |
1880 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) | |
1881 | return; | |
1882 | ||
1883 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) | |
1884 | start_sw_period(apic); | |
1885 | else if (apic_lvtt_tscdeadline(apic)) | |
1886 | start_sw_tscdeadline(apic); | |
1887 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); | |
1888 | } | |
35ee9e48 | 1889 | |
a749e247 PB |
1890 | static void restart_apic_timer(struct kvm_lapic *apic) |
1891 | { | |
1d518c68 | 1892 | preempt_disable(); |
4ca88b3f SC |
1893 | |
1894 | if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) | |
1895 | goto out; | |
1896 | ||
a749e247 PB |
1897 | if (!start_hv_timer(apic)) |
1898 | start_sw_timer(apic); | |
4ca88b3f | 1899 | out: |
1d518c68 | 1900 | preempt_enable(); |
196f20ca WL |
1901 | } |
1902 | ||
8003c9ae WL |
1903 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1904 | { | |
1905 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1906 | ||
1d518c68 WL |
1907 | preempt_disable(); |
1908 | /* If the preempt notifier has already run, it also called apic_timer_expired */ | |
1909 | if (!apic->lapic_timer.hv_timer_in_use) | |
1910 | goto out; | |
da4ad88c | 1911 | WARN_ON(rcuwait_active(&vcpu->wait)); |
8003c9ae | 1912 | cancel_hv_timer(apic); |
ae95f566 | 1913 | apic_timer_expired(apic, false); |
8003c9ae WL |
1914 | |
1915 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { | |
1916 | advance_periodic_target_expiration(apic); | |
a749e247 | 1917 | restart_apic_timer(apic); |
8003c9ae | 1918 | } |
1d518c68 WL |
1919 | out: |
1920 | preempt_enable(); | |
8003c9ae WL |
1921 | } |
1922 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1923 | ||
ce7a058a YJ |
1924 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1925 | { | |
a749e247 | 1926 | restart_apic_timer(vcpu->arch.apic); |
ce7a058a YJ |
1927 | } |
1928 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1929 | ||
1930 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1931 | { | |
1932 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1933 | ||
1d518c68 | 1934 | preempt_disable(); |
ce7a058a | 1935 | /* Possibly the TSC deadline timer is not enabled yet */ |
a749e247 PB |
1936 | if (apic->lapic_timer.hv_timer_in_use) |
1937 | start_sw_timer(apic); | |
1d518c68 | 1938 | preempt_enable(); |
a749e247 PB |
1939 | } |
1940 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
ce7a058a | 1941 | |
a749e247 PB |
1942 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) |
1943 | { | |
1944 | struct kvm_lapic *apic = vcpu->arch.apic; | |
ce7a058a | 1945 | |
a749e247 PB |
1946 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
1947 | restart_apic_timer(apic); | |
ce7a058a | 1948 | } |
ce7a058a | 1949 | |
24647e0a | 1950 | static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg) |
97222cc8 | 1951 | { |
d3c7b77d | 1952 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1953 | |
a749e247 | 1954 | if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) |
24647e0a | 1955 | && !set_target_expiration(apic, count_reg)) |
a749e247 PB |
1956 | return; |
1957 | ||
1958 | restart_apic_timer(apic); | |
97222cc8 ED |
1959 | } |
1960 | ||
24647e0a PS |
1961 | static void start_apic_timer(struct kvm_lapic *apic) |
1962 | { | |
1963 | __start_apic_timer(apic, APIC_TMICT); | |
1964 | } | |
1965 | ||
cc6e462c JK |
1966 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1967 | { | |
59fd1323 | 1968 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1969 | |
59fd1323 RK |
1970 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1971 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1972 | if (lvt0_in_nmi_mode) { | |
42720138 | 1973 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1974 | } else |
1975 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1976 | } | |
cc6e462c JK |
1977 | } |
1978 | ||
1e6e2755 | 1979 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1980 | { |
0105d1a5 | 1981 | int ret = 0; |
97222cc8 | 1982 | |
0105d1a5 | 1983 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1984 | |
0105d1a5 | 1985 | switch (reg) { |
97222cc8 | 1986 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1987 | if (!apic_x2apic_mode(apic)) |
a92e2543 | 1988 | kvm_apic_set_xapic_id(apic, val >> 24); |
0105d1a5 GN |
1989 | else |
1990 | ret = 1; | |
97222cc8 ED |
1991 | break; |
1992 | ||
1993 | case APIC_TASKPRI: | |
b209749f | 1994 | report_tpr_access(apic, true); |
97222cc8 ED |
1995 | apic_set_tpr(apic, val & 0xff); |
1996 | break; | |
1997 | ||
1998 | case APIC_EOI: | |
1999 | apic_set_eoi(apic); | |
2000 | break; | |
2001 | ||
2002 | case APIC_LDR: | |
0105d1a5 | 2003 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 2004 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
2005 | else |
2006 | ret = 1; | |
97222cc8 ED |
2007 | break; |
2008 | ||
2009 | case APIC_DFR: | |
ae6f2496 WL |
2010 | if (!apic_x2apic_mode(apic)) |
2011 | kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); | |
2012 | else | |
0105d1a5 | 2013 | ret = 1; |
97222cc8 ED |
2014 | break; |
2015 | ||
fc61b800 GN |
2016 | case APIC_SPIV: { |
2017 | u32 mask = 0x3ff; | |
dfb95954 | 2018 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 2019 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 2020 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
2021 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
2022 | int i; | |
2023 | u32 lvt_val; | |
2024 | ||
1e6e2755 | 2025 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 2026 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 2027 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 2028 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
2029 | lvt_val | APIC_LVT_MASKED); |
2030 | } | |
b6ac0695 | 2031 | apic_update_lvtt(apic); |
d3c7b77d | 2032 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
2033 | |
2034 | } | |
2035 | break; | |
fc61b800 | 2036 | } |
97222cc8 ED |
2037 | case APIC_ICR: |
2038 | /* No delay here, so we always clear the pending bit */ | |
2b0911d1 | 2039 | val &= ~(1 << 12); |
d5361678 | 2040 | kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); |
2b0911d1 | 2041 | kvm_lapic_set_reg(apic, APIC_ICR, val); |
97222cc8 ED |
2042 | break; |
2043 | ||
2044 | case APIC_ICR2: | |
0105d1a5 GN |
2045 | if (!apic_x2apic_mode(apic)) |
2046 | val &= 0xff000000; | |
1e6e2755 | 2047 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
2048 | break; |
2049 | ||
23930f95 | 2050 | case APIC_LVT0: |
cc6e462c | 2051 | apic_manage_nmi_watchdog(apic, val); |
df561f66 | 2052 | fallthrough; |
97222cc8 ED |
2053 | case APIC_LVTTHMR: |
2054 | case APIC_LVTPC: | |
97222cc8 | 2055 | case APIC_LVT1: |
4bf79cb0 | 2056 | case APIC_LVTERR: { |
97222cc8 | 2057 | /* TODO: Check vector */ |
4bf79cb0 MP |
2058 | size_t size; |
2059 | u32 index; | |
2060 | ||
c48f1496 | 2061 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 | 2062 | val |= APIC_LVT_MASKED; |
4bf79cb0 MP |
2063 | size = ARRAY_SIZE(apic_lvt_mask); |
2064 | index = array_index_nospec( | |
2065 | (reg - APIC_LVTT) >> 4, size); | |
2066 | val &= apic_lvt_mask[index]; | |
1e6e2755 | 2067 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 | 2068 | break; |
4bf79cb0 | 2069 | } |
97222cc8 | 2070 | |
b6ac0695 | 2071 | case APIC_LVTT: |
c48f1496 | 2072 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
2073 | val |= APIC_LVT_MASKED; |
2074 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 2075 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 2076 | apic_update_lvtt(apic); |
a3e06bbe LJ |
2077 | break; |
2078 | ||
97222cc8 | 2079 | case APIC_TMICT: |
a3e06bbe LJ |
2080 | if (apic_lvtt_tscdeadline(apic)) |
2081 | break; | |
2082 | ||
d3c7b77d | 2083 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 2084 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 2085 | start_apic_timer(apic); |
0105d1a5 | 2086 | break; |
97222cc8 | 2087 | |
c301b909 WL |
2088 | case APIC_TDCR: { |
2089 | uint32_t old_divisor = apic->divide_count; | |
2090 | ||
a445fc45 | 2091 | kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); |
97222cc8 | 2092 | update_divide_count(apic); |
c301b909 WL |
2093 | if (apic->divide_count != old_divisor && |
2094 | apic->lapic_timer.period) { | |
2095 | hrtimer_cancel(&apic->lapic_timer.timer); | |
2096 | update_target_expiration(apic, old_divisor); | |
2097 | restart_apic_timer(apic); | |
2098 | } | |
97222cc8 | 2099 | break; |
c301b909 | 2100 | } |
0105d1a5 | 2101 | case APIC_ESR: |
0d88800d | 2102 | if (apic_x2apic_mode(apic) && val != 0) |
0105d1a5 | 2103 | ret = 1; |
0105d1a5 GN |
2104 | break; |
2105 | ||
2106 | case APIC_SELF_IPI: | |
2107 | if (apic_x2apic_mode(apic)) { | |
9c2475f3 HL |
2108 | kvm_lapic_reg_write(apic, APIC_ICR, |
2109 | APIC_DEST_SELF | (val & APIC_VECTOR_MASK)); | |
0105d1a5 GN |
2110 | } else |
2111 | ret = 1; | |
2112 | break; | |
97222cc8 | 2113 | default: |
0105d1a5 | 2114 | ret = 1; |
97222cc8 ED |
2115 | break; |
2116 | } | |
0d88800d | 2117 | |
4abaffce WL |
2118 | kvm_recalculate_apic_map(apic->vcpu->kvm); |
2119 | ||
0105d1a5 GN |
2120 | return ret; |
2121 | } | |
1e6e2755 | 2122 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 2123 | |
e32edf4f | 2124 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
2125 | gpa_t address, int len, const void *data) |
2126 | { | |
2127 | struct kvm_lapic *apic = to_lapic(this); | |
2128 | unsigned int offset = address - apic->base_address; | |
2129 | u32 val; | |
2130 | ||
2131 | if (!apic_mmio_in_range(apic, address)) | |
2132 | return -EOPNOTSUPP; | |
2133 | ||
d1766202 VK |
2134 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
2135 | if (!kvm_check_has_quirk(vcpu->kvm, | |
2136 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
2137 | return -EOPNOTSUPP; | |
2138 | ||
2139 | return 0; | |
2140 | } | |
2141 | ||
0105d1a5 GN |
2142 | /* |
2143 | * APIC register must be aligned on 128-bits boundary. | |
2144 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
2145 | * Refer SDM 8.4.1 | |
2146 | */ | |
0d88800d | 2147 | if (len != 4 || (offset & 0xf)) |
756975bb | 2148 | return 0; |
0105d1a5 GN |
2149 | |
2150 | val = *(u32*)data; | |
2151 | ||
0d88800d | 2152 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 2153 | |
bda9020e | 2154 | return 0; |
97222cc8 ED |
2155 | } |
2156 | ||
58fbbf26 KT |
2157 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
2158 | { | |
1e6e2755 | 2159 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
2160 | } |
2161 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
2162 | ||
83d4c286 YZ |
2163 | /* emulate APIC access in a trap manner */ |
2164 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
2165 | { | |
2166 | u32 val = 0; | |
2167 | ||
2168 | /* hw has done the conditional check and inst decode */ | |
2169 | offset &= 0xff0; | |
2170 | ||
1e6e2755 | 2171 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
2172 | |
2173 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 2174 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
2175 | } |
2176 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
2177 | ||
d589444e | 2178 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 2179 | { |
f8c1ea10 GN |
2180 | struct kvm_lapic *apic = vcpu->arch.apic; |
2181 | ||
ad312c7c | 2182 | if (!vcpu->arch.apic) |
97222cc8 ED |
2183 | return; |
2184 | ||
f8c1ea10 | 2185 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2186 | |
c5cc421b | 2187 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
6e4e3b4d | 2188 | static_branch_slow_dec_deferred(&apic_hw_disabled); |
c5cc421b | 2189 | |
e462755c | 2190 | if (!apic->sw_enabled) |
6e4e3b4d | 2191 | static_branch_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 2192 | |
f8c1ea10 GN |
2193 | if (apic->regs) |
2194 | free_page((unsigned long)apic->regs); | |
2195 | ||
2196 | kfree(apic); | |
97222cc8 ED |
2197 | } |
2198 | ||
2199 | /* | |
2200 | *---------------------------------------------------------------------- | |
2201 | * LAPIC interface | |
2202 | *---------------------------------------------------------------------- | |
2203 | */ | |
a3e06bbe LJ |
2204 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
2205 | { | |
2206 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2207 | |
a970e9b2 | 2208 | if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) |
a3e06bbe LJ |
2209 | return 0; |
2210 | ||
2211 | return apic->lapic_timer.tscdeadline; | |
2212 | } | |
2213 | ||
2214 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
2215 | { | |
2216 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2217 | |
27503833 | 2218 | if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) |
a3e06bbe LJ |
2219 | return; |
2220 | ||
2221 | hrtimer_cancel(&apic->lapic_timer.timer); | |
2222 | apic->lapic_timer.tscdeadline = data; | |
2223 | start_apic_timer(apic); | |
2224 | } | |
2225 | ||
97222cc8 ED |
2226 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
2227 | { | |
ad312c7c | 2228 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2229 | |
b93463aa | 2230 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 2231 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
2232 | } |
2233 | ||
2234 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
2235 | { | |
97222cc8 ED |
2236 | u64 tpr; |
2237 | ||
dfb95954 | 2238 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
2239 | |
2240 | return (tpr & 0xf0) >> 4; | |
2241 | } | |
2242 | ||
2243 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
2244 | { | |
8d14695f | 2245 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 2246 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2247 | |
c7dd15b3 | 2248 | if (!apic) |
97222cc8 | 2249 | value |= MSR_IA32_APICBASE_BSP; |
c5af89b6 | 2250 | |
e66d2ae7 JK |
2251 | vcpu->arch.apic_base = value; |
2252 | ||
c7dd15b3 | 2253 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) |
aedbaf4f | 2254 | kvm_update_cpuid_runtime(vcpu); |
c7dd15b3 JM |
2255 | |
2256 | if (!apic) | |
2257 | return; | |
2258 | ||
c5cc421b | 2259 | /* update jump label if enable bit changes */ |
0dce7cd6 | 2260 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
49bd29ba RK |
2261 | if (value & MSR_IA32_APICBASE_ENABLE) { |
2262 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); | |
6e4e3b4d | 2263 | static_branch_slow_dec_deferred(&apic_hw_disabled); |
187ca84b | 2264 | } else { |
6e4e3b4d | 2265 | static_branch_inc(&apic_hw_disabled.key); |
44d52717 | 2266 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
187ca84b | 2267 | } |
c5cc421b GN |
2268 | } |
2269 | ||
8d860bbe JM |
2270 | if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) |
2271 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); | |
2272 | ||
2273 | if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) | |
b3646477 | 2274 | static_call(kvm_x86_set_virtual_apic_mode)(vcpu); |
8d14695f | 2275 | |
ad312c7c | 2276 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
2277 | MSR_IA32_APICBASE_BASE; |
2278 | ||
db324fe6 NA |
2279 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
2280 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
2281 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
97222cc8 ED |
2282 | } |
2283 | ||
b26a695a SS |
2284 | void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) |
2285 | { | |
2286 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2287 | ||
2288 | if (vcpu->arch.apicv_active) { | |
2289 | /* irr_pending is always true when apicv is activated. */ | |
2290 | apic->irr_pending = true; | |
2291 | apic->isr_count = 1; | |
2292 | } else { | |
2293 | apic->irr_pending = (apic_search_irr(apic) != -1); | |
2294 | apic->isr_count = count_vectors(apic->regs + APIC_ISR); | |
2295 | } | |
2296 | } | |
2297 | EXPORT_SYMBOL_GPL(kvm_apic_update_apicv); | |
2298 | ||
d28bc9dd | 2299 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 | 2300 | { |
b7e31be3 | 2301 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
2302 | int i; |
2303 | ||
b7e31be3 RK |
2304 | if (!apic) |
2305 | return; | |
97222cc8 | 2306 | |
97222cc8 | 2307 | /* Stop the timer in case it's a reset to an active apic */ |
d3c7b77d | 2308 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2309 | |
4d8e772b RK |
2310 | if (!init_event) { |
2311 | kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | | |
2312 | MSR_IA32_APICBASE_ENABLE); | |
a92e2543 | 2313 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); |
4d8e772b | 2314 | } |
fc61b800 | 2315 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 2316 | |
1e6e2755 SS |
2317 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
2318 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 2319 | apic_update_lvtt(apic); |
52b54190 JS |
2320 | if (kvm_vcpu_is_reset_bsp(vcpu) && |
2321 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) | |
1e6e2755 | 2322 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 2323 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 2324 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 2325 | |
ae6f2496 | 2326 | kvm_apic_set_dfr(apic, 0xffffffffU); |
f8c1ea10 | 2327 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 2328 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
2329 | if (!apic_x2apic_mode(apic)) |
2330 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
2331 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
2332 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
2333 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
2334 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
2335 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 2336 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
2337 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
2338 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
2339 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 2340 | } |
b26a695a | 2341 | kvm_apic_update_apicv(vcpu); |
8680b94b | 2342 | apic->highest_isr_cache = -1; |
b33ac88b | 2343 | update_divide_count(apic); |
d3c7b77d | 2344 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 2345 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
2346 | kvm_lapic_set_base(vcpu, |
2347 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 2348 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 | 2349 | apic_update_ppr(apic); |
4191db26 | 2350 | if (vcpu->arch.apicv_active) { |
b3646477 JB |
2351 | static_call(kvm_x86_apicv_post_state_restore)(vcpu); |
2352 | static_call(kvm_x86_hwapic_irr_update)(vcpu, -1); | |
2353 | static_call(kvm_x86_hwapic_isr_update)(vcpu, -1); | |
4191db26 | 2354 | } |
97222cc8 | 2355 | |
e1035715 | 2356 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 2357 | vcpu->arch.apic_attention = 0; |
4abaffce WL |
2358 | |
2359 | kvm_recalculate_apic_map(vcpu->kvm); | |
97222cc8 ED |
2360 | } |
2361 | ||
97222cc8 ED |
2362 | /* |
2363 | *---------------------------------------------------------------------- | |
2364 | * timer interface | |
2365 | *---------------------------------------------------------------------- | |
2366 | */ | |
1b9778da | 2367 | |
2a6eac96 | 2368 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 2369 | { |
d3c7b77d | 2370 | return apic_lvtt_period(apic); |
97222cc8 ED |
2371 | } |
2372 | ||
3d80840d MT |
2373 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
2374 | { | |
54e9818f | 2375 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 2376 | |
1e3161b4 | 2377 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 2378 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
2379 | |
2380 | return 0; | |
2381 | } | |
2382 | ||
89342082 | 2383 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 2384 | { |
dfb95954 | 2385 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 2386 | int vector, mode, trig_mode; |
23930f95 | 2387 | |
c48f1496 | 2388 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
2389 | vector = reg & APIC_VECTOR_MASK; |
2390 | mode = reg & APIC_MODE_MASK; | |
2391 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
2392 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
2393 | NULL); | |
23930f95 JK |
2394 | } |
2395 | return 0; | |
2396 | } | |
1b9778da | 2397 | |
8fdb2351 | 2398 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 2399 | { |
8fdb2351 JK |
2400 | struct kvm_lapic *apic = vcpu->arch.apic; |
2401 | ||
2402 | if (apic) | |
2403 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
2404 | } |
2405 | ||
d76685c4 GH |
2406 | static const struct kvm_io_device_ops apic_mmio_ops = { |
2407 | .read = apic_mmio_read, | |
2408 | .write = apic_mmio_write, | |
d76685c4 GH |
2409 | }; |
2410 | ||
e9d90d47 AK |
2411 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
2412 | { | |
2413 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 2414 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 2415 | |
ae95f566 | 2416 | apic_timer_expired(apic, true); |
e9d90d47 | 2417 | |
2a6eac96 | 2418 | if (lapic_is_periodic(apic)) { |
8003c9ae | 2419 | advance_periodic_target_expiration(apic); |
e9d90d47 AK |
2420 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
2421 | return HRTIMER_RESTART; | |
2422 | } else | |
2423 | return HRTIMER_NORESTART; | |
2424 | } | |
2425 | ||
c3941d9e | 2426 | int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns) |
97222cc8 ED |
2427 | { |
2428 | struct kvm_lapic *apic; | |
2429 | ||
2430 | ASSERT(vcpu != NULL); | |
97222cc8 | 2431 | |
254272ce | 2432 | apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); |
97222cc8 ED |
2433 | if (!apic) |
2434 | goto nomem; | |
2435 | ||
ad312c7c | 2436 | vcpu->arch.apic = apic; |
97222cc8 | 2437 | |
254272ce | 2438 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
afc20184 | 2439 | if (!apic->regs) { |
97222cc8 ED |
2440 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
2441 | vcpu->vcpu_id); | |
d589444e | 2442 | goto nomem_free_apic; |
97222cc8 | 2443 | } |
97222cc8 ED |
2444 | apic->vcpu = vcpu; |
2445 | ||
d3c7b77d | 2446 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
2c0d278f | 2447 | HRTIMER_MODE_ABS_HARD); |
e9d90d47 | 2448 | apic->lapic_timer.timer.function = apic_timer_fn; |
c3941d9e | 2449 | if (timer_advance_ns == -1) { |
a0f0037e | 2450 | apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; |
d0f5a86a | 2451 | lapic_timer_advance_dynamic = true; |
c3941d9e SC |
2452 | } else { |
2453 | apic->lapic_timer.timer_advance_ns = timer_advance_ns; | |
d0f5a86a | 2454 | lapic_timer_advance_dynamic = false; |
c3941d9e SC |
2455 | } |
2456 | ||
c5cc421b GN |
2457 | /* |
2458 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
ee171d2f | 2459 | * thinking that APIC state has changed. |
c5cc421b GN |
2460 | */ |
2461 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6e4e3b4d | 2462 | static_branch_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d76685c4 | 2463 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
2464 | |
2465 | return 0; | |
d589444e RR |
2466 | nomem_free_apic: |
2467 | kfree(apic); | |
a251fb90 | 2468 | vcpu->arch.apic = NULL; |
97222cc8 | 2469 | nomem: |
97222cc8 ED |
2470 | return -ENOMEM; |
2471 | } | |
97222cc8 ED |
2472 | |
2473 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
2474 | { | |
ad312c7c | 2475 | struct kvm_lapic *apic = vcpu->arch.apic; |
b3c045d3 | 2476 | u32 ppr; |
97222cc8 | 2477 | |
72c3bcdc | 2478 | if (!kvm_apic_present(vcpu)) |
97222cc8 ED |
2479 | return -1; |
2480 | ||
b3c045d3 PB |
2481 | __apic_update_ppr(apic, &ppr); |
2482 | return apic_has_interrupt_for_ppr(apic, ppr); | |
97222cc8 | 2483 | } |
25bb2cf9 | 2484 | EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt); |
97222cc8 | 2485 | |
40487c68 QH |
2486 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
2487 | { | |
dfb95954 | 2488 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 | 2489 | |
c48f1496 | 2490 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
3ce4dc17 | 2491 | return 1; |
e7dca5c0 CL |
2492 | if ((lvt0 & APIC_LVT_MASKED) == 0 && |
2493 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
3ce4dc17 ML |
2494 | return 1; |
2495 | return 0; | |
40487c68 QH |
2496 | } |
2497 | ||
1b9778da ED |
2498 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
2499 | { | |
ad312c7c | 2500 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 2501 | |
54e9818f | 2502 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
0c5f81da | 2503 | kvm_apic_inject_pending_timer_irqs(apic); |
f1ed0450 | 2504 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
2505 | } |
2506 | } | |
2507 | ||
97222cc8 ED |
2508 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
2509 | { | |
2510 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 2511 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d82d12b | 2512 | u32 ppr; |
97222cc8 ED |
2513 | |
2514 | if (vector == -1) | |
2515 | return -1; | |
2516 | ||
56cc2406 WL |
2517 | /* |
2518 | * We get here even with APIC virtualization enabled, if doing | |
2519 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
2520 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
2521 | * because the process would deliver it through the IDT. | |
2522 | */ | |
2523 | ||
97222cc8 | 2524 | apic_clear_irr(vector, apic); |
f2bc14b6 | 2525 | if (to_hv_vcpu(vcpu) && test_bit(vector, to_hv_synic(vcpu)->auto_eoi_bitmap)) { |
4d82d12b PB |
2526 | /* |
2527 | * For auto-EOI interrupts, there might be another pending | |
2528 | * interrupt above PPR, so check whether to raise another | |
2529 | * KVM_REQ_EVENT. | |
2530 | */ | |
5c919412 | 2531 | apic_update_ppr(apic); |
4d82d12b PB |
2532 | } else { |
2533 | /* | |
2534 | * For normal interrupts, PPR has been raised and there cannot | |
2535 | * be a higher-priority pending interrupt---except if there was | |
2536 | * a concurrent interrupt injection, but that would have | |
2537 | * triggered KVM_REQ_EVENT already. | |
2538 | */ | |
2539 | apic_set_isr(vector, apic); | |
2540 | __apic_update_ppr(apic, &ppr); | |
5c919412 AS |
2541 | } |
2542 | ||
97222cc8 ED |
2543 | return vector; |
2544 | } | |
96ad2cc6 | 2545 | |
a92e2543 RK |
2546 | static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, |
2547 | struct kvm_lapic_state *s, bool set) | |
2548 | { | |
2549 | if (apic_x2apic_mode(vcpu->arch.apic)) { | |
2550 | u32 *id = (u32 *)(s->regs + APIC_ID); | |
12806ba9 | 2551 | u32 *ldr = (u32 *)(s->regs + APIC_LDR); |
a92e2543 | 2552 | |
37131313 RK |
2553 | if (vcpu->kvm->arch.x2apic_format) { |
2554 | if (*id != vcpu->vcpu_id) | |
2555 | return -EINVAL; | |
2556 | } else { | |
2557 | if (set) | |
2558 | *id >>= 24; | |
2559 | else | |
2560 | *id <<= 24; | |
2561 | } | |
12806ba9 DDAG |
2562 | |
2563 | /* In x2APIC mode, the LDR is fixed and based on the id */ | |
2564 | if (set) | |
2565 | *ldr = kvm_apic_calc_x2apic_ldr(*id); | |
a92e2543 RK |
2566 | } |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
2571 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
2572 | { | |
2573 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); | |
24647e0a PS |
2574 | |
2575 | /* | |
2576 | * Get calculated timer current count for remaining timer period (if | |
2577 | * any) and store it in the returned register set. | |
2578 | */ | |
2579 | __kvm_lapic_set_reg(s->regs, APIC_TMCCT, | |
2580 | __apic_read(vcpu->arch.apic, APIC_TMCCT)); | |
2581 | ||
a92e2543 RK |
2582 | return kvm_apic_state_fixup(vcpu, s, false); |
2583 | } | |
2584 | ||
2585 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
96ad2cc6 | 2586 | { |
ad312c7c | 2587 | struct kvm_lapic *apic = vcpu->arch.apic; |
a92e2543 RK |
2588 | int r; |
2589 | ||
5dbc8f3f | 2590 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
2591 | /* set SPIV separately to get count of SW disabled APICs right */ |
2592 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
a92e2543 RK |
2593 | |
2594 | r = kvm_apic_state_fixup(vcpu, s, true); | |
4abaffce WL |
2595 | if (r) { |
2596 | kvm_recalculate_apic_map(vcpu->kvm); | |
a92e2543 | 2597 | return r; |
4abaffce | 2598 | } |
0e96f31e | 2599 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); |
a92e2543 | 2600 | |
44d52717 | 2601 | atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); |
4abaffce | 2602 | kvm_recalculate_apic_map(vcpu->kvm); |
fc61b800 GN |
2603 | kvm_apic_set_version(vcpu); |
2604 | ||
96ad2cc6 | 2605 | apic_update_ppr(apic); |
d3c7b77d | 2606 | hrtimer_cancel(&apic->lapic_timer.timer); |
35737d2d | 2607 | apic->lapic_timer.expired_tscdeadline = 0; |
b6ac0695 | 2608 | apic_update_lvtt(apic); |
dfb95954 | 2609 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 | 2610 | update_divide_count(apic); |
24647e0a | 2611 | __start_apic_timer(apic, APIC_TMCCT); |
b26a695a | 2612 | kvm_apic_update_apicv(vcpu); |
8680b94b | 2613 | apic->highest_isr_cache = -1; |
d62caabb | 2614 | if (vcpu->arch.apicv_active) { |
b3646477 JB |
2615 | static_call(kvm_x86_apicv_post_state_restore)(vcpu); |
2616 | static_call(kvm_x86_hwapic_irr_update)(vcpu, | |
4114c27d | 2617 | apic_find_highest_irr(apic)); |
b3646477 | 2618 | static_call(kvm_x86_hwapic_isr_update)(vcpu, |
b4eef9b3 | 2619 | apic_find_highest_isr(apic)); |
d62caabb | 2620 | } |
3842d135 | 2621 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2622 | if (ioapic_in_kernel(vcpu->kvm)) |
2623 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2624 | |
2625 | vcpu->arch.apic_arb_prio = 0; | |
a92e2543 RK |
2626 | |
2627 | return 0; | |
96ad2cc6 | 2628 | } |
a3d7f85f | 2629 | |
2f52d58c | 2630 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2631 | { |
a3d7f85f ED |
2632 | struct hrtimer *timer; |
2633 | ||
0c5f81da WL |
2634 | if (!lapic_in_kernel(vcpu) || |
2635 | kvm_can_post_timer_interrupt(vcpu)) | |
a3d7f85f ED |
2636 | return; |
2637 | ||
54e9818f | 2638 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2639 | if (hrtimer_cancel(timer)) |
2c0d278f | 2640 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD); |
a3d7f85f | 2641 | } |
b93463aa | 2642 | |
ae7a2a3f MT |
2643 | /* |
2644 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2645 | * | |
2646 | * Detect whether guest triggered PV EOI since the | |
2647 | * last entry. If yes, set EOI on guests's behalf. | |
2648 | * Clear PV EOI in guest memory in any case. | |
2649 | */ | |
2650 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2651 | struct kvm_lapic *apic) | |
2652 | { | |
2653 | bool pending; | |
2654 | int vector; | |
2655 | /* | |
2656 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2657 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2658 | * | |
2659 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2660 | * -> host disabled PV EOI. | |
2661 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2662 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2663 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2664 | * -> host enabled PV EOI, guest executed EOI. | |
2665 | */ | |
2666 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2667 | pending = pv_eoi_get_pending(vcpu); | |
2668 | /* | |
2669 | * Clear pending bit in any case: it will be set again on vmentry. | |
2670 | * While this might not be ideal from performance point of view, | |
2671 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2672 | */ | |
2673 | pv_eoi_clr_pending(vcpu); | |
2674 | if (pending) | |
2675 | return; | |
2676 | vector = apic_set_eoi(apic); | |
2677 | trace_kvm_pv_eoi(apic, vector); | |
2678 | } | |
2679 | ||
b93463aa AK |
2680 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2681 | { | |
2682 | u32 data; | |
b93463aa | 2683 | |
ae7a2a3f MT |
2684 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2685 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2686 | ||
41383771 | 2687 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2688 | return; |
2689 | ||
4e335d9e PB |
2690 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2691 | sizeof(u32))) | |
603242a8 | 2692 | return; |
b93463aa AK |
2693 | |
2694 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2695 | } | |
2696 | ||
ae7a2a3f MT |
2697 | /* |
2698 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2699 | * | |
2700 | * Detect whether it's safe to enable PV EOI and | |
2701 | * if yes do so. | |
2702 | */ | |
2703 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2704 | struct kvm_lapic *apic) | |
2705 | { | |
2706 | if (!pv_eoi_enabled(vcpu) || | |
2707 | /* IRR set or many bits in ISR: could be nested. */ | |
2708 | apic->irr_pending || | |
2709 | /* Cache not set: could be safe but we don't bother. */ | |
2710 | apic->highest_isr_cache == -1 || | |
2711 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2712 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2713 | /* |
2714 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2715 | * so we need not do anything here. | |
2716 | */ | |
2717 | return; | |
2718 | } | |
2719 | ||
2720 | pv_eoi_set_pending(apic->vcpu); | |
2721 | } | |
2722 | ||
b93463aa AK |
2723 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2724 | { | |
2725 | u32 data, tpr; | |
2726 | int max_irr, max_isr; | |
ae7a2a3f | 2727 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2728 | |
ae7a2a3f MT |
2729 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2730 | ||
41383771 | 2731 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2732 | return; |
2733 | ||
dfb95954 | 2734 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2735 | max_irr = apic_find_highest_irr(apic); |
2736 | if (max_irr < 0) | |
2737 | max_irr = 0; | |
2738 | max_isr = apic_find_highest_isr(apic); | |
2739 | if (max_isr < 0) | |
2740 | max_isr = 0; | |
2741 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2742 | ||
4e335d9e PB |
2743 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2744 | sizeof(u32)); | |
b93463aa AK |
2745 | } |
2746 | ||
fda4e2e8 | 2747 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2748 | { |
fda4e2e8 | 2749 | if (vapic_addr) { |
4e335d9e | 2750 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
fda4e2e8 AH |
2751 | &vcpu->arch.apic->vapic_cache, |
2752 | vapic_addr, sizeof(u32))) | |
2753 | return -EINVAL; | |
41383771 | 2754 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2755 | } else { |
41383771 | 2756 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2757 | } |
2758 | ||
2759 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2760 | return 0; | |
b93463aa | 2761 | } |
0105d1a5 GN |
2762 | |
2763 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2764 | { | |
2765 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2766 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2767 | ||
35754c98 | 2768 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2769 | return 1; |
2770 | ||
c69d3d9b NA |
2771 | if (reg == APIC_ICR2) |
2772 | return 1; | |
2773 | ||
0105d1a5 | 2774 | /* if this is ICR write vector before command */ |
decdc283 | 2775 | if (reg == APIC_ICR) |
1e6e2755 SS |
2776 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2777 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2778 | } |
2779 | ||
2780 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2781 | { | |
2782 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2783 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2784 | ||
35754c98 | 2785 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2786 | return 1; |
2787 | ||
0d88800d | 2788 | if (reg == APIC_DFR || reg == APIC_ICR2) |
c69d3d9b | 2789 | return 1; |
c69d3d9b | 2790 | |
1e6e2755 | 2791 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2792 | return 1; |
decdc283 | 2793 | if (reg == APIC_ICR) |
1e6e2755 | 2794 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2795 | |
2796 | *data = (((u64)high) << 32) | low; | |
2797 | ||
2798 | return 0; | |
2799 | } | |
10388a07 GN |
2800 | |
2801 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2802 | { | |
2803 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2804 | ||
bce87cce | 2805 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2806 | return 1; |
2807 | ||
2808 | /* if this is ICR write vector before command */ | |
2809 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2810 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2811 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2812 | } |
2813 | ||
2814 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2815 | { | |
2816 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2817 | u32 low, high = 0; | |
2818 | ||
bce87cce | 2819 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2820 | return 1; |
2821 | ||
1e6e2755 | 2822 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2823 | return 1; |
2824 | if (reg == APIC_ICR) | |
1e6e2755 | 2825 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2826 | |
2827 | *data = (((u64)high) << 32) | low; | |
2828 | ||
2829 | return 0; | |
2830 | } | |
ae7a2a3f | 2831 | |
72bbf935 | 2832 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len) |
ae7a2a3f MT |
2833 | { |
2834 | u64 addr = data & ~KVM_MSR_ENABLED; | |
a7c42bb6 VK |
2835 | struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; |
2836 | unsigned long new_len; | |
2837 | ||
ae7a2a3f MT |
2838 | if (!IS_ALIGNED(addr, 4)) |
2839 | return 1; | |
2840 | ||
2841 | vcpu->arch.pv_eoi.msr_val = data; | |
2842 | if (!pv_eoi_enabled(vcpu)) | |
2843 | return 0; | |
a7c42bb6 VK |
2844 | |
2845 | if (addr == ghc->gpa && len <= ghc->len) | |
2846 | new_len = ghc->len; | |
2847 | else | |
2848 | new_len = len; | |
2849 | ||
2850 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); | |
ae7a2a3f | 2851 | } |
c5cc421b | 2852 | |
66450a21 JK |
2853 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2854 | { | |
2855 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2856 | u8 sipi_vector; |
1c96dcce | 2857 | int r; |
299018f4 | 2858 | unsigned long pe; |
66450a21 | 2859 | |
1c96dcce PB |
2860 | if (!lapic_in_kernel(vcpu)) |
2861 | return; | |
2862 | ||
2863 | /* | |
2864 | * Read pending events before calling the check_events | |
2865 | * callback. | |
2866 | */ | |
2867 | pe = smp_load_acquire(&apic->pending_events); | |
2868 | if (!pe) | |
66450a21 JK |
2869 | return; |
2870 | ||
1c96dcce PB |
2871 | if (is_guest_mode(vcpu)) { |
2872 | r = kvm_x86_ops.nested_ops->check_events(vcpu); | |
2873 | if (r < 0) | |
2874 | return; | |
2875 | /* | |
2876 | * If an event has happened and caused a vmexit, | |
2877 | * we know INITs are latched and therefore | |
2878 | * we will not incorrectly deliver an APIC | |
2879 | * event instead of a vmexit. | |
2880 | */ | |
2881 | } | |
2882 | ||
cd7764fe | 2883 | /* |
4b9852f4 | 2884 | * INITs are latched while CPU is in specific states |
1c96dcce | 2885 | * (SMM, VMX root mode, SVM with GIF=0). |
4b9852f4 LA |
2886 | * Because a CPU cannot be in these states immediately |
2887 | * after it has processed an INIT signal (and thus in | |
2888 | * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs | |
2889 | * and leave the INIT pending. | |
cd7764fe | 2890 | */ |
27cbe7d6 | 2891 | if (kvm_vcpu_latch_init(vcpu)) { |
cd7764fe | 2892 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); |
1c96dcce | 2893 | if (test_bit(KVM_APIC_SIPI, &pe)) |
cd7764fe PB |
2894 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); |
2895 | return; | |
2896 | } | |
299018f4 GN |
2897 | |
2898 | if (test_bit(KVM_APIC_INIT, &pe)) { | |
1c96dcce | 2899 | clear_bit(KVM_APIC_INIT, &apic->pending_events); |
d28bc9dd | 2900 | kvm_vcpu_reset(vcpu, true); |
66450a21 JK |
2901 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2902 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2903 | else | |
2904 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2905 | } | |
f57ad63a | 2906 | if (test_bit(KVM_APIC_SIPI, &pe)) { |
1c96dcce | 2907 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); |
f57ad63a ML |
2908 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2909 | /* evaluate pending_events before reading the vector */ | |
2910 | smp_rmb(); | |
2911 | sipi_vector = apic->sipi_vector; | |
647daca2 | 2912 | kvm_x86_ops.vcpu_deliver_sipi_vector(vcpu, sipi_vector); |
f57ad63a ML |
2913 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
2914 | } | |
66450a21 JK |
2915 | } |
2916 | } | |
2917 | ||
cef84c30 DM |
2918 | void kvm_lapic_exit(void) |
2919 | { | |
2920 | static_key_deferred_flush(&apic_hw_disabled); | |
2921 | static_key_deferred_flush(&apic_sw_disabled); | |
2922 | } |