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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
97222cc8 ED |
2 | |
3 | /* | |
4 | * Local APIC virtualization | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * Copyright (C) 2007 Novell | |
8 | * Copyright (C) 2007 Intel | |
9611c187 | 9 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
10 | * |
11 | * Authors: | |
12 | * Dor Laor <dor.laor@qumranet.com> | |
13 | * Gregory Haskins <ghaskins@novell.com> | |
14 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
15 | * | |
16 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
97222cc8 ED |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
97222cc8 ED |
20 | #include <linux/kvm.h> |
21 | #include <linux/mm.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/hrtimer.h> | |
25 | #include <linux/io.h> | |
1767e931 | 26 | #include <linux/export.h> |
6f6d6a1a | 27 | #include <linux/math64.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
97222cc8 ED |
29 | #include <asm/processor.h> |
30 | #include <asm/msr.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/current.h> | |
33 | #include <asm/apicdef.h> | |
d0659d94 | 34 | #include <asm/delay.h> |
60063497 | 35 | #include <linux/atomic.h> |
c5cc421b | 36 | #include <linux/jump_label.h> |
5fdbf976 | 37 | #include "kvm_cache_regs.h" |
97222cc8 | 38 | #include "irq.h" |
229456fc | 39 | #include "trace.h" |
fc61b800 | 40 | #include "x86.h" |
00b27a3e | 41 | #include "cpuid.h" |
5c919412 | 42 | #include "hyperv.h" |
97222cc8 | 43 | |
b682b814 MT |
44 | #ifndef CONFIG_X86_64 |
45 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
46 | #else | |
47 | #define mod_64(x, y) ((x) % (y)) | |
48 | #endif | |
49 | ||
97222cc8 ED |
50 | #define PRId64 "d" |
51 | #define PRIx64 "llx" | |
52 | #define PRIu64 "u" | |
53 | #define PRIo64 "o" | |
54 | ||
97222cc8 | 55 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 56 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
57 | #define LAPIC_MMIO_LENGTH (1 << 12) |
58 | /* followed define is not in apicdef.h */ | |
59 | #define APIC_SHORT_MASK 0xc0000 | |
60 | #define APIC_DEST_NOSHORT 0x0 | |
61 | #define APIC_DEST_MASK 0x800 | |
62 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 63 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 64 | |
394457a9 NA |
65 | #define APIC_BROADCAST 0xFF |
66 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
67 | ||
d0f5a86a | 68 | static bool lapic_timer_advance_dynamic __read_mostly; |
a0f0037e WL |
69 | #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */ |
70 | #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */ | |
71 | #define LAPIC_TIMER_ADVANCE_NS_INIT 1000 | |
72 | #define LAPIC_TIMER_ADVANCE_NS_MAX 5000 | |
3b8a5df6 WL |
73 | /* step-by-step approximation to mitigate fluctuation */ |
74 | #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8 | |
75 | ||
a0c9a822 MT |
76 | static inline int apic_test_vector(int vec, void *bitmap) |
77 | { | |
78 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
79 | } | |
80 | ||
10606919 YZ |
81 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
82 | { | |
83 | struct kvm_lapic *apic = vcpu->arch.apic; | |
84 | ||
85 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
86 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
87 | } | |
88 | ||
8680b94b MT |
89 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
90 | { | |
91 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
92 | } | |
93 | ||
94 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
95 | { | |
96 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
97 | } | |
98 | ||
c5cc421b | 99 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
100 | struct static_key_deferred apic_sw_disabled __read_mostly; |
101 | ||
97222cc8 ED |
102 | static inline int apic_enabled(struct kvm_lapic *apic) |
103 | { | |
c48f1496 | 104 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
105 | } |
106 | ||
97222cc8 ED |
107 | #define LVT_MASK \ |
108 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
109 | ||
110 | #define LINT_MASK \ | |
111 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
112 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
113 | ||
6e500439 RK |
114 | static inline u8 kvm_xapic_id(struct kvm_lapic *apic) |
115 | { | |
116 | return kvm_lapic_get_reg(apic, APIC_ID) >> 24; | |
117 | } | |
118 | ||
119 | static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) | |
120 | { | |
121 | return apic->vcpu->vcpu_id; | |
122 | } | |
123 | ||
0c5f81da WL |
124 | bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu) |
125 | { | |
126 | return pi_inject_timer && kvm_vcpu_apicv_active(vcpu); | |
127 | } | |
128 | EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt); | |
129 | ||
130 | static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu) | |
131 | { | |
132 | return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; | |
133 | } | |
134 | ||
e45115b6 RK |
135 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
136 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
137 | switch (map->mode) { | |
138 | case KVM_APIC_MODE_X2APIC: { | |
139 | u32 offset = (dest_id >> 16) * 16; | |
0ca52e7b | 140 | u32 max_apic_id = map->max_apic_id; |
e45115b6 RK |
141 | |
142 | if (offset <= max_apic_id) { | |
143 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
144 | ||
1d487e9b | 145 | offset = array_index_nospec(offset, map->max_apic_id + 1); |
e45115b6 RK |
146 | *cluster = &map->phys_map[offset]; |
147 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
148 | } else { | |
149 | *mask = 0; | |
150 | } | |
3b5a5ffa | 151 | |
e45115b6 RK |
152 | return true; |
153 | } | |
154 | case KVM_APIC_MODE_XAPIC_FLAT: | |
155 | *cluster = map->xapic_flat_map; | |
156 | *mask = dest_id & 0xff; | |
157 | return true; | |
158 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
444fdad8 | 159 | *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; |
e45115b6 RK |
160 | *mask = dest_id & 0xf; |
161 | return true; | |
162 | default: | |
163 | /* Not optimized. */ | |
164 | return false; | |
165 | } | |
3548a259 RK |
166 | } |
167 | ||
af1bae54 | 168 | static void kvm_apic_map_free(struct rcu_head *rcu) |
3b5a5ffa | 169 | { |
af1bae54 | 170 | struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu); |
3b5a5ffa | 171 | |
af1bae54 | 172 | kvfree(map); |
3b5a5ffa RK |
173 | } |
174 | ||
1e08ec4a GN |
175 | static void recalculate_apic_map(struct kvm *kvm) |
176 | { | |
177 | struct kvm_apic_map *new, *old = NULL; | |
178 | struct kvm_vcpu *vcpu; | |
179 | int i; | |
6e500439 | 180 | u32 max_id = 255; /* enough space for any xAPIC ID */ |
1e08ec4a GN |
181 | |
182 | mutex_lock(&kvm->arch.apic_map_lock); | |
183 | ||
0ca52e7b RK |
184 | kvm_for_each_vcpu(i, vcpu, kvm) |
185 | if (kvm_apic_present(vcpu)) | |
6e500439 | 186 | max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); |
0ca52e7b | 187 | |
a7c3e901 | 188 | new = kvzalloc(sizeof(struct kvm_apic_map) + |
254272ce BG |
189 | sizeof(struct kvm_lapic *) * ((u64)max_id + 1), |
190 | GFP_KERNEL_ACCOUNT); | |
0ca52e7b | 191 | |
1e08ec4a GN |
192 | if (!new) |
193 | goto out; | |
194 | ||
0ca52e7b RK |
195 | new->max_apic_id = max_id; |
196 | ||
173beedc NA |
197 | kvm_for_each_vcpu(i, vcpu, kvm) { |
198 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
199 | struct kvm_lapic **cluster; |
200 | u16 mask; | |
5bd5db38 RK |
201 | u32 ldr; |
202 | u8 xapic_id; | |
203 | u32 x2apic_id; | |
1e08ec4a | 204 | |
df04d1d1 RK |
205 | if (!kvm_apic_present(vcpu)) |
206 | continue; | |
207 | ||
5bd5db38 RK |
208 | xapic_id = kvm_xapic_id(apic); |
209 | x2apic_id = kvm_x2apic_id(apic); | |
210 | ||
211 | /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */ | |
212 | if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && | |
213 | x2apic_id <= new->max_apic_id) | |
214 | new->phys_map[x2apic_id] = apic; | |
215 | /* | |
216 | * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, | |
217 | * prevent them from masking VCPUs with APIC ID <= 0xff. | |
218 | */ | |
219 | if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) | |
220 | new->phys_map[xapic_id] = apic; | |
3548a259 | 221 | |
b14c876b RK |
222 | if (!kvm_apic_sw_enabled(apic)) |
223 | continue; | |
224 | ||
6e500439 RK |
225 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
226 | ||
3b5a5ffa RK |
227 | if (apic_x2apic_mode(apic)) { |
228 | new->mode |= KVM_APIC_MODE_X2APIC; | |
229 | } else if (ldr) { | |
230 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 231 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
232 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
233 | else | |
234 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
235 | } | |
236 | ||
e45115b6 | 237 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
238 | continue; |
239 | ||
e45115b6 RK |
240 | if (mask) |
241 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
242 | } |
243 | out: | |
244 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
245 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
246 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
247 | mutex_unlock(&kvm->arch.apic_map_lock); | |
248 | ||
249 | if (old) | |
af1bae54 | 250 | call_rcu(&old->rcu, kvm_apic_map_free); |
c7c9c56c | 251 | |
b053b2ae | 252 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
253 | } |
254 | ||
1e1b6c26 NA |
255 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
256 | { | |
e462755c | 257 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 258 | |
1e6e2755 | 259 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
260 | |
261 | if (enabled != apic->sw_enabled) { | |
262 | apic->sw_enabled = enabled; | |
eb1ff0a9 | 263 | if (enabled) |
1e1b6c26 | 264 | static_key_slow_dec_deferred(&apic_sw_disabled); |
eb1ff0a9 | 265 | else |
1e1b6c26 | 266 | static_key_slow_inc(&apic_sw_disabled.key); |
b14c876b RK |
267 | |
268 | recalculate_apic_map(apic->vcpu->kvm); | |
1e1b6c26 NA |
269 | } |
270 | } | |
271 | ||
a92e2543 | 272 | static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) |
1e08ec4a | 273 | { |
1e6e2755 | 274 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
275 | recalculate_apic_map(apic->vcpu->kvm); |
276 | } | |
277 | ||
278 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
279 | { | |
1e6e2755 | 280 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
281 | recalculate_apic_map(apic->vcpu->kvm); |
282 | } | |
283 | ||
e872fa94 DDAG |
284 | static inline u32 kvm_apic_calc_x2apic_ldr(u32 id) |
285 | { | |
286 | return ((id >> 4) << 16) | (1 << (id & 0xf)); | |
287 | } | |
288 | ||
a92e2543 | 289 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) |
257b9a5f | 290 | { |
e872fa94 | 291 | u32 ldr = kvm_apic_calc_x2apic_ldr(id); |
257b9a5f | 292 | |
6e500439 RK |
293 | WARN_ON_ONCE(id != apic->vcpu->vcpu_id); |
294 | ||
a92e2543 | 295 | kvm_lapic_set_reg(apic, APIC_ID, id); |
1e6e2755 | 296 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); |
257b9a5f RK |
297 | recalculate_apic_map(apic->vcpu->kvm); |
298 | } | |
299 | ||
97222cc8 ED |
300 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
301 | { | |
dfb95954 | 302 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
303 | } |
304 | ||
305 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
306 | { | |
dfb95954 | 307 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
308 | } |
309 | ||
a3e06bbe LJ |
310 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
311 | { | |
f30ebc31 | 312 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
313 | } |
314 | ||
97222cc8 ED |
315 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
316 | { | |
f30ebc31 | 317 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
318 | } |
319 | ||
320 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
321 | { | |
f30ebc31 | 322 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
323 | } |
324 | ||
cc6e462c JK |
325 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
326 | { | |
327 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
328 | } | |
329 | ||
fc61b800 GN |
330 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
331 | { | |
332 | struct kvm_lapic *apic = vcpu->arch.apic; | |
333 | struct kvm_cpuid_entry2 *feat; | |
334 | u32 v = APIC_VERSION; | |
335 | ||
bce87cce | 336 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
337 | return; |
338 | ||
0bcc3fb9 VK |
339 | /* |
340 | * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) | |
341 | * which doesn't have EOI register; Some buggy OSes (e.g. Windows with | |
342 | * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC | |
343 | * version first and level-triggered interrupts never get EOIed in | |
344 | * IOAPIC. | |
345 | */ | |
fc61b800 | 346 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); |
0bcc3fb9 VK |
347 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) && |
348 | !ioapic_in_kernel(vcpu->kvm)) | |
fc61b800 | 349 | v |= APIC_LVR_DIRECTED_EOI; |
1e6e2755 | 350 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
351 | } |
352 | ||
1e6e2755 | 353 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 354 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
355 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
356 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
357 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
358 | LVT_MASK /* LVTERR */ | |
359 | }; | |
360 | ||
361 | static int find_highest_vector(void *bitmap) | |
362 | { | |
ecba9a52 TY |
363 | int vec; |
364 | u32 *reg; | |
97222cc8 | 365 | |
ecba9a52 TY |
366 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
367 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
368 | reg = bitmap + REG_POS(vec); | |
369 | if (*reg) | |
810e6def | 370 | return __fls(*reg) + vec; |
ecba9a52 | 371 | } |
97222cc8 | 372 | |
ecba9a52 | 373 | return -1; |
97222cc8 ED |
374 | } |
375 | ||
8680b94b MT |
376 | static u8 count_vectors(void *bitmap) |
377 | { | |
ecba9a52 TY |
378 | int vec; |
379 | u32 *reg; | |
8680b94b | 380 | u8 count = 0; |
ecba9a52 TY |
381 | |
382 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
383 | reg = bitmap + REG_POS(vec); | |
384 | count += hweight32(*reg); | |
385 | } | |
386 | ||
8680b94b MT |
387 | return count; |
388 | } | |
389 | ||
e7387b0e | 390 | bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) |
a20ed54d | 391 | { |
810e6def | 392 | u32 i, vec; |
e7387b0e LA |
393 | u32 pir_val, irr_val, prev_irr_val; |
394 | int max_updated_irr; | |
395 | ||
396 | max_updated_irr = -1; | |
397 | *max_irr = -1; | |
a20ed54d | 398 | |
810e6def | 399 | for (i = vec = 0; i <= 7; i++, vec += 32) { |
ad361091 | 400 | pir_val = READ_ONCE(pir[i]); |
810e6def | 401 | irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10)); |
ad361091 | 402 | if (pir_val) { |
e7387b0e | 403 | prev_irr_val = irr_val; |
810e6def PB |
404 | irr_val |= xchg(&pir[i], 0); |
405 | *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val; | |
e7387b0e LA |
406 | if (prev_irr_val != irr_val) { |
407 | max_updated_irr = | |
408 | __fls(irr_val ^ prev_irr_val) + vec; | |
409 | } | |
ad361091 | 410 | } |
810e6def | 411 | if (irr_val) |
e7387b0e | 412 | *max_irr = __fls(irr_val) + vec; |
a20ed54d | 413 | } |
810e6def | 414 | |
e7387b0e LA |
415 | return ((max_updated_irr != -1) && |
416 | (max_updated_irr == *max_irr)); | |
a20ed54d | 417 | } |
705699a1 WV |
418 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
419 | ||
e7387b0e | 420 | bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr) |
705699a1 WV |
421 | { |
422 | struct kvm_lapic *apic = vcpu->arch.apic; | |
423 | ||
e7387b0e | 424 | return __kvm_apic_update_irr(pir, apic->regs, max_irr); |
705699a1 | 425 | } |
a20ed54d YZ |
426 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
427 | ||
33e4c686 | 428 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 429 | { |
33e4c686 | 430 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
431 | } |
432 | ||
433 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
434 | { | |
435 | int result; | |
436 | ||
c7c9c56c YZ |
437 | /* |
438 | * Note that irr_pending is just a hint. It will be always | |
439 | * true with virtual interrupt delivery enabled. | |
440 | */ | |
33e4c686 GN |
441 | if (!apic->irr_pending) |
442 | return -1; | |
443 | ||
444 | result = apic_search_irr(apic); | |
97222cc8 ED |
445 | ASSERT(result == -1 || result >= 16); |
446 | ||
447 | return result; | |
448 | } | |
449 | ||
33e4c686 GN |
450 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
451 | { | |
56cc2406 WL |
452 | struct kvm_vcpu *vcpu; |
453 | ||
454 | vcpu = apic->vcpu; | |
455 | ||
d62caabb | 456 | if (unlikely(vcpu->arch.apicv_active)) { |
b95234c8 | 457 | /* need to update RVI */ |
ee171d2f | 458 | kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); |
b95234c8 PB |
459 | kvm_x86_ops->hwapic_irr_update(vcpu, |
460 | apic_find_highest_irr(apic)); | |
f210f757 NA |
461 | } else { |
462 | apic->irr_pending = false; | |
ee171d2f | 463 | kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); |
f210f757 NA |
464 | if (apic_search_irr(apic) != -1) |
465 | apic->irr_pending = true; | |
56cc2406 | 466 | } |
33e4c686 GN |
467 | } |
468 | ||
8680b94b MT |
469 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
470 | { | |
56cc2406 WL |
471 | struct kvm_vcpu *vcpu; |
472 | ||
473 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
474 | return; | |
475 | ||
476 | vcpu = apic->vcpu; | |
fc57ac2c | 477 | |
8680b94b | 478 | /* |
56cc2406 WL |
479 | * With APIC virtualization enabled, all caching is disabled |
480 | * because the processor can modify ISR under the hood. Instead | |
481 | * just set SVI. | |
8680b94b | 482 | */ |
d62caabb | 483 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 484 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
485 | else { |
486 | ++apic->isr_count; | |
487 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
488 | /* | |
489 | * ISR (in service register) bit is set when injecting an interrupt. | |
490 | * The highest vector is injected. Thus the latest bit set matches | |
491 | * the highest bit in ISR. | |
492 | */ | |
493 | apic->highest_isr_cache = vec; | |
494 | } | |
8680b94b MT |
495 | } |
496 | ||
fc57ac2c PB |
497 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
498 | { | |
499 | int result; | |
500 | ||
501 | /* | |
502 | * Note that isr_count is always 1, and highest_isr_cache | |
503 | * is always -1, with APIC virtualization enabled. | |
504 | */ | |
505 | if (!apic->isr_count) | |
506 | return -1; | |
507 | if (likely(apic->highest_isr_cache != -1)) | |
508 | return apic->highest_isr_cache; | |
509 | ||
510 | result = find_highest_vector(apic->regs + APIC_ISR); | |
511 | ASSERT(result == -1 || result >= 16); | |
512 | ||
513 | return result; | |
514 | } | |
515 | ||
8680b94b MT |
516 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
517 | { | |
fc57ac2c PB |
518 | struct kvm_vcpu *vcpu; |
519 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
520 | return; | |
521 | ||
522 | vcpu = apic->vcpu; | |
523 | ||
524 | /* | |
525 | * We do get here for APIC virtualization enabled if the guest | |
526 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
527 | * to trigger a new interrupt delivery by writing the SVI field; | |
528 | * on the other hand isr_count and highest_isr_cache are unused | |
529 | * and must be left alone. | |
530 | */ | |
d62caabb | 531 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 532 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
533 | apic_find_highest_isr(apic)); |
534 | else { | |
8680b94b | 535 | --apic->isr_count; |
fc57ac2c PB |
536 | BUG_ON(apic->isr_count < 0); |
537 | apic->highest_isr_cache = -1; | |
538 | } | |
8680b94b MT |
539 | } |
540 | ||
6e5d865c YS |
541 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
542 | { | |
33e4c686 GN |
543 | /* This may race with setting of irr in __apic_accept_irq() and |
544 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
545 | * will cause vmexit immediately and the value will be recalculated | |
546 | * on the next vmentry. | |
547 | */ | |
f8543d6a | 548 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 549 | } |
76dfafd5 | 550 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); |
6e5d865c | 551 | |
6da7e3f6 | 552 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 553 | int vector, int level, int trig_mode, |
9e4aabe2 | 554 | struct dest_map *dest_map); |
6da7e3f6 | 555 | |
b4f2225c | 556 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 557 | struct dest_map *dest_map) |
97222cc8 | 558 | { |
ad312c7c | 559 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 560 | |
58c2dde1 | 561 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 562 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
563 | } |
564 | ||
1a686237 ML |
565 | static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map, |
566 | struct kvm_lapic_irq *irq, u32 min) | |
567 | { | |
568 | int i, count = 0; | |
569 | struct kvm_vcpu *vcpu; | |
570 | ||
571 | if (min > map->max_apic_id) | |
572 | return 0; | |
573 | ||
574 | for_each_set_bit(i, ipi_bitmap, | |
575 | min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { | |
576 | if (map->phys_map[min + i]) { | |
577 | vcpu = map->phys_map[min + i]->vcpu; | |
578 | count += kvm_apic_set_irq(vcpu, irq, NULL); | |
579 | } | |
580 | } | |
581 | ||
582 | return count; | |
583 | } | |
584 | ||
4180bf1b | 585 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 586 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
587 | unsigned long icr, int op_64_bit) |
588 | { | |
4180bf1b | 589 | struct kvm_apic_map *map; |
4180bf1b WL |
590 | struct kvm_lapic_irq irq = {0}; |
591 | int cluster_size = op_64_bit ? 64 : 32; | |
1a686237 ML |
592 | int count; |
593 | ||
594 | if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK)) | |
595 | return -KVM_EINVAL; | |
4180bf1b WL |
596 | |
597 | irq.vector = icr & APIC_VECTOR_MASK; | |
598 | irq.delivery_mode = icr & APIC_MODE_MASK; | |
599 | irq.level = (icr & APIC_INT_ASSERT) != 0; | |
600 | irq.trig_mode = icr & APIC_INT_LEVELTRIG; | |
601 | ||
4180bf1b WL |
602 | rcu_read_lock(); |
603 | map = rcu_dereference(kvm->arch.apic_map); | |
604 | ||
1a686237 ML |
605 | count = -EOPNOTSUPP; |
606 | if (likely(map)) { | |
607 | count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min); | |
608 | min += cluster_size; | |
609 | count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min); | |
4180bf1b WL |
610 | } |
611 | ||
612 | rcu_read_unlock(); | |
613 | return count; | |
614 | } | |
615 | ||
ae7a2a3f MT |
616 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
617 | { | |
4e335d9e PB |
618 | |
619 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
620 | sizeof(val)); | |
ae7a2a3f MT |
621 | } |
622 | ||
623 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
624 | { | |
4e335d9e PB |
625 | |
626 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
627 | sizeof(*val)); | |
ae7a2a3f MT |
628 | } |
629 | ||
630 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
631 | { | |
632 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
633 | } | |
634 | ||
635 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
636 | { | |
637 | u8 val; | |
638 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
0d88800d | 639 | printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n", |
96893977 | 640 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
641 | return val & 0x1; |
642 | } | |
643 | ||
644 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
645 | { | |
646 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
0d88800d | 647 | printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n", |
96893977 | 648 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
649 | return; |
650 | } | |
651 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
652 | } | |
653 | ||
654 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
655 | { | |
656 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
0d88800d | 657 | printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n", |
96893977 | 658 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
659 | return; |
660 | } | |
661 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
662 | } | |
663 | ||
b3c045d3 PB |
664 | static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) |
665 | { | |
3d92789f | 666 | int highest_irr; |
fa59cc00 | 667 | if (apic->vcpu->arch.apicv_active) |
76dfafd5 PB |
668 | highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu); |
669 | else | |
670 | highest_irr = apic_find_highest_irr(apic); | |
b3c045d3 PB |
671 | if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) |
672 | return -1; | |
673 | return highest_irr; | |
674 | } | |
675 | ||
676 | static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) | |
97222cc8 | 677 | { |
3842d135 | 678 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
679 | int isr; |
680 | ||
dfb95954 SS |
681 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
682 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
683 | isr = apic_find_highest_isr(apic); |
684 | isrv = (isr != -1) ? isr : 0; | |
685 | ||
686 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
687 | ppr = tpr & 0xff; | |
688 | else | |
689 | ppr = isrv & 0xf0; | |
690 | ||
b3c045d3 PB |
691 | *new_ppr = ppr; |
692 | if (old_ppr != ppr) | |
1e6e2755 | 693 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
b3c045d3 PB |
694 | |
695 | return ppr < old_ppr; | |
696 | } | |
697 | ||
698 | static void apic_update_ppr(struct kvm_lapic *apic) | |
699 | { | |
700 | u32 ppr; | |
701 | ||
26fbbee5 PB |
702 | if (__apic_update_ppr(apic, &ppr) && |
703 | apic_has_interrupt_for_ppr(apic, ppr) != -1) | |
b3c045d3 | 704 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
97222cc8 ED |
705 | } |
706 | ||
eb90f341 PB |
707 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu) |
708 | { | |
709 | apic_update_ppr(vcpu->arch.apic); | |
710 | } | |
711 | EXPORT_SYMBOL_GPL(kvm_apic_update_ppr); | |
712 | ||
97222cc8 ED |
713 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) |
714 | { | |
1e6e2755 | 715 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
716 | apic_update_ppr(apic); |
717 | } | |
718 | ||
03d2249e | 719 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 720 | { |
b4535b58 RK |
721 | return mda == (apic_x2apic_mode(apic) ? |
722 | X2APIC_BROADCAST : APIC_BROADCAST); | |
394457a9 NA |
723 | } |
724 | ||
03d2249e | 725 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 726 | { |
03d2249e RK |
727 | if (kvm_apic_broadcast(apic, mda)) |
728 | return true; | |
729 | ||
730 | if (apic_x2apic_mode(apic)) | |
6e500439 | 731 | return mda == kvm_x2apic_id(apic); |
03d2249e | 732 | |
5bd5db38 RK |
733 | /* |
734 | * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if | |
735 | * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and | |
736 | * this allows unique addressing of VCPUs with APIC ID over 0xff. | |
737 | * The 0xff condition is needed because writeable xAPIC ID. | |
738 | */ | |
739 | if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) | |
740 | return true; | |
741 | ||
b4535b58 | 742 | return mda == kvm_xapic_id(apic); |
97222cc8 ED |
743 | } |
744 | ||
52c233a4 | 745 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 746 | { |
0105d1a5 GN |
747 | u32 logical_id; |
748 | ||
394457a9 | 749 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 750 | return true; |
394457a9 | 751 | |
dfb95954 | 752 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 753 | |
9368b567 | 754 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
755 | return ((logical_id >> 16) == (mda >> 16)) |
756 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 757 | |
9368b567 | 758 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
97222cc8 | 759 | |
dfb95954 | 760 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 761 | case APIC_DFR_FLAT: |
9368b567 | 762 | return (logical_id & mda) != 0; |
97222cc8 | 763 | case APIC_DFR_CLUSTER: |
9368b567 RK |
764 | return ((logical_id >> 4) == (mda >> 4)) |
765 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 766 | default: |
9368b567 | 767 | return false; |
97222cc8 | 768 | } |
97222cc8 ED |
769 | } |
770 | ||
c519265f RK |
771 | /* The KVM local APIC implementation has two quirks: |
772 | * | |
b4535b58 RK |
773 | * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs |
774 | * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID. | |
775 | * KVM doesn't do that aliasing. | |
c519265f RK |
776 | * |
777 | * - in-kernel IOAPIC messages have to be delivered directly to | |
778 | * x2APIC, because the kernel does not support interrupt remapping. | |
779 | * In order to support broadcast without interrupt remapping, x2APIC | |
780 | * rewrites the destination of non-IPI messages from APIC_BROADCAST | |
781 | * to X2APIC_BROADCAST. | |
782 | * | |
783 | * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is | |
784 | * important when userspace wants to use x2APIC-format MSIs, because | |
785 | * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7". | |
03d2249e | 786 | */ |
c519265f RK |
787 | static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id, |
788 | struct kvm_lapic *source, struct kvm_lapic *target) | |
03d2249e RK |
789 | { |
790 | bool ipi = source != NULL; | |
03d2249e | 791 | |
c519265f | 792 | if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && |
b4535b58 | 793 | !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) |
03d2249e RK |
794 | return X2APIC_BROADCAST; |
795 | ||
b4535b58 | 796 | return dest_id; |
03d2249e RK |
797 | } |
798 | ||
52c233a4 | 799 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 800 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 801 | { |
ad312c7c | 802 | struct kvm_lapic *target = vcpu->arch.apic; |
c519265f | 803 | u32 mda = kvm_apic_mda(vcpu, dest, source, target); |
97222cc8 | 804 | |
bd371396 | 805 | ASSERT(target); |
97222cc8 ED |
806 | switch (short_hand) { |
807 | case APIC_DEST_NOSHORT: | |
3697f302 | 808 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 809 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 810 | else |
03d2249e | 811 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 812 | case APIC_DEST_SELF: |
9368b567 | 813 | return target == source; |
97222cc8 | 814 | case APIC_DEST_ALLINC: |
9368b567 | 815 | return true; |
97222cc8 | 816 | case APIC_DEST_ALLBUT: |
9368b567 | 817 | return target != source; |
97222cc8 | 818 | default: |
9368b567 | 819 | return false; |
97222cc8 | 820 | } |
97222cc8 | 821 | } |
1e6e2755 | 822 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 823 | |
52004014 FW |
824 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
825 | const unsigned long *bitmap, u32 bitmap_size) | |
826 | { | |
827 | u32 mod; | |
828 | int i, idx = -1; | |
829 | ||
830 | mod = vector % dest_vcpus; | |
831 | ||
832 | for (i = 0; i <= mod; i++) { | |
833 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
834 | BUG_ON(idx == bitmap_size); | |
835 | } | |
836 | ||
837 | return idx; | |
838 | } | |
839 | ||
4efd805f RK |
840 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
841 | { | |
842 | if (!kvm->arch.disabled_lapic_found) { | |
843 | kvm->arch.disabled_lapic_found = true; | |
844 | printk(KERN_INFO | |
845 | "Disabled LAPIC found during irq injection\n"); | |
846 | } | |
847 | } | |
848 | ||
c519265f RK |
849 | static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src, |
850 | struct kvm_lapic_irq *irq, struct kvm_apic_map *map) | |
1e08ec4a | 851 | { |
c519265f RK |
852 | if (kvm->arch.x2apic_broadcast_quirk_disabled) { |
853 | if ((irq->dest_id == APIC_BROADCAST && | |
854 | map->mode != KVM_APIC_MODE_X2APIC)) | |
855 | return true; | |
856 | if (irq->dest_id == X2APIC_BROADCAST) | |
857 | return true; | |
858 | } else { | |
859 | bool x2apic_ipi = src && *src && apic_x2apic_mode(*src); | |
860 | if (irq->dest_id == (x2apic_ipi ? | |
861 | X2APIC_BROADCAST : APIC_BROADCAST)) | |
862 | return true; | |
863 | } | |
1e08ec4a | 864 | |
c519265f RK |
865 | return false; |
866 | } | |
1e08ec4a | 867 | |
64aa47bf RK |
868 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
869 | * for valid destinations in *dst array. | |
870 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
871 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
872 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
873 | * zero and *dst undefined. | |
874 | */ | |
875 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
876 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
877 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
878 | unsigned long *bitmap) | |
879 | { | |
880 | int i, lowest; | |
1e08ec4a | 881 | |
64aa47bf RK |
882 | if (irq->shorthand == APIC_DEST_SELF && src) { |
883 | *dst = src; | |
884 | *bitmap = 1; | |
885 | return true; | |
886 | } else if (irq->shorthand) | |
1e08ec4a GN |
887 | return false; |
888 | ||
c519265f | 889 | if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map)) |
9ea369b0 RK |
890 | return false; |
891 | ||
64aa47bf | 892 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
0ca52e7b | 893 | if (irq->dest_id > map->max_apic_id) { |
64aa47bf RK |
894 | *bitmap = 0; |
895 | } else { | |
1d487e9b PB |
896 | u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1); |
897 | *dst = &map->phys_map[dest_id]; | |
64aa47bf RK |
898 | *bitmap = 1; |
899 | } | |
1e08ec4a | 900 | return true; |
bea15428 | 901 | } |
698f9755 | 902 | |
e45115b6 RK |
903 | *bitmap = 0; |
904 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
905 | (u16 *)bitmap)) | |
1e08ec4a | 906 | return false; |
fa834e91 | 907 | |
64aa47bf RK |
908 | if (!kvm_lowest_prio_delivery(irq)) |
909 | return true; | |
3548a259 | 910 | |
64aa47bf RK |
911 | if (!kvm_vector_hashing_enabled()) { |
912 | lowest = -1; | |
913 | for_each_set_bit(i, bitmap, 16) { | |
914 | if (!(*dst)[i]) | |
915 | continue; | |
916 | if (lowest < 0) | |
917 | lowest = i; | |
918 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
919 | (*dst)[lowest]->vcpu) < 0) | |
920 | lowest = i; | |
3548a259 | 921 | } |
64aa47bf RK |
922 | } else { |
923 | if (!*bitmap) | |
924 | return true; | |
3548a259 | 925 | |
64aa47bf RK |
926 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
927 | bitmap, 16); | |
45c3094a | 928 | |
64aa47bf RK |
929 | if (!(*dst)[lowest]) { |
930 | kvm_apic_disabled_lapic_found(kvm); | |
931 | *bitmap = 0; | |
932 | return true; | |
933 | } | |
934 | } | |
1e08ec4a | 935 | |
64aa47bf | 936 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 937 | |
64aa47bf RK |
938 | return true; |
939 | } | |
52004014 | 940 | |
64aa47bf RK |
941 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
942 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
943 | { | |
944 | struct kvm_apic_map *map; | |
945 | unsigned long bitmap; | |
946 | struct kvm_lapic **dst = NULL; | |
947 | int i; | |
948 | bool ret; | |
52004014 | 949 | |
64aa47bf | 950 | *r = -1; |
52004014 | 951 | |
64aa47bf RK |
952 | if (irq->shorthand == APIC_DEST_SELF) { |
953 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
954 | return true; | |
955 | } | |
52004014 | 956 | |
64aa47bf RK |
957 | rcu_read_lock(); |
958 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 959 | |
64aa47bf | 960 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
0624fca9 PB |
961 | if (ret) { |
962 | *r = 0; | |
64aa47bf RK |
963 | for_each_set_bit(i, &bitmap, 16) { |
964 | if (!dst[i]) | |
965 | continue; | |
64aa47bf | 966 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 967 | } |
0624fca9 | 968 | } |
1e08ec4a | 969 | |
1e08ec4a GN |
970 | rcu_read_unlock(); |
971 | return ret; | |
972 | } | |
973 | ||
6228a0da FW |
974 | /* |
975 | * This routine tries to handler interrupts in posted mode, here is how | |
976 | * it deals with different cases: | |
977 | * - For single-destination interrupts, handle it in posted mode | |
978 | * - Else if vector hashing is enabled and it is a lowest-priority | |
979 | * interrupt, handle it in posted mode and use the following mechanism | |
980 | * to find the destinaiton vCPU. | |
981 | * 1. For lowest-priority interrupts, store all the possible | |
982 | * destination vCPUs in an array. | |
983 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
984 | * the right destination vCPU in the array for the lowest-priority | |
985 | * interrupt. | |
986 | * - Otherwise, use remapped mode to inject the interrupt. | |
987 | */ | |
8feb4a04 FW |
988 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
989 | struct kvm_vcpu **dest_vcpu) | |
990 | { | |
991 | struct kvm_apic_map *map; | |
64aa47bf RK |
992 | unsigned long bitmap; |
993 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 994 | bool ret = false; |
8feb4a04 FW |
995 | |
996 | if (irq->shorthand) | |
997 | return false; | |
998 | ||
999 | rcu_read_lock(); | |
1000 | map = rcu_dereference(kvm->arch.apic_map); | |
1001 | ||
64aa47bf RK |
1002 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
1003 | hweight16(bitmap) == 1) { | |
1004 | unsigned long i = find_first_bit(&bitmap, 16); | |
6228a0da | 1005 | |
64aa47bf RK |
1006 | if (dst[i]) { |
1007 | *dest_vcpu = dst[i]->vcpu; | |
1008 | ret = true; | |
6228a0da | 1009 | } |
8feb4a04 FW |
1010 | } |
1011 | ||
8feb4a04 FW |
1012 | rcu_read_unlock(); |
1013 | return ret; | |
1014 | } | |
1015 | ||
97222cc8 ED |
1016 | /* |
1017 | * Add a pending IRQ into lapic. | |
1018 | * Return 1 if successfully added and 0 if discarded. | |
1019 | */ | |
1020 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 1021 | int vector, int level, int trig_mode, |
9e4aabe2 | 1022 | struct dest_map *dest_map) |
97222cc8 | 1023 | { |
6da7e3f6 | 1024 | int result = 0; |
c5ec1534 | 1025 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 1026 | |
a183b638 PB |
1027 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
1028 | trig_mode, vector); | |
97222cc8 | 1029 | switch (delivery_mode) { |
97222cc8 | 1030 | case APIC_DM_LOWEST: |
e1035715 | 1031 | vcpu->arch.apic_arb_prio++; |
b2869f28 | 1032 | /* fall through */ |
e1035715 | 1033 | case APIC_DM_FIXED: |
bdaffe1d PB |
1034 | if (unlikely(trig_mode && !level)) |
1035 | break; | |
1036 | ||
97222cc8 ED |
1037 | /* FIXME add logic for vcpu on reset */ |
1038 | if (unlikely(!apic_enabled(apic))) | |
1039 | break; | |
1040 | ||
11f5cc05 JK |
1041 | result = 1; |
1042 | ||
9daa5007 | 1043 | if (dest_map) { |
9e4aabe2 | 1044 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
1045 | dest_map->vectors[vcpu->vcpu_id] = vector; |
1046 | } | |
a5d36f82 | 1047 | |
bdaffe1d PB |
1048 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
1049 | if (trig_mode) | |
ee171d2f WY |
1050 | kvm_lapic_set_vector(vector, |
1051 | apic->regs + APIC_TMR); | |
bdaffe1d | 1052 | else |
ee171d2f WY |
1053 | kvm_lapic_clear_vector(vector, |
1054 | apic->regs + APIC_TMR); | |
bdaffe1d PB |
1055 | } |
1056 | ||
d62caabb | 1057 | if (vcpu->arch.apicv_active) |
5a71785d | 1058 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 1059 | else { |
1e6e2755 | 1060 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
1061 | |
1062 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1063 | kvm_vcpu_kick(vcpu); | |
1064 | } | |
97222cc8 ED |
1065 | break; |
1066 | ||
1067 | case APIC_DM_REMRD: | |
24d2166b R |
1068 | result = 1; |
1069 | vcpu->arch.pv.pv_unhalted = 1; | |
1070 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1071 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1072 | break; |
1073 | ||
1074 | case APIC_DM_SMI: | |
64d60670 PB |
1075 | result = 1; |
1076 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
1077 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 1078 | break; |
3419ffc8 | 1079 | |
97222cc8 | 1080 | case APIC_DM_NMI: |
6da7e3f6 | 1081 | result = 1; |
3419ffc8 | 1082 | kvm_inject_nmi(vcpu); |
26df99c6 | 1083 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
1084 | break; |
1085 | ||
1086 | case APIC_DM_INIT: | |
a52315e1 | 1087 | if (!trig_mode || level) { |
6da7e3f6 | 1088 | result = 1; |
66450a21 JK |
1089 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
1090 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
1091 | /* make sure pending_events is visible before sending | |
1092 | * the request */ | |
1093 | smp_wmb(); | |
3842d135 | 1094 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 | 1095 | kvm_vcpu_kick(vcpu); |
c5ec1534 | 1096 | } |
97222cc8 ED |
1097 | break; |
1098 | ||
1099 | case APIC_DM_STARTUP: | |
66450a21 JK |
1100 | result = 1; |
1101 | apic->sipi_vector = vector; | |
1102 | /* make sure sipi_vector is visible for the receiver */ | |
1103 | smp_wmb(); | |
1104 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
1105 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1106 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1107 | break; |
1108 | ||
23930f95 JK |
1109 | case APIC_DM_EXTINT: |
1110 | /* | |
1111 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
1112 | * before NMI watchdog was enabled. Already handled by | |
1113 | * kvm_apic_accept_pic_intr(). | |
1114 | */ | |
1115 | break; | |
1116 | ||
97222cc8 ED |
1117 | default: |
1118 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
1119 | delivery_mode); | |
1120 | break; | |
1121 | } | |
1122 | return result; | |
1123 | } | |
1124 | ||
7ee30bc1 NNL |
1125 | /* |
1126 | * This routine identifies the destination vcpus mask meant to receive the | |
1127 | * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find | |
1128 | * out the destination vcpus array and set the bitmap or it traverses to | |
1129 | * each available vcpu to identify the same. | |
1130 | */ | |
1131 | void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, | |
1132 | unsigned long *vcpu_bitmap) | |
1133 | { | |
1134 | struct kvm_lapic **dest_vcpu = NULL; | |
1135 | struct kvm_lapic *src = NULL; | |
1136 | struct kvm_apic_map *map; | |
1137 | struct kvm_vcpu *vcpu; | |
1138 | unsigned long bitmap; | |
1139 | int i, vcpu_idx; | |
1140 | bool ret; | |
1141 | ||
1142 | rcu_read_lock(); | |
1143 | map = rcu_dereference(kvm->arch.apic_map); | |
1144 | ||
1145 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu, | |
1146 | &bitmap); | |
1147 | if (ret) { | |
1148 | for_each_set_bit(i, &bitmap, 16) { | |
1149 | if (!dest_vcpu[i]) | |
1150 | continue; | |
1151 | vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx; | |
1152 | __set_bit(vcpu_idx, vcpu_bitmap); | |
1153 | } | |
1154 | } else { | |
1155 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1156 | if (!kvm_apic_present(vcpu)) | |
1157 | continue; | |
1158 | if (!kvm_apic_match_dest(vcpu, NULL, | |
1159 | irq->delivery_mode, | |
1160 | irq->dest_id, | |
1161 | irq->dest_mode)) | |
1162 | continue; | |
1163 | __set_bit(i, vcpu_bitmap); | |
1164 | } | |
1165 | } | |
1166 | rcu_read_unlock(); | |
1167 | } | |
1168 | ||
e1035715 | 1169 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 1170 | { |
e1035715 | 1171 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
1172 | } |
1173 | ||
3bb345f3 PB |
1174 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
1175 | { | |
6308630b | 1176 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
1177 | } |
1178 | ||
c7c9c56c YZ |
1179 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
1180 | { | |
7543a635 SR |
1181 | int trigger_mode; |
1182 | ||
1183 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
1184 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
1185 | return; | |
3bb345f3 | 1186 | |
7543a635 SR |
1187 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
1188 | if (irqchip_split(apic->vcpu->kvm)) { | |
1189 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
1190 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
1191 | return; | |
c7c9c56c | 1192 | } |
7543a635 SR |
1193 | |
1194 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
1195 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
1196 | else | |
1197 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1198 | ||
1199 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
1200 | } |
1201 | ||
ae7a2a3f | 1202 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
1203 | { |
1204 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
1205 | |
1206 | trace_kvm_eoi(apic, vector); | |
1207 | ||
97222cc8 ED |
1208 | /* |
1209 | * Not every write EOI will has corresponding ISR, | |
1210 | * one example is when Kernel check timer on setup_IO_APIC | |
1211 | */ | |
1212 | if (vector == -1) | |
ae7a2a3f | 1213 | return vector; |
97222cc8 | 1214 | |
8680b94b | 1215 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1216 | apic_update_ppr(apic); |
1217 | ||
5c919412 AS |
1218 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
1219 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
1220 | ||
c7c9c56c | 1221 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1222 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1223 | return vector; |
97222cc8 ED |
1224 | } |
1225 | ||
c7c9c56c YZ |
1226 | /* |
1227 | * this interface assumes a trap-like exit, which has already finished | |
1228 | * desired side effect including vISR and vPPR update. | |
1229 | */ | |
1230 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1231 | { | |
1232 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1233 | ||
1234 | trace_kvm_eoi(apic, vector); | |
1235 | ||
1236 | kvm_ioapic_send_eoi(apic, vector); | |
1237 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1238 | } | |
1239 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1240 | ||
2b0911d1 | 1241 | static void apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) |
97222cc8 | 1242 | { |
58c2dde1 | 1243 | struct kvm_lapic_irq irq; |
97222cc8 | 1244 | |
58c2dde1 GN |
1245 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1246 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1247 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1248 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1249 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1250 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1251 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1252 | if (apic_x2apic_mode(apic)) |
1253 | irq.dest_id = icr_high; | |
1254 | else | |
1255 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1256 | |
1000ff8d GN |
1257 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1258 | ||
b4f2225c | 1259 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1260 | } |
1261 | ||
1262 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1263 | { | |
8003c9ae | 1264 | ktime_t remaining, now; |
b682b814 | 1265 | s64 ns; |
9da8f4e8 | 1266 | u32 tmcct; |
97222cc8 ED |
1267 | |
1268 | ASSERT(apic != NULL); | |
1269 | ||
9da8f4e8 | 1270 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1271 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1272 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1273 | return 0; |
1274 | ||
5587859f | 1275 | now = ktime_get(); |
8003c9ae | 1276 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); |
b682b814 | 1277 | if (ktime_to_ns(remaining) < 0) |
8b0e1953 | 1278 | remaining = 0; |
b682b814 | 1279 | |
d3c7b77d MT |
1280 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1281 | tmcct = div64_u64(ns, | |
1282 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1283 | |
1284 | return tmcct; | |
1285 | } | |
1286 | ||
b209749f AK |
1287 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1288 | { | |
1289 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1290 | struct kvm_run *run = vcpu->run; | |
1291 | ||
a8eeb04a | 1292 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1293 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1294 | run->tpr_access.is_write = write; |
1295 | } | |
1296 | ||
1297 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1298 | { | |
1299 | if (apic->vcpu->arch.tpr_access_reporting) | |
1300 | __report_tpr_access(apic, write); | |
1301 | } | |
1302 | ||
97222cc8 ED |
1303 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1304 | { | |
1305 | u32 val = 0; | |
1306 | ||
1307 | if (offset >= LAPIC_MMIO_LENGTH) | |
1308 | return 0; | |
1309 | ||
1310 | switch (offset) { | |
1311 | case APIC_ARBPRI: | |
97222cc8 ED |
1312 | break; |
1313 | ||
1314 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1315 | if (apic_lvtt_tscdeadline(apic)) |
1316 | return 0; | |
1317 | ||
97222cc8 ED |
1318 | val = apic_get_tmcct(apic); |
1319 | break; | |
4a4541a4 AK |
1320 | case APIC_PROCPRI: |
1321 | apic_update_ppr(apic); | |
dfb95954 | 1322 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1323 | break; |
b209749f AK |
1324 | case APIC_TASKPRI: |
1325 | report_tpr_access(apic, false); | |
1326 | /* fall thru */ | |
97222cc8 | 1327 | default: |
dfb95954 | 1328 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1329 | break; |
1330 | } | |
1331 | ||
1332 | return val; | |
1333 | } | |
1334 | ||
d76685c4 GH |
1335 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1336 | { | |
1337 | return container_of(dev, struct kvm_lapic, dev); | |
1338 | } | |
1339 | ||
01402cf8 PB |
1340 | #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4)) |
1341 | #define APIC_REGS_MASK(first, count) \ | |
1342 | (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) | |
1343 | ||
1e6e2755 | 1344 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1345 | void *data) |
97222cc8 | 1346 | { |
97222cc8 ED |
1347 | unsigned char alignment = offset & 0xf; |
1348 | u32 result; | |
d5b0b5b1 | 1349 | /* this bitmask has a bit cleared for each reserved register */ |
01402cf8 PB |
1350 | u64 valid_reg_mask = |
1351 | APIC_REG_MASK(APIC_ID) | | |
1352 | APIC_REG_MASK(APIC_LVR) | | |
1353 | APIC_REG_MASK(APIC_TASKPRI) | | |
1354 | APIC_REG_MASK(APIC_PROCPRI) | | |
1355 | APIC_REG_MASK(APIC_LDR) | | |
1356 | APIC_REG_MASK(APIC_DFR) | | |
1357 | APIC_REG_MASK(APIC_SPIV) | | |
1358 | APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) | | |
1359 | APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) | | |
1360 | APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) | | |
1361 | APIC_REG_MASK(APIC_ESR) | | |
1362 | APIC_REG_MASK(APIC_ICR) | | |
1363 | APIC_REG_MASK(APIC_ICR2) | | |
1364 | APIC_REG_MASK(APIC_LVTT) | | |
1365 | APIC_REG_MASK(APIC_LVTTHMR) | | |
1366 | APIC_REG_MASK(APIC_LVTPC) | | |
1367 | APIC_REG_MASK(APIC_LVT0) | | |
1368 | APIC_REG_MASK(APIC_LVT1) | | |
1369 | APIC_REG_MASK(APIC_LVTERR) | | |
1370 | APIC_REG_MASK(APIC_TMICT) | | |
1371 | APIC_REG_MASK(APIC_TMCCT) | | |
1372 | APIC_REG_MASK(APIC_TDCR); | |
1373 | ||
1374 | /* ARBPRI is not valid on x2APIC */ | |
1375 | if (!apic_x2apic_mode(apic)) | |
1376 | valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI); | |
0105d1a5 | 1377 | |
0d88800d | 1378 | if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) |
0105d1a5 | 1379 | return 1; |
0105d1a5 | 1380 | |
97222cc8 ED |
1381 | result = __apic_read(apic, offset & ~0xf); |
1382 | ||
229456fc MT |
1383 | trace_kvm_apic_read(offset, result); |
1384 | ||
97222cc8 ED |
1385 | switch (len) { |
1386 | case 1: | |
1387 | case 2: | |
1388 | case 4: | |
1389 | memcpy(data, (char *)&result + alignment, len); | |
1390 | break; | |
1391 | default: | |
1392 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1393 | "should be 1,2, or 4 instead\n", len); | |
1394 | break; | |
1395 | } | |
bda9020e | 1396 | return 0; |
97222cc8 | 1397 | } |
1e6e2755 | 1398 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1399 | |
0105d1a5 GN |
1400 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1401 | { | |
d1766202 VK |
1402 | return addr >= apic->base_address && |
1403 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
0105d1a5 GN |
1404 | } |
1405 | ||
e32edf4f | 1406 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1407 | gpa_t address, int len, void *data) |
1408 | { | |
1409 | struct kvm_lapic *apic = to_lapic(this); | |
1410 | u32 offset = address - apic->base_address; | |
1411 | ||
1412 | if (!apic_mmio_in_range(apic, address)) | |
1413 | return -EOPNOTSUPP; | |
1414 | ||
d1766202 VK |
1415 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
1416 | if (!kvm_check_has_quirk(vcpu->kvm, | |
1417 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
1418 | return -EOPNOTSUPP; | |
1419 | ||
1420 | memset(data, 0xff, len); | |
1421 | return 0; | |
1422 | } | |
1423 | ||
1e6e2755 | 1424 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
97222cc8 ED |
1429 | static void update_divide_count(struct kvm_lapic *apic) |
1430 | { | |
1431 | u32 tmp1, tmp2, tdcr; | |
1432 | ||
dfb95954 | 1433 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1434 | tmp1 = tdcr & 0xf; |
1435 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1436 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1437 | } |
1438 | ||
ccbfa1d3 WL |
1439 | static void limit_periodic_timer_frequency(struct kvm_lapic *apic) |
1440 | { | |
1441 | /* | |
1442 | * Do not allow the guest to program periodic timers with small | |
1443 | * interval, since the hrtimers are not throttled by the host | |
1444 | * scheduler. | |
1445 | */ | |
dedf9c5e | 1446 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { |
ccbfa1d3 WL |
1447 | s64 min_period = min_timer_period_us * 1000LL; |
1448 | ||
1449 | if (apic->lapic_timer.period < min_period) { | |
1450 | pr_info_ratelimited( | |
1451 | "kvm: vcpu %i: requested %lld ns " | |
1452 | "lapic timer period limited to %lld ns\n", | |
1453 | apic->vcpu->vcpu_id, | |
1454 | apic->lapic_timer.period, min_period); | |
1455 | apic->lapic_timer.period = min_period; | |
1456 | } | |
1457 | } | |
1458 | } | |
1459 | ||
b6ac0695 RK |
1460 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1461 | { | |
dfb95954 | 1462 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1463 | apic->lapic_timer.timer_mode_mask; |
1464 | ||
1465 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
c69518c8 | 1466 | if (apic_lvtt_tscdeadline(apic) != (timer_mode == |
dedf9c5e | 1467 | APIC_LVT_TIMER_TSCDEADLINE)) { |
dedf9c5e | 1468 | hrtimer_cancel(&apic->lapic_timer.timer); |
44275932 RK |
1469 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); |
1470 | apic->lapic_timer.period = 0; | |
1471 | apic->lapic_timer.tscdeadline = 0; | |
dedf9c5e | 1472 | } |
b6ac0695 | 1473 | apic->lapic_timer.timer_mode = timer_mode; |
dedf9c5e | 1474 | limit_periodic_timer_frequency(apic); |
b6ac0695 RK |
1475 | } |
1476 | } | |
1477 | ||
d0659d94 MT |
1478 | /* |
1479 | * On APICv, this test will cause a busy wait | |
1480 | * during a higher-priority task. | |
1481 | */ | |
1482 | ||
1483 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1484 | { | |
1485 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1486 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1487 | |
1488 | if (kvm_apic_hw_enabled(apic)) { | |
1489 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1490 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1491 | |
d62caabb | 1492 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1493 | bitmap = apic->regs + APIC_IRR; |
1494 | ||
1495 | if (apic_test_vector(vec, bitmap)) | |
1496 | return true; | |
d0659d94 MT |
1497 | } |
1498 | return false; | |
1499 | } | |
1500 | ||
b6aa57c6 SC |
1501 | static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles) |
1502 | { | |
1503 | u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; | |
1504 | ||
1505 | /* | |
1506 | * If the guest TSC is running at a different ratio than the host, then | |
1507 | * convert the delay to nanoseconds to achieve an accurate delay. Note | |
1508 | * that __delay() uses delay_tsc whenever the hardware has TSC, thus | |
1509 | * always for VMX enabled hardware. | |
1510 | */ | |
1511 | if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) { | |
1512 | __delay(min(guest_cycles, | |
1513 | nsec_to_cycles(vcpu, timer_advance_ns))); | |
1514 | } else { | |
1515 | u64 delay_ns = guest_cycles * 1000000ULL; | |
1516 | do_div(delay_ns, vcpu->arch.virtual_tsc_khz); | |
1517 | ndelay(min_t(u32, delay_ns, timer_advance_ns)); | |
1518 | } | |
1519 | } | |
1520 | ||
84ea3aca | 1521 | static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu, |
ec0671d5 | 1522 | s64 advance_expire_delta) |
d0659d94 MT |
1523 | { |
1524 | struct kvm_lapic *apic = vcpu->arch.apic; | |
39497d76 | 1525 | u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; |
84ea3aca WL |
1526 | u64 ns; |
1527 | ||
d0f5a86a WL |
1528 | /* Do not adjust for tiny fluctuations or large random spikes. */ |
1529 | if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX || | |
1530 | abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN) | |
1531 | return; | |
1532 | ||
84ea3aca | 1533 | /* too early */ |
ec0671d5 WL |
1534 | if (advance_expire_delta < 0) { |
1535 | ns = -advance_expire_delta * 1000000ULL; | |
84ea3aca | 1536 | do_div(ns, vcpu->arch.virtual_tsc_khz); |
d0f5a86a | 1537 | timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; |
84ea3aca WL |
1538 | } else { |
1539 | /* too late */ | |
ec0671d5 | 1540 | ns = advance_expire_delta * 1000000ULL; |
84ea3aca | 1541 | do_div(ns, vcpu->arch.virtual_tsc_khz); |
d0f5a86a | 1542 | timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; |
84ea3aca WL |
1543 | } |
1544 | ||
a0f0037e WL |
1545 | if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX)) |
1546 | timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; | |
84ea3aca WL |
1547 | apic->lapic_timer.timer_advance_ns = timer_advance_ns; |
1548 | } | |
1549 | ||
0c5f81da | 1550 | static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) |
84ea3aca WL |
1551 | { |
1552 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1553 | u64 guest_tsc, tsc_deadline; | |
d0659d94 | 1554 | |
d0659d94 MT |
1555 | if (apic->lapic_timer.expired_tscdeadline == 0) |
1556 | return; | |
1557 | ||
d0659d94 MT |
1558 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; |
1559 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1560 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
ec0671d5 | 1561 | apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline; |
d0659d94 | 1562 | |
d0659d94 | 1563 | if (guest_tsc < tsc_deadline) |
b6aa57c6 | 1564 | __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc); |
3b8a5df6 | 1565 | |
d0f5a86a | 1566 | if (lapic_timer_advance_dynamic) |
ec0671d5 | 1567 | adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta); |
5d87db71 | 1568 | } |
0c5f81da WL |
1569 | |
1570 | void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1571 | { | |
1572 | if (lapic_timer_int_injected(vcpu)) | |
1573 | __kvm_wait_lapic_expire(vcpu); | |
1574 | } | |
b6c4bc65 | 1575 | EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire); |
5d87db71 | 1576 | |
0c5f81da WL |
1577 | static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) |
1578 | { | |
1579 | struct kvm_timer *ktimer = &apic->lapic_timer; | |
1580 | ||
1581 | kvm_apic_local_deliver(apic, APIC_LVTT); | |
1582 | if (apic_lvtt_tscdeadline(apic)) | |
1583 | ktimer->tscdeadline = 0; | |
1584 | if (apic_lvtt_oneshot(apic)) { | |
1585 | ktimer->tscdeadline = 0; | |
1586 | ktimer->target_expiration = 0; | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | static void apic_timer_expired(struct kvm_lapic *apic) | |
1591 | { | |
1592 | struct kvm_vcpu *vcpu = apic->vcpu; | |
0c5f81da WL |
1593 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1594 | ||
1595 | if (atomic_read(&apic->lapic_timer.pending)) | |
1596 | return; | |
1597 | ||
1598 | if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) | |
1599 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1600 | ||
1601 | if (kvm_use_posted_timer_interrupt(apic->vcpu)) { | |
1602 | if (apic->lapic_timer.timer_advance_ns) | |
1603 | __kvm_wait_lapic_expire(vcpu); | |
1604 | kvm_apic_inject_pending_timer_irqs(apic); | |
1605 | return; | |
1606 | } | |
1607 | ||
1608 | atomic_inc(&apic->lapic_timer.pending); | |
1609 | kvm_set_pending_timer(vcpu); | |
0c5f81da WL |
1610 | } |
1611 | ||
53f9eedf YJ |
1612 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1613 | { | |
39497d76 SC |
1614 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1615 | u64 guest_tsc, tscdeadline = ktimer->tscdeadline; | |
53f9eedf YJ |
1616 | u64 ns = 0; |
1617 | ktime_t expire; | |
1618 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1619 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1620 | unsigned long flags; | |
1621 | ktime_t now; | |
1622 | ||
1623 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1624 | return; | |
1625 | ||
1626 | local_irq_save(flags); | |
1627 | ||
5587859f | 1628 | now = ktime_get(); |
53f9eedf | 1629 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
c09d65d9 LA |
1630 | |
1631 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1632 | do_div(ns, this_tsc_khz); | |
1633 | ||
1634 | if (likely(tscdeadline > guest_tsc) && | |
39497d76 | 1635 | likely(ns > apic->lapic_timer.timer_advance_ns)) { |
53f9eedf | 1636 | expire = ktime_add_ns(now, ns); |
39497d76 | 1637 | expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); |
2c0d278f | 1638 | hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD); |
53f9eedf YJ |
1639 | } else |
1640 | apic_timer_expired(apic); | |
1641 | ||
1642 | local_irq_restore(flags); | |
1643 | } | |
1644 | ||
c301b909 WL |
1645 | static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) |
1646 | { | |
1647 | ktime_t now, remaining; | |
1648 | u64 ns_remaining_old, ns_remaining_new; | |
1649 | ||
1650 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) | |
1651 | * APIC_BUS_CYCLE_NS * apic->divide_count; | |
1652 | limit_periodic_timer_frequency(apic); | |
1653 | ||
1654 | now = ktime_get(); | |
1655 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); | |
1656 | if (ktime_to_ns(remaining) < 0) | |
1657 | remaining = 0; | |
1658 | ||
1659 | ns_remaining_old = ktime_to_ns(remaining); | |
1660 | ns_remaining_new = mul_u64_u32_div(ns_remaining_old, | |
1661 | apic->divide_count, old_divisor); | |
1662 | ||
1663 | apic->lapic_timer.tscdeadline += | |
1664 | nsec_to_cycles(apic->vcpu, ns_remaining_new) - | |
1665 | nsec_to_cycles(apic->vcpu, ns_remaining_old); | |
1666 | apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); | |
1667 | } | |
1668 | ||
8003c9ae | 1669 | static bool set_target_expiration(struct kvm_lapic *apic) |
7d7f7da2 WL |
1670 | { |
1671 | ktime_t now; | |
8003c9ae | 1672 | u64 tscl = rdtsc(); |
7d7f7da2 | 1673 | |
5587859f | 1674 | now = ktime_get(); |
7d7f7da2 | 1675 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
8003c9ae | 1676 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
7d7f7da2 | 1677 | |
5d74a699 RK |
1678 | if (!apic->lapic_timer.period) { |
1679 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae | 1680 | return false; |
7d7f7da2 WL |
1681 | } |
1682 | ||
ccbfa1d3 | 1683 | limit_periodic_timer_frequency(apic); |
7d7f7da2 | 1684 | |
8003c9ae WL |
1685 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + |
1686 | nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); | |
1687 | apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); | |
1688 | ||
1689 | return true; | |
1690 | } | |
1691 | ||
1692 | static void advance_periodic_target_expiration(struct kvm_lapic *apic) | |
1693 | { | |
d8f2f498 DV |
1694 | ktime_t now = ktime_get(); |
1695 | u64 tscl = rdtsc(); | |
1696 | ktime_t delta; | |
1697 | ||
1698 | /* | |
1699 | * Synchronize both deadlines to the same time source or | |
1700 | * differences in the periods (caused by differences in the | |
1701 | * underlying clocks or numerical approximation errors) will | |
1702 | * cause the two to drift apart over time as the errors | |
1703 | * accumulate. | |
1704 | */ | |
8003c9ae WL |
1705 | apic->lapic_timer.target_expiration = |
1706 | ktime_add_ns(apic->lapic_timer.target_expiration, | |
1707 | apic->lapic_timer.period); | |
d8f2f498 DV |
1708 | delta = ktime_sub(apic->lapic_timer.target_expiration, now); |
1709 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + | |
1710 | nsec_to_cycles(apic->vcpu, delta); | |
7d7f7da2 WL |
1711 | } |
1712 | ||
ecf08dad AB |
1713 | static void start_sw_period(struct kvm_lapic *apic) |
1714 | { | |
1715 | if (!apic->lapic_timer.period) | |
1716 | return; | |
1717 | ||
1718 | if (ktime_after(ktime_get(), | |
1719 | apic->lapic_timer.target_expiration)) { | |
1720 | apic_timer_expired(apic); | |
1721 | ||
1722 | if (apic_lvtt_oneshot(apic)) | |
1723 | return; | |
1724 | ||
1725 | advance_periodic_target_expiration(apic); | |
1726 | } | |
1727 | ||
1728 | hrtimer_start(&apic->lapic_timer.timer, | |
1729 | apic->lapic_timer.target_expiration, | |
4d151bf3 | 1730 | HRTIMER_MODE_ABS); |
ecf08dad AB |
1731 | } |
1732 | ||
ce7a058a YJ |
1733 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1734 | { | |
91005300 WL |
1735 | if (!lapic_in_kernel(vcpu)) |
1736 | return false; | |
1737 | ||
ce7a058a YJ |
1738 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; |
1739 | } | |
1740 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1741 | ||
7e810a38 | 1742 | static void cancel_hv_timer(struct kvm_lapic *apic) |
bd97ad0e | 1743 | { |
1d518c68 | 1744 | WARN_ON(preemptible()); |
a749e247 | 1745 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
bd97ad0e WL |
1746 | kvm_x86_ops->cancel_hv_timer(apic->vcpu); |
1747 | apic->lapic_timer.hv_timer_in_use = false; | |
1748 | } | |
1749 | ||
a749e247 | 1750 | static bool start_hv_timer(struct kvm_lapic *apic) |
196f20ca | 1751 | { |
35ee9e48 | 1752 | struct kvm_timer *ktimer = &apic->lapic_timer; |
f9927982 SC |
1753 | struct kvm_vcpu *vcpu = apic->vcpu; |
1754 | bool expired; | |
196f20ca | 1755 | |
1d518c68 | 1756 | WARN_ON(preemptible()); |
a749e247 PB |
1757 | if (!kvm_x86_ops->set_hv_timer) |
1758 | return false; | |
1759 | ||
86bbc1e6 RK |
1760 | if (!ktimer->tscdeadline) |
1761 | return false; | |
1762 | ||
f9927982 | 1763 | if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired)) |
35ee9e48 PB |
1764 | return false; |
1765 | ||
1766 | ktimer->hv_timer_in_use = true; | |
1767 | hrtimer_cancel(&ktimer->timer); | |
196f20ca | 1768 | |
35ee9e48 | 1769 | /* |
f1ba5cfb SC |
1770 | * To simplify handling the periodic timer, leave the hv timer running |
1771 | * even if the deadline timer has expired, i.e. rely on the resulting | |
1772 | * VM-Exit to recompute the periodic timer's target expiration. | |
35ee9e48 | 1773 | */ |
f1ba5cfb SC |
1774 | if (!apic_lvtt_period(apic)) { |
1775 | /* | |
1776 | * Cancel the hv timer if the sw timer fired while the hv timer | |
1777 | * was being programmed, or if the hv timer itself expired. | |
1778 | */ | |
1779 | if (atomic_read(&ktimer->pending)) { | |
1780 | cancel_hv_timer(apic); | |
f9927982 | 1781 | } else if (expired) { |
c8533544 | 1782 | apic_timer_expired(apic); |
f1ba5cfb SC |
1783 | cancel_hv_timer(apic); |
1784 | } | |
c8533544 | 1785 | } |
a749e247 | 1786 | |
f9927982 | 1787 | trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use); |
f1ba5cfb | 1788 | |
35ee9e48 PB |
1789 | return true; |
1790 | } | |
1791 | ||
a749e247 | 1792 | static void start_sw_timer(struct kvm_lapic *apic) |
35ee9e48 | 1793 | { |
a749e247 | 1794 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1d518c68 WL |
1795 | |
1796 | WARN_ON(preemptible()); | |
a749e247 PB |
1797 | if (apic->lapic_timer.hv_timer_in_use) |
1798 | cancel_hv_timer(apic); | |
1799 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) | |
1800 | return; | |
1801 | ||
1802 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) | |
1803 | start_sw_period(apic); | |
1804 | else if (apic_lvtt_tscdeadline(apic)) | |
1805 | start_sw_tscdeadline(apic); | |
1806 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); | |
1807 | } | |
35ee9e48 | 1808 | |
a749e247 PB |
1809 | static void restart_apic_timer(struct kvm_lapic *apic) |
1810 | { | |
1d518c68 | 1811 | preempt_disable(); |
4ca88b3f SC |
1812 | |
1813 | if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) | |
1814 | goto out; | |
1815 | ||
a749e247 PB |
1816 | if (!start_hv_timer(apic)) |
1817 | start_sw_timer(apic); | |
4ca88b3f | 1818 | out: |
1d518c68 | 1819 | preempt_enable(); |
196f20ca WL |
1820 | } |
1821 | ||
8003c9ae WL |
1822 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1823 | { | |
1824 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1825 | ||
1d518c68 WL |
1826 | preempt_disable(); |
1827 | /* If the preempt notifier has already run, it also called apic_timer_expired */ | |
1828 | if (!apic->lapic_timer.hv_timer_in_use) | |
1829 | goto out; | |
8003c9ae WL |
1830 | WARN_ON(swait_active(&vcpu->wq)); |
1831 | cancel_hv_timer(apic); | |
1832 | apic_timer_expired(apic); | |
1833 | ||
1834 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { | |
1835 | advance_periodic_target_expiration(apic); | |
a749e247 | 1836 | restart_apic_timer(apic); |
8003c9ae | 1837 | } |
1d518c68 WL |
1838 | out: |
1839 | preempt_enable(); | |
8003c9ae WL |
1840 | } |
1841 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1842 | ||
ce7a058a YJ |
1843 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1844 | { | |
a749e247 | 1845 | restart_apic_timer(vcpu->arch.apic); |
ce7a058a YJ |
1846 | } |
1847 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1848 | ||
1849 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1850 | { | |
1851 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1852 | ||
1d518c68 | 1853 | preempt_disable(); |
ce7a058a | 1854 | /* Possibly the TSC deadline timer is not enabled yet */ |
a749e247 PB |
1855 | if (apic->lapic_timer.hv_timer_in_use) |
1856 | start_sw_timer(apic); | |
1d518c68 | 1857 | preempt_enable(); |
a749e247 PB |
1858 | } |
1859 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
ce7a058a | 1860 | |
a749e247 PB |
1861 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) |
1862 | { | |
1863 | struct kvm_lapic *apic = vcpu->arch.apic; | |
ce7a058a | 1864 | |
a749e247 PB |
1865 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
1866 | restart_apic_timer(apic); | |
ce7a058a | 1867 | } |
ce7a058a | 1868 | |
97222cc8 ED |
1869 | static void start_apic_timer(struct kvm_lapic *apic) |
1870 | { | |
d3c7b77d | 1871 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1872 | |
a749e247 PB |
1873 | if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) |
1874 | && !set_target_expiration(apic)) | |
1875 | return; | |
1876 | ||
1877 | restart_apic_timer(apic); | |
97222cc8 ED |
1878 | } |
1879 | ||
cc6e462c JK |
1880 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1881 | { | |
59fd1323 | 1882 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1883 | |
59fd1323 RK |
1884 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1885 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1886 | if (lvt0_in_nmi_mode) { | |
42720138 | 1887 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1888 | } else |
1889 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1890 | } | |
cc6e462c JK |
1891 | } |
1892 | ||
1e6e2755 | 1893 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1894 | { |
0105d1a5 | 1895 | int ret = 0; |
97222cc8 | 1896 | |
0105d1a5 | 1897 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1898 | |
0105d1a5 | 1899 | switch (reg) { |
97222cc8 | 1900 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1901 | if (!apic_x2apic_mode(apic)) |
a92e2543 | 1902 | kvm_apic_set_xapic_id(apic, val >> 24); |
0105d1a5 GN |
1903 | else |
1904 | ret = 1; | |
97222cc8 ED |
1905 | break; |
1906 | ||
1907 | case APIC_TASKPRI: | |
b209749f | 1908 | report_tpr_access(apic, true); |
97222cc8 ED |
1909 | apic_set_tpr(apic, val & 0xff); |
1910 | break; | |
1911 | ||
1912 | case APIC_EOI: | |
1913 | apic_set_eoi(apic); | |
1914 | break; | |
1915 | ||
1916 | case APIC_LDR: | |
0105d1a5 | 1917 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1918 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1919 | else |
1920 | ret = 1; | |
97222cc8 ED |
1921 | break; |
1922 | ||
1923 | case APIC_DFR: | |
1e08ec4a | 1924 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1925 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1926 | recalculate_apic_map(apic->vcpu->kvm); |
1927 | } else | |
0105d1a5 | 1928 | ret = 1; |
97222cc8 ED |
1929 | break; |
1930 | ||
fc61b800 GN |
1931 | case APIC_SPIV: { |
1932 | u32 mask = 0x3ff; | |
dfb95954 | 1933 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1934 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1935 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1936 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1937 | int i; | |
1938 | u32 lvt_val; | |
1939 | ||
1e6e2755 | 1940 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1941 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1942 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1943 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1944 | lvt_val | APIC_LVT_MASKED); |
1945 | } | |
b6ac0695 | 1946 | apic_update_lvtt(apic); |
d3c7b77d | 1947 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1948 | |
1949 | } | |
1950 | break; | |
fc61b800 | 1951 | } |
97222cc8 ED |
1952 | case APIC_ICR: |
1953 | /* No delay here, so we always clear the pending bit */ | |
2b0911d1 WL |
1954 | val &= ~(1 << 12); |
1955 | apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); | |
1956 | kvm_lapic_set_reg(apic, APIC_ICR, val); | |
97222cc8 ED |
1957 | break; |
1958 | ||
1959 | case APIC_ICR2: | |
0105d1a5 GN |
1960 | if (!apic_x2apic_mode(apic)) |
1961 | val &= 0xff000000; | |
1e6e2755 | 1962 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1963 | break; |
1964 | ||
23930f95 | 1965 | case APIC_LVT0: |
cc6e462c | 1966 | apic_manage_nmi_watchdog(apic, val); |
b2869f28 | 1967 | /* fall through */ |
97222cc8 ED |
1968 | case APIC_LVTTHMR: |
1969 | case APIC_LVTPC: | |
97222cc8 ED |
1970 | case APIC_LVT1: |
1971 | case APIC_LVTERR: | |
1972 | /* TODO: Check vector */ | |
c48f1496 | 1973 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1974 | val |= APIC_LVT_MASKED; |
1975 | ||
0105d1a5 | 1976 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1977 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1978 | |
1979 | break; | |
1980 | ||
b6ac0695 | 1981 | case APIC_LVTT: |
c48f1496 | 1982 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1983 | val |= APIC_LVT_MASKED; |
1984 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1985 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1986 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1987 | break; |
1988 | ||
97222cc8 | 1989 | case APIC_TMICT: |
a3e06bbe LJ |
1990 | if (apic_lvtt_tscdeadline(apic)) |
1991 | break; | |
1992 | ||
d3c7b77d | 1993 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1994 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1995 | start_apic_timer(apic); |
0105d1a5 | 1996 | break; |
97222cc8 | 1997 | |
c301b909 WL |
1998 | case APIC_TDCR: { |
1999 | uint32_t old_divisor = apic->divide_count; | |
2000 | ||
1e6e2755 | 2001 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 | 2002 | update_divide_count(apic); |
c301b909 WL |
2003 | if (apic->divide_count != old_divisor && |
2004 | apic->lapic_timer.period) { | |
2005 | hrtimer_cancel(&apic->lapic_timer.timer); | |
2006 | update_target_expiration(apic, old_divisor); | |
2007 | restart_apic_timer(apic); | |
2008 | } | |
97222cc8 | 2009 | break; |
c301b909 | 2010 | } |
0105d1a5 | 2011 | case APIC_ESR: |
0d88800d | 2012 | if (apic_x2apic_mode(apic) && val != 0) |
0105d1a5 | 2013 | ret = 1; |
0105d1a5 GN |
2014 | break; |
2015 | ||
2016 | case APIC_SELF_IPI: | |
2017 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 2018 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
2019 | } else |
2020 | ret = 1; | |
2021 | break; | |
97222cc8 | 2022 | default: |
0105d1a5 | 2023 | ret = 1; |
97222cc8 ED |
2024 | break; |
2025 | } | |
0d88800d | 2026 | |
0105d1a5 GN |
2027 | return ret; |
2028 | } | |
1e6e2755 | 2029 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 2030 | |
e32edf4f | 2031 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
2032 | gpa_t address, int len, const void *data) |
2033 | { | |
2034 | struct kvm_lapic *apic = to_lapic(this); | |
2035 | unsigned int offset = address - apic->base_address; | |
2036 | u32 val; | |
2037 | ||
2038 | if (!apic_mmio_in_range(apic, address)) | |
2039 | return -EOPNOTSUPP; | |
2040 | ||
d1766202 VK |
2041 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
2042 | if (!kvm_check_has_quirk(vcpu->kvm, | |
2043 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
2044 | return -EOPNOTSUPP; | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
0105d1a5 GN |
2049 | /* |
2050 | * APIC register must be aligned on 128-bits boundary. | |
2051 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
2052 | * Refer SDM 8.4.1 | |
2053 | */ | |
0d88800d | 2054 | if (len != 4 || (offset & 0xf)) |
756975bb | 2055 | return 0; |
0105d1a5 GN |
2056 | |
2057 | val = *(u32*)data; | |
2058 | ||
0d88800d | 2059 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 2060 | |
bda9020e | 2061 | return 0; |
97222cc8 ED |
2062 | } |
2063 | ||
58fbbf26 KT |
2064 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
2065 | { | |
1e6e2755 | 2066 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
2067 | } |
2068 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
2069 | ||
83d4c286 YZ |
2070 | /* emulate APIC access in a trap manner */ |
2071 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
2072 | { | |
2073 | u32 val = 0; | |
2074 | ||
2075 | /* hw has done the conditional check and inst decode */ | |
2076 | offset &= 0xff0; | |
2077 | ||
1e6e2755 | 2078 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
2079 | |
2080 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 2081 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
2082 | } |
2083 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
2084 | ||
d589444e | 2085 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 2086 | { |
f8c1ea10 GN |
2087 | struct kvm_lapic *apic = vcpu->arch.apic; |
2088 | ||
ad312c7c | 2089 | if (!vcpu->arch.apic) |
97222cc8 ED |
2090 | return; |
2091 | ||
f8c1ea10 | 2092 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2093 | |
c5cc421b GN |
2094 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
2095 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
2096 | ||
e462755c | 2097 | if (!apic->sw_enabled) |
f8c1ea10 | 2098 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 2099 | |
f8c1ea10 GN |
2100 | if (apic->regs) |
2101 | free_page((unsigned long)apic->regs); | |
2102 | ||
2103 | kfree(apic); | |
97222cc8 ED |
2104 | } |
2105 | ||
2106 | /* | |
2107 | *---------------------------------------------------------------------- | |
2108 | * LAPIC interface | |
2109 | *---------------------------------------------------------------------- | |
2110 | */ | |
a3e06bbe LJ |
2111 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
2112 | { | |
2113 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2114 | |
a10388e1 WL |
2115 | if (!lapic_in_kernel(vcpu) || |
2116 | !apic_lvtt_tscdeadline(apic)) | |
a3e06bbe LJ |
2117 | return 0; |
2118 | ||
2119 | return apic->lapic_timer.tscdeadline; | |
2120 | } | |
2121 | ||
2122 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
2123 | { | |
2124 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2125 | |
bce87cce | 2126 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 2127 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
2128 | return; |
2129 | ||
2130 | hrtimer_cancel(&apic->lapic_timer.timer); | |
2131 | apic->lapic_timer.tscdeadline = data; | |
2132 | start_apic_timer(apic); | |
2133 | } | |
2134 | ||
97222cc8 ED |
2135 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
2136 | { | |
ad312c7c | 2137 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2138 | |
b93463aa | 2139 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 2140 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
2141 | } |
2142 | ||
2143 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
2144 | { | |
97222cc8 ED |
2145 | u64 tpr; |
2146 | ||
dfb95954 | 2147 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
2148 | |
2149 | return (tpr & 0xf0) >> 4; | |
2150 | } | |
2151 | ||
2152 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
2153 | { | |
8d14695f | 2154 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 2155 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2156 | |
c7dd15b3 | 2157 | if (!apic) |
97222cc8 | 2158 | value |= MSR_IA32_APICBASE_BSP; |
c5af89b6 | 2159 | |
e66d2ae7 JK |
2160 | vcpu->arch.apic_base = value; |
2161 | ||
c7dd15b3 JM |
2162 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) |
2163 | kvm_update_cpuid(vcpu); | |
2164 | ||
2165 | if (!apic) | |
2166 | return; | |
2167 | ||
c5cc421b | 2168 | /* update jump label if enable bit changes */ |
0dce7cd6 | 2169 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
49bd29ba RK |
2170 | if (value & MSR_IA32_APICBASE_ENABLE) { |
2171 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); | |
c5cc421b | 2172 | static_key_slow_dec_deferred(&apic_hw_disabled); |
187ca84b | 2173 | } else { |
c5cc421b | 2174 | static_key_slow_inc(&apic_hw_disabled.key); |
187ca84b WL |
2175 | recalculate_apic_map(vcpu->kvm); |
2176 | } | |
c5cc421b GN |
2177 | } |
2178 | ||
8d860bbe JM |
2179 | if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) |
2180 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); | |
2181 | ||
2182 | if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) | |
2183 | kvm_x86_ops->set_virtual_apic_mode(vcpu); | |
8d14695f | 2184 | |
ad312c7c | 2185 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
2186 | MSR_IA32_APICBASE_BASE; |
2187 | ||
db324fe6 NA |
2188 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
2189 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
2190 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
97222cc8 ED |
2191 | } |
2192 | ||
d28bc9dd | 2193 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 | 2194 | { |
b7e31be3 | 2195 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
2196 | int i; |
2197 | ||
b7e31be3 RK |
2198 | if (!apic) |
2199 | return; | |
97222cc8 | 2200 | |
97222cc8 | 2201 | /* Stop the timer in case it's a reset to an active apic */ |
d3c7b77d | 2202 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2203 | |
4d8e772b RK |
2204 | if (!init_event) { |
2205 | kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | | |
2206 | MSR_IA32_APICBASE_ENABLE); | |
a92e2543 | 2207 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); |
4d8e772b | 2208 | } |
fc61b800 | 2209 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 2210 | |
1e6e2755 SS |
2211 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
2212 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 2213 | apic_update_lvtt(apic); |
52b54190 JS |
2214 | if (kvm_vcpu_is_reset_bsp(vcpu) && |
2215 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) | |
1e6e2755 | 2216 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 2217 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 2218 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 2219 | |
1e6e2755 | 2220 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 2221 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 2222 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
2223 | if (!apic_x2apic_mode(apic)) |
2224 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
2225 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
2226 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
2227 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
2228 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
2229 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 2230 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
2231 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
2232 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
2233 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 2234 | } |
d62caabb AS |
2235 | apic->irr_pending = vcpu->arch.apicv_active; |
2236 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 2237 | apic->highest_isr_cache = -1; |
b33ac88b | 2238 | update_divide_count(apic); |
d3c7b77d | 2239 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 2240 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
2241 | kvm_lapic_set_base(vcpu, |
2242 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 2243 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 | 2244 | apic_update_ppr(apic); |
4191db26 JS |
2245 | if (vcpu->arch.apicv_active) { |
2246 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
2247 | kvm_x86_ops->hwapic_irr_update(vcpu, -1); | |
2248 | kvm_x86_ops->hwapic_isr_update(vcpu, -1); | |
2249 | } | |
97222cc8 | 2250 | |
e1035715 | 2251 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 2252 | vcpu->arch.apic_attention = 0; |
97222cc8 ED |
2253 | } |
2254 | ||
97222cc8 ED |
2255 | /* |
2256 | *---------------------------------------------------------------------- | |
2257 | * timer interface | |
2258 | *---------------------------------------------------------------------- | |
2259 | */ | |
1b9778da | 2260 | |
2a6eac96 | 2261 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 2262 | { |
d3c7b77d | 2263 | return apic_lvtt_period(apic); |
97222cc8 ED |
2264 | } |
2265 | ||
3d80840d MT |
2266 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
2267 | { | |
54e9818f | 2268 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 2269 | |
1e3161b4 | 2270 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 2271 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
2272 | |
2273 | return 0; | |
2274 | } | |
2275 | ||
89342082 | 2276 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 2277 | { |
dfb95954 | 2278 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 2279 | int vector, mode, trig_mode; |
23930f95 | 2280 | |
c48f1496 | 2281 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
2282 | vector = reg & APIC_VECTOR_MASK; |
2283 | mode = reg & APIC_MODE_MASK; | |
2284 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
2285 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
2286 | NULL); | |
23930f95 JK |
2287 | } |
2288 | return 0; | |
2289 | } | |
1b9778da | 2290 | |
8fdb2351 | 2291 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 2292 | { |
8fdb2351 JK |
2293 | struct kvm_lapic *apic = vcpu->arch.apic; |
2294 | ||
2295 | if (apic) | |
2296 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
2297 | } |
2298 | ||
d76685c4 GH |
2299 | static const struct kvm_io_device_ops apic_mmio_ops = { |
2300 | .read = apic_mmio_read, | |
2301 | .write = apic_mmio_write, | |
d76685c4 GH |
2302 | }; |
2303 | ||
e9d90d47 AK |
2304 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
2305 | { | |
2306 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 2307 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 2308 | |
5d87db71 | 2309 | apic_timer_expired(apic); |
e9d90d47 | 2310 | |
2a6eac96 | 2311 | if (lapic_is_periodic(apic)) { |
8003c9ae | 2312 | advance_periodic_target_expiration(apic); |
e9d90d47 AK |
2313 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
2314 | return HRTIMER_RESTART; | |
2315 | } else | |
2316 | return HRTIMER_NORESTART; | |
2317 | } | |
2318 | ||
c3941d9e | 2319 | int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns) |
97222cc8 ED |
2320 | { |
2321 | struct kvm_lapic *apic; | |
2322 | ||
2323 | ASSERT(vcpu != NULL); | |
97222cc8 | 2324 | |
254272ce | 2325 | apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); |
97222cc8 ED |
2326 | if (!apic) |
2327 | goto nomem; | |
2328 | ||
ad312c7c | 2329 | vcpu->arch.apic = apic; |
97222cc8 | 2330 | |
254272ce | 2331 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
afc20184 | 2332 | if (!apic->regs) { |
97222cc8 ED |
2333 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
2334 | vcpu->vcpu_id); | |
d589444e | 2335 | goto nomem_free_apic; |
97222cc8 | 2336 | } |
97222cc8 ED |
2337 | apic->vcpu = vcpu; |
2338 | ||
d3c7b77d | 2339 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
2c0d278f | 2340 | HRTIMER_MODE_ABS_HARD); |
e9d90d47 | 2341 | apic->lapic_timer.timer.function = apic_timer_fn; |
c3941d9e | 2342 | if (timer_advance_ns == -1) { |
a0f0037e | 2343 | apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; |
d0f5a86a | 2344 | lapic_timer_advance_dynamic = true; |
c3941d9e SC |
2345 | } else { |
2346 | apic->lapic_timer.timer_advance_ns = timer_advance_ns; | |
d0f5a86a | 2347 | lapic_timer_advance_dynamic = false; |
c3941d9e SC |
2348 | } |
2349 | ||
c5cc421b GN |
2350 | /* |
2351 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
ee171d2f | 2352 | * thinking that APIC state has changed. |
c5cc421b GN |
2353 | */ |
2354 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
f8c1ea10 | 2355 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d76685c4 | 2356 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
2357 | |
2358 | return 0; | |
d589444e RR |
2359 | nomem_free_apic: |
2360 | kfree(apic); | |
a251fb90 | 2361 | vcpu->arch.apic = NULL; |
97222cc8 | 2362 | nomem: |
97222cc8 ED |
2363 | return -ENOMEM; |
2364 | } | |
97222cc8 ED |
2365 | |
2366 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
2367 | { | |
ad312c7c | 2368 | struct kvm_lapic *apic = vcpu->arch.apic; |
b3c045d3 | 2369 | u32 ppr; |
97222cc8 | 2370 | |
bb34e690 | 2371 | if (!kvm_apic_hw_enabled(apic)) |
97222cc8 ED |
2372 | return -1; |
2373 | ||
b3c045d3 PB |
2374 | __apic_update_ppr(apic, &ppr); |
2375 | return apic_has_interrupt_for_ppr(apic, ppr); | |
97222cc8 ED |
2376 | } |
2377 | ||
40487c68 QH |
2378 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
2379 | { | |
dfb95954 | 2380 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
2381 | int r = 0; |
2382 | ||
c48f1496 | 2383 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
2384 | r = 1; |
2385 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
2386 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
2387 | r = 1; | |
40487c68 QH |
2388 | return r; |
2389 | } | |
2390 | ||
1b9778da ED |
2391 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
2392 | { | |
ad312c7c | 2393 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 2394 | |
54e9818f | 2395 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
0c5f81da | 2396 | kvm_apic_inject_pending_timer_irqs(apic); |
f1ed0450 | 2397 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
2398 | } |
2399 | } | |
2400 | ||
97222cc8 ED |
2401 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
2402 | { | |
2403 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 2404 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d82d12b | 2405 | u32 ppr; |
97222cc8 ED |
2406 | |
2407 | if (vector == -1) | |
2408 | return -1; | |
2409 | ||
56cc2406 WL |
2410 | /* |
2411 | * We get here even with APIC virtualization enabled, if doing | |
2412 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
2413 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
2414 | * because the process would deliver it through the IDT. | |
2415 | */ | |
2416 | ||
97222cc8 | 2417 | apic_clear_irr(vector, apic); |
5c919412 | 2418 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { |
4d82d12b PB |
2419 | /* |
2420 | * For auto-EOI interrupts, there might be another pending | |
2421 | * interrupt above PPR, so check whether to raise another | |
2422 | * KVM_REQ_EVENT. | |
2423 | */ | |
5c919412 | 2424 | apic_update_ppr(apic); |
4d82d12b PB |
2425 | } else { |
2426 | /* | |
2427 | * For normal interrupts, PPR has been raised and there cannot | |
2428 | * be a higher-priority pending interrupt---except if there was | |
2429 | * a concurrent interrupt injection, but that would have | |
2430 | * triggered KVM_REQ_EVENT already. | |
2431 | */ | |
2432 | apic_set_isr(vector, apic); | |
2433 | __apic_update_ppr(apic, &ppr); | |
5c919412 AS |
2434 | } |
2435 | ||
97222cc8 ED |
2436 | return vector; |
2437 | } | |
96ad2cc6 | 2438 | |
a92e2543 RK |
2439 | static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, |
2440 | struct kvm_lapic_state *s, bool set) | |
2441 | { | |
2442 | if (apic_x2apic_mode(vcpu->arch.apic)) { | |
2443 | u32 *id = (u32 *)(s->regs + APIC_ID); | |
12806ba9 | 2444 | u32 *ldr = (u32 *)(s->regs + APIC_LDR); |
a92e2543 | 2445 | |
37131313 RK |
2446 | if (vcpu->kvm->arch.x2apic_format) { |
2447 | if (*id != vcpu->vcpu_id) | |
2448 | return -EINVAL; | |
2449 | } else { | |
2450 | if (set) | |
2451 | *id >>= 24; | |
2452 | else | |
2453 | *id <<= 24; | |
2454 | } | |
12806ba9 DDAG |
2455 | |
2456 | /* In x2APIC mode, the LDR is fixed and based on the id */ | |
2457 | if (set) | |
2458 | *ldr = kvm_apic_calc_x2apic_ldr(*id); | |
a92e2543 RK |
2459 | } |
2460 | ||
2461 | return 0; | |
2462 | } | |
2463 | ||
2464 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
2465 | { | |
2466 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); | |
2467 | return kvm_apic_state_fixup(vcpu, s, false); | |
2468 | } | |
2469 | ||
2470 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
96ad2cc6 | 2471 | { |
ad312c7c | 2472 | struct kvm_lapic *apic = vcpu->arch.apic; |
a92e2543 RK |
2473 | int r; |
2474 | ||
96ad2cc6 | 2475 | |
5dbc8f3f | 2476 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
2477 | /* set SPIV separately to get count of SW disabled APICs right */ |
2478 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
a92e2543 RK |
2479 | |
2480 | r = kvm_apic_state_fixup(vcpu, s, true); | |
2481 | if (r) | |
2482 | return r; | |
0e96f31e | 2483 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); |
a92e2543 RK |
2484 | |
2485 | recalculate_apic_map(vcpu->kvm); | |
fc61b800 GN |
2486 | kvm_apic_set_version(vcpu); |
2487 | ||
96ad2cc6 | 2488 | apic_update_ppr(apic); |
d3c7b77d | 2489 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 2490 | apic_update_lvtt(apic); |
dfb95954 | 2491 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
2492 | update_divide_count(apic); |
2493 | start_apic_timer(apic); | |
6e24a6ef | 2494 | apic->irr_pending = true; |
d62caabb | 2495 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 2496 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 2497 | apic->highest_isr_cache = -1; |
d62caabb | 2498 | if (vcpu->arch.apicv_active) { |
967235d3 | 2499 | kvm_x86_ops->apicv_post_state_restore(vcpu); |
4114c27d WW |
2500 | kvm_x86_ops->hwapic_irr_update(vcpu, |
2501 | apic_find_highest_irr(apic)); | |
67c9dddc | 2502 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 2503 | apic_find_highest_isr(apic)); |
d62caabb | 2504 | } |
3842d135 | 2505 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2506 | if (ioapic_in_kernel(vcpu->kvm)) |
2507 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2508 | |
2509 | vcpu->arch.apic_arb_prio = 0; | |
a92e2543 RK |
2510 | |
2511 | return 0; | |
96ad2cc6 | 2512 | } |
a3d7f85f | 2513 | |
2f52d58c | 2514 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2515 | { |
a3d7f85f ED |
2516 | struct hrtimer *timer; |
2517 | ||
0c5f81da WL |
2518 | if (!lapic_in_kernel(vcpu) || |
2519 | kvm_can_post_timer_interrupt(vcpu)) | |
a3d7f85f ED |
2520 | return; |
2521 | ||
54e9818f | 2522 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2523 | if (hrtimer_cancel(timer)) |
2c0d278f | 2524 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD); |
a3d7f85f | 2525 | } |
b93463aa | 2526 | |
ae7a2a3f MT |
2527 | /* |
2528 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2529 | * | |
2530 | * Detect whether guest triggered PV EOI since the | |
2531 | * last entry. If yes, set EOI on guests's behalf. | |
2532 | * Clear PV EOI in guest memory in any case. | |
2533 | */ | |
2534 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2535 | struct kvm_lapic *apic) | |
2536 | { | |
2537 | bool pending; | |
2538 | int vector; | |
2539 | /* | |
2540 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2541 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2542 | * | |
2543 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2544 | * -> host disabled PV EOI. | |
2545 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2546 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2547 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2548 | * -> host enabled PV EOI, guest executed EOI. | |
2549 | */ | |
2550 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2551 | pending = pv_eoi_get_pending(vcpu); | |
2552 | /* | |
2553 | * Clear pending bit in any case: it will be set again on vmentry. | |
2554 | * While this might not be ideal from performance point of view, | |
2555 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2556 | */ | |
2557 | pv_eoi_clr_pending(vcpu); | |
2558 | if (pending) | |
2559 | return; | |
2560 | vector = apic_set_eoi(apic); | |
2561 | trace_kvm_pv_eoi(apic, vector); | |
2562 | } | |
2563 | ||
b93463aa AK |
2564 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2565 | { | |
2566 | u32 data; | |
b93463aa | 2567 | |
ae7a2a3f MT |
2568 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2569 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2570 | ||
41383771 | 2571 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2572 | return; |
2573 | ||
4e335d9e PB |
2574 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2575 | sizeof(u32))) | |
603242a8 | 2576 | return; |
b93463aa AK |
2577 | |
2578 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2579 | } | |
2580 | ||
ae7a2a3f MT |
2581 | /* |
2582 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2583 | * | |
2584 | * Detect whether it's safe to enable PV EOI and | |
2585 | * if yes do so. | |
2586 | */ | |
2587 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2588 | struct kvm_lapic *apic) | |
2589 | { | |
2590 | if (!pv_eoi_enabled(vcpu) || | |
2591 | /* IRR set or many bits in ISR: could be nested. */ | |
2592 | apic->irr_pending || | |
2593 | /* Cache not set: could be safe but we don't bother. */ | |
2594 | apic->highest_isr_cache == -1 || | |
2595 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2596 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2597 | /* |
2598 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2599 | * so we need not do anything here. | |
2600 | */ | |
2601 | return; | |
2602 | } | |
2603 | ||
2604 | pv_eoi_set_pending(apic->vcpu); | |
2605 | } | |
2606 | ||
b93463aa AK |
2607 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2608 | { | |
2609 | u32 data, tpr; | |
2610 | int max_irr, max_isr; | |
ae7a2a3f | 2611 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2612 | |
ae7a2a3f MT |
2613 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2614 | ||
41383771 | 2615 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2616 | return; |
2617 | ||
dfb95954 | 2618 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2619 | max_irr = apic_find_highest_irr(apic); |
2620 | if (max_irr < 0) | |
2621 | max_irr = 0; | |
2622 | max_isr = apic_find_highest_isr(apic); | |
2623 | if (max_isr < 0) | |
2624 | max_isr = 0; | |
2625 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2626 | ||
4e335d9e PB |
2627 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2628 | sizeof(u32)); | |
b93463aa AK |
2629 | } |
2630 | ||
fda4e2e8 | 2631 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2632 | { |
fda4e2e8 | 2633 | if (vapic_addr) { |
4e335d9e | 2634 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
fda4e2e8 AH |
2635 | &vcpu->arch.apic->vapic_cache, |
2636 | vapic_addr, sizeof(u32))) | |
2637 | return -EINVAL; | |
41383771 | 2638 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2639 | } else { |
41383771 | 2640 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2641 | } |
2642 | ||
2643 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2644 | return 0; | |
b93463aa | 2645 | } |
0105d1a5 GN |
2646 | |
2647 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2648 | { | |
2649 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2650 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2651 | ||
35754c98 | 2652 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2653 | return 1; |
2654 | ||
c69d3d9b NA |
2655 | if (reg == APIC_ICR2) |
2656 | return 1; | |
2657 | ||
0105d1a5 | 2658 | /* if this is ICR write vector before command */ |
decdc283 | 2659 | if (reg == APIC_ICR) |
1e6e2755 SS |
2660 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2661 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2662 | } |
2663 | ||
2664 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2665 | { | |
2666 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2667 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2668 | ||
35754c98 | 2669 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2670 | return 1; |
2671 | ||
0d88800d | 2672 | if (reg == APIC_DFR || reg == APIC_ICR2) |
c69d3d9b | 2673 | return 1; |
c69d3d9b | 2674 | |
1e6e2755 | 2675 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2676 | return 1; |
decdc283 | 2677 | if (reg == APIC_ICR) |
1e6e2755 | 2678 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2679 | |
2680 | *data = (((u64)high) << 32) | low; | |
2681 | ||
2682 | return 0; | |
2683 | } | |
10388a07 GN |
2684 | |
2685 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2686 | { | |
2687 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2688 | ||
bce87cce | 2689 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2690 | return 1; |
2691 | ||
2692 | /* if this is ICR write vector before command */ | |
2693 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2694 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2695 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2696 | } |
2697 | ||
2698 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2699 | { | |
2700 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2701 | u32 low, high = 0; | |
2702 | ||
bce87cce | 2703 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2704 | return 1; |
2705 | ||
1e6e2755 | 2706 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2707 | return 1; |
2708 | if (reg == APIC_ICR) | |
1e6e2755 | 2709 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2710 | |
2711 | *data = (((u64)high) << 32) | low; | |
2712 | ||
2713 | return 0; | |
2714 | } | |
ae7a2a3f | 2715 | |
72bbf935 | 2716 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len) |
ae7a2a3f MT |
2717 | { |
2718 | u64 addr = data & ~KVM_MSR_ENABLED; | |
a7c42bb6 VK |
2719 | struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; |
2720 | unsigned long new_len; | |
2721 | ||
ae7a2a3f MT |
2722 | if (!IS_ALIGNED(addr, 4)) |
2723 | return 1; | |
2724 | ||
2725 | vcpu->arch.pv_eoi.msr_val = data; | |
2726 | if (!pv_eoi_enabled(vcpu)) | |
2727 | return 0; | |
a7c42bb6 VK |
2728 | |
2729 | if (addr == ghc->gpa && len <= ghc->len) | |
2730 | new_len = ghc->len; | |
2731 | else | |
2732 | new_len = len; | |
2733 | ||
2734 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); | |
ae7a2a3f | 2735 | } |
c5cc421b | 2736 | |
66450a21 JK |
2737 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2738 | { | |
2739 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2740 | u8 sipi_vector; |
299018f4 | 2741 | unsigned long pe; |
66450a21 | 2742 | |
bce87cce | 2743 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2744 | return; |
2745 | ||
cd7764fe | 2746 | /* |
4b9852f4 LA |
2747 | * INITs are latched while CPU is in specific states |
2748 | * (SMM, VMX non-root mode, SVM with GIF=0). | |
2749 | * Because a CPU cannot be in these states immediately | |
2750 | * after it has processed an INIT signal (and thus in | |
2751 | * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs | |
2752 | * and leave the INIT pending. | |
cd7764fe | 2753 | */ |
27cbe7d6 | 2754 | if (kvm_vcpu_latch_init(vcpu)) { |
cd7764fe PB |
2755 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); |
2756 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2757 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2758 | return; | |
2759 | } | |
299018f4 | 2760 | |
cd7764fe | 2761 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2762 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd | 2763 | kvm_vcpu_reset(vcpu, true); |
66450a21 JK |
2764 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2765 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2766 | else | |
2767 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2768 | } | |
299018f4 | 2769 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2770 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2771 | /* evaluate pending_events before reading the vector */ | |
2772 | smp_rmb(); | |
2773 | sipi_vector = apic->sipi_vector; | |
66450a21 JK |
2774 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); |
2775 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2776 | } | |
2777 | } | |
2778 | ||
c5cc421b GN |
2779 | void kvm_lapic_init(void) |
2780 | { | |
2781 | /* do not patch jump label more than once per second */ | |
2782 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2783 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2784 | } |
cef84c30 DM |
2785 | |
2786 | void kvm_lapic_exit(void) | |
2787 | { | |
2788 | static_key_deferred_flush(&apic_hw_disabled); | |
2789 | static_key_deferred_flush(&apic_sw_disabled); | |
2790 | } |