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KVM: LAPIC: Fix updating DFR missing apic map recalculation
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / lapic.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
97222cc8
ED		 2
3/*
4 * Local APIC virtualization
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9611c187 9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 10 *
11 * Authors:
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 *
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
97222cc8
ED		 17 */
18
edf88417 19#include <linux/kvm_host.h>
97222cc8
ED		 20#include <linux/kvm.h>
21#include <linux/mm.h>
22#include <linux/highmem.h>
23#include <linux/smp.h>
24#include <linux/hrtimer.h>
25#include <linux/io.h>
1767e931 26#include <linux/export.h>
6f6d6a1a 27#include <linux/math64.h>
5a0e3ad6 28#include <linux/slab.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
d0659d94 34#include <asm/delay.h>
60063497 35#include <linux/atomic.h>
c5cc421b 36#include <linux/jump_label.h>
5fdbf976 37#include "kvm_cache_regs.h"
97222cc8 38#include "irq.h"
88197e6a 39#include "ioapic.h"
229456fc 40#include "trace.h"
fc61b800 41#include "x86.h"
00b27a3e 42#include "cpuid.h"
5c919412 43#include "hyperv.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
97222cc8 56/* 14 is the version for Xeon and Pentium 8.4.8*/
1e6e2755 57#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
97222cc8
ED		 58#define LAPIC_MMIO_LENGTH (1 << 12)
59/* followed define is not in apicdef.h */
97222cc8 60#define MAX_APIC_VECTOR 256
ecba9a52 61#define APIC_VECTORS_PER_REG 32
97222cc8 62
d0f5a86a 63static bool lapic_timer_advance_dynamic __read_mostly;
a0f0037e
WL		 64#define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
65#define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
66#define LAPIC_TIMER_ADVANCE_NS_INIT 1000
67#define LAPIC_TIMER_ADVANCE_NS_MAX 5000
3b8a5df6
WL		 68/* step-by-step approximation to mitigate fluctuation */
69#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
70
a0c9a822
MT		 71static inline int apic_test_vector(int vec, void *bitmap)
72{
73 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
74}
75
10606919
YZ		 76bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
77{
78 struct kvm_lapic *apic = vcpu->arch.apic;
79
80 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
81 apic_test_vector(vector, apic->regs + APIC_IRR);
82}
83
8680b94b
MT		 84static inline int __apic_test_and_set_vector(int vec, void *bitmap)
85{
86 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
90{
91 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92}
93
c5cc421b 94struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 95struct static_key_deferred apic_sw_disabled __read_mostly;
96
97222cc8
ED		 97static inline int apic_enabled(struct kvm_lapic *apic)
98{
c48f1496 99 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 100}
101
97222cc8
ED		 102#define LVT_MASK \
103 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
104
105#define LINT_MASK \
106 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
107 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
108
6e500439
RK		 109static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
110{
111 return apic->vcpu->vcpu_id;
112}
113
199a8b84 114static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
0c5f81da
WL		 115{
116 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
117}
199a8b84
PB		 118
119bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu)
120{
121 return kvm_x86_ops.set_hv_timer
122 && !(kvm_mwait_in_guest(vcpu->kvm) ||
123 kvm_can_post_timer_interrupt(vcpu));
124}
125EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer);
0c5f81da
WL		 126
127static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
128{
129 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
130}
131
e45115b6
RK		 132static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
133 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
134 switch (map->mode) {
135 case KVM_APIC_MODE_X2APIC: {
136 u32 offset = (dest_id >> 16) * 16;
0ca52e7b 137 u32 max_apic_id = map->max_apic_id;
e45115b6
RK		 138
139 if (offset <= max_apic_id) {
140 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
141
1d487e9b 142 offset = array_index_nospec(offset, map->max_apic_id + 1);
e45115b6
RK		 143 *cluster = &map->phys_map[offset];
144 *mask = dest_id & (0xffff >> (16 - cluster_size));
145 } else {
146 *mask = 0;
147 }
3b5a5ffa 148
e45115b6
RK		 149 return true;
150 }
151 case KVM_APIC_MODE_XAPIC_FLAT:
152 *cluster = map->xapic_flat_map;
153 *mask = dest_id & 0xff;
154 return true;
155 case KVM_APIC_MODE_XAPIC_CLUSTER:
444fdad8 156 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
e45115b6
RK		 157 *mask = dest_id & 0xf;
158 return true;
159 default:
160 /* Not optimized. */
161 return false;
162 }
3548a259
RK		 163}
164
af1bae54 165static void kvm_apic_map_free(struct rcu_head *rcu)
3b5a5ffa 166{
af1bae54 167 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
3b5a5ffa 168
af1bae54 169 kvfree(map);
3b5a5ffa
RK		 170}
171
44d52717
PB		 172/*
173 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
174 *
175 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
176 * apic_map_lock_held.
177 */
178enum {
179 CLEAN,
180 UPDATE_IN_PROGRESS,
181 DIRTY
182};
183
4abaffce 184void kvm_recalculate_apic_map(struct kvm *kvm)
1e08ec4a
GN		 185{
186 struct kvm_apic_map *new, *old = NULL;
187 struct kvm_vcpu *vcpu;
188 int i;
6e500439 189 u32 max_id = 255; /* enough space for any xAPIC ID */
1e08ec4a 190
44d52717
PB		 191 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */
192 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN)
4abaffce 193 return;
4abaffce 194
1e08ec4a 195 mutex_lock(&kvm->arch.apic_map_lock);
44d52717
PB		 196 /*
197 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map
198 * (if clean) or the APIC registers (if dirty).
199 */
200 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty,
201 DIRTY, UPDATE_IN_PROGRESS) == CLEAN) {
4abaffce
WL		 202 /* Someone else has updated the map. */
203 mutex_unlock(&kvm->arch.apic_map_lock);
204 return;
205 }
1e08ec4a 206
0ca52e7b
RK		 207 kvm_for_each_vcpu(i, vcpu, kvm)
208 if (kvm_apic_present(vcpu))
6e500439 209 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
0ca52e7b 210
a7c3e901 211 new = kvzalloc(sizeof(struct kvm_apic_map) +
254272ce
BG		 212 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
213 GFP_KERNEL_ACCOUNT);
0ca52e7b 214
1e08ec4a
GN		 215 if (!new)
216 goto out;
217
0ca52e7b
RK		 218 new->max_apic_id = max_id;
219
173beedc
NA		 220 kvm_for_each_vcpu(i, vcpu, kvm) {
221 struct kvm_lapic *apic = vcpu->arch.apic;
e45115b6
RK		 222 struct kvm_lapic **cluster;
223 u16 mask;
5bd5db38
RK		 224 u32 ldr;
225 u8 xapic_id;
226 u32 x2apic_id;
1e08ec4a 227
df04d1d1
RK		 228 if (!kvm_apic_present(vcpu))
229 continue;
230
5bd5db38
RK		 231 xapic_id = kvm_xapic_id(apic);
232 x2apic_id = kvm_x2apic_id(apic);
233
234 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
235 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
236 x2apic_id <= new->max_apic_id)
237 new->phys_map[x2apic_id] = apic;
238 /*
239 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
240 * prevent them from masking VCPUs with APIC ID <= 0xff.
241 */
242 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
243 new->phys_map[xapic_id] = apic;
3548a259 244
b14c876b
RK		 245 if (!kvm_apic_sw_enabled(apic))
246 continue;
247
6e500439
RK		 248 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
249
3b5a5ffa
RK		 250 if (apic_x2apic_mode(apic)) {
251 new->mode |= KVM_APIC_MODE_X2APIC;
252 } else if (ldr) {
253 ldr = GET_APIC_LOGICAL_ID(ldr);
dfb95954 254 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
3b5a5ffa
RK		 255 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
256 else
257 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
258 }
259
e45115b6 260 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
3548a259
RK		 261 continue;
262
e45115b6
RK		 263 if (mask)
264 cluster[ffs(mask) - 1] = apic;
1e08ec4a
GN		 265 }
266out:
267 old = rcu_dereference_protected(kvm->arch.apic_map,
268 lockdep_is_held(&kvm->arch.apic_map_lock));
269 rcu_assign_pointer(kvm->arch.apic_map, new);
4abaffce 270 /*
44d52717
PB		 271 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
272 * If another update has come in, leave it DIRTY.
4abaffce 273 */
44d52717
PB		 274 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty,
275 UPDATE_IN_PROGRESS, CLEAN);
1e08ec4a
GN		 276 mutex_unlock(&kvm->arch.apic_map_lock);
277
278 if (old)
af1bae54 279 call_rcu(&old->rcu, kvm_apic_map_free);
c7c9c56c 280
b053b2ae 281 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 282}
283
1e1b6c26
NA		 284static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
285{
e462755c 286 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26 287
1e6e2755 288 kvm_lapic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 289
290 if (enabled != apic->sw_enabled) {
291 apic->sw_enabled = enabled;
eb1ff0a9 292 if (enabled)
1e1b6c26 293 static_key_slow_dec_deferred(&apic_sw_disabled);
eb1ff0a9 294 else
1e1b6c26 295 static_key_slow_inc(&apic_sw_disabled.key);
b14c876b 296
44d52717 297 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
1e1b6c26
NA		 298 }
299}
300
a92e2543 301static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
1e08ec4a 302{
1e6e2755 303 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
44d52717 304 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
1e08ec4a
GN		 305}
306
307static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
308{
1e6e2755 309 kvm_lapic_set_reg(apic, APIC_LDR, id);
44d52717 310 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
1e08ec4a
GN		 311}
312
ae6f2496
WL		 313static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
314{
315 kvm_lapic_set_reg(apic, APIC_DFR, val);
316 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
317}
318
e872fa94
DDAG		 319static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
320{
321 return ((id >> 4) << 16) | (1 << (id & 0xf));
322}
323
a92e2543 324static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
257b9a5f 325{
e872fa94 326 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
257b9a5f 327
6e500439
RK		 328 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
329
a92e2543 330 kvm_lapic_set_reg(apic, APIC_ID, id);
1e6e2755 331 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
44d52717 332 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
257b9a5f
RK		 333}
334
97222cc8
ED		 335static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
336{
dfb95954 337 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 338}
339
a3e06bbe
LJ		 340static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
341{
f30ebc31 342 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 343}
344
97222cc8
ED		 345static inline int apic_lvtt_period(struct kvm_lapic *apic)
346{
f30ebc31 347 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 348}
349
350static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
351{
f30ebc31 352 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 353}
354
cc6e462c
JK		 355static inline int apic_lvt_nmi_mode(u32 lvt_val)
356{
357 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
358}
359
fc61b800
GN		 360void kvm_apic_set_version(struct kvm_vcpu *vcpu)
361{
362 struct kvm_lapic *apic = vcpu->arch.apic;
fc61b800
GN		 363 u32 v = APIC_VERSION;
364
bce87cce 365 if (!lapic_in_kernel(vcpu))
fc61b800
GN		 366 return;
367
0bcc3fb9
VK		 368 /*
369 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
370 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
371 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
372 * version first and level-triggered interrupts never get EOIed in
373 * IOAPIC.
374 */
565b7820 375 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) &&
0bcc3fb9 376 !ioapic_in_kernel(vcpu->kvm))
fc61b800 377 v |= APIC_LVR_DIRECTED_EOI;
1e6e2755 378 kvm_lapic_set_reg(apic, APIC_LVR, v);
fc61b800
GN		 379}
380
1e6e2755 381static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
a3e06bbe 382 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 383 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
384 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
385 LINT_MASK, LINT_MASK, /* LVT0-1 */
386 LVT_MASK /* LVTERR */
387};
388
389static int find_highest_vector(void *bitmap)
390{
ecba9a52
TY		 391 int vec;
392 u32 *reg;
97222cc8 393
ecba9a52
TY		 394 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
395 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
396 reg = bitmap + REG_POS(vec);
397 if (*reg)
810e6def 398 return __fls(*reg) + vec;
ecba9a52 399 }
97222cc8 400
ecba9a52 401 return -1;
97222cc8
ED		 402}
403
8680b94b
MT		 404static u8 count_vectors(void *bitmap)
405{
ecba9a52
TY		 406 int vec;
407 u32 *reg;
8680b94b 408 u8 count = 0;
ecba9a52
TY		 409
410 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
411 reg = bitmap + REG_POS(vec);
412 count += hweight32(*reg);
413 }
414
8680b94b
MT		 415 return count;
416}
417
e7387b0e 418bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
a20ed54d 419{
810e6def 420 u32 i, vec;
e7387b0e
LA		 421 u32 pir_val, irr_val, prev_irr_val;
422 int max_updated_irr;
423
424 max_updated_irr = -1;
425 *max_irr = -1;
a20ed54d 426
810e6def 427 for (i = vec = 0; i <= 7; i++, vec += 32) {
ad361091 428 pir_val = READ_ONCE(pir[i]);
810e6def 429 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
ad361091 430 if (pir_val) {
e7387b0e 431 prev_irr_val = irr_val;
810e6def
PB		 432 irr_val |= xchg(&pir[i], 0);
433 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
e7387b0e
LA		 434 if (prev_irr_val != irr_val) {
435 max_updated_irr =
436 __fls(irr_val ^ prev_irr_val) + vec;
437 }
ad361091 438 }
810e6def 439 if (irr_val)
e7387b0e 440 *max_irr = __fls(irr_val) + vec;
a20ed54d 441 }
810e6def 442
e7387b0e
LA		 443 return ((max_updated_irr != -1) &&
444 (max_updated_irr == *max_irr));
a20ed54d 445}
705699a1
WV		 446EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
447
e7387b0e 448bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
705699a1
WV		 449{
450 struct kvm_lapic *apic = vcpu->arch.apic;
451
e7387b0e 452 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
705699a1 453}
a20ed54d
YZ		 454EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
455
33e4c686 456static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 457{
33e4c686 458 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 459}
460
461static inline int apic_find_highest_irr(struct kvm_lapic *apic)
462{
463 int result;
464
c7c9c56c
YZ		 465 /*
466 * Note that irr_pending is just a hint. It will be always
467 * true with virtual interrupt delivery enabled.
468 */
33e4c686
GN		 469 if (!apic->irr_pending)
470 return -1;
471
472 result = apic_search_irr(apic);
97222cc8
ED		 473 ASSERT(result == -1 || result >= 16);
474
475 return result;
476}
477
33e4c686
GN		 478static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
479{
56cc2406
WL		 480 struct kvm_vcpu *vcpu;
481
482 vcpu = apic->vcpu;
483
d62caabb 484 if (unlikely(vcpu->arch.apicv_active)) {
b95234c8 485 /* need to update RVI */
ee171d2f 486 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
afaf0b2f 487 kvm_x86_ops.hwapic_irr_update(vcpu,
b95234c8 488 apic_find_highest_irr(apic));
f210f757
NA		 489 } else {
490 apic->irr_pending = false;
ee171d2f 491 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 492 if (apic_search_irr(apic) != -1)
493 apic->irr_pending = true;
56cc2406 494 }
33e4c686
GN		 495}
496
8680b94b
MT		 497static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
498{
56cc2406
WL		 499 struct kvm_vcpu *vcpu;
500
501 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
502 return;
503
504 vcpu = apic->vcpu;
fc57ac2c 505
8680b94b 506 /*
56cc2406
WL		 507 * With APIC virtualization enabled, all caching is disabled
508 * because the processor can modify ISR under the hood. Instead
509 * just set SVI.
8680b94b 510 */
d62caabb 511 if (unlikely(vcpu->arch.apicv_active))
afaf0b2f 512 kvm_x86_ops.hwapic_isr_update(vcpu, vec);
56cc2406
WL		 513 else {
514 ++apic->isr_count;
515 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
516 /*
517 * ISR (in service register) bit is set when injecting an interrupt.
518 * The highest vector is injected. Thus the latest bit set matches
519 * the highest bit in ISR.
520 */
521 apic->highest_isr_cache = vec;
522 }
8680b94b
MT		 523}
524
fc57ac2c
PB		 525static inline int apic_find_highest_isr(struct kvm_lapic *apic)
526{
527 int result;
528
529 /*
530 * Note that isr_count is always 1, and highest_isr_cache
531 * is always -1, with APIC virtualization enabled.
532 */
533 if (!apic->isr_count)
534 return -1;
535 if (likely(apic->highest_isr_cache != -1))
536 return apic->highest_isr_cache;
537
538 result = find_highest_vector(apic->regs + APIC_ISR);
539 ASSERT(result == -1 || result >= 16);
540
541 return result;
542}
543
8680b94b
MT		 544static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
545{
fc57ac2c
PB		 546 struct kvm_vcpu *vcpu;
547 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
548 return;
549
550 vcpu = apic->vcpu;
551
552 /*
553 * We do get here for APIC virtualization enabled if the guest
554 * uses the Hyper-V APIC enlightenment. In this case we may need
555 * to trigger a new interrupt delivery by writing the SVI field;
556 * on the other hand isr_count and highest_isr_cache are unused
557 * and must be left alone.
558 */
d62caabb 559 if (unlikely(vcpu->arch.apicv_active))
afaf0b2f 560 kvm_x86_ops.hwapic_isr_update(vcpu,
fc57ac2c
PB		 561 apic_find_highest_isr(apic));
562 else {
8680b94b 563 --apic->isr_count;
fc57ac2c
PB		 564 BUG_ON(apic->isr_count < 0);
565 apic->highest_isr_cache = -1;
566 }
8680b94b
MT		 567}
568
6e5d865c
YS		 569int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
570{
33e4c686
GN		 571 /* This may race with setting of irr in __apic_accept_irq() and
572 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
573 * will cause vmexit immediately and the value will be recalculated
574 * on the next vmentry.
575 */
f8543d6a 576 return apic_find_highest_irr(vcpu->arch.apic);
6e5d865c 577}
76dfafd5 578EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
6e5d865c 579
6da7e3f6 580static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 581 int vector, int level, int trig_mode,
9e4aabe2 582 struct dest_map *dest_map);
6da7e3f6 583
b4f2225c 584int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
9e4aabe2 585 struct dest_map *dest_map)
97222cc8 586{
ad312c7c 587 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 588
58c2dde1 589 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 590 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 591}
592
1a686237
ML		 593static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
594 struct kvm_lapic_irq *irq, u32 min)
595{
596 int i, count = 0;
597 struct kvm_vcpu *vcpu;
598
599 if (min > map->max_apic_id)
600 return 0;
601
602 for_each_set_bit(i, ipi_bitmap,
603 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
604 if (map->phys_map[min + i]) {
605 vcpu = map->phys_map[min + i]->vcpu;
606 count += kvm_apic_set_irq(vcpu, irq, NULL);
607 }
608 }
609
610 return count;
611}
612
4180bf1b 613int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
bdf7ffc8 614 unsigned long ipi_bitmap_high, u32 min,
4180bf1b
WL		 615 unsigned long icr, int op_64_bit)
616{
4180bf1b 617 struct kvm_apic_map *map;
4180bf1b
WL		 618 struct kvm_lapic_irq irq = {0};
619 int cluster_size = op_64_bit ? 64 : 32;
1a686237
ML		 620 int count;
621
622 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
623 return -KVM_EINVAL;
4180bf1b
WL		 624
625 irq.vector = icr & APIC_VECTOR_MASK;
626 irq.delivery_mode = icr & APIC_MODE_MASK;
627 irq.level = (icr & APIC_INT_ASSERT) != 0;
628 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
629
4180bf1b
WL		 630 rcu_read_lock();
631 map = rcu_dereference(kvm->arch.apic_map);
632
1a686237
ML		 633 count = -EOPNOTSUPP;
634 if (likely(map)) {
635 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
636 min += cluster_size;
637 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
4180bf1b
WL		 638 }
639
640 rcu_read_unlock();
641 return count;
642}
643
ae7a2a3f
MT		 644static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
645{
4e335d9e
PB		 646
647 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
648 sizeof(val));
ae7a2a3f
MT		 649}
650
651static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
652{
4e335d9e
PB		 653
654 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
655 sizeof(*val));
ae7a2a3f
MT		 656}
657
658static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
659{
660 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
661}
662
663static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
664{
665 u8 val;
23520b2d 666 if (pv_eoi_get_user(vcpu, &val) < 0) {
0d88800d 667 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
96893977 668 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
23520b2d
ML		 669 return false;
670 }
ae7a2a3f
MT		 671 return val & 0x1;
672}
673
674static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
675{
676 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
0d88800d 677 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
96893977 678 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 679 return;
680 }
681 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
682}
683
684static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
685{
686 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
0d88800d 687 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
96893977 688 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 689 return;
690 }
691 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
692}
693
b3c045d3
PB		 694static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
695{
3d92789f 696 int highest_irr;
fa59cc00 697 if (apic->vcpu->arch.apicv_active)
afaf0b2f 698 highest_irr = kvm_x86_ops.sync_pir_to_irr(apic->vcpu);
76dfafd5
PB		 699 else
700 highest_irr = apic_find_highest_irr(apic);
b3c045d3
PB		 701 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
702 return -1;
703 return highest_irr;
704}
705
706static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
97222cc8 707{
3842d135 708 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 709 int isr;
710
dfb95954
SS		 711 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
712 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 713 isr = apic_find_highest_isr(apic);
714 isrv = (isr != -1) ? isr : 0;
715
716 if ((tpr & 0xf0) >= (isrv & 0xf0))
717 ppr = tpr & 0xff;
718 else
719 ppr = isrv & 0xf0;
720
b3c045d3
PB		 721 *new_ppr = ppr;
722 if (old_ppr != ppr)
1e6e2755 723 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
b3c045d3
PB		 724
725 return ppr < old_ppr;
726}
727
728static void apic_update_ppr(struct kvm_lapic *apic)
729{
730 u32 ppr;
731
26fbbee5
PB		 732 if (__apic_update_ppr(apic, &ppr) &&
733 apic_has_interrupt_for_ppr(apic, ppr) != -1)
b3c045d3 734 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 735}
736
eb90f341
PB		 737void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
738{
739 apic_update_ppr(vcpu->arch.apic);
740}
741EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
742
97222cc8
ED		 743static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
744{
1e6e2755 745 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
97222cc8
ED		 746 apic_update_ppr(apic);
747}
748
03d2249e 749static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 750{
b4535b58
RK		 751 return mda == (apic_x2apic_mode(apic) ?
752 X2APIC_BROADCAST : APIC_BROADCAST);
394457a9
NA		 753}
754
03d2249e 755static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 756{
03d2249e
RK		 757 if (kvm_apic_broadcast(apic, mda))
758 return true;
759
760 if (apic_x2apic_mode(apic))
6e500439 761 return mda == kvm_x2apic_id(apic);
03d2249e 762
5bd5db38
RK		 763 /*
764 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
765 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
766 * this allows unique addressing of VCPUs with APIC ID over 0xff.
767 * The 0xff condition is needed because writeable xAPIC ID.
768 */
769 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
770 return true;
771
b4535b58 772 return mda == kvm_xapic_id(apic);
97222cc8
ED		 773}
774
52c233a4 775static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 776{
0105d1a5
GN		 777 u32 logical_id;
778
394457a9 779 if (kvm_apic_broadcast(apic, mda))
9368b567 780 return true;
394457a9 781
dfb95954 782 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
97222cc8 783
9368b567 784 if (apic_x2apic_mode(apic))
8a395363
RK		 785 return ((logical_id >> 16) == (mda >> 16))
786 && (logical_id & mda & 0xffff) != 0;
97222cc8 787
9368b567 788 logical_id = GET_APIC_LOGICAL_ID(logical_id);
97222cc8 789
dfb95954 790 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
97222cc8 791 case APIC_DFR_FLAT:
9368b567 792 return (logical_id & mda) != 0;
97222cc8 793 case APIC_DFR_CLUSTER:
9368b567
RK		 794 return ((logical_id >> 4) == (mda >> 4))
795 && (logical_id & mda & 0xf) != 0;
97222cc8 796 default:
9368b567 797 return false;
97222cc8 798 }
97222cc8
ED		 799}
800
c519265f
RK		 801/* The KVM local APIC implementation has two quirks:
802 *
b4535b58
RK		 803 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
804 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
805 * KVM doesn't do that aliasing.
c519265f
RK		 806 *
807 * - in-kernel IOAPIC messages have to be delivered directly to
808 * x2APIC, because the kernel does not support interrupt remapping.
809 * In order to support broadcast without interrupt remapping, x2APIC
810 * rewrites the destination of non-IPI messages from APIC_BROADCAST
811 * to X2APIC_BROADCAST.
812 *
813 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
814 * important when userspace wants to use x2APIC-format MSIs, because
815 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
03d2249e 816 */
c519265f
RK		 817static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
818 struct kvm_lapic *source, struct kvm_lapic *target)
03d2249e
RK		 819{
820 bool ipi = source != NULL;
03d2249e 821
c519265f 822 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
b4535b58 823 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
03d2249e
RK		 824 return X2APIC_BROADCAST;
825
b4535b58 826 return dest_id;
03d2249e
RK		 827}
828
52c233a4 829bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
5c69d5c1 830 int shorthand, unsigned int dest, int dest_mode)
97222cc8 831{
ad312c7c 832 struct kvm_lapic *target = vcpu->arch.apic;
c519265f 833 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
97222cc8 834
bd371396 835 ASSERT(target);
5c69d5c1 836 switch (shorthand) {
97222cc8 837 case APIC_DEST_NOSHORT:
3697f302 838 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 839 return kvm_apic_match_physical_addr(target, mda);
343f94fe 840 else
03d2249e 841 return kvm_apic_match_logical_addr(target, mda);
97222cc8 842 case APIC_DEST_SELF:
9368b567 843 return target == source;
97222cc8 844 case APIC_DEST_ALLINC:
9368b567 845 return true;
97222cc8 846 case APIC_DEST_ALLBUT:
9368b567 847 return target != source;
97222cc8 848 default:
9368b567 849 return false;
97222cc8 850 }
97222cc8 851}
1e6e2755 852EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
97222cc8 853
52004014
FW		 854int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
855 const unsigned long *bitmap, u32 bitmap_size)
856{
857 u32 mod;
858 int i, idx = -1;
859
860 mod = vector % dest_vcpus;
861
862 for (i = 0; i <= mod; i++) {
863 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
864 BUG_ON(idx == bitmap_size);
865 }
866
867 return idx;
868}
869
4efd805f
RK		 870static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
871{
872 if (!kvm->arch.disabled_lapic_found) {
873 kvm->arch.disabled_lapic_found = true;
874 printk(KERN_INFO
875 "Disabled LAPIC found during irq injection\n");
876 }
877}
878
c519265f
RK		 879static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
880 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
1e08ec4a 881{
c519265f
RK		 882 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
883 if ((irq->dest_id == APIC_BROADCAST &&
884 map->mode != KVM_APIC_MODE_X2APIC))
885 return true;
886 if (irq->dest_id == X2APIC_BROADCAST)
887 return true;
888 } else {
889 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
890 if (irq->dest_id == (x2apic_ipi ?
891 X2APIC_BROADCAST : APIC_BROADCAST))
892 return true;
893 }
1e08ec4a 894
c519265f
RK		 895 return false;
896}
1e08ec4a 897
64aa47bf
RK		 898/* Return true if the interrupt can be handled by using *bitmap as index mask
899 * for valid destinations in *dst array.
900 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
901 * Note: we may have zero kvm_lapic destinations when we return true, which
902 * means that the interrupt should be dropped. In this case, *bitmap would be
903 * zero and *dst undefined.
904 */
905static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
906 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
907 struct kvm_apic_map *map, struct kvm_lapic ***dst,
908 unsigned long *bitmap)
909{
910 int i, lowest;
1e08ec4a 911
64aa47bf
RK		 912 if (irq->shorthand == APIC_DEST_SELF && src) {
913 *dst = src;
914 *bitmap = 1;
915 return true;
916 } else if (irq->shorthand)
1e08ec4a
GN		 917 return false;
918
c519265f 919 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
9ea369b0
RK		 920 return false;
921
64aa47bf 922 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
0ca52e7b 923 if (irq->dest_id > map->max_apic_id) {
64aa47bf
RK		 924 *bitmap = 0;
925 } else {
1d487e9b
PB		 926 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
927 *dst = &map->phys_map[dest_id];
64aa47bf
RK		 928 *bitmap = 1;
929 }
1e08ec4a 930 return true;
bea15428 931 }
698f9755 932
e45115b6
RK		 933 *bitmap = 0;
934 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
935 (u16 *)bitmap))
1e08ec4a 936 return false;
fa834e91 937
64aa47bf
RK		 938 if (!kvm_lowest_prio_delivery(irq))
939 return true;
3548a259 940
64aa47bf
RK		 941 if (!kvm_vector_hashing_enabled()) {
942 lowest = -1;
943 for_each_set_bit(i, bitmap, 16) {
944 if (!(*dst)[i])
945 continue;
946 if (lowest < 0)
947 lowest = i;
948 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
949 (*dst)[lowest]->vcpu) < 0)
950 lowest = i;
3548a259 951 }
64aa47bf
RK		 952 } else {
953 if (!*bitmap)
954 return true;
3548a259 955
64aa47bf
RK		 956 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
957 bitmap, 16);
45c3094a 958
64aa47bf
RK		 959 if (!(*dst)[lowest]) {
960 kvm_apic_disabled_lapic_found(kvm);
961 *bitmap = 0;
962 return true;
963 }
964 }
1e08ec4a 965
64aa47bf 966 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
1e08ec4a 967
64aa47bf
RK		 968 return true;
969}
52004014 970
64aa47bf
RK		 971bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
972 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
973{
974 struct kvm_apic_map *map;
975 unsigned long bitmap;
976 struct kvm_lapic **dst = NULL;
977 int i;
978 bool ret;
52004014 979
64aa47bf 980 *r = -1;
52004014 981
64aa47bf
RK		 982 if (irq->shorthand == APIC_DEST_SELF) {
983 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
984 return true;
985 }
52004014 986
64aa47bf
RK		 987 rcu_read_lock();
988 map = rcu_dereference(kvm->arch.apic_map);
52004014 989
64aa47bf 990 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
0624fca9
PB		 991 if (ret) {
992 *r = 0;
64aa47bf
RK		 993 for_each_set_bit(i, &bitmap, 16) {
994 if (!dst[i])
995 continue;
64aa47bf 996 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 997 }
0624fca9 998 }
1e08ec4a 999
1e08ec4a
GN		 1000 rcu_read_unlock();
1001 return ret;
1002}
1003
6228a0da 1004/*
00116795 1005 * This routine tries to handle interrupts in posted mode, here is how
6228a0da
FW		 1006 * it deals with different cases:
1007 * - For single-destination interrupts, handle it in posted mode
1008 * - Else if vector hashing is enabled and it is a lowest-priority
1009 * interrupt, handle it in posted mode and use the following mechanism
67b0ae43 1010 * to find the destination vCPU.
6228a0da
FW		 1011 * 1. For lowest-priority interrupts, store all the possible
1012 * destination vCPUs in an array.
1013 * 2. Use "guest vector % max number of destination vCPUs" to find
1014 * the right destination vCPU in the array for the lowest-priority
1015 * interrupt.
1016 * - Otherwise, use remapped mode to inject the interrupt.
1017 */
8feb4a04
FW		 1018bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1019 struct kvm_vcpu **dest_vcpu)
1020{
1021 struct kvm_apic_map *map;
64aa47bf
RK		 1022 unsigned long bitmap;
1023 struct kvm_lapic **dst = NULL;
8feb4a04 1024 bool ret = false;
8feb4a04
FW		 1025
1026 if (irq->shorthand)
1027 return false;
1028
1029 rcu_read_lock();
1030 map = rcu_dereference(kvm->arch.apic_map);
1031
64aa47bf
RK		 1032 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1033 hweight16(bitmap) == 1) {
1034 unsigned long i = find_first_bit(&bitmap, 16);
6228a0da 1035
64aa47bf
RK		 1036 if (dst[i]) {
1037 *dest_vcpu = dst[i]->vcpu;
1038 ret = true;
6228a0da 1039 }
8feb4a04
FW		 1040 }
1041
8feb4a04
FW		 1042 rcu_read_unlock();
1043 return ret;
1044}
1045
97222cc8
ED		 1046/*
1047 * Add a pending IRQ into lapic.
1048 * Return 1 if successfully added and 0 if discarded.
1049 */
1050static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 1051 int vector, int level, int trig_mode,
9e4aabe2 1052 struct dest_map *dest_map)
97222cc8 1053{
6da7e3f6 1054 int result = 0;
c5ec1534 1055 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 1056
a183b638
PB		 1057 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1058 trig_mode, vector);
97222cc8 1059 switch (delivery_mode) {
97222cc8 1060 case APIC_DM_LOWEST:
e1035715 1061 vcpu->arch.apic_arb_prio++;
df561f66 1062 fallthrough;
e1035715 1063 case APIC_DM_FIXED:
bdaffe1d
PB		 1064 if (unlikely(trig_mode && !level))
1065 break;
1066
97222cc8
ED		 1067 /* FIXME add logic for vcpu on reset */
1068 if (unlikely(!apic_enabled(apic)))
1069 break;
1070
11f5cc05
JK		 1071 result = 1;
1072
9daa5007 1073 if (dest_map) {
9e4aabe2 1074 __set_bit(vcpu->vcpu_id, dest_map->map);
9daa5007
JR		 1075 dest_map->vectors[vcpu->vcpu_id] = vector;
1076 }
a5d36f82 1077
bdaffe1d
PB		 1078 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1079 if (trig_mode)
ee171d2f
WY		 1080 kvm_lapic_set_vector(vector,
1081 apic->regs + APIC_TMR);
bdaffe1d 1082 else
ee171d2f
WY		 1083 kvm_lapic_clear_vector(vector,
1084 apic->regs + APIC_TMR);
bdaffe1d
PB		 1085 }
1086
afaf0b2f 1087 if (kvm_x86_ops.deliver_posted_interrupt(vcpu, vector)) {
1e6e2755 1088 kvm_lapic_set_irr(vector, apic);
5a71785d
YZ		 1089 kvm_make_request(KVM_REQ_EVENT, vcpu);
1090 kvm_vcpu_kick(vcpu);
1091 }
97222cc8
ED		 1092 break;
1093
1094 case APIC_DM_REMRD:
24d2166b
R		 1095 result = 1;
1096 vcpu->arch.pv.pv_unhalted = 1;
1097 kvm_make_request(KVM_REQ_EVENT, vcpu);
1098 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1099 break;
1100
1101 case APIC_DM_SMI:
64d60670
PB		 1102 result = 1;
1103 kvm_make_request(KVM_REQ_SMI, vcpu);
1104 kvm_vcpu_kick(vcpu);
97222cc8 1105 break;
3419ffc8 1106
97222cc8 1107 case APIC_DM_NMI:
6da7e3f6 1108 result = 1;
3419ffc8 1109 kvm_inject_nmi(vcpu);
26df99c6 1110 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1111 break;
1112
1113 case APIC_DM_INIT:
a52315e1 1114 if (!trig_mode || level) {
6da7e3f6 1115 result = 1;
66450a21
JK		 1116 /* assumes that there are only KVM_APIC_INIT/SIPI */
1117 apic->pending_events = (1UL << KVM_APIC_INIT);
3842d135 1118 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534 1119 kvm_vcpu_kick(vcpu);
c5ec1534 1120 }
97222cc8
ED		 1121 break;
1122
1123 case APIC_DM_STARTUP:
66450a21
JK		 1124 result = 1;
1125 apic->sipi_vector = vector;
1126 /* make sure sipi_vector is visible for the receiver */
1127 smp_wmb();
1128 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1129 kvm_make_request(KVM_REQ_EVENT, vcpu);
1130 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1131 break;
1132
23930f95
JK		 1133 case APIC_DM_EXTINT:
1134 /*
1135 * Should only be called by kvm_apic_local_deliver() with LVT0,
1136 * before NMI watchdog was enabled. Already handled by
1137 * kvm_apic_accept_pic_intr().
1138 */
1139 break;
1140
97222cc8
ED		 1141 default:
1142 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1143 delivery_mode);
1144 break;
1145 }
1146 return result;
1147}
1148
7ee30bc1
NNL		 1149/*
1150 * This routine identifies the destination vcpus mask meant to receive the
1151 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1152 * out the destination vcpus array and set the bitmap or it traverses to
1153 * each available vcpu to identify the same.
1154 */
1155void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1156 unsigned long *vcpu_bitmap)
1157{
1158 struct kvm_lapic **dest_vcpu = NULL;
1159 struct kvm_lapic *src = NULL;
1160 struct kvm_apic_map *map;
1161 struct kvm_vcpu *vcpu;
1162 unsigned long bitmap;
1163 int i, vcpu_idx;
1164 bool ret;
1165
1166 rcu_read_lock();
1167 map = rcu_dereference(kvm->arch.apic_map);
1168
1169 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1170 &bitmap);
1171 if (ret) {
1172 for_each_set_bit(i, &bitmap, 16) {
1173 if (!dest_vcpu[i])
1174 continue;
1175 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1176 __set_bit(vcpu_idx, vcpu_bitmap);
1177 }
1178 } else {
1179 kvm_for_each_vcpu(i, vcpu, kvm) {
1180 if (!kvm_apic_present(vcpu))
1181 continue;
1182 if (!kvm_apic_match_dest(vcpu, NULL,
b4b29636 1183 irq->shorthand,
7ee30bc1
NNL		 1184 irq->dest_id,
1185 irq->dest_mode))
1186 continue;
1187 __set_bit(i, vcpu_bitmap);
1188 }
1189 }
1190 rcu_read_unlock();
1191}
1192
e1035715 1193int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 1194{
e1035715 1195 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 1196}
1197
3bb345f3
PB		 1198static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1199{
6308630b 1200 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
3bb345f3
PB		 1201}
1202
c7c9c56c
YZ		 1203static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1204{
7543a635
SR		 1205 int trigger_mode;
1206
1207 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1208 if (!kvm_ioapic_handles_vector(apic, vector))
1209 return;
3bb345f3 1210
7543a635
SR		 1211 /* Request a KVM exit to inform the userspace IOAPIC. */
1212 if (irqchip_split(apic->vcpu->kvm)) {
1213 apic->vcpu->arch.pending_ioapic_eoi = vector;
1214 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1215 return;
c7c9c56c 1216 }
7543a635
SR		 1217
1218 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1219 trigger_mode = IOAPIC_LEVEL_TRIG;
1220 else
1221 trigger_mode = IOAPIC_EDGE_TRIG;
1222
1223 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 1224}
1225
ae7a2a3f 1226static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 1227{
1228 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 1229
1230 trace_kvm_eoi(apic, vector);
1231
97222cc8
ED		 1232 /*
1233 * Not every write EOI will has corresponding ISR,
1234 * one example is when Kernel check timer on setup_IO_APIC
1235 */
1236 if (vector == -1)
ae7a2a3f 1237 return vector;
97222cc8 1238
8680b94b 1239 apic_clear_isr(vector, apic);
97222cc8
ED		 1240 apic_update_ppr(apic);
1241
5c919412
AS		 1242 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1243 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1244
c7c9c56c 1245 kvm_ioapic_send_eoi(apic, vector);
3842d135 1246 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 1247 return vector;
97222cc8
ED		 1248}
1249
c7c9c56c
YZ		 1250/*
1251 * this interface assumes a trap-like exit, which has already finished
1252 * desired side effect including vISR and vPPR update.
1253 */
1254void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1255{
1256 struct kvm_lapic *apic = vcpu->arch.apic;
1257
1258 trace_kvm_eoi(apic, vector);
1259
1260 kvm_ioapic_send_eoi(apic, vector);
1261 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1262}
1263EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1264
d5361678 1265void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
97222cc8 1266{
58c2dde1 1267 struct kvm_lapic_irq irq;
97222cc8 1268
58c2dde1
GN		 1269 irq.vector = icr_low & APIC_VECTOR_MASK;
1270 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1271 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 1272 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 1273 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1274 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 1275 irq.msi_redir_hint = false;
0105d1a5
GN		 1276 if (apic_x2apic_mode(apic))
1277 irq.dest_id = icr_high;
1278 else
1279 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 1280
1000ff8d
GN		 1281 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1282
b4f2225c 1283 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 1284}
1285
1286static u32 apic_get_tmcct(struct kvm_lapic *apic)
1287{
8003c9ae 1288 ktime_t remaining, now;
b682b814 1289 s64 ns;
9da8f4e8 1290 u32 tmcct;
97222cc8
ED		 1291
1292 ASSERT(apic != NULL);
1293
9da8f4e8 1294 /* if initial count is 0, current count should also be 0 */
dfb95954 1295 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
b963a22e 1296 apic->lapic_timer.period == 0)
9da8f4e8
KP		 1297 return 0;
1298
5587859f 1299 now = ktime_get();
8003c9ae 1300 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
b682b814 1301 if (ktime_to_ns(remaining) < 0)
8b0e1953 1302 remaining = 0;
b682b814 1303
d3c7b77d
MT		 1304 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1305 tmcct = div64_u64(ns,
1306 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 1307
1308 return tmcct;
1309}
1310
b209749f
AK		 1311static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1312{
1313 struct kvm_vcpu *vcpu = apic->vcpu;
1314 struct kvm_run *run = vcpu->run;
1315
a8eeb04a 1316 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 1317 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 1318 run->tpr_access.is_write = write;
1319}
1320
1321static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1322{
1323 if (apic->vcpu->arch.tpr_access_reporting)
1324 __report_tpr_access(apic, write);
1325}
1326
97222cc8
ED		 1327static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1328{
1329 u32 val = 0;
1330
1331 if (offset >= LAPIC_MMIO_LENGTH)
1332 return 0;
1333
1334 switch (offset) {
1335 case APIC_ARBPRI:
97222cc8
ED		 1336 break;
1337
1338 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1339 if (apic_lvtt_tscdeadline(apic))
1340 return 0;
1341
97222cc8
ED		 1342 val = apic_get_tmcct(apic);
1343 break;
4a4541a4
AK		 1344 case APIC_PROCPRI:
1345 apic_update_ppr(apic);
dfb95954 1346 val = kvm_lapic_get_reg(apic, offset);
4a4541a4 1347 break;
b209749f
AK		 1348 case APIC_TASKPRI:
1349 report_tpr_access(apic, false);
df561f66 1350 fallthrough;
97222cc8 1351 default:
dfb95954 1352 val = kvm_lapic_get_reg(apic, offset);
97222cc8
ED		 1353 break;
1354 }
1355
1356 return val;
1357}
1358
d76685c4
GH		 1359static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1360{
1361 return container_of(dev, struct kvm_lapic, dev);
1362}
1363
01402cf8
PB		 1364#define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1365#define APIC_REGS_MASK(first, count) \
1366 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1367
1e6e2755 1368int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
0105d1a5 1369 void *data)
97222cc8 1370{
97222cc8
ED		 1371 unsigned char alignment = offset & 0xf;
1372 u32 result;
d5b0b5b1 1373 /* this bitmask has a bit cleared for each reserved register */
01402cf8
PB		 1374 u64 valid_reg_mask =
1375 APIC_REG_MASK(APIC_ID) |
1376 APIC_REG_MASK(APIC_LVR) |
1377 APIC_REG_MASK(APIC_TASKPRI) |
1378 APIC_REG_MASK(APIC_PROCPRI) |
1379 APIC_REG_MASK(APIC_LDR) |
1380 APIC_REG_MASK(APIC_DFR) |
1381 APIC_REG_MASK(APIC_SPIV) |
1382 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1383 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1384 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1385 APIC_REG_MASK(APIC_ESR) |
1386 APIC_REG_MASK(APIC_ICR) |
1387 APIC_REG_MASK(APIC_ICR2) |
1388 APIC_REG_MASK(APIC_LVTT) |
1389 APIC_REG_MASK(APIC_LVTTHMR) |
1390 APIC_REG_MASK(APIC_LVTPC) |
1391 APIC_REG_MASK(APIC_LVT0) |
1392 APIC_REG_MASK(APIC_LVT1) |
1393 APIC_REG_MASK(APIC_LVTERR) |
1394 APIC_REG_MASK(APIC_TMICT) |
1395 APIC_REG_MASK(APIC_TMCCT) |
1396 APIC_REG_MASK(APIC_TDCR);
1397
1398 /* ARBPRI is not valid on x2APIC */
1399 if (!apic_x2apic_mode(apic))
1400 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
0105d1a5 1401
0d88800d 1402 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
0105d1a5 1403 return 1;
0105d1a5 1404
97222cc8
ED		 1405 result = __apic_read(apic, offset & ~0xf);
1406
229456fc
MT		 1407 trace_kvm_apic_read(offset, result);
1408
97222cc8
ED		 1409 switch (len) {
1410 case 1:
1411 case 2:
1412 case 4:
1413 memcpy(data, (char *)&result + alignment, len);
1414 break;
1415 default:
1416 printk(KERN_ERR "Local APIC read with len = %x, "
1417 "should be 1,2, or 4 instead\n", len);
1418 break;
1419 }
bda9020e 1420 return 0;
97222cc8 1421}
1e6e2755 1422EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
97222cc8 1423
0105d1a5
GN		 1424static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1425{
d1766202
VK		 1426 return addr >= apic->base_address &&
1427 addr < apic->base_address + LAPIC_MMIO_LENGTH;
0105d1a5
GN		 1428}
1429
e32edf4f 1430static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1431 gpa_t address, int len, void *data)
1432{
1433 struct kvm_lapic *apic = to_lapic(this);
1434 u32 offset = address - apic->base_address;
1435
1436 if (!apic_mmio_in_range(apic, address))
1437 return -EOPNOTSUPP;
1438
d1766202
VK		 1439 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1440 if (!kvm_check_has_quirk(vcpu->kvm,
1441 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1442 return -EOPNOTSUPP;
1443
1444 memset(data, 0xff, len);
1445 return 0;
1446 }
1447
1e6e2755 1448 kvm_lapic_reg_read(apic, offset, len, data);
0105d1a5
GN		 1449
1450 return 0;
1451}
1452
97222cc8
ED		 1453static void update_divide_count(struct kvm_lapic *apic)
1454{
1455 u32 tmp1, tmp2, tdcr;
1456
dfb95954 1457 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1458 tmp1 = tdcr & 0xf;
1459 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1460 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1461}
1462
ccbfa1d3
WL		 1463static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1464{
1465 /*
1466 * Do not allow the guest to program periodic timers with small
1467 * interval, since the hrtimers are not throttled by the host
1468 * scheduler.
1469 */
dedf9c5e 1470 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
ccbfa1d3
WL		 1471 s64 min_period = min_timer_period_us * 1000LL;
1472
1473 if (apic->lapic_timer.period < min_period) {
1474 pr_info_ratelimited(
1475 "kvm: vcpu %i: requested %lld ns "
1476 "lapic timer period limited to %lld ns\n",
1477 apic->vcpu->vcpu_id,
1478 apic->lapic_timer.period, min_period);
1479 apic->lapic_timer.period = min_period;
1480 }
1481 }
1482}
1483
94be4b85
WL		 1484static void cancel_hv_timer(struct kvm_lapic *apic);
1485
b6ac0695
RK		 1486static void apic_update_lvtt(struct kvm_lapic *apic)
1487{
dfb95954 1488 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
b6ac0695
RK		 1489 apic->lapic_timer.timer_mode_mask;
1490
1491 if (apic->lapic_timer.timer_mode != timer_mode) {
c69518c8 1492 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
dedf9c5e 1493 APIC_LVT_TIMER_TSCDEADLINE)) {
dedf9c5e 1494 hrtimer_cancel(&apic->lapic_timer.timer);
94be4b85
WL		 1495 preempt_disable();
1496 if (apic->lapic_timer.hv_timer_in_use)
1497 cancel_hv_timer(apic);
1498 preempt_enable();
44275932
RK		 1499 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1500 apic->lapic_timer.period = 0;
1501 apic->lapic_timer.tscdeadline = 0;
dedf9c5e 1502 }
b6ac0695 1503 apic->lapic_timer.timer_mode = timer_mode;
dedf9c5e 1504 limit_periodic_timer_frequency(apic);
b6ac0695
RK		 1505 }
1506}
1507
d0659d94
MT		 1508/*
1509 * On APICv, this test will cause a busy wait
1510 * during a higher-priority task.
1511 */
1512
1513static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1514{
1515 struct kvm_lapic *apic = vcpu->arch.apic;
dfb95954 1516 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
d0659d94
MT		 1517
1518 if (kvm_apic_hw_enabled(apic)) {
1519 int vec = reg & APIC_VECTOR_MASK;
f9339860 1520 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1521
d62caabb 1522 if (vcpu->arch.apicv_active)
f9339860
MT		 1523 bitmap = apic->regs + APIC_IRR;
1524
1525 if (apic_test_vector(vec, bitmap))
1526 return true;
d0659d94
MT		 1527 }
1528 return false;
1529}
1530
b6aa57c6
SC		 1531static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1532{
1533 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1534
1535 /*
1536 * If the guest TSC is running at a different ratio than the host, then
1537 * convert the delay to nanoseconds to achieve an accurate delay. Note
1538 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1539 * always for VMX enabled hardware.
1540 */
1541 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1542 __delay(min(guest_cycles,
1543 nsec_to_cycles(vcpu, timer_advance_ns)));
1544 } else {
1545 u64 delay_ns = guest_cycles * 1000000ULL;
1546 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1547 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1548 }
1549}
1550
84ea3aca 1551static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
ec0671d5 1552 s64 advance_expire_delta)
d0659d94
MT		 1553{
1554 struct kvm_lapic *apic = vcpu->arch.apic;
39497d76 1555 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
84ea3aca
WL		 1556 u64 ns;
1557
d0f5a86a
WL		 1558 /* Do not adjust for tiny fluctuations or large random spikes. */
1559 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1560 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1561 return;
1562
84ea3aca 1563 /* too early */
ec0671d5
WL		 1564 if (advance_expire_delta < 0) {
1565 ns = -advance_expire_delta * 1000000ULL;
84ea3aca 1566 do_div(ns, vcpu->arch.virtual_tsc_khz);
d0f5a86a 1567 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
84ea3aca
WL		 1568 } else {
1569 /* too late */
ec0671d5 1570 ns = advance_expire_delta * 1000000ULL;
84ea3aca 1571 do_div(ns, vcpu->arch.virtual_tsc_khz);
d0f5a86a 1572 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
84ea3aca
WL		 1573 }
1574
a0f0037e
WL		 1575 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1576 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
84ea3aca
WL		 1577 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1578}
1579
0c5f81da 1580static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
84ea3aca
WL		 1581{
1582 struct kvm_lapic *apic = vcpu->arch.apic;
1583 u64 guest_tsc, tsc_deadline;
d0659d94 1584
d0659d94
MT		 1585 if (apic->lapic_timer.expired_tscdeadline == 0)
1586 return;
1587
d0659d94
MT		 1588 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1589 apic->lapic_timer.expired_tscdeadline = 0;
4ba76538 1590 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
ec0671d5 1591 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
d0659d94 1592
d0659d94 1593 if (guest_tsc < tsc_deadline)
b6aa57c6 1594 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
3b8a5df6 1595
d0f5a86a 1596 if (lapic_timer_advance_dynamic)
ec0671d5 1597 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
5d87db71 1598}
0c5f81da
WL		 1599
1600void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1601{
1602 if (lapic_timer_int_injected(vcpu))
1603 __kvm_wait_lapic_expire(vcpu);
1604}
b6c4bc65 1605EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
5d87db71 1606
0c5f81da
WL		 1607static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1608{
1609 struct kvm_timer *ktimer = &apic->lapic_timer;
1610
1611 kvm_apic_local_deliver(apic, APIC_LVTT);
17ac43a8 1612 if (apic_lvtt_tscdeadline(apic)) {
0c5f81da 1613 ktimer->tscdeadline = 0;
17ac43a8 1614 } else if (apic_lvtt_oneshot(apic)) {
0c5f81da
WL		 1615 ktimer->tscdeadline = 0;
1616 ktimer->target_expiration = 0;
1617 }
1618}
1619
ae95f566 1620static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
0c5f81da
WL		 1621{
1622 struct kvm_vcpu *vcpu = apic->vcpu;
0c5f81da
WL		 1623 struct kvm_timer *ktimer = &apic->lapic_timer;
1624
1625 if (atomic_read(&apic->lapic_timer.pending))
1626 return;
1627
1628 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1629 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1630
ae95f566
WL		 1631 if (!from_timer_fn && vcpu->arch.apicv_active) {
1632 WARN_ON(kvm_get_running_vcpu() != vcpu);
1633 kvm_apic_inject_pending_timer_irqs(apic);
1634 return;
1635 }
1636
0c5f81da
WL		 1637 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1638 if (apic->lapic_timer.timer_advance_ns)
1639 __kvm_wait_lapic_expire(vcpu);
1640 kvm_apic_inject_pending_timer_irqs(apic);
1641 return;
1642 }
1643
1644 atomic_inc(&apic->lapic_timer.pending);
1645 kvm_set_pending_timer(vcpu);
0c5f81da
WL		 1646}
1647
53f9eedf
YJ		 1648static void start_sw_tscdeadline(struct kvm_lapic *apic)
1649{
39497d76
SC		 1650 struct kvm_timer *ktimer = &apic->lapic_timer;
1651 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
53f9eedf
YJ		 1652 u64 ns = 0;
1653 ktime_t expire;
1654 struct kvm_vcpu *vcpu = apic->vcpu;
1655 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1656 unsigned long flags;
1657 ktime_t now;
1658
1659 if (unlikely(!tscdeadline || !this_tsc_khz))
1660 return;
1661
1662 local_irq_save(flags);
1663
5587859f 1664 now = ktime_get();
53f9eedf 1665 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
c09d65d9
LA		 1666
1667 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1668 do_div(ns, this_tsc_khz);
1669
1670 if (likely(tscdeadline > guest_tsc) &&
39497d76 1671 likely(ns > apic->lapic_timer.timer_advance_ns)) {
53f9eedf 1672 expire = ktime_add_ns(now, ns);
39497d76 1673 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
2c0d278f 1674 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
53f9eedf 1675 } else
ae95f566 1676 apic_timer_expired(apic, false);
53f9eedf
YJ		 1677
1678 local_irq_restore(flags);
1679}
1680
24647e0a
PS		 1681static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1682{
1683 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
1684}
1685
c301b909
WL		 1686static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1687{
1688 ktime_t now, remaining;
1689 u64 ns_remaining_old, ns_remaining_new;
1690
24647e0a
PS		 1691 apic->lapic_timer.period =
1692 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
c301b909
WL		 1693 limit_periodic_timer_frequency(apic);
1694
1695 now = ktime_get();
1696 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1697 if (ktime_to_ns(remaining) < 0)
1698 remaining = 0;
1699
1700 ns_remaining_old = ktime_to_ns(remaining);
1701 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1702 apic->divide_count, old_divisor);
1703
1704 apic->lapic_timer.tscdeadline +=
1705 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1706 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1707 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1708}
1709
24647e0a 1710static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
7d7f7da2
WL		 1711{
1712 ktime_t now;
8003c9ae 1713 u64 tscl = rdtsc();
24647e0a 1714 s64 deadline;
7d7f7da2 1715
5587859f 1716 now = ktime_get();
24647e0a
PS		 1717 apic->lapic_timer.period =
1718 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
7d7f7da2 1719
5d74a699
RK		 1720 if (!apic->lapic_timer.period) {
1721 apic->lapic_timer.tscdeadline = 0;
8003c9ae 1722 return false;
7d7f7da2
WL		 1723 }
1724
ccbfa1d3 1725 limit_periodic_timer_frequency(apic);
24647e0a
PS		 1726 deadline = apic->lapic_timer.period;
1727
1728 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1729 if (unlikely(count_reg != APIC_TMICT)) {
1730 deadline = tmict_to_ns(apic,
1731 kvm_lapic_get_reg(apic, count_reg));
1732 if (unlikely(deadline <= 0))
1733 deadline = apic->lapic_timer.period;
1734 else if (unlikely(deadline > apic->lapic_timer.period)) {
1735 pr_info_ratelimited(
1736 "kvm: vcpu %i: requested lapic timer restore with "
1737 "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
1738 "Using initial count to start timer.\n",
1739 apic->vcpu->vcpu_id,
1740 count_reg,
1741 kvm_lapic_get_reg(apic, count_reg),
1742 deadline, apic->lapic_timer.period);
1743 kvm_lapic_set_reg(apic, count_reg, 0);
1744 deadline = apic->lapic_timer.period;
1745 }
1746 }
1747 }
7d7f7da2 1748
8003c9ae 1749 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
24647e0a
PS		 1750 nsec_to_cycles(apic->vcpu, deadline);
1751 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
8003c9ae
WL		 1752
1753 return true;
1754}
1755
1756static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1757{
d8f2f498
DV		 1758 ktime_t now = ktime_get();
1759 u64 tscl = rdtsc();
1760 ktime_t delta;
1761
1762 /*
1763 * Synchronize both deadlines to the same time source or
1764 * differences in the periods (caused by differences in the
1765 * underlying clocks or numerical approximation errors) will
1766 * cause the two to drift apart over time as the errors
1767 * accumulate.
1768 */
8003c9ae
WL		 1769 apic->lapic_timer.target_expiration =
1770 ktime_add_ns(apic->lapic_timer.target_expiration,
1771 apic->lapic_timer.period);
d8f2f498
DV		 1772 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1773 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1774 nsec_to_cycles(apic->vcpu, delta);
7d7f7da2
WL		 1775}
1776
ecf08dad
AB		 1777static void start_sw_period(struct kvm_lapic *apic)
1778{
1779 if (!apic->lapic_timer.period)
1780 return;
1781
1782 if (ktime_after(ktime_get(),
1783 apic->lapic_timer.target_expiration)) {
ae95f566 1784 apic_timer_expired(apic, false);
ecf08dad
AB		 1785
1786 if (apic_lvtt_oneshot(apic))
1787 return;
1788
1789 advance_periodic_target_expiration(apic);
1790 }
1791
1792 hrtimer_start(&apic->lapic_timer.timer,
1793 apic->lapic_timer.target_expiration,
edec6e01 1794 HRTIMER_MODE_ABS_HARD);
ecf08dad
AB		 1795}
1796
ce7a058a
YJ		 1797bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1798{
91005300
WL		 1799 if (!lapic_in_kernel(vcpu))
1800 return false;
1801
ce7a058a
YJ		 1802 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1803}
1804EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1805
7e810a38 1806static void cancel_hv_timer(struct kvm_lapic *apic)
bd97ad0e 1807{
1d518c68 1808 WARN_ON(preemptible());
a749e247 1809 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
afaf0b2f 1810 kvm_x86_ops.cancel_hv_timer(apic->vcpu);
bd97ad0e
WL		 1811 apic->lapic_timer.hv_timer_in_use = false;
1812}
1813
a749e247 1814static bool start_hv_timer(struct kvm_lapic *apic)
196f20ca 1815{
35ee9e48 1816 struct kvm_timer *ktimer = &apic->lapic_timer;
f9927982
SC		 1817 struct kvm_vcpu *vcpu = apic->vcpu;
1818 bool expired;
196f20ca 1819
1d518c68 1820 WARN_ON(preemptible());
199a8b84 1821 if (!kvm_can_use_hv_timer(vcpu))
a749e247
PB		 1822 return false;
1823
86bbc1e6
RK		 1824 if (!ktimer->tscdeadline)
1825 return false;
1826
afaf0b2f 1827 if (kvm_x86_ops.set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
35ee9e48
PB		 1828 return false;
1829
1830 ktimer->hv_timer_in_use = true;
1831 hrtimer_cancel(&ktimer->timer);
196f20ca 1832
35ee9e48 1833 /*
f1ba5cfb
SC		 1834 * To simplify handling the periodic timer, leave the hv timer running
1835 * even if the deadline timer has expired, i.e. rely on the resulting
1836 * VM-Exit to recompute the periodic timer's target expiration.
35ee9e48 1837 */
f1ba5cfb
SC		 1838 if (!apic_lvtt_period(apic)) {
1839 /*
1840 * Cancel the hv timer if the sw timer fired while the hv timer
1841 * was being programmed, or if the hv timer itself expired.
1842 */
1843 if (atomic_read(&ktimer->pending)) {
1844 cancel_hv_timer(apic);
f9927982 1845 } else if (expired) {
ae95f566 1846 apic_timer_expired(apic, false);
f1ba5cfb
SC		 1847 cancel_hv_timer(apic);
1848 }
c8533544 1849 }
a749e247 1850
f9927982 1851 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
f1ba5cfb 1852
35ee9e48
PB		 1853 return true;
1854}
1855
a749e247 1856static void start_sw_timer(struct kvm_lapic *apic)
35ee9e48 1857{
a749e247 1858 struct kvm_timer *ktimer = &apic->lapic_timer;
1d518c68
WL		 1859
1860 WARN_ON(preemptible());
a749e247
PB		 1861 if (apic->lapic_timer.hv_timer_in_use)
1862 cancel_hv_timer(apic);
1863 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1864 return;
1865
1866 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1867 start_sw_period(apic);
1868 else if (apic_lvtt_tscdeadline(apic))
1869 start_sw_tscdeadline(apic);
1870 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1871}
35ee9e48 1872
a749e247
PB		 1873static void restart_apic_timer(struct kvm_lapic *apic)
1874{
1d518c68 1875 preempt_disable();
4ca88b3f
SC		 1876
1877 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1878 goto out;
1879
a749e247
PB		 1880 if (!start_hv_timer(apic))
1881 start_sw_timer(apic);
4ca88b3f 1882out:
1d518c68 1883 preempt_enable();
196f20ca
WL		 1884}
1885
8003c9ae
WL		 1886void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1887{
1888 struct kvm_lapic *apic = vcpu->arch.apic;
1889
1d518c68
WL		 1890 preempt_disable();
1891 /* If the preempt notifier has already run, it also called apic_timer_expired */
1892 if (!apic->lapic_timer.hv_timer_in_use)
1893 goto out;
da4ad88c 1894 WARN_ON(rcuwait_active(&vcpu->wait));
8003c9ae 1895 cancel_hv_timer(apic);
ae95f566 1896 apic_timer_expired(apic, false);
8003c9ae
WL		 1897
1898 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1899 advance_periodic_target_expiration(apic);
a749e247 1900 restart_apic_timer(apic);
8003c9ae 1901 }
1d518c68
WL		 1902out:
1903 preempt_enable();
8003c9ae
WL		 1904}
1905EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1906
ce7a058a
YJ		 1907void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1908{
a749e247 1909 restart_apic_timer(vcpu->arch.apic);
ce7a058a
YJ		 1910}
1911EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1912
1913void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1914{
1915 struct kvm_lapic *apic = vcpu->arch.apic;
1916
1d518c68 1917 preempt_disable();
ce7a058a 1918 /* Possibly the TSC deadline timer is not enabled yet */
a749e247
PB		 1919 if (apic->lapic_timer.hv_timer_in_use)
1920 start_sw_timer(apic);
1d518c68 1921 preempt_enable();
a749e247
PB		 1922}
1923EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
ce7a058a 1924
a749e247
PB		 1925void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1926{
1927 struct kvm_lapic *apic = vcpu->arch.apic;
ce7a058a 1928
a749e247
PB		 1929 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1930 restart_apic_timer(apic);
ce7a058a 1931}
ce7a058a 1932
24647e0a 1933static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
97222cc8 1934{
d3c7b77d 1935 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1936
a749e247 1937 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
24647e0a 1938 && !set_target_expiration(apic, count_reg))
a749e247
PB		 1939 return;
1940
1941 restart_apic_timer(apic);
97222cc8
ED		 1942}
1943
24647e0a
PS		 1944static void start_apic_timer(struct kvm_lapic *apic)
1945{
1946 __start_apic_timer(apic, APIC_TMICT);
1947}
1948
cc6e462c
JK		 1949static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1950{
59fd1323 1951 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1952
59fd1323
RK		 1953 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1954 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1955 if (lvt0_in_nmi_mode) {
42720138 1956 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1957 } else
1958 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1959 }
cc6e462c
JK		 1960}
1961
1e6e2755 1962int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1963{
0105d1a5 1964 int ret = 0;
97222cc8 1965
0105d1a5 1966 trace_kvm_apic_write(reg, val);
97222cc8 1967
0105d1a5 1968 switch (reg) {
97222cc8 1969 case APIC_ID: /* Local APIC ID */
0105d1a5 1970 if (!apic_x2apic_mode(apic))
a92e2543 1971 kvm_apic_set_xapic_id(apic, val >> 24);
0105d1a5
GN		 1972 else
1973 ret = 1;
97222cc8
ED		 1974 break;
1975
1976 case APIC_TASKPRI:
b209749f 1977 report_tpr_access(apic, true);
97222cc8
ED		 1978 apic_set_tpr(apic, val & 0xff);
1979 break;
1980
1981 case APIC_EOI:
1982 apic_set_eoi(apic);
1983 break;
1984
1985 case APIC_LDR:
0105d1a5 1986 if (!apic_x2apic_mode(apic))
1e08ec4a 1987 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1988 else
1989 ret = 1;
97222cc8
ED		 1990 break;
1991
1992 case APIC_DFR:
ae6f2496
WL		 1993 if (!apic_x2apic_mode(apic))
1994 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
1995 else
0105d1a5 1996 ret = 1;
97222cc8
ED		 1997 break;
1998
fc61b800
GN		 1999 case APIC_SPIV: {
2000 u32 mask = 0x3ff;
dfb95954 2001 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 2002 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 2003 apic_set_spiv(apic, val & mask);
97222cc8
ED		 2004 if (!(val & APIC_SPIV_APIC_ENABLED)) {
2005 int i;
2006 u32 lvt_val;
2007
1e6e2755 2008 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
dfb95954 2009 lvt_val = kvm_lapic_get_reg(apic,
97222cc8 2010 APIC_LVTT + 0x10 * i);
1e6e2755 2011 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
97222cc8
ED		 2012 lvt_val | APIC_LVT_MASKED);
2013 }
b6ac0695 2014 apic_update_lvtt(apic);
d3c7b77d 2015 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 2016
2017 }
2018 break;
fc61b800 2019 }
97222cc8
ED		 2020 case APIC_ICR:
2021 /* No delay here, so we always clear the pending bit */
2b0911d1 2022 val &= ~(1 << 12);
d5361678 2023 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2b0911d1 2024 kvm_lapic_set_reg(apic, APIC_ICR, val);
97222cc8
ED		 2025 break;
2026
2027 case APIC_ICR2:
0105d1a5
GN		 2028 if (!apic_x2apic_mode(apic))
2029 val &= 0xff000000;
1e6e2755 2030 kvm_lapic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 2031 break;
2032
23930f95 2033 case APIC_LVT0:
cc6e462c 2034 apic_manage_nmi_watchdog(apic, val);
df561f66 2035 fallthrough;
97222cc8
ED		 2036 case APIC_LVTTHMR:
2037 case APIC_LVTPC:
97222cc8 2038 case APIC_LVT1:
4bf79cb0 2039 case APIC_LVTERR: {
97222cc8 2040 /* TODO: Check vector */
4bf79cb0
MP		 2041 size_t size;
2042 u32 index;
2043
c48f1496 2044 if (!kvm_apic_sw_enabled(apic))
97222cc8 2045 val |= APIC_LVT_MASKED;
4bf79cb0
MP		 2046 size = ARRAY_SIZE(apic_lvt_mask);
2047 index = array_index_nospec(
2048 (reg - APIC_LVTT) >> 4, size);
2049 val &= apic_lvt_mask[index];
1e6e2755 2050 kvm_lapic_set_reg(apic, reg, val);
97222cc8 2051 break;
4bf79cb0 2052 }
97222cc8 2053
b6ac0695 2054 case APIC_LVTT:
c48f1496 2055 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 2056 val |= APIC_LVT_MASKED;
2057 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1e6e2755 2058 kvm_lapic_set_reg(apic, APIC_LVTT, val);
b6ac0695 2059 apic_update_lvtt(apic);
a3e06bbe
LJ		 2060 break;
2061
97222cc8 2062 case APIC_TMICT:
a3e06bbe
LJ		 2063 if (apic_lvtt_tscdeadline(apic))
2064 break;
2065
d3c7b77d 2066 hrtimer_cancel(&apic->lapic_timer.timer);
1e6e2755 2067 kvm_lapic_set_reg(apic, APIC_TMICT, val);
97222cc8 2068 start_apic_timer(apic);
0105d1a5 2069 break;
97222cc8 2070
c301b909
WL		 2071 case APIC_TDCR: {
2072 uint32_t old_divisor = apic->divide_count;
2073
a445fc45 2074 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
97222cc8 2075 update_divide_count(apic);
c301b909
WL		 2076 if (apic->divide_count != old_divisor &&
2077 apic->lapic_timer.period) {
2078 hrtimer_cancel(&apic->lapic_timer.timer);
2079 update_target_expiration(apic, old_divisor);
2080 restart_apic_timer(apic);
2081 }
97222cc8 2082 break;
c301b909 2083 }
0105d1a5 2084 case APIC_ESR:
0d88800d 2085 if (apic_x2apic_mode(apic) && val != 0)
0105d1a5 2086 ret = 1;
0105d1a5
GN		 2087 break;
2088
2089 case APIC_SELF_IPI:
2090 if (apic_x2apic_mode(apic)) {
9c2475f3
HL		 2091 kvm_lapic_reg_write(apic, APIC_ICR,
2092 APIC_DEST_SELF | (val & APIC_VECTOR_MASK));
0105d1a5
GN		 2093 } else
2094 ret = 1;
2095 break;
97222cc8 2096 default:
0105d1a5 2097 ret = 1;
97222cc8
ED		 2098 break;
2099 }
0d88800d 2100
4abaffce
WL		 2101 kvm_recalculate_apic_map(apic->vcpu->kvm);
2102
0105d1a5
GN		 2103 return ret;
2104}
1e6e2755 2105EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
0105d1a5 2106
e32edf4f 2107static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 2108 gpa_t address, int len, const void *data)
2109{
2110 struct kvm_lapic *apic = to_lapic(this);
2111 unsigned int offset = address - apic->base_address;
2112 u32 val;
2113
2114 if (!apic_mmio_in_range(apic, address))
2115 return -EOPNOTSUPP;
2116
d1766202
VK		 2117 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2118 if (!kvm_check_has_quirk(vcpu->kvm,
2119 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2120 return -EOPNOTSUPP;
2121
2122 return 0;
2123 }
2124
0105d1a5
GN		 2125 /*
2126 * APIC register must be aligned on 128-bits boundary.
2127 * 32/64/128 bits registers must be accessed thru 32 bits.
2128 * Refer SDM 8.4.1
2129 */
0d88800d 2130 if (len != 4 || (offset & 0xf))
756975bb 2131 return 0;
0105d1a5
GN		 2132
2133 val = *(u32*)data;
2134
0d88800d 2135 kvm_lapic_reg_write(apic, offset & 0xff0, val);
0105d1a5 2136
bda9020e 2137 return 0;
97222cc8
ED		 2138}
2139
58fbbf26
KT		 2140void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2141{
1e6e2755 2142 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
58fbbf26
KT		 2143}
2144EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2145
83d4c286
YZ		 2146/* emulate APIC access in a trap manner */
2147void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2148{
2149 u32 val = 0;
2150
2151 /* hw has done the conditional check and inst decode */
2152 offset &= 0xff0;
2153
1e6e2755 2154 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
83d4c286
YZ		 2155
2156 /* TODO: optimize to just emulate side effect w/o one more write */
1e6e2755 2157 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
83d4c286
YZ		 2158}
2159EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2160
d589444e 2161void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 2162{
f8c1ea10
GN		 2163 struct kvm_lapic *apic = vcpu->arch.apic;
2164
ad312c7c 2165 if (!vcpu->arch.apic)
97222cc8
ED		 2166 return;
2167
f8c1ea10 2168 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 2169
c5cc421b
GN		 2170 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2171 static_key_slow_dec_deferred(&apic_hw_disabled);
2172
e462755c 2173 if (!apic->sw_enabled)
f8c1ea10 2174 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 2175
f8c1ea10
GN		 2176 if (apic->regs)
2177 free_page((unsigned long)apic->regs);
2178
2179 kfree(apic);
97222cc8
ED		 2180}
2181
2182/*
2183 *----------------------------------------------------------------------
2184 * LAPIC interface
2185 *----------------------------------------------------------------------
2186 */
a3e06bbe
LJ		 2187u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2188{
2189 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 2190
a10388e1
WL		 2191 if (!lapic_in_kernel(vcpu) ||
2192 !apic_lvtt_tscdeadline(apic))
a3e06bbe
LJ		 2193 return 0;
2194
2195 return apic->lapic_timer.tscdeadline;
2196}
2197
2198void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2199{
2200 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 2201
d2286ba7 2202 if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 2203 apic_lvtt_period(apic))
a3e06bbe
LJ		 2204 return;
2205
2206 hrtimer_cancel(&apic->lapic_timer.timer);
2207 apic->lapic_timer.tscdeadline = data;
2208 start_apic_timer(apic);
2209}
2210
97222cc8
ED		 2211void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2212{
ad312c7c 2213 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 2214
b93463aa 2215 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
dfb95954 2216 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 2217}
2218
2219u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2220{
97222cc8
ED		 2221 u64 tpr;
2222
dfb95954 2223 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 2224
2225 return (tpr & 0xf0) >> 4;
2226}
2227
2228void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2229{
8d14695f 2230 u64 old_value = vcpu->arch.apic_base;
ad312c7c 2231 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 2232
c7dd15b3 2233 if (!apic)
97222cc8 2234 value |= MSR_IA32_APICBASE_BSP;
c5af89b6 2235
e66d2ae7
JK		 2236 vcpu->arch.apic_base = value;
2237
c7dd15b3 2238 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
aedbaf4f 2239 kvm_update_cpuid_runtime(vcpu);
c7dd15b3
JM		 2240
2241 if (!apic)
2242 return;
2243
c5cc421b 2244 /* update jump label if enable bit changes */
0dce7cd6 2245 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
49bd29ba
RK		 2246 if (value & MSR_IA32_APICBASE_ENABLE) {
2247 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
c5cc421b 2248 static_key_slow_dec_deferred(&apic_hw_disabled);
187ca84b 2249 } else {
c5cc421b 2250 static_key_slow_inc(&apic_hw_disabled.key);
44d52717 2251 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
187ca84b 2252 }
c5cc421b
GN		 2253 }
2254
8d860bbe
JM		 2255 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2256 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2257
2258 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
afaf0b2f 2259 kvm_x86_ops.set_virtual_apic_mode(vcpu);
8d14695f 2260
ad312c7c 2261 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 2262 MSR_IA32_APICBASE_BASE;
2263
db324fe6
NA		 2264 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2265 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2266 pr_warn_once("APIC base relocation is unsupported by KVM");
97222cc8
ED		 2267}
2268
b26a695a
SS		 2269void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2270{
2271 struct kvm_lapic *apic = vcpu->arch.apic;
2272
2273 if (vcpu->arch.apicv_active) {
2274 /* irr_pending is always true when apicv is activated. */
2275 apic->irr_pending = true;
2276 apic->isr_count = 1;
2277 } else {
2278 apic->irr_pending = (apic_search_irr(apic) != -1);
2279 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2280 }
2281}
2282EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
2283
d28bc9dd 2284void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8 2285{
b7e31be3 2286 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 2287 int i;
2288
b7e31be3
RK		 2289 if (!apic)
2290 return;
97222cc8 2291
97222cc8 2292 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 2293 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 2294
4d8e772b
RK		 2295 if (!init_event) {
2296 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2297 MSR_IA32_APICBASE_ENABLE);
a92e2543 2298 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
4d8e772b 2299 }
fc61b800 2300 kvm_apic_set_version(apic->vcpu);
97222cc8 2301
1e6e2755
SS		 2302 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2303 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 2304 apic_update_lvtt(apic);
52b54190
JS		 2305 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2306 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1e6e2755 2307 kvm_lapic_set_reg(apic, APIC_LVT0,
90de4a18 2308 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
dfb95954 2309 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
97222cc8 2310
ae6f2496 2311 kvm_apic_set_dfr(apic, 0xffffffffU);
f8c1ea10 2312 apic_set_spiv(apic, 0xff);
1e6e2755 2313 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 2314 if (!apic_x2apic_mode(apic))
2315 kvm_apic_set_ldr(apic, 0);
1e6e2755
SS		 2316 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2317 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2318 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2319 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2320 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
97222cc8 2321 for (i = 0; i < 8; i++) {
1e6e2755
SS		 2322 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2323 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2324 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
97222cc8 2325 }
b26a695a 2326 kvm_apic_update_apicv(vcpu);
8680b94b 2327 apic->highest_isr_cache = -1;
b33ac88b 2328 update_divide_count(apic);
d3c7b77d 2329 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 2330 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 2331 kvm_lapic_set_base(vcpu,
2332 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 2333 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8 2334 apic_update_ppr(apic);
4191db26 2335 if (vcpu->arch.apicv_active) {
afaf0b2f
SC		 2336 kvm_x86_ops.apicv_post_state_restore(vcpu);
2337 kvm_x86_ops.hwapic_irr_update(vcpu, -1);
2338 kvm_x86_ops.hwapic_isr_update(vcpu, -1);
4191db26 2339 }
97222cc8 2340
e1035715 2341 vcpu->arch.apic_arb_prio = 0;
41383771 2342 vcpu->arch.apic_attention = 0;
4abaffce
WL		 2343
2344 kvm_recalculate_apic_map(vcpu->kvm);
97222cc8
ED		 2345}
2346
97222cc8
ED		 2347/*
2348 *----------------------------------------------------------------------
2349 * timer interface
2350 *----------------------------------------------------------------------
2351 */
1b9778da 2352
2a6eac96 2353static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 2354{
d3c7b77d 2355 return apic_lvtt_period(apic);
97222cc8
ED		 2356}
2357
3d80840d
MT		 2358int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2359{
54e9818f 2360 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 2361
1e3161b4 2362 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
54e9818f 2363 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 2364
2365 return 0;
2366}
2367
89342082 2368int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 2369{
dfb95954 2370 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
23930f95 2371 int vector, mode, trig_mode;
23930f95 2372
c48f1496 2373 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 2374 vector = reg & APIC_VECTOR_MASK;
2375 mode = reg & APIC_MODE_MASK;
2376 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 2377 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2378 NULL);
23930f95
JK		 2379 }
2380 return 0;
2381}
1b9778da 2382
8fdb2351 2383void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 2384{
8fdb2351
JK		 2385 struct kvm_lapic *apic = vcpu->arch.apic;
2386
2387 if (apic)
2388 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 2389}
2390
d76685c4
GH		 2391static const struct kvm_io_device_ops apic_mmio_ops = {
2392 .read = apic_mmio_read,
2393 .write = apic_mmio_write,
d76685c4
GH		 2394};
2395
e9d90d47
AK		 2396static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2397{
2398 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 2399 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 2400
ae95f566 2401 apic_timer_expired(apic, true);
e9d90d47 2402
2a6eac96 2403 if (lapic_is_periodic(apic)) {
8003c9ae 2404 advance_periodic_target_expiration(apic);
e9d90d47
AK		 2405 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2406 return HRTIMER_RESTART;
2407 } else
2408 return HRTIMER_NORESTART;
2409}
2410
c3941d9e 2411int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
97222cc8
ED		 2412{
2413 struct kvm_lapic *apic;
2414
2415 ASSERT(vcpu != NULL);
97222cc8 2416
254272ce 2417 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
97222cc8
ED		 2418 if (!apic)
2419 goto nomem;
2420
ad312c7c 2421 vcpu->arch.apic = apic;
97222cc8 2422
254272ce 2423 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
afc20184 2424 if (!apic->regs) {
97222cc8
ED		 2425 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2426 vcpu->vcpu_id);
d589444e 2427 goto nomem_free_apic;
97222cc8 2428 }
97222cc8
ED		 2429 apic->vcpu = vcpu;
2430
d3c7b77d 2431 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2c0d278f 2432 HRTIMER_MODE_ABS_HARD);
e9d90d47 2433 apic->lapic_timer.timer.function = apic_timer_fn;
c3941d9e 2434 if (timer_advance_ns == -1) {
a0f0037e 2435 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
d0f5a86a 2436 lapic_timer_advance_dynamic = true;
c3941d9e
SC		 2437 } else {
2438 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
d0f5a86a 2439 lapic_timer_advance_dynamic = false;
c3941d9e
SC		 2440 }
2441
c5cc421b
GN		 2442 /*
2443 * APIC is created enabled. This will prevent kvm_lapic_set_base from
ee171d2f 2444 * thinking that APIC state has changed.
c5cc421b
GN		 2445 */
2446 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
f8c1ea10 2447 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d76685c4 2448 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 2449
2450 return 0;
d589444e
RR		 2451nomem_free_apic:
2452 kfree(apic);
a251fb90 2453 vcpu->arch.apic = NULL;
97222cc8 2454nomem:
97222cc8
ED		 2455 return -ENOMEM;
2456}
97222cc8
ED		 2457
2458int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2459{
ad312c7c 2460 struct kvm_lapic *apic = vcpu->arch.apic;
b3c045d3 2461 u32 ppr;
97222cc8 2462
bb34e690 2463 if (!kvm_apic_hw_enabled(apic))
97222cc8
ED		 2464 return -1;
2465
b3c045d3
PB		 2466 __apic_update_ppr(apic, &ppr);
2467 return apic_has_interrupt_for_ppr(apic, ppr);
97222cc8
ED		 2468}
2469
40487c68
QH		 2470int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2471{
dfb95954 2472 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68 2473
c48f1496 2474 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
3ce4dc17 2475 return 1;
e7dca5c0
CL		 2476 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2477 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
3ce4dc17
ML		 2478 return 1;
2479 return 0;
40487c68
QH		 2480}
2481
1b9778da
ED		 2482void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2483{
ad312c7c 2484 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 2485
54e9818f 2486 if (atomic_read(&apic->lapic_timer.pending) > 0) {
0c5f81da 2487 kvm_apic_inject_pending_timer_irqs(apic);
f1ed0450 2488 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 2489 }
2490}
2491
97222cc8
ED		 2492int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2493{
2494 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 2495 struct kvm_lapic *apic = vcpu->arch.apic;
4d82d12b 2496 u32 ppr;
97222cc8
ED		 2497
2498 if (vector == -1)
2499 return -1;
2500
56cc2406
WL		 2501 /*
2502 * We get here even with APIC virtualization enabled, if doing
2503 * nested virtualization and L1 runs with the "acknowledge interrupt
2504 * on exit" mode. Then we cannot inject the interrupt via RVI,
2505 * because the process would deliver it through the IDT.
2506 */
2507
97222cc8 2508 apic_clear_irr(vector, apic);
5c919412 2509 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
4d82d12b
PB		 2510 /*
2511 * For auto-EOI interrupts, there might be another pending
2512 * interrupt above PPR, so check whether to raise another
2513 * KVM_REQ_EVENT.
2514 */
5c919412 2515 apic_update_ppr(apic);
4d82d12b
PB		 2516 } else {
2517 /*
2518 * For normal interrupts, PPR has been raised and there cannot
2519 * be a higher-priority pending interrupt---except if there was
2520 * a concurrent interrupt injection, but that would have
2521 * triggered KVM_REQ_EVENT already.
2522 */
2523 apic_set_isr(vector, apic);
2524 __apic_update_ppr(apic, &ppr);
5c919412
AS		 2525 }
2526
97222cc8
ED		 2527 return vector;
2528}
96ad2cc6 2529
a92e2543
RK		 2530static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2531 struct kvm_lapic_state *s, bool set)
2532{
2533 if (apic_x2apic_mode(vcpu->arch.apic)) {
2534 u32 *id = (u32 *)(s->regs + APIC_ID);
12806ba9 2535 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
a92e2543 2536
37131313
RK		 2537 if (vcpu->kvm->arch.x2apic_format) {
2538 if (*id != vcpu->vcpu_id)
2539 return -EINVAL;
2540 } else {
2541 if (set)
2542 *id >>= 24;
2543 else
2544 *id <<= 24;
2545 }
12806ba9
DDAG		 2546
2547 /* In x2APIC mode, the LDR is fixed and based on the id */
2548 if (set)
2549 *ldr = kvm_apic_calc_x2apic_ldr(*id);
a92e2543
RK		 2550 }
2551
2552 return 0;
2553}
2554
2555int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2556{
2557 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
24647e0a
PS		 2558
2559 /*
2560 * Get calculated timer current count for remaining timer period (if
2561 * any) and store it in the returned register set.
2562 */
2563 __kvm_lapic_set_reg(s->regs, APIC_TMCCT,
2564 __apic_read(vcpu->arch.apic, APIC_TMCCT));
2565
a92e2543
RK		 2566 return kvm_apic_state_fixup(vcpu, s, false);
2567}
2568
2569int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
96ad2cc6 2570{
ad312c7c 2571 struct kvm_lapic *apic = vcpu->arch.apic;
a92e2543
RK		 2572 int r;
2573
5dbc8f3f 2574 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 2575 /* set SPIV separately to get count of SW disabled APICs right */
2576 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
a92e2543
RK		 2577
2578 r = kvm_apic_state_fixup(vcpu, s, true);
4abaffce
WL		 2579 if (r) {
2580 kvm_recalculate_apic_map(vcpu->kvm);
a92e2543 2581 return r;
4abaffce 2582 }
0e96f31e 2583 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
a92e2543 2584
44d52717 2585 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
4abaffce 2586 kvm_recalculate_apic_map(vcpu->kvm);
fc61b800
GN		 2587 kvm_apic_set_version(vcpu);
2588
96ad2cc6 2589 apic_update_ppr(apic);
d3c7b77d 2590 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 2591 apic_update_lvtt(apic);
dfb95954 2592 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
96ad2cc6 2593 update_divide_count(apic);
24647e0a 2594 __start_apic_timer(apic, APIC_TMCCT);
b26a695a 2595 kvm_apic_update_apicv(vcpu);
8680b94b 2596 apic->highest_isr_cache = -1;
d62caabb 2597 if (vcpu->arch.apicv_active) {
afaf0b2f
SC		 2598 kvm_x86_ops.apicv_post_state_restore(vcpu);
2599 kvm_x86_ops.hwapic_irr_update(vcpu,
4114c27d 2600 apic_find_highest_irr(apic));
afaf0b2f 2601 kvm_x86_ops.hwapic_isr_update(vcpu,
b4eef9b3 2602 apic_find_highest_isr(apic));
d62caabb 2603 }
3842d135 2604 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 2605 if (ioapic_in_kernel(vcpu->kvm))
2606 kvm_rtc_eoi_tracking_restore_one(vcpu);
0669a510
RK		 2607
2608 vcpu->arch.apic_arb_prio = 0;
a92e2543
RK		 2609
2610 return 0;
96ad2cc6 2611}
a3d7f85f 2612
2f52d58c 2613void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 2614{
a3d7f85f
ED		 2615 struct hrtimer *timer;
2616
0c5f81da
WL		 2617 if (!lapic_in_kernel(vcpu) ||
2618 kvm_can_post_timer_interrupt(vcpu))
a3d7f85f
ED		 2619 return;
2620
54e9818f 2621 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 2622 if (hrtimer_cancel(timer))
2c0d278f 2623 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
a3d7f85f 2624}
b93463aa 2625
ae7a2a3f
MT		 2626/*
2627 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2628 *
2629 * Detect whether guest triggered PV EOI since the
2630 * last entry. If yes, set EOI on guests's behalf.
2631 * Clear PV EOI in guest memory in any case.
2632 */
2633static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2634 struct kvm_lapic *apic)
2635{
2636 bool pending;
2637 int vector;
2638 /*
2639 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2640 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2641 *
2642 * KVM_APIC_PV_EOI_PENDING is unset:
2643 * -> host disabled PV EOI.
2644 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2645 * -> host enabled PV EOI, guest did not execute EOI yet.
2646 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2647 * -> host enabled PV EOI, guest executed EOI.
2648 */
2649 BUG_ON(!pv_eoi_enabled(vcpu));
2650 pending = pv_eoi_get_pending(vcpu);
2651 /*
2652 * Clear pending bit in any case: it will be set again on vmentry.
2653 * While this might not be ideal from performance point of view,
2654 * this makes sure pv eoi is only enabled when we know it's safe.
2655 */
2656 pv_eoi_clr_pending(vcpu);
2657 if (pending)
2658 return;
2659 vector = apic_set_eoi(apic);
2660 trace_kvm_pv_eoi(apic, vector);
2661}
2662
b93463aa
AK		 2663void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2664{
2665 u32 data;
b93463aa 2666
ae7a2a3f
MT		 2667 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2668 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2669
41383771 2670 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2671 return;
2672
4e335d9e
PB		 2673 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2674 sizeof(u32)))
603242a8 2675 return;
b93463aa
AK		 2676
2677 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2678}
2679
ae7a2a3f
MT		 2680/*
2681 * apic_sync_pv_eoi_to_guest - called before vmentry
2682 *
2683 * Detect whether it's safe to enable PV EOI and
2684 * if yes do so.
2685 */
2686static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2687 struct kvm_lapic *apic)
2688{
2689 if (!pv_eoi_enabled(vcpu) ||
2690 /* IRR set or many bits in ISR: could be nested. */
2691 apic->irr_pending ||
2692 /* Cache not set: could be safe but we don't bother. */
2693 apic->highest_isr_cache == -1 ||
2694 /* Need EOI to update ioapic. */
3bb345f3 2695 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 2696 /*
2697 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2698 * so we need not do anything here.
2699 */
2700 return;
2701 }
2702
2703 pv_eoi_set_pending(apic->vcpu);
2704}
2705
b93463aa
AK		 2706void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2707{
2708 u32 data, tpr;
2709 int max_irr, max_isr;
ae7a2a3f 2710 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 2711
ae7a2a3f
MT		 2712 apic_sync_pv_eoi_to_guest(vcpu, apic);
2713
41383771 2714 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2715 return;
2716
dfb95954 2717 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 2718 max_irr = apic_find_highest_irr(apic);
2719 if (max_irr < 0)
2720 max_irr = 0;
2721 max_isr = apic_find_highest_isr(apic);
2722 if (max_isr < 0)
2723 max_isr = 0;
2724 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2725
4e335d9e
PB		 2726 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2727 sizeof(u32));
b93463aa
AK		 2728}
2729
fda4e2e8 2730int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 2731{
fda4e2e8 2732 if (vapic_addr) {
4e335d9e 2733 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
fda4e2e8
AH		 2734 &vcpu->arch.apic->vapic_cache,
2735 vapic_addr, sizeof(u32)))
2736 return -EINVAL;
41383771 2737 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 2738 } else {
41383771 2739 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 2740 }
2741
2742 vcpu->arch.apic->vapic_addr = vapic_addr;
2743 return 0;
b93463aa 2744}
0105d1a5
GN		 2745
2746int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2747{
2748 struct kvm_lapic *apic = vcpu->arch.apic;
2749 u32 reg = (msr - APIC_BASE_MSR) << 4;
2750
35754c98 2751 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2752 return 1;
2753
c69d3d9b
NA		 2754 if (reg == APIC_ICR2)
2755 return 1;
2756
0105d1a5 2757 /* if this is ICR write vector before command */
decdc283 2758 if (reg == APIC_ICR)
1e6e2755
SS		 2759 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2760 return kvm_lapic_reg_write(apic, reg, (u32)data);
0105d1a5
GN		 2761}
2762
2763int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2764{
2765 struct kvm_lapic *apic = vcpu->arch.apic;
2766 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2767
35754c98 2768 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2769 return 1;
2770
0d88800d 2771 if (reg == APIC_DFR || reg == APIC_ICR2)
c69d3d9b 2772 return 1;
c69d3d9b 2773
1e6e2755 2774 if (kvm_lapic_reg_read(apic, reg, 4, &low))
0105d1a5 2775 return 1;
decdc283 2776 if (reg == APIC_ICR)
1e6e2755 2777 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
0105d1a5
GN		 2778
2779 *data = (((u64)high) << 32) | low;
2780
2781 return 0;
2782}
10388a07
GN		 2783
2784int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2785{
2786 struct kvm_lapic *apic = vcpu->arch.apic;
2787
bce87cce 2788 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2789 return 1;
2790
2791 /* if this is ICR write vector before command */
2792 if (reg == APIC_ICR)
1e6e2755
SS		 2793 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2794 return kvm_lapic_reg_write(apic, reg, (u32)data);
10388a07
GN		 2795}
2796
2797int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2798{
2799 struct kvm_lapic *apic = vcpu->arch.apic;
2800 u32 low, high = 0;
2801
bce87cce 2802 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2803 return 1;
2804
1e6e2755 2805 if (kvm_lapic_reg_read(apic, reg, 4, &low))
10388a07
GN		 2806 return 1;
2807 if (reg == APIC_ICR)
1e6e2755 2808 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
10388a07
GN		 2809
2810 *data = (((u64)high) << 32) | low;
2811
2812 return 0;
2813}
ae7a2a3f 2814
72bbf935 2815int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
ae7a2a3f
MT		 2816{
2817 u64 addr = data & ~KVM_MSR_ENABLED;
a7c42bb6
VK		 2818 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2819 unsigned long new_len;
2820
ae7a2a3f
MT		 2821 if (!IS_ALIGNED(addr, 4))
2822 return 1;
2823
2824 vcpu->arch.pv_eoi.msr_val = data;
2825 if (!pv_eoi_enabled(vcpu))
2826 return 0;
a7c42bb6
VK		 2827
2828 if (addr == ghc->gpa && len <= ghc->len)
2829 new_len = ghc->len;
2830 else
2831 new_len = len;
2832
2833 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
ae7a2a3f 2834}
c5cc421b 2835
66450a21
JK		 2836void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2837{
2838 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2839 u8 sipi_vector;
299018f4 2840 unsigned long pe;
66450a21 2841
bce87cce 2842 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
66450a21
JK		 2843 return;
2844
cd7764fe 2845 /*
4b9852f4
LA		 2846 * INITs are latched while CPU is in specific states
2847 * (SMM, VMX non-root mode, SVM with GIF=0).
2848 * Because a CPU cannot be in these states immediately
2849 * after it has processed an INIT signal (and thus in
2850 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2851 * and leave the INIT pending.
cd7764fe 2852 */
27cbe7d6 2853 if (kvm_vcpu_latch_init(vcpu)) {
cd7764fe
PB		 2854 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2855 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2856 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2857 return;
2858 }
299018f4 2859
cd7764fe 2860 pe = xchg(&apic->pending_events, 0);
299018f4 2861 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd 2862 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2863 if (kvm_vcpu_is_bsp(apic->vcpu))
2864 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2865 else
2866 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2867 }
299018f4 2868 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2869 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2870 /* evaluate pending_events before reading the vector */
2871 smp_rmb();
2872 sipi_vector = apic->sipi_vector;
66450a21
JK		 2873 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2874 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2875 }
2876}
2877
c5cc421b
GN		 2878void kvm_lapic_init(void)
2879{
2880 /* do not patch jump label more than once per second */
2881 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2882 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2883}
cef84c30
DM		 2884
2885void kvm_lapic_exit(void)
2886{
2887 static_key_deferred_flush(&apic_hw_disabled);
2888 static_key_deferred_flush(&apic_sw_disabled);
2889}
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