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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
8 | * | |
9 | * Authors: | |
10 | * Dor Laor <dor.laor@qumranet.com> | |
11 | * Gregory Haskins <ghaskins@novell.com> | |
12 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
13 | * | |
14 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | */ | |
19 | ||
edf88417 | 20 | #include <linux/kvm_host.h> |
97222cc8 ED |
21 | #include <linux/kvm.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/highmem.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/hrtimer.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/module.h> | |
6f6d6a1a | 28 | #include <linux/math64.h> |
97222cc8 ED |
29 | #include <asm/processor.h> |
30 | #include <asm/msr.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/current.h> | |
33 | #include <asm/apicdef.h> | |
34 | #include <asm/atomic.h> | |
5fdbf976 | 35 | #include "kvm_cache_regs.h" |
97222cc8 ED |
36 | #include "irq.h" |
37 | ||
b682b814 MT |
38 | #ifndef CONFIG_X86_64 |
39 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
40 | #else | |
41 | #define mod_64(x, y) ((x) % (y)) | |
42 | #endif | |
43 | ||
97222cc8 ED |
44 | #define PRId64 "d" |
45 | #define PRIx64 "llx" | |
46 | #define PRIu64 "u" | |
47 | #define PRIo64 "o" | |
48 | ||
49 | #define APIC_BUS_CYCLE_NS 1 | |
50 | ||
51 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
52 | #define apic_debug(fmt, arg...) | |
53 | ||
54 | #define APIC_LVT_NUM 6 | |
55 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
56 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
57 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
58 | /* followed define is not in apicdef.h */ | |
59 | #define APIC_SHORT_MASK 0xc0000 | |
60 | #define APIC_DEST_NOSHORT 0x0 | |
61 | #define APIC_DEST_MASK 0x800 | |
62 | #define MAX_APIC_VECTOR 256 | |
63 | ||
64 | #define VEC_POS(v) ((v) & (32 - 1)) | |
65 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 66 | |
97222cc8 ED |
67 | static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) |
68 | { | |
69 | return *((u32 *) (apic->regs + reg_off)); | |
70 | } | |
71 | ||
72 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) | |
73 | { | |
74 | *((u32 *) (apic->regs + reg_off)) = val; | |
75 | } | |
76 | ||
77 | static inline int apic_test_and_set_vector(int vec, void *bitmap) | |
78 | { | |
79 | return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
80 | } | |
81 | ||
82 | static inline int apic_test_and_clear_vector(int vec, void *bitmap) | |
83 | { | |
84 | return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
85 | } | |
86 | ||
87 | static inline void apic_set_vector(int vec, void *bitmap) | |
88 | { | |
89 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
90 | } | |
91 | ||
92 | static inline void apic_clear_vector(int vec, void *bitmap) | |
93 | { | |
94 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
95 | } | |
96 | ||
97 | static inline int apic_hw_enabled(struct kvm_lapic *apic) | |
98 | { | |
ad312c7c | 99 | return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; |
97222cc8 ED |
100 | } |
101 | ||
102 | static inline int apic_sw_enabled(struct kvm_lapic *apic) | |
103 | { | |
104 | return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; | |
105 | } | |
106 | ||
107 | static inline int apic_enabled(struct kvm_lapic *apic) | |
108 | { | |
109 | return apic_sw_enabled(apic) && apic_hw_enabled(apic); | |
110 | } | |
111 | ||
112 | #define LVT_MASK \ | |
113 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
114 | ||
115 | #define LINT_MASK \ | |
116 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
117 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
118 | ||
119 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
120 | { | |
121 | return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; | |
122 | } | |
123 | ||
124 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) | |
125 | { | |
126 | return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); | |
127 | } | |
128 | ||
129 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
130 | { | |
131 | return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; | |
132 | } | |
133 | ||
134 | static inline int apic_lvtt_period(struct kvm_lapic *apic) | |
135 | { | |
136 | return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC; | |
137 | } | |
138 | ||
cc6e462c JK |
139 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
140 | { | |
141 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
142 | } | |
143 | ||
97222cc8 ED |
144 | static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
145 | LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */ | |
146 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ | |
147 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
148 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
149 | LVT_MASK /* LVTERR */ | |
150 | }; | |
151 | ||
152 | static int find_highest_vector(void *bitmap) | |
153 | { | |
154 | u32 *word = bitmap; | |
155 | int word_offset = MAX_APIC_VECTOR >> 5; | |
156 | ||
157 | while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) | |
158 | continue; | |
159 | ||
160 | if (likely(!word_offset && !word[0])) | |
161 | return -1; | |
162 | else | |
163 | return fls(word[word_offset << 2]) - 1 + (word_offset << 5); | |
164 | } | |
165 | ||
166 | static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) | |
167 | { | |
168 | return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); | |
169 | } | |
170 | ||
171 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) | |
172 | { | |
173 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
174 | } | |
175 | ||
176 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
177 | { | |
178 | int result; | |
179 | ||
180 | result = find_highest_vector(apic->regs + APIC_IRR); | |
181 | ASSERT(result == -1 || result >= 16); | |
182 | ||
183 | return result; | |
184 | } | |
185 | ||
6e5d865c YS |
186 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
187 | { | |
ad312c7c | 188 | struct kvm_lapic *apic = vcpu->arch.apic; |
6e5d865c YS |
189 | int highest_irr; |
190 | ||
191 | if (!apic) | |
192 | return 0; | |
193 | highest_irr = apic_find_highest_irr(apic); | |
194 | ||
195 | return highest_irr; | |
196 | } | |
197 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); | |
198 | ||
8be5453f | 199 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig) |
97222cc8 | 200 | { |
ad312c7c | 201 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 202 | |
97222cc8 ED |
203 | if (!apic_test_and_set_irr(vec, apic)) { |
204 | /* a new pending irq is set in IRR */ | |
205 | if (trig) | |
206 | apic_set_vector(vec, apic->regs + APIC_TMR); | |
207 | else | |
208 | apic_clear_vector(vec, apic->regs + APIC_TMR); | |
209 | kvm_vcpu_kick(apic->vcpu); | |
210 | return 1; | |
211 | } | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) | |
216 | { | |
217 | int result; | |
218 | ||
219 | result = find_highest_vector(apic->regs + APIC_ISR); | |
220 | ASSERT(result == -1 || result >= 16); | |
221 | ||
222 | return result; | |
223 | } | |
224 | ||
225 | static void apic_update_ppr(struct kvm_lapic *apic) | |
226 | { | |
227 | u32 tpr, isrv, ppr; | |
228 | int isr; | |
229 | ||
230 | tpr = apic_get_reg(apic, APIC_TASKPRI); | |
231 | isr = apic_find_highest_isr(apic); | |
232 | isrv = (isr != -1) ? isr : 0; | |
233 | ||
234 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
235 | ppr = tpr & 0xff; | |
236 | else | |
237 | ppr = isrv & 0xf0; | |
238 | ||
239 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
240 | apic, ppr, isr, isrv); | |
241 | ||
242 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
243 | } | |
244 | ||
245 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
246 | { | |
247 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
248 | apic_update_ppr(apic); | |
249 | } | |
250 | ||
251 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) | |
252 | { | |
253 | return kvm_apic_id(apic) == dest; | |
254 | } | |
255 | ||
256 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) | |
257 | { | |
258 | int result = 0; | |
259 | u8 logical_id; | |
260 | ||
261 | logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); | |
262 | ||
263 | switch (apic_get_reg(apic, APIC_DFR)) { | |
264 | case APIC_DFR_FLAT: | |
265 | if (logical_id & mda) | |
266 | result = 1; | |
267 | break; | |
268 | case APIC_DFR_CLUSTER: | |
269 | if (((logical_id >> 4) == (mda >> 0x4)) | |
270 | && (logical_id & mda & 0xf)) | |
271 | result = 1; | |
272 | break; | |
273 | default: | |
274 | printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n", | |
275 | apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); | |
276 | break; | |
277 | } | |
278 | ||
279 | return result; | |
280 | } | |
281 | ||
282 | static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, | |
283 | int short_hand, int dest, int dest_mode) | |
284 | { | |
285 | int result = 0; | |
ad312c7c | 286 | struct kvm_lapic *target = vcpu->arch.apic; |
97222cc8 ED |
287 | |
288 | apic_debug("target %p, source %p, dest 0x%x, " | |
289 | "dest_mode 0x%x, short_hand 0x%x", | |
290 | target, source, dest, dest_mode, short_hand); | |
291 | ||
292 | ASSERT(!target); | |
293 | switch (short_hand) { | |
294 | case APIC_DEST_NOSHORT: | |
295 | if (dest_mode == 0) { | |
296 | /* Physical mode. */ | |
297 | if ((dest == 0xFF) || (dest == kvm_apic_id(target))) | |
298 | result = 1; | |
299 | } else | |
300 | /* Logical mode. */ | |
301 | result = kvm_apic_match_logical_addr(target, dest); | |
302 | break; | |
303 | case APIC_DEST_SELF: | |
304 | if (target == source) | |
305 | result = 1; | |
306 | break; | |
307 | case APIC_DEST_ALLINC: | |
308 | result = 1; | |
309 | break; | |
310 | case APIC_DEST_ALLBUT: | |
311 | if (target != source) | |
312 | result = 1; | |
313 | break; | |
314 | default: | |
315 | printk(KERN_WARNING "Bad dest shorthand value %x\n", | |
316 | short_hand); | |
317 | break; | |
318 | } | |
319 | ||
320 | return result; | |
321 | } | |
322 | ||
323 | /* | |
324 | * Add a pending IRQ into lapic. | |
325 | * Return 1 if successfully added and 0 if discarded. | |
326 | */ | |
327 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
328 | int vector, int level, int trig_mode) | |
329 | { | |
c5ec1534 HQ |
330 | int orig_irr, result = 0; |
331 | struct kvm_vcpu *vcpu = apic->vcpu; | |
97222cc8 ED |
332 | |
333 | switch (delivery_mode) { | |
334 | case APIC_DM_FIXED: | |
335 | case APIC_DM_LOWEST: | |
336 | /* FIXME add logic for vcpu on reset */ | |
337 | if (unlikely(!apic_enabled(apic))) | |
338 | break; | |
339 | ||
1b9778da ED |
340 | orig_irr = apic_test_and_set_irr(vector, apic); |
341 | if (orig_irr && trig_mode) { | |
97222cc8 ED |
342 | apic_debug("level trig mode repeatedly for vector %d", |
343 | vector); | |
344 | break; | |
345 | } | |
346 | ||
347 | if (trig_mode) { | |
348 | apic_debug("level trig mode for vector %d", vector); | |
349 | apic_set_vector(vector, apic->regs + APIC_TMR); | |
350 | } else | |
351 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
352 | ||
d7690175 | 353 | kvm_vcpu_kick(vcpu); |
97222cc8 | 354 | |
1b9778da | 355 | result = (orig_irr == 0); |
97222cc8 ED |
356 | break; |
357 | ||
358 | case APIC_DM_REMRD: | |
359 | printk(KERN_DEBUG "Ignoring delivery mode 3\n"); | |
360 | break; | |
361 | ||
362 | case APIC_DM_SMI: | |
363 | printk(KERN_DEBUG "Ignoring guest SMI\n"); | |
364 | break; | |
3419ffc8 | 365 | |
97222cc8 | 366 | case APIC_DM_NMI: |
3419ffc8 | 367 | kvm_inject_nmi(vcpu); |
26df99c6 | 368 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
369 | break; |
370 | ||
371 | case APIC_DM_INIT: | |
c5ec1534 | 372 | if (level) { |
a4535290 | 373 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
c5ec1534 HQ |
374 | printk(KERN_DEBUG |
375 | "INIT on a runnable vcpu %d\n", | |
376 | vcpu->vcpu_id); | |
a4535290 | 377 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; |
c5ec1534 HQ |
378 | kvm_vcpu_kick(vcpu); |
379 | } else { | |
1b10bf31 JK |
380 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
381 | vcpu->vcpu_id); | |
c5ec1534 | 382 | } |
97222cc8 ED |
383 | break; |
384 | ||
385 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
386 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
387 | vcpu->vcpu_id, vector); | |
a4535290 | 388 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
ad312c7c | 389 | vcpu->arch.sipi_vector = vector; |
a4535290 | 390 | vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; |
d7690175 | 391 | kvm_vcpu_kick(vcpu); |
c5ec1534 | 392 | } |
97222cc8 ED |
393 | break; |
394 | ||
23930f95 JK |
395 | case APIC_DM_EXTINT: |
396 | /* | |
397 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
398 | * before NMI watchdog was enabled. Already handled by | |
399 | * kvm_apic_accept_pic_intr(). | |
400 | */ | |
401 | break; | |
402 | ||
97222cc8 ED |
403 | default: |
404 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
405 | delivery_mode); | |
406 | break; | |
407 | } | |
408 | return result; | |
409 | } | |
410 | ||
8be5453f | 411 | static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector, |
97222cc8 ED |
412 | unsigned long bitmap) |
413 | { | |
932f72ad HQ |
414 | int last; |
415 | int next; | |
e4d47f40 | 416 | struct kvm_lapic *apic = NULL; |
932f72ad | 417 | |
bfc6d222 | 418 | last = kvm->arch.round_robin_prev_vcpu; |
932f72ad HQ |
419 | next = last; |
420 | ||
421 | do { | |
422 | if (++next == KVM_MAX_VCPUS) | |
423 | next = 0; | |
424 | if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap)) | |
425 | continue; | |
ad312c7c | 426 | apic = kvm->vcpus[next]->arch.apic; |
932f72ad HQ |
427 | if (apic && apic_enabled(apic)) |
428 | break; | |
429 | apic = NULL; | |
430 | } while (next != last); | |
bfc6d222 | 431 | kvm->arch.round_robin_prev_vcpu = next; |
932f72ad | 432 | |
e4d47f40 QH |
433 | if (!apic) |
434 | printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n"); | |
97222cc8 | 435 | |
932f72ad | 436 | return apic; |
97222cc8 ED |
437 | } |
438 | ||
8be5453f ZX |
439 | struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector, |
440 | unsigned long bitmap) | |
441 | { | |
442 | struct kvm_lapic *apic; | |
443 | ||
444 | apic = kvm_apic_round_robin(kvm, vector, bitmap); | |
445 | if (apic) | |
446 | return apic->vcpu; | |
447 | return NULL; | |
448 | } | |
449 | ||
97222cc8 ED |
450 | static void apic_set_eoi(struct kvm_lapic *apic) |
451 | { | |
452 | int vector = apic_find_highest_isr(apic); | |
f5244726 | 453 | int trigger_mode; |
97222cc8 ED |
454 | /* |
455 | * Not every write EOI will has corresponding ISR, | |
456 | * one example is when Kernel check timer on setup_IO_APIC | |
457 | */ | |
458 | if (vector == -1) | |
459 | return; | |
460 | ||
461 | apic_clear_vector(vector, apic->regs + APIC_ISR); | |
462 | apic_update_ppr(apic); | |
463 | ||
464 | if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR)) | |
f5244726 MT |
465 | trigger_mode = IOAPIC_LEVEL_TRIG; |
466 | else | |
467 | trigger_mode = IOAPIC_EDGE_TRIG; | |
468 | kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); | |
97222cc8 ED |
469 | } |
470 | ||
471 | static void apic_send_ipi(struct kvm_lapic *apic) | |
472 | { | |
473 | u32 icr_low = apic_get_reg(apic, APIC_ICR); | |
474 | u32 icr_high = apic_get_reg(apic, APIC_ICR2); | |
475 | ||
476 | unsigned int dest = GET_APIC_DEST_FIELD(icr_high); | |
477 | unsigned int short_hand = icr_low & APIC_SHORT_MASK; | |
478 | unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG; | |
479 | unsigned int level = icr_low & APIC_INT_ASSERT; | |
480 | unsigned int dest_mode = icr_low & APIC_DEST_MASK; | |
481 | unsigned int delivery_mode = icr_low & APIC_MODE_MASK; | |
482 | unsigned int vector = icr_low & APIC_VECTOR_MASK; | |
483 | ||
8be5453f | 484 | struct kvm_vcpu *target; |
97222cc8 ED |
485 | struct kvm_vcpu *vcpu; |
486 | unsigned long lpr_map = 0; | |
487 | int i; | |
488 | ||
489 | apic_debug("icr_high 0x%x, icr_low 0x%x, " | |
490 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
491 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", | |
492 | icr_high, icr_low, short_hand, dest, | |
493 | trig_mode, level, dest_mode, delivery_mode, vector); | |
494 | ||
495 | for (i = 0; i < KVM_MAX_VCPUS; i++) { | |
496 | vcpu = apic->vcpu->kvm->vcpus[i]; | |
497 | if (!vcpu) | |
498 | continue; | |
499 | ||
ad312c7c | 500 | if (vcpu->arch.apic && |
97222cc8 ED |
501 | apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) { |
502 | if (delivery_mode == APIC_DM_LOWEST) | |
503 | set_bit(vcpu->vcpu_id, &lpr_map); | |
504 | else | |
ad312c7c | 505 | __apic_accept_irq(vcpu->arch.apic, delivery_mode, |
97222cc8 ED |
506 | vector, level, trig_mode); |
507 | } | |
508 | } | |
509 | ||
510 | if (delivery_mode == APIC_DM_LOWEST) { | |
8be5453f | 511 | target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map); |
97222cc8 | 512 | if (target != NULL) |
ad312c7c | 513 | __apic_accept_irq(target->arch.apic, delivery_mode, |
97222cc8 ED |
514 | vector, level, trig_mode); |
515 | } | |
516 | } | |
517 | ||
518 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
519 | { | |
b682b814 MT |
520 | ktime_t remaining; |
521 | s64 ns; | |
9da8f4e8 | 522 | u32 tmcct; |
97222cc8 ED |
523 | |
524 | ASSERT(apic != NULL); | |
525 | ||
9da8f4e8 | 526 | /* if initial count is 0, current count should also be 0 */ |
b682b814 | 527 | if (apic_get_reg(apic, APIC_TMICT) == 0) |
9da8f4e8 KP |
528 | return 0; |
529 | ||
b682b814 MT |
530 | remaining = hrtimer_expires_remaining(&apic->timer.dev); |
531 | if (ktime_to_ns(remaining) < 0) | |
532 | remaining = ktime_set(0, 0); | |
533 | ||
534 | ns = mod_64(ktime_to_ns(remaining), apic->timer.period); | |
535 | tmcct = div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->timer.divide_count)); | |
97222cc8 ED |
536 | |
537 | return tmcct; | |
538 | } | |
539 | ||
b209749f AK |
540 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
541 | { | |
542 | struct kvm_vcpu *vcpu = apic->vcpu; | |
543 | struct kvm_run *run = vcpu->run; | |
544 | ||
545 | set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests); | |
5fdbf976 | 546 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
547 | run->tpr_access.is_write = write; |
548 | } | |
549 | ||
550 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
551 | { | |
552 | if (apic->vcpu->arch.tpr_access_reporting) | |
553 | __report_tpr_access(apic, write); | |
554 | } | |
555 | ||
97222cc8 ED |
556 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
557 | { | |
558 | u32 val = 0; | |
559 | ||
c7bf23ba JR |
560 | KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); |
561 | ||
97222cc8 ED |
562 | if (offset >= LAPIC_MMIO_LENGTH) |
563 | return 0; | |
564 | ||
565 | switch (offset) { | |
566 | case APIC_ARBPRI: | |
567 | printk(KERN_WARNING "Access APIC ARBPRI register " | |
568 | "which is for P6\n"); | |
569 | break; | |
570 | ||
571 | case APIC_TMCCT: /* Timer CCR */ | |
572 | val = apic_get_tmcct(apic); | |
573 | break; | |
574 | ||
b209749f AK |
575 | case APIC_TASKPRI: |
576 | report_tpr_access(apic, false); | |
577 | /* fall thru */ | |
97222cc8 | 578 | default: |
6e5d865c | 579 | apic_update_ppr(apic); |
97222cc8 ED |
580 | val = apic_get_reg(apic, offset); |
581 | break; | |
582 | } | |
583 | ||
584 | return val; | |
585 | } | |
586 | ||
587 | static void apic_mmio_read(struct kvm_io_device *this, | |
588 | gpa_t address, int len, void *data) | |
589 | { | |
590 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
591 | unsigned int offset = address - apic->base_address; | |
592 | unsigned char alignment = offset & 0xf; | |
593 | u32 result; | |
594 | ||
595 | if ((alignment + len) > 4) { | |
596 | printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d", | |
597 | (unsigned long)address, len); | |
598 | return; | |
599 | } | |
600 | result = __apic_read(apic, offset & ~0xf); | |
601 | ||
602 | switch (len) { | |
603 | case 1: | |
604 | case 2: | |
605 | case 4: | |
606 | memcpy(data, (char *)&result + alignment, len); | |
607 | break; | |
608 | default: | |
609 | printk(KERN_ERR "Local APIC read with len = %x, " | |
610 | "should be 1,2, or 4 instead\n", len); | |
611 | break; | |
612 | } | |
613 | } | |
614 | ||
615 | static void update_divide_count(struct kvm_lapic *apic) | |
616 | { | |
617 | u32 tmp1, tmp2, tdcr; | |
618 | ||
619 | tdcr = apic_get_reg(apic, APIC_TDCR); | |
620 | tmp1 = tdcr & 0xf; | |
621 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
622 | apic->timer.divide_count = 0x1 << (tmp2 & 0x7); | |
623 | ||
624 | apic_debug("timer divide count is 0x%x\n", | |
625 | apic->timer.divide_count); | |
626 | } | |
627 | ||
628 | static void start_apic_timer(struct kvm_lapic *apic) | |
629 | { | |
630 | ktime_t now = apic->timer.dev.base->get_time(); | |
631 | ||
97222cc8 ED |
632 | apic->timer.period = apic_get_reg(apic, APIC_TMICT) * |
633 | APIC_BUS_CYCLE_NS * apic->timer.divide_count; | |
634 | atomic_set(&apic->timer.pending, 0); | |
0b975a3c AK |
635 | |
636 | if (!apic->timer.period) | |
637 | return; | |
638 | ||
97222cc8 ED |
639 | hrtimer_start(&apic->timer.dev, |
640 | ktime_add_ns(now, apic->timer.period), | |
641 | HRTIMER_MODE_ABS); | |
642 | ||
643 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" | |
644 | PRIx64 ", " | |
645 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 646 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 ED |
647 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
648 | apic_get_reg(apic, APIC_TMICT), | |
649 | apic->timer.period, | |
650 | ktime_to_ns(ktime_add_ns(now, | |
651 | apic->timer.period))); | |
652 | } | |
653 | ||
cc6e462c JK |
654 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
655 | { | |
656 | int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0)); | |
657 | ||
658 | if (apic_lvt_nmi_mode(lvt0_val)) { | |
659 | if (!nmi_wd_enabled) { | |
660 | apic_debug("Receive NMI setting on APIC_LVT0 " | |
661 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
662 | apic->vcpu->kvm->arch.vapics_in_nmi_mode++; | |
663 | } | |
664 | } else if (nmi_wd_enabled) | |
665 | apic->vcpu->kvm->arch.vapics_in_nmi_mode--; | |
666 | } | |
667 | ||
97222cc8 ED |
668 | static void apic_mmio_write(struct kvm_io_device *this, |
669 | gpa_t address, int len, const void *data) | |
670 | { | |
671 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
672 | unsigned int offset = address - apic->base_address; | |
673 | unsigned char alignment = offset & 0xf; | |
674 | u32 val; | |
675 | ||
676 | /* | |
677 | * APIC register must be aligned on 128-bits boundary. | |
678 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
679 | * Refer SDM 8.4.1 | |
680 | */ | |
681 | if (len != 4 || alignment) { | |
1b10bf31 JK |
682 | /* Don't shout loud, $infamous_os would cause only noise. */ |
683 | apic_debug("apic write: bad size=%d %lx\n", | |
684 | len, (long)address); | |
97222cc8 ED |
685 | return; |
686 | } | |
687 | ||
688 | val = *(u32 *) data; | |
689 | ||
690 | /* too common printing */ | |
691 | if (offset != APIC_EOI) | |
692 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
b8688d51 | 693 | "0x%x\n", __func__, offset, len, val); |
97222cc8 ED |
694 | |
695 | offset &= 0xff0; | |
696 | ||
c7bf23ba JR |
697 | KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); |
698 | ||
97222cc8 ED |
699 | switch (offset) { |
700 | case APIC_ID: /* Local APIC ID */ | |
701 | apic_set_reg(apic, APIC_ID, val); | |
702 | break; | |
703 | ||
704 | case APIC_TASKPRI: | |
b209749f | 705 | report_tpr_access(apic, true); |
97222cc8 ED |
706 | apic_set_tpr(apic, val & 0xff); |
707 | break; | |
708 | ||
709 | case APIC_EOI: | |
710 | apic_set_eoi(apic); | |
711 | break; | |
712 | ||
713 | case APIC_LDR: | |
714 | apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); | |
715 | break; | |
716 | ||
717 | case APIC_DFR: | |
718 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); | |
719 | break; | |
720 | ||
721 | case APIC_SPIV: | |
722 | apic_set_reg(apic, APIC_SPIV, val & 0x3ff); | |
723 | if (!(val & APIC_SPIV_APIC_ENABLED)) { | |
724 | int i; | |
725 | u32 lvt_val; | |
726 | ||
727 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
728 | lvt_val = apic_get_reg(apic, | |
729 | APIC_LVTT + 0x10 * i); | |
730 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
731 | lvt_val | APIC_LVT_MASKED); | |
732 | } | |
733 | atomic_set(&apic->timer.pending, 0); | |
734 | ||
735 | } | |
736 | break; | |
737 | ||
738 | case APIC_ICR: | |
739 | /* No delay here, so we always clear the pending bit */ | |
740 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
741 | apic_send_ipi(apic); | |
742 | break; | |
743 | ||
744 | case APIC_ICR2: | |
745 | apic_set_reg(apic, APIC_ICR2, val & 0xff000000); | |
746 | break; | |
747 | ||
23930f95 | 748 | case APIC_LVT0: |
cc6e462c | 749 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
750 | case APIC_LVTT: |
751 | case APIC_LVTTHMR: | |
752 | case APIC_LVTPC: | |
97222cc8 ED |
753 | case APIC_LVT1: |
754 | case APIC_LVTERR: | |
755 | /* TODO: Check vector */ | |
756 | if (!apic_sw_enabled(apic)) | |
757 | val |= APIC_LVT_MASKED; | |
758 | ||
759 | val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4]; | |
760 | apic_set_reg(apic, offset, val); | |
761 | ||
762 | break; | |
763 | ||
764 | case APIC_TMICT: | |
765 | hrtimer_cancel(&apic->timer.dev); | |
766 | apic_set_reg(apic, APIC_TMICT, val); | |
767 | start_apic_timer(apic); | |
768 | return; | |
769 | ||
770 | case APIC_TDCR: | |
771 | if (val & 4) | |
772 | printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val); | |
773 | apic_set_reg(apic, APIC_TDCR, val); | |
774 | update_divide_count(apic); | |
775 | break; | |
776 | ||
777 | default: | |
778 | apic_debug("Local APIC Write to read-only register %x\n", | |
779 | offset); | |
780 | break; | |
781 | } | |
782 | ||
783 | } | |
784 | ||
92760499 LV |
785 | static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr, |
786 | int len, int size) | |
97222cc8 ED |
787 | { |
788 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
789 | int ret = 0; | |
790 | ||
791 | ||
792 | if (apic_hw_enabled(apic) && | |
793 | (addr >= apic->base_address) && | |
794 | (addr < (apic->base_address + LAPIC_MMIO_LENGTH))) | |
795 | ret = 1; | |
796 | ||
797 | return ret; | |
798 | } | |
799 | ||
d589444e | 800 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 801 | { |
ad312c7c | 802 | if (!vcpu->arch.apic) |
97222cc8 ED |
803 | return; |
804 | ||
ad312c7c | 805 | hrtimer_cancel(&vcpu->arch.apic->timer.dev); |
97222cc8 | 806 | |
ad312c7c ZX |
807 | if (vcpu->arch.apic->regs_page) |
808 | __free_page(vcpu->arch.apic->regs_page); | |
97222cc8 | 809 | |
ad312c7c | 810 | kfree(vcpu->arch.apic); |
97222cc8 ED |
811 | } |
812 | ||
813 | /* | |
814 | *---------------------------------------------------------------------- | |
815 | * LAPIC interface | |
816 | *---------------------------------------------------------------------- | |
817 | */ | |
818 | ||
819 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) | |
820 | { | |
ad312c7c | 821 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
822 | |
823 | if (!apic) | |
824 | return; | |
b93463aa AK |
825 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
826 | | (apic_get_reg(apic, APIC_TASKPRI) & 4)); | |
97222cc8 | 827 | } |
ec7cf690 | 828 | EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr); |
97222cc8 ED |
829 | |
830 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
831 | { | |
ad312c7c | 832 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
833 | u64 tpr; |
834 | ||
835 | if (!apic) | |
836 | return 0; | |
837 | tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); | |
838 | ||
839 | return (tpr & 0xf0) >> 4; | |
840 | } | |
6e5d865c | 841 | EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8); |
97222cc8 ED |
842 | |
843 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
844 | { | |
ad312c7c | 845 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
846 | |
847 | if (!apic) { | |
848 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 849 | vcpu->arch.apic_base = value; |
97222cc8 ED |
850 | return; |
851 | } | |
852 | if (apic->vcpu->vcpu_id) | |
853 | value &= ~MSR_IA32_APICBASE_BSP; | |
854 | ||
ad312c7c ZX |
855 | vcpu->arch.apic_base = value; |
856 | apic->base_address = apic->vcpu->arch.apic_base & | |
97222cc8 ED |
857 | MSR_IA32_APICBASE_BASE; |
858 | ||
859 | /* with FSB delivery interrupt, we can restart APIC functionality */ | |
860 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 861 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
862 | |
863 | } | |
864 | ||
865 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu) | |
866 | { | |
ad312c7c | 867 | return vcpu->arch.apic_base; |
97222cc8 ED |
868 | } |
869 | EXPORT_SYMBOL_GPL(kvm_lapic_get_base); | |
870 | ||
c5ec1534 | 871 | void kvm_lapic_reset(struct kvm_vcpu *vcpu) |
97222cc8 ED |
872 | { |
873 | struct kvm_lapic *apic; | |
874 | int i; | |
875 | ||
b8688d51 | 876 | apic_debug("%s\n", __func__); |
97222cc8 ED |
877 | |
878 | ASSERT(vcpu); | |
ad312c7c | 879 | apic = vcpu->arch.apic; |
97222cc8 ED |
880 | ASSERT(apic != NULL); |
881 | ||
882 | /* Stop the timer in case it's a reset to an active apic */ | |
883 | hrtimer_cancel(&apic->timer.dev); | |
884 | ||
885 | apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); | |
886 | apic_set_reg(apic, APIC_LVR, APIC_VERSION); | |
887 | ||
888 | for (i = 0; i < APIC_LVT_NUM; i++) | |
889 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
40487c68 QH |
890 | apic_set_reg(apic, APIC_LVT0, |
891 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
97222cc8 ED |
892 | |
893 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
894 | apic_set_reg(apic, APIC_SPIV, 0xff); | |
895 | apic_set_reg(apic, APIC_TASKPRI, 0); | |
896 | apic_set_reg(apic, APIC_LDR, 0); | |
897 | apic_set_reg(apic, APIC_ESR, 0); | |
898 | apic_set_reg(apic, APIC_ICR, 0); | |
899 | apic_set_reg(apic, APIC_ICR2, 0); | |
900 | apic_set_reg(apic, APIC_TDCR, 0); | |
901 | apic_set_reg(apic, APIC_TMICT, 0); | |
902 | for (i = 0; i < 8; i++) { | |
903 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
904 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
905 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
906 | } | |
b33ac88b | 907 | update_divide_count(apic); |
97222cc8 ED |
908 | atomic_set(&apic->timer.pending, 0); |
909 | if (vcpu->vcpu_id == 0) | |
ad312c7c | 910 | vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; |
97222cc8 ED |
911 | apic_update_ppr(apic); |
912 | ||
913 | apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" | |
b8688d51 | 914 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 915 | vcpu, kvm_apic_id(apic), |
ad312c7c | 916 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 | 917 | } |
c5ec1534 | 918 | EXPORT_SYMBOL_GPL(kvm_lapic_reset); |
97222cc8 ED |
919 | |
920 | int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
921 | { | |
ad312c7c | 922 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
923 | int ret = 0; |
924 | ||
925 | if (!apic) | |
926 | return 0; | |
927 | ret = apic_enabled(apic); | |
928 | ||
929 | return ret; | |
930 | } | |
6e5d865c | 931 | EXPORT_SYMBOL_GPL(kvm_lapic_enabled); |
97222cc8 ED |
932 | |
933 | /* | |
934 | *---------------------------------------------------------------------- | |
935 | * timer interface | |
936 | *---------------------------------------------------------------------- | |
937 | */ | |
1b9778da ED |
938 | |
939 | /* TODO: make sure __apic_timer_fn runs in current pCPU */ | |
97222cc8 ED |
940 | static int __apic_timer_fn(struct kvm_lapic *apic) |
941 | { | |
97222cc8 | 942 | int result = 0; |
1b9778da | 943 | wait_queue_head_t *q = &apic->vcpu->wq; |
97222cc8 | 944 | |
622395a9 MT |
945 | if(!atomic_inc_and_test(&apic->timer.pending)) |
946 | set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests); | |
d7690175 | 947 | if (waitqueue_active(q)) |
1b9778da | 948 | wake_up_interruptible(q); |
d7690175 | 949 | |
97222cc8 | 950 | if (apic_lvtt_period(apic)) { |
97222cc8 | 951 | result = 1; |
beb20d52 | 952 | hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period); |
97222cc8 | 953 | } |
97222cc8 ED |
954 | return result; |
955 | } | |
956 | ||
3d80840d MT |
957 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
958 | { | |
959 | struct kvm_lapic *lapic = vcpu->arch.apic; | |
960 | ||
54aaacee | 961 | if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) |
3d80840d MT |
962 | return atomic_read(&lapic->timer.pending); |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
8fdb2351 | 967 | static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 968 | { |
8fdb2351 | 969 | u32 reg = apic_get_reg(apic, lvt_type); |
23930f95 | 970 | int vector, mode, trig_mode; |
23930f95 | 971 | |
8fdb2351 | 972 | if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
973 | vector = reg & APIC_VECTOR_MASK; |
974 | mode = reg & APIC_MODE_MASK; | |
975 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
976 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode); | |
977 | } | |
978 | return 0; | |
979 | } | |
1b9778da | 980 | |
8fdb2351 | 981 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 982 | { |
8fdb2351 JK |
983 | struct kvm_lapic *apic = vcpu->arch.apic; |
984 | ||
985 | if (apic) | |
986 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
987 | } |
988 | ||
97222cc8 ED |
989 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
990 | { | |
991 | struct kvm_lapic *apic; | |
992 | int restart_timer = 0; | |
993 | ||
994 | apic = container_of(data, struct kvm_lapic, timer.dev); | |
995 | ||
996 | restart_timer = __apic_timer_fn(apic); | |
997 | ||
998 | if (restart_timer) | |
999 | return HRTIMER_RESTART; | |
1000 | else | |
1001 | return HRTIMER_NORESTART; | |
1002 | } | |
1003 | ||
1004 | int kvm_create_lapic(struct kvm_vcpu *vcpu) | |
1005 | { | |
1006 | struct kvm_lapic *apic; | |
1007 | ||
1008 | ASSERT(vcpu != NULL); | |
1009 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1010 | ||
1011 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1012 | if (!apic) | |
1013 | goto nomem; | |
1014 | ||
ad312c7c | 1015 | vcpu->arch.apic = apic; |
97222cc8 ED |
1016 | |
1017 | apic->regs_page = alloc_page(GFP_KERNEL); | |
1018 | if (apic->regs_page == NULL) { | |
1019 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", | |
1020 | vcpu->vcpu_id); | |
d589444e | 1021 | goto nomem_free_apic; |
97222cc8 ED |
1022 | } |
1023 | apic->regs = page_address(apic->regs_page); | |
1024 | memset(apic->regs, 0, PAGE_SIZE); | |
1025 | apic->vcpu = vcpu; | |
1026 | ||
1027 | hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
1028 | apic->timer.dev.function = apic_timer_fn; | |
1029 | apic->base_address = APIC_DEFAULT_PHYS_BASE; | |
ad312c7c | 1030 | vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; |
97222cc8 | 1031 | |
c5ec1534 | 1032 | kvm_lapic_reset(vcpu); |
97222cc8 ED |
1033 | apic->dev.read = apic_mmio_read; |
1034 | apic->dev.write = apic_mmio_write; | |
1035 | apic->dev.in_range = apic_mmio_range; | |
1036 | apic->dev.private = apic; | |
1037 | ||
1038 | return 0; | |
d589444e RR |
1039 | nomem_free_apic: |
1040 | kfree(apic); | |
97222cc8 | 1041 | nomem: |
97222cc8 ED |
1042 | return -ENOMEM; |
1043 | } | |
1044 | EXPORT_SYMBOL_GPL(kvm_create_lapic); | |
1045 | ||
1046 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1047 | { | |
ad312c7c | 1048 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1049 | int highest_irr; |
1050 | ||
1051 | if (!apic || !apic_enabled(apic)) | |
1052 | return -1; | |
1053 | ||
6e5d865c | 1054 | apic_update_ppr(apic); |
97222cc8 ED |
1055 | highest_irr = apic_find_highest_irr(apic); |
1056 | if ((highest_irr == -1) || | |
1057 | ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) | |
1058 | return -1; | |
1059 | return highest_irr; | |
1060 | } | |
1061 | ||
40487c68 QH |
1062 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1063 | { | |
ad312c7c | 1064 | u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1065 | int r = 0; |
1066 | ||
1067 | if (vcpu->vcpu_id == 0) { | |
ad312c7c | 1068 | if (!apic_hw_enabled(vcpu->arch.apic)) |
40487c68 QH |
1069 | r = 1; |
1070 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1071 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1072 | r = 1; | |
1073 | } | |
1074 | return r; | |
1075 | } | |
1076 | ||
1b9778da ED |
1077 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1078 | { | |
ad312c7c | 1079 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1080 | |
8fdb2351 JK |
1081 | if (apic && atomic_read(&apic->timer.pending) > 0) { |
1082 | if (kvm_apic_local_deliver(apic, APIC_LVTT)) | |
1b9778da ED |
1083 | atomic_dec(&apic->timer.pending); |
1084 | } | |
1085 | } | |
1086 | ||
97222cc8 ED |
1087 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1088 | { | |
1089 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1090 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1091 | |
1092 | if (vector == -1) | |
1093 | return -1; | |
1094 | ||
1095 | apic_set_vector(vector, apic->regs + APIC_ISR); | |
1096 | apic_update_ppr(apic); | |
1097 | apic_clear_irr(vector, apic); | |
1098 | return vector; | |
1099 | } | |
96ad2cc6 ED |
1100 | |
1101 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) | |
1102 | { | |
ad312c7c | 1103 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1104 | |
ad312c7c | 1105 | apic->base_address = vcpu->arch.apic_base & |
96ad2cc6 ED |
1106 | MSR_IA32_APICBASE_BASE; |
1107 | apic_set_reg(apic, APIC_LVR, APIC_VERSION); | |
1108 | apic_update_ppr(apic); | |
1109 | hrtimer_cancel(&apic->timer.dev); | |
1110 | update_divide_count(apic); | |
1111 | start_apic_timer(apic); | |
1112 | } | |
a3d7f85f | 1113 | |
2f52d58c | 1114 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1115 | { |
ad312c7c | 1116 | struct kvm_lapic *apic = vcpu->arch.apic; |
a3d7f85f ED |
1117 | struct hrtimer *timer; |
1118 | ||
1119 | if (!apic) | |
1120 | return; | |
1121 | ||
1122 | timer = &apic->timer.dev; | |
1123 | if (hrtimer_cancel(timer)) | |
beb20d52 | 1124 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1125 | } |
b93463aa AK |
1126 | |
1127 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) | |
1128 | { | |
1129 | u32 data; | |
1130 | void *vapic; | |
1131 | ||
1132 | if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) | |
1133 | return; | |
1134 | ||
1135 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); | |
1136 | data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); | |
1137 | kunmap_atomic(vapic, KM_USER0); | |
1138 | ||
1139 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1140 | } | |
1141 | ||
1142 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) | |
1143 | { | |
1144 | u32 data, tpr; | |
1145 | int max_irr, max_isr; | |
1146 | struct kvm_lapic *apic; | |
1147 | void *vapic; | |
1148 | ||
1149 | if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) | |
1150 | return; | |
1151 | ||
1152 | apic = vcpu->arch.apic; | |
1153 | tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; | |
1154 | max_irr = apic_find_highest_irr(apic); | |
1155 | if (max_irr < 0) | |
1156 | max_irr = 0; | |
1157 | max_isr = apic_find_highest_isr(apic); | |
1158 | if (max_isr < 0) | |
1159 | max_isr = 0; | |
1160 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1161 | ||
1162 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); | |
1163 | *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; | |
1164 | kunmap_atomic(vapic, KM_USER0); | |
1165 | } | |
1166 | ||
1167 | void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) | |
1168 | { | |
1169 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1170 | return; | |
1171 | ||
1172 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
1173 | } |