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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
57 | #define APIC_BUS_CYCLE_NS 1 | |
58 | ||
59 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
60 | #define apic_debug(fmt, arg...) | |
61 | ||
62 | #define APIC_LVT_NUM 6 | |
63 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
64 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
65 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
66 | /* followed define is not in apicdef.h */ | |
67 | #define APIC_SHORT_MASK 0xc0000 | |
68 | #define APIC_DEST_NOSHORT 0x0 | |
69 | #define APIC_DEST_MASK 0x800 | |
70 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 71 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 72 | |
394457a9 NA |
73 | #define APIC_BROADCAST 0xFF |
74 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
75 | ||
97222cc8 ED |
76 | #define VEC_POS(v) ((v) & (32 - 1)) |
77 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 78 | |
97222cc8 ED |
79 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
80 | { | |
81 | *((u32 *) (apic->regs + reg_off)) = val; | |
82 | } | |
83 | ||
a0c9a822 MT |
84 | static inline int apic_test_vector(int vec, void *bitmap) |
85 | { | |
86 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
87 | } | |
88 | ||
10606919 YZ |
89 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
90 | { | |
91 | struct kvm_lapic *apic = vcpu->arch.apic; | |
92 | ||
93 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
94 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
95 | } | |
96 | ||
97222cc8 ED |
97 | static inline void apic_set_vector(int vec, void *bitmap) |
98 | { | |
99 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
100 | } | |
101 | ||
102 | static inline void apic_clear_vector(int vec, void *bitmap) | |
103 | { | |
104 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
105 | } | |
106 | ||
8680b94b MT |
107 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
108 | { | |
109 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
110 | } | |
111 | ||
112 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
113 | { | |
114 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
115 | } | |
116 | ||
c5cc421b | 117 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
118 | struct static_key_deferred apic_sw_disabled __read_mostly; |
119 | ||
97222cc8 ED |
120 | static inline int apic_enabled(struct kvm_lapic *apic) |
121 | { | |
c48f1496 | 122 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
123 | } |
124 | ||
97222cc8 ED |
125 | #define LVT_MASK \ |
126 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
127 | ||
128 | #define LINT_MASK \ | |
129 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
130 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
131 | ||
3548a259 RK |
132 | /* The logical map is definitely wrong if we have multiple |
133 | * modes at the same time. (Physical map is always right.) | |
134 | */ | |
135 | static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map) | |
136 | { | |
137 | return !(map->mode & (map->mode - 1)); | |
138 | } | |
139 | ||
3b5a5ffa RK |
140 | static inline void |
141 | apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid) | |
142 | { | |
143 | unsigned lid_bits; | |
144 | ||
145 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4); | |
146 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8); | |
147 | BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16); | |
148 | lid_bits = map->mode; | |
149 | ||
150 | *cid = dest_id >> lid_bits; | |
151 | *lid = dest_id & ((1 << lid_bits) - 1); | |
152 | } | |
153 | ||
1e08ec4a GN |
154 | static void recalculate_apic_map(struct kvm *kvm) |
155 | { | |
156 | struct kvm_apic_map *new, *old = NULL; | |
157 | struct kvm_vcpu *vcpu; | |
158 | int i; | |
159 | ||
160 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
161 | ||
162 | mutex_lock(&kvm->arch.apic_map_lock); | |
163 | ||
164 | if (!new) | |
165 | goto out; | |
166 | ||
173beedc NA |
167 | kvm_for_each_vcpu(i, vcpu, kvm) { |
168 | struct kvm_lapic *apic = vcpu->arch.apic; | |
169 | u16 cid, lid; | |
25995e5b | 170 | u32 ldr, aid; |
1e08ec4a | 171 | |
df04d1d1 RK |
172 | if (!kvm_apic_present(vcpu)) |
173 | continue; | |
174 | ||
25995e5b | 175 | aid = kvm_apic_id(apic); |
1e08ec4a | 176 | ldr = kvm_apic_get_reg(apic, APIC_LDR); |
1e08ec4a | 177 | |
25995e5b RK |
178 | if (aid < ARRAY_SIZE(new->phys_map)) |
179 | new->phys_map[aid] = apic; | |
3548a259 | 180 | |
3b5a5ffa RK |
181 | if (apic_x2apic_mode(apic)) { |
182 | new->mode |= KVM_APIC_MODE_X2APIC; | |
183 | } else if (ldr) { | |
184 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
185 | if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) | |
186 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; | |
187 | else | |
188 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
189 | } | |
190 | ||
191 | if (!kvm_apic_logical_map_valid(new)) | |
3548a259 RK |
192 | continue; |
193 | ||
3b5a5ffa RK |
194 | apic_logical_id(new, ldr, &cid, &lid); |
195 | ||
25995e5b | 196 | if (lid && cid < ARRAY_SIZE(new->logical_map)) |
1e08ec4a GN |
197 | new->logical_map[cid][ffs(lid) - 1] = apic; |
198 | } | |
199 | out: | |
200 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
201 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
202 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
203 | mutex_unlock(&kvm->arch.apic_map_lock); | |
204 | ||
205 | if (old) | |
206 | kfree_rcu(old, rcu); | |
c7c9c56c | 207 | |
b053b2ae | 208 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
209 | } |
210 | ||
1e1b6c26 NA |
211 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
212 | { | |
e462755c | 213 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 NA |
214 | |
215 | apic_set_reg(apic, APIC_SPIV, val); | |
e462755c RK |
216 | |
217 | if (enabled != apic->sw_enabled) { | |
218 | apic->sw_enabled = enabled; | |
219 | if (enabled) { | |
1e1b6c26 NA |
220 | static_key_slow_dec_deferred(&apic_sw_disabled); |
221 | recalculate_apic_map(apic->vcpu->kvm); | |
222 | } else | |
223 | static_key_slow_inc(&apic_sw_disabled.key); | |
224 | } | |
225 | } | |
226 | ||
1e08ec4a GN |
227 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
228 | { | |
229 | apic_set_reg(apic, APIC_ID, id << 24); | |
230 | recalculate_apic_map(apic->vcpu->kvm); | |
231 | } | |
232 | ||
233 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
234 | { | |
235 | apic_set_reg(apic, APIC_LDR, id); | |
236 | recalculate_apic_map(apic->vcpu->kvm); | |
237 | } | |
238 | ||
257b9a5f RK |
239 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id) |
240 | { | |
241 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
242 | ||
243 | apic_set_reg(apic, APIC_ID, id << 24); | |
244 | apic_set_reg(apic, APIC_LDR, ldr); | |
245 | recalculate_apic_map(apic->vcpu->kvm); | |
246 | } | |
247 | ||
97222cc8 ED |
248 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
249 | { | |
c48f1496 | 250 | return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
251 | } |
252 | ||
253 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
254 | { | |
c48f1496 | 255 | return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
256 | } |
257 | ||
a3e06bbe LJ |
258 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
259 | { | |
f30ebc31 | 260 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
261 | } |
262 | ||
97222cc8 ED |
263 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
264 | { | |
f30ebc31 | 265 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
266 | } |
267 | ||
268 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
269 | { | |
f30ebc31 | 270 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
271 | } |
272 | ||
cc6e462c JK |
273 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
274 | { | |
275 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
276 | } | |
277 | ||
fc61b800 GN |
278 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
279 | { | |
280 | struct kvm_lapic *apic = vcpu->arch.apic; | |
281 | struct kvm_cpuid_entry2 *feat; | |
282 | u32 v = APIC_VERSION; | |
283 | ||
c48f1496 | 284 | if (!kvm_vcpu_has_lapic(vcpu)) |
fc61b800 GN |
285 | return; |
286 | ||
287 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
288 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
289 | v |= APIC_LVR_DIRECTED_EOI; | |
290 | apic_set_reg(apic, APIC_LVR, v); | |
291 | } | |
292 | ||
f1d24831 | 293 | static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
a3e06bbe | 294 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
295 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
296 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
297 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
298 | LVT_MASK /* LVTERR */ | |
299 | }; | |
300 | ||
301 | static int find_highest_vector(void *bitmap) | |
302 | { | |
ecba9a52 TY |
303 | int vec; |
304 | u32 *reg; | |
97222cc8 | 305 | |
ecba9a52 TY |
306 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
307 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
308 | reg = bitmap + REG_POS(vec); | |
309 | if (*reg) | |
310 | return fls(*reg) - 1 + vec; | |
311 | } | |
97222cc8 | 312 | |
ecba9a52 | 313 | return -1; |
97222cc8 ED |
314 | } |
315 | ||
8680b94b MT |
316 | static u8 count_vectors(void *bitmap) |
317 | { | |
ecba9a52 TY |
318 | int vec; |
319 | u32 *reg; | |
8680b94b | 320 | u8 count = 0; |
ecba9a52 TY |
321 | |
322 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
323 | reg = bitmap + REG_POS(vec); | |
324 | count += hweight32(*reg); | |
325 | } | |
326 | ||
8680b94b MT |
327 | return count; |
328 | } | |
329 | ||
705699a1 | 330 | void __kvm_apic_update_irr(u32 *pir, void *regs) |
a20ed54d YZ |
331 | { |
332 | u32 i, pir_val; | |
a20ed54d YZ |
333 | |
334 | for (i = 0; i <= 7; i++) { | |
335 | pir_val = xchg(&pir[i], 0); | |
336 | if (pir_val) | |
705699a1 | 337 | *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val; |
a20ed54d YZ |
338 | } |
339 | } | |
705699a1 WV |
340 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
341 | ||
342 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) | |
343 | { | |
344 | struct kvm_lapic *apic = vcpu->arch.apic; | |
345 | ||
346 | __kvm_apic_update_irr(pir, apic->regs); | |
c77f3fab RK |
347 | |
348 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
705699a1 | 349 | } |
a20ed54d YZ |
350 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
351 | ||
11f5cc05 | 352 | static inline void apic_set_irr(int vec, struct kvm_lapic *apic) |
97222cc8 | 353 | { |
11f5cc05 | 354 | apic_set_vector(vec, apic->regs + APIC_IRR); |
f210f757 NA |
355 | /* |
356 | * irr_pending must be true if any interrupt is pending; set it after | |
357 | * APIC_IRR to avoid race with apic_clear_irr | |
358 | */ | |
359 | apic->irr_pending = true; | |
97222cc8 ED |
360 | } |
361 | ||
33e4c686 | 362 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 363 | { |
33e4c686 | 364 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
365 | } |
366 | ||
367 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
368 | { | |
369 | int result; | |
370 | ||
c7c9c56c YZ |
371 | /* |
372 | * Note that irr_pending is just a hint. It will be always | |
373 | * true with virtual interrupt delivery enabled. | |
374 | */ | |
33e4c686 GN |
375 | if (!apic->irr_pending) |
376 | return -1; | |
377 | ||
d62caabb AS |
378 | if (apic->vcpu->arch.apicv_active) |
379 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); | |
33e4c686 | 380 | result = apic_search_irr(apic); |
97222cc8 ED |
381 | ASSERT(result == -1 || result >= 16); |
382 | ||
383 | return result; | |
384 | } | |
385 | ||
33e4c686 GN |
386 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
387 | { | |
56cc2406 WL |
388 | struct kvm_vcpu *vcpu; |
389 | ||
390 | vcpu = apic->vcpu; | |
391 | ||
d62caabb | 392 | if (unlikely(vcpu->arch.apicv_active)) { |
56cc2406 | 393 | /* try to update RVI */ |
f210f757 | 394 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 395 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
396 | } else { |
397 | apic->irr_pending = false; | |
398 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
399 | if (apic_search_irr(apic) != -1) | |
400 | apic->irr_pending = true; | |
56cc2406 | 401 | } |
33e4c686 GN |
402 | } |
403 | ||
8680b94b MT |
404 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
405 | { | |
56cc2406 WL |
406 | struct kvm_vcpu *vcpu; |
407 | ||
408 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
409 | return; | |
410 | ||
411 | vcpu = apic->vcpu; | |
fc57ac2c | 412 | |
8680b94b | 413 | /* |
56cc2406 WL |
414 | * With APIC virtualization enabled, all caching is disabled |
415 | * because the processor can modify ISR under the hood. Instead | |
416 | * just set SVI. | |
8680b94b | 417 | */ |
d62caabb | 418 | if (unlikely(vcpu->arch.apicv_active)) |
56cc2406 WL |
419 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec); |
420 | else { | |
421 | ++apic->isr_count; | |
422 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
423 | /* | |
424 | * ISR (in service register) bit is set when injecting an interrupt. | |
425 | * The highest vector is injected. Thus the latest bit set matches | |
426 | * the highest bit in ISR. | |
427 | */ | |
428 | apic->highest_isr_cache = vec; | |
429 | } | |
8680b94b MT |
430 | } |
431 | ||
fc57ac2c PB |
432 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
433 | { | |
434 | int result; | |
435 | ||
436 | /* | |
437 | * Note that isr_count is always 1, and highest_isr_cache | |
438 | * is always -1, with APIC virtualization enabled. | |
439 | */ | |
440 | if (!apic->isr_count) | |
441 | return -1; | |
442 | if (likely(apic->highest_isr_cache != -1)) | |
443 | return apic->highest_isr_cache; | |
444 | ||
445 | result = find_highest_vector(apic->regs + APIC_ISR); | |
446 | ASSERT(result == -1 || result >= 16); | |
447 | ||
448 | return result; | |
449 | } | |
450 | ||
8680b94b MT |
451 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
452 | { | |
fc57ac2c PB |
453 | struct kvm_vcpu *vcpu; |
454 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
455 | return; | |
456 | ||
457 | vcpu = apic->vcpu; | |
458 | ||
459 | /* | |
460 | * We do get here for APIC virtualization enabled if the guest | |
461 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
462 | * to trigger a new interrupt delivery by writing the SVI field; | |
463 | * on the other hand isr_count and highest_isr_cache are unused | |
464 | * and must be left alone. | |
465 | */ | |
d62caabb | 466 | if (unlikely(vcpu->arch.apicv_active)) |
fc57ac2c PB |
467 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, |
468 | apic_find_highest_isr(apic)); | |
469 | else { | |
8680b94b | 470 | --apic->isr_count; |
fc57ac2c PB |
471 | BUG_ON(apic->isr_count < 0); |
472 | apic->highest_isr_cache = -1; | |
473 | } | |
8680b94b MT |
474 | } |
475 | ||
6e5d865c YS |
476 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
477 | { | |
6e5d865c YS |
478 | int highest_irr; |
479 | ||
33e4c686 GN |
480 | /* This may race with setting of irr in __apic_accept_irq() and |
481 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
482 | * will cause vmexit immediately and the value will be recalculated | |
483 | * on the next vmentry. | |
484 | */ | |
c48f1496 | 485 | if (!kvm_vcpu_has_lapic(vcpu)) |
6e5d865c | 486 | return 0; |
54e9818f | 487 | highest_irr = apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c YS |
488 | |
489 | return highest_irr; | |
490 | } | |
6e5d865c | 491 | |
6da7e3f6 | 492 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c YZ |
493 | int vector, int level, int trig_mode, |
494 | unsigned long *dest_map); | |
6da7e3f6 | 495 | |
b4f2225c YZ |
496 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
497 | unsigned long *dest_map) | |
97222cc8 | 498 | { |
ad312c7c | 499 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 500 | |
58c2dde1 | 501 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 502 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
503 | } |
504 | ||
ae7a2a3f MT |
505 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
506 | { | |
507 | ||
508 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
509 | sizeof(val)); | |
510 | } | |
511 | ||
512 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
513 | { | |
514 | ||
515 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
516 | sizeof(*val)); | |
517 | } | |
518 | ||
519 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
520 | { | |
521 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
522 | } | |
523 | ||
524 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
525 | { | |
526 | u8 val; | |
527 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
528 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 529 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
530 | return val & 0x1; |
531 | } | |
532 | ||
533 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
534 | { | |
535 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
536 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 537 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
538 | return; |
539 | } | |
540 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
541 | } | |
542 | ||
543 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
544 | { | |
545 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
546 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 547 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
548 | return; |
549 | } | |
550 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
551 | } | |
552 | ||
97222cc8 ED |
553 | static void apic_update_ppr(struct kvm_lapic *apic) |
554 | { | |
3842d135 | 555 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
556 | int isr; |
557 | ||
c48f1496 GN |
558 | old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); |
559 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
560 | isr = apic_find_highest_isr(apic); |
561 | isrv = (isr != -1) ? isr : 0; | |
562 | ||
563 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
564 | ppr = tpr & 0xff; | |
565 | else | |
566 | ppr = isrv & 0xf0; | |
567 | ||
568 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
569 | apic, ppr, isr, isrv); | |
570 | ||
3842d135 AK |
571 | if (old_ppr != ppr) { |
572 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
83bcacb1 AK |
573 | if (ppr < old_ppr) |
574 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 575 | } |
97222cc8 ED |
576 | } |
577 | ||
578 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
579 | { | |
580 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
581 | apic_update_ppr(apic); | |
582 | } | |
583 | ||
03d2249e | 584 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 585 | { |
03d2249e RK |
586 | if (apic_x2apic_mode(apic)) |
587 | return mda == X2APIC_BROADCAST; | |
588 | ||
589 | return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST; | |
394457a9 NA |
590 | } |
591 | ||
03d2249e | 592 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 593 | { |
03d2249e RK |
594 | if (kvm_apic_broadcast(apic, mda)) |
595 | return true; | |
596 | ||
597 | if (apic_x2apic_mode(apic)) | |
598 | return mda == kvm_apic_id(apic); | |
599 | ||
600 | return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic)); | |
97222cc8 ED |
601 | } |
602 | ||
52c233a4 | 603 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 604 | { |
0105d1a5 GN |
605 | u32 logical_id; |
606 | ||
394457a9 | 607 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 608 | return true; |
394457a9 | 609 | |
9368b567 | 610 | logical_id = kvm_apic_get_reg(apic, APIC_LDR); |
97222cc8 | 611 | |
9368b567 | 612 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
613 | return ((logical_id >> 16) == (mda >> 16)) |
614 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 615 | |
9368b567 | 616 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
03d2249e | 617 | mda = GET_APIC_DEST_FIELD(mda); |
97222cc8 | 618 | |
c48f1496 | 619 | switch (kvm_apic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 620 | case APIC_DFR_FLAT: |
9368b567 | 621 | return (logical_id & mda) != 0; |
97222cc8 | 622 | case APIC_DFR_CLUSTER: |
9368b567 RK |
623 | return ((logical_id >> 4) == (mda >> 4)) |
624 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 625 | default: |
7712de87 | 626 | apic_debug("Bad DFR vcpu %d: %08x\n", |
c48f1496 | 627 | apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); |
9368b567 | 628 | return false; |
97222cc8 | 629 | } |
97222cc8 ED |
630 | } |
631 | ||
03d2249e RK |
632 | /* KVM APIC implementation has two quirks |
633 | * - dest always begins at 0 while xAPIC MDA has offset 24, | |
634 | * - IOxAPIC messages have to be delivered (directly) to x2APIC. | |
635 | */ | |
636 | static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source, | |
637 | struct kvm_lapic *target) | |
638 | { | |
639 | bool ipi = source != NULL; | |
640 | bool x2apic_mda = apic_x2apic_mode(ipi ? source : target); | |
641 | ||
642 | if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda) | |
643 | return X2APIC_BROADCAST; | |
644 | ||
645 | return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id); | |
646 | } | |
647 | ||
52c233a4 | 648 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 649 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 650 | { |
ad312c7c | 651 | struct kvm_lapic *target = vcpu->arch.apic; |
03d2249e | 652 | u32 mda = kvm_apic_mda(dest, source, target); |
97222cc8 ED |
653 | |
654 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 655 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
656 | target, source, dest, dest_mode, short_hand); |
657 | ||
bd371396 | 658 | ASSERT(target); |
97222cc8 ED |
659 | switch (short_hand) { |
660 | case APIC_DEST_NOSHORT: | |
3697f302 | 661 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 662 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 663 | else |
03d2249e | 664 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 665 | case APIC_DEST_SELF: |
9368b567 | 666 | return target == source; |
97222cc8 | 667 | case APIC_DEST_ALLINC: |
9368b567 | 668 | return true; |
97222cc8 | 669 | case APIC_DEST_ALLBUT: |
9368b567 | 670 | return target != source; |
97222cc8 | 671 | default: |
7712de87 JK |
672 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
673 | short_hand); | |
9368b567 | 674 | return false; |
97222cc8 | 675 | } |
97222cc8 ED |
676 | } |
677 | ||
1e08ec4a | 678 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 679 | struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) |
1e08ec4a GN |
680 | { |
681 | struct kvm_apic_map *map; | |
682 | unsigned long bitmap = 1; | |
683 | struct kvm_lapic **dst; | |
684 | int i; | |
bea15428 | 685 | bool ret, x2apic_ipi; |
1e08ec4a GN |
686 | |
687 | *r = -1; | |
688 | ||
689 | if (irq->shorthand == APIC_DEST_SELF) { | |
b4f2225c | 690 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); |
1e08ec4a GN |
691 | return true; |
692 | } | |
693 | ||
694 | if (irq->shorthand) | |
695 | return false; | |
696 | ||
bea15428 | 697 | x2apic_ipi = src && apic_x2apic_mode(src); |
9ea369b0 RK |
698 | if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST)) |
699 | return false; | |
700 | ||
bea15428 | 701 | ret = true; |
1e08ec4a GN |
702 | rcu_read_lock(); |
703 | map = rcu_dereference(kvm->arch.apic_map); | |
704 | ||
bea15428 PB |
705 | if (!map) { |
706 | ret = false; | |
1e08ec4a | 707 | goto out; |
bea15428 | 708 | } |
698f9755 | 709 | |
3697f302 | 710 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
fa834e91 RK |
711 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) |
712 | goto out; | |
713 | ||
714 | dst = &map->phys_map[irq->dest_id]; | |
1e08ec4a | 715 | } else { |
3548a259 RK |
716 | u16 cid; |
717 | ||
718 | if (!kvm_apic_logical_map_valid(map)) { | |
719 | ret = false; | |
720 | goto out; | |
721 | } | |
722 | ||
3b5a5ffa | 723 | apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap); |
45c3094a RK |
724 | |
725 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
726 | goto out; | |
1e08ec4a | 727 | |
45c3094a | 728 | dst = map->logical_map[cid]; |
1e08ec4a | 729 | |
d1ebdbf9 | 730 | if (kvm_lowest_prio_delivery(irq)) { |
1e08ec4a GN |
731 | int l = -1; |
732 | for_each_set_bit(i, &bitmap, 16) { | |
733 | if (!dst[i]) | |
734 | continue; | |
735 | if (l < 0) | |
736 | l = i; | |
737 | else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) | |
738 | l = i; | |
739 | } | |
740 | ||
741 | bitmap = (l >= 0) ? 1 << l : 0; | |
742 | } | |
743 | } | |
744 | ||
745 | for_each_set_bit(i, &bitmap, 16) { | |
746 | if (!dst[i]) | |
747 | continue; | |
748 | if (*r < 0) | |
749 | *r = 0; | |
b4f2225c | 750 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 751 | } |
1e08ec4a GN |
752 | out: |
753 | rcu_read_unlock(); | |
754 | return ret; | |
755 | } | |
756 | ||
8feb4a04 FW |
757 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
758 | struct kvm_vcpu **dest_vcpu) | |
759 | { | |
760 | struct kvm_apic_map *map; | |
761 | bool ret = false; | |
762 | struct kvm_lapic *dst = NULL; | |
763 | ||
764 | if (irq->shorthand) | |
765 | return false; | |
766 | ||
767 | rcu_read_lock(); | |
768 | map = rcu_dereference(kvm->arch.apic_map); | |
769 | ||
770 | if (!map) | |
771 | goto out; | |
772 | ||
773 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { | |
774 | if (irq->dest_id == 0xFF) | |
775 | goto out; | |
776 | ||
777 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) | |
778 | goto out; | |
779 | ||
780 | dst = map->phys_map[irq->dest_id]; | |
781 | if (dst && kvm_apic_present(dst->vcpu)) | |
782 | *dest_vcpu = dst->vcpu; | |
783 | else | |
784 | goto out; | |
785 | } else { | |
786 | u16 cid; | |
787 | unsigned long bitmap = 1; | |
788 | int i, r = 0; | |
789 | ||
790 | if (!kvm_apic_logical_map_valid(map)) | |
791 | goto out; | |
792 | ||
793 | apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap); | |
794 | ||
795 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
796 | goto out; | |
797 | ||
798 | for_each_set_bit(i, &bitmap, 16) { | |
799 | dst = map->logical_map[cid][i]; | |
800 | if (++r == 2) | |
801 | goto out; | |
802 | } | |
803 | ||
804 | if (dst && kvm_apic_present(dst->vcpu)) | |
805 | *dest_vcpu = dst->vcpu; | |
806 | else | |
807 | goto out; | |
808 | } | |
809 | ||
810 | ret = true; | |
811 | out: | |
812 | rcu_read_unlock(); | |
813 | return ret; | |
814 | } | |
815 | ||
97222cc8 ED |
816 | /* |
817 | * Add a pending IRQ into lapic. | |
818 | * Return 1 if successfully added and 0 if discarded. | |
819 | */ | |
820 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c YZ |
821 | int vector, int level, int trig_mode, |
822 | unsigned long *dest_map) | |
97222cc8 | 823 | { |
6da7e3f6 | 824 | int result = 0; |
c5ec1534 | 825 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 826 | |
a183b638 PB |
827 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
828 | trig_mode, vector); | |
97222cc8 | 829 | switch (delivery_mode) { |
97222cc8 | 830 | case APIC_DM_LOWEST: |
e1035715 GN |
831 | vcpu->arch.apic_arb_prio++; |
832 | case APIC_DM_FIXED: | |
bdaffe1d PB |
833 | if (unlikely(trig_mode && !level)) |
834 | break; | |
835 | ||
97222cc8 ED |
836 | /* FIXME add logic for vcpu on reset */ |
837 | if (unlikely(!apic_enabled(apic))) | |
838 | break; | |
839 | ||
11f5cc05 JK |
840 | result = 1; |
841 | ||
b4f2225c YZ |
842 | if (dest_map) |
843 | __set_bit(vcpu->vcpu_id, dest_map); | |
a5d36f82 | 844 | |
bdaffe1d PB |
845 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
846 | if (trig_mode) | |
847 | apic_set_vector(vector, apic->regs + APIC_TMR); | |
848 | else | |
849 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
850 | } | |
851 | ||
d62caabb | 852 | if (vcpu->arch.apicv_active) |
5a71785d | 853 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 JK |
854 | else { |
855 | apic_set_irr(vector, apic); | |
5a71785d YZ |
856 | |
857 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
858 | kvm_vcpu_kick(vcpu); | |
859 | } | |
97222cc8 ED |
860 | break; |
861 | ||
862 | case APIC_DM_REMRD: | |
24d2166b R |
863 | result = 1; |
864 | vcpu->arch.pv.pv_unhalted = 1; | |
865 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
866 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
867 | break; |
868 | ||
869 | case APIC_DM_SMI: | |
64d60670 PB |
870 | result = 1; |
871 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
872 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 873 | break; |
3419ffc8 | 874 | |
97222cc8 | 875 | case APIC_DM_NMI: |
6da7e3f6 | 876 | result = 1; |
3419ffc8 | 877 | kvm_inject_nmi(vcpu); |
26df99c6 | 878 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
879 | break; |
880 | ||
881 | case APIC_DM_INIT: | |
a52315e1 | 882 | if (!trig_mode || level) { |
6da7e3f6 | 883 | result = 1; |
66450a21 JK |
884 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
885 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
886 | /* make sure pending_events is visible before sending | |
887 | * the request */ | |
888 | smp_wmb(); | |
3842d135 | 889 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
890 | kvm_vcpu_kick(vcpu); |
891 | } else { | |
1b10bf31 JK |
892 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
893 | vcpu->vcpu_id); | |
c5ec1534 | 894 | } |
97222cc8 ED |
895 | break; |
896 | ||
897 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
898 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
899 | vcpu->vcpu_id, vector); | |
66450a21 JK |
900 | result = 1; |
901 | apic->sipi_vector = vector; | |
902 | /* make sure sipi_vector is visible for the receiver */ | |
903 | smp_wmb(); | |
904 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
905 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
906 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
907 | break; |
908 | ||
23930f95 JK |
909 | case APIC_DM_EXTINT: |
910 | /* | |
911 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
912 | * before NMI watchdog was enabled. Already handled by | |
913 | * kvm_apic_accept_pic_intr(). | |
914 | */ | |
915 | break; | |
916 | ||
97222cc8 ED |
917 | default: |
918 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
919 | delivery_mode); | |
920 | break; | |
921 | } | |
922 | return result; | |
923 | } | |
924 | ||
e1035715 | 925 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 926 | { |
e1035715 | 927 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
928 | } |
929 | ||
3bb345f3 PB |
930 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
931 | { | |
6308630b | 932 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
933 | } |
934 | ||
c7c9c56c YZ |
935 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
936 | { | |
7543a635 SR |
937 | int trigger_mode; |
938 | ||
939 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
940 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
941 | return; | |
3bb345f3 | 942 | |
7543a635 SR |
943 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
944 | if (irqchip_split(apic->vcpu->kvm)) { | |
945 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
946 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
947 | return; | |
c7c9c56c | 948 | } |
7543a635 SR |
949 | |
950 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
951 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
952 | else | |
953 | trigger_mode = IOAPIC_EDGE_TRIG; | |
954 | ||
955 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
956 | } |
957 | ||
ae7a2a3f | 958 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
959 | { |
960 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
961 | |
962 | trace_kvm_eoi(apic, vector); | |
963 | ||
97222cc8 ED |
964 | /* |
965 | * Not every write EOI will has corresponding ISR, | |
966 | * one example is when Kernel check timer on setup_IO_APIC | |
967 | */ | |
968 | if (vector == -1) | |
ae7a2a3f | 969 | return vector; |
97222cc8 | 970 | |
8680b94b | 971 | apic_clear_isr(vector, apic); |
97222cc8 ED |
972 | apic_update_ppr(apic); |
973 | ||
5c919412 AS |
974 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
975 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
976 | ||
c7c9c56c | 977 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 978 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 979 | return vector; |
97222cc8 ED |
980 | } |
981 | ||
c7c9c56c YZ |
982 | /* |
983 | * this interface assumes a trap-like exit, which has already finished | |
984 | * desired side effect including vISR and vPPR update. | |
985 | */ | |
986 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
987 | { | |
988 | struct kvm_lapic *apic = vcpu->arch.apic; | |
989 | ||
990 | trace_kvm_eoi(apic, vector); | |
991 | ||
992 | kvm_ioapic_send_eoi(apic, vector); | |
993 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
994 | } | |
995 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
996 | ||
97222cc8 ED |
997 | static void apic_send_ipi(struct kvm_lapic *apic) |
998 | { | |
c48f1496 GN |
999 | u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); |
1000 | u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1001 | struct kvm_lapic_irq irq; |
97222cc8 | 1002 | |
58c2dde1 GN |
1003 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1004 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1005 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1006 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1007 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1008 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1009 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1010 | if (apic_x2apic_mode(apic)) |
1011 | irq.dest_id = icr_high; | |
1012 | else | |
1013 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1014 | |
1000ff8d GN |
1015 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1016 | ||
97222cc8 ED |
1017 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1018 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1019 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1020 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1021 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1022 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1023 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1024 | |
b4f2225c | 1025 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1026 | } |
1027 | ||
1028 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1029 | { | |
b682b814 MT |
1030 | ktime_t remaining; |
1031 | s64 ns; | |
9da8f4e8 | 1032 | u32 tmcct; |
97222cc8 ED |
1033 | |
1034 | ASSERT(apic != NULL); | |
1035 | ||
9da8f4e8 | 1036 | /* if initial count is 0, current count should also be 0 */ |
b963a22e AH |
1037 | if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 || |
1038 | apic->lapic_timer.period == 0) | |
9da8f4e8 KP |
1039 | return 0; |
1040 | ||
ace15464 | 1041 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
1042 | if (ktime_to_ns(remaining) < 0) |
1043 | remaining = ktime_set(0, 0); | |
1044 | ||
d3c7b77d MT |
1045 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1046 | tmcct = div64_u64(ns, | |
1047 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1048 | |
1049 | return tmcct; | |
1050 | } | |
1051 | ||
b209749f AK |
1052 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1053 | { | |
1054 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1055 | struct kvm_run *run = vcpu->run; | |
1056 | ||
a8eeb04a | 1057 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1058 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1059 | run->tpr_access.is_write = write; |
1060 | } | |
1061 | ||
1062 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1063 | { | |
1064 | if (apic->vcpu->arch.tpr_access_reporting) | |
1065 | __report_tpr_access(apic, write); | |
1066 | } | |
1067 | ||
97222cc8 ED |
1068 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1069 | { | |
1070 | u32 val = 0; | |
1071 | ||
1072 | if (offset >= LAPIC_MMIO_LENGTH) | |
1073 | return 0; | |
1074 | ||
1075 | switch (offset) { | |
0105d1a5 GN |
1076 | case APIC_ID: |
1077 | if (apic_x2apic_mode(apic)) | |
1078 | val = kvm_apic_id(apic); | |
1079 | else | |
1080 | val = kvm_apic_id(apic) << 24; | |
1081 | break; | |
97222cc8 | 1082 | case APIC_ARBPRI: |
7712de87 | 1083 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1084 | break; |
1085 | ||
1086 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1087 | if (apic_lvtt_tscdeadline(apic)) |
1088 | return 0; | |
1089 | ||
97222cc8 ED |
1090 | val = apic_get_tmcct(apic); |
1091 | break; | |
4a4541a4 AK |
1092 | case APIC_PROCPRI: |
1093 | apic_update_ppr(apic); | |
c48f1496 | 1094 | val = kvm_apic_get_reg(apic, offset); |
4a4541a4 | 1095 | break; |
b209749f AK |
1096 | case APIC_TASKPRI: |
1097 | report_tpr_access(apic, false); | |
1098 | /* fall thru */ | |
97222cc8 | 1099 | default: |
c48f1496 | 1100 | val = kvm_apic_get_reg(apic, offset); |
97222cc8 ED |
1101 | break; |
1102 | } | |
1103 | ||
1104 | return val; | |
1105 | } | |
1106 | ||
d76685c4 GH |
1107 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1108 | { | |
1109 | return container_of(dev, struct kvm_lapic, dev); | |
1110 | } | |
1111 | ||
0105d1a5 GN |
1112 | static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
1113 | void *data) | |
97222cc8 | 1114 | { |
97222cc8 ED |
1115 | unsigned char alignment = offset & 0xf; |
1116 | u32 result; | |
d5b0b5b1 | 1117 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1118 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1119 | |
1120 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1121 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1122 | offset, len); | |
0105d1a5 | 1123 | return 1; |
97222cc8 | 1124 | } |
0105d1a5 GN |
1125 | |
1126 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1127 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1128 | offset); | |
0105d1a5 GN |
1129 | return 1; |
1130 | } | |
1131 | ||
97222cc8 ED |
1132 | result = __apic_read(apic, offset & ~0xf); |
1133 | ||
229456fc MT |
1134 | trace_kvm_apic_read(offset, result); |
1135 | ||
97222cc8 ED |
1136 | switch (len) { |
1137 | case 1: | |
1138 | case 2: | |
1139 | case 4: | |
1140 | memcpy(data, (char *)&result + alignment, len); | |
1141 | break; | |
1142 | default: | |
1143 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1144 | "should be 1,2, or 4 instead\n", len); | |
1145 | break; | |
1146 | } | |
bda9020e | 1147 | return 0; |
97222cc8 ED |
1148 | } |
1149 | ||
0105d1a5 GN |
1150 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1151 | { | |
c48f1496 | 1152 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1153 | addr >= apic->base_address && |
1154 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1155 | } | |
1156 | ||
e32edf4f | 1157 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1158 | gpa_t address, int len, void *data) |
1159 | { | |
1160 | struct kvm_lapic *apic = to_lapic(this); | |
1161 | u32 offset = address - apic->base_address; | |
1162 | ||
1163 | if (!apic_mmio_in_range(apic, address)) | |
1164 | return -EOPNOTSUPP; | |
1165 | ||
1166 | apic_reg_read(apic, offset, len, data); | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
97222cc8 ED |
1171 | static void update_divide_count(struct kvm_lapic *apic) |
1172 | { | |
1173 | u32 tmp1, tmp2, tdcr; | |
1174 | ||
c48f1496 | 1175 | tdcr = kvm_apic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1176 | tmp1 = tdcr & 0xf; |
1177 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1178 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1179 | |
1180 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1181 | apic->divide_count); |
97222cc8 ED |
1182 | } |
1183 | ||
b6ac0695 RK |
1184 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1185 | { | |
1186 | u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) & | |
1187 | apic->lapic_timer.timer_mode_mask; | |
1188 | ||
1189 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1190 | apic->lapic_timer.timer_mode = timer_mode; | |
1191 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1192 | } | |
1193 | } | |
1194 | ||
5d87db71 RK |
1195 | static void apic_timer_expired(struct kvm_lapic *apic) |
1196 | { | |
1197 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1198 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1199 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1200 | |
5d87db71 RK |
1201 | if (atomic_read(&apic->lapic_timer.pending)) |
1202 | return; | |
1203 | ||
1204 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1205 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1206 | |
8577370f MT |
1207 | if (swait_active(q)) |
1208 | swake_up(q); | |
d0659d94 MT |
1209 | |
1210 | if (apic_lvtt_tscdeadline(apic)) | |
1211 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * On APICv, this test will cause a busy wait | |
1216 | * during a higher-priority task. | |
1217 | */ | |
1218 | ||
1219 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1220 | { | |
1221 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1222 | u32 reg = kvm_apic_get_reg(apic, APIC_LVTT); | |
1223 | ||
1224 | if (kvm_apic_hw_enabled(apic)) { | |
1225 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1226 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1227 | |
d62caabb | 1228 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1229 | bitmap = apic->regs + APIC_IRR; |
1230 | ||
1231 | if (apic_test_vector(vec, bitmap)) | |
1232 | return true; | |
d0659d94 MT |
1233 | } |
1234 | return false; | |
1235 | } | |
1236 | ||
1237 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1238 | { | |
1239 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1240 | u64 guest_tsc, tsc_deadline; | |
1241 | ||
1242 | if (!kvm_vcpu_has_lapic(vcpu)) | |
1243 | return; | |
1244 | ||
1245 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1246 | return; | |
1247 | ||
1248 | if (!lapic_timer_int_injected(vcpu)) | |
1249 | return; | |
1250 | ||
1251 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1252 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1253 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1254 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1255 | |
1256 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1257 | if (guest_tsc < tsc_deadline) | |
1258 | __delay(tsc_deadline - guest_tsc); | |
5d87db71 RK |
1259 | } |
1260 | ||
97222cc8 ED |
1261 | static void start_apic_timer(struct kvm_lapic *apic) |
1262 | { | |
a3e06bbe | 1263 | ktime_t now; |
d0659d94 | 1264 | |
d3c7b77d | 1265 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1266 | |
a3e06bbe | 1267 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1268 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1269 | now = apic->lapic_timer.timer.base->get_time(); |
c48f1496 | 1270 | apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1271 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1272 | ||
1273 | if (!apic->lapic_timer.period) | |
1274 | return; | |
1275 | /* | |
1276 | * Do not allow the guest to program periodic timers with small | |
1277 | * interval, since the hrtimers are not throttled by the host | |
1278 | * scheduler. | |
1279 | */ | |
1280 | if (apic_lvtt_period(apic)) { | |
1281 | s64 min_period = min_timer_period_us * 1000LL; | |
1282 | ||
1283 | if (apic->lapic_timer.period < min_period) { | |
1284 | pr_info_ratelimited( | |
1285 | "kvm: vcpu %i: requested %lld ns " | |
1286 | "lapic timer period limited to %lld ns\n", | |
1287 | apic->vcpu->vcpu_id, | |
1288 | apic->lapic_timer.period, min_period); | |
1289 | apic->lapic_timer.period = min_period; | |
1290 | } | |
9bc5791d | 1291 | } |
0b975a3c | 1292 | |
a3e06bbe LJ |
1293 | hrtimer_start(&apic->lapic_timer.timer, |
1294 | ktime_add_ns(now, apic->lapic_timer.period), | |
1295 | HRTIMER_MODE_ABS); | |
97222cc8 | 1296 | |
a3e06bbe | 1297 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1298 | PRIx64 ", " |
1299 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1300 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1301 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
c48f1496 | 1302 | kvm_apic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1303 | apic->lapic_timer.period, |
97222cc8 | 1304 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1305 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1306 | } else if (apic_lvtt_tscdeadline(apic)) { |
1307 | /* lapic timer in tsc deadline mode */ | |
1308 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1309 | u64 ns = 0; | |
d0659d94 | 1310 | ktime_t expire; |
a3e06bbe | 1311 | struct kvm_vcpu *vcpu = apic->vcpu; |
cc578287 | 1312 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1313 | unsigned long flags; |
1314 | ||
1315 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1316 | return; | |
1317 | ||
1318 | local_irq_save(flags); | |
1319 | ||
1320 | now = apic->lapic_timer.timer.base->get_time(); | |
4ba76538 | 1321 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
a3e06bbe LJ |
1322 | if (likely(tscdeadline > guest_tsc)) { |
1323 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1324 | do_div(ns, this_tsc_khz); | |
d0659d94 MT |
1325 | expire = ktime_add_ns(now, ns); |
1326 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1e0ad70c | 1327 | hrtimer_start(&apic->lapic_timer.timer, |
d0659d94 | 1328 | expire, HRTIMER_MODE_ABS); |
1e0ad70c RK |
1329 | } else |
1330 | apic_timer_expired(apic); | |
a3e06bbe LJ |
1331 | |
1332 | local_irq_restore(flags); | |
1333 | } | |
97222cc8 ED |
1334 | } |
1335 | ||
cc6e462c JK |
1336 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1337 | { | |
59fd1323 | 1338 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1339 | |
59fd1323 RK |
1340 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1341 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1342 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1343 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1344 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1345 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1346 | } else |
1347 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1348 | } | |
cc6e462c JK |
1349 | } |
1350 | ||
0105d1a5 | 1351 | static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1352 | { |
0105d1a5 | 1353 | int ret = 0; |
97222cc8 | 1354 | |
0105d1a5 | 1355 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1356 | |
0105d1a5 | 1357 | switch (reg) { |
97222cc8 | 1358 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1359 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1360 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1361 | else |
1362 | ret = 1; | |
97222cc8 ED |
1363 | break; |
1364 | ||
1365 | case APIC_TASKPRI: | |
b209749f | 1366 | report_tpr_access(apic, true); |
97222cc8 ED |
1367 | apic_set_tpr(apic, val & 0xff); |
1368 | break; | |
1369 | ||
1370 | case APIC_EOI: | |
1371 | apic_set_eoi(apic); | |
1372 | break; | |
1373 | ||
1374 | case APIC_LDR: | |
0105d1a5 | 1375 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1376 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1377 | else |
1378 | ret = 1; | |
97222cc8 ED |
1379 | break; |
1380 | ||
1381 | case APIC_DFR: | |
1e08ec4a | 1382 | if (!apic_x2apic_mode(apic)) { |
0105d1a5 | 1383 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1384 | recalculate_apic_map(apic->vcpu->kvm); |
1385 | } else | |
0105d1a5 | 1386 | ret = 1; |
97222cc8 ED |
1387 | break; |
1388 | ||
fc61b800 GN |
1389 | case APIC_SPIV: { |
1390 | u32 mask = 0x3ff; | |
c48f1496 | 1391 | if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1392 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1393 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1394 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1395 | int i; | |
1396 | u32 lvt_val; | |
1397 | ||
1398 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
c48f1496 | 1399 | lvt_val = kvm_apic_get_reg(apic, |
97222cc8 ED |
1400 | APIC_LVTT + 0x10 * i); |
1401 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
1402 | lvt_val | APIC_LVT_MASKED); | |
1403 | } | |
b6ac0695 | 1404 | apic_update_lvtt(apic); |
d3c7b77d | 1405 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1406 | |
1407 | } | |
1408 | break; | |
fc61b800 | 1409 | } |
97222cc8 ED |
1410 | case APIC_ICR: |
1411 | /* No delay here, so we always clear the pending bit */ | |
1412 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
1413 | apic_send_ipi(apic); | |
1414 | break; | |
1415 | ||
1416 | case APIC_ICR2: | |
0105d1a5 GN |
1417 | if (!apic_x2apic_mode(apic)) |
1418 | val &= 0xff000000; | |
1419 | apic_set_reg(apic, APIC_ICR2, val); | |
97222cc8 ED |
1420 | break; |
1421 | ||
23930f95 | 1422 | case APIC_LVT0: |
cc6e462c | 1423 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1424 | case APIC_LVTTHMR: |
1425 | case APIC_LVTPC: | |
97222cc8 ED |
1426 | case APIC_LVT1: |
1427 | case APIC_LVTERR: | |
1428 | /* TODO: Check vector */ | |
c48f1496 | 1429 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1430 | val |= APIC_LVT_MASKED; |
1431 | ||
0105d1a5 GN |
1432 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1433 | apic_set_reg(apic, reg, val); | |
97222cc8 ED |
1434 | |
1435 | break; | |
1436 | ||
b6ac0695 | 1437 | case APIC_LVTT: |
c48f1496 | 1438 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1439 | val |= APIC_LVT_MASKED; |
1440 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1441 | apic_set_reg(apic, APIC_LVTT, val); | |
b6ac0695 | 1442 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1443 | break; |
1444 | ||
97222cc8 | 1445 | case APIC_TMICT: |
a3e06bbe LJ |
1446 | if (apic_lvtt_tscdeadline(apic)) |
1447 | break; | |
1448 | ||
d3c7b77d | 1449 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 ED |
1450 | apic_set_reg(apic, APIC_TMICT, val); |
1451 | start_apic_timer(apic); | |
0105d1a5 | 1452 | break; |
97222cc8 ED |
1453 | |
1454 | case APIC_TDCR: | |
1455 | if (val & 4) | |
7712de87 | 1456 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
97222cc8 ED |
1457 | apic_set_reg(apic, APIC_TDCR, val); |
1458 | update_divide_count(apic); | |
1459 | break; | |
1460 | ||
0105d1a5 GN |
1461 | case APIC_ESR: |
1462 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1463 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1464 | ret = 1; |
1465 | } | |
1466 | break; | |
1467 | ||
1468 | case APIC_SELF_IPI: | |
1469 | if (apic_x2apic_mode(apic)) { | |
1470 | apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); | |
1471 | } else | |
1472 | ret = 1; | |
1473 | break; | |
97222cc8 | 1474 | default: |
0105d1a5 | 1475 | ret = 1; |
97222cc8 ED |
1476 | break; |
1477 | } | |
0105d1a5 GN |
1478 | if (ret) |
1479 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1480 | return ret; | |
1481 | } | |
1482 | ||
e32edf4f | 1483 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1484 | gpa_t address, int len, const void *data) |
1485 | { | |
1486 | struct kvm_lapic *apic = to_lapic(this); | |
1487 | unsigned int offset = address - apic->base_address; | |
1488 | u32 val; | |
1489 | ||
1490 | if (!apic_mmio_in_range(apic, address)) | |
1491 | return -EOPNOTSUPP; | |
1492 | ||
1493 | /* | |
1494 | * APIC register must be aligned on 128-bits boundary. | |
1495 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1496 | * Refer SDM 8.4.1 | |
1497 | */ | |
1498 | if (len != 4 || (offset & 0xf)) { | |
1499 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1500 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1501 | return 0; |
0105d1a5 GN |
1502 | } |
1503 | ||
1504 | val = *(u32*)data; | |
1505 | ||
1506 | /* too common printing */ | |
1507 | if (offset != APIC_EOI) | |
1508 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1509 | "0x%x\n", __func__, offset, len, val); | |
1510 | ||
1511 | apic_reg_write(apic, offset & 0xff0, val); | |
1512 | ||
bda9020e | 1513 | return 0; |
97222cc8 ED |
1514 | } |
1515 | ||
58fbbf26 KT |
1516 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1517 | { | |
c48f1496 | 1518 | if (kvm_vcpu_has_lapic(vcpu)) |
58fbbf26 KT |
1519 | apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
1520 | } | |
1521 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1522 | ||
83d4c286 YZ |
1523 | /* emulate APIC access in a trap manner */ |
1524 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1525 | { | |
1526 | u32 val = 0; | |
1527 | ||
1528 | /* hw has done the conditional check and inst decode */ | |
1529 | offset &= 0xff0; | |
1530 | ||
1531 | apic_reg_read(vcpu->arch.apic, offset, 4, &val); | |
1532 | ||
1533 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1534 | apic_reg_write(vcpu->arch.apic, offset, val); | |
1535 | } | |
1536 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1537 | ||
d589444e | 1538 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1539 | { |
f8c1ea10 GN |
1540 | struct kvm_lapic *apic = vcpu->arch.apic; |
1541 | ||
ad312c7c | 1542 | if (!vcpu->arch.apic) |
97222cc8 ED |
1543 | return; |
1544 | ||
f8c1ea10 | 1545 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1546 | |
c5cc421b GN |
1547 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1548 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1549 | ||
e462755c | 1550 | if (!apic->sw_enabled) |
f8c1ea10 | 1551 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1552 | |
f8c1ea10 GN |
1553 | if (apic->regs) |
1554 | free_page((unsigned long)apic->regs); | |
1555 | ||
1556 | kfree(apic); | |
97222cc8 ED |
1557 | } |
1558 | ||
1559 | /* | |
1560 | *---------------------------------------------------------------------- | |
1561 | * LAPIC interface | |
1562 | *---------------------------------------------------------------------- | |
1563 | */ | |
1564 | ||
a3e06bbe LJ |
1565 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1566 | { | |
1567 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1568 | |
c48f1496 | 1569 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1570 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1571 | return 0; |
1572 | ||
1573 | return apic->lapic_timer.tscdeadline; | |
1574 | } | |
1575 | ||
1576 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1577 | { | |
1578 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1579 | |
c48f1496 | 1580 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1581 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1582 | return; |
1583 | ||
1584 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1585 | apic->lapic_timer.tscdeadline = data; | |
1586 | start_apic_timer(apic); | |
1587 | } | |
1588 | ||
97222cc8 ED |
1589 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1590 | { | |
ad312c7c | 1591 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1592 | |
c48f1496 | 1593 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1594 | return; |
54e9818f | 1595 | |
b93463aa | 1596 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
c48f1496 | 1597 | | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1598 | } |
1599 | ||
1600 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1601 | { | |
97222cc8 ED |
1602 | u64 tpr; |
1603 | ||
c48f1496 | 1604 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1605 | return 0; |
54e9818f | 1606 | |
c48f1496 | 1607 | tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1608 | |
1609 | return (tpr & 0xf0) >> 4; | |
1610 | } | |
1611 | ||
1612 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1613 | { | |
8d14695f | 1614 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1615 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1616 | |
1617 | if (!apic) { | |
1618 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1619 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1620 | return; |
1621 | } | |
c5af89b6 | 1622 | |
e66d2ae7 JK |
1623 | vcpu->arch.apic_base = value; |
1624 | ||
c5cc421b | 1625 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1626 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1627 | if (value & MSR_IA32_APICBASE_ENABLE) |
1628 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1629 | else | |
1630 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1631 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1632 | } |
1633 | ||
8d14695f YZ |
1634 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1635 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1636 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1637 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1638 | } else | |
1639 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1640 | } |
8d14695f | 1641 | |
ad312c7c | 1642 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1643 | MSR_IA32_APICBASE_BASE; |
1644 | ||
db324fe6 NA |
1645 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1646 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1647 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1648 | ||
97222cc8 ED |
1649 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1650 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1651 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1652 | |
1653 | } | |
1654 | ||
d28bc9dd | 1655 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
1656 | { |
1657 | struct kvm_lapic *apic; | |
1658 | int i; | |
1659 | ||
b8688d51 | 1660 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1661 | |
1662 | ASSERT(vcpu); | |
ad312c7c | 1663 | apic = vcpu->arch.apic; |
97222cc8 ED |
1664 | ASSERT(apic != NULL); |
1665 | ||
1666 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1667 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1668 | |
d28bc9dd NA |
1669 | if (!init_event) |
1670 | kvm_apic_set_id(apic, vcpu->vcpu_id); | |
fc61b800 | 1671 | kvm_apic_set_version(apic->vcpu); |
97222cc8 ED |
1672 | |
1673 | for (i = 0; i < APIC_LVT_NUM; i++) | |
1674 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 1675 | apic_update_lvtt(apic); |
0da029ed | 1676 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) |
90de4a18 NA |
1677 | apic_set_reg(apic, APIC_LVT0, |
1678 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
59fd1323 | 1679 | apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0)); |
97222cc8 ED |
1680 | |
1681 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
f8c1ea10 | 1682 | apic_set_spiv(apic, 0xff); |
97222cc8 | 1683 | apic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
1684 | if (!apic_x2apic_mode(apic)) |
1685 | kvm_apic_set_ldr(apic, 0); | |
97222cc8 ED |
1686 | apic_set_reg(apic, APIC_ESR, 0); |
1687 | apic_set_reg(apic, APIC_ICR, 0); | |
1688 | apic_set_reg(apic, APIC_ICR2, 0); | |
1689 | apic_set_reg(apic, APIC_TDCR, 0); | |
1690 | apic_set_reg(apic, APIC_TMICT, 0); | |
1691 | for (i = 0; i < 8; i++) { | |
1692 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
1693 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1694 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
1695 | } | |
d62caabb AS |
1696 | apic->irr_pending = vcpu->arch.apicv_active; |
1697 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 1698 | apic->highest_isr_cache = -1; |
b33ac88b | 1699 | update_divide_count(apic); |
d3c7b77d | 1700 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1701 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1702 | kvm_lapic_set_base(vcpu, |
1703 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1704 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1705 | apic_update_ppr(apic); |
1706 | ||
e1035715 | 1707 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1708 | vcpu->arch.apic_attention = 0; |
e1035715 | 1709 | |
98eff52a | 1710 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1711 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1712 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1713 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1714 | } |
1715 | ||
97222cc8 ED |
1716 | /* |
1717 | *---------------------------------------------------------------------- | |
1718 | * timer interface | |
1719 | *---------------------------------------------------------------------- | |
1720 | */ | |
1b9778da | 1721 | |
2a6eac96 | 1722 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1723 | { |
d3c7b77d | 1724 | return apic_lvtt_period(apic); |
97222cc8 ED |
1725 | } |
1726 | ||
3d80840d MT |
1727 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1728 | { | |
54e9818f | 1729 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1730 | |
c48f1496 | 1731 | if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && |
54e9818f GN |
1732 | apic_lvt_enabled(apic, APIC_LVTT)) |
1733 | return atomic_read(&apic->lapic_timer.pending); | |
3d80840d MT |
1734 | |
1735 | return 0; | |
1736 | } | |
1737 | ||
89342082 | 1738 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1739 | { |
c48f1496 | 1740 | u32 reg = kvm_apic_get_reg(apic, lvt_type); |
23930f95 | 1741 | int vector, mode, trig_mode; |
23930f95 | 1742 | |
c48f1496 | 1743 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1744 | vector = reg & APIC_VECTOR_MASK; |
1745 | mode = reg & APIC_MODE_MASK; | |
1746 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1747 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1748 | NULL); | |
23930f95 JK |
1749 | } |
1750 | return 0; | |
1751 | } | |
1b9778da | 1752 | |
8fdb2351 | 1753 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1754 | { |
8fdb2351 JK |
1755 | struct kvm_lapic *apic = vcpu->arch.apic; |
1756 | ||
1757 | if (apic) | |
1758 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1759 | } |
1760 | ||
d76685c4 GH |
1761 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1762 | .read = apic_mmio_read, | |
1763 | .write = apic_mmio_write, | |
d76685c4 GH |
1764 | }; |
1765 | ||
e9d90d47 AK |
1766 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1767 | { | |
1768 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1769 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1770 | |
5d87db71 | 1771 | apic_timer_expired(apic); |
e9d90d47 | 1772 | |
2a6eac96 | 1773 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1774 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1775 | return HRTIMER_RESTART; | |
1776 | } else | |
1777 | return HRTIMER_NORESTART; | |
1778 | } | |
1779 | ||
97222cc8 ED |
1780 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1781 | { | |
1782 | struct kvm_lapic *apic; | |
1783 | ||
1784 | ASSERT(vcpu != NULL); | |
1785 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1786 | ||
1787 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1788 | if (!apic) | |
1789 | goto nomem; | |
1790 | ||
ad312c7c | 1791 | vcpu->arch.apic = apic; |
97222cc8 | 1792 | |
afc20184 TY |
1793 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1794 | if (!apic->regs) { | |
97222cc8 ED |
1795 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1796 | vcpu->vcpu_id); | |
d589444e | 1797 | goto nomem_free_apic; |
97222cc8 | 1798 | } |
97222cc8 ED |
1799 | apic->vcpu = vcpu; |
1800 | ||
d3c7b77d MT |
1801 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
1802 | HRTIMER_MODE_ABS); | |
e9d90d47 | 1803 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1804 | |
c5cc421b GN |
1805 | /* |
1806 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1807 | * thinking that APIC satet has changed. | |
1808 | */ | |
1809 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1810 | kvm_lapic_set_base(vcpu, |
1811 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1812 | |
f8c1ea10 | 1813 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d28bc9dd | 1814 | kvm_lapic_reset(vcpu, false); |
d76685c4 | 1815 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1816 | |
1817 | return 0; | |
d589444e RR |
1818 | nomem_free_apic: |
1819 | kfree(apic); | |
97222cc8 | 1820 | nomem: |
97222cc8 ED |
1821 | return -ENOMEM; |
1822 | } | |
97222cc8 ED |
1823 | |
1824 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1825 | { | |
ad312c7c | 1826 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1827 | int highest_irr; |
1828 | ||
c48f1496 | 1829 | if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) |
97222cc8 ED |
1830 | return -1; |
1831 | ||
6e5d865c | 1832 | apic_update_ppr(apic); |
97222cc8 ED |
1833 | highest_irr = apic_find_highest_irr(apic); |
1834 | if ((highest_irr == -1) || | |
c48f1496 | 1835 | ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1836 | return -1; |
1837 | return highest_irr; | |
1838 | } | |
1839 | ||
40487c68 QH |
1840 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1841 | { | |
c48f1496 | 1842 | u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1843 | int r = 0; |
1844 | ||
c48f1496 | 1845 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1846 | r = 1; |
1847 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1848 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1849 | r = 1; | |
40487c68 QH |
1850 | return r; |
1851 | } | |
1852 | ||
1b9778da ED |
1853 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1854 | { | |
ad312c7c | 1855 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1856 | |
c48f1496 | 1857 | if (!kvm_vcpu_has_lapic(vcpu)) |
54e9818f GN |
1858 | return; |
1859 | ||
1860 | if (atomic_read(&apic->lapic_timer.pending) > 0) { | |
f1ed0450 | 1861 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1862 | if (apic_lvtt_tscdeadline(apic)) |
1863 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1864 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1865 | } |
1866 | } | |
1867 | ||
97222cc8 ED |
1868 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1869 | { | |
1870 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1871 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1872 | |
1873 | if (vector == -1) | |
1874 | return -1; | |
1875 | ||
56cc2406 WL |
1876 | /* |
1877 | * We get here even with APIC virtualization enabled, if doing | |
1878 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1879 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1880 | * because the process would deliver it through the IDT. | |
1881 | */ | |
1882 | ||
8680b94b | 1883 | apic_set_isr(vector, apic); |
97222cc8 ED |
1884 | apic_update_ppr(apic); |
1885 | apic_clear_irr(vector, apic); | |
5c919412 AS |
1886 | |
1887 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { | |
1888 | apic_clear_isr(vector, apic); | |
1889 | apic_update_ppr(apic); | |
1890 | } | |
1891 | ||
97222cc8 ED |
1892 | return vector; |
1893 | } | |
96ad2cc6 | 1894 | |
64eb0620 GN |
1895 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1896 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1897 | { |
ad312c7c | 1898 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1899 | |
5dbc8f3f | 1900 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1901 | /* set SPIV separately to get count of SW disabled APICs right */ |
1902 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1903 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1904 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1905 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1906 | kvm_apic_set_version(vcpu); |
1907 | ||
96ad2cc6 | 1908 | apic_update_ppr(apic); |
d3c7b77d | 1909 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 1910 | apic_update_lvtt(apic); |
db138562 | 1911 | apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
1912 | update_divide_count(apic); |
1913 | start_apic_timer(apic); | |
6e24a6ef | 1914 | apic->irr_pending = true; |
d62caabb | 1915 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 1916 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 1917 | apic->highest_isr_cache = -1; |
d62caabb | 1918 | if (vcpu->arch.apicv_active) { |
4114c27d WW |
1919 | kvm_x86_ops->hwapic_irr_update(vcpu, |
1920 | apic_find_highest_irr(apic)); | |
b4eef9b3 TC |
1921 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, |
1922 | apic_find_highest_isr(apic)); | |
d62caabb | 1923 | } |
3842d135 | 1924 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
1925 | if (ioapic_in_kernel(vcpu->kvm)) |
1926 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
1927 | |
1928 | vcpu->arch.apic_arb_prio = 0; | |
96ad2cc6 | 1929 | } |
a3d7f85f | 1930 | |
2f52d58c | 1931 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1932 | { |
a3d7f85f ED |
1933 | struct hrtimer *timer; |
1934 | ||
c48f1496 | 1935 | if (!kvm_vcpu_has_lapic(vcpu)) |
a3d7f85f ED |
1936 | return; |
1937 | ||
54e9818f | 1938 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1939 | if (hrtimer_cancel(timer)) |
beb20d52 | 1940 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1941 | } |
b93463aa | 1942 | |
ae7a2a3f MT |
1943 | /* |
1944 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1945 | * | |
1946 | * Detect whether guest triggered PV EOI since the | |
1947 | * last entry. If yes, set EOI on guests's behalf. | |
1948 | * Clear PV EOI in guest memory in any case. | |
1949 | */ | |
1950 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1951 | struct kvm_lapic *apic) | |
1952 | { | |
1953 | bool pending; | |
1954 | int vector; | |
1955 | /* | |
1956 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
1957 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
1958 | * | |
1959 | * KVM_APIC_PV_EOI_PENDING is unset: | |
1960 | * -> host disabled PV EOI. | |
1961 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
1962 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
1963 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
1964 | * -> host enabled PV EOI, guest executed EOI. | |
1965 | */ | |
1966 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
1967 | pending = pv_eoi_get_pending(vcpu); | |
1968 | /* | |
1969 | * Clear pending bit in any case: it will be set again on vmentry. | |
1970 | * While this might not be ideal from performance point of view, | |
1971 | * this makes sure pv eoi is only enabled when we know it's safe. | |
1972 | */ | |
1973 | pv_eoi_clr_pending(vcpu); | |
1974 | if (pending) | |
1975 | return; | |
1976 | vector = apic_set_eoi(apic); | |
1977 | trace_kvm_pv_eoi(apic, vector); | |
1978 | } | |
1979 | ||
b93463aa AK |
1980 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
1981 | { | |
1982 | u32 data; | |
b93463aa | 1983 | |
ae7a2a3f MT |
1984 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
1985 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
1986 | ||
41383771 | 1987 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1988 | return; |
1989 | ||
603242a8 NK |
1990 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
1991 | sizeof(u32))) | |
1992 | return; | |
b93463aa AK |
1993 | |
1994 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1995 | } | |
1996 | ||
ae7a2a3f MT |
1997 | /* |
1998 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
1999 | * | |
2000 | * Detect whether it's safe to enable PV EOI and | |
2001 | * if yes do so. | |
2002 | */ | |
2003 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2004 | struct kvm_lapic *apic) | |
2005 | { | |
2006 | if (!pv_eoi_enabled(vcpu) || | |
2007 | /* IRR set or many bits in ISR: could be nested. */ | |
2008 | apic->irr_pending || | |
2009 | /* Cache not set: could be safe but we don't bother. */ | |
2010 | apic->highest_isr_cache == -1 || | |
2011 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2012 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2013 | /* |
2014 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2015 | * so we need not do anything here. | |
2016 | */ | |
2017 | return; | |
2018 | } | |
2019 | ||
2020 | pv_eoi_set_pending(apic->vcpu); | |
2021 | } | |
2022 | ||
b93463aa AK |
2023 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2024 | { | |
2025 | u32 data, tpr; | |
2026 | int max_irr, max_isr; | |
ae7a2a3f | 2027 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2028 | |
ae7a2a3f MT |
2029 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2030 | ||
41383771 | 2031 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2032 | return; |
2033 | ||
c48f1496 | 2034 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2035 | max_irr = apic_find_highest_irr(apic); |
2036 | if (max_irr < 0) | |
2037 | max_irr = 0; | |
2038 | max_isr = apic_find_highest_isr(apic); | |
2039 | if (max_isr < 0) | |
2040 | max_isr = 0; | |
2041 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2042 | ||
fda4e2e8 AH |
2043 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2044 | sizeof(u32)); | |
b93463aa AK |
2045 | } |
2046 | ||
fda4e2e8 | 2047 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2048 | { |
fda4e2e8 AH |
2049 | if (vapic_addr) { |
2050 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2051 | &vcpu->arch.apic->vapic_cache, | |
2052 | vapic_addr, sizeof(u32))) | |
2053 | return -EINVAL; | |
41383771 | 2054 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2055 | } else { |
41383771 | 2056 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2057 | } |
2058 | ||
2059 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2060 | return 0; | |
b93463aa | 2061 | } |
0105d1a5 GN |
2062 | |
2063 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2064 | { | |
2065 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2066 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2067 | ||
35754c98 | 2068 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2069 | return 1; |
2070 | ||
c69d3d9b NA |
2071 | if (reg == APIC_ICR2) |
2072 | return 1; | |
2073 | ||
0105d1a5 | 2074 | /* if this is ICR write vector before command */ |
decdc283 | 2075 | if (reg == APIC_ICR) |
0105d1a5 GN |
2076 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2077 | return apic_reg_write(apic, reg, (u32)data); | |
2078 | } | |
2079 | ||
2080 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2081 | { | |
2082 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2083 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2084 | ||
35754c98 | 2085 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2086 | return 1; |
2087 | ||
c69d3d9b NA |
2088 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2089 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2090 | reg); | |
2091 | return 1; | |
2092 | } | |
2093 | ||
0105d1a5 GN |
2094 | if (apic_reg_read(apic, reg, 4, &low)) |
2095 | return 1; | |
decdc283 | 2096 | if (reg == APIC_ICR) |
0105d1a5 GN |
2097 | apic_reg_read(apic, APIC_ICR2, 4, &high); |
2098 | ||
2099 | *data = (((u64)high) << 32) | low; | |
2100 | ||
2101 | return 0; | |
2102 | } | |
10388a07 GN |
2103 | |
2104 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2105 | { | |
2106 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2107 | ||
c48f1496 | 2108 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
2109 | return 1; |
2110 | ||
2111 | /* if this is ICR write vector before command */ | |
2112 | if (reg == APIC_ICR) | |
2113 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
2114 | return apic_reg_write(apic, reg, (u32)data); | |
2115 | } | |
2116 | ||
2117 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2118 | { | |
2119 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2120 | u32 low, high = 0; | |
2121 | ||
c48f1496 | 2122 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
2123 | return 1; |
2124 | ||
2125 | if (apic_reg_read(apic, reg, 4, &low)) | |
2126 | return 1; | |
2127 | if (reg == APIC_ICR) | |
2128 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
2129 | ||
2130 | *data = (((u64)high) << 32) | low; | |
2131 | ||
2132 | return 0; | |
2133 | } | |
ae7a2a3f MT |
2134 | |
2135 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2136 | { | |
2137 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2138 | if (!IS_ALIGNED(addr, 4)) | |
2139 | return 1; | |
2140 | ||
2141 | vcpu->arch.pv_eoi.msr_val = data; | |
2142 | if (!pv_eoi_enabled(vcpu)) | |
2143 | return 0; | |
2144 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2145 | addr, sizeof(u8)); |
ae7a2a3f | 2146 | } |
c5cc421b | 2147 | |
66450a21 JK |
2148 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2149 | { | |
2150 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2151 | u8 sipi_vector; |
299018f4 | 2152 | unsigned long pe; |
66450a21 | 2153 | |
299018f4 | 2154 | if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) |
66450a21 JK |
2155 | return; |
2156 | ||
cd7764fe PB |
2157 | /* |
2158 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2159 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2160 | * and delay processing of INIT until the next RSM. | |
2161 | */ | |
2162 | if (is_smm(vcpu)) { | |
2163 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2164 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2165 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2166 | return; | |
2167 | } | |
299018f4 | 2168 | |
cd7764fe | 2169 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2170 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2171 | kvm_lapic_reset(vcpu, true); |
2172 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2173 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2174 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2175 | else | |
2176 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2177 | } | |
299018f4 | 2178 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2179 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2180 | /* evaluate pending_events before reading the vector */ | |
2181 | smp_rmb(); | |
2182 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2183 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2184 | vcpu->vcpu_id, sipi_vector); |
2185 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2186 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2187 | } | |
2188 | } | |
2189 | ||
c5cc421b GN |
2190 | void kvm_lapic_init(void) |
2191 | { | |
2192 | /* do not patch jump label more than once per second */ | |
2193 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2194 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2195 | } |