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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
97222cc8 | 44 | |
b682b814 MT |
45 | #ifndef CONFIG_X86_64 |
46 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
47 | #else | |
48 | #define mod_64(x, y) ((x) % (y)) | |
49 | #endif | |
50 | ||
97222cc8 ED |
51 | #define PRId64 "d" |
52 | #define PRIx64 "llx" | |
53 | #define PRIu64 "u" | |
54 | #define PRIo64 "o" | |
55 | ||
56 | #define APIC_BUS_CYCLE_NS 1 | |
57 | ||
58 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
59 | #define apic_debug(fmt, arg...) | |
60 | ||
61 | #define APIC_LVT_NUM 6 | |
62 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
63 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
64 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
65 | /* followed define is not in apicdef.h */ | |
66 | #define APIC_SHORT_MASK 0xc0000 | |
67 | #define APIC_DEST_NOSHORT 0x0 | |
68 | #define APIC_DEST_MASK 0x800 | |
69 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 70 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 71 | |
394457a9 NA |
72 | #define APIC_BROADCAST 0xFF |
73 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
74 | ||
97222cc8 ED |
75 | #define VEC_POS(v) ((v) & (32 - 1)) |
76 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 77 | |
97222cc8 ED |
78 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
79 | { | |
80 | *((u32 *) (apic->regs + reg_off)) = val; | |
81 | } | |
82 | ||
a0c9a822 MT |
83 | static inline int apic_test_vector(int vec, void *bitmap) |
84 | { | |
85 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
86 | } | |
87 | ||
10606919 YZ |
88 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
89 | { | |
90 | struct kvm_lapic *apic = vcpu->arch.apic; | |
91 | ||
92 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
93 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
94 | } | |
95 | ||
97222cc8 ED |
96 | static inline void apic_set_vector(int vec, void *bitmap) |
97 | { | |
98 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
99 | } | |
100 | ||
101 | static inline void apic_clear_vector(int vec, void *bitmap) | |
102 | { | |
103 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
104 | } | |
105 | ||
8680b94b MT |
106 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
107 | { | |
108 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
109 | } | |
110 | ||
111 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
112 | { | |
113 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
114 | } | |
115 | ||
c5cc421b | 116 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
117 | struct static_key_deferred apic_sw_disabled __read_mostly; |
118 | ||
97222cc8 ED |
119 | static inline int apic_enabled(struct kvm_lapic *apic) |
120 | { | |
c48f1496 | 121 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
122 | } |
123 | ||
97222cc8 ED |
124 | #define LVT_MASK \ |
125 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
126 | ||
127 | #define LINT_MASK \ | |
128 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
129 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
130 | ||
131 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
132 | { | |
c48f1496 | 133 | return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; |
97222cc8 ED |
134 | } |
135 | ||
3548a259 RK |
136 | /* The logical map is definitely wrong if we have multiple |
137 | * modes at the same time. (Physical map is always right.) | |
138 | */ | |
139 | static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map) | |
140 | { | |
141 | return !(map->mode & (map->mode - 1)); | |
142 | } | |
143 | ||
3b5a5ffa RK |
144 | static inline void |
145 | apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid) | |
146 | { | |
147 | unsigned lid_bits; | |
148 | ||
149 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4); | |
150 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8); | |
151 | BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16); | |
152 | lid_bits = map->mode; | |
153 | ||
154 | *cid = dest_id >> lid_bits; | |
155 | *lid = dest_id & ((1 << lid_bits) - 1); | |
156 | } | |
157 | ||
1e08ec4a GN |
158 | static void recalculate_apic_map(struct kvm *kvm) |
159 | { | |
160 | struct kvm_apic_map *new, *old = NULL; | |
161 | struct kvm_vcpu *vcpu; | |
162 | int i; | |
163 | ||
164 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
165 | ||
166 | mutex_lock(&kvm->arch.apic_map_lock); | |
167 | ||
168 | if (!new) | |
169 | goto out; | |
170 | ||
173beedc NA |
171 | kvm_for_each_vcpu(i, vcpu, kvm) { |
172 | struct kvm_lapic *apic = vcpu->arch.apic; | |
173 | u16 cid, lid; | |
25995e5b | 174 | u32 ldr, aid; |
1e08ec4a | 175 | |
df04d1d1 RK |
176 | if (!kvm_apic_present(vcpu)) |
177 | continue; | |
178 | ||
25995e5b | 179 | aid = kvm_apic_id(apic); |
1e08ec4a | 180 | ldr = kvm_apic_get_reg(apic, APIC_LDR); |
1e08ec4a | 181 | |
25995e5b RK |
182 | if (aid < ARRAY_SIZE(new->phys_map)) |
183 | new->phys_map[aid] = apic; | |
3548a259 | 184 | |
3b5a5ffa RK |
185 | if (apic_x2apic_mode(apic)) { |
186 | new->mode |= KVM_APIC_MODE_X2APIC; | |
187 | } else if (ldr) { | |
188 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
189 | if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) | |
190 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; | |
191 | else | |
192 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
193 | } | |
194 | ||
195 | if (!kvm_apic_logical_map_valid(new)) | |
3548a259 RK |
196 | continue; |
197 | ||
3b5a5ffa RK |
198 | apic_logical_id(new, ldr, &cid, &lid); |
199 | ||
25995e5b | 200 | if (lid && cid < ARRAY_SIZE(new->logical_map)) |
1e08ec4a GN |
201 | new->logical_map[cid][ffs(lid) - 1] = apic; |
202 | } | |
203 | out: | |
204 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
205 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
206 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
207 | mutex_unlock(&kvm->arch.apic_map_lock); | |
208 | ||
209 | if (old) | |
210 | kfree_rcu(old, rcu); | |
c7c9c56c | 211 | |
3d81bc7e | 212 | kvm_vcpu_request_scan_ioapic(kvm); |
1e08ec4a GN |
213 | } |
214 | ||
1e1b6c26 NA |
215 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
216 | { | |
e462755c | 217 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 NA |
218 | |
219 | apic_set_reg(apic, APIC_SPIV, val); | |
e462755c RK |
220 | |
221 | if (enabled != apic->sw_enabled) { | |
222 | apic->sw_enabled = enabled; | |
223 | if (enabled) { | |
1e1b6c26 NA |
224 | static_key_slow_dec_deferred(&apic_sw_disabled); |
225 | recalculate_apic_map(apic->vcpu->kvm); | |
226 | } else | |
227 | static_key_slow_inc(&apic_sw_disabled.key); | |
228 | } | |
229 | } | |
230 | ||
1e08ec4a GN |
231 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
232 | { | |
233 | apic_set_reg(apic, APIC_ID, id << 24); | |
234 | recalculate_apic_map(apic->vcpu->kvm); | |
235 | } | |
236 | ||
237 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
238 | { | |
239 | apic_set_reg(apic, APIC_LDR, id); | |
240 | recalculate_apic_map(apic->vcpu->kvm); | |
241 | } | |
242 | ||
257b9a5f RK |
243 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id) |
244 | { | |
245 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
246 | ||
247 | apic_set_reg(apic, APIC_ID, id << 24); | |
248 | apic_set_reg(apic, APIC_LDR, ldr); | |
249 | recalculate_apic_map(apic->vcpu->kvm); | |
250 | } | |
251 | ||
97222cc8 ED |
252 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
253 | { | |
c48f1496 | 254 | return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
255 | } |
256 | ||
257 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
258 | { | |
c48f1496 | 259 | return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
260 | } |
261 | ||
a3e06bbe LJ |
262 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
263 | { | |
f30ebc31 | 264 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
265 | } |
266 | ||
97222cc8 ED |
267 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
268 | { | |
f30ebc31 | 269 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
270 | } |
271 | ||
272 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
273 | { | |
f30ebc31 | 274 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
275 | } |
276 | ||
cc6e462c JK |
277 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
278 | { | |
279 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
280 | } | |
281 | ||
fc61b800 GN |
282 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
283 | { | |
284 | struct kvm_lapic *apic = vcpu->arch.apic; | |
285 | struct kvm_cpuid_entry2 *feat; | |
286 | u32 v = APIC_VERSION; | |
287 | ||
c48f1496 | 288 | if (!kvm_vcpu_has_lapic(vcpu)) |
fc61b800 GN |
289 | return; |
290 | ||
291 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
292 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
293 | v |= APIC_LVR_DIRECTED_EOI; | |
294 | apic_set_reg(apic, APIC_LVR, v); | |
295 | } | |
296 | ||
f1d24831 | 297 | static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
a3e06bbe | 298 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
299 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
300 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
301 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
302 | LVT_MASK /* LVTERR */ | |
303 | }; | |
304 | ||
305 | static int find_highest_vector(void *bitmap) | |
306 | { | |
ecba9a52 TY |
307 | int vec; |
308 | u32 *reg; | |
97222cc8 | 309 | |
ecba9a52 TY |
310 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
311 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
312 | reg = bitmap + REG_POS(vec); | |
313 | if (*reg) | |
314 | return fls(*reg) - 1 + vec; | |
315 | } | |
97222cc8 | 316 | |
ecba9a52 | 317 | return -1; |
97222cc8 ED |
318 | } |
319 | ||
8680b94b MT |
320 | static u8 count_vectors(void *bitmap) |
321 | { | |
ecba9a52 TY |
322 | int vec; |
323 | u32 *reg; | |
8680b94b | 324 | u8 count = 0; |
ecba9a52 TY |
325 | |
326 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
327 | reg = bitmap + REG_POS(vec); | |
328 | count += hweight32(*reg); | |
329 | } | |
330 | ||
8680b94b MT |
331 | return count; |
332 | } | |
333 | ||
705699a1 | 334 | void __kvm_apic_update_irr(u32 *pir, void *regs) |
a20ed54d YZ |
335 | { |
336 | u32 i, pir_val; | |
a20ed54d YZ |
337 | |
338 | for (i = 0; i <= 7; i++) { | |
339 | pir_val = xchg(&pir[i], 0); | |
340 | if (pir_val) | |
705699a1 | 341 | *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val; |
a20ed54d YZ |
342 | } |
343 | } | |
705699a1 WV |
344 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
345 | ||
346 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) | |
347 | { | |
348 | struct kvm_lapic *apic = vcpu->arch.apic; | |
349 | ||
350 | __kvm_apic_update_irr(pir, apic->regs); | |
351 | } | |
a20ed54d YZ |
352 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
353 | ||
11f5cc05 | 354 | static inline void apic_set_irr(int vec, struct kvm_lapic *apic) |
97222cc8 | 355 | { |
11f5cc05 | 356 | apic_set_vector(vec, apic->regs + APIC_IRR); |
f210f757 NA |
357 | /* |
358 | * irr_pending must be true if any interrupt is pending; set it after | |
359 | * APIC_IRR to avoid race with apic_clear_irr | |
360 | */ | |
361 | apic->irr_pending = true; | |
97222cc8 ED |
362 | } |
363 | ||
33e4c686 | 364 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 365 | { |
33e4c686 | 366 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
367 | } |
368 | ||
369 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
370 | { | |
371 | int result; | |
372 | ||
c7c9c56c YZ |
373 | /* |
374 | * Note that irr_pending is just a hint. It will be always | |
375 | * true with virtual interrupt delivery enabled. | |
376 | */ | |
33e4c686 GN |
377 | if (!apic->irr_pending) |
378 | return -1; | |
379 | ||
5a71785d | 380 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); |
33e4c686 | 381 | result = apic_search_irr(apic); |
97222cc8 ED |
382 | ASSERT(result == -1 || result >= 16); |
383 | ||
384 | return result; | |
385 | } | |
386 | ||
33e4c686 GN |
387 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
388 | { | |
56cc2406 WL |
389 | struct kvm_vcpu *vcpu; |
390 | ||
391 | vcpu = apic->vcpu; | |
392 | ||
f210f757 | 393 | if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) { |
56cc2406 | 394 | /* try to update RVI */ |
f210f757 | 395 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 396 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
397 | } else { |
398 | apic->irr_pending = false; | |
399 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
400 | if (apic_search_irr(apic) != -1) | |
401 | apic->irr_pending = true; | |
56cc2406 | 402 | } |
33e4c686 GN |
403 | } |
404 | ||
8680b94b MT |
405 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
406 | { | |
56cc2406 WL |
407 | struct kvm_vcpu *vcpu; |
408 | ||
409 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
410 | return; | |
411 | ||
412 | vcpu = apic->vcpu; | |
fc57ac2c | 413 | |
8680b94b | 414 | /* |
56cc2406 WL |
415 | * With APIC virtualization enabled, all caching is disabled |
416 | * because the processor can modify ISR under the hood. Instead | |
417 | * just set SVI. | |
8680b94b | 418 | */ |
b4eef9b3 | 419 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
56cc2406 WL |
420 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec); |
421 | else { | |
422 | ++apic->isr_count; | |
423 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
424 | /* | |
425 | * ISR (in service register) bit is set when injecting an interrupt. | |
426 | * The highest vector is injected. Thus the latest bit set matches | |
427 | * the highest bit in ISR. | |
428 | */ | |
429 | apic->highest_isr_cache = vec; | |
430 | } | |
8680b94b MT |
431 | } |
432 | ||
fc57ac2c PB |
433 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
434 | { | |
435 | int result; | |
436 | ||
437 | /* | |
438 | * Note that isr_count is always 1, and highest_isr_cache | |
439 | * is always -1, with APIC virtualization enabled. | |
440 | */ | |
441 | if (!apic->isr_count) | |
442 | return -1; | |
443 | if (likely(apic->highest_isr_cache != -1)) | |
444 | return apic->highest_isr_cache; | |
445 | ||
446 | result = find_highest_vector(apic->regs + APIC_ISR); | |
447 | ASSERT(result == -1 || result >= 16); | |
448 | ||
449 | return result; | |
450 | } | |
451 | ||
8680b94b MT |
452 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
453 | { | |
fc57ac2c PB |
454 | struct kvm_vcpu *vcpu; |
455 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
456 | return; | |
457 | ||
458 | vcpu = apic->vcpu; | |
459 | ||
460 | /* | |
461 | * We do get here for APIC virtualization enabled if the guest | |
462 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
463 | * to trigger a new interrupt delivery by writing the SVI field; | |
464 | * on the other hand isr_count and highest_isr_cache are unused | |
465 | * and must be left alone. | |
466 | */ | |
b4eef9b3 | 467 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
fc57ac2c PB |
468 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, |
469 | apic_find_highest_isr(apic)); | |
470 | else { | |
8680b94b | 471 | --apic->isr_count; |
fc57ac2c PB |
472 | BUG_ON(apic->isr_count < 0); |
473 | apic->highest_isr_cache = -1; | |
474 | } | |
8680b94b MT |
475 | } |
476 | ||
6e5d865c YS |
477 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
478 | { | |
6e5d865c YS |
479 | int highest_irr; |
480 | ||
33e4c686 GN |
481 | /* This may race with setting of irr in __apic_accept_irq() and |
482 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
483 | * will cause vmexit immediately and the value will be recalculated | |
484 | * on the next vmentry. | |
485 | */ | |
c48f1496 | 486 | if (!kvm_vcpu_has_lapic(vcpu)) |
6e5d865c | 487 | return 0; |
54e9818f | 488 | highest_irr = apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c YS |
489 | |
490 | return highest_irr; | |
491 | } | |
6e5d865c | 492 | |
6da7e3f6 | 493 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c YZ |
494 | int vector, int level, int trig_mode, |
495 | unsigned long *dest_map); | |
6da7e3f6 | 496 | |
b4f2225c YZ |
497 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
498 | unsigned long *dest_map) | |
97222cc8 | 499 | { |
ad312c7c | 500 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 501 | |
58c2dde1 | 502 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 503 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
504 | } |
505 | ||
ae7a2a3f MT |
506 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
507 | { | |
508 | ||
509 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
510 | sizeof(val)); | |
511 | } | |
512 | ||
513 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
514 | { | |
515 | ||
516 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
517 | sizeof(*val)); | |
518 | } | |
519 | ||
520 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
521 | { | |
522 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
523 | } | |
524 | ||
525 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
526 | { | |
527 | u8 val; | |
528 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
529 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 530 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
531 | return val & 0x1; |
532 | } | |
533 | ||
534 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
535 | { | |
536 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
537 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 538 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
539 | return; |
540 | } | |
541 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
542 | } | |
543 | ||
544 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
545 | { | |
546 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
547 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 548 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
549 | return; |
550 | } | |
551 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
552 | } | |
553 | ||
97222cc8 ED |
554 | static void apic_update_ppr(struct kvm_lapic *apic) |
555 | { | |
3842d135 | 556 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
557 | int isr; |
558 | ||
c48f1496 GN |
559 | old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); |
560 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
561 | isr = apic_find_highest_isr(apic); |
562 | isrv = (isr != -1) ? isr : 0; | |
563 | ||
564 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
565 | ppr = tpr & 0xff; | |
566 | else | |
567 | ppr = isrv & 0xf0; | |
568 | ||
569 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
570 | apic, ppr, isr, isrv); | |
571 | ||
3842d135 AK |
572 | if (old_ppr != ppr) { |
573 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
83bcacb1 AK |
574 | if (ppr < old_ppr) |
575 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 576 | } |
97222cc8 ED |
577 | } |
578 | ||
579 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
580 | { | |
581 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
582 | apic_update_ppr(apic); | |
583 | } | |
584 | ||
03d2249e | 585 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 586 | { |
03d2249e RK |
587 | if (apic_x2apic_mode(apic)) |
588 | return mda == X2APIC_BROADCAST; | |
589 | ||
590 | return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST; | |
394457a9 NA |
591 | } |
592 | ||
03d2249e | 593 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 594 | { |
03d2249e RK |
595 | if (kvm_apic_broadcast(apic, mda)) |
596 | return true; | |
597 | ||
598 | if (apic_x2apic_mode(apic)) | |
599 | return mda == kvm_apic_id(apic); | |
600 | ||
601 | return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic)); | |
97222cc8 ED |
602 | } |
603 | ||
52c233a4 | 604 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 605 | { |
0105d1a5 GN |
606 | u32 logical_id; |
607 | ||
394457a9 | 608 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 609 | return true; |
394457a9 | 610 | |
9368b567 | 611 | logical_id = kvm_apic_get_reg(apic, APIC_LDR); |
97222cc8 | 612 | |
9368b567 | 613 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
614 | return ((logical_id >> 16) == (mda >> 16)) |
615 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 616 | |
9368b567 | 617 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
03d2249e | 618 | mda = GET_APIC_DEST_FIELD(mda); |
97222cc8 | 619 | |
c48f1496 | 620 | switch (kvm_apic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 621 | case APIC_DFR_FLAT: |
9368b567 | 622 | return (logical_id & mda) != 0; |
97222cc8 | 623 | case APIC_DFR_CLUSTER: |
9368b567 RK |
624 | return ((logical_id >> 4) == (mda >> 4)) |
625 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 626 | default: |
7712de87 | 627 | apic_debug("Bad DFR vcpu %d: %08x\n", |
c48f1496 | 628 | apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); |
9368b567 | 629 | return false; |
97222cc8 | 630 | } |
97222cc8 ED |
631 | } |
632 | ||
03d2249e RK |
633 | /* KVM APIC implementation has two quirks |
634 | * - dest always begins at 0 while xAPIC MDA has offset 24, | |
635 | * - IOxAPIC messages have to be delivered (directly) to x2APIC. | |
636 | */ | |
637 | static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source, | |
638 | struct kvm_lapic *target) | |
639 | { | |
640 | bool ipi = source != NULL; | |
641 | bool x2apic_mda = apic_x2apic_mode(ipi ? source : target); | |
642 | ||
643 | if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda) | |
644 | return X2APIC_BROADCAST; | |
645 | ||
646 | return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id); | |
647 | } | |
648 | ||
52c233a4 | 649 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 650 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 651 | { |
ad312c7c | 652 | struct kvm_lapic *target = vcpu->arch.apic; |
03d2249e | 653 | u32 mda = kvm_apic_mda(dest, source, target); |
97222cc8 ED |
654 | |
655 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 656 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
657 | target, source, dest, dest_mode, short_hand); |
658 | ||
bd371396 | 659 | ASSERT(target); |
97222cc8 ED |
660 | switch (short_hand) { |
661 | case APIC_DEST_NOSHORT: | |
3697f302 | 662 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 663 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 664 | else |
03d2249e | 665 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 666 | case APIC_DEST_SELF: |
9368b567 | 667 | return target == source; |
97222cc8 | 668 | case APIC_DEST_ALLINC: |
9368b567 | 669 | return true; |
97222cc8 | 670 | case APIC_DEST_ALLBUT: |
9368b567 | 671 | return target != source; |
97222cc8 | 672 | default: |
7712de87 JK |
673 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
674 | short_hand); | |
9368b567 | 675 | return false; |
97222cc8 | 676 | } |
97222cc8 ED |
677 | } |
678 | ||
1e08ec4a | 679 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 680 | struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) |
1e08ec4a GN |
681 | { |
682 | struct kvm_apic_map *map; | |
683 | unsigned long bitmap = 1; | |
684 | struct kvm_lapic **dst; | |
685 | int i; | |
bea15428 | 686 | bool ret, x2apic_ipi; |
1e08ec4a GN |
687 | |
688 | *r = -1; | |
689 | ||
690 | if (irq->shorthand == APIC_DEST_SELF) { | |
b4f2225c | 691 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); |
1e08ec4a GN |
692 | return true; |
693 | } | |
694 | ||
695 | if (irq->shorthand) | |
696 | return false; | |
697 | ||
bea15428 | 698 | x2apic_ipi = src && apic_x2apic_mode(src); |
9ea369b0 RK |
699 | if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST)) |
700 | return false; | |
701 | ||
bea15428 | 702 | ret = true; |
1e08ec4a GN |
703 | rcu_read_lock(); |
704 | map = rcu_dereference(kvm->arch.apic_map); | |
705 | ||
bea15428 PB |
706 | if (!map) { |
707 | ret = false; | |
1e08ec4a | 708 | goto out; |
bea15428 | 709 | } |
698f9755 | 710 | |
3697f302 | 711 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
fa834e91 RK |
712 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) |
713 | goto out; | |
714 | ||
715 | dst = &map->phys_map[irq->dest_id]; | |
1e08ec4a | 716 | } else { |
3548a259 RK |
717 | u16 cid; |
718 | ||
719 | if (!kvm_apic_logical_map_valid(map)) { | |
720 | ret = false; | |
721 | goto out; | |
722 | } | |
723 | ||
3b5a5ffa | 724 | apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap); |
45c3094a RK |
725 | |
726 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
727 | goto out; | |
1e08ec4a | 728 | |
45c3094a | 729 | dst = map->logical_map[cid]; |
1e08ec4a | 730 | |
d1ebdbf9 | 731 | if (kvm_lowest_prio_delivery(irq)) { |
1e08ec4a GN |
732 | int l = -1; |
733 | for_each_set_bit(i, &bitmap, 16) { | |
734 | if (!dst[i]) | |
735 | continue; | |
736 | if (l < 0) | |
737 | l = i; | |
738 | else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) | |
739 | l = i; | |
740 | } | |
741 | ||
742 | bitmap = (l >= 0) ? 1 << l : 0; | |
743 | } | |
744 | } | |
745 | ||
746 | for_each_set_bit(i, &bitmap, 16) { | |
747 | if (!dst[i]) | |
748 | continue; | |
749 | if (*r < 0) | |
750 | *r = 0; | |
b4f2225c | 751 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 752 | } |
1e08ec4a GN |
753 | out: |
754 | rcu_read_unlock(); | |
755 | return ret; | |
756 | } | |
757 | ||
97222cc8 ED |
758 | /* |
759 | * Add a pending IRQ into lapic. | |
760 | * Return 1 if successfully added and 0 if discarded. | |
761 | */ | |
762 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c YZ |
763 | int vector, int level, int trig_mode, |
764 | unsigned long *dest_map) | |
97222cc8 | 765 | { |
6da7e3f6 | 766 | int result = 0; |
c5ec1534 | 767 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 768 | |
a183b638 PB |
769 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
770 | trig_mode, vector); | |
97222cc8 | 771 | switch (delivery_mode) { |
97222cc8 | 772 | case APIC_DM_LOWEST: |
e1035715 GN |
773 | vcpu->arch.apic_arb_prio++; |
774 | case APIC_DM_FIXED: | |
bdaffe1d PB |
775 | if (unlikely(trig_mode && !level)) |
776 | break; | |
777 | ||
97222cc8 ED |
778 | /* FIXME add logic for vcpu on reset */ |
779 | if (unlikely(!apic_enabled(apic))) | |
780 | break; | |
781 | ||
11f5cc05 JK |
782 | result = 1; |
783 | ||
b4f2225c YZ |
784 | if (dest_map) |
785 | __set_bit(vcpu->vcpu_id, dest_map); | |
a5d36f82 | 786 | |
bdaffe1d PB |
787 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
788 | if (trig_mode) | |
789 | apic_set_vector(vector, apic->regs + APIC_TMR); | |
790 | else | |
791 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
792 | } | |
793 | ||
11f5cc05 | 794 | if (kvm_x86_ops->deliver_posted_interrupt) |
5a71785d | 795 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 JK |
796 | else { |
797 | apic_set_irr(vector, apic); | |
5a71785d YZ |
798 | |
799 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
800 | kvm_vcpu_kick(vcpu); | |
801 | } | |
97222cc8 ED |
802 | break; |
803 | ||
804 | case APIC_DM_REMRD: | |
24d2166b R |
805 | result = 1; |
806 | vcpu->arch.pv.pv_unhalted = 1; | |
807 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
808 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
809 | break; |
810 | ||
811 | case APIC_DM_SMI: | |
64d60670 PB |
812 | result = 1; |
813 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
814 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 815 | break; |
3419ffc8 | 816 | |
97222cc8 | 817 | case APIC_DM_NMI: |
6da7e3f6 | 818 | result = 1; |
3419ffc8 | 819 | kvm_inject_nmi(vcpu); |
26df99c6 | 820 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
821 | break; |
822 | ||
823 | case APIC_DM_INIT: | |
a52315e1 | 824 | if (!trig_mode || level) { |
6da7e3f6 | 825 | result = 1; |
66450a21 JK |
826 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
827 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
828 | /* make sure pending_events is visible before sending | |
829 | * the request */ | |
830 | smp_wmb(); | |
3842d135 | 831 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
832 | kvm_vcpu_kick(vcpu); |
833 | } else { | |
1b10bf31 JK |
834 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
835 | vcpu->vcpu_id); | |
c5ec1534 | 836 | } |
97222cc8 ED |
837 | break; |
838 | ||
839 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
840 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
841 | vcpu->vcpu_id, vector); | |
66450a21 JK |
842 | result = 1; |
843 | apic->sipi_vector = vector; | |
844 | /* make sure sipi_vector is visible for the receiver */ | |
845 | smp_wmb(); | |
846 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
847 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
848 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
849 | break; |
850 | ||
23930f95 JK |
851 | case APIC_DM_EXTINT: |
852 | /* | |
853 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
854 | * before NMI watchdog was enabled. Already handled by | |
855 | * kvm_apic_accept_pic_intr(). | |
856 | */ | |
857 | break; | |
858 | ||
97222cc8 ED |
859 | default: |
860 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
861 | delivery_mode); | |
862 | break; | |
863 | } | |
864 | return result; | |
865 | } | |
866 | ||
e1035715 | 867 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 868 | { |
e1035715 | 869 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
870 | } |
871 | ||
c7c9c56c YZ |
872 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
873 | { | |
c806a6ad | 874 | if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { |
c7c9c56c YZ |
875 | int trigger_mode; |
876 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
877 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
878 | else | |
879 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1fcc7890 | 880 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); |
c7c9c56c YZ |
881 | } |
882 | } | |
883 | ||
ae7a2a3f | 884 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
885 | { |
886 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
887 | |
888 | trace_kvm_eoi(apic, vector); | |
889 | ||
97222cc8 ED |
890 | /* |
891 | * Not every write EOI will has corresponding ISR, | |
892 | * one example is when Kernel check timer on setup_IO_APIC | |
893 | */ | |
894 | if (vector == -1) | |
ae7a2a3f | 895 | return vector; |
97222cc8 | 896 | |
8680b94b | 897 | apic_clear_isr(vector, apic); |
97222cc8 ED |
898 | apic_update_ppr(apic); |
899 | ||
c7c9c56c | 900 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 901 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 902 | return vector; |
97222cc8 ED |
903 | } |
904 | ||
c7c9c56c YZ |
905 | /* |
906 | * this interface assumes a trap-like exit, which has already finished | |
907 | * desired side effect including vISR and vPPR update. | |
908 | */ | |
909 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
910 | { | |
911 | struct kvm_lapic *apic = vcpu->arch.apic; | |
912 | ||
913 | trace_kvm_eoi(apic, vector); | |
914 | ||
915 | kvm_ioapic_send_eoi(apic, vector); | |
916 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
917 | } | |
918 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
919 | ||
97222cc8 ED |
920 | static void apic_send_ipi(struct kvm_lapic *apic) |
921 | { | |
c48f1496 GN |
922 | u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); |
923 | u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 924 | struct kvm_lapic_irq irq; |
97222cc8 | 925 | |
58c2dde1 GN |
926 | irq.vector = icr_low & APIC_VECTOR_MASK; |
927 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
928 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 929 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
930 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
931 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 932 | irq.msi_redir_hint = false; |
0105d1a5 GN |
933 | if (apic_x2apic_mode(apic)) |
934 | irq.dest_id = icr_high; | |
935 | else | |
936 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 937 | |
1000ff8d GN |
938 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
939 | ||
97222cc8 ED |
940 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
941 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
942 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
943 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 944 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 945 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 946 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 947 | |
b4f2225c | 948 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
949 | } |
950 | ||
951 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
952 | { | |
b682b814 MT |
953 | ktime_t remaining; |
954 | s64 ns; | |
9da8f4e8 | 955 | u32 tmcct; |
97222cc8 ED |
956 | |
957 | ASSERT(apic != NULL); | |
958 | ||
9da8f4e8 | 959 | /* if initial count is 0, current count should also be 0 */ |
b963a22e AH |
960 | if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 || |
961 | apic->lapic_timer.period == 0) | |
9da8f4e8 KP |
962 | return 0; |
963 | ||
ace15464 | 964 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
965 | if (ktime_to_ns(remaining) < 0) |
966 | remaining = ktime_set(0, 0); | |
967 | ||
d3c7b77d MT |
968 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
969 | tmcct = div64_u64(ns, | |
970 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
971 | |
972 | return tmcct; | |
973 | } | |
974 | ||
b209749f AK |
975 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
976 | { | |
977 | struct kvm_vcpu *vcpu = apic->vcpu; | |
978 | struct kvm_run *run = vcpu->run; | |
979 | ||
a8eeb04a | 980 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 981 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
982 | run->tpr_access.is_write = write; |
983 | } | |
984 | ||
985 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
986 | { | |
987 | if (apic->vcpu->arch.tpr_access_reporting) | |
988 | __report_tpr_access(apic, write); | |
989 | } | |
990 | ||
97222cc8 ED |
991 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
992 | { | |
993 | u32 val = 0; | |
994 | ||
995 | if (offset >= LAPIC_MMIO_LENGTH) | |
996 | return 0; | |
997 | ||
998 | switch (offset) { | |
0105d1a5 GN |
999 | case APIC_ID: |
1000 | if (apic_x2apic_mode(apic)) | |
1001 | val = kvm_apic_id(apic); | |
1002 | else | |
1003 | val = kvm_apic_id(apic) << 24; | |
1004 | break; | |
97222cc8 | 1005 | case APIC_ARBPRI: |
7712de87 | 1006 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1007 | break; |
1008 | ||
1009 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1010 | if (apic_lvtt_tscdeadline(apic)) |
1011 | return 0; | |
1012 | ||
97222cc8 ED |
1013 | val = apic_get_tmcct(apic); |
1014 | break; | |
4a4541a4 AK |
1015 | case APIC_PROCPRI: |
1016 | apic_update_ppr(apic); | |
c48f1496 | 1017 | val = kvm_apic_get_reg(apic, offset); |
4a4541a4 | 1018 | break; |
b209749f AK |
1019 | case APIC_TASKPRI: |
1020 | report_tpr_access(apic, false); | |
1021 | /* fall thru */ | |
97222cc8 | 1022 | default: |
c48f1496 | 1023 | val = kvm_apic_get_reg(apic, offset); |
97222cc8 ED |
1024 | break; |
1025 | } | |
1026 | ||
1027 | return val; | |
1028 | } | |
1029 | ||
d76685c4 GH |
1030 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1031 | { | |
1032 | return container_of(dev, struct kvm_lapic, dev); | |
1033 | } | |
1034 | ||
0105d1a5 GN |
1035 | static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
1036 | void *data) | |
97222cc8 | 1037 | { |
97222cc8 ED |
1038 | unsigned char alignment = offset & 0xf; |
1039 | u32 result; | |
d5b0b5b1 | 1040 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1041 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1042 | |
1043 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1044 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1045 | offset, len); | |
0105d1a5 | 1046 | return 1; |
97222cc8 | 1047 | } |
0105d1a5 GN |
1048 | |
1049 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1050 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1051 | offset); | |
0105d1a5 GN |
1052 | return 1; |
1053 | } | |
1054 | ||
97222cc8 ED |
1055 | result = __apic_read(apic, offset & ~0xf); |
1056 | ||
229456fc MT |
1057 | trace_kvm_apic_read(offset, result); |
1058 | ||
97222cc8 ED |
1059 | switch (len) { |
1060 | case 1: | |
1061 | case 2: | |
1062 | case 4: | |
1063 | memcpy(data, (char *)&result + alignment, len); | |
1064 | break; | |
1065 | default: | |
1066 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1067 | "should be 1,2, or 4 instead\n", len); | |
1068 | break; | |
1069 | } | |
bda9020e | 1070 | return 0; |
97222cc8 ED |
1071 | } |
1072 | ||
0105d1a5 GN |
1073 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1074 | { | |
c48f1496 | 1075 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1076 | addr >= apic->base_address && |
1077 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1078 | } | |
1079 | ||
e32edf4f | 1080 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1081 | gpa_t address, int len, void *data) |
1082 | { | |
1083 | struct kvm_lapic *apic = to_lapic(this); | |
1084 | u32 offset = address - apic->base_address; | |
1085 | ||
1086 | if (!apic_mmio_in_range(apic, address)) | |
1087 | return -EOPNOTSUPP; | |
1088 | ||
1089 | apic_reg_read(apic, offset, len, data); | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
97222cc8 ED |
1094 | static void update_divide_count(struct kvm_lapic *apic) |
1095 | { | |
1096 | u32 tmp1, tmp2, tdcr; | |
1097 | ||
c48f1496 | 1098 | tdcr = kvm_apic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1099 | tmp1 = tdcr & 0xf; |
1100 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1101 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1102 | |
1103 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1104 | apic->divide_count); |
97222cc8 ED |
1105 | } |
1106 | ||
b6ac0695 RK |
1107 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1108 | { | |
1109 | u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) & | |
1110 | apic->lapic_timer.timer_mode_mask; | |
1111 | ||
1112 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1113 | apic->lapic_timer.timer_mode = timer_mode; | |
1114 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1115 | } | |
1116 | } | |
1117 | ||
5d87db71 RK |
1118 | static void apic_timer_expired(struct kvm_lapic *apic) |
1119 | { | |
1120 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1121 | wait_queue_head_t *q = &vcpu->wq; | |
d0659d94 | 1122 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1123 | |
5d87db71 RK |
1124 | if (atomic_read(&apic->lapic_timer.pending)) |
1125 | return; | |
1126 | ||
1127 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1128 | kvm_set_pending_timer(vcpu); |
5d87db71 RK |
1129 | |
1130 | if (waitqueue_active(q)) | |
1131 | wake_up_interruptible(q); | |
d0659d94 MT |
1132 | |
1133 | if (apic_lvtt_tscdeadline(apic)) | |
1134 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1135 | } | |
1136 | ||
1137 | /* | |
1138 | * On APICv, this test will cause a busy wait | |
1139 | * during a higher-priority task. | |
1140 | */ | |
1141 | ||
1142 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1143 | { | |
1144 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1145 | u32 reg = kvm_apic_get_reg(apic, APIC_LVTT); | |
1146 | ||
1147 | if (kvm_apic_hw_enabled(apic)) { | |
1148 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1149 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1150 | |
f9339860 MT |
1151 | if (kvm_x86_ops->deliver_posted_interrupt) |
1152 | bitmap = apic->regs + APIC_IRR; | |
1153 | ||
1154 | if (apic_test_vector(vec, bitmap)) | |
1155 | return true; | |
d0659d94 MT |
1156 | } |
1157 | return false; | |
1158 | } | |
1159 | ||
1160 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1161 | { | |
1162 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1163 | u64 guest_tsc, tsc_deadline; | |
1164 | ||
1165 | if (!kvm_vcpu_has_lapic(vcpu)) | |
1166 | return; | |
1167 | ||
1168 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1169 | return; | |
1170 | ||
1171 | if (!lapic_timer_int_injected(vcpu)) | |
1172 | return; | |
1173 | ||
1174 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1175 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ea1636b | 1176 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1177 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1178 | |
1179 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1180 | if (guest_tsc < tsc_deadline) | |
1181 | __delay(tsc_deadline - guest_tsc); | |
5d87db71 RK |
1182 | } |
1183 | ||
97222cc8 ED |
1184 | static void start_apic_timer(struct kvm_lapic *apic) |
1185 | { | |
a3e06bbe | 1186 | ktime_t now; |
d0659d94 | 1187 | |
d3c7b77d | 1188 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1189 | |
a3e06bbe | 1190 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1191 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1192 | now = apic->lapic_timer.timer.base->get_time(); |
c48f1496 | 1193 | apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1194 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1195 | ||
1196 | if (!apic->lapic_timer.period) | |
1197 | return; | |
1198 | /* | |
1199 | * Do not allow the guest to program periodic timers with small | |
1200 | * interval, since the hrtimers are not throttled by the host | |
1201 | * scheduler. | |
1202 | */ | |
1203 | if (apic_lvtt_period(apic)) { | |
1204 | s64 min_period = min_timer_period_us * 1000LL; | |
1205 | ||
1206 | if (apic->lapic_timer.period < min_period) { | |
1207 | pr_info_ratelimited( | |
1208 | "kvm: vcpu %i: requested %lld ns " | |
1209 | "lapic timer period limited to %lld ns\n", | |
1210 | apic->vcpu->vcpu_id, | |
1211 | apic->lapic_timer.period, min_period); | |
1212 | apic->lapic_timer.period = min_period; | |
1213 | } | |
9bc5791d | 1214 | } |
0b975a3c | 1215 | |
a3e06bbe LJ |
1216 | hrtimer_start(&apic->lapic_timer.timer, |
1217 | ktime_add_ns(now, apic->lapic_timer.period), | |
1218 | HRTIMER_MODE_ABS); | |
97222cc8 | 1219 | |
a3e06bbe | 1220 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1221 | PRIx64 ", " |
1222 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1223 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1224 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
c48f1496 | 1225 | kvm_apic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1226 | apic->lapic_timer.period, |
97222cc8 | 1227 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1228 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1229 | } else if (apic_lvtt_tscdeadline(apic)) { |
1230 | /* lapic timer in tsc deadline mode */ | |
1231 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1232 | u64 ns = 0; | |
d0659d94 | 1233 | ktime_t expire; |
a3e06bbe | 1234 | struct kvm_vcpu *vcpu = apic->vcpu; |
cc578287 | 1235 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1236 | unsigned long flags; |
1237 | ||
1238 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1239 | return; | |
1240 | ||
1241 | local_irq_save(flags); | |
1242 | ||
1243 | now = apic->lapic_timer.timer.base->get_time(); | |
4ea1636b | 1244 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc()); |
a3e06bbe LJ |
1245 | if (likely(tscdeadline > guest_tsc)) { |
1246 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1247 | do_div(ns, this_tsc_khz); | |
d0659d94 MT |
1248 | expire = ktime_add_ns(now, ns); |
1249 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1e0ad70c | 1250 | hrtimer_start(&apic->lapic_timer.timer, |
d0659d94 | 1251 | expire, HRTIMER_MODE_ABS); |
1e0ad70c RK |
1252 | } else |
1253 | apic_timer_expired(apic); | |
a3e06bbe LJ |
1254 | |
1255 | local_irq_restore(flags); | |
1256 | } | |
97222cc8 ED |
1257 | } |
1258 | ||
cc6e462c JK |
1259 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1260 | { | |
59fd1323 | 1261 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1262 | |
59fd1323 RK |
1263 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1264 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1265 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1266 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1267 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1268 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1269 | } else |
1270 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1271 | } | |
cc6e462c JK |
1272 | } |
1273 | ||
0105d1a5 | 1274 | static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1275 | { |
0105d1a5 | 1276 | int ret = 0; |
97222cc8 | 1277 | |
0105d1a5 | 1278 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1279 | |
0105d1a5 | 1280 | switch (reg) { |
97222cc8 | 1281 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1282 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1283 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1284 | else |
1285 | ret = 1; | |
97222cc8 ED |
1286 | break; |
1287 | ||
1288 | case APIC_TASKPRI: | |
b209749f | 1289 | report_tpr_access(apic, true); |
97222cc8 ED |
1290 | apic_set_tpr(apic, val & 0xff); |
1291 | break; | |
1292 | ||
1293 | case APIC_EOI: | |
1294 | apic_set_eoi(apic); | |
1295 | break; | |
1296 | ||
1297 | case APIC_LDR: | |
0105d1a5 | 1298 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1299 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1300 | else |
1301 | ret = 1; | |
97222cc8 ED |
1302 | break; |
1303 | ||
1304 | case APIC_DFR: | |
1e08ec4a | 1305 | if (!apic_x2apic_mode(apic)) { |
0105d1a5 | 1306 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1307 | recalculate_apic_map(apic->vcpu->kvm); |
1308 | } else | |
0105d1a5 | 1309 | ret = 1; |
97222cc8 ED |
1310 | break; |
1311 | ||
fc61b800 GN |
1312 | case APIC_SPIV: { |
1313 | u32 mask = 0x3ff; | |
c48f1496 | 1314 | if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1315 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1316 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1317 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1318 | int i; | |
1319 | u32 lvt_val; | |
1320 | ||
1321 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
c48f1496 | 1322 | lvt_val = kvm_apic_get_reg(apic, |
97222cc8 ED |
1323 | APIC_LVTT + 0x10 * i); |
1324 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
1325 | lvt_val | APIC_LVT_MASKED); | |
1326 | } | |
b6ac0695 | 1327 | apic_update_lvtt(apic); |
d3c7b77d | 1328 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1329 | |
1330 | } | |
1331 | break; | |
fc61b800 | 1332 | } |
97222cc8 ED |
1333 | case APIC_ICR: |
1334 | /* No delay here, so we always clear the pending bit */ | |
1335 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
1336 | apic_send_ipi(apic); | |
1337 | break; | |
1338 | ||
1339 | case APIC_ICR2: | |
0105d1a5 GN |
1340 | if (!apic_x2apic_mode(apic)) |
1341 | val &= 0xff000000; | |
1342 | apic_set_reg(apic, APIC_ICR2, val); | |
97222cc8 ED |
1343 | break; |
1344 | ||
23930f95 | 1345 | case APIC_LVT0: |
cc6e462c | 1346 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1347 | case APIC_LVTTHMR: |
1348 | case APIC_LVTPC: | |
97222cc8 ED |
1349 | case APIC_LVT1: |
1350 | case APIC_LVTERR: | |
1351 | /* TODO: Check vector */ | |
c48f1496 | 1352 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1353 | val |= APIC_LVT_MASKED; |
1354 | ||
0105d1a5 GN |
1355 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1356 | apic_set_reg(apic, reg, val); | |
97222cc8 ED |
1357 | |
1358 | break; | |
1359 | ||
b6ac0695 | 1360 | case APIC_LVTT: |
c48f1496 | 1361 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1362 | val |= APIC_LVT_MASKED; |
1363 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1364 | apic_set_reg(apic, APIC_LVTT, val); | |
b6ac0695 | 1365 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1366 | break; |
1367 | ||
97222cc8 | 1368 | case APIC_TMICT: |
a3e06bbe LJ |
1369 | if (apic_lvtt_tscdeadline(apic)) |
1370 | break; | |
1371 | ||
d3c7b77d | 1372 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 ED |
1373 | apic_set_reg(apic, APIC_TMICT, val); |
1374 | start_apic_timer(apic); | |
0105d1a5 | 1375 | break; |
97222cc8 ED |
1376 | |
1377 | case APIC_TDCR: | |
1378 | if (val & 4) | |
7712de87 | 1379 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
97222cc8 ED |
1380 | apic_set_reg(apic, APIC_TDCR, val); |
1381 | update_divide_count(apic); | |
1382 | break; | |
1383 | ||
0105d1a5 GN |
1384 | case APIC_ESR: |
1385 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1386 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1387 | ret = 1; |
1388 | } | |
1389 | break; | |
1390 | ||
1391 | case APIC_SELF_IPI: | |
1392 | if (apic_x2apic_mode(apic)) { | |
1393 | apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); | |
1394 | } else | |
1395 | ret = 1; | |
1396 | break; | |
97222cc8 | 1397 | default: |
0105d1a5 | 1398 | ret = 1; |
97222cc8 ED |
1399 | break; |
1400 | } | |
0105d1a5 GN |
1401 | if (ret) |
1402 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1403 | return ret; | |
1404 | } | |
1405 | ||
e32edf4f | 1406 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1407 | gpa_t address, int len, const void *data) |
1408 | { | |
1409 | struct kvm_lapic *apic = to_lapic(this); | |
1410 | unsigned int offset = address - apic->base_address; | |
1411 | u32 val; | |
1412 | ||
1413 | if (!apic_mmio_in_range(apic, address)) | |
1414 | return -EOPNOTSUPP; | |
1415 | ||
1416 | /* | |
1417 | * APIC register must be aligned on 128-bits boundary. | |
1418 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1419 | * Refer SDM 8.4.1 | |
1420 | */ | |
1421 | if (len != 4 || (offset & 0xf)) { | |
1422 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1423 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1424 | return 0; |
0105d1a5 GN |
1425 | } |
1426 | ||
1427 | val = *(u32*)data; | |
1428 | ||
1429 | /* too common printing */ | |
1430 | if (offset != APIC_EOI) | |
1431 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1432 | "0x%x\n", __func__, offset, len, val); | |
1433 | ||
1434 | apic_reg_write(apic, offset & 0xff0, val); | |
1435 | ||
bda9020e | 1436 | return 0; |
97222cc8 ED |
1437 | } |
1438 | ||
58fbbf26 KT |
1439 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1440 | { | |
c48f1496 | 1441 | if (kvm_vcpu_has_lapic(vcpu)) |
58fbbf26 KT |
1442 | apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
1443 | } | |
1444 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1445 | ||
83d4c286 YZ |
1446 | /* emulate APIC access in a trap manner */ |
1447 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1448 | { | |
1449 | u32 val = 0; | |
1450 | ||
1451 | /* hw has done the conditional check and inst decode */ | |
1452 | offset &= 0xff0; | |
1453 | ||
1454 | apic_reg_read(vcpu->arch.apic, offset, 4, &val); | |
1455 | ||
1456 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1457 | apic_reg_write(vcpu->arch.apic, offset, val); | |
1458 | } | |
1459 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1460 | ||
d589444e | 1461 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1462 | { |
f8c1ea10 GN |
1463 | struct kvm_lapic *apic = vcpu->arch.apic; |
1464 | ||
ad312c7c | 1465 | if (!vcpu->arch.apic) |
97222cc8 ED |
1466 | return; |
1467 | ||
f8c1ea10 | 1468 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1469 | |
c5cc421b GN |
1470 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1471 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1472 | ||
e462755c | 1473 | if (!apic->sw_enabled) |
f8c1ea10 | 1474 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1475 | |
f8c1ea10 GN |
1476 | if (apic->regs) |
1477 | free_page((unsigned long)apic->regs); | |
1478 | ||
1479 | kfree(apic); | |
97222cc8 ED |
1480 | } |
1481 | ||
1482 | /* | |
1483 | *---------------------------------------------------------------------- | |
1484 | * LAPIC interface | |
1485 | *---------------------------------------------------------------------- | |
1486 | */ | |
1487 | ||
a3e06bbe LJ |
1488 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1489 | { | |
1490 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1491 | |
c48f1496 | 1492 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1493 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1494 | return 0; |
1495 | ||
1496 | return apic->lapic_timer.tscdeadline; | |
1497 | } | |
1498 | ||
1499 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1500 | { | |
1501 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1502 | |
c48f1496 | 1503 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1504 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1505 | return; |
1506 | ||
1507 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1508 | apic->lapic_timer.tscdeadline = data; | |
1509 | start_apic_timer(apic); | |
1510 | } | |
1511 | ||
97222cc8 ED |
1512 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1513 | { | |
ad312c7c | 1514 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1515 | |
c48f1496 | 1516 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1517 | return; |
54e9818f | 1518 | |
b93463aa | 1519 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
c48f1496 | 1520 | | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1521 | } |
1522 | ||
1523 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1524 | { | |
97222cc8 ED |
1525 | u64 tpr; |
1526 | ||
c48f1496 | 1527 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1528 | return 0; |
54e9818f | 1529 | |
c48f1496 | 1530 | tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1531 | |
1532 | return (tpr & 0xf0) >> 4; | |
1533 | } | |
1534 | ||
1535 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1536 | { | |
8d14695f | 1537 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1538 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1539 | |
1540 | if (!apic) { | |
1541 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1542 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1543 | return; |
1544 | } | |
c5af89b6 | 1545 | |
e66d2ae7 JK |
1546 | vcpu->arch.apic_base = value; |
1547 | ||
c5cc421b | 1548 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1549 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1550 | if (value & MSR_IA32_APICBASE_ENABLE) |
1551 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1552 | else | |
1553 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1554 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1555 | } |
1556 | ||
8d14695f YZ |
1557 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1558 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1559 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1560 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1561 | } else | |
1562 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1563 | } |
8d14695f | 1564 | |
ad312c7c | 1565 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1566 | MSR_IA32_APICBASE_BASE; |
1567 | ||
db324fe6 NA |
1568 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1569 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1570 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1571 | ||
97222cc8 ED |
1572 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1573 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1574 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1575 | |
1576 | } | |
1577 | ||
d28bc9dd | 1578 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
1579 | { |
1580 | struct kvm_lapic *apic; | |
1581 | int i; | |
1582 | ||
b8688d51 | 1583 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1584 | |
1585 | ASSERT(vcpu); | |
ad312c7c | 1586 | apic = vcpu->arch.apic; |
97222cc8 ED |
1587 | ASSERT(apic != NULL); |
1588 | ||
1589 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1590 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1591 | |
d28bc9dd NA |
1592 | if (!init_event) |
1593 | kvm_apic_set_id(apic, vcpu->vcpu_id); | |
fc61b800 | 1594 | kvm_apic_set_version(apic->vcpu); |
97222cc8 ED |
1595 | |
1596 | for (i = 0; i < APIC_LVT_NUM; i++) | |
1597 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 1598 | apic_update_lvtt(apic); |
0da029ed | 1599 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) |
90de4a18 NA |
1600 | apic_set_reg(apic, APIC_LVT0, |
1601 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
59fd1323 | 1602 | apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0)); |
97222cc8 ED |
1603 | |
1604 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
f8c1ea10 | 1605 | apic_set_spiv(apic, 0xff); |
97222cc8 | 1606 | apic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
1607 | if (!apic_x2apic_mode(apic)) |
1608 | kvm_apic_set_ldr(apic, 0); | |
97222cc8 ED |
1609 | apic_set_reg(apic, APIC_ESR, 0); |
1610 | apic_set_reg(apic, APIC_ICR, 0); | |
1611 | apic_set_reg(apic, APIC_ICR2, 0); | |
1612 | apic_set_reg(apic, APIC_TDCR, 0); | |
1613 | apic_set_reg(apic, APIC_TMICT, 0); | |
1614 | for (i = 0; i < 8; i++) { | |
1615 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
1616 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1617 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
1618 | } | |
c7c9c56c | 1619 | apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); |
f563db4b | 1620 | apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0; |
8680b94b | 1621 | apic->highest_isr_cache = -1; |
b33ac88b | 1622 | update_divide_count(apic); |
d3c7b77d | 1623 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1624 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1625 | kvm_lapic_set_base(vcpu, |
1626 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1627 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1628 | apic_update_ppr(apic); |
1629 | ||
e1035715 | 1630 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1631 | vcpu->arch.apic_attention = 0; |
e1035715 | 1632 | |
98eff52a | 1633 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1634 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1635 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1636 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1637 | } |
1638 | ||
97222cc8 ED |
1639 | /* |
1640 | *---------------------------------------------------------------------- | |
1641 | * timer interface | |
1642 | *---------------------------------------------------------------------- | |
1643 | */ | |
1b9778da | 1644 | |
2a6eac96 | 1645 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1646 | { |
d3c7b77d | 1647 | return apic_lvtt_period(apic); |
97222cc8 ED |
1648 | } |
1649 | ||
3d80840d MT |
1650 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1651 | { | |
54e9818f | 1652 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1653 | |
c48f1496 | 1654 | if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && |
54e9818f GN |
1655 | apic_lvt_enabled(apic, APIC_LVTT)) |
1656 | return atomic_read(&apic->lapic_timer.pending); | |
3d80840d MT |
1657 | |
1658 | return 0; | |
1659 | } | |
1660 | ||
89342082 | 1661 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1662 | { |
c48f1496 | 1663 | u32 reg = kvm_apic_get_reg(apic, lvt_type); |
23930f95 | 1664 | int vector, mode, trig_mode; |
23930f95 | 1665 | |
c48f1496 | 1666 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1667 | vector = reg & APIC_VECTOR_MASK; |
1668 | mode = reg & APIC_MODE_MASK; | |
1669 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1670 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1671 | NULL); | |
23930f95 JK |
1672 | } |
1673 | return 0; | |
1674 | } | |
1b9778da | 1675 | |
8fdb2351 | 1676 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1677 | { |
8fdb2351 JK |
1678 | struct kvm_lapic *apic = vcpu->arch.apic; |
1679 | ||
1680 | if (apic) | |
1681 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1682 | } |
1683 | ||
d76685c4 GH |
1684 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1685 | .read = apic_mmio_read, | |
1686 | .write = apic_mmio_write, | |
d76685c4 GH |
1687 | }; |
1688 | ||
e9d90d47 AK |
1689 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1690 | { | |
1691 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1692 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1693 | |
5d87db71 | 1694 | apic_timer_expired(apic); |
e9d90d47 | 1695 | |
2a6eac96 | 1696 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1697 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1698 | return HRTIMER_RESTART; | |
1699 | } else | |
1700 | return HRTIMER_NORESTART; | |
1701 | } | |
1702 | ||
97222cc8 ED |
1703 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1704 | { | |
1705 | struct kvm_lapic *apic; | |
1706 | ||
1707 | ASSERT(vcpu != NULL); | |
1708 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1709 | ||
1710 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1711 | if (!apic) | |
1712 | goto nomem; | |
1713 | ||
ad312c7c | 1714 | vcpu->arch.apic = apic; |
97222cc8 | 1715 | |
afc20184 TY |
1716 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1717 | if (!apic->regs) { | |
97222cc8 ED |
1718 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1719 | vcpu->vcpu_id); | |
d589444e | 1720 | goto nomem_free_apic; |
97222cc8 | 1721 | } |
97222cc8 ED |
1722 | apic->vcpu = vcpu; |
1723 | ||
d3c7b77d MT |
1724 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
1725 | HRTIMER_MODE_ABS); | |
e9d90d47 | 1726 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1727 | |
c5cc421b GN |
1728 | /* |
1729 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1730 | * thinking that APIC satet has changed. | |
1731 | */ | |
1732 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1733 | kvm_lapic_set_base(vcpu, |
1734 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1735 | |
f8c1ea10 | 1736 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d28bc9dd | 1737 | kvm_lapic_reset(vcpu, false); |
d76685c4 | 1738 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1739 | |
1740 | return 0; | |
d589444e RR |
1741 | nomem_free_apic: |
1742 | kfree(apic); | |
97222cc8 | 1743 | nomem: |
97222cc8 ED |
1744 | return -ENOMEM; |
1745 | } | |
97222cc8 ED |
1746 | |
1747 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1748 | { | |
ad312c7c | 1749 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1750 | int highest_irr; |
1751 | ||
c48f1496 | 1752 | if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) |
97222cc8 ED |
1753 | return -1; |
1754 | ||
6e5d865c | 1755 | apic_update_ppr(apic); |
97222cc8 ED |
1756 | highest_irr = apic_find_highest_irr(apic); |
1757 | if ((highest_irr == -1) || | |
c48f1496 | 1758 | ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1759 | return -1; |
1760 | return highest_irr; | |
1761 | } | |
1762 | ||
40487c68 QH |
1763 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1764 | { | |
c48f1496 | 1765 | u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1766 | int r = 0; |
1767 | ||
c48f1496 | 1768 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1769 | r = 1; |
1770 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1771 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1772 | r = 1; | |
40487c68 QH |
1773 | return r; |
1774 | } | |
1775 | ||
1b9778da ED |
1776 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1777 | { | |
ad312c7c | 1778 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1779 | |
c48f1496 | 1780 | if (!kvm_vcpu_has_lapic(vcpu)) |
54e9818f GN |
1781 | return; |
1782 | ||
1783 | if (atomic_read(&apic->lapic_timer.pending) > 0) { | |
f1ed0450 | 1784 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1785 | if (apic_lvtt_tscdeadline(apic)) |
1786 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1787 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1788 | } |
1789 | } | |
1790 | ||
97222cc8 ED |
1791 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1792 | { | |
1793 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1794 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1795 | |
1796 | if (vector == -1) | |
1797 | return -1; | |
1798 | ||
56cc2406 WL |
1799 | /* |
1800 | * We get here even with APIC virtualization enabled, if doing | |
1801 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1802 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1803 | * because the process would deliver it through the IDT. | |
1804 | */ | |
1805 | ||
8680b94b | 1806 | apic_set_isr(vector, apic); |
97222cc8 ED |
1807 | apic_update_ppr(apic); |
1808 | apic_clear_irr(vector, apic); | |
1809 | return vector; | |
1810 | } | |
96ad2cc6 | 1811 | |
64eb0620 GN |
1812 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1813 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1814 | { |
ad312c7c | 1815 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1816 | |
5dbc8f3f | 1817 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1818 | /* set SPIV separately to get count of SW disabled APICs right */ |
1819 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1820 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1821 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1822 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1823 | kvm_apic_set_version(vcpu); |
1824 | ||
96ad2cc6 | 1825 | apic_update_ppr(apic); |
d3c7b77d | 1826 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 1827 | apic_update_lvtt(apic); |
db138562 | 1828 | apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
1829 | update_divide_count(apic); |
1830 | start_apic_timer(apic); | |
6e24a6ef | 1831 | apic->irr_pending = true; |
f563db4b | 1832 | apic->isr_count = kvm_x86_ops->hwapic_isr_update ? |
c7c9c56c | 1833 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 1834 | apic->highest_isr_cache = -1; |
4114c27d WW |
1835 | if (kvm_x86_ops->hwapic_irr_update) |
1836 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
1837 | apic_find_highest_irr(apic)); | |
b4eef9b3 TC |
1838 | if (unlikely(kvm_x86_ops->hwapic_isr_update)) |
1839 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, | |
1840 | apic_find_highest_isr(apic)); | |
3842d135 | 1841 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
10606919 | 1842 | kvm_rtc_eoi_tracking_restore_one(vcpu); |
96ad2cc6 | 1843 | } |
a3d7f85f | 1844 | |
2f52d58c | 1845 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1846 | { |
a3d7f85f ED |
1847 | struct hrtimer *timer; |
1848 | ||
c48f1496 | 1849 | if (!kvm_vcpu_has_lapic(vcpu)) |
a3d7f85f ED |
1850 | return; |
1851 | ||
54e9818f | 1852 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1853 | if (hrtimer_cancel(timer)) |
beb20d52 | 1854 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1855 | } |
b93463aa | 1856 | |
ae7a2a3f MT |
1857 | /* |
1858 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1859 | * | |
1860 | * Detect whether guest triggered PV EOI since the | |
1861 | * last entry. If yes, set EOI on guests's behalf. | |
1862 | * Clear PV EOI in guest memory in any case. | |
1863 | */ | |
1864 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1865 | struct kvm_lapic *apic) | |
1866 | { | |
1867 | bool pending; | |
1868 | int vector; | |
1869 | /* | |
1870 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
1871 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
1872 | * | |
1873 | * KVM_APIC_PV_EOI_PENDING is unset: | |
1874 | * -> host disabled PV EOI. | |
1875 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
1876 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
1877 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
1878 | * -> host enabled PV EOI, guest executed EOI. | |
1879 | */ | |
1880 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
1881 | pending = pv_eoi_get_pending(vcpu); | |
1882 | /* | |
1883 | * Clear pending bit in any case: it will be set again on vmentry. | |
1884 | * While this might not be ideal from performance point of view, | |
1885 | * this makes sure pv eoi is only enabled when we know it's safe. | |
1886 | */ | |
1887 | pv_eoi_clr_pending(vcpu); | |
1888 | if (pending) | |
1889 | return; | |
1890 | vector = apic_set_eoi(apic); | |
1891 | trace_kvm_pv_eoi(apic, vector); | |
1892 | } | |
1893 | ||
b93463aa AK |
1894 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
1895 | { | |
1896 | u32 data; | |
b93463aa | 1897 | |
ae7a2a3f MT |
1898 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
1899 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
1900 | ||
41383771 | 1901 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1902 | return; |
1903 | ||
603242a8 NK |
1904 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
1905 | sizeof(u32))) | |
1906 | return; | |
b93463aa AK |
1907 | |
1908 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1909 | } | |
1910 | ||
ae7a2a3f MT |
1911 | /* |
1912 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
1913 | * | |
1914 | * Detect whether it's safe to enable PV EOI and | |
1915 | * if yes do so. | |
1916 | */ | |
1917 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
1918 | struct kvm_lapic *apic) | |
1919 | { | |
1920 | if (!pv_eoi_enabled(vcpu) || | |
1921 | /* IRR set or many bits in ISR: could be nested. */ | |
1922 | apic->irr_pending || | |
1923 | /* Cache not set: could be safe but we don't bother. */ | |
1924 | apic->highest_isr_cache == -1 || | |
1925 | /* Need EOI to update ioapic. */ | |
1926 | kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { | |
1927 | /* | |
1928 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
1929 | * so we need not do anything here. | |
1930 | */ | |
1931 | return; | |
1932 | } | |
1933 | ||
1934 | pv_eoi_set_pending(apic->vcpu); | |
1935 | } | |
1936 | ||
b93463aa AK |
1937 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
1938 | { | |
1939 | u32 data, tpr; | |
1940 | int max_irr, max_isr; | |
ae7a2a3f | 1941 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 1942 | |
ae7a2a3f MT |
1943 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
1944 | ||
41383771 | 1945 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1946 | return; |
1947 | ||
c48f1496 | 1948 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
1949 | max_irr = apic_find_highest_irr(apic); |
1950 | if (max_irr < 0) | |
1951 | max_irr = 0; | |
1952 | max_isr = apic_find_highest_isr(apic); | |
1953 | if (max_isr < 0) | |
1954 | max_isr = 0; | |
1955 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1956 | ||
fda4e2e8 AH |
1957 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
1958 | sizeof(u32)); | |
b93463aa AK |
1959 | } |
1960 | ||
fda4e2e8 | 1961 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 1962 | { |
fda4e2e8 AH |
1963 | if (vapic_addr) { |
1964 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
1965 | &vcpu->arch.apic->vapic_cache, | |
1966 | vapic_addr, sizeof(u32))) | |
1967 | return -EINVAL; | |
41383771 | 1968 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 1969 | } else { |
41383771 | 1970 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
1971 | } |
1972 | ||
1973 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
1974 | return 0; | |
b93463aa | 1975 | } |
0105d1a5 GN |
1976 | |
1977 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1978 | { | |
1979 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1980 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
1981 | ||
1982 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1983 | return 1; | |
1984 | ||
c69d3d9b NA |
1985 | if (reg == APIC_ICR2) |
1986 | return 1; | |
1987 | ||
0105d1a5 | 1988 | /* if this is ICR write vector before command */ |
decdc283 | 1989 | if (reg == APIC_ICR) |
0105d1a5 GN |
1990 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
1991 | return apic_reg_write(apic, reg, (u32)data); | |
1992 | } | |
1993 | ||
1994 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
1995 | { | |
1996 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1997 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
1998 | ||
1999 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
2000 | return 1; | |
2001 | ||
c69d3d9b NA |
2002 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2003 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2004 | reg); | |
2005 | return 1; | |
2006 | } | |
2007 | ||
0105d1a5 GN |
2008 | if (apic_reg_read(apic, reg, 4, &low)) |
2009 | return 1; | |
decdc283 | 2010 | if (reg == APIC_ICR) |
0105d1a5 GN |
2011 | apic_reg_read(apic, APIC_ICR2, 4, &high); |
2012 | ||
2013 | *data = (((u64)high) << 32) | low; | |
2014 | ||
2015 | return 0; | |
2016 | } | |
10388a07 GN |
2017 | |
2018 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2019 | { | |
2020 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2021 | ||
c48f1496 | 2022 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
2023 | return 1; |
2024 | ||
2025 | /* if this is ICR write vector before command */ | |
2026 | if (reg == APIC_ICR) | |
2027 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
2028 | return apic_reg_write(apic, reg, (u32)data); | |
2029 | } | |
2030 | ||
2031 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2032 | { | |
2033 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2034 | u32 low, high = 0; | |
2035 | ||
c48f1496 | 2036 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
2037 | return 1; |
2038 | ||
2039 | if (apic_reg_read(apic, reg, 4, &low)) | |
2040 | return 1; | |
2041 | if (reg == APIC_ICR) | |
2042 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
2043 | ||
2044 | *data = (((u64)high) << 32) | low; | |
2045 | ||
2046 | return 0; | |
2047 | } | |
ae7a2a3f MT |
2048 | |
2049 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2050 | { | |
2051 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2052 | if (!IS_ALIGNED(addr, 4)) | |
2053 | return 1; | |
2054 | ||
2055 | vcpu->arch.pv_eoi.msr_val = data; | |
2056 | if (!pv_eoi_enabled(vcpu)) | |
2057 | return 0; | |
2058 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2059 | addr, sizeof(u8)); |
ae7a2a3f | 2060 | } |
c5cc421b | 2061 | |
66450a21 JK |
2062 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2063 | { | |
2064 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2065 | u8 sipi_vector; |
299018f4 | 2066 | unsigned long pe; |
66450a21 | 2067 | |
299018f4 | 2068 | if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) |
66450a21 JK |
2069 | return; |
2070 | ||
cd7764fe PB |
2071 | /* |
2072 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2073 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2074 | * and delay processing of INIT until the next RSM. | |
2075 | */ | |
2076 | if (is_smm(vcpu)) { | |
2077 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2078 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2079 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2080 | return; | |
2081 | } | |
299018f4 | 2082 | |
cd7764fe | 2083 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2084 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2085 | kvm_lapic_reset(vcpu, true); |
2086 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2087 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2088 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2089 | else | |
2090 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2091 | } | |
299018f4 | 2092 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2093 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2094 | /* evaluate pending_events before reading the vector */ | |
2095 | smp_rmb(); | |
2096 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2097 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2098 | vcpu->vcpu_id, sipi_vector); |
2099 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2100 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2101 | } | |
2102 | } | |
2103 | ||
c5cc421b GN |
2104 | void kvm_lapic_init(void) |
2105 | { | |
2106 | /* do not patch jump label more than once per second */ | |
2107 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2108 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2109 | } |