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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
1767e931 | 28 | #include <linux/export.h> |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
97222cc8 | 57 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ |
354cb410 | 58 | #define apic_debug(fmt, arg...) do {} while (0) |
97222cc8 | 59 | |
97222cc8 | 60 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 61 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
62 | #define LAPIC_MMIO_LENGTH (1 << 12) |
63 | /* followed define is not in apicdef.h */ | |
64 | #define APIC_SHORT_MASK 0xc0000 | |
65 | #define APIC_DEST_NOSHORT 0x0 | |
66 | #define APIC_DEST_MASK 0x800 | |
67 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 68 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 69 | |
394457a9 NA |
70 | #define APIC_BROADCAST 0xFF |
71 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
72 | ||
3b8a5df6 WL |
73 | static bool lapic_timer_advance_adjust_done = false; |
74 | #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100 | |
75 | /* step-by-step approximation to mitigate fluctuation */ | |
76 | #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8 | |
77 | ||
a0c9a822 MT |
78 | static inline int apic_test_vector(int vec, void *bitmap) |
79 | { | |
80 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
81 | } | |
82 | ||
10606919 YZ |
83 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
84 | { | |
85 | struct kvm_lapic *apic = vcpu->arch.apic; | |
86 | ||
87 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
88 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
89 | } | |
90 | ||
97222cc8 ED |
91 | static inline void apic_clear_vector(int vec, void *bitmap) |
92 | { | |
93 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
94 | } | |
95 | ||
8680b94b MT |
96 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
97 | { | |
98 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
99 | } | |
100 | ||
101 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
102 | { | |
103 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
104 | } | |
105 | ||
c5cc421b | 106 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
107 | struct static_key_deferred apic_sw_disabled __read_mostly; |
108 | ||
97222cc8 ED |
109 | static inline int apic_enabled(struct kvm_lapic *apic) |
110 | { | |
c48f1496 | 111 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
112 | } |
113 | ||
97222cc8 ED |
114 | #define LVT_MASK \ |
115 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
116 | ||
117 | #define LINT_MASK \ | |
118 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
119 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
120 | ||
6e500439 RK |
121 | static inline u8 kvm_xapic_id(struct kvm_lapic *apic) |
122 | { | |
123 | return kvm_lapic_get_reg(apic, APIC_ID) >> 24; | |
124 | } | |
125 | ||
126 | static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) | |
127 | { | |
128 | return apic->vcpu->vcpu_id; | |
129 | } | |
130 | ||
e45115b6 RK |
131 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
132 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
133 | switch (map->mode) { | |
134 | case KVM_APIC_MODE_X2APIC: { | |
135 | u32 offset = (dest_id >> 16) * 16; | |
0ca52e7b | 136 | u32 max_apic_id = map->max_apic_id; |
e45115b6 RK |
137 | |
138 | if (offset <= max_apic_id) { | |
139 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
140 | ||
141 | *cluster = &map->phys_map[offset]; | |
142 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
143 | } else { | |
144 | *mask = 0; | |
145 | } | |
3b5a5ffa | 146 | |
e45115b6 RK |
147 | return true; |
148 | } | |
149 | case KVM_APIC_MODE_XAPIC_FLAT: | |
150 | *cluster = map->xapic_flat_map; | |
151 | *mask = dest_id & 0xff; | |
152 | return true; | |
153 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
444fdad8 | 154 | *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; |
e45115b6 RK |
155 | *mask = dest_id & 0xf; |
156 | return true; | |
157 | default: | |
158 | /* Not optimized. */ | |
159 | return false; | |
160 | } | |
3548a259 RK |
161 | } |
162 | ||
af1bae54 | 163 | static void kvm_apic_map_free(struct rcu_head *rcu) |
3b5a5ffa | 164 | { |
af1bae54 | 165 | struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu); |
3b5a5ffa | 166 | |
af1bae54 | 167 | kvfree(map); |
3b5a5ffa RK |
168 | } |
169 | ||
1e08ec4a GN |
170 | static void recalculate_apic_map(struct kvm *kvm) |
171 | { | |
172 | struct kvm_apic_map *new, *old = NULL; | |
173 | struct kvm_vcpu *vcpu; | |
174 | int i; | |
6e500439 | 175 | u32 max_id = 255; /* enough space for any xAPIC ID */ |
1e08ec4a GN |
176 | |
177 | mutex_lock(&kvm->arch.apic_map_lock); | |
178 | ||
0ca52e7b RK |
179 | kvm_for_each_vcpu(i, vcpu, kvm) |
180 | if (kvm_apic_present(vcpu)) | |
6e500439 | 181 | max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); |
0ca52e7b | 182 | |
a7c3e901 | 183 | new = kvzalloc(sizeof(struct kvm_apic_map) + |
254272ce BG |
184 | sizeof(struct kvm_lapic *) * ((u64)max_id + 1), |
185 | GFP_KERNEL_ACCOUNT); | |
0ca52e7b | 186 | |
1e08ec4a GN |
187 | if (!new) |
188 | goto out; | |
189 | ||
0ca52e7b RK |
190 | new->max_apic_id = max_id; |
191 | ||
173beedc NA |
192 | kvm_for_each_vcpu(i, vcpu, kvm) { |
193 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
194 | struct kvm_lapic **cluster; |
195 | u16 mask; | |
5bd5db38 RK |
196 | u32 ldr; |
197 | u8 xapic_id; | |
198 | u32 x2apic_id; | |
1e08ec4a | 199 | |
df04d1d1 RK |
200 | if (!kvm_apic_present(vcpu)) |
201 | continue; | |
202 | ||
5bd5db38 RK |
203 | xapic_id = kvm_xapic_id(apic); |
204 | x2apic_id = kvm_x2apic_id(apic); | |
205 | ||
206 | /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */ | |
207 | if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && | |
208 | x2apic_id <= new->max_apic_id) | |
209 | new->phys_map[x2apic_id] = apic; | |
210 | /* | |
211 | * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, | |
212 | * prevent them from masking VCPUs with APIC ID <= 0xff. | |
213 | */ | |
214 | if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) | |
215 | new->phys_map[xapic_id] = apic; | |
3548a259 | 216 | |
6e500439 RK |
217 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
218 | ||
3b5a5ffa RK |
219 | if (apic_x2apic_mode(apic)) { |
220 | new->mode |= KVM_APIC_MODE_X2APIC; | |
221 | } else if (ldr) { | |
222 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 223 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
224 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
225 | else | |
226 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
227 | } | |
228 | ||
e45115b6 | 229 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
230 | continue; |
231 | ||
e45115b6 RK |
232 | if (mask) |
233 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
234 | } |
235 | out: | |
236 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
237 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
238 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
239 | mutex_unlock(&kvm->arch.apic_map_lock); | |
240 | ||
241 | if (old) | |
af1bae54 | 242 | call_rcu(&old->rcu, kvm_apic_map_free); |
c7c9c56c | 243 | |
b053b2ae | 244 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
245 | } |
246 | ||
1e1b6c26 NA |
247 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
248 | { | |
e462755c | 249 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 250 | |
1e6e2755 | 251 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
252 | |
253 | if (enabled != apic->sw_enabled) { | |
254 | apic->sw_enabled = enabled; | |
eb1ff0a9 | 255 | if (enabled) |
1e1b6c26 | 256 | static_key_slow_dec_deferred(&apic_sw_disabled); |
eb1ff0a9 | 257 | else |
1e1b6c26 NA |
258 | static_key_slow_inc(&apic_sw_disabled.key); |
259 | } | |
260 | } | |
261 | ||
a92e2543 | 262 | static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) |
1e08ec4a | 263 | { |
1e6e2755 | 264 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
265 | recalculate_apic_map(apic->vcpu->kvm); |
266 | } | |
267 | ||
268 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
269 | { | |
1e6e2755 | 270 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
271 | recalculate_apic_map(apic->vcpu->kvm); |
272 | } | |
273 | ||
e872fa94 DDAG |
274 | static inline u32 kvm_apic_calc_x2apic_ldr(u32 id) |
275 | { | |
276 | return ((id >> 4) << 16) | (1 << (id & 0xf)); | |
277 | } | |
278 | ||
a92e2543 | 279 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) |
257b9a5f | 280 | { |
e872fa94 | 281 | u32 ldr = kvm_apic_calc_x2apic_ldr(id); |
257b9a5f | 282 | |
6e500439 RK |
283 | WARN_ON_ONCE(id != apic->vcpu->vcpu_id); |
284 | ||
a92e2543 | 285 | kvm_lapic_set_reg(apic, APIC_ID, id); |
1e6e2755 | 286 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); |
257b9a5f RK |
287 | recalculate_apic_map(apic->vcpu->kvm); |
288 | } | |
289 | ||
97222cc8 ED |
290 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
291 | { | |
dfb95954 | 292 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
293 | } |
294 | ||
295 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
296 | { | |
dfb95954 | 297 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
298 | } |
299 | ||
a3e06bbe LJ |
300 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
301 | { | |
f30ebc31 | 302 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
303 | } |
304 | ||
97222cc8 ED |
305 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
306 | { | |
f30ebc31 | 307 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
308 | } |
309 | ||
310 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
311 | { | |
f30ebc31 | 312 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
313 | } |
314 | ||
cc6e462c JK |
315 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
316 | { | |
317 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
318 | } | |
319 | ||
fc61b800 GN |
320 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
321 | { | |
322 | struct kvm_lapic *apic = vcpu->arch.apic; | |
323 | struct kvm_cpuid_entry2 *feat; | |
324 | u32 v = APIC_VERSION; | |
325 | ||
bce87cce | 326 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
327 | return; |
328 | ||
0bcc3fb9 VK |
329 | /* |
330 | * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) | |
331 | * which doesn't have EOI register; Some buggy OSes (e.g. Windows with | |
332 | * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC | |
333 | * version first and level-triggered interrupts never get EOIed in | |
334 | * IOAPIC. | |
335 | */ | |
fc61b800 | 336 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); |
0bcc3fb9 VK |
337 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) && |
338 | !ioapic_in_kernel(vcpu->kvm)) | |
fc61b800 | 339 | v |= APIC_LVR_DIRECTED_EOI; |
1e6e2755 | 340 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
341 | } |
342 | ||
1e6e2755 | 343 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 344 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
345 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
346 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
347 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
348 | LVT_MASK /* LVTERR */ | |
349 | }; | |
350 | ||
351 | static int find_highest_vector(void *bitmap) | |
352 | { | |
ecba9a52 TY |
353 | int vec; |
354 | u32 *reg; | |
97222cc8 | 355 | |
ecba9a52 TY |
356 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
357 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
358 | reg = bitmap + REG_POS(vec); | |
359 | if (*reg) | |
810e6def | 360 | return __fls(*reg) + vec; |
ecba9a52 | 361 | } |
97222cc8 | 362 | |
ecba9a52 | 363 | return -1; |
97222cc8 ED |
364 | } |
365 | ||
8680b94b MT |
366 | static u8 count_vectors(void *bitmap) |
367 | { | |
ecba9a52 TY |
368 | int vec; |
369 | u32 *reg; | |
8680b94b | 370 | u8 count = 0; |
ecba9a52 TY |
371 | |
372 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
373 | reg = bitmap + REG_POS(vec); | |
374 | count += hweight32(*reg); | |
375 | } | |
376 | ||
8680b94b MT |
377 | return count; |
378 | } | |
379 | ||
e7387b0e | 380 | bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) |
a20ed54d | 381 | { |
810e6def | 382 | u32 i, vec; |
e7387b0e LA |
383 | u32 pir_val, irr_val, prev_irr_val; |
384 | int max_updated_irr; | |
385 | ||
386 | max_updated_irr = -1; | |
387 | *max_irr = -1; | |
a20ed54d | 388 | |
810e6def | 389 | for (i = vec = 0; i <= 7; i++, vec += 32) { |
ad361091 | 390 | pir_val = READ_ONCE(pir[i]); |
810e6def | 391 | irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10)); |
ad361091 | 392 | if (pir_val) { |
e7387b0e | 393 | prev_irr_val = irr_val; |
810e6def PB |
394 | irr_val |= xchg(&pir[i], 0); |
395 | *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val; | |
e7387b0e LA |
396 | if (prev_irr_val != irr_val) { |
397 | max_updated_irr = | |
398 | __fls(irr_val ^ prev_irr_val) + vec; | |
399 | } | |
ad361091 | 400 | } |
810e6def | 401 | if (irr_val) |
e7387b0e | 402 | *max_irr = __fls(irr_val) + vec; |
a20ed54d | 403 | } |
810e6def | 404 | |
e7387b0e LA |
405 | return ((max_updated_irr != -1) && |
406 | (max_updated_irr == *max_irr)); | |
a20ed54d | 407 | } |
705699a1 WV |
408 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
409 | ||
e7387b0e | 410 | bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr) |
705699a1 WV |
411 | { |
412 | struct kvm_lapic *apic = vcpu->arch.apic; | |
413 | ||
e7387b0e | 414 | return __kvm_apic_update_irr(pir, apic->regs, max_irr); |
705699a1 | 415 | } |
a20ed54d YZ |
416 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
417 | ||
33e4c686 | 418 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 419 | { |
33e4c686 | 420 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
421 | } |
422 | ||
423 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
424 | { | |
425 | int result; | |
426 | ||
c7c9c56c YZ |
427 | /* |
428 | * Note that irr_pending is just a hint. It will be always | |
429 | * true with virtual interrupt delivery enabled. | |
430 | */ | |
33e4c686 GN |
431 | if (!apic->irr_pending) |
432 | return -1; | |
433 | ||
434 | result = apic_search_irr(apic); | |
97222cc8 ED |
435 | ASSERT(result == -1 || result >= 16); |
436 | ||
437 | return result; | |
438 | } | |
439 | ||
33e4c686 GN |
440 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
441 | { | |
56cc2406 WL |
442 | struct kvm_vcpu *vcpu; |
443 | ||
444 | vcpu = apic->vcpu; | |
445 | ||
d62caabb | 446 | if (unlikely(vcpu->arch.apicv_active)) { |
b95234c8 | 447 | /* need to update RVI */ |
f210f757 | 448 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
b95234c8 PB |
449 | kvm_x86_ops->hwapic_irr_update(vcpu, |
450 | apic_find_highest_irr(apic)); | |
f210f757 NA |
451 | } else { |
452 | apic->irr_pending = false; | |
453 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
454 | if (apic_search_irr(apic) != -1) | |
455 | apic->irr_pending = true; | |
56cc2406 | 456 | } |
33e4c686 GN |
457 | } |
458 | ||
8680b94b MT |
459 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
460 | { | |
56cc2406 WL |
461 | struct kvm_vcpu *vcpu; |
462 | ||
463 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
464 | return; | |
465 | ||
466 | vcpu = apic->vcpu; | |
fc57ac2c | 467 | |
8680b94b | 468 | /* |
56cc2406 WL |
469 | * With APIC virtualization enabled, all caching is disabled |
470 | * because the processor can modify ISR under the hood. Instead | |
471 | * just set SVI. | |
8680b94b | 472 | */ |
d62caabb | 473 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 474 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
475 | else { |
476 | ++apic->isr_count; | |
477 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
478 | /* | |
479 | * ISR (in service register) bit is set when injecting an interrupt. | |
480 | * The highest vector is injected. Thus the latest bit set matches | |
481 | * the highest bit in ISR. | |
482 | */ | |
483 | apic->highest_isr_cache = vec; | |
484 | } | |
8680b94b MT |
485 | } |
486 | ||
fc57ac2c PB |
487 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
488 | { | |
489 | int result; | |
490 | ||
491 | /* | |
492 | * Note that isr_count is always 1, and highest_isr_cache | |
493 | * is always -1, with APIC virtualization enabled. | |
494 | */ | |
495 | if (!apic->isr_count) | |
496 | return -1; | |
497 | if (likely(apic->highest_isr_cache != -1)) | |
498 | return apic->highest_isr_cache; | |
499 | ||
500 | result = find_highest_vector(apic->regs + APIC_ISR); | |
501 | ASSERT(result == -1 || result >= 16); | |
502 | ||
503 | return result; | |
504 | } | |
505 | ||
8680b94b MT |
506 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
507 | { | |
fc57ac2c PB |
508 | struct kvm_vcpu *vcpu; |
509 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
510 | return; | |
511 | ||
512 | vcpu = apic->vcpu; | |
513 | ||
514 | /* | |
515 | * We do get here for APIC virtualization enabled if the guest | |
516 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
517 | * to trigger a new interrupt delivery by writing the SVI field; | |
518 | * on the other hand isr_count and highest_isr_cache are unused | |
519 | * and must be left alone. | |
520 | */ | |
d62caabb | 521 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 522 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
523 | apic_find_highest_isr(apic)); |
524 | else { | |
8680b94b | 525 | --apic->isr_count; |
fc57ac2c PB |
526 | BUG_ON(apic->isr_count < 0); |
527 | apic->highest_isr_cache = -1; | |
528 | } | |
8680b94b MT |
529 | } |
530 | ||
6e5d865c YS |
531 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
532 | { | |
33e4c686 GN |
533 | /* This may race with setting of irr in __apic_accept_irq() and |
534 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
535 | * will cause vmexit immediately and the value will be recalculated | |
536 | * on the next vmentry. | |
537 | */ | |
f8543d6a | 538 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 539 | } |
76dfafd5 | 540 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); |
6e5d865c | 541 | |
6da7e3f6 | 542 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 543 | int vector, int level, int trig_mode, |
9e4aabe2 | 544 | struct dest_map *dest_map); |
6da7e3f6 | 545 | |
b4f2225c | 546 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 547 | struct dest_map *dest_map) |
97222cc8 | 548 | { |
ad312c7c | 549 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 550 | |
58c2dde1 | 551 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 552 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
553 | } |
554 | ||
4180bf1b | 555 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 556 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
557 | unsigned long icr, int op_64_bit) |
558 | { | |
559 | int i; | |
560 | struct kvm_apic_map *map; | |
561 | struct kvm_vcpu *vcpu; | |
562 | struct kvm_lapic_irq irq = {0}; | |
563 | int cluster_size = op_64_bit ? 64 : 32; | |
564 | int count = 0; | |
565 | ||
566 | irq.vector = icr & APIC_VECTOR_MASK; | |
567 | irq.delivery_mode = icr & APIC_MODE_MASK; | |
568 | irq.level = (icr & APIC_INT_ASSERT) != 0; | |
569 | irq.trig_mode = icr & APIC_INT_LEVELTRIG; | |
570 | ||
571 | if (icr & APIC_DEST_MASK) | |
572 | return -KVM_EINVAL; | |
573 | if (icr & APIC_SHORT_MASK) | |
574 | return -KVM_EINVAL; | |
575 | ||
576 | rcu_read_lock(); | |
577 | map = rcu_dereference(kvm->arch.apic_map); | |
578 | ||
38ab012f WL |
579 | if (unlikely(!map)) { |
580 | count = -EOPNOTSUPP; | |
581 | goto out; | |
582 | } | |
583 | ||
bdf7ffc8 WL |
584 | if (min > map->max_apic_id) |
585 | goto out; | |
4180bf1b | 586 | /* Bits above cluster_size are masked in the caller. */ |
bdf7ffc8 WL |
587 | for_each_set_bit(i, &ipi_bitmap_low, |
588 | min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { | |
589 | if (map->phys_map[min + i]) { | |
590 | vcpu = map->phys_map[min + i]->vcpu; | |
591 | count += kvm_apic_set_irq(vcpu, &irq, NULL); | |
592 | } | |
4180bf1b WL |
593 | } |
594 | ||
595 | min += cluster_size; | |
bdf7ffc8 WL |
596 | |
597 | if (min > map->max_apic_id) | |
598 | goto out; | |
599 | ||
600 | for_each_set_bit(i, &ipi_bitmap_high, | |
601 | min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { | |
602 | if (map->phys_map[min + i]) { | |
603 | vcpu = map->phys_map[min + i]->vcpu; | |
604 | count += kvm_apic_set_irq(vcpu, &irq, NULL); | |
605 | } | |
4180bf1b WL |
606 | } |
607 | ||
bdf7ffc8 | 608 | out: |
4180bf1b WL |
609 | rcu_read_unlock(); |
610 | return count; | |
611 | } | |
612 | ||
ae7a2a3f MT |
613 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
614 | { | |
4e335d9e PB |
615 | |
616 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
617 | sizeof(val)); | |
ae7a2a3f MT |
618 | } |
619 | ||
620 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
621 | { | |
4e335d9e PB |
622 | |
623 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
624 | sizeof(*val)); | |
ae7a2a3f MT |
625 | } |
626 | ||
627 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
628 | { | |
629 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
630 | } | |
631 | ||
632 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
633 | { | |
634 | u8 val; | |
635 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
636 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 637 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
638 | return val & 0x1; |
639 | } | |
640 | ||
641 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
642 | { | |
643 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
644 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 645 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
646 | return; |
647 | } | |
648 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
649 | } | |
650 | ||
651 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
652 | { | |
653 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
654 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 655 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
656 | return; |
657 | } | |
658 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
659 | } | |
660 | ||
b3c045d3 PB |
661 | static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) |
662 | { | |
3d92789f | 663 | int highest_irr; |
fa59cc00 | 664 | if (apic->vcpu->arch.apicv_active) |
76dfafd5 PB |
665 | highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu); |
666 | else | |
667 | highest_irr = apic_find_highest_irr(apic); | |
b3c045d3 PB |
668 | if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) |
669 | return -1; | |
670 | return highest_irr; | |
671 | } | |
672 | ||
673 | static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) | |
97222cc8 | 674 | { |
3842d135 | 675 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
676 | int isr; |
677 | ||
dfb95954 SS |
678 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
679 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
680 | isr = apic_find_highest_isr(apic); |
681 | isrv = (isr != -1) ? isr : 0; | |
682 | ||
683 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
684 | ppr = tpr & 0xff; | |
685 | else | |
686 | ppr = isrv & 0xf0; | |
687 | ||
688 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
689 | apic, ppr, isr, isrv); | |
690 | ||
b3c045d3 PB |
691 | *new_ppr = ppr; |
692 | if (old_ppr != ppr) | |
1e6e2755 | 693 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
b3c045d3 PB |
694 | |
695 | return ppr < old_ppr; | |
696 | } | |
697 | ||
698 | static void apic_update_ppr(struct kvm_lapic *apic) | |
699 | { | |
700 | u32 ppr; | |
701 | ||
26fbbee5 PB |
702 | if (__apic_update_ppr(apic, &ppr) && |
703 | apic_has_interrupt_for_ppr(apic, ppr) != -1) | |
b3c045d3 | 704 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
97222cc8 ED |
705 | } |
706 | ||
eb90f341 PB |
707 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu) |
708 | { | |
709 | apic_update_ppr(vcpu->arch.apic); | |
710 | } | |
711 | EXPORT_SYMBOL_GPL(kvm_apic_update_ppr); | |
712 | ||
97222cc8 ED |
713 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) |
714 | { | |
1e6e2755 | 715 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
716 | apic_update_ppr(apic); |
717 | } | |
718 | ||
03d2249e | 719 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 720 | { |
b4535b58 RK |
721 | return mda == (apic_x2apic_mode(apic) ? |
722 | X2APIC_BROADCAST : APIC_BROADCAST); | |
394457a9 NA |
723 | } |
724 | ||
03d2249e | 725 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 726 | { |
03d2249e RK |
727 | if (kvm_apic_broadcast(apic, mda)) |
728 | return true; | |
729 | ||
730 | if (apic_x2apic_mode(apic)) | |
6e500439 | 731 | return mda == kvm_x2apic_id(apic); |
03d2249e | 732 | |
5bd5db38 RK |
733 | /* |
734 | * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if | |
735 | * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and | |
736 | * this allows unique addressing of VCPUs with APIC ID over 0xff. | |
737 | * The 0xff condition is needed because writeable xAPIC ID. | |
738 | */ | |
739 | if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) | |
740 | return true; | |
741 | ||
b4535b58 | 742 | return mda == kvm_xapic_id(apic); |
97222cc8 ED |
743 | } |
744 | ||
52c233a4 | 745 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 746 | { |
0105d1a5 GN |
747 | u32 logical_id; |
748 | ||
394457a9 | 749 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 750 | return true; |
394457a9 | 751 | |
dfb95954 | 752 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 753 | |
9368b567 | 754 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
755 | return ((logical_id >> 16) == (mda >> 16)) |
756 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 757 | |
9368b567 | 758 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
97222cc8 | 759 | |
dfb95954 | 760 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 761 | case APIC_DFR_FLAT: |
9368b567 | 762 | return (logical_id & mda) != 0; |
97222cc8 | 763 | case APIC_DFR_CLUSTER: |
9368b567 RK |
764 | return ((logical_id >> 4) == (mda >> 4)) |
765 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 766 | default: |
7712de87 | 767 | apic_debug("Bad DFR vcpu %d: %08x\n", |
dfb95954 | 768 | apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); |
9368b567 | 769 | return false; |
97222cc8 | 770 | } |
97222cc8 ED |
771 | } |
772 | ||
c519265f RK |
773 | /* The KVM local APIC implementation has two quirks: |
774 | * | |
b4535b58 RK |
775 | * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs |
776 | * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID. | |
777 | * KVM doesn't do that aliasing. | |
c519265f RK |
778 | * |
779 | * - in-kernel IOAPIC messages have to be delivered directly to | |
780 | * x2APIC, because the kernel does not support interrupt remapping. | |
781 | * In order to support broadcast without interrupt remapping, x2APIC | |
782 | * rewrites the destination of non-IPI messages from APIC_BROADCAST | |
783 | * to X2APIC_BROADCAST. | |
784 | * | |
785 | * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is | |
786 | * important when userspace wants to use x2APIC-format MSIs, because | |
787 | * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7". | |
03d2249e | 788 | */ |
c519265f RK |
789 | static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id, |
790 | struct kvm_lapic *source, struct kvm_lapic *target) | |
03d2249e RK |
791 | { |
792 | bool ipi = source != NULL; | |
03d2249e | 793 | |
c519265f | 794 | if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && |
b4535b58 | 795 | !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) |
03d2249e RK |
796 | return X2APIC_BROADCAST; |
797 | ||
b4535b58 | 798 | return dest_id; |
03d2249e RK |
799 | } |
800 | ||
52c233a4 | 801 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 802 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 803 | { |
ad312c7c | 804 | struct kvm_lapic *target = vcpu->arch.apic; |
c519265f | 805 | u32 mda = kvm_apic_mda(vcpu, dest, source, target); |
97222cc8 ED |
806 | |
807 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 808 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
809 | target, source, dest, dest_mode, short_hand); |
810 | ||
bd371396 | 811 | ASSERT(target); |
97222cc8 ED |
812 | switch (short_hand) { |
813 | case APIC_DEST_NOSHORT: | |
3697f302 | 814 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 815 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 816 | else |
03d2249e | 817 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 818 | case APIC_DEST_SELF: |
9368b567 | 819 | return target == source; |
97222cc8 | 820 | case APIC_DEST_ALLINC: |
9368b567 | 821 | return true; |
97222cc8 | 822 | case APIC_DEST_ALLBUT: |
9368b567 | 823 | return target != source; |
97222cc8 | 824 | default: |
7712de87 JK |
825 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
826 | short_hand); | |
9368b567 | 827 | return false; |
97222cc8 | 828 | } |
97222cc8 | 829 | } |
1e6e2755 | 830 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 831 | |
52004014 FW |
832 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
833 | const unsigned long *bitmap, u32 bitmap_size) | |
834 | { | |
835 | u32 mod; | |
836 | int i, idx = -1; | |
837 | ||
838 | mod = vector % dest_vcpus; | |
839 | ||
840 | for (i = 0; i <= mod; i++) { | |
841 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
842 | BUG_ON(idx == bitmap_size); | |
843 | } | |
844 | ||
845 | return idx; | |
846 | } | |
847 | ||
4efd805f RK |
848 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
849 | { | |
850 | if (!kvm->arch.disabled_lapic_found) { | |
851 | kvm->arch.disabled_lapic_found = true; | |
852 | printk(KERN_INFO | |
853 | "Disabled LAPIC found during irq injection\n"); | |
854 | } | |
855 | } | |
856 | ||
c519265f RK |
857 | static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src, |
858 | struct kvm_lapic_irq *irq, struct kvm_apic_map *map) | |
1e08ec4a | 859 | { |
c519265f RK |
860 | if (kvm->arch.x2apic_broadcast_quirk_disabled) { |
861 | if ((irq->dest_id == APIC_BROADCAST && | |
862 | map->mode != KVM_APIC_MODE_X2APIC)) | |
863 | return true; | |
864 | if (irq->dest_id == X2APIC_BROADCAST) | |
865 | return true; | |
866 | } else { | |
867 | bool x2apic_ipi = src && *src && apic_x2apic_mode(*src); | |
868 | if (irq->dest_id == (x2apic_ipi ? | |
869 | X2APIC_BROADCAST : APIC_BROADCAST)) | |
870 | return true; | |
871 | } | |
1e08ec4a | 872 | |
c519265f RK |
873 | return false; |
874 | } | |
1e08ec4a | 875 | |
64aa47bf RK |
876 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
877 | * for valid destinations in *dst array. | |
878 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
879 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
880 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
881 | * zero and *dst undefined. | |
882 | */ | |
883 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
884 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
885 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
886 | unsigned long *bitmap) | |
887 | { | |
888 | int i, lowest; | |
1e08ec4a | 889 | |
64aa47bf RK |
890 | if (irq->shorthand == APIC_DEST_SELF && src) { |
891 | *dst = src; | |
892 | *bitmap = 1; | |
893 | return true; | |
894 | } else if (irq->shorthand) | |
1e08ec4a GN |
895 | return false; |
896 | ||
c519265f | 897 | if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map)) |
9ea369b0 RK |
898 | return false; |
899 | ||
64aa47bf | 900 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
0ca52e7b | 901 | if (irq->dest_id > map->max_apic_id) { |
64aa47bf RK |
902 | *bitmap = 0; |
903 | } else { | |
904 | *dst = &map->phys_map[irq->dest_id]; | |
905 | *bitmap = 1; | |
906 | } | |
1e08ec4a | 907 | return true; |
bea15428 | 908 | } |
698f9755 | 909 | |
e45115b6 RK |
910 | *bitmap = 0; |
911 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
912 | (u16 *)bitmap)) | |
1e08ec4a | 913 | return false; |
fa834e91 | 914 | |
64aa47bf RK |
915 | if (!kvm_lowest_prio_delivery(irq)) |
916 | return true; | |
3548a259 | 917 | |
64aa47bf RK |
918 | if (!kvm_vector_hashing_enabled()) { |
919 | lowest = -1; | |
920 | for_each_set_bit(i, bitmap, 16) { | |
921 | if (!(*dst)[i]) | |
922 | continue; | |
923 | if (lowest < 0) | |
924 | lowest = i; | |
925 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
926 | (*dst)[lowest]->vcpu) < 0) | |
927 | lowest = i; | |
3548a259 | 928 | } |
64aa47bf RK |
929 | } else { |
930 | if (!*bitmap) | |
931 | return true; | |
3548a259 | 932 | |
64aa47bf RK |
933 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
934 | bitmap, 16); | |
45c3094a | 935 | |
64aa47bf RK |
936 | if (!(*dst)[lowest]) { |
937 | kvm_apic_disabled_lapic_found(kvm); | |
938 | *bitmap = 0; | |
939 | return true; | |
940 | } | |
941 | } | |
1e08ec4a | 942 | |
64aa47bf | 943 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 944 | |
64aa47bf RK |
945 | return true; |
946 | } | |
52004014 | 947 | |
64aa47bf RK |
948 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
949 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
950 | { | |
951 | struct kvm_apic_map *map; | |
952 | unsigned long bitmap; | |
953 | struct kvm_lapic **dst = NULL; | |
954 | int i; | |
955 | bool ret; | |
52004014 | 956 | |
64aa47bf | 957 | *r = -1; |
52004014 | 958 | |
64aa47bf RK |
959 | if (irq->shorthand == APIC_DEST_SELF) { |
960 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
961 | return true; | |
962 | } | |
52004014 | 963 | |
64aa47bf RK |
964 | rcu_read_lock(); |
965 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 966 | |
64aa47bf | 967 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
0624fca9 PB |
968 | if (ret) { |
969 | *r = 0; | |
64aa47bf RK |
970 | for_each_set_bit(i, &bitmap, 16) { |
971 | if (!dst[i]) | |
972 | continue; | |
64aa47bf | 973 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 974 | } |
0624fca9 | 975 | } |
1e08ec4a | 976 | |
1e08ec4a GN |
977 | rcu_read_unlock(); |
978 | return ret; | |
979 | } | |
980 | ||
6228a0da FW |
981 | /* |
982 | * This routine tries to handler interrupts in posted mode, here is how | |
983 | * it deals with different cases: | |
984 | * - For single-destination interrupts, handle it in posted mode | |
985 | * - Else if vector hashing is enabled and it is a lowest-priority | |
986 | * interrupt, handle it in posted mode and use the following mechanism | |
987 | * to find the destinaiton vCPU. | |
988 | * 1. For lowest-priority interrupts, store all the possible | |
989 | * destination vCPUs in an array. | |
990 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
991 | * the right destination vCPU in the array for the lowest-priority | |
992 | * interrupt. | |
993 | * - Otherwise, use remapped mode to inject the interrupt. | |
994 | */ | |
8feb4a04 FW |
995 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
996 | struct kvm_vcpu **dest_vcpu) | |
997 | { | |
998 | struct kvm_apic_map *map; | |
64aa47bf RK |
999 | unsigned long bitmap; |
1000 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 1001 | bool ret = false; |
8feb4a04 FW |
1002 | |
1003 | if (irq->shorthand) | |
1004 | return false; | |
1005 | ||
1006 | rcu_read_lock(); | |
1007 | map = rcu_dereference(kvm->arch.apic_map); | |
1008 | ||
64aa47bf RK |
1009 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
1010 | hweight16(bitmap) == 1) { | |
1011 | unsigned long i = find_first_bit(&bitmap, 16); | |
6228a0da | 1012 | |
64aa47bf RK |
1013 | if (dst[i]) { |
1014 | *dest_vcpu = dst[i]->vcpu; | |
1015 | ret = true; | |
6228a0da | 1016 | } |
8feb4a04 FW |
1017 | } |
1018 | ||
8feb4a04 FW |
1019 | rcu_read_unlock(); |
1020 | return ret; | |
1021 | } | |
1022 | ||
97222cc8 ED |
1023 | /* |
1024 | * Add a pending IRQ into lapic. | |
1025 | * Return 1 if successfully added and 0 if discarded. | |
1026 | */ | |
1027 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 1028 | int vector, int level, int trig_mode, |
9e4aabe2 | 1029 | struct dest_map *dest_map) |
97222cc8 | 1030 | { |
6da7e3f6 | 1031 | int result = 0; |
c5ec1534 | 1032 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 1033 | |
a183b638 PB |
1034 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
1035 | trig_mode, vector); | |
97222cc8 | 1036 | switch (delivery_mode) { |
97222cc8 | 1037 | case APIC_DM_LOWEST: |
e1035715 | 1038 | vcpu->arch.apic_arb_prio++; |
b2869f28 | 1039 | /* fall through */ |
e1035715 | 1040 | case APIC_DM_FIXED: |
bdaffe1d PB |
1041 | if (unlikely(trig_mode && !level)) |
1042 | break; | |
1043 | ||
97222cc8 ED |
1044 | /* FIXME add logic for vcpu on reset */ |
1045 | if (unlikely(!apic_enabled(apic))) | |
1046 | break; | |
1047 | ||
11f5cc05 JK |
1048 | result = 1; |
1049 | ||
9daa5007 | 1050 | if (dest_map) { |
9e4aabe2 | 1051 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
1052 | dest_map->vectors[vcpu->vcpu_id] = vector; |
1053 | } | |
a5d36f82 | 1054 | |
bdaffe1d PB |
1055 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
1056 | if (trig_mode) | |
1e6e2755 | 1057 | kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); |
bdaffe1d PB |
1058 | else |
1059 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
1060 | } | |
1061 | ||
d62caabb | 1062 | if (vcpu->arch.apicv_active) |
5a71785d | 1063 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 1064 | else { |
1e6e2755 | 1065 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
1066 | |
1067 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1068 | kvm_vcpu_kick(vcpu); | |
1069 | } | |
97222cc8 ED |
1070 | break; |
1071 | ||
1072 | case APIC_DM_REMRD: | |
24d2166b R |
1073 | result = 1; |
1074 | vcpu->arch.pv.pv_unhalted = 1; | |
1075 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1076 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1077 | break; |
1078 | ||
1079 | case APIC_DM_SMI: | |
64d60670 PB |
1080 | result = 1; |
1081 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
1082 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 1083 | break; |
3419ffc8 | 1084 | |
97222cc8 | 1085 | case APIC_DM_NMI: |
6da7e3f6 | 1086 | result = 1; |
3419ffc8 | 1087 | kvm_inject_nmi(vcpu); |
26df99c6 | 1088 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
1089 | break; |
1090 | ||
1091 | case APIC_DM_INIT: | |
a52315e1 | 1092 | if (!trig_mode || level) { |
6da7e3f6 | 1093 | result = 1; |
66450a21 JK |
1094 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
1095 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
1096 | /* make sure pending_events is visible before sending | |
1097 | * the request */ | |
1098 | smp_wmb(); | |
3842d135 | 1099 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
1100 | kvm_vcpu_kick(vcpu); |
1101 | } else { | |
1b10bf31 JK |
1102 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
1103 | vcpu->vcpu_id); | |
c5ec1534 | 1104 | } |
97222cc8 ED |
1105 | break; |
1106 | ||
1107 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
1108 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
1109 | vcpu->vcpu_id, vector); | |
66450a21 JK |
1110 | result = 1; |
1111 | apic->sipi_vector = vector; | |
1112 | /* make sure sipi_vector is visible for the receiver */ | |
1113 | smp_wmb(); | |
1114 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
1115 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
1116 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
1117 | break; |
1118 | ||
23930f95 JK |
1119 | case APIC_DM_EXTINT: |
1120 | /* | |
1121 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
1122 | * before NMI watchdog was enabled. Already handled by | |
1123 | * kvm_apic_accept_pic_intr(). | |
1124 | */ | |
1125 | break; | |
1126 | ||
97222cc8 ED |
1127 | default: |
1128 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
1129 | delivery_mode); | |
1130 | break; | |
1131 | } | |
1132 | return result; | |
1133 | } | |
1134 | ||
e1035715 | 1135 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 1136 | { |
e1035715 | 1137 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
1138 | } |
1139 | ||
3bb345f3 PB |
1140 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
1141 | { | |
6308630b | 1142 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
1143 | } |
1144 | ||
c7c9c56c YZ |
1145 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
1146 | { | |
7543a635 SR |
1147 | int trigger_mode; |
1148 | ||
1149 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
1150 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
1151 | return; | |
3bb345f3 | 1152 | |
7543a635 SR |
1153 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
1154 | if (irqchip_split(apic->vcpu->kvm)) { | |
1155 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
1156 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
1157 | return; | |
c7c9c56c | 1158 | } |
7543a635 SR |
1159 | |
1160 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
1161 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
1162 | else | |
1163 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1164 | ||
1165 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
1166 | } |
1167 | ||
ae7a2a3f | 1168 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
1169 | { |
1170 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
1171 | |
1172 | trace_kvm_eoi(apic, vector); | |
1173 | ||
97222cc8 ED |
1174 | /* |
1175 | * Not every write EOI will has corresponding ISR, | |
1176 | * one example is when Kernel check timer on setup_IO_APIC | |
1177 | */ | |
1178 | if (vector == -1) | |
ae7a2a3f | 1179 | return vector; |
97222cc8 | 1180 | |
8680b94b | 1181 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1182 | apic_update_ppr(apic); |
1183 | ||
5c919412 AS |
1184 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
1185 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
1186 | ||
c7c9c56c | 1187 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1188 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1189 | return vector; |
97222cc8 ED |
1190 | } |
1191 | ||
c7c9c56c YZ |
1192 | /* |
1193 | * this interface assumes a trap-like exit, which has already finished | |
1194 | * desired side effect including vISR and vPPR update. | |
1195 | */ | |
1196 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1197 | { | |
1198 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1199 | ||
1200 | trace_kvm_eoi(apic, vector); | |
1201 | ||
1202 | kvm_ioapic_send_eoi(apic, vector); | |
1203 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1204 | } | |
1205 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1206 | ||
97222cc8 ED |
1207 | static void apic_send_ipi(struct kvm_lapic *apic) |
1208 | { | |
dfb95954 SS |
1209 | u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); |
1210 | u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1211 | struct kvm_lapic_irq irq; |
97222cc8 | 1212 | |
58c2dde1 GN |
1213 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1214 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1215 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1216 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1217 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1218 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1219 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1220 | if (apic_x2apic_mode(apic)) |
1221 | irq.dest_id = icr_high; | |
1222 | else | |
1223 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1224 | |
1000ff8d GN |
1225 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1226 | ||
97222cc8 ED |
1227 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1228 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1229 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1230 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1231 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1232 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1233 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1234 | |
b4f2225c | 1235 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1236 | } |
1237 | ||
1238 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1239 | { | |
8003c9ae | 1240 | ktime_t remaining, now; |
b682b814 | 1241 | s64 ns; |
9da8f4e8 | 1242 | u32 tmcct; |
97222cc8 ED |
1243 | |
1244 | ASSERT(apic != NULL); | |
1245 | ||
9da8f4e8 | 1246 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1247 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1248 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1249 | return 0; |
1250 | ||
5587859f | 1251 | now = ktime_get(); |
8003c9ae | 1252 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); |
b682b814 | 1253 | if (ktime_to_ns(remaining) < 0) |
8b0e1953 | 1254 | remaining = 0; |
b682b814 | 1255 | |
d3c7b77d MT |
1256 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1257 | tmcct = div64_u64(ns, | |
1258 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1259 | |
1260 | return tmcct; | |
1261 | } | |
1262 | ||
b209749f AK |
1263 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1264 | { | |
1265 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1266 | struct kvm_run *run = vcpu->run; | |
1267 | ||
a8eeb04a | 1268 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1269 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1270 | run->tpr_access.is_write = write; |
1271 | } | |
1272 | ||
1273 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1274 | { | |
1275 | if (apic->vcpu->arch.tpr_access_reporting) | |
1276 | __report_tpr_access(apic, write); | |
1277 | } | |
1278 | ||
97222cc8 ED |
1279 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1280 | { | |
1281 | u32 val = 0; | |
1282 | ||
1283 | if (offset >= LAPIC_MMIO_LENGTH) | |
1284 | return 0; | |
1285 | ||
1286 | switch (offset) { | |
1287 | case APIC_ARBPRI: | |
7712de87 | 1288 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1289 | break; |
1290 | ||
1291 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1292 | if (apic_lvtt_tscdeadline(apic)) |
1293 | return 0; | |
1294 | ||
97222cc8 ED |
1295 | val = apic_get_tmcct(apic); |
1296 | break; | |
4a4541a4 AK |
1297 | case APIC_PROCPRI: |
1298 | apic_update_ppr(apic); | |
dfb95954 | 1299 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1300 | break; |
b209749f AK |
1301 | case APIC_TASKPRI: |
1302 | report_tpr_access(apic, false); | |
1303 | /* fall thru */ | |
97222cc8 | 1304 | default: |
dfb95954 | 1305 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1306 | break; |
1307 | } | |
1308 | ||
1309 | return val; | |
1310 | } | |
1311 | ||
d76685c4 GH |
1312 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1313 | { | |
1314 | return container_of(dev, struct kvm_lapic, dev); | |
1315 | } | |
1316 | ||
1e6e2755 | 1317 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1318 | void *data) |
97222cc8 | 1319 | { |
97222cc8 ED |
1320 | unsigned char alignment = offset & 0xf; |
1321 | u32 result; | |
d5b0b5b1 | 1322 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1323 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1324 | |
1325 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1326 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1327 | offset, len); | |
0105d1a5 | 1328 | return 1; |
97222cc8 | 1329 | } |
0105d1a5 GN |
1330 | |
1331 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1332 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1333 | offset); | |
0105d1a5 GN |
1334 | return 1; |
1335 | } | |
1336 | ||
97222cc8 ED |
1337 | result = __apic_read(apic, offset & ~0xf); |
1338 | ||
229456fc MT |
1339 | trace_kvm_apic_read(offset, result); |
1340 | ||
97222cc8 ED |
1341 | switch (len) { |
1342 | case 1: | |
1343 | case 2: | |
1344 | case 4: | |
1345 | memcpy(data, (char *)&result + alignment, len); | |
1346 | break; | |
1347 | default: | |
1348 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1349 | "should be 1,2, or 4 instead\n", len); | |
1350 | break; | |
1351 | } | |
bda9020e | 1352 | return 0; |
97222cc8 | 1353 | } |
1e6e2755 | 1354 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1355 | |
0105d1a5 GN |
1356 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1357 | { | |
d1766202 VK |
1358 | return addr >= apic->base_address && |
1359 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
0105d1a5 GN |
1360 | } |
1361 | ||
e32edf4f | 1362 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1363 | gpa_t address, int len, void *data) |
1364 | { | |
1365 | struct kvm_lapic *apic = to_lapic(this); | |
1366 | u32 offset = address - apic->base_address; | |
1367 | ||
1368 | if (!apic_mmio_in_range(apic, address)) | |
1369 | return -EOPNOTSUPP; | |
1370 | ||
d1766202 VK |
1371 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
1372 | if (!kvm_check_has_quirk(vcpu->kvm, | |
1373 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
1374 | return -EOPNOTSUPP; | |
1375 | ||
1376 | memset(data, 0xff, len); | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1e6e2755 | 1380 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1381 | |
1382 | return 0; | |
1383 | } | |
1384 | ||
97222cc8 ED |
1385 | static void update_divide_count(struct kvm_lapic *apic) |
1386 | { | |
1387 | u32 tmp1, tmp2, tdcr; | |
1388 | ||
dfb95954 | 1389 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1390 | tmp1 = tdcr & 0xf; |
1391 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1392 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1393 | |
1394 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1395 | apic->divide_count); |
97222cc8 ED |
1396 | } |
1397 | ||
ccbfa1d3 WL |
1398 | static void limit_periodic_timer_frequency(struct kvm_lapic *apic) |
1399 | { | |
1400 | /* | |
1401 | * Do not allow the guest to program periodic timers with small | |
1402 | * interval, since the hrtimers are not throttled by the host | |
1403 | * scheduler. | |
1404 | */ | |
dedf9c5e | 1405 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { |
ccbfa1d3 WL |
1406 | s64 min_period = min_timer_period_us * 1000LL; |
1407 | ||
1408 | if (apic->lapic_timer.period < min_period) { | |
1409 | pr_info_ratelimited( | |
1410 | "kvm: vcpu %i: requested %lld ns " | |
1411 | "lapic timer period limited to %lld ns\n", | |
1412 | apic->vcpu->vcpu_id, | |
1413 | apic->lapic_timer.period, min_period); | |
1414 | apic->lapic_timer.period = min_period; | |
1415 | } | |
1416 | } | |
1417 | } | |
1418 | ||
b6ac0695 RK |
1419 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1420 | { | |
dfb95954 | 1421 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1422 | apic->lapic_timer.timer_mode_mask; |
1423 | ||
1424 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
c69518c8 | 1425 | if (apic_lvtt_tscdeadline(apic) != (timer_mode == |
dedf9c5e | 1426 | APIC_LVT_TIMER_TSCDEADLINE)) { |
dedf9c5e | 1427 | hrtimer_cancel(&apic->lapic_timer.timer); |
44275932 RK |
1428 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); |
1429 | apic->lapic_timer.period = 0; | |
1430 | apic->lapic_timer.tscdeadline = 0; | |
dedf9c5e | 1431 | } |
b6ac0695 | 1432 | apic->lapic_timer.timer_mode = timer_mode; |
dedf9c5e | 1433 | limit_periodic_timer_frequency(apic); |
b6ac0695 RK |
1434 | } |
1435 | } | |
1436 | ||
5d87db71 RK |
1437 | static void apic_timer_expired(struct kvm_lapic *apic) |
1438 | { | |
1439 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1440 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1441 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1442 | |
5d87db71 RK |
1443 | if (atomic_read(&apic->lapic_timer.pending)) |
1444 | return; | |
1445 | ||
1446 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1447 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1448 | |
cc1b4680 DB |
1449 | /* |
1450 | * For x86, the atomic_inc() is serialized, thus | |
1451 | * using swait_active() is safe. | |
1452 | */ | |
8577370f | 1453 | if (swait_active(q)) |
b3dae109 | 1454 | swake_up_one(q); |
d0659d94 MT |
1455 | |
1456 | if (apic_lvtt_tscdeadline(apic)) | |
1457 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1458 | } | |
1459 | ||
1460 | /* | |
1461 | * On APICv, this test will cause a busy wait | |
1462 | * during a higher-priority task. | |
1463 | */ | |
1464 | ||
1465 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1466 | { | |
1467 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1468 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1469 | |
1470 | if (kvm_apic_hw_enabled(apic)) { | |
1471 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1472 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1473 | |
d62caabb | 1474 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1475 | bitmap = apic->regs + APIC_IRR; |
1476 | ||
1477 | if (apic_test_vector(vec, bitmap)) | |
1478 | return true; | |
d0659d94 MT |
1479 | } |
1480 | return false; | |
1481 | } | |
1482 | ||
1483 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1484 | { | |
1485 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3b8a5df6 | 1486 | u64 guest_tsc, tsc_deadline, ns; |
d0659d94 | 1487 | |
bce87cce | 1488 | if (!lapic_in_kernel(vcpu)) |
d0659d94 MT |
1489 | return; |
1490 | ||
1491 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1492 | return; | |
1493 | ||
1494 | if (!lapic_timer_int_injected(vcpu)) | |
1495 | return; | |
1496 | ||
1497 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1498 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1499 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1500 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1501 | |
1502 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1503 | if (guest_tsc < tsc_deadline) | |
b606f189 MT |
1504 | __delay(min(tsc_deadline - guest_tsc, |
1505 | nsec_to_cycles(vcpu, lapic_timer_advance_ns))); | |
3b8a5df6 WL |
1506 | |
1507 | if (!lapic_timer_advance_adjust_done) { | |
1508 | /* too early */ | |
1509 | if (guest_tsc < tsc_deadline) { | |
1510 | ns = (tsc_deadline - guest_tsc) * 1000000ULL; | |
1511 | do_div(ns, vcpu->arch.virtual_tsc_khz); | |
1512 | lapic_timer_advance_ns -= min((unsigned int)ns, | |
1513 | lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP); | |
1514 | } else { | |
1515 | /* too late */ | |
1516 | ns = (guest_tsc - tsc_deadline) * 1000000ULL; | |
1517 | do_div(ns, vcpu->arch.virtual_tsc_khz); | |
1518 | lapic_timer_advance_ns += min((unsigned int)ns, | |
1519 | lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP); | |
1520 | } | |
1521 | if (abs(guest_tsc - tsc_deadline) < LAPIC_TIMER_ADVANCE_ADJUST_DONE) | |
1522 | lapic_timer_advance_adjust_done = true; | |
1523 | } | |
5d87db71 RK |
1524 | } |
1525 | ||
53f9eedf YJ |
1526 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1527 | { | |
1528 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1529 | u64 ns = 0; | |
1530 | ktime_t expire; | |
1531 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1532 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1533 | unsigned long flags; | |
1534 | ktime_t now; | |
1535 | ||
1536 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1537 | return; | |
1538 | ||
1539 | local_irq_save(flags); | |
1540 | ||
5587859f | 1541 | now = ktime_get(); |
53f9eedf YJ |
1542 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1543 | if (likely(tscdeadline > guest_tsc)) { | |
1544 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1545 | do_div(ns, this_tsc_khz); | |
1546 | expire = ktime_add_ns(now, ns); | |
1547 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1548 | hrtimer_start(&apic->lapic_timer.timer, | |
1549 | expire, HRTIMER_MODE_ABS_PINNED); | |
1550 | } else | |
1551 | apic_timer_expired(apic); | |
1552 | ||
1553 | local_irq_restore(flags); | |
1554 | } | |
1555 | ||
c301b909 WL |
1556 | static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) |
1557 | { | |
1558 | ktime_t now, remaining; | |
1559 | u64 ns_remaining_old, ns_remaining_new; | |
1560 | ||
1561 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) | |
1562 | * APIC_BUS_CYCLE_NS * apic->divide_count; | |
1563 | limit_periodic_timer_frequency(apic); | |
1564 | ||
1565 | now = ktime_get(); | |
1566 | remaining = ktime_sub(apic->lapic_timer.target_expiration, now); | |
1567 | if (ktime_to_ns(remaining) < 0) | |
1568 | remaining = 0; | |
1569 | ||
1570 | ns_remaining_old = ktime_to_ns(remaining); | |
1571 | ns_remaining_new = mul_u64_u32_div(ns_remaining_old, | |
1572 | apic->divide_count, old_divisor); | |
1573 | ||
1574 | apic->lapic_timer.tscdeadline += | |
1575 | nsec_to_cycles(apic->vcpu, ns_remaining_new) - | |
1576 | nsec_to_cycles(apic->vcpu, ns_remaining_old); | |
1577 | apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); | |
1578 | } | |
1579 | ||
8003c9ae | 1580 | static bool set_target_expiration(struct kvm_lapic *apic) |
7d7f7da2 WL |
1581 | { |
1582 | ktime_t now; | |
8003c9ae | 1583 | u64 tscl = rdtsc(); |
7d7f7da2 | 1584 | |
5587859f | 1585 | now = ktime_get(); |
7d7f7da2 | 1586 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
8003c9ae | 1587 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
7d7f7da2 | 1588 | |
5d74a699 RK |
1589 | if (!apic->lapic_timer.period) { |
1590 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae | 1591 | return false; |
7d7f7da2 WL |
1592 | } |
1593 | ||
ccbfa1d3 | 1594 | limit_periodic_timer_frequency(apic); |
7d7f7da2 | 1595 | |
7d7f7da2 WL |
1596 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
1597 | PRIx64 ", " | |
1598 | "timer initial count 0x%x, period %lldns, " | |
1599 | "expire @ 0x%016" PRIx64 ".\n", __func__, | |
1600 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), | |
1601 | kvm_lapic_get_reg(apic, APIC_TMICT), | |
1602 | apic->lapic_timer.period, | |
1603 | ktime_to_ns(ktime_add_ns(now, | |
1604 | apic->lapic_timer.period))); | |
8003c9ae WL |
1605 | |
1606 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + | |
1607 | nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); | |
1608 | apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); | |
1609 | ||
1610 | return true; | |
1611 | } | |
1612 | ||
1613 | static void advance_periodic_target_expiration(struct kvm_lapic *apic) | |
1614 | { | |
d8f2f498 DV |
1615 | ktime_t now = ktime_get(); |
1616 | u64 tscl = rdtsc(); | |
1617 | ktime_t delta; | |
1618 | ||
1619 | /* | |
1620 | * Synchronize both deadlines to the same time source or | |
1621 | * differences in the periods (caused by differences in the | |
1622 | * underlying clocks or numerical approximation errors) will | |
1623 | * cause the two to drift apart over time as the errors | |
1624 | * accumulate. | |
1625 | */ | |
8003c9ae WL |
1626 | apic->lapic_timer.target_expiration = |
1627 | ktime_add_ns(apic->lapic_timer.target_expiration, | |
1628 | apic->lapic_timer.period); | |
d8f2f498 DV |
1629 | delta = ktime_sub(apic->lapic_timer.target_expiration, now); |
1630 | apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + | |
1631 | nsec_to_cycles(apic->vcpu, delta); | |
7d7f7da2 WL |
1632 | } |
1633 | ||
ecf08dad AB |
1634 | static void start_sw_period(struct kvm_lapic *apic) |
1635 | { | |
1636 | if (!apic->lapic_timer.period) | |
1637 | return; | |
1638 | ||
1639 | if (ktime_after(ktime_get(), | |
1640 | apic->lapic_timer.target_expiration)) { | |
1641 | apic_timer_expired(apic); | |
1642 | ||
1643 | if (apic_lvtt_oneshot(apic)) | |
1644 | return; | |
1645 | ||
1646 | advance_periodic_target_expiration(apic); | |
1647 | } | |
1648 | ||
1649 | hrtimer_start(&apic->lapic_timer.timer, | |
1650 | apic->lapic_timer.target_expiration, | |
1651 | HRTIMER_MODE_ABS_PINNED); | |
1652 | } | |
1653 | ||
ce7a058a YJ |
1654 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1655 | { | |
91005300 WL |
1656 | if (!lapic_in_kernel(vcpu)) |
1657 | return false; | |
1658 | ||
ce7a058a YJ |
1659 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; |
1660 | } | |
1661 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1662 | ||
7e810a38 | 1663 | static void cancel_hv_timer(struct kvm_lapic *apic) |
bd97ad0e | 1664 | { |
1d518c68 | 1665 | WARN_ON(preemptible()); |
a749e247 | 1666 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
bd97ad0e WL |
1667 | kvm_x86_ops->cancel_hv_timer(apic->vcpu); |
1668 | apic->lapic_timer.hv_timer_in_use = false; | |
1669 | } | |
1670 | ||
a749e247 | 1671 | static bool start_hv_timer(struct kvm_lapic *apic) |
196f20ca | 1672 | { |
35ee9e48 PB |
1673 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1674 | int r; | |
196f20ca | 1675 | |
1d518c68 | 1676 | WARN_ON(preemptible()); |
a749e247 PB |
1677 | if (!kvm_x86_ops->set_hv_timer) |
1678 | return false; | |
1679 | ||
35ee9e48 PB |
1680 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) |
1681 | return false; | |
1682 | ||
86bbc1e6 RK |
1683 | if (!ktimer->tscdeadline) |
1684 | return false; | |
1685 | ||
35ee9e48 PB |
1686 | r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline); |
1687 | if (r < 0) | |
1688 | return false; | |
1689 | ||
1690 | ktimer->hv_timer_in_use = true; | |
1691 | hrtimer_cancel(&ktimer->timer); | |
196f20ca | 1692 | |
35ee9e48 PB |
1693 | /* |
1694 | * Also recheck ktimer->pending, in case the sw timer triggered in | |
1695 | * the window. For periodic timer, leave the hv timer running for | |
1696 | * simplicity, and the deadline will be recomputed on the next vmexit. | |
1697 | */ | |
c8533544 WL |
1698 | if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) { |
1699 | if (r) | |
1700 | apic_timer_expired(apic); | |
35ee9e48 | 1701 | return false; |
c8533544 | 1702 | } |
a749e247 PB |
1703 | |
1704 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true); | |
35ee9e48 PB |
1705 | return true; |
1706 | } | |
1707 | ||
a749e247 | 1708 | static void start_sw_timer(struct kvm_lapic *apic) |
35ee9e48 | 1709 | { |
a749e247 | 1710 | struct kvm_timer *ktimer = &apic->lapic_timer; |
1d518c68 WL |
1711 | |
1712 | WARN_ON(preemptible()); | |
a749e247 PB |
1713 | if (apic->lapic_timer.hv_timer_in_use) |
1714 | cancel_hv_timer(apic); | |
1715 | if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) | |
1716 | return; | |
1717 | ||
1718 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) | |
1719 | start_sw_period(apic); | |
1720 | else if (apic_lvtt_tscdeadline(apic)) | |
1721 | start_sw_tscdeadline(apic); | |
1722 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); | |
1723 | } | |
35ee9e48 | 1724 | |
a749e247 PB |
1725 | static void restart_apic_timer(struct kvm_lapic *apic) |
1726 | { | |
1d518c68 | 1727 | preempt_disable(); |
a749e247 PB |
1728 | if (!start_hv_timer(apic)) |
1729 | start_sw_timer(apic); | |
1d518c68 | 1730 | preempt_enable(); |
196f20ca WL |
1731 | } |
1732 | ||
8003c9ae WL |
1733 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1734 | { | |
1735 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1736 | ||
1d518c68 WL |
1737 | preempt_disable(); |
1738 | /* If the preempt notifier has already run, it also called apic_timer_expired */ | |
1739 | if (!apic->lapic_timer.hv_timer_in_use) | |
1740 | goto out; | |
8003c9ae WL |
1741 | WARN_ON(swait_active(&vcpu->wq)); |
1742 | cancel_hv_timer(apic); | |
1743 | apic_timer_expired(apic); | |
1744 | ||
1745 | if (apic_lvtt_period(apic) && apic->lapic_timer.period) { | |
1746 | advance_periodic_target_expiration(apic); | |
a749e247 | 1747 | restart_apic_timer(apic); |
8003c9ae | 1748 | } |
1d518c68 WL |
1749 | out: |
1750 | preempt_enable(); | |
8003c9ae WL |
1751 | } |
1752 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1753 | ||
ce7a058a YJ |
1754 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1755 | { | |
a749e247 | 1756 | restart_apic_timer(vcpu->arch.apic); |
ce7a058a YJ |
1757 | } |
1758 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1759 | ||
1760 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1761 | { | |
1762 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1763 | ||
1d518c68 | 1764 | preempt_disable(); |
ce7a058a | 1765 | /* Possibly the TSC deadline timer is not enabled yet */ |
a749e247 PB |
1766 | if (apic->lapic_timer.hv_timer_in_use) |
1767 | start_sw_timer(apic); | |
1d518c68 | 1768 | preempt_enable(); |
a749e247 PB |
1769 | } |
1770 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
ce7a058a | 1771 | |
a749e247 PB |
1772 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu) |
1773 | { | |
1774 | struct kvm_lapic *apic = vcpu->arch.apic; | |
ce7a058a | 1775 | |
a749e247 PB |
1776 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); |
1777 | restart_apic_timer(apic); | |
ce7a058a | 1778 | } |
ce7a058a | 1779 | |
97222cc8 ED |
1780 | static void start_apic_timer(struct kvm_lapic *apic) |
1781 | { | |
d3c7b77d | 1782 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1783 | |
a749e247 PB |
1784 | if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) |
1785 | && !set_target_expiration(apic)) | |
1786 | return; | |
1787 | ||
1788 | restart_apic_timer(apic); | |
97222cc8 ED |
1789 | } |
1790 | ||
cc6e462c JK |
1791 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1792 | { | |
59fd1323 | 1793 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1794 | |
59fd1323 RK |
1795 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1796 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1797 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1798 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1799 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1800 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1801 | } else |
1802 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1803 | } | |
cc6e462c JK |
1804 | } |
1805 | ||
1e6e2755 | 1806 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1807 | { |
0105d1a5 | 1808 | int ret = 0; |
97222cc8 | 1809 | |
0105d1a5 | 1810 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1811 | |
0105d1a5 | 1812 | switch (reg) { |
97222cc8 | 1813 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1814 | if (!apic_x2apic_mode(apic)) |
a92e2543 | 1815 | kvm_apic_set_xapic_id(apic, val >> 24); |
0105d1a5 GN |
1816 | else |
1817 | ret = 1; | |
97222cc8 ED |
1818 | break; |
1819 | ||
1820 | case APIC_TASKPRI: | |
b209749f | 1821 | report_tpr_access(apic, true); |
97222cc8 ED |
1822 | apic_set_tpr(apic, val & 0xff); |
1823 | break; | |
1824 | ||
1825 | case APIC_EOI: | |
1826 | apic_set_eoi(apic); | |
1827 | break; | |
1828 | ||
1829 | case APIC_LDR: | |
0105d1a5 | 1830 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1831 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1832 | else |
1833 | ret = 1; | |
97222cc8 ED |
1834 | break; |
1835 | ||
1836 | case APIC_DFR: | |
1e08ec4a | 1837 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1838 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1839 | recalculate_apic_map(apic->vcpu->kvm); |
1840 | } else | |
0105d1a5 | 1841 | ret = 1; |
97222cc8 ED |
1842 | break; |
1843 | ||
fc61b800 GN |
1844 | case APIC_SPIV: { |
1845 | u32 mask = 0x3ff; | |
dfb95954 | 1846 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1847 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1848 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1849 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1850 | int i; | |
1851 | u32 lvt_val; | |
1852 | ||
1e6e2755 | 1853 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1854 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1855 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1856 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1857 | lvt_val | APIC_LVT_MASKED); |
1858 | } | |
b6ac0695 | 1859 | apic_update_lvtt(apic); |
d3c7b77d | 1860 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1861 | |
1862 | } | |
1863 | break; | |
fc61b800 | 1864 | } |
97222cc8 ED |
1865 | case APIC_ICR: |
1866 | /* No delay here, so we always clear the pending bit */ | |
1e6e2755 | 1867 | kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); |
97222cc8 ED |
1868 | apic_send_ipi(apic); |
1869 | break; | |
1870 | ||
1871 | case APIC_ICR2: | |
0105d1a5 GN |
1872 | if (!apic_x2apic_mode(apic)) |
1873 | val &= 0xff000000; | |
1e6e2755 | 1874 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1875 | break; |
1876 | ||
23930f95 | 1877 | case APIC_LVT0: |
cc6e462c | 1878 | apic_manage_nmi_watchdog(apic, val); |
b2869f28 | 1879 | /* fall through */ |
97222cc8 ED |
1880 | case APIC_LVTTHMR: |
1881 | case APIC_LVTPC: | |
97222cc8 ED |
1882 | case APIC_LVT1: |
1883 | case APIC_LVTERR: | |
1884 | /* TODO: Check vector */ | |
c48f1496 | 1885 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1886 | val |= APIC_LVT_MASKED; |
1887 | ||
0105d1a5 | 1888 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1889 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1890 | |
1891 | break; | |
1892 | ||
b6ac0695 | 1893 | case APIC_LVTT: |
c48f1496 | 1894 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1895 | val |= APIC_LVT_MASKED; |
1896 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1897 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1898 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1899 | break; |
1900 | ||
97222cc8 | 1901 | case APIC_TMICT: |
a3e06bbe LJ |
1902 | if (apic_lvtt_tscdeadline(apic)) |
1903 | break; | |
1904 | ||
d3c7b77d | 1905 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1906 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1907 | start_apic_timer(apic); |
0105d1a5 | 1908 | break; |
97222cc8 | 1909 | |
c301b909 WL |
1910 | case APIC_TDCR: { |
1911 | uint32_t old_divisor = apic->divide_count; | |
1912 | ||
97222cc8 | 1913 | if (val & 4) |
7712de87 | 1914 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
1e6e2755 | 1915 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 | 1916 | update_divide_count(apic); |
c301b909 WL |
1917 | if (apic->divide_count != old_divisor && |
1918 | apic->lapic_timer.period) { | |
1919 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1920 | update_target_expiration(apic, old_divisor); | |
1921 | restart_apic_timer(apic); | |
1922 | } | |
97222cc8 | 1923 | break; |
c301b909 | 1924 | } |
0105d1a5 GN |
1925 | case APIC_ESR: |
1926 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1927 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1928 | ret = 1; |
1929 | } | |
1930 | break; | |
1931 | ||
1932 | case APIC_SELF_IPI: | |
1933 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 1934 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
1935 | } else |
1936 | ret = 1; | |
1937 | break; | |
97222cc8 | 1938 | default: |
0105d1a5 | 1939 | ret = 1; |
97222cc8 ED |
1940 | break; |
1941 | } | |
0105d1a5 GN |
1942 | if (ret) |
1943 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1944 | return ret; | |
1945 | } | |
1e6e2755 | 1946 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 1947 | |
e32edf4f | 1948 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1949 | gpa_t address, int len, const void *data) |
1950 | { | |
1951 | struct kvm_lapic *apic = to_lapic(this); | |
1952 | unsigned int offset = address - apic->base_address; | |
1953 | u32 val; | |
1954 | ||
1955 | if (!apic_mmio_in_range(apic, address)) | |
1956 | return -EOPNOTSUPP; | |
1957 | ||
d1766202 VK |
1958 | if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { |
1959 | if (!kvm_check_has_quirk(vcpu->kvm, | |
1960 | KVM_X86_QUIRK_LAPIC_MMIO_HOLE)) | |
1961 | return -EOPNOTSUPP; | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
0105d1a5 GN |
1966 | /* |
1967 | * APIC register must be aligned on 128-bits boundary. | |
1968 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1969 | * Refer SDM 8.4.1 | |
1970 | */ | |
1971 | if (len != 4 || (offset & 0xf)) { | |
1972 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1973 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1974 | return 0; |
0105d1a5 GN |
1975 | } |
1976 | ||
1977 | val = *(u32*)data; | |
1978 | ||
1979 | /* too common printing */ | |
1980 | if (offset != APIC_EOI) | |
1981 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1982 | "0x%x\n", __func__, offset, len, val); | |
1983 | ||
1e6e2755 | 1984 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 1985 | |
bda9020e | 1986 | return 0; |
97222cc8 ED |
1987 | } |
1988 | ||
58fbbf26 KT |
1989 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1990 | { | |
1e6e2755 | 1991 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
1992 | } |
1993 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1994 | ||
83d4c286 YZ |
1995 | /* emulate APIC access in a trap manner */ |
1996 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1997 | { | |
1998 | u32 val = 0; | |
1999 | ||
2000 | /* hw has done the conditional check and inst decode */ | |
2001 | offset &= 0xff0; | |
2002 | ||
1e6e2755 | 2003 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
2004 | |
2005 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 2006 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
2007 | } |
2008 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
2009 | ||
d589444e | 2010 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 2011 | { |
f8c1ea10 GN |
2012 | struct kvm_lapic *apic = vcpu->arch.apic; |
2013 | ||
ad312c7c | 2014 | if (!vcpu->arch.apic) |
97222cc8 ED |
2015 | return; |
2016 | ||
f8c1ea10 | 2017 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2018 | |
c5cc421b GN |
2019 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
2020 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
2021 | ||
e462755c | 2022 | if (!apic->sw_enabled) |
f8c1ea10 | 2023 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 2024 | |
f8c1ea10 GN |
2025 | if (apic->regs) |
2026 | free_page((unsigned long)apic->regs); | |
2027 | ||
2028 | kfree(apic); | |
97222cc8 ED |
2029 | } |
2030 | ||
2031 | /* | |
2032 | *---------------------------------------------------------------------- | |
2033 | * LAPIC interface | |
2034 | *---------------------------------------------------------------------- | |
2035 | */ | |
a3e06bbe LJ |
2036 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
2037 | { | |
2038 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2039 | |
a10388e1 WL |
2040 | if (!lapic_in_kernel(vcpu) || |
2041 | !apic_lvtt_tscdeadline(apic)) | |
a3e06bbe LJ |
2042 | return 0; |
2043 | ||
2044 | return apic->lapic_timer.tscdeadline; | |
2045 | } | |
2046 | ||
2047 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
2048 | { | |
2049 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 2050 | |
bce87cce | 2051 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 2052 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
2053 | return; |
2054 | ||
2055 | hrtimer_cancel(&apic->lapic_timer.timer); | |
2056 | apic->lapic_timer.tscdeadline = data; | |
2057 | start_apic_timer(apic); | |
2058 | } | |
2059 | ||
97222cc8 ED |
2060 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
2061 | { | |
ad312c7c | 2062 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2063 | |
b93463aa | 2064 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 2065 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
2066 | } |
2067 | ||
2068 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
2069 | { | |
97222cc8 ED |
2070 | u64 tpr; |
2071 | ||
dfb95954 | 2072 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
2073 | |
2074 | return (tpr & 0xf0) >> 4; | |
2075 | } | |
2076 | ||
2077 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
2078 | { | |
8d14695f | 2079 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 2080 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 2081 | |
c7dd15b3 | 2082 | if (!apic) |
97222cc8 | 2083 | value |= MSR_IA32_APICBASE_BSP; |
c5af89b6 | 2084 | |
e66d2ae7 JK |
2085 | vcpu->arch.apic_base = value; |
2086 | ||
c7dd15b3 JM |
2087 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) |
2088 | kvm_update_cpuid(vcpu); | |
2089 | ||
2090 | if (!apic) | |
2091 | return; | |
2092 | ||
c5cc421b | 2093 | /* update jump label if enable bit changes */ |
0dce7cd6 | 2094 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
49bd29ba RK |
2095 | if (value & MSR_IA32_APICBASE_ENABLE) { |
2096 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); | |
c5cc421b | 2097 | static_key_slow_dec_deferred(&apic_hw_disabled); |
187ca84b | 2098 | } else { |
c5cc421b | 2099 | static_key_slow_inc(&apic_hw_disabled.key); |
187ca84b WL |
2100 | recalculate_apic_map(vcpu->kvm); |
2101 | } | |
c5cc421b GN |
2102 | } |
2103 | ||
8d860bbe JM |
2104 | if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE)) |
2105 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); | |
2106 | ||
2107 | if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) | |
2108 | kvm_x86_ops->set_virtual_apic_mode(vcpu); | |
8d14695f | 2109 | |
ad312c7c | 2110 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
2111 | MSR_IA32_APICBASE_BASE; |
2112 | ||
db324fe6 NA |
2113 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
2114 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
2115 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
2116 | ||
97222cc8 ED |
2117 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
2118 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 2119 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
2120 | |
2121 | } | |
2122 | ||
d28bc9dd | 2123 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 | 2124 | { |
b7e31be3 | 2125 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
2126 | int i; |
2127 | ||
b7e31be3 RK |
2128 | if (!apic) |
2129 | return; | |
97222cc8 | 2130 | |
b7e31be3 | 2131 | apic_debug("%s\n", __func__); |
97222cc8 ED |
2132 | |
2133 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 2134 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 2135 | |
4d8e772b RK |
2136 | if (!init_event) { |
2137 | kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE | | |
2138 | MSR_IA32_APICBASE_ENABLE); | |
a92e2543 | 2139 | kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); |
4d8e772b | 2140 | } |
fc61b800 | 2141 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 2142 | |
1e6e2755 SS |
2143 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
2144 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 2145 | apic_update_lvtt(apic); |
52b54190 JS |
2146 | if (kvm_vcpu_is_reset_bsp(vcpu) && |
2147 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) | |
1e6e2755 | 2148 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 2149 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 2150 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 2151 | |
1e6e2755 | 2152 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 2153 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 2154 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
2155 | if (!apic_x2apic_mode(apic)) |
2156 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
2157 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
2158 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
2159 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
2160 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
2161 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 2162 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
2163 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
2164 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
2165 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 2166 | } |
d62caabb AS |
2167 | apic->irr_pending = vcpu->arch.apicv_active; |
2168 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 2169 | apic->highest_isr_cache = -1; |
b33ac88b | 2170 | update_divide_count(apic); |
d3c7b77d | 2171 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 2172 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
2173 | kvm_lapic_set_base(vcpu, |
2174 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 2175 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 | 2176 | apic_update_ppr(apic); |
4191db26 JS |
2177 | if (vcpu->arch.apicv_active) { |
2178 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
2179 | kvm_x86_ops->hwapic_irr_update(vcpu, -1); | |
2180 | kvm_x86_ops->hwapic_isr_update(vcpu, -1); | |
2181 | } | |
97222cc8 | 2182 | |
e1035715 | 2183 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 2184 | vcpu->arch.apic_attention = 0; |
e1035715 | 2185 | |
6e500439 | 2186 | apic_debug("%s: vcpu=%p, id=0x%x, base_msr=" |
b8688d51 | 2187 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
6e500439 | 2188 | vcpu, kvm_lapic_get_reg(apic, APIC_ID), |
ad312c7c | 2189 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
2190 | } |
2191 | ||
97222cc8 ED |
2192 | /* |
2193 | *---------------------------------------------------------------------- | |
2194 | * timer interface | |
2195 | *---------------------------------------------------------------------- | |
2196 | */ | |
1b9778da | 2197 | |
2a6eac96 | 2198 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 2199 | { |
d3c7b77d | 2200 | return apic_lvtt_period(apic); |
97222cc8 ED |
2201 | } |
2202 | ||
3d80840d MT |
2203 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
2204 | { | |
54e9818f | 2205 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 2206 | |
1e3161b4 | 2207 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 2208 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
2209 | |
2210 | return 0; | |
2211 | } | |
2212 | ||
89342082 | 2213 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 2214 | { |
dfb95954 | 2215 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 2216 | int vector, mode, trig_mode; |
23930f95 | 2217 | |
c48f1496 | 2218 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
2219 | vector = reg & APIC_VECTOR_MASK; |
2220 | mode = reg & APIC_MODE_MASK; | |
2221 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
2222 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
2223 | NULL); | |
23930f95 JK |
2224 | } |
2225 | return 0; | |
2226 | } | |
1b9778da | 2227 | |
8fdb2351 | 2228 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 2229 | { |
8fdb2351 JK |
2230 | struct kvm_lapic *apic = vcpu->arch.apic; |
2231 | ||
2232 | if (apic) | |
2233 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
2234 | } |
2235 | ||
d76685c4 GH |
2236 | static const struct kvm_io_device_ops apic_mmio_ops = { |
2237 | .read = apic_mmio_read, | |
2238 | .write = apic_mmio_write, | |
d76685c4 GH |
2239 | }; |
2240 | ||
e9d90d47 AK |
2241 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
2242 | { | |
2243 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 2244 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 2245 | |
5d87db71 | 2246 | apic_timer_expired(apic); |
e9d90d47 | 2247 | |
2a6eac96 | 2248 | if (lapic_is_periodic(apic)) { |
8003c9ae | 2249 | advance_periodic_target_expiration(apic); |
e9d90d47 AK |
2250 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
2251 | return HRTIMER_RESTART; | |
2252 | } else | |
2253 | return HRTIMER_NORESTART; | |
2254 | } | |
2255 | ||
97222cc8 ED |
2256 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
2257 | { | |
2258 | struct kvm_lapic *apic; | |
2259 | ||
2260 | ASSERT(vcpu != NULL); | |
2261 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
2262 | ||
254272ce | 2263 | apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); |
97222cc8 ED |
2264 | if (!apic) |
2265 | goto nomem; | |
2266 | ||
ad312c7c | 2267 | vcpu->arch.apic = apic; |
97222cc8 | 2268 | |
254272ce | 2269 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
afc20184 | 2270 | if (!apic->regs) { |
97222cc8 ED |
2271 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
2272 | vcpu->vcpu_id); | |
d589444e | 2273 | goto nomem_free_apic; |
97222cc8 | 2274 | } |
97222cc8 ED |
2275 | apic->vcpu = vcpu; |
2276 | ||
d3c7b77d | 2277 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
61abdbe0 | 2278 | HRTIMER_MODE_ABS_PINNED); |
e9d90d47 | 2279 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 2280 | |
c5cc421b GN |
2281 | /* |
2282 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
2283 | * thinking that APIC satet has changed. | |
2284 | */ | |
2285 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
f8c1ea10 | 2286 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d76685c4 | 2287 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
2288 | |
2289 | return 0; | |
d589444e RR |
2290 | nomem_free_apic: |
2291 | kfree(apic); | |
97222cc8 | 2292 | nomem: |
97222cc8 ED |
2293 | return -ENOMEM; |
2294 | } | |
97222cc8 ED |
2295 | |
2296 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
2297 | { | |
ad312c7c | 2298 | struct kvm_lapic *apic = vcpu->arch.apic; |
b3c045d3 | 2299 | u32 ppr; |
97222cc8 | 2300 | |
f8543d6a | 2301 | if (!apic_enabled(apic)) |
97222cc8 ED |
2302 | return -1; |
2303 | ||
b3c045d3 PB |
2304 | __apic_update_ppr(apic, &ppr); |
2305 | return apic_has_interrupt_for_ppr(apic, ppr); | |
97222cc8 ED |
2306 | } |
2307 | ||
40487c68 QH |
2308 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
2309 | { | |
dfb95954 | 2310 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
2311 | int r = 0; |
2312 | ||
c48f1496 | 2313 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
2314 | r = 1; |
2315 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
2316 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
2317 | r = 1; | |
40487c68 QH |
2318 | return r; |
2319 | } | |
2320 | ||
1b9778da ED |
2321 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
2322 | { | |
ad312c7c | 2323 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 2324 | |
54e9818f | 2325 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
f1ed0450 | 2326 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
2327 | if (apic_lvtt_tscdeadline(apic)) |
2328 | apic->lapic_timer.tscdeadline = 0; | |
8003c9ae WL |
2329 | if (apic_lvtt_oneshot(apic)) { |
2330 | apic->lapic_timer.tscdeadline = 0; | |
8b0e1953 | 2331 | apic->lapic_timer.target_expiration = 0; |
8003c9ae | 2332 | } |
f1ed0450 | 2333 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
2334 | } |
2335 | } | |
2336 | ||
97222cc8 ED |
2337 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
2338 | { | |
2339 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 2340 | struct kvm_lapic *apic = vcpu->arch.apic; |
4d82d12b | 2341 | u32 ppr; |
97222cc8 ED |
2342 | |
2343 | if (vector == -1) | |
2344 | return -1; | |
2345 | ||
56cc2406 WL |
2346 | /* |
2347 | * We get here even with APIC virtualization enabled, if doing | |
2348 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
2349 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
2350 | * because the process would deliver it through the IDT. | |
2351 | */ | |
2352 | ||
97222cc8 | 2353 | apic_clear_irr(vector, apic); |
5c919412 | 2354 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { |
4d82d12b PB |
2355 | /* |
2356 | * For auto-EOI interrupts, there might be another pending | |
2357 | * interrupt above PPR, so check whether to raise another | |
2358 | * KVM_REQ_EVENT. | |
2359 | */ | |
5c919412 | 2360 | apic_update_ppr(apic); |
4d82d12b PB |
2361 | } else { |
2362 | /* | |
2363 | * For normal interrupts, PPR has been raised and there cannot | |
2364 | * be a higher-priority pending interrupt---except if there was | |
2365 | * a concurrent interrupt injection, but that would have | |
2366 | * triggered KVM_REQ_EVENT already. | |
2367 | */ | |
2368 | apic_set_isr(vector, apic); | |
2369 | __apic_update_ppr(apic, &ppr); | |
5c919412 AS |
2370 | } |
2371 | ||
97222cc8 ED |
2372 | return vector; |
2373 | } | |
96ad2cc6 | 2374 | |
a92e2543 RK |
2375 | static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, |
2376 | struct kvm_lapic_state *s, bool set) | |
2377 | { | |
2378 | if (apic_x2apic_mode(vcpu->arch.apic)) { | |
2379 | u32 *id = (u32 *)(s->regs + APIC_ID); | |
12806ba9 | 2380 | u32 *ldr = (u32 *)(s->regs + APIC_LDR); |
a92e2543 | 2381 | |
37131313 RK |
2382 | if (vcpu->kvm->arch.x2apic_format) { |
2383 | if (*id != vcpu->vcpu_id) | |
2384 | return -EINVAL; | |
2385 | } else { | |
2386 | if (set) | |
2387 | *id >>= 24; | |
2388 | else | |
2389 | *id <<= 24; | |
2390 | } | |
12806ba9 DDAG |
2391 | |
2392 | /* In x2APIC mode, the LDR is fixed and based on the id */ | |
2393 | if (set) | |
2394 | *ldr = kvm_apic_calc_x2apic_ldr(*id); | |
a92e2543 RK |
2395 | } |
2396 | ||
2397 | return 0; | |
2398 | } | |
2399 | ||
2400 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
2401 | { | |
2402 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); | |
2403 | return kvm_apic_state_fixup(vcpu, s, false); | |
2404 | } | |
2405 | ||
2406 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) | |
96ad2cc6 | 2407 | { |
ad312c7c | 2408 | struct kvm_lapic *apic = vcpu->arch.apic; |
a92e2543 RK |
2409 | int r; |
2410 | ||
96ad2cc6 | 2411 | |
5dbc8f3f | 2412 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
2413 | /* set SPIV separately to get count of SW disabled APICs right */ |
2414 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
a92e2543 RK |
2415 | |
2416 | r = kvm_apic_state_fixup(vcpu, s, true); | |
2417 | if (r) | |
2418 | return r; | |
0e96f31e | 2419 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); |
a92e2543 RK |
2420 | |
2421 | recalculate_apic_map(vcpu->kvm); | |
fc61b800 GN |
2422 | kvm_apic_set_version(vcpu); |
2423 | ||
96ad2cc6 | 2424 | apic_update_ppr(apic); |
d3c7b77d | 2425 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 2426 | apic_update_lvtt(apic); |
dfb95954 | 2427 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
2428 | update_divide_count(apic); |
2429 | start_apic_timer(apic); | |
6e24a6ef | 2430 | apic->irr_pending = true; |
d62caabb | 2431 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 2432 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 2433 | apic->highest_isr_cache = -1; |
d62caabb | 2434 | if (vcpu->arch.apicv_active) { |
967235d3 | 2435 | kvm_x86_ops->apicv_post_state_restore(vcpu); |
4114c27d WW |
2436 | kvm_x86_ops->hwapic_irr_update(vcpu, |
2437 | apic_find_highest_irr(apic)); | |
67c9dddc | 2438 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 2439 | apic_find_highest_isr(apic)); |
d62caabb | 2440 | } |
3842d135 | 2441 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2442 | if (ioapic_in_kernel(vcpu->kvm)) |
2443 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2444 | |
2445 | vcpu->arch.apic_arb_prio = 0; | |
a92e2543 RK |
2446 | |
2447 | return 0; | |
96ad2cc6 | 2448 | } |
a3d7f85f | 2449 | |
2f52d58c | 2450 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2451 | { |
a3d7f85f ED |
2452 | struct hrtimer *timer; |
2453 | ||
bce87cce | 2454 | if (!lapic_in_kernel(vcpu)) |
a3d7f85f ED |
2455 | return; |
2456 | ||
54e9818f | 2457 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2458 | if (hrtimer_cancel(timer)) |
61abdbe0 | 2459 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); |
a3d7f85f | 2460 | } |
b93463aa | 2461 | |
ae7a2a3f MT |
2462 | /* |
2463 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2464 | * | |
2465 | * Detect whether guest triggered PV EOI since the | |
2466 | * last entry. If yes, set EOI on guests's behalf. | |
2467 | * Clear PV EOI in guest memory in any case. | |
2468 | */ | |
2469 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2470 | struct kvm_lapic *apic) | |
2471 | { | |
2472 | bool pending; | |
2473 | int vector; | |
2474 | /* | |
2475 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2476 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2477 | * | |
2478 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2479 | * -> host disabled PV EOI. | |
2480 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2481 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2482 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2483 | * -> host enabled PV EOI, guest executed EOI. | |
2484 | */ | |
2485 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2486 | pending = pv_eoi_get_pending(vcpu); | |
2487 | /* | |
2488 | * Clear pending bit in any case: it will be set again on vmentry. | |
2489 | * While this might not be ideal from performance point of view, | |
2490 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2491 | */ | |
2492 | pv_eoi_clr_pending(vcpu); | |
2493 | if (pending) | |
2494 | return; | |
2495 | vector = apic_set_eoi(apic); | |
2496 | trace_kvm_pv_eoi(apic, vector); | |
2497 | } | |
2498 | ||
b93463aa AK |
2499 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2500 | { | |
2501 | u32 data; | |
b93463aa | 2502 | |
ae7a2a3f MT |
2503 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2504 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2505 | ||
41383771 | 2506 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2507 | return; |
2508 | ||
4e335d9e PB |
2509 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2510 | sizeof(u32))) | |
603242a8 | 2511 | return; |
b93463aa AK |
2512 | |
2513 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2514 | } | |
2515 | ||
ae7a2a3f MT |
2516 | /* |
2517 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2518 | * | |
2519 | * Detect whether it's safe to enable PV EOI and | |
2520 | * if yes do so. | |
2521 | */ | |
2522 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2523 | struct kvm_lapic *apic) | |
2524 | { | |
2525 | if (!pv_eoi_enabled(vcpu) || | |
2526 | /* IRR set or many bits in ISR: could be nested. */ | |
2527 | apic->irr_pending || | |
2528 | /* Cache not set: could be safe but we don't bother. */ | |
2529 | apic->highest_isr_cache == -1 || | |
2530 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2531 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2532 | /* |
2533 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2534 | * so we need not do anything here. | |
2535 | */ | |
2536 | return; | |
2537 | } | |
2538 | ||
2539 | pv_eoi_set_pending(apic->vcpu); | |
2540 | } | |
2541 | ||
b93463aa AK |
2542 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2543 | { | |
2544 | u32 data, tpr; | |
2545 | int max_irr, max_isr; | |
ae7a2a3f | 2546 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2547 | |
ae7a2a3f MT |
2548 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2549 | ||
41383771 | 2550 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2551 | return; |
2552 | ||
dfb95954 | 2553 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2554 | max_irr = apic_find_highest_irr(apic); |
2555 | if (max_irr < 0) | |
2556 | max_irr = 0; | |
2557 | max_isr = apic_find_highest_isr(apic); | |
2558 | if (max_isr < 0) | |
2559 | max_isr = 0; | |
2560 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2561 | ||
4e335d9e PB |
2562 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2563 | sizeof(u32)); | |
b93463aa AK |
2564 | } |
2565 | ||
fda4e2e8 | 2566 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2567 | { |
fda4e2e8 | 2568 | if (vapic_addr) { |
4e335d9e | 2569 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
fda4e2e8 AH |
2570 | &vcpu->arch.apic->vapic_cache, |
2571 | vapic_addr, sizeof(u32))) | |
2572 | return -EINVAL; | |
41383771 | 2573 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2574 | } else { |
41383771 | 2575 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2576 | } |
2577 | ||
2578 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2579 | return 0; | |
b93463aa | 2580 | } |
0105d1a5 GN |
2581 | |
2582 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2583 | { | |
2584 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2585 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2586 | ||
35754c98 | 2587 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2588 | return 1; |
2589 | ||
c69d3d9b NA |
2590 | if (reg == APIC_ICR2) |
2591 | return 1; | |
2592 | ||
0105d1a5 | 2593 | /* if this is ICR write vector before command */ |
decdc283 | 2594 | if (reg == APIC_ICR) |
1e6e2755 SS |
2595 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2596 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2597 | } |
2598 | ||
2599 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2600 | { | |
2601 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2602 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2603 | ||
35754c98 | 2604 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2605 | return 1; |
2606 | ||
c69d3d9b NA |
2607 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2608 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2609 | reg); | |
2610 | return 1; | |
2611 | } | |
2612 | ||
1e6e2755 | 2613 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2614 | return 1; |
decdc283 | 2615 | if (reg == APIC_ICR) |
1e6e2755 | 2616 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2617 | |
2618 | *data = (((u64)high) << 32) | low; | |
2619 | ||
2620 | return 0; | |
2621 | } | |
10388a07 GN |
2622 | |
2623 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2624 | { | |
2625 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2626 | ||
bce87cce | 2627 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2628 | return 1; |
2629 | ||
2630 | /* if this is ICR write vector before command */ | |
2631 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2632 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2633 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2634 | } |
2635 | ||
2636 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2637 | { | |
2638 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2639 | u32 low, high = 0; | |
2640 | ||
bce87cce | 2641 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2642 | return 1; |
2643 | ||
1e6e2755 | 2644 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2645 | return 1; |
2646 | if (reg == APIC_ICR) | |
1e6e2755 | 2647 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2648 | |
2649 | *data = (((u64)high) << 32) | low; | |
2650 | ||
2651 | return 0; | |
2652 | } | |
ae7a2a3f | 2653 | |
72bbf935 | 2654 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len) |
ae7a2a3f MT |
2655 | { |
2656 | u64 addr = data & ~KVM_MSR_ENABLED; | |
a7c42bb6 VK |
2657 | struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; |
2658 | unsigned long new_len; | |
2659 | ||
ae7a2a3f MT |
2660 | if (!IS_ALIGNED(addr, 4)) |
2661 | return 1; | |
2662 | ||
2663 | vcpu->arch.pv_eoi.msr_val = data; | |
2664 | if (!pv_eoi_enabled(vcpu)) | |
2665 | return 0; | |
a7c42bb6 VK |
2666 | |
2667 | if (addr == ghc->gpa && len <= ghc->len) | |
2668 | new_len = ghc->len; | |
2669 | else | |
2670 | new_len = len; | |
2671 | ||
2672 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); | |
ae7a2a3f | 2673 | } |
c5cc421b | 2674 | |
66450a21 JK |
2675 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2676 | { | |
2677 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2678 | u8 sipi_vector; |
299018f4 | 2679 | unsigned long pe; |
66450a21 | 2680 | |
bce87cce | 2681 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2682 | return; |
2683 | ||
cd7764fe PB |
2684 | /* |
2685 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2686 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2687 | * and delay processing of INIT until the next RSM. | |
2688 | */ | |
2689 | if (is_smm(vcpu)) { | |
2690 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2691 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2692 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2693 | return; | |
2694 | } | |
299018f4 | 2695 | |
cd7764fe | 2696 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2697 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd | 2698 | kvm_vcpu_reset(vcpu, true); |
66450a21 JK |
2699 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2700 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2701 | else | |
2702 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2703 | } | |
299018f4 | 2704 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2705 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2706 | /* evaluate pending_events before reading the vector */ | |
2707 | smp_rmb(); | |
2708 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2709 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2710 | vcpu->vcpu_id, sipi_vector); |
2711 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2712 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2713 | } | |
2714 | } | |
2715 | ||
c5cc421b GN |
2716 | void kvm_lapic_init(void) |
2717 | { | |
2718 | /* do not patch jump label more than once per second */ | |
2719 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2720 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2721 | } |
cef84c30 DM |
2722 | |
2723 | void kvm_lapic_exit(void) | |
2724 | { | |
2725 | static_key_deferred_flush(&apic_hw_disabled); | |
2726 | static_key_deferred_flush(&apic_sw_disabled); | |
2727 | } |