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KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
[mirror_ubuntu-impish-kernel.git] / arch / x86 / kvm / lapic.c
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20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
97222cc8
ED		 2
3/*
4 * Local APIC virtualization
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9611c187 9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 10 *
11 * Authors:
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 *
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
97222cc8
ED		 17 */
18
edf88417 19#include <linux/kvm_host.h>
97222cc8
ED		 20#include <linux/kvm.h>
21#include <linux/mm.h>
22#include <linux/highmem.h>
23#include <linux/smp.h>
24#include <linux/hrtimer.h>
25#include <linux/io.h>
1767e931 26#include <linux/export.h>
6f6d6a1a 27#include <linux/math64.h>
5a0e3ad6 28#include <linux/slab.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
d0659d94 34#include <asm/delay.h>
60063497 35#include <linux/atomic.h>
c5cc421b 36#include <linux/jump_label.h>
5fdbf976 37#include "kvm_cache_regs.h"
97222cc8 38#include "irq.h"
229456fc 39#include "trace.h"
fc61b800 40#include "x86.h"
00b27a3e 41#include "cpuid.h"
5c919412 42#include "hyperv.h"
97222cc8 43
b682b814
MT		 44#ifndef CONFIG_X86_64
45#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46#else
47#define mod_64(x, y) ((x) % (y))
48#endif
49
97222cc8
ED		 50#define PRId64 "d"
51#define PRIx64 "llx"
52#define PRIu64 "u"
53#define PRIo64 "o"
54
97222cc8 55/* 14 is the version for Xeon and Pentium 8.4.8*/
1e6e2755 56#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
97222cc8
ED		 57#define LAPIC_MMIO_LENGTH (1 << 12)
58/* followed define is not in apicdef.h */
59#define APIC_SHORT_MASK 0xc0000
60#define APIC_DEST_NOSHORT 0x0
61#define APIC_DEST_MASK 0x800
62#define MAX_APIC_VECTOR 256
ecba9a52 63#define APIC_VECTORS_PER_REG 32
97222cc8 64
394457a9
NA		 65#define APIC_BROADCAST 0xFF
66#define X2APIC_BROADCAST 0xFFFFFFFFul
67
3b8a5df6 68#define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
548f7fb2 69#define LAPIC_TIMER_ADVANCE_ADJUST_INIT 1000
3b8a5df6
WL		 70/* step-by-step approximation to mitigate fluctuation */
71#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
72
a0c9a822
MT		 73static inline int apic_test_vector(int vec, void *bitmap)
74{
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76}
77
10606919
YZ		 78bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
79{
80 struct kvm_lapic *apic = vcpu->arch.apic;
81
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
84}
85
8680b94b
MT		 86static inline int __apic_test_and_set_vector(int vec, void *bitmap)
87{
88 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
91static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
92{
93 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94}
95
c5cc421b 96struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 97struct static_key_deferred apic_sw_disabled __read_mostly;
98
97222cc8
ED		 99static inline int apic_enabled(struct kvm_lapic *apic)
100{
c48f1496 101 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 102}
103
97222cc8
ED		 104#define LVT_MASK \
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106
107#define LINT_MASK \
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
110
6e500439
RK		 111static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
112{
113 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
114}
115
116static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
117{
118 return apic->vcpu->vcpu_id;
119}
120
0c5f81da
WL		 121bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
122{
123 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
124}
125EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt);
126
127static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
128{
129 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
130}
131
e45115b6
RK		 132static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
133 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
134 switch (map->mode) {
135 case KVM_APIC_MODE_X2APIC: {
136 u32 offset = (dest_id >> 16) * 16;
0ca52e7b 137 u32 max_apic_id = map->max_apic_id;
e45115b6
RK		 138
139 if (offset <= max_apic_id) {
140 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
141
1d487e9b 142 offset = array_index_nospec(offset, map->max_apic_id + 1);
e45115b6
RK		 143 *cluster = &map->phys_map[offset];
144 *mask = dest_id & (0xffff >> (16 - cluster_size));
145 } else {
146 *mask = 0;
147 }
3b5a5ffa 148
e45115b6
RK		 149 return true;
150 }
151 case KVM_APIC_MODE_XAPIC_FLAT:
152 *cluster = map->xapic_flat_map;
153 *mask = dest_id & 0xff;
154 return true;
155 case KVM_APIC_MODE_XAPIC_CLUSTER:
444fdad8 156 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
e45115b6
RK		 157 *mask = dest_id & 0xf;
158 return true;
159 default:
160 /* Not optimized. */
161 return false;
162 }
3548a259
RK		 163}
164
af1bae54 165static void kvm_apic_map_free(struct rcu_head *rcu)
3b5a5ffa 166{
af1bae54 167 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
3b5a5ffa 168
af1bae54 169 kvfree(map);
3b5a5ffa
RK		 170}
171
1e08ec4a
GN		 172static void recalculate_apic_map(struct kvm *kvm)
173{
174 struct kvm_apic_map *new, *old = NULL;
175 struct kvm_vcpu *vcpu;
176 int i;
6e500439 177 u32 max_id = 255; /* enough space for any xAPIC ID */
1e08ec4a
GN		 178
179 mutex_lock(&kvm->arch.apic_map_lock);
180
0ca52e7b
RK		 181 kvm_for_each_vcpu(i, vcpu, kvm)
182 if (kvm_apic_present(vcpu))
6e500439 183 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
0ca52e7b 184
a7c3e901 185 new = kvzalloc(sizeof(struct kvm_apic_map) +
254272ce
BG		 186 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
187 GFP_KERNEL_ACCOUNT);
0ca52e7b 188
1e08ec4a
GN		 189 if (!new)
190 goto out;
191
0ca52e7b
RK		 192 new->max_apic_id = max_id;
193
173beedc
NA		 194 kvm_for_each_vcpu(i, vcpu, kvm) {
195 struct kvm_lapic *apic = vcpu->arch.apic;
e45115b6
RK		 196 struct kvm_lapic **cluster;
197 u16 mask;
5bd5db38
RK		 198 u32 ldr;
199 u8 xapic_id;
200 u32 x2apic_id;
1e08ec4a 201
df04d1d1
RK		 202 if (!kvm_apic_present(vcpu))
203 continue;
204
5bd5db38
RK		 205 xapic_id = kvm_xapic_id(apic);
206 x2apic_id = kvm_x2apic_id(apic);
207
208 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
209 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
210 x2apic_id <= new->max_apic_id)
211 new->phys_map[x2apic_id] = apic;
212 /*
213 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
214 * prevent them from masking VCPUs with APIC ID <= 0xff.
215 */
216 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
217 new->phys_map[xapic_id] = apic;
3548a259 218
b14c876b
RK		 219 if (!kvm_apic_sw_enabled(apic))
220 continue;
221
6e500439
RK		 222 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
223
3b5a5ffa
RK		 224 if (apic_x2apic_mode(apic)) {
225 new->mode |= KVM_APIC_MODE_X2APIC;
226 } else if (ldr) {
227 ldr = GET_APIC_LOGICAL_ID(ldr);
dfb95954 228 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
3b5a5ffa
RK		 229 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
230 else
231 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
232 }
233
e45115b6 234 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
3548a259
RK		 235 continue;
236
e45115b6
RK		 237 if (mask)
238 cluster[ffs(mask) - 1] = apic;
1e08ec4a
GN		 239 }
240out:
241 old = rcu_dereference_protected(kvm->arch.apic_map,
242 lockdep_is_held(&kvm->arch.apic_map_lock));
243 rcu_assign_pointer(kvm->arch.apic_map, new);
244 mutex_unlock(&kvm->arch.apic_map_lock);
245
246 if (old)
af1bae54 247 call_rcu(&old->rcu, kvm_apic_map_free);
c7c9c56c 248
b053b2ae 249 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 250}
251
1e1b6c26
NA		 252static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
253{
e462755c 254 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26 255
1e6e2755 256 kvm_lapic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 257
258 if (enabled != apic->sw_enabled) {
259 apic->sw_enabled = enabled;
eb1ff0a9 260 if (enabled)
1e1b6c26 261 static_key_slow_dec_deferred(&apic_sw_disabled);
eb1ff0a9 262 else
1e1b6c26 263 static_key_slow_inc(&apic_sw_disabled.key);
b14c876b
RK		 264
265 recalculate_apic_map(apic->vcpu->kvm);
1e1b6c26
NA		 266 }
267}
268
a92e2543 269static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
1e08ec4a 270{
1e6e2755 271 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
1e08ec4a
GN		 272 recalculate_apic_map(apic->vcpu->kvm);
273}
274
275static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
276{
1e6e2755 277 kvm_lapic_set_reg(apic, APIC_LDR, id);
1e08ec4a
GN		 278 recalculate_apic_map(apic->vcpu->kvm);
279}
280
e872fa94
DDAG		 281static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
282{
283 return ((id >> 4) << 16) | (1 << (id & 0xf));
284}
285
a92e2543 286static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
257b9a5f 287{
e872fa94 288 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
257b9a5f 289
6e500439
RK		 290 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
291
a92e2543 292 kvm_lapic_set_reg(apic, APIC_ID, id);
1e6e2755 293 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
257b9a5f
RK		 294 recalculate_apic_map(apic->vcpu->kvm);
295}
296
97222cc8
ED		 297static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
298{
dfb95954 299 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 300}
301
302static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
303{
dfb95954 304 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 305}
306
a3e06bbe
LJ		 307static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
308{
f30ebc31 309 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 310}
311
97222cc8
ED		 312static inline int apic_lvtt_period(struct kvm_lapic *apic)
313{
f30ebc31 314 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 315}
316
317static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
318{
f30ebc31 319 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 320}
321
cc6e462c
JK		 322static inline int apic_lvt_nmi_mode(u32 lvt_val)
323{
324 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
325}
326
fc61b800
GN		 327void kvm_apic_set_version(struct kvm_vcpu *vcpu)
328{
329 struct kvm_lapic *apic = vcpu->arch.apic;
330 struct kvm_cpuid_entry2 *feat;
331 u32 v = APIC_VERSION;
332
bce87cce 333 if (!lapic_in_kernel(vcpu))
fc61b800
GN		 334 return;
335
0bcc3fb9
VK		 336 /*
337 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
338 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
339 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
340 * version first and level-triggered interrupts never get EOIed in
341 * IOAPIC.
342 */
fc61b800 343 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
0bcc3fb9
VK		 344 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
345 !ioapic_in_kernel(vcpu->kvm))
fc61b800 346 v |= APIC_LVR_DIRECTED_EOI;
1e6e2755 347 kvm_lapic_set_reg(apic, APIC_LVR, v);
fc61b800
GN		 348}
349
1e6e2755 350static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
a3e06bbe 351 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 352 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
353 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
354 LINT_MASK, LINT_MASK, /* LVT0-1 */
355 LVT_MASK /* LVTERR */
356};
357
358static int find_highest_vector(void *bitmap)
359{
ecba9a52
TY		 360 int vec;
361 u32 *reg;
97222cc8 362
ecba9a52
TY		 363 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
364 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
365 reg = bitmap + REG_POS(vec);
366 if (*reg)
810e6def 367 return __fls(*reg) + vec;
ecba9a52 368 }
97222cc8 369
ecba9a52 370 return -1;
97222cc8
ED		 371}
372
8680b94b
MT		 373static u8 count_vectors(void *bitmap)
374{
ecba9a52
TY		 375 int vec;
376 u32 *reg;
8680b94b 377 u8 count = 0;
ecba9a52
TY		 378
379 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
380 reg = bitmap + REG_POS(vec);
381 count += hweight32(*reg);
382 }
383
8680b94b
MT		 384 return count;
385}
386
e7387b0e 387bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
a20ed54d 388{
810e6def 389 u32 i, vec;
e7387b0e
LA		 390 u32 pir_val, irr_val, prev_irr_val;
391 int max_updated_irr;
392
393 max_updated_irr = -1;
394 *max_irr = -1;
a20ed54d 395
810e6def 396 for (i = vec = 0; i <= 7; i++, vec += 32) {
ad361091 397 pir_val = READ_ONCE(pir[i]);
810e6def 398 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
ad361091 399 if (pir_val) {
e7387b0e 400 prev_irr_val = irr_val;
810e6def
PB		 401 irr_val |= xchg(&pir[i], 0);
402 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
e7387b0e
LA		 403 if (prev_irr_val != irr_val) {
404 max_updated_irr =
405 __fls(irr_val ^ prev_irr_val) + vec;
406 }
ad361091 407 }
810e6def 408 if (irr_val)
e7387b0e 409 *max_irr = __fls(irr_val) + vec;
a20ed54d 410 }
810e6def 411
e7387b0e
LA		 412 return ((max_updated_irr != -1) &&
413 (max_updated_irr == *max_irr));
a20ed54d 414}
705699a1
WV		 415EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
416
e7387b0e 417bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
705699a1
WV		 418{
419 struct kvm_lapic *apic = vcpu->arch.apic;
420
e7387b0e 421 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
705699a1 422}
a20ed54d
YZ		 423EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
424
33e4c686 425static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 426{
33e4c686 427 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 428}
429
430static inline int apic_find_highest_irr(struct kvm_lapic *apic)
431{
432 int result;
433
c7c9c56c
YZ		 434 /*
435 * Note that irr_pending is just a hint. It will be always
436 * true with virtual interrupt delivery enabled.
437 */
33e4c686
GN		 438 if (!apic->irr_pending)
439 return -1;
440
441 result = apic_search_irr(apic);
97222cc8
ED		 442 ASSERT(result == -1 || result >= 16);
443
444 return result;
445}
446
33e4c686
GN		 447static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
448{
56cc2406
WL		 449 struct kvm_vcpu *vcpu;
450
451 vcpu = apic->vcpu;
452
d62caabb 453 if (unlikely(vcpu->arch.apicv_active)) {
b95234c8 454 /* need to update RVI */
ee171d2f 455 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
b95234c8
PB		 456 kvm_x86_ops->hwapic_irr_update(vcpu,
457 apic_find_highest_irr(apic));
f210f757
NA		 458 } else {
459 apic->irr_pending = false;
ee171d2f 460 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 461 if (apic_search_irr(apic) != -1)
462 apic->irr_pending = true;
56cc2406 463 }
33e4c686
GN		 464}
465
8680b94b
MT		 466static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
467{
56cc2406
WL		 468 struct kvm_vcpu *vcpu;
469
470 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
471 return;
472
473 vcpu = apic->vcpu;
fc57ac2c 474
8680b94b 475 /*
56cc2406
WL		 476 * With APIC virtualization enabled, all caching is disabled
477 * because the processor can modify ISR under the hood. Instead
478 * just set SVI.
8680b94b 479 */
d62caabb 480 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 481 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
56cc2406
WL		 482 else {
483 ++apic->isr_count;
484 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
485 /*
486 * ISR (in service register) bit is set when injecting an interrupt.
487 * The highest vector is injected. Thus the latest bit set matches
488 * the highest bit in ISR.
489 */
490 apic->highest_isr_cache = vec;
491 }
8680b94b
MT		 492}
493
fc57ac2c
PB		 494static inline int apic_find_highest_isr(struct kvm_lapic *apic)
495{
496 int result;
497
498 /*
499 * Note that isr_count is always 1, and highest_isr_cache
500 * is always -1, with APIC virtualization enabled.
501 */
502 if (!apic->isr_count)
503 return -1;
504 if (likely(apic->highest_isr_cache != -1))
505 return apic->highest_isr_cache;
506
507 result = find_highest_vector(apic->regs + APIC_ISR);
508 ASSERT(result == -1 || result >= 16);
509
510 return result;
511}
512
8680b94b
MT		 513static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
514{
fc57ac2c
PB		 515 struct kvm_vcpu *vcpu;
516 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
517 return;
518
519 vcpu = apic->vcpu;
520
521 /*
522 * We do get here for APIC virtualization enabled if the guest
523 * uses the Hyper-V APIC enlightenment. In this case we may need
524 * to trigger a new interrupt delivery by writing the SVI field;
525 * on the other hand isr_count and highest_isr_cache are unused
526 * and must be left alone.
527 */
d62caabb 528 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 529 kvm_x86_ops->hwapic_isr_update(vcpu,
fc57ac2c
PB		 530 apic_find_highest_isr(apic));
531 else {
8680b94b 532 --apic->isr_count;
fc57ac2c
PB		 533 BUG_ON(apic->isr_count < 0);
534 apic->highest_isr_cache = -1;
535 }
8680b94b
MT		 536}
537
6e5d865c
YS		 538int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
539{
33e4c686
GN		 540 /* This may race with setting of irr in __apic_accept_irq() and
541 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
542 * will cause vmexit immediately and the value will be recalculated
543 * on the next vmentry.
544 */
f8543d6a 545 return apic_find_highest_irr(vcpu->arch.apic);
6e5d865c 546}
76dfafd5 547EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
6e5d865c 548
6da7e3f6 549static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 550 int vector, int level, int trig_mode,
9e4aabe2 551 struct dest_map *dest_map);
6da7e3f6 552
b4f2225c 553int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
9e4aabe2 554 struct dest_map *dest_map)
97222cc8 555{
ad312c7c 556 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 557
58c2dde1 558 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 559 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 560}
561
4180bf1b 562int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
bdf7ffc8 563 unsigned long ipi_bitmap_high, u32 min,
4180bf1b
WL		 564 unsigned long icr, int op_64_bit)
565{
566 int i;
567 struct kvm_apic_map *map;
568 struct kvm_vcpu *vcpu;
569 struct kvm_lapic_irq irq = {0};
570 int cluster_size = op_64_bit ? 64 : 32;
571 int count = 0;
572
573 irq.vector = icr & APIC_VECTOR_MASK;
574 irq.delivery_mode = icr & APIC_MODE_MASK;
575 irq.level = (icr & APIC_INT_ASSERT) != 0;
576 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
577
578 if (icr & APIC_DEST_MASK)
579 return -KVM_EINVAL;
580 if (icr & APIC_SHORT_MASK)
581 return -KVM_EINVAL;
582
583 rcu_read_lock();
584 map = rcu_dereference(kvm->arch.apic_map);
585
38ab012f
WL		 586 if (unlikely(!map)) {
587 count = -EOPNOTSUPP;
588 goto out;
589 }
590
bdf7ffc8
WL		 591 if (min > map->max_apic_id)
592 goto out;
4180bf1b 593 /* Bits above cluster_size are masked in the caller. */
bdf7ffc8
WL		 594 for_each_set_bit(i, &ipi_bitmap_low,
595 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
596 if (map->phys_map[min + i]) {
597 vcpu = map->phys_map[min + i]->vcpu;
598 count += kvm_apic_set_irq(vcpu, &irq, NULL);
599 }
4180bf1b
WL		 600 }
601
602 min += cluster_size;
bdf7ffc8
WL		 603
604 if (min > map->max_apic_id)
605 goto out;
606
607 for_each_set_bit(i, &ipi_bitmap_high,
608 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
609 if (map->phys_map[min + i]) {
610 vcpu = map->phys_map[min + i]->vcpu;
611 count += kvm_apic_set_irq(vcpu, &irq, NULL);
612 }
4180bf1b
WL		 613 }
614
bdf7ffc8 615out:
4180bf1b
WL		 616 rcu_read_unlock();
617 return count;
618}
619
ae7a2a3f
MT		 620static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
621{
4e335d9e
PB		 622
623 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
624 sizeof(val));
ae7a2a3f
MT		 625}
626
627static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
628{
4e335d9e
PB		 629
630 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
631 sizeof(*val));
ae7a2a3f
MT		 632}
633
634static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
635{
636 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
637}
638
639static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
640{
641 u8 val;
642 if (pv_eoi_get_user(vcpu, &val) < 0)
0d88800d 643 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
96893977 644 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 645 return val & 0x1;
646}
647
648static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
649{
650 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
0d88800d 651 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
96893977 652 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 653 return;
654 }
655 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
656}
657
658static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
659{
660 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
0d88800d 661 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
96893977 662 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 663 return;
664 }
665 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
666}
667
b3c045d3
PB		 668static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
669{
3d92789f 670 int highest_irr;
fa59cc00 671 if (apic->vcpu->arch.apicv_active)
76dfafd5
PB		 672 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
673 else
674 highest_irr = apic_find_highest_irr(apic);
b3c045d3
PB		 675 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
676 return -1;
677 return highest_irr;
678}
679
680static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
97222cc8 681{
3842d135 682 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 683 int isr;
684
dfb95954
SS		 685 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
686 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 687 isr = apic_find_highest_isr(apic);
688 isrv = (isr != -1) ? isr : 0;
689
690 if ((tpr & 0xf0) >= (isrv & 0xf0))
691 ppr = tpr & 0xff;
692 else
693 ppr = isrv & 0xf0;
694
b3c045d3
PB		 695 *new_ppr = ppr;
696 if (old_ppr != ppr)
1e6e2755 697 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
b3c045d3
PB		 698
699 return ppr < old_ppr;
700}
701
702static void apic_update_ppr(struct kvm_lapic *apic)
703{
704 u32 ppr;
705
26fbbee5
PB		 706 if (__apic_update_ppr(apic, &ppr) &&
707 apic_has_interrupt_for_ppr(apic, ppr) != -1)
b3c045d3 708 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
97222cc8
ED		 709}
710
eb90f341
PB		 711void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
712{
713 apic_update_ppr(vcpu->arch.apic);
714}
715EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
716
97222cc8
ED		 717static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
718{
1e6e2755 719 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
97222cc8
ED		 720 apic_update_ppr(apic);
721}
722
03d2249e 723static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 724{
b4535b58
RK		 725 return mda == (apic_x2apic_mode(apic) ?
726 X2APIC_BROADCAST : APIC_BROADCAST);
394457a9
NA		 727}
728
03d2249e 729static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 730{
03d2249e
RK		 731 if (kvm_apic_broadcast(apic, mda))
732 return true;
733
734 if (apic_x2apic_mode(apic))
6e500439 735 return mda == kvm_x2apic_id(apic);
03d2249e 736
5bd5db38
RK		 737 /*
738 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
739 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
740 * this allows unique addressing of VCPUs with APIC ID over 0xff.
741 * The 0xff condition is needed because writeable xAPIC ID.
742 */
743 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
744 return true;
745
b4535b58 746 return mda == kvm_xapic_id(apic);
97222cc8
ED		 747}
748
52c233a4 749static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 750{
0105d1a5
GN		 751 u32 logical_id;
752
394457a9 753 if (kvm_apic_broadcast(apic, mda))
9368b567 754 return true;
394457a9 755
dfb95954 756 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
97222cc8 757
9368b567 758 if (apic_x2apic_mode(apic))
8a395363
RK		 759 return ((logical_id >> 16) == (mda >> 16))
760 && (logical_id & mda & 0xffff) != 0;
97222cc8 761
9368b567 762 logical_id = GET_APIC_LOGICAL_ID(logical_id);
97222cc8 763
dfb95954 764 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
97222cc8 765 case APIC_DFR_FLAT:
9368b567 766 return (logical_id & mda) != 0;
97222cc8 767 case APIC_DFR_CLUSTER:
9368b567
RK		 768 return ((logical_id >> 4) == (mda >> 4))
769 && (logical_id & mda & 0xf) != 0;
97222cc8 770 default:
9368b567 771 return false;
97222cc8 772 }
97222cc8
ED		 773}
774
c519265f
RK		 775/* The KVM local APIC implementation has two quirks:
776 *
b4535b58
RK		 777 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
778 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
779 * KVM doesn't do that aliasing.
c519265f
RK		 780 *
781 * - in-kernel IOAPIC messages have to be delivered directly to
782 * x2APIC, because the kernel does not support interrupt remapping.
783 * In order to support broadcast without interrupt remapping, x2APIC
784 * rewrites the destination of non-IPI messages from APIC_BROADCAST
785 * to X2APIC_BROADCAST.
786 *
787 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
788 * important when userspace wants to use x2APIC-format MSIs, because
789 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
03d2249e 790 */
c519265f
RK		 791static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
792 struct kvm_lapic *source, struct kvm_lapic *target)
03d2249e
RK		 793{
794 bool ipi = source != NULL;
03d2249e 795
c519265f 796 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
b4535b58 797 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
03d2249e
RK		 798 return X2APIC_BROADCAST;
799
b4535b58 800 return dest_id;
03d2249e
RK		 801}
802
52c233a4 803bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 804 int short_hand, unsigned int dest, int dest_mode)
97222cc8 805{
ad312c7c 806 struct kvm_lapic *target = vcpu->arch.apic;
c519265f 807 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
97222cc8 808
bd371396 809 ASSERT(target);
97222cc8
ED		 810 switch (short_hand) {
811 case APIC_DEST_NOSHORT:
3697f302 812 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 813 return kvm_apic_match_physical_addr(target, mda);
343f94fe 814 else
03d2249e 815 return kvm_apic_match_logical_addr(target, mda);
97222cc8 816 case APIC_DEST_SELF:
9368b567 817 return target == source;
97222cc8 818 case APIC_DEST_ALLINC:
9368b567 819 return true;
97222cc8 820 case APIC_DEST_ALLBUT:
9368b567 821 return target != source;
97222cc8 822 default:
9368b567 823 return false;
97222cc8 824 }
97222cc8 825}
1e6e2755 826EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
97222cc8 827
52004014
FW		 828int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
829 const unsigned long *bitmap, u32 bitmap_size)
830{
831 u32 mod;
832 int i, idx = -1;
833
834 mod = vector % dest_vcpus;
835
836 for (i = 0; i <= mod; i++) {
837 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
838 BUG_ON(idx == bitmap_size);
839 }
840
841 return idx;
842}
843
4efd805f
RK		 844static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
845{
846 if (!kvm->arch.disabled_lapic_found) {
847 kvm->arch.disabled_lapic_found = true;
848 printk(KERN_INFO
849 "Disabled LAPIC found during irq injection\n");
850 }
851}
852
c519265f
RK		 853static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
854 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
1e08ec4a 855{
c519265f
RK		 856 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
857 if ((irq->dest_id == APIC_BROADCAST &&
858 map->mode != KVM_APIC_MODE_X2APIC))
859 return true;
860 if (irq->dest_id == X2APIC_BROADCAST)
861 return true;
862 } else {
863 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
864 if (irq->dest_id == (x2apic_ipi ?
865 X2APIC_BROADCAST : APIC_BROADCAST))
866 return true;
867 }
1e08ec4a 868
c519265f
RK		 869 return false;
870}
1e08ec4a 871
64aa47bf
RK		 872/* Return true if the interrupt can be handled by using *bitmap as index mask
873 * for valid destinations in *dst array.
874 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
875 * Note: we may have zero kvm_lapic destinations when we return true, which
876 * means that the interrupt should be dropped. In this case, *bitmap would be
877 * zero and *dst undefined.
878 */
879static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
880 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
881 struct kvm_apic_map *map, struct kvm_lapic ***dst,
882 unsigned long *bitmap)
883{
884 int i, lowest;
1e08ec4a 885
64aa47bf
RK		 886 if (irq->shorthand == APIC_DEST_SELF && src) {
887 *dst = src;
888 *bitmap = 1;
889 return true;
890 } else if (irq->shorthand)
1e08ec4a
GN		 891 return false;
892
c519265f 893 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
9ea369b0
RK		 894 return false;
895
64aa47bf 896 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
0ca52e7b 897 if (irq->dest_id > map->max_apic_id) {
64aa47bf
RK		 898 *bitmap = 0;
899 } else {
1d487e9b
PB		 900 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
901 *dst = &map->phys_map[dest_id];
64aa47bf
RK		 902 *bitmap = 1;
903 }
1e08ec4a 904 return true;
bea15428 905 }
698f9755 906
e45115b6
RK		 907 *bitmap = 0;
908 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
909 (u16 *)bitmap))
1e08ec4a 910 return false;
fa834e91 911
64aa47bf
RK		 912 if (!kvm_lowest_prio_delivery(irq))
913 return true;
3548a259 914
64aa47bf
RK		 915 if (!kvm_vector_hashing_enabled()) {
916 lowest = -1;
917 for_each_set_bit(i, bitmap, 16) {
918 if (!(*dst)[i])
919 continue;
920 if (lowest < 0)
921 lowest = i;
922 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
923 (*dst)[lowest]->vcpu) < 0)
924 lowest = i;
3548a259 925 }
64aa47bf
RK		 926 } else {
927 if (!*bitmap)
928 return true;
3548a259 929
64aa47bf
RK		 930 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
931 bitmap, 16);
45c3094a 932
64aa47bf
RK		 933 if (!(*dst)[lowest]) {
934 kvm_apic_disabled_lapic_found(kvm);
935 *bitmap = 0;
936 return true;
937 }
938 }
1e08ec4a 939
64aa47bf 940 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
1e08ec4a 941
64aa47bf
RK		 942 return true;
943}
52004014 944
64aa47bf
RK		 945bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
946 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
947{
948 struct kvm_apic_map *map;
949 unsigned long bitmap;
950 struct kvm_lapic **dst = NULL;
951 int i;
952 bool ret;
52004014 953
64aa47bf 954 *r = -1;
52004014 955
64aa47bf
RK		 956 if (irq->shorthand == APIC_DEST_SELF) {
957 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
958 return true;
959 }
52004014 960
64aa47bf
RK		 961 rcu_read_lock();
962 map = rcu_dereference(kvm->arch.apic_map);
52004014 963
64aa47bf 964 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
0624fca9
PB		 965 if (ret) {
966 *r = 0;
64aa47bf
RK		 967 for_each_set_bit(i, &bitmap, 16) {
968 if (!dst[i])
969 continue;
64aa47bf 970 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 971 }
0624fca9 972 }
1e08ec4a 973
1e08ec4a
GN		 974 rcu_read_unlock();
975 return ret;
976}
977
6228a0da
FW		 978/*
979 * This routine tries to handler interrupts in posted mode, here is how
980 * it deals with different cases:
981 * - For single-destination interrupts, handle it in posted mode
982 * - Else if vector hashing is enabled and it is a lowest-priority
983 * interrupt, handle it in posted mode and use the following mechanism
984 * to find the destinaiton vCPU.
985 * 1. For lowest-priority interrupts, store all the possible
986 * destination vCPUs in an array.
987 * 2. Use "guest vector % max number of destination vCPUs" to find
988 * the right destination vCPU in the array for the lowest-priority
989 * interrupt.
990 * - Otherwise, use remapped mode to inject the interrupt.
991 */
8feb4a04
FW		 992bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
993 struct kvm_vcpu **dest_vcpu)
994{
995 struct kvm_apic_map *map;
64aa47bf
RK		 996 unsigned long bitmap;
997 struct kvm_lapic **dst = NULL;
8feb4a04 998 bool ret = false;
8feb4a04
FW		 999
1000 if (irq->shorthand)
1001 return false;
1002
1003 rcu_read_lock();
1004 map = rcu_dereference(kvm->arch.apic_map);
1005
64aa47bf
RK		 1006 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1007 hweight16(bitmap) == 1) {
1008 unsigned long i = find_first_bit(&bitmap, 16);
6228a0da 1009
64aa47bf
RK		 1010 if (dst[i]) {
1011 *dest_vcpu = dst[i]->vcpu;
1012 ret = true;
6228a0da 1013 }
8feb4a04
FW		 1014 }
1015
8feb4a04
FW		 1016 rcu_read_unlock();
1017 return ret;
1018}
1019
97222cc8
ED		 1020/*
1021 * Add a pending IRQ into lapic.
1022 * Return 1 if successfully added and 0 if discarded.
1023 */
1024static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 1025 int vector, int level, int trig_mode,
9e4aabe2 1026 struct dest_map *dest_map)
97222cc8 1027{
6da7e3f6 1028 int result = 0;
c5ec1534 1029 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 1030
a183b638
PB		 1031 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1032 trig_mode, vector);
97222cc8 1033 switch (delivery_mode) {
97222cc8 1034 case APIC_DM_LOWEST:
e1035715 1035 vcpu->arch.apic_arb_prio++;
b2869f28 1036 /* fall through */
e1035715 1037 case APIC_DM_FIXED:
bdaffe1d
PB		 1038 if (unlikely(trig_mode && !level))
1039 break;
1040
97222cc8
ED		 1041 /* FIXME add logic for vcpu on reset */
1042 if (unlikely(!apic_enabled(apic)))
1043 break;
1044
11f5cc05
JK		 1045 result = 1;
1046
9daa5007 1047 if (dest_map) {
9e4aabe2 1048 __set_bit(vcpu->vcpu_id, dest_map->map);
9daa5007
JR		 1049 dest_map->vectors[vcpu->vcpu_id] = vector;
1050 }
a5d36f82 1051
bdaffe1d
PB		 1052 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1053 if (trig_mode)
ee171d2f
WY		 1054 kvm_lapic_set_vector(vector,
1055 apic->regs + APIC_TMR);
bdaffe1d 1056 else
ee171d2f
WY		 1057 kvm_lapic_clear_vector(vector,
1058 apic->regs + APIC_TMR);
bdaffe1d
PB		 1059 }
1060
d62caabb 1061 if (vcpu->arch.apicv_active)
5a71785d 1062 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05 1063 else {
1e6e2755 1064 kvm_lapic_set_irr(vector, apic);
5a71785d
YZ		 1065
1066 kvm_make_request(KVM_REQ_EVENT, vcpu);
1067 kvm_vcpu_kick(vcpu);
1068 }
97222cc8
ED		 1069 break;
1070
1071 case APIC_DM_REMRD:
24d2166b
R		 1072 result = 1;
1073 vcpu->arch.pv.pv_unhalted = 1;
1074 kvm_make_request(KVM_REQ_EVENT, vcpu);
1075 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1076 break;
1077
1078 case APIC_DM_SMI:
64d60670
PB		 1079 result = 1;
1080 kvm_make_request(KVM_REQ_SMI, vcpu);
1081 kvm_vcpu_kick(vcpu);
97222cc8 1082 break;
3419ffc8 1083
97222cc8 1084 case APIC_DM_NMI:
6da7e3f6 1085 result = 1;
3419ffc8 1086 kvm_inject_nmi(vcpu);
26df99c6 1087 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1088 break;
1089
1090 case APIC_DM_INIT:
a52315e1 1091 if (!trig_mode || level) {
6da7e3f6 1092 result = 1;
66450a21
JK		 1093 /* assumes that there are only KVM_APIC_INIT/SIPI */
1094 apic->pending_events = (1UL << KVM_APIC_INIT);
1095 /* make sure pending_events is visible before sending
1096 * the request */
1097 smp_wmb();
3842d135 1098 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534 1099 kvm_vcpu_kick(vcpu);
c5ec1534 1100 }
97222cc8
ED		 1101 break;
1102
1103 case APIC_DM_STARTUP:
66450a21
JK		 1104 result = 1;
1105 apic->sipi_vector = vector;
1106 /* make sure sipi_vector is visible for the receiver */
1107 smp_wmb();
1108 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1109 kvm_make_request(KVM_REQ_EVENT, vcpu);
1110 kvm_vcpu_kick(vcpu);
97222cc8
ED		 1111 break;
1112
23930f95
JK		 1113 case APIC_DM_EXTINT:
1114 /*
1115 * Should only be called by kvm_apic_local_deliver() with LVT0,
1116 * before NMI watchdog was enabled. Already handled by
1117 * kvm_apic_accept_pic_intr().
1118 */
1119 break;
1120
97222cc8
ED		 1121 default:
1122 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1123 delivery_mode);
1124 break;
1125 }
1126 return result;
1127}
1128
e1035715 1129int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 1130{
e1035715 1131 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 1132}
1133
3bb345f3
PB		 1134static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1135{
6308630b 1136 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
3bb345f3
PB		 1137}
1138
c7c9c56c
YZ		 1139static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1140{
7543a635
SR		 1141 int trigger_mode;
1142
1143 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1144 if (!kvm_ioapic_handles_vector(apic, vector))
1145 return;
3bb345f3 1146
7543a635
SR		 1147 /* Request a KVM exit to inform the userspace IOAPIC. */
1148 if (irqchip_split(apic->vcpu->kvm)) {
1149 apic->vcpu->arch.pending_ioapic_eoi = vector;
1150 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1151 return;
c7c9c56c 1152 }
7543a635
SR		 1153
1154 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1155 trigger_mode = IOAPIC_LEVEL_TRIG;
1156 else
1157 trigger_mode = IOAPIC_EDGE_TRIG;
1158
1159 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 1160}
1161
ae7a2a3f 1162static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 1163{
1164 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 1165
1166 trace_kvm_eoi(apic, vector);
1167
97222cc8
ED		 1168 /*
1169 * Not every write EOI will has corresponding ISR,
1170 * one example is when Kernel check timer on setup_IO_APIC
1171 */
1172 if (vector == -1)
ae7a2a3f 1173 return vector;
97222cc8 1174
8680b94b 1175 apic_clear_isr(vector, apic);
97222cc8
ED		 1176 apic_update_ppr(apic);
1177
5c919412
AS		 1178 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1179 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1180
c7c9c56c 1181 kvm_ioapic_send_eoi(apic, vector);
3842d135 1182 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 1183 return vector;
97222cc8
ED		 1184}
1185
c7c9c56c
YZ		 1186/*
1187 * this interface assumes a trap-like exit, which has already finished
1188 * desired side effect including vISR and vPPR update.
1189 */
1190void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1191{
1192 struct kvm_lapic *apic = vcpu->arch.apic;
1193
1194 trace_kvm_eoi(apic, vector);
1195
1196 kvm_ioapic_send_eoi(apic, vector);
1197 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1198}
1199EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1200
2b0911d1 1201static void apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
97222cc8 1202{
58c2dde1 1203 struct kvm_lapic_irq irq;
97222cc8 1204
58c2dde1
GN		 1205 irq.vector = icr_low & APIC_VECTOR_MASK;
1206 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1207 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 1208 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 1209 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1210 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 1211 irq.msi_redir_hint = false;
0105d1a5
GN		 1212 if (apic_x2apic_mode(apic))
1213 irq.dest_id = icr_high;
1214 else
1215 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 1216
1000ff8d
GN		 1217 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1218
b4f2225c 1219 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 1220}
1221
1222static u32 apic_get_tmcct(struct kvm_lapic *apic)
1223{
8003c9ae 1224 ktime_t remaining, now;
b682b814 1225 s64 ns;
9da8f4e8 1226 u32 tmcct;
97222cc8
ED		 1227
1228 ASSERT(apic != NULL);
1229
9da8f4e8 1230 /* if initial count is 0, current count should also be 0 */
dfb95954 1231 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
b963a22e 1232 apic->lapic_timer.period == 0)
9da8f4e8
KP		 1233 return 0;
1234
5587859f 1235 now = ktime_get();
8003c9ae 1236 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
b682b814 1237 if (ktime_to_ns(remaining) < 0)
8b0e1953 1238 remaining = 0;
b682b814 1239
d3c7b77d
MT		 1240 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1241 tmcct = div64_u64(ns,
1242 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 1243
1244 return tmcct;
1245}
1246
b209749f
AK		 1247static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1248{
1249 struct kvm_vcpu *vcpu = apic->vcpu;
1250 struct kvm_run *run = vcpu->run;
1251
a8eeb04a 1252 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 1253 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 1254 run->tpr_access.is_write = write;
1255}
1256
1257static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1258{
1259 if (apic->vcpu->arch.tpr_access_reporting)
1260 __report_tpr_access(apic, write);
1261}
1262
97222cc8
ED		 1263static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1264{
1265 u32 val = 0;
1266
1267 if (offset >= LAPIC_MMIO_LENGTH)
1268 return 0;
1269
1270 switch (offset) {
1271 case APIC_ARBPRI:
97222cc8
ED		 1272 break;
1273
1274 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1275 if (apic_lvtt_tscdeadline(apic))
1276 return 0;
1277
97222cc8
ED		 1278 val = apic_get_tmcct(apic);
1279 break;
4a4541a4
AK		 1280 case APIC_PROCPRI:
1281 apic_update_ppr(apic);
dfb95954 1282 val = kvm_lapic_get_reg(apic, offset);
4a4541a4 1283 break;
b209749f
AK		 1284 case APIC_TASKPRI:
1285 report_tpr_access(apic, false);
1286 /* fall thru */
97222cc8 1287 default:
dfb95954 1288 val = kvm_lapic_get_reg(apic, offset);
97222cc8
ED		 1289 break;
1290 }
1291
1292 return val;
1293}
1294
d76685c4
GH		 1295static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1296{
1297 return container_of(dev, struct kvm_lapic, dev);
1298}
1299
01402cf8
PB		 1300#define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1301#define APIC_REGS_MASK(first, count) \
1302 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1303
1e6e2755 1304int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
0105d1a5 1305 void *data)
97222cc8 1306{
97222cc8
ED		 1307 unsigned char alignment = offset & 0xf;
1308 u32 result;
d5b0b5b1 1309 /* this bitmask has a bit cleared for each reserved register */
01402cf8
PB		 1310 u64 valid_reg_mask =
1311 APIC_REG_MASK(APIC_ID) |
1312 APIC_REG_MASK(APIC_LVR) |
1313 APIC_REG_MASK(APIC_TASKPRI) |
1314 APIC_REG_MASK(APIC_PROCPRI) |
1315 APIC_REG_MASK(APIC_LDR) |
1316 APIC_REG_MASK(APIC_DFR) |
1317 APIC_REG_MASK(APIC_SPIV) |
1318 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1319 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1320 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1321 APIC_REG_MASK(APIC_ESR) |
1322 APIC_REG_MASK(APIC_ICR) |
1323 APIC_REG_MASK(APIC_ICR2) |
1324 APIC_REG_MASK(APIC_LVTT) |
1325 APIC_REG_MASK(APIC_LVTTHMR) |
1326 APIC_REG_MASK(APIC_LVTPC) |
1327 APIC_REG_MASK(APIC_LVT0) |
1328 APIC_REG_MASK(APIC_LVT1) |
1329 APIC_REG_MASK(APIC_LVTERR) |
1330 APIC_REG_MASK(APIC_TMICT) |
1331 APIC_REG_MASK(APIC_TMCCT) |
1332 APIC_REG_MASK(APIC_TDCR);
1333
1334 /* ARBPRI is not valid on x2APIC */
1335 if (!apic_x2apic_mode(apic))
1336 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
0105d1a5 1337
0d88800d 1338 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
0105d1a5 1339 return 1;
0105d1a5 1340
97222cc8
ED		 1341 result = __apic_read(apic, offset & ~0xf);
1342
229456fc
MT		 1343 trace_kvm_apic_read(offset, result);
1344
97222cc8
ED		 1345 switch (len) {
1346 case 1:
1347 case 2:
1348 case 4:
1349 memcpy(data, (char *)&result + alignment, len);
1350 break;
1351 default:
1352 printk(KERN_ERR "Local APIC read with len = %x, "
1353 "should be 1,2, or 4 instead\n", len);
1354 break;
1355 }
bda9020e 1356 return 0;
97222cc8 1357}
1e6e2755 1358EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
97222cc8 1359
0105d1a5
GN		 1360static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1361{
d1766202
VK		 1362 return addr >= apic->base_address &&
1363 addr < apic->base_address + LAPIC_MMIO_LENGTH;
0105d1a5
GN		 1364}
1365
e32edf4f 1366static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1367 gpa_t address, int len, void *data)
1368{
1369 struct kvm_lapic *apic = to_lapic(this);
1370 u32 offset = address - apic->base_address;
1371
1372 if (!apic_mmio_in_range(apic, address))
1373 return -EOPNOTSUPP;
1374
d1766202
VK		 1375 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1376 if (!kvm_check_has_quirk(vcpu->kvm,
1377 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1378 return -EOPNOTSUPP;
1379
1380 memset(data, 0xff, len);
1381 return 0;
1382 }
1383
1e6e2755 1384 kvm_lapic_reg_read(apic, offset, len, data);
0105d1a5
GN		 1385
1386 return 0;
1387}
1388
97222cc8
ED		 1389static void update_divide_count(struct kvm_lapic *apic)
1390{
1391 u32 tmp1, tmp2, tdcr;
1392
dfb95954 1393 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1394 tmp1 = tdcr & 0xf;
1395 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1396 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1397}
1398
ccbfa1d3
WL		 1399static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1400{
1401 /*
1402 * Do not allow the guest to program periodic timers with small
1403 * interval, since the hrtimers are not throttled by the host
1404 * scheduler.
1405 */
dedf9c5e 1406 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
ccbfa1d3
WL		 1407 s64 min_period = min_timer_period_us * 1000LL;
1408
1409 if (apic->lapic_timer.period < min_period) {
1410 pr_info_ratelimited(
1411 "kvm: vcpu %i: requested %lld ns "
1412 "lapic timer period limited to %lld ns\n",
1413 apic->vcpu->vcpu_id,
1414 apic->lapic_timer.period, min_period);
1415 apic->lapic_timer.period = min_period;
1416 }
1417 }
1418}
1419
b6ac0695
RK		 1420static void apic_update_lvtt(struct kvm_lapic *apic)
1421{
dfb95954 1422 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
b6ac0695
RK		 1423 apic->lapic_timer.timer_mode_mask;
1424
1425 if (apic->lapic_timer.timer_mode != timer_mode) {
c69518c8 1426 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
dedf9c5e 1427 APIC_LVT_TIMER_TSCDEADLINE)) {
dedf9c5e 1428 hrtimer_cancel(&apic->lapic_timer.timer);
44275932
RK		 1429 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1430 apic->lapic_timer.period = 0;
1431 apic->lapic_timer.tscdeadline = 0;
dedf9c5e 1432 }
b6ac0695 1433 apic->lapic_timer.timer_mode = timer_mode;
dedf9c5e 1434 limit_periodic_timer_frequency(apic);
b6ac0695
RK		 1435 }
1436}
1437
d0659d94
MT		 1438/*
1439 * On APICv, this test will cause a busy wait
1440 * during a higher-priority task.
1441 */
1442
1443static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1444{
1445 struct kvm_lapic *apic = vcpu->arch.apic;
dfb95954 1446 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
d0659d94
MT		 1447
1448 if (kvm_apic_hw_enabled(apic)) {
1449 int vec = reg & APIC_VECTOR_MASK;
f9339860 1450 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1451
d62caabb 1452 if (vcpu->arch.apicv_active)
f9339860
MT		 1453 bitmap = apic->regs + APIC_IRR;
1454
1455 if (apic_test_vector(vec, bitmap))
1456 return true;
d0659d94
MT		 1457 }
1458 return false;
1459}
1460
b6aa57c6
SC		 1461static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1462{
1463 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1464
1465 /*
1466 * If the guest TSC is running at a different ratio than the host, then
1467 * convert the delay to nanoseconds to achieve an accurate delay. Note
1468 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1469 * always for VMX enabled hardware.
1470 */
1471 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1472 __delay(min(guest_cycles,
1473 nsec_to_cycles(vcpu, timer_advance_ns)));
1474 } else {
1475 u64 delay_ns = guest_cycles * 1000000ULL;
1476 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1477 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1478 }
1479}
1480
84ea3aca 1481static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
ec0671d5 1482 s64 advance_expire_delta)
d0659d94
MT		 1483{
1484 struct kvm_lapic *apic = vcpu->arch.apic;
39497d76 1485 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
84ea3aca
WL		 1486 u64 ns;
1487
1488 /* too early */
ec0671d5
WL		 1489 if (advance_expire_delta < 0) {
1490 ns = -advance_expire_delta * 1000000ULL;
84ea3aca
WL		 1491 do_div(ns, vcpu->arch.virtual_tsc_khz);
1492 timer_advance_ns -= min((u32)ns,
1493 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1494 } else {
1495 /* too late */
ec0671d5 1496 ns = advance_expire_delta * 1000000ULL;
84ea3aca
WL		 1497 do_div(ns, vcpu->arch.virtual_tsc_khz);
1498 timer_advance_ns += min((u32)ns,
1499 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1500 }
1501
ec0671d5 1502 if (abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
84ea3aca
WL		 1503 apic->lapic_timer.timer_advance_adjust_done = true;
1504 if (unlikely(timer_advance_ns > 5000)) {
548f7fb2
WL		 1505 timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT;
1506 apic->lapic_timer.timer_advance_adjust_done = false;
84ea3aca
WL		 1507 }
1508 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1509}
1510
0c5f81da 1511static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
84ea3aca
WL		 1512{
1513 struct kvm_lapic *apic = vcpu->arch.apic;
1514 u64 guest_tsc, tsc_deadline;
d0659d94 1515
d0659d94
MT		 1516 if (apic->lapic_timer.expired_tscdeadline == 0)
1517 return;
1518
d0659d94
MT		 1519 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1520 apic->lapic_timer.expired_tscdeadline = 0;
4ba76538 1521 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
ec0671d5 1522 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
d0659d94 1523
d0659d94 1524 if (guest_tsc < tsc_deadline)
b6aa57c6 1525 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
3b8a5df6 1526
84ea3aca 1527 if (unlikely(!apic->lapic_timer.timer_advance_adjust_done))
ec0671d5 1528 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
5d87db71 1529}
0c5f81da
WL		 1530
1531void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1532{
1533 if (lapic_timer_int_injected(vcpu))
1534 __kvm_wait_lapic_expire(vcpu);
1535}
b6c4bc65 1536EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
5d87db71 1537
0c5f81da
WL		 1538static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1539{
1540 struct kvm_timer *ktimer = &apic->lapic_timer;
1541
1542 kvm_apic_local_deliver(apic, APIC_LVTT);
1543 if (apic_lvtt_tscdeadline(apic))
1544 ktimer->tscdeadline = 0;
1545 if (apic_lvtt_oneshot(apic)) {
1546 ktimer->tscdeadline = 0;
1547 ktimer->target_expiration = 0;
1548 }
1549}
1550
1551static void apic_timer_expired(struct kvm_lapic *apic)
1552{
1553 struct kvm_vcpu *vcpu = apic->vcpu;
0c5f81da
WL		 1554 struct kvm_timer *ktimer = &apic->lapic_timer;
1555
1556 if (atomic_read(&apic->lapic_timer.pending))
1557 return;
1558
1559 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1560 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1561
1562 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1563 if (apic->lapic_timer.timer_advance_ns)
1564 __kvm_wait_lapic_expire(vcpu);
1565 kvm_apic_inject_pending_timer_irqs(apic);
1566 return;
1567 }
1568
1569 atomic_inc(&apic->lapic_timer.pending);
1570 kvm_set_pending_timer(vcpu);
0c5f81da
WL		 1571}
1572
53f9eedf
YJ		 1573static void start_sw_tscdeadline(struct kvm_lapic *apic)
1574{
39497d76
SC		 1575 struct kvm_timer *ktimer = &apic->lapic_timer;
1576 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
53f9eedf
YJ		 1577 u64 ns = 0;
1578 ktime_t expire;
1579 struct kvm_vcpu *vcpu = apic->vcpu;
1580 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1581 unsigned long flags;
1582 ktime_t now;
1583
1584 if (unlikely(!tscdeadline || !this_tsc_khz))
1585 return;
1586
1587 local_irq_save(flags);
1588
5587859f 1589 now = ktime_get();
53f9eedf 1590 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
c09d65d9
LA		 1591
1592 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1593 do_div(ns, this_tsc_khz);
1594
1595 if (likely(tscdeadline > guest_tsc) &&
39497d76 1596 likely(ns > apic->lapic_timer.timer_advance_ns)) {
53f9eedf 1597 expire = ktime_add_ns(now, ns);
39497d76 1598 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
2c0d278f 1599 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
53f9eedf
YJ		 1600 } else
1601 apic_timer_expired(apic);
1602
1603 local_irq_restore(flags);
1604}
1605
c301b909
WL		 1606static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1607{
1608 ktime_t now, remaining;
1609 u64 ns_remaining_old, ns_remaining_new;
1610
1611 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1612 * APIC_BUS_CYCLE_NS * apic->divide_count;
1613 limit_periodic_timer_frequency(apic);
1614
1615 now = ktime_get();
1616 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1617 if (ktime_to_ns(remaining) < 0)
1618 remaining = 0;
1619
1620 ns_remaining_old = ktime_to_ns(remaining);
1621 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1622 apic->divide_count, old_divisor);
1623
1624 apic->lapic_timer.tscdeadline +=
1625 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1626 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1627 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1628}
1629
8003c9ae 1630static bool set_target_expiration(struct kvm_lapic *apic)
7d7f7da2
WL		 1631{
1632 ktime_t now;
8003c9ae 1633 u64 tscl = rdtsc();
7d7f7da2 1634
5587859f 1635 now = ktime_get();
7d7f7da2 1636 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
8003c9ae 1637 * APIC_BUS_CYCLE_NS * apic->divide_count;
7d7f7da2 1638
5d74a699
RK		 1639 if (!apic->lapic_timer.period) {
1640 apic->lapic_timer.tscdeadline = 0;
8003c9ae 1641 return false;
7d7f7da2
WL		 1642 }
1643
ccbfa1d3 1644 limit_periodic_timer_frequency(apic);
7d7f7da2 1645
8003c9ae
WL		 1646 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1647 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1648 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1649
1650 return true;
1651}
1652
1653static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1654{
d8f2f498
DV		 1655 ktime_t now = ktime_get();
1656 u64 tscl = rdtsc();
1657 ktime_t delta;
1658
1659 /*
1660 * Synchronize both deadlines to the same time source or
1661 * differences in the periods (caused by differences in the
1662 * underlying clocks or numerical approximation errors) will
1663 * cause the two to drift apart over time as the errors
1664 * accumulate.
1665 */
8003c9ae
WL		 1666 apic->lapic_timer.target_expiration =
1667 ktime_add_ns(apic->lapic_timer.target_expiration,
1668 apic->lapic_timer.period);
d8f2f498
DV		 1669 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1670 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1671 nsec_to_cycles(apic->vcpu, delta);
7d7f7da2
WL		 1672}
1673
ecf08dad
AB		 1674static void start_sw_period(struct kvm_lapic *apic)
1675{
1676 if (!apic->lapic_timer.period)
1677 return;
1678
1679 if (ktime_after(ktime_get(),
1680 apic->lapic_timer.target_expiration)) {
1681 apic_timer_expired(apic);
1682
1683 if (apic_lvtt_oneshot(apic))
1684 return;
1685
1686 advance_periodic_target_expiration(apic);
1687 }
1688
1689 hrtimer_start(&apic->lapic_timer.timer,
1690 apic->lapic_timer.target_expiration,
4d151bf3 1691 HRTIMER_MODE_ABS);
ecf08dad
AB		 1692}
1693
ce7a058a
YJ		 1694bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1695{
91005300
WL		 1696 if (!lapic_in_kernel(vcpu))
1697 return false;
1698
ce7a058a
YJ		 1699 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1700}
1701EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1702
7e810a38 1703static void cancel_hv_timer(struct kvm_lapic *apic)
bd97ad0e 1704{
1d518c68 1705 WARN_ON(preemptible());
a749e247 1706 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
bd97ad0e
WL		 1707 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1708 apic->lapic_timer.hv_timer_in_use = false;
1709}
1710
a749e247 1711static bool start_hv_timer(struct kvm_lapic *apic)
196f20ca 1712{
35ee9e48 1713 struct kvm_timer *ktimer = &apic->lapic_timer;
f9927982
SC		 1714 struct kvm_vcpu *vcpu = apic->vcpu;
1715 bool expired;
196f20ca 1716
1d518c68 1717 WARN_ON(preemptible());
a749e247
PB		 1718 if (!kvm_x86_ops->set_hv_timer)
1719 return false;
1720
86bbc1e6
RK		 1721 if (!ktimer->tscdeadline)
1722 return false;
1723
f9927982 1724 if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
35ee9e48
PB		 1725 return false;
1726
1727 ktimer->hv_timer_in_use = true;
1728 hrtimer_cancel(&ktimer->timer);
196f20ca 1729
35ee9e48 1730 /*
f1ba5cfb
SC		 1731 * To simplify handling the periodic timer, leave the hv timer running
1732 * even if the deadline timer has expired, i.e. rely on the resulting
1733 * VM-Exit to recompute the periodic timer's target expiration.
35ee9e48 1734 */
f1ba5cfb
SC		 1735 if (!apic_lvtt_period(apic)) {
1736 /*
1737 * Cancel the hv timer if the sw timer fired while the hv timer
1738 * was being programmed, or if the hv timer itself expired.
1739 */
1740 if (atomic_read(&ktimer->pending)) {
1741 cancel_hv_timer(apic);
f9927982 1742 } else if (expired) {
c8533544 1743 apic_timer_expired(apic);
f1ba5cfb
SC		 1744 cancel_hv_timer(apic);
1745 }
c8533544 1746 }
a749e247 1747
f9927982 1748 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
f1ba5cfb 1749
35ee9e48
PB		 1750 return true;
1751}
1752
a749e247 1753static void start_sw_timer(struct kvm_lapic *apic)
35ee9e48 1754{
a749e247 1755 struct kvm_timer *ktimer = &apic->lapic_timer;
1d518c68
WL		 1756
1757 WARN_ON(preemptible());
a749e247
PB		 1758 if (apic->lapic_timer.hv_timer_in_use)
1759 cancel_hv_timer(apic);
1760 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1761 return;
1762
1763 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1764 start_sw_period(apic);
1765 else if (apic_lvtt_tscdeadline(apic))
1766 start_sw_tscdeadline(apic);
1767 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1768}
35ee9e48 1769
a749e247
PB		 1770static void restart_apic_timer(struct kvm_lapic *apic)
1771{
1d518c68 1772 preempt_disable();
4ca88b3f
SC		 1773
1774 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1775 goto out;
1776
a749e247
PB		 1777 if (!start_hv_timer(apic))
1778 start_sw_timer(apic);
4ca88b3f 1779out:
1d518c68 1780 preempt_enable();
196f20ca
WL		 1781}
1782
8003c9ae
WL		 1783void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1784{
1785 struct kvm_lapic *apic = vcpu->arch.apic;
1786
1d518c68
WL		 1787 preempt_disable();
1788 /* If the preempt notifier has already run, it also called apic_timer_expired */
1789 if (!apic->lapic_timer.hv_timer_in_use)
1790 goto out;
8003c9ae
WL		 1791 WARN_ON(swait_active(&vcpu->wq));
1792 cancel_hv_timer(apic);
1793 apic_timer_expired(apic);
1794
1795 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1796 advance_periodic_target_expiration(apic);
a749e247 1797 restart_apic_timer(apic);
8003c9ae 1798 }
1d518c68
WL		 1799out:
1800 preempt_enable();
8003c9ae
WL		 1801}
1802EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1803
ce7a058a
YJ		 1804void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1805{
a749e247 1806 restart_apic_timer(vcpu->arch.apic);
ce7a058a
YJ		 1807}
1808EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1809
1810void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1811{
1812 struct kvm_lapic *apic = vcpu->arch.apic;
1813
1d518c68 1814 preempt_disable();
ce7a058a 1815 /* Possibly the TSC deadline timer is not enabled yet */
a749e247
PB		 1816 if (apic->lapic_timer.hv_timer_in_use)
1817 start_sw_timer(apic);
1d518c68 1818 preempt_enable();
a749e247
PB		 1819}
1820EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
ce7a058a 1821
a749e247
PB		 1822void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1823{
1824 struct kvm_lapic *apic = vcpu->arch.apic;
ce7a058a 1825
a749e247
PB		 1826 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1827 restart_apic_timer(apic);
ce7a058a 1828}
ce7a058a 1829
97222cc8
ED		 1830static void start_apic_timer(struct kvm_lapic *apic)
1831{
d3c7b77d 1832 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1833
a749e247
PB		 1834 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1835 && !set_target_expiration(apic))
1836 return;
1837
1838 restart_apic_timer(apic);
97222cc8
ED		 1839}
1840
cc6e462c
JK		 1841static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1842{
59fd1323 1843 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1844
59fd1323
RK		 1845 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1846 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1847 if (lvt0_in_nmi_mode) {
42720138 1848 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1849 } else
1850 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1851 }
cc6e462c
JK		 1852}
1853
1e6e2755 1854int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1855{
0105d1a5 1856 int ret = 0;
97222cc8 1857
0105d1a5 1858 trace_kvm_apic_write(reg, val);
97222cc8 1859
0105d1a5 1860 switch (reg) {
97222cc8 1861 case APIC_ID: /* Local APIC ID */
0105d1a5 1862 if (!apic_x2apic_mode(apic))
a92e2543 1863 kvm_apic_set_xapic_id(apic, val >> 24);
0105d1a5
GN		 1864 else
1865 ret = 1;
97222cc8
ED		 1866 break;
1867
1868 case APIC_TASKPRI:
b209749f 1869 report_tpr_access(apic, true);
97222cc8
ED		 1870 apic_set_tpr(apic, val & 0xff);
1871 break;
1872
1873 case APIC_EOI:
1874 apic_set_eoi(apic);
1875 break;
1876
1877 case APIC_LDR:
0105d1a5 1878 if (!apic_x2apic_mode(apic))
1e08ec4a 1879 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1880 else
1881 ret = 1;
97222cc8
ED		 1882 break;
1883
1884 case APIC_DFR:
1e08ec4a 1885 if (!apic_x2apic_mode(apic)) {
1e6e2755 1886 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1887 recalculate_apic_map(apic->vcpu->kvm);
1888 } else
0105d1a5 1889 ret = 1;
97222cc8
ED		 1890 break;
1891
fc61b800
GN		 1892 case APIC_SPIV: {
1893 u32 mask = 0x3ff;
dfb95954 1894 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1895 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1896 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1897 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1898 int i;
1899 u32 lvt_val;
1900
1e6e2755 1901 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
dfb95954 1902 lvt_val = kvm_lapic_get_reg(apic,
97222cc8 1903 APIC_LVTT + 0x10 * i);
1e6e2755 1904 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
97222cc8
ED		 1905 lvt_val | APIC_LVT_MASKED);
1906 }
b6ac0695 1907 apic_update_lvtt(apic);
d3c7b77d 1908 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1909
1910 }
1911 break;
fc61b800 1912 }
97222cc8
ED		 1913 case APIC_ICR:
1914 /* No delay here, so we always clear the pending bit */
2b0911d1
WL		 1915 val &= ~(1 << 12);
1916 apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
1917 kvm_lapic_set_reg(apic, APIC_ICR, val);
97222cc8
ED		 1918 break;
1919
1920 case APIC_ICR2:
0105d1a5
GN		 1921 if (!apic_x2apic_mode(apic))
1922 val &= 0xff000000;
1e6e2755 1923 kvm_lapic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1924 break;
1925
23930f95 1926 case APIC_LVT0:
cc6e462c 1927 apic_manage_nmi_watchdog(apic, val);
b2869f28 1928 /* fall through */
97222cc8
ED		 1929 case APIC_LVTTHMR:
1930 case APIC_LVTPC:
97222cc8
ED		 1931 case APIC_LVT1:
1932 case APIC_LVTERR:
1933 /* TODO: Check vector */
c48f1496 1934 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1935 val |= APIC_LVT_MASKED;
1936
0105d1a5 1937 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1e6e2755 1938 kvm_lapic_set_reg(apic, reg, val);
97222cc8
ED		 1939
1940 break;
1941
b6ac0695 1942 case APIC_LVTT:
c48f1496 1943 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1944 val |= APIC_LVT_MASKED;
1945 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1e6e2755 1946 kvm_lapic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1947 apic_update_lvtt(apic);
a3e06bbe
LJ		 1948 break;
1949
97222cc8 1950 case APIC_TMICT:
a3e06bbe
LJ		 1951 if (apic_lvtt_tscdeadline(apic))
1952 break;
1953
d3c7b77d 1954 hrtimer_cancel(&apic->lapic_timer.timer);
1e6e2755 1955 kvm_lapic_set_reg(apic, APIC_TMICT, val);
97222cc8 1956 start_apic_timer(apic);
0105d1a5 1957 break;
97222cc8 1958
c301b909
WL		 1959 case APIC_TDCR: {
1960 uint32_t old_divisor = apic->divide_count;
1961
1e6e2755 1962 kvm_lapic_set_reg(apic, APIC_TDCR, val);
97222cc8 1963 update_divide_count(apic);
c301b909
WL		 1964 if (apic->divide_count != old_divisor &&
1965 apic->lapic_timer.period) {
1966 hrtimer_cancel(&apic->lapic_timer.timer);
1967 update_target_expiration(apic, old_divisor);
1968 restart_apic_timer(apic);
1969 }
97222cc8 1970 break;
c301b909 1971 }
0105d1a5 1972 case APIC_ESR:
0d88800d 1973 if (apic_x2apic_mode(apic) && val != 0)
0105d1a5 1974 ret = 1;
0105d1a5
GN		 1975 break;
1976
1977 case APIC_SELF_IPI:
1978 if (apic_x2apic_mode(apic)) {
1e6e2755 1979 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
0105d1a5
GN		 1980 } else
1981 ret = 1;
1982 break;
97222cc8 1983 default:
0105d1a5 1984 ret = 1;
97222cc8
ED		 1985 break;
1986 }
0d88800d 1987
0105d1a5
GN		 1988 return ret;
1989}
1e6e2755 1990EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
0105d1a5 1991
e32edf4f 1992static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1993 gpa_t address, int len, const void *data)
1994{
1995 struct kvm_lapic *apic = to_lapic(this);
1996 unsigned int offset = address - apic->base_address;
1997 u32 val;
1998
1999 if (!apic_mmio_in_range(apic, address))
2000 return -EOPNOTSUPP;
2001
d1766202
VK		 2002 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2003 if (!kvm_check_has_quirk(vcpu->kvm,
2004 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2005 return -EOPNOTSUPP;
2006
2007 return 0;
2008 }
2009
0105d1a5
GN		 2010 /*
2011 * APIC register must be aligned on 128-bits boundary.
2012 * 32/64/128 bits registers must be accessed thru 32 bits.
2013 * Refer SDM 8.4.1
2014 */
0d88800d 2015 if (len != 4 || (offset & 0xf))
756975bb 2016 return 0;
0105d1a5
GN		 2017
2018 val = *(u32*)data;
2019
0d88800d 2020 kvm_lapic_reg_write(apic, offset & 0xff0, val);
0105d1a5 2021
bda9020e 2022 return 0;
97222cc8
ED		 2023}
2024
58fbbf26
KT		 2025void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2026{
1e6e2755 2027 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
58fbbf26
KT		 2028}
2029EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2030
83d4c286
YZ		 2031/* emulate APIC access in a trap manner */
2032void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2033{
2034 u32 val = 0;
2035
2036 /* hw has done the conditional check and inst decode */
2037 offset &= 0xff0;
2038
1e6e2755 2039 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
83d4c286
YZ		 2040
2041 /* TODO: optimize to just emulate side effect w/o one more write */
1e6e2755 2042 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
83d4c286
YZ		 2043}
2044EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2045
d589444e 2046void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 2047{
f8c1ea10
GN		 2048 struct kvm_lapic *apic = vcpu->arch.apic;
2049
ad312c7c 2050 if (!vcpu->arch.apic)
97222cc8
ED		 2051 return;
2052
f8c1ea10 2053 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 2054
c5cc421b
GN		 2055 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2056 static_key_slow_dec_deferred(&apic_hw_disabled);
2057
e462755c 2058 if (!apic->sw_enabled)
f8c1ea10 2059 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 2060
f8c1ea10
GN		 2061 if (apic->regs)
2062 free_page((unsigned long)apic->regs);
2063
2064 kfree(apic);
97222cc8
ED		 2065}
2066
2067/*
2068 *----------------------------------------------------------------------
2069 * LAPIC interface
2070 *----------------------------------------------------------------------
2071 */
a3e06bbe
LJ		 2072u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2073{
2074 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 2075
a10388e1
WL		 2076 if (!lapic_in_kernel(vcpu) ||
2077 !apic_lvtt_tscdeadline(apic))
a3e06bbe
LJ		 2078 return 0;
2079
2080 return apic->lapic_timer.tscdeadline;
2081}
2082
2083void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2084{
2085 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 2086
bce87cce 2087 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 2088 apic_lvtt_period(apic))
a3e06bbe
LJ		 2089 return;
2090
2091 hrtimer_cancel(&apic->lapic_timer.timer);
2092 apic->lapic_timer.tscdeadline = data;
2093 start_apic_timer(apic);
2094}
2095
97222cc8
ED		 2096void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2097{
ad312c7c 2098 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 2099
b93463aa 2100 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
dfb95954 2101 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 2102}
2103
2104u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2105{
97222cc8
ED		 2106 u64 tpr;
2107
dfb95954 2108 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 2109
2110 return (tpr & 0xf0) >> 4;
2111}
2112
2113void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2114{
8d14695f 2115 u64 old_value = vcpu->arch.apic_base;
ad312c7c 2116 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 2117
c7dd15b3 2118 if (!apic)
97222cc8 2119 value |= MSR_IA32_APICBASE_BSP;
c5af89b6 2120
e66d2ae7
JK		 2121 vcpu->arch.apic_base = value;
2122
c7dd15b3
JM		 2123 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2124 kvm_update_cpuid(vcpu);
2125
2126 if (!apic)
2127 return;
2128
c5cc421b 2129 /* update jump label if enable bit changes */
0dce7cd6 2130 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
49bd29ba
RK		 2131 if (value & MSR_IA32_APICBASE_ENABLE) {
2132 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
c5cc421b 2133 static_key_slow_dec_deferred(&apic_hw_disabled);
187ca84b 2134 } else {
c5cc421b 2135 static_key_slow_inc(&apic_hw_disabled.key);
187ca84b
WL		 2136 recalculate_apic_map(vcpu->kvm);
2137 }
c5cc421b
GN		 2138 }
2139
8d860bbe
JM		 2140 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2141 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2142
2143 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2144 kvm_x86_ops->set_virtual_apic_mode(vcpu);
8d14695f 2145
ad312c7c 2146 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 2147 MSR_IA32_APICBASE_BASE;
2148
db324fe6
NA		 2149 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2150 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2151 pr_warn_once("APIC base relocation is unsupported by KVM");
97222cc8
ED		 2152}
2153
d28bc9dd 2154void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8 2155{
b7e31be3 2156 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 2157 int i;
2158
b7e31be3
RK		 2159 if (!apic)
2160 return;
97222cc8 2161
97222cc8 2162 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 2163 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 2164
4d8e772b
RK		 2165 if (!init_event) {
2166 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2167 MSR_IA32_APICBASE_ENABLE);
a92e2543 2168 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
4d8e772b 2169 }
fc61b800 2170 kvm_apic_set_version(apic->vcpu);
97222cc8 2171
1e6e2755
SS		 2172 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2173 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 2174 apic_update_lvtt(apic);
52b54190
JS		 2175 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2176 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1e6e2755 2177 kvm_lapic_set_reg(apic, APIC_LVT0,
90de4a18 2178 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
dfb95954 2179 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
97222cc8 2180
1e6e2755 2181 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 2182 apic_set_spiv(apic, 0xff);
1e6e2755 2183 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 2184 if (!apic_x2apic_mode(apic))
2185 kvm_apic_set_ldr(apic, 0);
1e6e2755
SS		 2186 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2187 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2188 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2189 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2190 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
97222cc8 2191 for (i = 0; i < 8; i++) {
1e6e2755
SS		 2192 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2193 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2194 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
97222cc8 2195 }
d62caabb
AS		 2196 apic->irr_pending = vcpu->arch.apicv_active;
2197 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
8680b94b 2198 apic->highest_isr_cache = -1;
b33ac88b 2199 update_divide_count(apic);
d3c7b77d 2200 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 2201 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 2202 kvm_lapic_set_base(vcpu,
2203 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 2204 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8 2205 apic_update_ppr(apic);
4191db26
JS		 2206 if (vcpu->arch.apicv_active) {
2207 kvm_x86_ops->apicv_post_state_restore(vcpu);
2208 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2209 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2210 }
97222cc8 2211
e1035715 2212 vcpu->arch.apic_arb_prio = 0;
41383771 2213 vcpu->arch.apic_attention = 0;
97222cc8
ED		 2214}
2215
97222cc8
ED		 2216/*
2217 *----------------------------------------------------------------------
2218 * timer interface
2219 *----------------------------------------------------------------------
2220 */
1b9778da 2221
2a6eac96 2222static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 2223{
d3c7b77d 2224 return apic_lvtt_period(apic);
97222cc8
ED		 2225}
2226
3d80840d
MT		 2227int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2228{
54e9818f 2229 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 2230
1e3161b4 2231 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
54e9818f 2232 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 2233
2234 return 0;
2235}
2236
89342082 2237int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 2238{
dfb95954 2239 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
23930f95 2240 int vector, mode, trig_mode;
23930f95 2241
c48f1496 2242 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 2243 vector = reg & APIC_VECTOR_MASK;
2244 mode = reg & APIC_MODE_MASK;
2245 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 2246 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2247 NULL);
23930f95
JK		 2248 }
2249 return 0;
2250}
1b9778da 2251
8fdb2351 2252void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 2253{
8fdb2351
JK		 2254 struct kvm_lapic *apic = vcpu->arch.apic;
2255
2256 if (apic)
2257 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 2258}
2259
d76685c4
GH		 2260static const struct kvm_io_device_ops apic_mmio_ops = {
2261 .read = apic_mmio_read,
2262 .write = apic_mmio_write,
d76685c4
GH		 2263};
2264
e9d90d47
AK		 2265static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2266{
2267 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 2268 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 2269
5d87db71 2270 apic_timer_expired(apic);
e9d90d47 2271
2a6eac96 2272 if (lapic_is_periodic(apic)) {
8003c9ae 2273 advance_periodic_target_expiration(apic);
e9d90d47
AK		 2274 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2275 return HRTIMER_RESTART;
2276 } else
2277 return HRTIMER_NORESTART;
2278}
2279
c3941d9e 2280int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
97222cc8
ED		 2281{
2282 struct kvm_lapic *apic;
2283
2284 ASSERT(vcpu != NULL);
97222cc8 2285
254272ce 2286 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
97222cc8
ED		 2287 if (!apic)
2288 goto nomem;
2289
ad312c7c 2290 vcpu->arch.apic = apic;
97222cc8 2291
254272ce 2292 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
afc20184 2293 if (!apic->regs) {
97222cc8
ED		 2294 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2295 vcpu->vcpu_id);
d589444e 2296 goto nomem_free_apic;
97222cc8 2297 }
97222cc8
ED		 2298 apic->vcpu = vcpu;
2299
d3c7b77d 2300 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2c0d278f 2301 HRTIMER_MODE_ABS_HARD);
e9d90d47 2302 apic->lapic_timer.timer.function = apic_timer_fn;
c3941d9e 2303 if (timer_advance_ns == -1) {
548f7fb2 2304 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT;
c3941d9e
SC		 2305 apic->lapic_timer.timer_advance_adjust_done = false;
2306 } else {
2307 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2308 apic->lapic_timer.timer_advance_adjust_done = true;
2309 }
2310
d3c7b77d 2311
c5cc421b
GN		 2312 /*
2313 * APIC is created enabled. This will prevent kvm_lapic_set_base from
ee171d2f 2314 * thinking that APIC state has changed.
c5cc421b
GN		 2315 */
2316 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
f8c1ea10 2317 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d76685c4 2318 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 2319
2320 return 0;
d589444e
RR		 2321nomem_free_apic:
2322 kfree(apic);
a251fb90 2323 vcpu->arch.apic = NULL;
97222cc8 2324nomem:
97222cc8
ED		 2325 return -ENOMEM;
2326}
97222cc8
ED		 2327
2328int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2329{
ad312c7c 2330 struct kvm_lapic *apic = vcpu->arch.apic;
b3c045d3 2331 u32 ppr;
97222cc8 2332
bb34e690 2333 if (!kvm_apic_hw_enabled(apic))
97222cc8
ED		 2334 return -1;
2335
b3c045d3
PB		 2336 __apic_update_ppr(apic, &ppr);
2337 return apic_has_interrupt_for_ppr(apic, ppr);
97222cc8
ED		 2338}
2339
40487c68
QH		 2340int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2341{
dfb95954 2342 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 2343 int r = 0;
2344
c48f1496 2345 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 2346 r = 1;
2347 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2348 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2349 r = 1;
40487c68
QH		 2350 return r;
2351}
2352
1b9778da
ED		 2353void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2354{
ad312c7c 2355 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 2356
54e9818f 2357 if (atomic_read(&apic->lapic_timer.pending) > 0) {
0c5f81da 2358 kvm_apic_inject_pending_timer_irqs(apic);
f1ed0450 2359 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 2360 }
2361}
2362
97222cc8
ED		 2363int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2364{
2365 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 2366 struct kvm_lapic *apic = vcpu->arch.apic;
4d82d12b 2367 u32 ppr;
97222cc8
ED		 2368
2369 if (vector == -1)
2370 return -1;
2371
56cc2406
WL		 2372 /*
2373 * We get here even with APIC virtualization enabled, if doing
2374 * nested virtualization and L1 runs with the "acknowledge interrupt
2375 * on exit" mode. Then we cannot inject the interrupt via RVI,
2376 * because the process would deliver it through the IDT.
2377 */
2378
97222cc8 2379 apic_clear_irr(vector, apic);
5c919412 2380 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
4d82d12b
PB		 2381 /*
2382 * For auto-EOI interrupts, there might be another pending
2383 * interrupt above PPR, so check whether to raise another
2384 * KVM_REQ_EVENT.
2385 */
5c919412 2386 apic_update_ppr(apic);
4d82d12b
PB		 2387 } else {
2388 /*
2389 * For normal interrupts, PPR has been raised and there cannot
2390 * be a higher-priority pending interrupt---except if there was
2391 * a concurrent interrupt injection, but that would have
2392 * triggered KVM_REQ_EVENT already.
2393 */
2394 apic_set_isr(vector, apic);
2395 __apic_update_ppr(apic, &ppr);
5c919412
AS		 2396 }
2397
97222cc8
ED		 2398 return vector;
2399}
96ad2cc6 2400
a92e2543
RK		 2401static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2402 struct kvm_lapic_state *s, bool set)
2403{
2404 if (apic_x2apic_mode(vcpu->arch.apic)) {
2405 u32 *id = (u32 *)(s->regs + APIC_ID);
12806ba9 2406 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
a92e2543 2407
37131313
RK		 2408 if (vcpu->kvm->arch.x2apic_format) {
2409 if (*id != vcpu->vcpu_id)
2410 return -EINVAL;
2411 } else {
2412 if (set)
2413 *id >>= 24;
2414 else
2415 *id <<= 24;
2416 }
12806ba9
DDAG		 2417
2418 /* In x2APIC mode, the LDR is fixed and based on the id */
2419 if (set)
2420 *ldr = kvm_apic_calc_x2apic_ldr(*id);
a92e2543
RK		 2421 }
2422
2423 return 0;
2424}
2425
2426int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2427{
2428 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2429 return kvm_apic_state_fixup(vcpu, s, false);
2430}
2431
2432int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
96ad2cc6 2433{
ad312c7c 2434 struct kvm_lapic *apic = vcpu->arch.apic;
a92e2543
RK		 2435 int r;
2436
96ad2cc6 2437
5dbc8f3f 2438 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 2439 /* set SPIV separately to get count of SW disabled APICs right */
2440 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
a92e2543
RK		 2441
2442 r = kvm_apic_state_fixup(vcpu, s, true);
2443 if (r)
2444 return r;
0e96f31e 2445 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
a92e2543
RK		 2446
2447 recalculate_apic_map(vcpu->kvm);
fc61b800
GN		 2448 kvm_apic_set_version(vcpu);
2449
96ad2cc6 2450 apic_update_ppr(apic);
d3c7b77d 2451 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 2452 apic_update_lvtt(apic);
dfb95954 2453 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 2454 update_divide_count(apic);
2455 start_apic_timer(apic);
6e24a6ef 2456 apic->irr_pending = true;
d62caabb 2457 apic->isr_count = vcpu->arch.apicv_active ?
c7c9c56c 2458 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 2459 apic->highest_isr_cache = -1;
d62caabb 2460 if (vcpu->arch.apicv_active) {
967235d3 2461 kvm_x86_ops->apicv_post_state_restore(vcpu);
4114c27d
WW		 2462 kvm_x86_ops->hwapic_irr_update(vcpu,
2463 apic_find_highest_irr(apic));
67c9dddc 2464 kvm_x86_ops->hwapic_isr_update(vcpu,
b4eef9b3 2465 apic_find_highest_isr(apic));
d62caabb 2466 }
3842d135 2467 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 2468 if (ioapic_in_kernel(vcpu->kvm))
2469 kvm_rtc_eoi_tracking_restore_one(vcpu);
0669a510
RK		 2470
2471 vcpu->arch.apic_arb_prio = 0;
a92e2543
RK		 2472
2473 return 0;
96ad2cc6 2474}
a3d7f85f 2475
2f52d58c 2476void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 2477{
a3d7f85f
ED		 2478 struct hrtimer *timer;
2479
0c5f81da
WL		 2480 if (!lapic_in_kernel(vcpu) ||
2481 kvm_can_post_timer_interrupt(vcpu))
a3d7f85f
ED		 2482 return;
2483
54e9818f 2484 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 2485 if (hrtimer_cancel(timer))
2c0d278f 2486 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
a3d7f85f 2487}
b93463aa 2488
ae7a2a3f
MT		 2489/*
2490 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2491 *
2492 * Detect whether guest triggered PV EOI since the
2493 * last entry. If yes, set EOI on guests's behalf.
2494 * Clear PV EOI in guest memory in any case.
2495 */
2496static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2497 struct kvm_lapic *apic)
2498{
2499 bool pending;
2500 int vector;
2501 /*
2502 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2503 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2504 *
2505 * KVM_APIC_PV_EOI_PENDING is unset:
2506 * -> host disabled PV EOI.
2507 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2508 * -> host enabled PV EOI, guest did not execute EOI yet.
2509 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2510 * -> host enabled PV EOI, guest executed EOI.
2511 */
2512 BUG_ON(!pv_eoi_enabled(vcpu));
2513 pending = pv_eoi_get_pending(vcpu);
2514 /*
2515 * Clear pending bit in any case: it will be set again on vmentry.
2516 * While this might not be ideal from performance point of view,
2517 * this makes sure pv eoi is only enabled when we know it's safe.
2518 */
2519 pv_eoi_clr_pending(vcpu);
2520 if (pending)
2521 return;
2522 vector = apic_set_eoi(apic);
2523 trace_kvm_pv_eoi(apic, vector);
2524}
2525
b93463aa
AK		 2526void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2527{
2528 u32 data;
b93463aa 2529
ae7a2a3f
MT		 2530 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2531 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2532
41383771 2533 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2534 return;
2535
4e335d9e
PB		 2536 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2537 sizeof(u32)))
603242a8 2538 return;
b93463aa
AK		 2539
2540 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2541}
2542
ae7a2a3f
MT		 2543/*
2544 * apic_sync_pv_eoi_to_guest - called before vmentry
2545 *
2546 * Detect whether it's safe to enable PV EOI and
2547 * if yes do so.
2548 */
2549static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2550 struct kvm_lapic *apic)
2551{
2552 if (!pv_eoi_enabled(vcpu) ||
2553 /* IRR set or many bits in ISR: could be nested. */
2554 apic->irr_pending ||
2555 /* Cache not set: could be safe but we don't bother. */
2556 apic->highest_isr_cache == -1 ||
2557 /* Need EOI to update ioapic. */
3bb345f3 2558 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 2559 /*
2560 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2561 * so we need not do anything here.
2562 */
2563 return;
2564 }
2565
2566 pv_eoi_set_pending(apic->vcpu);
2567}
2568
b93463aa
AK		 2569void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2570{
2571 u32 data, tpr;
2572 int max_irr, max_isr;
ae7a2a3f 2573 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 2574
ae7a2a3f
MT		 2575 apic_sync_pv_eoi_to_guest(vcpu, apic);
2576
41383771 2577 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2578 return;
2579
dfb95954 2580 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 2581 max_irr = apic_find_highest_irr(apic);
2582 if (max_irr < 0)
2583 max_irr = 0;
2584 max_isr = apic_find_highest_isr(apic);
2585 if (max_isr < 0)
2586 max_isr = 0;
2587 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2588
4e335d9e
PB		 2589 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2590 sizeof(u32));
b93463aa
AK		 2591}
2592
fda4e2e8 2593int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 2594{
fda4e2e8 2595 if (vapic_addr) {
4e335d9e 2596 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
fda4e2e8
AH		 2597 &vcpu->arch.apic->vapic_cache,
2598 vapic_addr, sizeof(u32)))
2599 return -EINVAL;
41383771 2600 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 2601 } else {
41383771 2602 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 2603 }
2604
2605 vcpu->arch.apic->vapic_addr = vapic_addr;
2606 return 0;
b93463aa 2607}
0105d1a5
GN		 2608
2609int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2610{
2611 struct kvm_lapic *apic = vcpu->arch.apic;
2612 u32 reg = (msr - APIC_BASE_MSR) << 4;
2613
35754c98 2614 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2615 return 1;
2616
c69d3d9b
NA		 2617 if (reg == APIC_ICR2)
2618 return 1;
2619
0105d1a5 2620 /* if this is ICR write vector before command */
decdc283 2621 if (reg == APIC_ICR)
1e6e2755
SS		 2622 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2623 return kvm_lapic_reg_write(apic, reg, (u32)data);
0105d1a5
GN		 2624}
2625
2626int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2627{
2628 struct kvm_lapic *apic = vcpu->arch.apic;
2629 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2630
35754c98 2631 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2632 return 1;
2633
0d88800d 2634 if (reg == APIC_DFR || reg == APIC_ICR2)
c69d3d9b 2635 return 1;
c69d3d9b 2636
1e6e2755 2637 if (kvm_lapic_reg_read(apic, reg, 4, &low))
0105d1a5 2638 return 1;
decdc283 2639 if (reg == APIC_ICR)
1e6e2755 2640 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
0105d1a5
GN		 2641
2642 *data = (((u64)high) << 32) | low;
2643
2644 return 0;
2645}
10388a07
GN		 2646
2647int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2648{
2649 struct kvm_lapic *apic = vcpu->arch.apic;
2650
bce87cce 2651 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2652 return 1;
2653
2654 /* if this is ICR write vector before command */
2655 if (reg == APIC_ICR)
1e6e2755
SS		 2656 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2657 return kvm_lapic_reg_write(apic, reg, (u32)data);
10388a07
GN		 2658}
2659
2660int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2661{
2662 struct kvm_lapic *apic = vcpu->arch.apic;
2663 u32 low, high = 0;
2664
bce87cce 2665 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2666 return 1;
2667
1e6e2755 2668 if (kvm_lapic_reg_read(apic, reg, 4, &low))
10388a07
GN		 2669 return 1;
2670 if (reg == APIC_ICR)
1e6e2755 2671 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
10388a07
GN		 2672
2673 *data = (((u64)high) << 32) | low;
2674
2675 return 0;
2676}
ae7a2a3f 2677
72bbf935 2678int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
ae7a2a3f
MT		 2679{
2680 u64 addr = data & ~KVM_MSR_ENABLED;
a7c42bb6
VK		 2681 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2682 unsigned long new_len;
2683
ae7a2a3f
MT		 2684 if (!IS_ALIGNED(addr, 4))
2685 return 1;
2686
2687 vcpu->arch.pv_eoi.msr_val = data;
2688 if (!pv_eoi_enabled(vcpu))
2689 return 0;
a7c42bb6
VK		 2690
2691 if (addr == ghc->gpa && len <= ghc->len)
2692 new_len = ghc->len;
2693 else
2694 new_len = len;
2695
2696 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
ae7a2a3f 2697}
c5cc421b 2698
66450a21
JK		 2699void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2700{
2701 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2702 u8 sipi_vector;
299018f4 2703 unsigned long pe;
66450a21 2704
bce87cce 2705 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
66450a21
JK		 2706 return;
2707
cd7764fe 2708 /*
4b9852f4
LA		 2709 * INITs are latched while CPU is in specific states
2710 * (SMM, VMX non-root mode, SVM with GIF=0).
2711 * Because a CPU cannot be in these states immediately
2712 * after it has processed an INIT signal (and thus in
2713 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2714 * and leave the INIT pending.
cd7764fe 2715 */
4b9852f4 2716 if (is_smm(vcpu) || kvm_x86_ops->apic_init_signal_blocked(vcpu)) {
cd7764fe
PB		 2717 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2718 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2719 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2720 return;
2721 }
299018f4 2722
cd7764fe 2723 pe = xchg(&apic->pending_events, 0);
299018f4 2724 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd 2725 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2726 if (kvm_vcpu_is_bsp(apic->vcpu))
2727 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2728 else
2729 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2730 }
299018f4 2731 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2732 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2733 /* evaluate pending_events before reading the vector */
2734 smp_rmb();
2735 sipi_vector = apic->sipi_vector;
66450a21
JK		 2736 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2737 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2738 }
2739}
2740
c5cc421b
GN		 2741void kvm_lapic_init(void)
2742{
2743 /* do not patch jump label more than once per second */
2744 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2745 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2746}
cef84c30
DM		 2747
2748void kvm_lapic_exit(void)
2749{
2750 static_key_deferred_flush(&apic_hw_disabled);
2751 static_key_deferred_flush(&apic_sw_disabled);
2752}
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