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Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
60063497 | 36 | #include <linux/atomic.h> |
c5cc421b | 37 | #include <linux/jump_label.h> |
5fdbf976 | 38 | #include "kvm_cache_regs.h" |
97222cc8 | 39 | #include "irq.h" |
229456fc | 40 | #include "trace.h" |
fc61b800 | 41 | #include "x86.h" |
00b27a3e | 42 | #include "cpuid.h" |
97222cc8 | 43 | |
b682b814 MT |
44 | #ifndef CONFIG_X86_64 |
45 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
46 | #else | |
47 | #define mod_64(x, y) ((x) % (y)) | |
48 | #endif | |
49 | ||
97222cc8 ED |
50 | #define PRId64 "d" |
51 | #define PRIx64 "llx" | |
52 | #define PRIu64 "u" | |
53 | #define PRIo64 "o" | |
54 | ||
55 | #define APIC_BUS_CYCLE_NS 1 | |
56 | ||
57 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
58 | #define apic_debug(fmt, arg...) | |
59 | ||
60 | #define APIC_LVT_NUM 6 | |
61 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
62 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
63 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
64 | /* followed define is not in apicdef.h */ | |
65 | #define APIC_SHORT_MASK 0xc0000 | |
66 | #define APIC_DEST_NOSHORT 0x0 | |
67 | #define APIC_DEST_MASK 0x800 | |
68 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 69 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 ED |
70 | |
71 | #define VEC_POS(v) ((v) & (32 - 1)) | |
72 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 73 | |
9bc5791d JK |
74 | static unsigned int min_timer_period_us = 500; |
75 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
76 | ||
97222cc8 ED |
77 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
78 | { | |
79 | *((u32 *) (apic->regs + reg_off)) = val; | |
80 | } | |
81 | ||
82 | static inline int apic_test_and_set_vector(int vec, void *bitmap) | |
83 | { | |
84 | return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
85 | } | |
86 | ||
87 | static inline int apic_test_and_clear_vector(int vec, void *bitmap) | |
88 | { | |
89 | return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
90 | } | |
91 | ||
a0c9a822 MT |
92 | static inline int apic_test_vector(int vec, void *bitmap) |
93 | { | |
94 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
95 | } | |
96 | ||
10606919 YZ |
97 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
98 | { | |
99 | struct kvm_lapic *apic = vcpu->arch.apic; | |
100 | ||
101 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
102 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
103 | } | |
104 | ||
97222cc8 ED |
105 | static inline void apic_set_vector(int vec, void *bitmap) |
106 | { | |
107 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
108 | } | |
109 | ||
110 | static inline void apic_clear_vector(int vec, void *bitmap) | |
111 | { | |
112 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
113 | } | |
114 | ||
8680b94b MT |
115 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
116 | { | |
117 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
118 | } | |
119 | ||
120 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
121 | { | |
122 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
123 | } | |
124 | ||
c5cc421b | 125 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
126 | struct static_key_deferred apic_sw_disabled __read_mostly; |
127 | ||
128 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) | |
129 | { | |
c48f1496 | 130 | if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) { |
f8c1ea10 GN |
131 | if (val & APIC_SPIV_APIC_ENABLED) |
132 | static_key_slow_dec_deferred(&apic_sw_disabled); | |
133 | else | |
134 | static_key_slow_inc(&apic_sw_disabled.key); | |
135 | } | |
136 | apic_set_reg(apic, APIC_SPIV, val); | |
137 | } | |
138 | ||
97222cc8 ED |
139 | static inline int apic_enabled(struct kvm_lapic *apic) |
140 | { | |
c48f1496 | 141 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
142 | } |
143 | ||
97222cc8 ED |
144 | #define LVT_MASK \ |
145 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
146 | ||
147 | #define LINT_MASK \ | |
148 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
149 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
150 | ||
151 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
152 | { | |
c48f1496 | 153 | return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; |
97222cc8 ED |
154 | } |
155 | ||
1e08ec4a GN |
156 | static void recalculate_apic_map(struct kvm *kvm) |
157 | { | |
158 | struct kvm_apic_map *new, *old = NULL; | |
159 | struct kvm_vcpu *vcpu; | |
160 | int i; | |
161 | ||
162 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
163 | ||
164 | mutex_lock(&kvm->arch.apic_map_lock); | |
165 | ||
166 | if (!new) | |
167 | goto out; | |
168 | ||
169 | new->ldr_bits = 8; | |
170 | /* flat mode is default */ | |
171 | new->cid_shift = 8; | |
172 | new->cid_mask = 0; | |
173 | new->lid_mask = 0xff; | |
174 | ||
175 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
176 | struct kvm_lapic *apic = vcpu->arch.apic; | |
177 | u16 cid, lid; | |
178 | u32 ldr; | |
179 | ||
180 | if (!kvm_apic_present(vcpu)) | |
181 | continue; | |
182 | ||
183 | /* | |
184 | * All APICs have to be configured in the same mode by an OS. | |
185 | * We take advatage of this while building logical id loockup | |
186 | * table. After reset APICs are in xapic/flat mode, so if we | |
187 | * find apic with different setting we assume this is the mode | |
188 | * OS wants all apics to be in; build lookup table accordingly. | |
189 | */ | |
190 | if (apic_x2apic_mode(apic)) { | |
191 | new->ldr_bits = 32; | |
192 | new->cid_shift = 16; | |
193 | new->cid_mask = new->lid_mask = 0xffff; | |
194 | } else if (kvm_apic_sw_enabled(apic) && | |
195 | !new->cid_mask /* flat mode */ && | |
196 | kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) { | |
197 | new->cid_shift = 4; | |
198 | new->cid_mask = 0xf; | |
199 | new->lid_mask = 0xf; | |
200 | } | |
201 | ||
202 | new->phys_map[kvm_apic_id(apic)] = apic; | |
203 | ||
204 | ldr = kvm_apic_get_reg(apic, APIC_LDR); | |
205 | cid = apic_cluster_id(new, ldr); | |
206 | lid = apic_logical_id(new, ldr); | |
207 | ||
208 | if (lid) | |
209 | new->logical_map[cid][ffs(lid) - 1] = apic; | |
210 | } | |
211 | out: | |
212 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
213 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
214 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
215 | mutex_unlock(&kvm->arch.apic_map_lock); | |
216 | ||
217 | if (old) | |
218 | kfree_rcu(old, rcu); | |
c7c9c56c | 219 | |
3d81bc7e | 220 | kvm_vcpu_request_scan_ioapic(kvm); |
1e08ec4a GN |
221 | } |
222 | ||
223 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) | |
224 | { | |
225 | apic_set_reg(apic, APIC_ID, id << 24); | |
226 | recalculate_apic_map(apic->vcpu->kvm); | |
227 | } | |
228 | ||
229 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
230 | { | |
231 | apic_set_reg(apic, APIC_LDR, id); | |
232 | recalculate_apic_map(apic->vcpu->kvm); | |
233 | } | |
234 | ||
97222cc8 ED |
235 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
236 | { | |
c48f1496 | 237 | return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
238 | } |
239 | ||
240 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
241 | { | |
c48f1496 | 242 | return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
243 | } |
244 | ||
a3e06bbe LJ |
245 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
246 | { | |
c48f1496 | 247 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
248 | apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT); |
249 | } | |
250 | ||
97222cc8 ED |
251 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
252 | { | |
c48f1496 | 253 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
254 | apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC); |
255 | } | |
256 | ||
257 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
258 | { | |
c48f1496 | 259 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
260 | apic->lapic_timer.timer_mode_mask) == |
261 | APIC_LVT_TIMER_TSCDEADLINE); | |
97222cc8 ED |
262 | } |
263 | ||
cc6e462c JK |
264 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
265 | { | |
266 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
267 | } | |
268 | ||
fc61b800 GN |
269 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
270 | { | |
271 | struct kvm_lapic *apic = vcpu->arch.apic; | |
272 | struct kvm_cpuid_entry2 *feat; | |
273 | u32 v = APIC_VERSION; | |
274 | ||
c48f1496 | 275 | if (!kvm_vcpu_has_lapic(vcpu)) |
fc61b800 GN |
276 | return; |
277 | ||
278 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
279 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
280 | v |= APIC_LVR_DIRECTED_EOI; | |
281 | apic_set_reg(apic, APIC_LVR, v); | |
282 | } | |
283 | ||
f1d24831 | 284 | static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
a3e06bbe | 285 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
286 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
287 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
288 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
289 | LVT_MASK /* LVTERR */ | |
290 | }; | |
291 | ||
292 | static int find_highest_vector(void *bitmap) | |
293 | { | |
ecba9a52 TY |
294 | int vec; |
295 | u32 *reg; | |
97222cc8 | 296 | |
ecba9a52 TY |
297 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
298 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
299 | reg = bitmap + REG_POS(vec); | |
300 | if (*reg) | |
301 | return fls(*reg) - 1 + vec; | |
302 | } | |
97222cc8 | 303 | |
ecba9a52 | 304 | return -1; |
97222cc8 ED |
305 | } |
306 | ||
8680b94b MT |
307 | static u8 count_vectors(void *bitmap) |
308 | { | |
ecba9a52 TY |
309 | int vec; |
310 | u32 *reg; | |
8680b94b | 311 | u8 count = 0; |
ecba9a52 TY |
312 | |
313 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
314 | reg = bitmap + REG_POS(vec); | |
315 | count += hweight32(*reg); | |
316 | } | |
317 | ||
8680b94b MT |
318 | return count; |
319 | } | |
320 | ||
97222cc8 ED |
321 | static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) |
322 | { | |
33e4c686 | 323 | apic->irr_pending = true; |
97222cc8 ED |
324 | return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); |
325 | } | |
326 | ||
33e4c686 | 327 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 328 | { |
33e4c686 | 329 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
330 | } |
331 | ||
332 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
333 | { | |
334 | int result; | |
335 | ||
c7c9c56c YZ |
336 | /* |
337 | * Note that irr_pending is just a hint. It will be always | |
338 | * true with virtual interrupt delivery enabled. | |
339 | */ | |
33e4c686 GN |
340 | if (!apic->irr_pending) |
341 | return -1; | |
342 | ||
343 | result = apic_search_irr(apic); | |
97222cc8 ED |
344 | ASSERT(result == -1 || result >= 16); |
345 | ||
346 | return result; | |
347 | } | |
348 | ||
33e4c686 GN |
349 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
350 | { | |
351 | apic->irr_pending = false; | |
352 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
353 | if (apic_search_irr(apic) != -1) | |
354 | apic->irr_pending = true; | |
355 | } | |
356 | ||
8680b94b MT |
357 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
358 | { | |
359 | if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
360 | ++apic->isr_count; | |
361 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
362 | /* | |
363 | * ISR (in service register) bit is set when injecting an interrupt. | |
364 | * The highest vector is injected. Thus the latest bit set matches | |
365 | * the highest bit in ISR. | |
366 | */ | |
367 | apic->highest_isr_cache = vec; | |
368 | } | |
369 | ||
370 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) | |
371 | { | |
372 | if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
373 | --apic->isr_count; | |
374 | BUG_ON(apic->isr_count < 0); | |
375 | apic->highest_isr_cache = -1; | |
376 | } | |
377 | ||
6e5d865c YS |
378 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
379 | { | |
6e5d865c YS |
380 | int highest_irr; |
381 | ||
33e4c686 GN |
382 | /* This may race with setting of irr in __apic_accept_irq() and |
383 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
384 | * will cause vmexit immediately and the value will be recalculated | |
385 | * on the next vmentry. | |
386 | */ | |
c48f1496 | 387 | if (!kvm_vcpu_has_lapic(vcpu)) |
6e5d865c | 388 | return 0; |
54e9818f | 389 | highest_irr = apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c YS |
390 | |
391 | return highest_irr; | |
392 | } | |
6e5d865c | 393 | |
6da7e3f6 | 394 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c YZ |
395 | int vector, int level, int trig_mode, |
396 | unsigned long *dest_map); | |
6da7e3f6 | 397 | |
b4f2225c YZ |
398 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
399 | unsigned long *dest_map) | |
97222cc8 | 400 | { |
ad312c7c | 401 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 402 | |
58c2dde1 | 403 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 404 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
405 | } |
406 | ||
ae7a2a3f MT |
407 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
408 | { | |
409 | ||
410 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
411 | sizeof(val)); | |
412 | } | |
413 | ||
414 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
415 | { | |
416 | ||
417 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
418 | sizeof(*val)); | |
419 | } | |
420 | ||
421 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
422 | { | |
423 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
424 | } | |
425 | ||
426 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
427 | { | |
428 | u8 val; | |
429 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
430 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
431 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
432 | return val & 0x1; | |
433 | } | |
434 | ||
435 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
436 | { | |
437 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
438 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
439 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
440 | return; | |
441 | } | |
442 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
443 | } | |
444 | ||
445 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
446 | { | |
447 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
448 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
449 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
450 | return; | |
451 | } | |
452 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
453 | } | |
454 | ||
97222cc8 ED |
455 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
456 | { | |
457 | int result; | |
c7c9c56c YZ |
458 | |
459 | /* Note that isr_count is always 1 with vid enabled */ | |
8680b94b MT |
460 | if (!apic->isr_count) |
461 | return -1; | |
462 | if (likely(apic->highest_isr_cache != -1)) | |
463 | return apic->highest_isr_cache; | |
97222cc8 ED |
464 | |
465 | result = find_highest_vector(apic->regs + APIC_ISR); | |
466 | ASSERT(result == -1 || result >= 16); | |
467 | ||
468 | return result; | |
469 | } | |
470 | ||
cf9e65b7 YZ |
471 | void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr) |
472 | { | |
473 | struct kvm_lapic *apic = vcpu->arch.apic; | |
474 | int i; | |
475 | ||
476 | for (i = 0; i < 8; i++) | |
477 | apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]); | |
478 | } | |
479 | ||
97222cc8 ED |
480 | static void apic_update_ppr(struct kvm_lapic *apic) |
481 | { | |
3842d135 | 482 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
483 | int isr; |
484 | ||
c48f1496 GN |
485 | old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); |
486 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
487 | isr = apic_find_highest_isr(apic); |
488 | isrv = (isr != -1) ? isr : 0; | |
489 | ||
490 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
491 | ppr = tpr & 0xff; | |
492 | else | |
493 | ppr = isrv & 0xf0; | |
494 | ||
495 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
496 | apic, ppr, isr, isrv); | |
497 | ||
3842d135 AK |
498 | if (old_ppr != ppr) { |
499 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
83bcacb1 AK |
500 | if (ppr < old_ppr) |
501 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 502 | } |
97222cc8 ED |
503 | } |
504 | ||
505 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
506 | { | |
507 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
508 | apic_update_ppr(apic); | |
509 | } | |
510 | ||
511 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) | |
512 | { | |
343f94fe | 513 | return dest == 0xff || kvm_apic_id(apic) == dest; |
97222cc8 ED |
514 | } |
515 | ||
516 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) | |
517 | { | |
518 | int result = 0; | |
0105d1a5 GN |
519 | u32 logical_id; |
520 | ||
521 | if (apic_x2apic_mode(apic)) { | |
c48f1496 | 522 | logical_id = kvm_apic_get_reg(apic, APIC_LDR); |
0105d1a5 GN |
523 | return logical_id & mda; |
524 | } | |
97222cc8 | 525 | |
c48f1496 | 526 | logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR)); |
97222cc8 | 527 | |
c48f1496 | 528 | switch (kvm_apic_get_reg(apic, APIC_DFR)) { |
97222cc8 ED |
529 | case APIC_DFR_FLAT: |
530 | if (logical_id & mda) | |
531 | result = 1; | |
532 | break; | |
533 | case APIC_DFR_CLUSTER: | |
534 | if (((logical_id >> 4) == (mda >> 0x4)) | |
535 | && (logical_id & mda & 0xf)) | |
536 | result = 1; | |
537 | break; | |
538 | default: | |
7712de87 | 539 | apic_debug("Bad DFR vcpu %d: %08x\n", |
c48f1496 | 540 | apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); |
97222cc8 ED |
541 | break; |
542 | } | |
543 | ||
544 | return result; | |
545 | } | |
546 | ||
343f94fe | 547 | int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
97222cc8 ED |
548 | int short_hand, int dest, int dest_mode) |
549 | { | |
550 | int result = 0; | |
ad312c7c | 551 | struct kvm_lapic *target = vcpu->arch.apic; |
97222cc8 ED |
552 | |
553 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 554 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
555 | target, source, dest, dest_mode, short_hand); |
556 | ||
bd371396 | 557 | ASSERT(target); |
97222cc8 ED |
558 | switch (short_hand) { |
559 | case APIC_DEST_NOSHORT: | |
343f94fe | 560 | if (dest_mode == 0) |
97222cc8 | 561 | /* Physical mode. */ |
343f94fe GN |
562 | result = kvm_apic_match_physical_addr(target, dest); |
563 | else | |
97222cc8 ED |
564 | /* Logical mode. */ |
565 | result = kvm_apic_match_logical_addr(target, dest); | |
566 | break; | |
567 | case APIC_DEST_SELF: | |
343f94fe | 568 | result = (target == source); |
97222cc8 ED |
569 | break; |
570 | case APIC_DEST_ALLINC: | |
571 | result = 1; | |
572 | break; | |
573 | case APIC_DEST_ALLBUT: | |
343f94fe | 574 | result = (target != source); |
97222cc8 ED |
575 | break; |
576 | default: | |
7712de87 JK |
577 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
578 | short_hand); | |
97222cc8 ED |
579 | break; |
580 | } | |
581 | ||
582 | return result; | |
583 | } | |
584 | ||
1e08ec4a | 585 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 586 | struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) |
1e08ec4a GN |
587 | { |
588 | struct kvm_apic_map *map; | |
589 | unsigned long bitmap = 1; | |
590 | struct kvm_lapic **dst; | |
591 | int i; | |
592 | bool ret = false; | |
593 | ||
594 | *r = -1; | |
595 | ||
596 | if (irq->shorthand == APIC_DEST_SELF) { | |
b4f2225c | 597 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); |
1e08ec4a GN |
598 | return true; |
599 | } | |
600 | ||
601 | if (irq->shorthand) | |
602 | return false; | |
603 | ||
604 | rcu_read_lock(); | |
605 | map = rcu_dereference(kvm->arch.apic_map); | |
606 | ||
607 | if (!map) | |
608 | goto out; | |
609 | ||
610 | if (irq->dest_mode == 0) { /* physical mode */ | |
611 | if (irq->delivery_mode == APIC_DM_LOWEST || | |
612 | irq->dest_id == 0xff) | |
613 | goto out; | |
614 | dst = &map->phys_map[irq->dest_id & 0xff]; | |
615 | } else { | |
616 | u32 mda = irq->dest_id << (32 - map->ldr_bits); | |
617 | ||
618 | dst = map->logical_map[apic_cluster_id(map, mda)]; | |
619 | ||
620 | bitmap = apic_logical_id(map, mda); | |
621 | ||
622 | if (irq->delivery_mode == APIC_DM_LOWEST) { | |
623 | int l = -1; | |
624 | for_each_set_bit(i, &bitmap, 16) { | |
625 | if (!dst[i]) | |
626 | continue; | |
627 | if (l < 0) | |
628 | l = i; | |
629 | else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) | |
630 | l = i; | |
631 | } | |
632 | ||
633 | bitmap = (l >= 0) ? 1 << l : 0; | |
634 | } | |
635 | } | |
636 | ||
637 | for_each_set_bit(i, &bitmap, 16) { | |
638 | if (!dst[i]) | |
639 | continue; | |
640 | if (*r < 0) | |
641 | *r = 0; | |
b4f2225c | 642 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a GN |
643 | } |
644 | ||
645 | ret = true; | |
646 | out: | |
647 | rcu_read_unlock(); | |
648 | return ret; | |
649 | } | |
650 | ||
97222cc8 ED |
651 | /* |
652 | * Add a pending IRQ into lapic. | |
653 | * Return 1 if successfully added and 0 if discarded. | |
654 | */ | |
655 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c YZ |
656 | int vector, int level, int trig_mode, |
657 | unsigned long *dest_map) | |
97222cc8 | 658 | { |
6da7e3f6 | 659 | int result = 0; |
c5ec1534 | 660 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 ED |
661 | |
662 | switch (delivery_mode) { | |
97222cc8 | 663 | case APIC_DM_LOWEST: |
e1035715 GN |
664 | vcpu->arch.apic_arb_prio++; |
665 | case APIC_DM_FIXED: | |
97222cc8 ED |
666 | /* FIXME add logic for vcpu on reset */ |
667 | if (unlikely(!apic_enabled(apic))) | |
668 | break; | |
669 | ||
b4f2225c YZ |
670 | if (dest_map) |
671 | __set_bit(vcpu->vcpu_id, dest_map); | |
672 | ||
6da7e3f6 | 673 | result = !apic_test_and_set_irr(vector, apic); |
1000ff8d | 674 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
4da74896 | 675 | trig_mode, vector, !result); |
6da7e3f6 GN |
676 | if (!result) { |
677 | if (trig_mode) | |
678 | apic_debug("level trig mode repeatedly for " | |
679 | "vector %d", vector); | |
97222cc8 ED |
680 | break; |
681 | } | |
682 | ||
3842d135 | 683 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
d7690175 | 684 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
685 | break; |
686 | ||
687 | case APIC_DM_REMRD: | |
7712de87 | 688 | apic_debug("Ignoring delivery mode 3\n"); |
97222cc8 ED |
689 | break; |
690 | ||
691 | case APIC_DM_SMI: | |
7712de87 | 692 | apic_debug("Ignoring guest SMI\n"); |
97222cc8 | 693 | break; |
3419ffc8 | 694 | |
97222cc8 | 695 | case APIC_DM_NMI: |
6da7e3f6 | 696 | result = 1; |
3419ffc8 | 697 | kvm_inject_nmi(vcpu); |
26df99c6 | 698 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
699 | break; |
700 | ||
701 | case APIC_DM_INIT: | |
a52315e1 | 702 | if (!trig_mode || level) { |
6da7e3f6 | 703 | result = 1; |
66450a21 JK |
704 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
705 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
706 | /* make sure pending_events is visible before sending | |
707 | * the request */ | |
708 | smp_wmb(); | |
3842d135 | 709 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
710 | kvm_vcpu_kick(vcpu); |
711 | } else { | |
1b10bf31 JK |
712 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
713 | vcpu->vcpu_id); | |
c5ec1534 | 714 | } |
97222cc8 ED |
715 | break; |
716 | ||
717 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
718 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
719 | vcpu->vcpu_id, vector); | |
66450a21 JK |
720 | result = 1; |
721 | apic->sipi_vector = vector; | |
722 | /* make sure sipi_vector is visible for the receiver */ | |
723 | smp_wmb(); | |
724 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
725 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
726 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
727 | break; |
728 | ||
23930f95 JK |
729 | case APIC_DM_EXTINT: |
730 | /* | |
731 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
732 | * before NMI watchdog was enabled. Already handled by | |
733 | * kvm_apic_accept_pic_intr(). | |
734 | */ | |
735 | break; | |
736 | ||
97222cc8 ED |
737 | default: |
738 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
739 | delivery_mode); | |
740 | break; | |
741 | } | |
742 | return result; | |
743 | } | |
744 | ||
e1035715 | 745 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 746 | { |
e1035715 | 747 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
748 | } |
749 | ||
c7c9c56c YZ |
750 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
751 | { | |
752 | if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && | |
753 | kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { | |
754 | int trigger_mode; | |
755 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
756 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
757 | else | |
758 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1fcc7890 | 759 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); |
c7c9c56c YZ |
760 | } |
761 | } | |
762 | ||
ae7a2a3f | 763 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
764 | { |
765 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
766 | |
767 | trace_kvm_eoi(apic, vector); | |
768 | ||
97222cc8 ED |
769 | /* |
770 | * Not every write EOI will has corresponding ISR, | |
771 | * one example is when Kernel check timer on setup_IO_APIC | |
772 | */ | |
773 | if (vector == -1) | |
ae7a2a3f | 774 | return vector; |
97222cc8 | 775 | |
8680b94b | 776 | apic_clear_isr(vector, apic); |
97222cc8 ED |
777 | apic_update_ppr(apic); |
778 | ||
c7c9c56c | 779 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 780 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 781 | return vector; |
97222cc8 ED |
782 | } |
783 | ||
c7c9c56c YZ |
784 | /* |
785 | * this interface assumes a trap-like exit, which has already finished | |
786 | * desired side effect including vISR and vPPR update. | |
787 | */ | |
788 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
789 | { | |
790 | struct kvm_lapic *apic = vcpu->arch.apic; | |
791 | ||
792 | trace_kvm_eoi(apic, vector); | |
793 | ||
794 | kvm_ioapic_send_eoi(apic, vector); | |
795 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
796 | } | |
797 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
798 | ||
97222cc8 ED |
799 | static void apic_send_ipi(struct kvm_lapic *apic) |
800 | { | |
c48f1496 GN |
801 | u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); |
802 | u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 803 | struct kvm_lapic_irq irq; |
97222cc8 | 804 | |
58c2dde1 GN |
805 | irq.vector = icr_low & APIC_VECTOR_MASK; |
806 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
807 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
808 | irq.level = icr_low & APIC_INT_ASSERT; | |
809 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; | |
810 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
0105d1a5 GN |
811 | if (apic_x2apic_mode(apic)) |
812 | irq.dest_id = icr_high; | |
813 | else | |
814 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 815 | |
1000ff8d GN |
816 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
817 | ||
97222cc8 ED |
818 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
819 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
820 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", | |
9b5843dd | 821 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 GN |
822 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
823 | irq.vector); | |
824 | ||
b4f2225c | 825 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
826 | } |
827 | ||
828 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
829 | { | |
b682b814 MT |
830 | ktime_t remaining; |
831 | s64 ns; | |
9da8f4e8 | 832 | u32 tmcct; |
97222cc8 ED |
833 | |
834 | ASSERT(apic != NULL); | |
835 | ||
9da8f4e8 | 836 | /* if initial count is 0, current count should also be 0 */ |
c48f1496 | 837 | if (kvm_apic_get_reg(apic, APIC_TMICT) == 0) |
9da8f4e8 KP |
838 | return 0; |
839 | ||
ace15464 | 840 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
841 | if (ktime_to_ns(remaining) < 0) |
842 | remaining = ktime_set(0, 0); | |
843 | ||
d3c7b77d MT |
844 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
845 | tmcct = div64_u64(ns, | |
846 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
847 | |
848 | return tmcct; | |
849 | } | |
850 | ||
b209749f AK |
851 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
852 | { | |
853 | struct kvm_vcpu *vcpu = apic->vcpu; | |
854 | struct kvm_run *run = vcpu->run; | |
855 | ||
a8eeb04a | 856 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 857 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
858 | run->tpr_access.is_write = write; |
859 | } | |
860 | ||
861 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
862 | { | |
863 | if (apic->vcpu->arch.tpr_access_reporting) | |
864 | __report_tpr_access(apic, write); | |
865 | } | |
866 | ||
97222cc8 ED |
867 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
868 | { | |
869 | u32 val = 0; | |
870 | ||
871 | if (offset >= LAPIC_MMIO_LENGTH) | |
872 | return 0; | |
873 | ||
874 | switch (offset) { | |
0105d1a5 GN |
875 | case APIC_ID: |
876 | if (apic_x2apic_mode(apic)) | |
877 | val = kvm_apic_id(apic); | |
878 | else | |
879 | val = kvm_apic_id(apic) << 24; | |
880 | break; | |
97222cc8 | 881 | case APIC_ARBPRI: |
7712de87 | 882 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
883 | break; |
884 | ||
885 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
886 | if (apic_lvtt_tscdeadline(apic)) |
887 | return 0; | |
888 | ||
97222cc8 ED |
889 | val = apic_get_tmcct(apic); |
890 | break; | |
4a4541a4 AK |
891 | case APIC_PROCPRI: |
892 | apic_update_ppr(apic); | |
c48f1496 | 893 | val = kvm_apic_get_reg(apic, offset); |
4a4541a4 | 894 | break; |
b209749f AK |
895 | case APIC_TASKPRI: |
896 | report_tpr_access(apic, false); | |
897 | /* fall thru */ | |
97222cc8 | 898 | default: |
c48f1496 | 899 | val = kvm_apic_get_reg(apic, offset); |
97222cc8 ED |
900 | break; |
901 | } | |
902 | ||
903 | return val; | |
904 | } | |
905 | ||
d76685c4 GH |
906 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
907 | { | |
908 | return container_of(dev, struct kvm_lapic, dev); | |
909 | } | |
910 | ||
0105d1a5 GN |
911 | static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
912 | void *data) | |
97222cc8 | 913 | { |
97222cc8 ED |
914 | unsigned char alignment = offset & 0xf; |
915 | u32 result; | |
d5b0b5b1 | 916 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 917 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
918 | |
919 | if ((alignment + len) > 4) { | |
4088bb3c GN |
920 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
921 | offset, len); | |
0105d1a5 | 922 | return 1; |
97222cc8 | 923 | } |
0105d1a5 GN |
924 | |
925 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
926 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
927 | offset); | |
0105d1a5 GN |
928 | return 1; |
929 | } | |
930 | ||
97222cc8 ED |
931 | result = __apic_read(apic, offset & ~0xf); |
932 | ||
229456fc MT |
933 | trace_kvm_apic_read(offset, result); |
934 | ||
97222cc8 ED |
935 | switch (len) { |
936 | case 1: | |
937 | case 2: | |
938 | case 4: | |
939 | memcpy(data, (char *)&result + alignment, len); | |
940 | break; | |
941 | default: | |
942 | printk(KERN_ERR "Local APIC read with len = %x, " | |
943 | "should be 1,2, or 4 instead\n", len); | |
944 | break; | |
945 | } | |
bda9020e | 946 | return 0; |
97222cc8 ED |
947 | } |
948 | ||
0105d1a5 GN |
949 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
950 | { | |
c48f1496 | 951 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
952 | addr >= apic->base_address && |
953 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
954 | } | |
955 | ||
956 | static int apic_mmio_read(struct kvm_io_device *this, | |
957 | gpa_t address, int len, void *data) | |
958 | { | |
959 | struct kvm_lapic *apic = to_lapic(this); | |
960 | u32 offset = address - apic->base_address; | |
961 | ||
962 | if (!apic_mmio_in_range(apic, address)) | |
963 | return -EOPNOTSUPP; | |
964 | ||
965 | apic_reg_read(apic, offset, len, data); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
97222cc8 ED |
970 | static void update_divide_count(struct kvm_lapic *apic) |
971 | { | |
972 | u32 tmp1, tmp2, tdcr; | |
973 | ||
c48f1496 | 974 | tdcr = kvm_apic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
975 | tmp1 = tdcr & 0xf; |
976 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 977 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
978 | |
979 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 980 | apic->divide_count); |
97222cc8 ED |
981 | } |
982 | ||
983 | static void start_apic_timer(struct kvm_lapic *apic) | |
984 | { | |
a3e06bbe | 985 | ktime_t now; |
d3c7b77d | 986 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 987 | |
a3e06bbe | 988 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 989 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 990 | now = apic->lapic_timer.timer.base->get_time(); |
c48f1496 | 991 | apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
992 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
993 | ||
994 | if (!apic->lapic_timer.period) | |
995 | return; | |
996 | /* | |
997 | * Do not allow the guest to program periodic timers with small | |
998 | * interval, since the hrtimers are not throttled by the host | |
999 | * scheduler. | |
1000 | */ | |
1001 | if (apic_lvtt_period(apic)) { | |
1002 | s64 min_period = min_timer_period_us * 1000LL; | |
1003 | ||
1004 | if (apic->lapic_timer.period < min_period) { | |
1005 | pr_info_ratelimited( | |
1006 | "kvm: vcpu %i: requested %lld ns " | |
1007 | "lapic timer period limited to %lld ns\n", | |
1008 | apic->vcpu->vcpu_id, | |
1009 | apic->lapic_timer.period, min_period); | |
1010 | apic->lapic_timer.period = min_period; | |
1011 | } | |
9bc5791d | 1012 | } |
0b975a3c | 1013 | |
a3e06bbe LJ |
1014 | hrtimer_start(&apic->lapic_timer.timer, |
1015 | ktime_add_ns(now, apic->lapic_timer.period), | |
1016 | HRTIMER_MODE_ABS); | |
97222cc8 | 1017 | |
a3e06bbe | 1018 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1019 | PRIx64 ", " |
1020 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1021 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1022 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
c48f1496 | 1023 | kvm_apic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1024 | apic->lapic_timer.period, |
97222cc8 | 1025 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1026 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1027 | } else if (apic_lvtt_tscdeadline(apic)) { |
1028 | /* lapic timer in tsc deadline mode */ | |
1029 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1030 | u64 ns = 0; | |
1031 | struct kvm_vcpu *vcpu = apic->vcpu; | |
cc578287 | 1032 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1033 | unsigned long flags; |
1034 | ||
1035 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1036 | return; | |
1037 | ||
1038 | local_irq_save(flags); | |
1039 | ||
1040 | now = apic->lapic_timer.timer.base->get_time(); | |
886b470c | 1041 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); |
a3e06bbe LJ |
1042 | if (likely(tscdeadline > guest_tsc)) { |
1043 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1044 | do_div(ns, this_tsc_khz); | |
1045 | } | |
1046 | hrtimer_start(&apic->lapic_timer.timer, | |
1047 | ktime_add_ns(now, ns), HRTIMER_MODE_ABS); | |
1048 | ||
1049 | local_irq_restore(flags); | |
1050 | } | |
97222cc8 ED |
1051 | } |
1052 | ||
cc6e462c JK |
1053 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1054 | { | |
c48f1496 | 1055 | int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0)); |
cc6e462c JK |
1056 | |
1057 | if (apic_lvt_nmi_mode(lvt0_val)) { | |
1058 | if (!nmi_wd_enabled) { | |
1059 | apic_debug("Receive NMI setting on APIC_LVT0 " | |
1060 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
1061 | apic->vcpu->kvm->arch.vapics_in_nmi_mode++; | |
1062 | } | |
1063 | } else if (nmi_wd_enabled) | |
1064 | apic->vcpu->kvm->arch.vapics_in_nmi_mode--; | |
1065 | } | |
1066 | ||
0105d1a5 | 1067 | static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1068 | { |
0105d1a5 | 1069 | int ret = 0; |
97222cc8 | 1070 | |
0105d1a5 | 1071 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1072 | |
0105d1a5 | 1073 | switch (reg) { |
97222cc8 | 1074 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1075 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1076 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1077 | else |
1078 | ret = 1; | |
97222cc8 ED |
1079 | break; |
1080 | ||
1081 | case APIC_TASKPRI: | |
b209749f | 1082 | report_tpr_access(apic, true); |
97222cc8 ED |
1083 | apic_set_tpr(apic, val & 0xff); |
1084 | break; | |
1085 | ||
1086 | case APIC_EOI: | |
1087 | apic_set_eoi(apic); | |
1088 | break; | |
1089 | ||
1090 | case APIC_LDR: | |
0105d1a5 | 1091 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1092 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1093 | else |
1094 | ret = 1; | |
97222cc8 ED |
1095 | break; |
1096 | ||
1097 | case APIC_DFR: | |
1e08ec4a | 1098 | if (!apic_x2apic_mode(apic)) { |
0105d1a5 | 1099 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1100 | recalculate_apic_map(apic->vcpu->kvm); |
1101 | } else | |
0105d1a5 | 1102 | ret = 1; |
97222cc8 ED |
1103 | break; |
1104 | ||
fc61b800 GN |
1105 | case APIC_SPIV: { |
1106 | u32 mask = 0x3ff; | |
c48f1496 | 1107 | if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1108 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1109 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1110 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1111 | int i; | |
1112 | u32 lvt_val; | |
1113 | ||
1114 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
c48f1496 | 1115 | lvt_val = kvm_apic_get_reg(apic, |
97222cc8 ED |
1116 | APIC_LVTT + 0x10 * i); |
1117 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
1118 | lvt_val | APIC_LVT_MASKED); | |
1119 | } | |
d3c7b77d | 1120 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1121 | |
1122 | } | |
1123 | break; | |
fc61b800 | 1124 | } |
97222cc8 ED |
1125 | case APIC_ICR: |
1126 | /* No delay here, so we always clear the pending bit */ | |
1127 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
1128 | apic_send_ipi(apic); | |
1129 | break; | |
1130 | ||
1131 | case APIC_ICR2: | |
0105d1a5 GN |
1132 | if (!apic_x2apic_mode(apic)) |
1133 | val &= 0xff000000; | |
1134 | apic_set_reg(apic, APIC_ICR2, val); | |
97222cc8 ED |
1135 | break; |
1136 | ||
23930f95 | 1137 | case APIC_LVT0: |
cc6e462c | 1138 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1139 | case APIC_LVTTHMR: |
1140 | case APIC_LVTPC: | |
97222cc8 ED |
1141 | case APIC_LVT1: |
1142 | case APIC_LVTERR: | |
1143 | /* TODO: Check vector */ | |
c48f1496 | 1144 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1145 | val |= APIC_LVT_MASKED; |
1146 | ||
0105d1a5 GN |
1147 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1148 | apic_set_reg(apic, reg, val); | |
97222cc8 ED |
1149 | |
1150 | break; | |
1151 | ||
a3e06bbe | 1152 | case APIC_LVTT: |
c48f1496 | 1153 | if ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
1154 | apic->lapic_timer.timer_mode_mask) != |
1155 | (val & apic->lapic_timer.timer_mode_mask)) | |
1156 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1157 | ||
c48f1496 | 1158 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1159 | val |= APIC_LVT_MASKED; |
1160 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1161 | apic_set_reg(apic, APIC_LVTT, val); | |
1162 | break; | |
1163 | ||
97222cc8 | 1164 | case APIC_TMICT: |
a3e06bbe LJ |
1165 | if (apic_lvtt_tscdeadline(apic)) |
1166 | break; | |
1167 | ||
d3c7b77d | 1168 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 ED |
1169 | apic_set_reg(apic, APIC_TMICT, val); |
1170 | start_apic_timer(apic); | |
0105d1a5 | 1171 | break; |
97222cc8 ED |
1172 | |
1173 | case APIC_TDCR: | |
1174 | if (val & 4) | |
7712de87 | 1175 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
97222cc8 ED |
1176 | apic_set_reg(apic, APIC_TDCR, val); |
1177 | update_divide_count(apic); | |
1178 | break; | |
1179 | ||
0105d1a5 GN |
1180 | case APIC_ESR: |
1181 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1182 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1183 | ret = 1; |
1184 | } | |
1185 | break; | |
1186 | ||
1187 | case APIC_SELF_IPI: | |
1188 | if (apic_x2apic_mode(apic)) { | |
1189 | apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); | |
1190 | } else | |
1191 | ret = 1; | |
1192 | break; | |
97222cc8 | 1193 | default: |
0105d1a5 | 1194 | ret = 1; |
97222cc8 ED |
1195 | break; |
1196 | } | |
0105d1a5 GN |
1197 | if (ret) |
1198 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1199 | return ret; | |
1200 | } | |
1201 | ||
1202 | static int apic_mmio_write(struct kvm_io_device *this, | |
1203 | gpa_t address, int len, const void *data) | |
1204 | { | |
1205 | struct kvm_lapic *apic = to_lapic(this); | |
1206 | unsigned int offset = address - apic->base_address; | |
1207 | u32 val; | |
1208 | ||
1209 | if (!apic_mmio_in_range(apic, address)) | |
1210 | return -EOPNOTSUPP; | |
1211 | ||
1212 | /* | |
1213 | * APIC register must be aligned on 128-bits boundary. | |
1214 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1215 | * Refer SDM 8.4.1 | |
1216 | */ | |
1217 | if (len != 4 || (offset & 0xf)) { | |
1218 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1219 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1220 | return 0; |
0105d1a5 GN |
1221 | } |
1222 | ||
1223 | val = *(u32*)data; | |
1224 | ||
1225 | /* too common printing */ | |
1226 | if (offset != APIC_EOI) | |
1227 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1228 | "0x%x\n", __func__, offset, len, val); | |
1229 | ||
1230 | apic_reg_write(apic, offset & 0xff0, val); | |
1231 | ||
bda9020e | 1232 | return 0; |
97222cc8 ED |
1233 | } |
1234 | ||
58fbbf26 KT |
1235 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1236 | { | |
c48f1496 | 1237 | if (kvm_vcpu_has_lapic(vcpu)) |
58fbbf26 KT |
1238 | apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
1239 | } | |
1240 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1241 | ||
83d4c286 YZ |
1242 | /* emulate APIC access in a trap manner */ |
1243 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1244 | { | |
1245 | u32 val = 0; | |
1246 | ||
1247 | /* hw has done the conditional check and inst decode */ | |
1248 | offset &= 0xff0; | |
1249 | ||
1250 | apic_reg_read(vcpu->arch.apic, offset, 4, &val); | |
1251 | ||
1252 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1253 | apic_reg_write(vcpu->arch.apic, offset, val); | |
1254 | } | |
1255 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1256 | ||
d589444e | 1257 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1258 | { |
f8c1ea10 GN |
1259 | struct kvm_lapic *apic = vcpu->arch.apic; |
1260 | ||
ad312c7c | 1261 | if (!vcpu->arch.apic) |
97222cc8 ED |
1262 | return; |
1263 | ||
f8c1ea10 | 1264 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1265 | |
c5cc421b GN |
1266 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1267 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1268 | ||
c48f1496 | 1269 | if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED)) |
f8c1ea10 | 1270 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1271 | |
f8c1ea10 GN |
1272 | if (apic->regs) |
1273 | free_page((unsigned long)apic->regs); | |
1274 | ||
1275 | kfree(apic); | |
97222cc8 ED |
1276 | } |
1277 | ||
1278 | /* | |
1279 | *---------------------------------------------------------------------- | |
1280 | * LAPIC interface | |
1281 | *---------------------------------------------------------------------- | |
1282 | */ | |
1283 | ||
a3e06bbe LJ |
1284 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1285 | { | |
1286 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1287 | |
c48f1496 | 1288 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1289 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1290 | return 0; |
1291 | ||
1292 | return apic->lapic_timer.tscdeadline; | |
1293 | } | |
1294 | ||
1295 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1296 | { | |
1297 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1298 | |
c48f1496 | 1299 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1300 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1301 | return; |
1302 | ||
1303 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1304 | apic->lapic_timer.tscdeadline = data; | |
1305 | start_apic_timer(apic); | |
1306 | } | |
1307 | ||
97222cc8 ED |
1308 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1309 | { | |
ad312c7c | 1310 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1311 | |
c48f1496 | 1312 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1313 | return; |
54e9818f | 1314 | |
b93463aa | 1315 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
c48f1496 | 1316 | | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1317 | } |
1318 | ||
1319 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1320 | { | |
97222cc8 ED |
1321 | u64 tpr; |
1322 | ||
c48f1496 | 1323 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1324 | return 0; |
54e9818f | 1325 | |
c48f1496 | 1326 | tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1327 | |
1328 | return (tpr & 0xf0) >> 4; | |
1329 | } | |
1330 | ||
1331 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1332 | { | |
8d14695f | 1333 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1334 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1335 | |
1336 | if (!apic) { | |
1337 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1338 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1339 | return; |
1340 | } | |
c5af89b6 | 1341 | |
c5cc421b GN |
1342 | /* update jump label if enable bit changes */ |
1343 | if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) { | |
1344 | if (value & MSR_IA32_APICBASE_ENABLE) | |
1345 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1346 | else | |
1347 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1348 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1349 | } |
1350 | ||
c5af89b6 | 1351 | if (!kvm_vcpu_is_bsp(apic->vcpu)) |
97222cc8 ED |
1352 | value &= ~MSR_IA32_APICBASE_BSP; |
1353 | ||
ad312c7c | 1354 | vcpu->arch.apic_base = value; |
8d14695f YZ |
1355 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1356 | if (value & X2APIC_ENABLE) { | |
1357 | u32 id = kvm_apic_id(apic); | |
1358 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
1359 | kvm_apic_set_ldr(apic, ldr); | |
1360 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); | |
1361 | } else | |
1362 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1363 | } |
8d14695f | 1364 | |
ad312c7c | 1365 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1366 | MSR_IA32_APICBASE_BASE; |
1367 | ||
1368 | /* with FSB delivery interrupt, we can restart APIC functionality */ | |
1369 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1370 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1371 | |
1372 | } | |
1373 | ||
c5ec1534 | 1374 | void kvm_lapic_reset(struct kvm_vcpu *vcpu) |
97222cc8 ED |
1375 | { |
1376 | struct kvm_lapic *apic; | |
1377 | int i; | |
1378 | ||
b8688d51 | 1379 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1380 | |
1381 | ASSERT(vcpu); | |
ad312c7c | 1382 | apic = vcpu->arch.apic; |
97222cc8 ED |
1383 | ASSERT(apic != NULL); |
1384 | ||
1385 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1386 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1387 | |
1e08ec4a | 1388 | kvm_apic_set_id(apic, vcpu->vcpu_id); |
fc61b800 | 1389 | kvm_apic_set_version(apic->vcpu); |
97222cc8 ED |
1390 | |
1391 | for (i = 0; i < APIC_LVT_NUM; i++) | |
1392 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
40487c68 QH |
1393 | apic_set_reg(apic, APIC_LVT0, |
1394 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
97222cc8 ED |
1395 | |
1396 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
f8c1ea10 | 1397 | apic_set_spiv(apic, 0xff); |
97222cc8 | 1398 | apic_set_reg(apic, APIC_TASKPRI, 0); |
1e08ec4a | 1399 | kvm_apic_set_ldr(apic, 0); |
97222cc8 ED |
1400 | apic_set_reg(apic, APIC_ESR, 0); |
1401 | apic_set_reg(apic, APIC_ICR, 0); | |
1402 | apic_set_reg(apic, APIC_ICR2, 0); | |
1403 | apic_set_reg(apic, APIC_TDCR, 0); | |
1404 | apic_set_reg(apic, APIC_TMICT, 0); | |
1405 | for (i = 0; i < 8; i++) { | |
1406 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
1407 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1408 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
1409 | } | |
c7c9c56c YZ |
1410 | apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); |
1411 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm); | |
8680b94b | 1412 | apic->highest_isr_cache = -1; |
b33ac88b | 1413 | update_divide_count(apic); |
d3c7b77d | 1414 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1415 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1416 | kvm_lapic_set_base(vcpu, |
1417 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1418 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1419 | apic_update_ppr(apic); |
1420 | ||
e1035715 | 1421 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1422 | vcpu->arch.apic_attention = 0; |
e1035715 | 1423 | |
97222cc8 | 1424 | apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1425 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1426 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1427 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1428 | } |
1429 | ||
97222cc8 ED |
1430 | /* |
1431 | *---------------------------------------------------------------------- | |
1432 | * timer interface | |
1433 | *---------------------------------------------------------------------- | |
1434 | */ | |
1b9778da | 1435 | |
2a6eac96 | 1436 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1437 | { |
d3c7b77d | 1438 | return apic_lvtt_period(apic); |
97222cc8 ED |
1439 | } |
1440 | ||
3d80840d MT |
1441 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1442 | { | |
54e9818f | 1443 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1444 | |
c48f1496 | 1445 | if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && |
54e9818f GN |
1446 | apic_lvt_enabled(apic, APIC_LVTT)) |
1447 | return atomic_read(&apic->lapic_timer.pending); | |
3d80840d MT |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | ||
89342082 | 1452 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1453 | { |
c48f1496 | 1454 | u32 reg = kvm_apic_get_reg(apic, lvt_type); |
23930f95 | 1455 | int vector, mode, trig_mode; |
23930f95 | 1456 | |
c48f1496 | 1457 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1458 | vector = reg & APIC_VECTOR_MASK; |
1459 | mode = reg & APIC_MODE_MASK; | |
1460 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1461 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1462 | NULL); | |
23930f95 JK |
1463 | } |
1464 | return 0; | |
1465 | } | |
1b9778da | 1466 | |
8fdb2351 | 1467 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1468 | { |
8fdb2351 JK |
1469 | struct kvm_lapic *apic = vcpu->arch.apic; |
1470 | ||
1471 | if (apic) | |
1472 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1473 | } |
1474 | ||
d76685c4 GH |
1475 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1476 | .read = apic_mmio_read, | |
1477 | .write = apic_mmio_write, | |
d76685c4 GH |
1478 | }; |
1479 | ||
e9d90d47 AK |
1480 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1481 | { | |
1482 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 AK |
1483 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
1484 | struct kvm_vcpu *vcpu = apic->vcpu; | |
e9d90d47 AK |
1485 | wait_queue_head_t *q = &vcpu->wq; |
1486 | ||
1487 | /* | |
1488 | * There is a race window between reading and incrementing, but we do | |
1489 | * not care about potentially losing timer events in the !reinject | |
1490 | * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked | |
1491 | * in vcpu_enter_guest. | |
1492 | */ | |
2a6eac96 | 1493 | if (!atomic_read(&ktimer->pending)) { |
e9d90d47 AK |
1494 | atomic_inc(&ktimer->pending); |
1495 | /* FIXME: this code should not know anything about vcpus */ | |
1496 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1497 | } | |
1498 | ||
1499 | if (waitqueue_active(q)) | |
1500 | wake_up_interruptible(q); | |
1501 | ||
2a6eac96 | 1502 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1503 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1504 | return HRTIMER_RESTART; | |
1505 | } else | |
1506 | return HRTIMER_NORESTART; | |
1507 | } | |
1508 | ||
97222cc8 ED |
1509 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1510 | { | |
1511 | struct kvm_lapic *apic; | |
1512 | ||
1513 | ASSERT(vcpu != NULL); | |
1514 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1515 | ||
1516 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1517 | if (!apic) | |
1518 | goto nomem; | |
1519 | ||
ad312c7c | 1520 | vcpu->arch.apic = apic; |
97222cc8 | 1521 | |
afc20184 TY |
1522 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1523 | if (!apic->regs) { | |
97222cc8 ED |
1524 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1525 | vcpu->vcpu_id); | |
d589444e | 1526 | goto nomem_free_apic; |
97222cc8 | 1527 | } |
97222cc8 ED |
1528 | apic->vcpu = vcpu; |
1529 | ||
d3c7b77d MT |
1530 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
1531 | HRTIMER_MODE_ABS); | |
e9d90d47 | 1532 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1533 | |
c5cc421b GN |
1534 | /* |
1535 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1536 | * thinking that APIC satet has changed. | |
1537 | */ | |
1538 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1539 | kvm_lapic_set_base(vcpu, |
1540 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1541 | |
f8c1ea10 | 1542 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
c5ec1534 | 1543 | kvm_lapic_reset(vcpu); |
d76685c4 | 1544 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1545 | |
1546 | return 0; | |
d589444e RR |
1547 | nomem_free_apic: |
1548 | kfree(apic); | |
97222cc8 | 1549 | nomem: |
97222cc8 ED |
1550 | return -ENOMEM; |
1551 | } | |
97222cc8 ED |
1552 | |
1553 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1554 | { | |
ad312c7c | 1555 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1556 | int highest_irr; |
1557 | ||
c48f1496 | 1558 | if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) |
97222cc8 ED |
1559 | return -1; |
1560 | ||
6e5d865c | 1561 | apic_update_ppr(apic); |
97222cc8 ED |
1562 | highest_irr = apic_find_highest_irr(apic); |
1563 | if ((highest_irr == -1) || | |
c48f1496 | 1564 | ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1565 | return -1; |
1566 | return highest_irr; | |
1567 | } | |
1568 | ||
40487c68 QH |
1569 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1570 | { | |
c48f1496 | 1571 | u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1572 | int r = 0; |
1573 | ||
c48f1496 | 1574 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1575 | r = 1; |
1576 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1577 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1578 | r = 1; | |
40487c68 QH |
1579 | return r; |
1580 | } | |
1581 | ||
1b9778da ED |
1582 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1583 | { | |
ad312c7c | 1584 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1585 | |
c48f1496 | 1586 | if (!kvm_vcpu_has_lapic(vcpu)) |
54e9818f GN |
1587 | return; |
1588 | ||
1589 | if (atomic_read(&apic->lapic_timer.pending) > 0) { | |
8fdb2351 | 1590 | if (kvm_apic_local_deliver(apic, APIC_LVTT)) |
d3c7b77d | 1591 | atomic_dec(&apic->lapic_timer.pending); |
1b9778da ED |
1592 | } |
1593 | } | |
1594 | ||
97222cc8 ED |
1595 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1596 | { | |
1597 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1598 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1599 | |
1600 | if (vector == -1) | |
1601 | return -1; | |
1602 | ||
8680b94b | 1603 | apic_set_isr(vector, apic); |
97222cc8 ED |
1604 | apic_update_ppr(apic); |
1605 | apic_clear_irr(vector, apic); | |
1606 | return vector; | |
1607 | } | |
96ad2cc6 | 1608 | |
64eb0620 GN |
1609 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1610 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1611 | { |
ad312c7c | 1612 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1613 | |
5dbc8f3f | 1614 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1615 | /* set SPIV separately to get count of SW disabled APICs right */ |
1616 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1617 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1618 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1619 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1620 | kvm_apic_set_version(vcpu); |
1621 | ||
96ad2cc6 | 1622 | apic_update_ppr(apic); |
d3c7b77d | 1623 | hrtimer_cancel(&apic->lapic_timer.timer); |
96ad2cc6 ED |
1624 | update_divide_count(apic); |
1625 | start_apic_timer(apic); | |
6e24a6ef | 1626 | apic->irr_pending = true; |
c7c9c56c YZ |
1627 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ? |
1628 | 1 : count_vectors(apic->regs + APIC_ISR); | |
8680b94b | 1629 | apic->highest_isr_cache = -1; |
c7c9c56c | 1630 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic)); |
3842d135 | 1631 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
10606919 | 1632 | kvm_rtc_eoi_tracking_restore_one(vcpu); |
96ad2cc6 | 1633 | } |
a3d7f85f | 1634 | |
2f52d58c | 1635 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1636 | { |
a3d7f85f ED |
1637 | struct hrtimer *timer; |
1638 | ||
c48f1496 | 1639 | if (!kvm_vcpu_has_lapic(vcpu)) |
a3d7f85f ED |
1640 | return; |
1641 | ||
54e9818f | 1642 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1643 | if (hrtimer_cancel(timer)) |
beb20d52 | 1644 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1645 | } |
b93463aa | 1646 | |
ae7a2a3f MT |
1647 | /* |
1648 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1649 | * | |
1650 | * Detect whether guest triggered PV EOI since the | |
1651 | * last entry. If yes, set EOI on guests's behalf. | |
1652 | * Clear PV EOI in guest memory in any case. | |
1653 | */ | |
1654 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1655 | struct kvm_lapic *apic) | |
1656 | { | |
1657 | bool pending; | |
1658 | int vector; | |
1659 | /* | |
1660 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
1661 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
1662 | * | |
1663 | * KVM_APIC_PV_EOI_PENDING is unset: | |
1664 | * -> host disabled PV EOI. | |
1665 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
1666 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
1667 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
1668 | * -> host enabled PV EOI, guest executed EOI. | |
1669 | */ | |
1670 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
1671 | pending = pv_eoi_get_pending(vcpu); | |
1672 | /* | |
1673 | * Clear pending bit in any case: it will be set again on vmentry. | |
1674 | * While this might not be ideal from performance point of view, | |
1675 | * this makes sure pv eoi is only enabled when we know it's safe. | |
1676 | */ | |
1677 | pv_eoi_clr_pending(vcpu); | |
1678 | if (pending) | |
1679 | return; | |
1680 | vector = apic_set_eoi(apic); | |
1681 | trace_kvm_pv_eoi(apic, vector); | |
1682 | } | |
1683 | ||
b93463aa AK |
1684 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
1685 | { | |
1686 | u32 data; | |
1687 | void *vapic; | |
1688 | ||
ae7a2a3f MT |
1689 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
1690 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
1691 | ||
41383771 | 1692 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1693 | return; |
1694 | ||
8fd75e12 | 1695 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page); |
b93463aa | 1696 | data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); |
8fd75e12 | 1697 | kunmap_atomic(vapic); |
b93463aa AK |
1698 | |
1699 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1700 | } | |
1701 | ||
ae7a2a3f MT |
1702 | /* |
1703 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
1704 | * | |
1705 | * Detect whether it's safe to enable PV EOI and | |
1706 | * if yes do so. | |
1707 | */ | |
1708 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
1709 | struct kvm_lapic *apic) | |
1710 | { | |
1711 | if (!pv_eoi_enabled(vcpu) || | |
1712 | /* IRR set or many bits in ISR: could be nested. */ | |
1713 | apic->irr_pending || | |
1714 | /* Cache not set: could be safe but we don't bother. */ | |
1715 | apic->highest_isr_cache == -1 || | |
1716 | /* Need EOI to update ioapic. */ | |
1717 | kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { | |
1718 | /* | |
1719 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
1720 | * so we need not do anything here. | |
1721 | */ | |
1722 | return; | |
1723 | } | |
1724 | ||
1725 | pv_eoi_set_pending(apic->vcpu); | |
1726 | } | |
1727 | ||
b93463aa AK |
1728 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
1729 | { | |
1730 | u32 data, tpr; | |
1731 | int max_irr, max_isr; | |
ae7a2a3f | 1732 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa AK |
1733 | void *vapic; |
1734 | ||
ae7a2a3f MT |
1735 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
1736 | ||
41383771 | 1737 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1738 | return; |
1739 | ||
c48f1496 | 1740 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
1741 | max_irr = apic_find_highest_irr(apic); |
1742 | if (max_irr < 0) | |
1743 | max_irr = 0; | |
1744 | max_isr = apic_find_highest_isr(apic); | |
1745 | if (max_isr < 0) | |
1746 | max_isr = 0; | |
1747 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1748 | ||
8fd75e12 | 1749 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page); |
b93463aa | 1750 | *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; |
8fd75e12 | 1751 | kunmap_atomic(vapic); |
b93463aa AK |
1752 | } |
1753 | ||
1754 | void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) | |
1755 | { | |
b93463aa | 1756 | vcpu->arch.apic->vapic_addr = vapic_addr; |
41383771 GN |
1757 | if (vapic_addr) |
1758 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); | |
1759 | else | |
1760 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); | |
b93463aa | 1761 | } |
0105d1a5 GN |
1762 | |
1763 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1764 | { | |
1765 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1766 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
1767 | ||
1768 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1769 | return 1; | |
1770 | ||
1771 | /* if this is ICR write vector before command */ | |
1772 | if (msr == 0x830) | |
1773 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
1774 | return apic_reg_write(apic, reg, (u32)data); | |
1775 | } | |
1776 | ||
1777 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
1778 | { | |
1779 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1780 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
1781 | ||
1782 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1783 | return 1; | |
1784 | ||
1785 | if (apic_reg_read(apic, reg, 4, &low)) | |
1786 | return 1; | |
1787 | if (msr == 0x830) | |
1788 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
1789 | ||
1790 | *data = (((u64)high) << 32) | low; | |
1791 | ||
1792 | return 0; | |
1793 | } | |
10388a07 GN |
1794 | |
1795 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
1796 | { | |
1797 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1798 | ||
c48f1496 | 1799 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1800 | return 1; |
1801 | ||
1802 | /* if this is ICR write vector before command */ | |
1803 | if (reg == APIC_ICR) | |
1804 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
1805 | return apic_reg_write(apic, reg, (u32)data); | |
1806 | } | |
1807 | ||
1808 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
1809 | { | |
1810 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1811 | u32 low, high = 0; | |
1812 | ||
c48f1496 | 1813 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1814 | return 1; |
1815 | ||
1816 | if (apic_reg_read(apic, reg, 4, &low)) | |
1817 | return 1; | |
1818 | if (reg == APIC_ICR) | |
1819 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
1820 | ||
1821 | *data = (((u64)high) << 32) | low; | |
1822 | ||
1823 | return 0; | |
1824 | } | |
ae7a2a3f MT |
1825 | |
1826 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
1827 | { | |
1828 | u64 addr = data & ~KVM_MSR_ENABLED; | |
1829 | if (!IS_ALIGNED(addr, 4)) | |
1830 | return 1; | |
1831 | ||
1832 | vcpu->arch.pv_eoi.msr_val = data; | |
1833 | if (!pv_eoi_enabled(vcpu)) | |
1834 | return 0; | |
1835 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
1836 | addr); | |
1837 | } | |
c5cc421b | 1838 | |
66450a21 JK |
1839 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
1840 | { | |
1841 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1842 | unsigned int sipi_vector; | |
1843 | ||
1844 | if (!kvm_vcpu_has_lapic(vcpu)) | |
1845 | return; | |
1846 | ||
1847 | if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { | |
1848 | kvm_lapic_reset(vcpu); | |
1849 | kvm_vcpu_reset(vcpu); | |
1850 | if (kvm_vcpu_is_bsp(apic->vcpu)) | |
1851 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
1852 | else | |
1853 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
1854 | } | |
1855 | if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events) && | |
1856 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
1857 | /* evaluate pending_events before reading the vector */ | |
1858 | smp_rmb(); | |
1859 | sipi_vector = apic->sipi_vector; | |
1860 | pr_debug("vcpu %d received sipi with vector # %x\n", | |
1861 | vcpu->vcpu_id, sipi_vector); | |
1862 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
1863 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
1864 | } | |
1865 | } | |
1866 | ||
c5cc421b GN |
1867 | void kvm_lapic_init(void) |
1868 | { | |
1869 | /* do not patch jump label more than once per second */ | |
1870 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 1871 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 1872 | } |