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82470196 ZX |
1 | #ifndef __KVM_X86_LAPIC_H |
2 | #define __KVM_X86_LAPIC_H | |
3 | ||
af669ac6 | 4 | #include <kvm/iodev.h> |
82470196 ZX |
5 | |
6 | #include <linux/kvm_host.h> | |
7 | ||
66450a21 JK |
8 | #define KVM_APIC_INIT 0 |
9 | #define KVM_APIC_SIPI 1 | |
10 | ||
e9d90d47 AK |
11 | struct kvm_timer { |
12 | struct hrtimer timer; | |
13 | s64 period; /* unit: ns */ | |
a323b409 | 14 | u32 timer_mode; |
e9d90d47 AK |
15 | u32 timer_mode_mask; |
16 | u64 tscdeadline; | |
d0659d94 | 17 | u64 expired_tscdeadline; |
e9d90d47 | 18 | atomic_t pending; /* accumulated triggered timers */ |
e9d90d47 AK |
19 | }; |
20 | ||
82470196 ZX |
21 | struct kvm_lapic { |
22 | unsigned long base_address; | |
23 | struct kvm_io_device dev; | |
d3c7b77d MT |
24 | struct kvm_timer lapic_timer; |
25 | u32 divide_count; | |
82470196 | 26 | struct kvm_vcpu *vcpu; |
e462755c | 27 | bool sw_enabled; |
33e4c686 | 28 | bool irr_pending; |
59fd1323 | 29 | bool lvt0_in_nmi_mode; |
8680b94b MT |
30 | /* Number of bits set in ISR. */ |
31 | s16 isr_count; | |
32 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ | |
33 | int highest_isr_cache; | |
5eadf916 MT |
34 | /** |
35 | * APIC register page. The layout matches the register layout seen by | |
36 | * the guest 1:1, because it is accessed by the vmx microcode. | |
37 | * Note: Only one register, the TPR, is used by the microcode. | |
38 | */ | |
82470196 | 39 | void *regs; |
b93463aa | 40 | gpa_t vapic_addr; |
fda4e2e8 | 41 | struct gfn_to_hva_cache vapic_cache; |
66450a21 JK |
42 | unsigned long pending_events; |
43 | unsigned int sipi_vector; | |
82470196 | 44 | }; |
9e4aabe2 JR |
45 | |
46 | struct dest_map; | |
47 | ||
82470196 ZX |
48 | int kvm_create_lapic(struct kvm_vcpu *vcpu); |
49 | void kvm_free_lapic(struct kvm_vcpu *vcpu); | |
50 | ||
51 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
52 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); | |
53 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); | |
66450a21 | 54 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu); |
d28bc9dd | 55 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); |
82470196 ZX |
56 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); |
57 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
58fbbf26 | 58 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
82470196 | 59 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
8b2cf73c | 60 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
fc61b800 | 61 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
82470196 | 62 | |
705699a1 | 63 | void __kvm_apic_update_irr(u32 *pir, void *regs); |
a20ed54d | 64 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); |
b4f2225c | 65 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 66 | struct dest_map *dest_map); |
89342082 | 67 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
82470196 | 68 | |
1e08ec4a | 69 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 70 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); |
1e08ec4a | 71 | |
82470196 | 72 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
58cb628d | 73 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
64eb0620 GN |
74 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
75 | struct kvm_lapic_state *s); | |
82470196 | 76 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
82470196 | 77 | |
a3e06bbe LJ |
78 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
79 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); | |
80 | ||
83d4c286 | 81 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
c7c9c56c | 82 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); |
83d4c286 | 83 | |
fda4e2e8 | 84 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
b93463aa AK |
85 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); |
86 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); | |
87 | ||
0105d1a5 GN |
88 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
89 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
10388a07 GN |
90 | |
91 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
92 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
93 | ||
94 | static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) | |
95 | { | |
e83d5887 | 96 | return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; |
10388a07 | 97 | } |
ae7a2a3f MT |
98 | |
99 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); | |
c5cc421b | 100 | void kvm_lapic_init(void); |
c48f1496 GN |
101 | |
102 | static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) | |
103 | { | |
104 | return *((u32 *) (apic->regs + reg_off)); | |
105 | } | |
106 | ||
107 | extern struct static_key kvm_no_apic_vcpu; | |
108 | ||
bce87cce | 109 | static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) |
c48f1496 GN |
110 | { |
111 | if (static_key_false(&kvm_no_apic_vcpu)) | |
112 | return vcpu->arch.apic; | |
113 | return true; | |
114 | } | |
115 | ||
116 | extern struct static_key_deferred apic_hw_disabled; | |
117 | ||
118 | static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) | |
119 | { | |
120 | if (static_key_false(&apic_hw_disabled.key)) | |
121 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; | |
122 | return MSR_IA32_APICBASE_ENABLE; | |
123 | } | |
124 | ||
125 | extern struct static_key_deferred apic_sw_disabled; | |
126 | ||
f30ebc31 | 127 | static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) |
c48f1496 GN |
128 | { |
129 | if (static_key_false(&apic_sw_disabled.key)) | |
f30ebc31 RK |
130 | return apic->sw_enabled; |
131 | return true; | |
c48f1496 GN |
132 | } |
133 | ||
134 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) | |
135 | { | |
bce87cce | 136 | return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); |
c48f1496 GN |
137 | } |
138 | ||
139 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
140 | { | |
141 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); | |
142 | } | |
143 | ||
8d14695f YZ |
144 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
145 | { | |
146 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; | |
147 | } | |
148 | ||
d62caabb | 149 | static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) |
c7c9c56c | 150 | { |
d62caabb | 151 | return vcpu->arch.apic && vcpu->arch.apicv_active; |
c7c9c56c YZ |
152 | } |
153 | ||
66450a21 JK |
154 | static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) |
155 | { | |
bce87cce | 156 | return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; |
66450a21 JK |
157 | } |
158 | ||
d1ebdbf9 JS |
159 | static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) |
160 | { | |
161 | return (irq->delivery_mode == APIC_DM_LOWEST || | |
162 | irq->msi_redir_hint); | |
163 | } | |
164 | ||
f077825a PB |
165 | static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) |
166 | { | |
bce87cce | 167 | return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); |
f077825a PB |
168 | } |
169 | ||
5c919412 AS |
170 | static inline int kvm_apic_id(struct kvm_lapic *apic) |
171 | { | |
172 | return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; | |
173 | } | |
174 | ||
10606919 YZ |
175 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); |
176 | ||
d0659d94 MT |
177 | void wait_lapic_expire(struct kvm_vcpu *vcpu); |
178 | ||
8feb4a04 FW |
179 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
180 | struct kvm_vcpu **dest_vcpu); | |
52004014 FW |
181 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
182 | const unsigned long *bitmap, u32 bitmap_size); | |
82470196 | 183 | #endif |