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82470196 ZX |
1 | #ifndef __KVM_X86_LAPIC_H |
2 | #define __KVM_X86_LAPIC_H | |
3 | ||
4 | #include "iodev.h" | |
5 | ||
6 | #include <linux/kvm_host.h> | |
7 | ||
66450a21 JK |
8 | #define KVM_APIC_INIT 0 |
9 | #define KVM_APIC_SIPI 1 | |
10 | ||
e9d90d47 AK |
11 | struct kvm_timer { |
12 | struct hrtimer timer; | |
13 | s64 period; /* unit: ns */ | |
a323b409 | 14 | u32 timer_mode; |
e9d90d47 AK |
15 | u32 timer_mode_mask; |
16 | u64 tscdeadline; | |
d0659d94 | 17 | u64 expired_tscdeadline; |
e9d90d47 | 18 | atomic_t pending; /* accumulated triggered timers */ |
e9d90d47 AK |
19 | }; |
20 | ||
82470196 ZX |
21 | struct kvm_lapic { |
22 | unsigned long base_address; | |
23 | struct kvm_io_device dev; | |
d3c7b77d MT |
24 | struct kvm_timer lapic_timer; |
25 | u32 divide_count; | |
82470196 | 26 | struct kvm_vcpu *vcpu; |
e462755c | 27 | bool sw_enabled; |
33e4c686 | 28 | bool irr_pending; |
8680b94b MT |
29 | /* Number of bits set in ISR. */ |
30 | s16 isr_count; | |
31 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ | |
32 | int highest_isr_cache; | |
5eadf916 MT |
33 | /** |
34 | * APIC register page. The layout matches the register layout seen by | |
35 | * the guest 1:1, because it is accessed by the vmx microcode. | |
36 | * Note: Only one register, the TPR, is used by the microcode. | |
37 | */ | |
82470196 | 38 | void *regs; |
b93463aa | 39 | gpa_t vapic_addr; |
fda4e2e8 | 40 | struct gfn_to_hva_cache vapic_cache; |
66450a21 JK |
41 | unsigned long pending_events; |
42 | unsigned int sipi_vector; | |
82470196 ZX |
43 | }; |
44 | int kvm_create_lapic(struct kvm_vcpu *vcpu); | |
45 | void kvm_free_lapic(struct kvm_vcpu *vcpu); | |
46 | ||
47 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
48 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); | |
49 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); | |
66450a21 | 50 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu); |
82470196 ZX |
51 | void kvm_lapic_reset(struct kvm_vcpu *vcpu); |
52 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); | |
53 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
58fbbf26 | 54 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
82470196 | 55 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
8b2cf73c | 56 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
fc61b800 | 57 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
82470196 | 58 | |
cf9e65b7 | 59 | void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr); |
705699a1 | 60 | void __kvm_apic_update_irr(u32 *pir, void *regs); |
a20ed54d | 61 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); |
b4f2225c YZ |
62 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
63 | unsigned long *dest_map); | |
89342082 | 64 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
82470196 | 65 | |
1e08ec4a | 66 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 67 | struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map); |
1e08ec4a | 68 | |
82470196 | 69 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
58cb628d | 70 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
64eb0620 GN |
71 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
72 | struct kvm_lapic_state *s); | |
82470196 | 73 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
82470196 | 74 | |
a3e06bbe LJ |
75 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
76 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); | |
77 | ||
83d4c286 | 78 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
c7c9c56c | 79 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); |
83d4c286 | 80 | |
fda4e2e8 | 81 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
b93463aa AK |
82 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); |
83 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); | |
84 | ||
0105d1a5 GN |
85 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
86 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
10388a07 GN |
87 | |
88 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
89 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
90 | ||
91 | static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) | |
92 | { | |
93 | return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; | |
94 | } | |
ae7a2a3f MT |
95 | |
96 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); | |
c5cc421b | 97 | void kvm_lapic_init(void); |
c48f1496 GN |
98 | |
99 | static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) | |
100 | { | |
101 | return *((u32 *) (apic->regs + reg_off)); | |
102 | } | |
103 | ||
104 | extern struct static_key kvm_no_apic_vcpu; | |
105 | ||
106 | static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) | |
107 | { | |
108 | if (static_key_false(&kvm_no_apic_vcpu)) | |
109 | return vcpu->arch.apic; | |
110 | return true; | |
111 | } | |
112 | ||
113 | extern struct static_key_deferred apic_hw_disabled; | |
114 | ||
115 | static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) | |
116 | { | |
117 | if (static_key_false(&apic_hw_disabled.key)) | |
118 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; | |
119 | return MSR_IA32_APICBASE_ENABLE; | |
120 | } | |
121 | ||
122 | extern struct static_key_deferred apic_sw_disabled; | |
123 | ||
f30ebc31 | 124 | static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) |
c48f1496 GN |
125 | { |
126 | if (static_key_false(&apic_sw_disabled.key)) | |
f30ebc31 RK |
127 | return apic->sw_enabled; |
128 | return true; | |
c48f1496 GN |
129 | } |
130 | ||
131 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) | |
132 | { | |
133 | return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); | |
134 | } | |
135 | ||
136 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
137 | { | |
138 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); | |
139 | } | |
140 | ||
8d14695f YZ |
141 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
142 | { | |
143 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; | |
144 | } | |
145 | ||
c7c9c56c YZ |
146 | static inline bool kvm_apic_vid_enabled(struct kvm *kvm) |
147 | { | |
148 | return kvm_x86_ops->vm_has_apicv(kvm); | |
149 | } | |
150 | ||
151 | static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr) | |
152 | { | |
153 | u16 cid; | |
154 | ldr >>= 32 - map->ldr_bits; | |
155 | cid = (ldr >> map->cid_shift) & map->cid_mask; | |
156 | ||
c7c9c56c YZ |
157 | return cid; |
158 | } | |
159 | ||
160 | static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr) | |
161 | { | |
162 | ldr >>= (32 - map->ldr_bits); | |
163 | return ldr & map->lid_mask; | |
164 | } | |
165 | ||
66450a21 JK |
166 | static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) |
167 | { | |
168 | return vcpu->arch.apic->pending_events; | |
169 | } | |
170 | ||
10606919 YZ |
171 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); |
172 | ||
d0659d94 MT |
173 | void wait_lapic_expire(struct kvm_vcpu *vcpu); |
174 | ||
82470196 | 175 | #endif |