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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
82470196 ZX |
2 | #ifndef __KVM_X86_LAPIC_H |
3 | #define __KVM_X86_LAPIC_H | |
4 | ||
af669ac6 | 5 | #include <kvm/iodev.h> |
82470196 ZX |
6 | |
7 | #include <linux/kvm_host.h> | |
8 | ||
66450a21 JK |
9 | #define KVM_APIC_INIT 0 |
10 | #define KVM_APIC_SIPI 1 | |
1e6e2755 | 11 | #define KVM_APIC_LVT_NUM 6 |
66450a21 | 12 | |
18f40c53 SS |
13 | #define KVM_APIC_SHORT_MASK 0xc0000 |
14 | #define KVM_APIC_DEST_MASK 0x800 | |
15 | ||
72c139ba LP |
16 | #define APIC_BUS_CYCLE_NS 1 |
17 | #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS) | |
18 | ||
e97ac445 JM |
19 | enum lapic_mode { |
20 | LAPIC_MODE_DISABLED = 0, | |
21 | LAPIC_MODE_INVALID = X2APIC_ENABLE, | |
22 | LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, | |
23 | LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, | |
24 | }; | |
25 | ||
e9d90d47 AK |
26 | struct kvm_timer { |
27 | struct hrtimer timer; | |
28 | s64 period; /* unit: ns */ | |
8003c9ae | 29 | ktime_t target_expiration; |
a323b409 | 30 | u32 timer_mode; |
e9d90d47 AK |
31 | u32 timer_mode_mask; |
32 | u64 tscdeadline; | |
d0659d94 | 33 | u64 expired_tscdeadline; |
e9d90d47 | 34 | atomic_t pending; /* accumulated triggered timers */ |
ce7a058a | 35 | bool hv_timer_in_use; |
e9d90d47 AK |
36 | }; |
37 | ||
82470196 ZX |
38 | struct kvm_lapic { |
39 | unsigned long base_address; | |
40 | struct kvm_io_device dev; | |
d3c7b77d MT |
41 | struct kvm_timer lapic_timer; |
42 | u32 divide_count; | |
82470196 | 43 | struct kvm_vcpu *vcpu; |
e462755c | 44 | bool sw_enabled; |
33e4c686 | 45 | bool irr_pending; |
59fd1323 | 46 | bool lvt0_in_nmi_mode; |
8680b94b MT |
47 | /* Number of bits set in ISR. */ |
48 | s16 isr_count; | |
49 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ | |
50 | int highest_isr_cache; | |
5eadf916 MT |
51 | /** |
52 | * APIC register page. The layout matches the register layout seen by | |
53 | * the guest 1:1, because it is accessed by the vmx microcode. | |
54 | * Note: Only one register, the TPR, is used by the microcode. | |
55 | */ | |
82470196 | 56 | void *regs; |
b93463aa | 57 | gpa_t vapic_addr; |
fda4e2e8 | 58 | struct gfn_to_hva_cache vapic_cache; |
66450a21 JK |
59 | unsigned long pending_events; |
60 | unsigned int sipi_vector; | |
82470196 | 61 | }; |
9e4aabe2 JR |
62 | |
63 | struct dest_map; | |
64 | ||
82470196 ZX |
65 | int kvm_create_lapic(struct kvm_vcpu *vcpu); |
66 | void kvm_free_lapic(struct kvm_vcpu *vcpu); | |
67 | ||
68 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
69 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); | |
70 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); | |
66450a21 | 71 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu); |
d28bc9dd | 72 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); |
82470196 ZX |
73 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); |
74 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
58fbbf26 | 75 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
82470196 | 76 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
8b2cf73c | 77 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
fc61b800 | 78 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
1e6e2755 SS |
79 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); |
80 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, | |
81 | void *data); | |
82 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, | |
83 | int short_hand, unsigned int dest, int dest_mode); | |
82470196 | 84 | |
810e6def PB |
85 | int __kvm_apic_update_irr(u32 *pir, void *regs); |
86 | int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); | |
eb90f341 | 87 | void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); |
b4f2225c | 88 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 89 | struct dest_map *dest_map); |
89342082 | 90 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
82470196 | 91 | |
1e08ec4a | 92 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 93 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); |
1e08ec4a | 94 | |
82470196 | 95 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
58cb628d | 96 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
a92e2543 RK |
97 | int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); |
98 | int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); | |
e97ac445 | 99 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu); |
82470196 | 100 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
82470196 | 101 | |
a3e06bbe LJ |
102 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
103 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); | |
104 | ||
83d4c286 | 105 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
c7c9c56c | 106 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); |
83d4c286 | 107 | |
fda4e2e8 | 108 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
b93463aa AK |
109 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); |
110 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); | |
111 | ||
0105d1a5 GN |
112 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
113 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
10388a07 GN |
114 | |
115 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
116 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
117 | ||
118 | static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) | |
119 | { | |
e83d5887 | 120 | return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; |
10388a07 | 121 | } |
ae7a2a3f MT |
122 | |
123 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); | |
c5cc421b | 124 | void kvm_lapic_init(void); |
cef84c30 | 125 | void kvm_lapic_exit(void); |
c48f1496 | 126 | |
1e6e2755 SS |
127 | #define VEC_POS(v) ((v) & (32 - 1)) |
128 | #define REG_POS(v) (((v) >> 5) << 4) | |
129 | ||
130 | static inline void kvm_lapic_set_vector(int vec, void *bitmap) | |
131 | { | |
132 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
133 | } | |
134 | ||
135 | static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) | |
136 | { | |
137 | kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); | |
138 | /* | |
139 | * irr_pending must be true if any interrupt is pending; set it after | |
140 | * APIC_IRR to avoid race with apic_clear_irr | |
141 | */ | |
142 | apic->irr_pending = true; | |
143 | } | |
144 | ||
dfb95954 | 145 | static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) |
c48f1496 | 146 | { |
dfb95954 | 147 | return *((u32 *) (apic->regs + reg_off)); |
c48f1496 GN |
148 | } |
149 | ||
1e6e2755 SS |
150 | static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
151 | { | |
152 | *((u32 *) (apic->regs + reg_off)) = val; | |
153 | } | |
154 | ||
c48f1496 GN |
155 | extern struct static_key kvm_no_apic_vcpu; |
156 | ||
bce87cce | 157 | static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) |
c48f1496 GN |
158 | { |
159 | if (static_key_false(&kvm_no_apic_vcpu)) | |
160 | return vcpu->arch.apic; | |
161 | return true; | |
162 | } | |
163 | ||
164 | extern struct static_key_deferred apic_hw_disabled; | |
165 | ||
166 | static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) | |
167 | { | |
168 | if (static_key_false(&apic_hw_disabled.key)) | |
169 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; | |
170 | return MSR_IA32_APICBASE_ENABLE; | |
171 | } | |
172 | ||
173 | extern struct static_key_deferred apic_sw_disabled; | |
174 | ||
f30ebc31 | 175 | static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) |
c48f1496 GN |
176 | { |
177 | if (static_key_false(&apic_sw_disabled.key)) | |
f30ebc31 RK |
178 | return apic->sw_enabled; |
179 | return true; | |
c48f1496 GN |
180 | } |
181 | ||
182 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) | |
183 | { | |
bce87cce | 184 | return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); |
c48f1496 GN |
185 | } |
186 | ||
187 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
188 | { | |
189 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); | |
190 | } | |
191 | ||
8d14695f YZ |
192 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
193 | { | |
194 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; | |
195 | } | |
196 | ||
d62caabb | 197 | static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) |
c7c9c56c | 198 | { |
d62caabb | 199 | return vcpu->arch.apic && vcpu->arch.apicv_active; |
c7c9c56c YZ |
200 | } |
201 | ||
66450a21 JK |
202 | static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) |
203 | { | |
bce87cce | 204 | return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; |
66450a21 JK |
205 | } |
206 | ||
d1ebdbf9 JS |
207 | static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) |
208 | { | |
209 | return (irq->delivery_mode == APIC_DM_LOWEST || | |
210 | irq->msi_redir_hint); | |
211 | } | |
212 | ||
f077825a PB |
213 | static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) |
214 | { | |
bce87cce | 215 | return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); |
f077825a PB |
216 | } |
217 | ||
10606919 YZ |
218 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); |
219 | ||
d0659d94 MT |
220 | void wait_lapic_expire(struct kvm_vcpu *vcpu); |
221 | ||
8feb4a04 FW |
222 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
223 | struct kvm_vcpu **dest_vcpu); | |
52004014 FW |
224 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
225 | const unsigned long *bitmap, u32 bitmap_size); | |
ce7a058a YJ |
226 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); |
227 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); | |
228 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); | |
229 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); | |
a749e247 | 230 | void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); |
e97ac445 JM |
231 | |
232 | static inline enum lapic_mode kvm_apic_mode(u64 apic_base) | |
233 | { | |
234 | return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
235 | } | |
236 | ||
82470196 | 237 | #endif |