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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
4a98623d | 51 | #include <asm/set_memory.h> |
13673a90 | 52 | #include <asm/vmx.h> |
3d0c27ad | 53 | #include <asm/kvm_page_track.h> |
1261bfa3 | 54 | #include "trace.h" |
6aa8b732 | 55 | |
fc9bf2e0 SC |
56 | #include "paging.h" |
57 | ||
b8e8c830 PB |
58 | extern bool itlb_multihit_kvm_mitigation; |
59 | ||
a9d6496d | 60 | int __read_mostly nx_huge_pages = -1; |
13fb5927 PB |
61 | #ifdef CONFIG_PREEMPT_RT |
62 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
63 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
64 | #else | |
1aa9b957 | 65 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 66 | #endif |
b8e8c830 PB |
67 | |
68 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 69 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 70 | |
d5d6c18d | 71 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
72 | .set = set_nx_huge_pages, |
73 | .get = param_get_bool, | |
74 | }; | |
75 | ||
d5d6c18d | 76 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
77 | .set = set_nx_huge_pages_recovery_ratio, |
78 | .get = param_get_uint, | |
79 | }; | |
80 | ||
b8e8c830 PB |
81 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
82 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
83 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
84 | &nx_huge_pages_recovery_ratio, 0644); | |
85 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 86 | |
71fe7013 SC |
87 | static bool __read_mostly force_flush_and_sync_on_reuse; |
88 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
89 | ||
18552672 JR |
90 | /* |
91 | * When setting this variable to true it enables Two-Dimensional-Paging | |
92 | * where the hardware walks 2 page tables: | |
93 | * 1. the guest-virtual to guest-physical | |
94 | * 2. while doing 1. it walks guest-physical to host-physical | |
95 | * If the hardware supports that we don't need to do shadow paging. | |
96 | */ | |
2f333bcb | 97 | bool tdp_enabled = false; |
18552672 | 98 | |
1d92d2e8 | 99 | static int max_huge_page_level __read_mostly; |
83013059 | 100 | static int max_tdp_level __read_mostly; |
703c335d | 101 | |
8b1fe17c XG |
102 | enum { |
103 | AUDIT_PRE_PAGE_FAULT, | |
104 | AUDIT_POST_PAGE_FAULT, | |
105 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
106 | AUDIT_POST_PTE_WRITE, |
107 | AUDIT_PRE_SYNC, | |
108 | AUDIT_POST_SYNC | |
8b1fe17c | 109 | }; |
37a7d8b0 | 110 | |
37a7d8b0 | 111 | #ifdef MMU_DEBUG |
5a9624af | 112 | bool dbg = 0; |
fa4a2c08 | 113 | module_param(dbg, bool, 0644); |
d6c69ee9 | 114 | #endif |
6aa8b732 | 115 | |
957ed9ef XG |
116 | #define PTE_PREFETCH_NUM 8 |
117 | ||
6aa8b732 AK |
118 | #define PT32_LEVEL_BITS 10 |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
6aa8b732 AK |
131 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
132 | #define PT32_DIR_BASE_ADDR_MASK \ | |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT32_LVL_ADDR_MASK(level) \ |
135 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 137 | |
90bb6fc5 AK |
138 | #include <trace/events/kvm.h> |
139 | ||
220f773a TY |
140 | /* make pte_list_desc fit well in cache line */ |
141 | #define PTE_LIST_EXT 3 | |
142 | ||
53c07b18 XG |
143 | struct pte_list_desc { |
144 | u64 *sptes[PTE_LIST_EXT]; | |
145 | struct pte_list_desc *more; | |
cd4a4e53 AK |
146 | }; |
147 | ||
2d11123a AK |
148 | struct kvm_shadow_walk_iterator { |
149 | u64 addr; | |
150 | hpa_t shadow_addr; | |
2d11123a | 151 | u64 *sptep; |
dd3bfd59 | 152 | int level; |
2d11123a AK |
153 | unsigned index; |
154 | }; | |
155 | ||
7eb77e9f JS |
156 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
157 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
158 | (_root), (_addr)); \ | |
159 | shadow_walk_okay(&(_walker)); \ | |
160 | shadow_walk_next(&(_walker))) | |
161 | ||
162 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
163 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
164 | shadow_walk_okay(&(_walker)); \ | |
165 | shadow_walk_next(&(_walker))) | |
166 | ||
c2a2ac2b XG |
167 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
168 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
169 | shadow_walk_okay(&(_walker)) && \ | |
170 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
171 | __shadow_walk_next(&(_walker), spte)) | |
172 | ||
53c07b18 | 173 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 174 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 175 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 176 | |
ce88decf | 177 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
178 | static union kvm_mmu_page_role |
179 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 180 | |
594e91a1 SC |
181 | struct kvm_mmu_role_regs { |
182 | const unsigned long cr0; | |
183 | const unsigned long cr4; | |
184 | const u64 efer; | |
185 | }; | |
186 | ||
335e192a PB |
187 | #define CREATE_TRACE_POINTS |
188 | #include "mmutrace.h" | |
189 | ||
594e91a1 SC |
190 | /* |
191 | * Yes, lot's of underscores. They're a hint that you probably shouldn't be | |
192 | * reading from the role_regs. Once the mmu_role is constructed, it becomes | |
193 | * the single source of truth for the MMU's state. | |
194 | */ | |
195 | #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \ | |
196 | static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\ | |
197 | { \ | |
198 | return !!(regs->reg & flag); \ | |
199 | } | |
200 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG); | |
201 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP); | |
202 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE); | |
203 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE); | |
204 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP); | |
205 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP); | |
206 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE); | |
207 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57); | |
208 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX); | |
209 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA); | |
210 | ||
60667724 SC |
211 | /* |
212 | * The MMU itself (with a valid role) is the single source of truth for the | |
213 | * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The | |
214 | * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1, | |
215 | * and the vCPU may be incorrect/irrelevant. | |
216 | */ | |
217 | #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \ | |
218 | static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \ | |
219 | { \ | |
220 | return !!(mmu->mmu_role. base_or_ext . reg##_##name); \ | |
221 | } | |
222 | BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg); | |
223 | BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp); | |
224 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse); | |
225 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae); | |
226 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep); | |
227 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap); | |
228 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke); | |
229 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57); | |
230 | BUILD_MMU_ROLE_ACCESSOR(base, efer, nx); | |
231 | ||
594e91a1 SC |
232 | static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu) |
233 | { | |
234 | struct kvm_mmu_role_regs regs = { | |
235 | .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS), | |
236 | .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS), | |
237 | .efer = vcpu->arch.efer, | |
238 | }; | |
239 | ||
240 | return regs; | |
241 | } | |
40ef75a7 | 242 | |
f4bd6f73 SC |
243 | static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs) |
244 | { | |
245 | if (!____is_cr0_pg(regs)) | |
246 | return 0; | |
247 | else if (____is_efer_lma(regs)) | |
248 | return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL : | |
249 | PT64_ROOT_4LEVEL; | |
250 | else if (____is_cr4_pae(regs)) | |
251 | return PT32E_ROOT_LEVEL; | |
252 | else | |
253 | return PT32_ROOT_LEVEL; | |
254 | } | |
40ef75a7 LT |
255 | |
256 | static inline bool kvm_available_flush_tlb_with_range(void) | |
257 | { | |
afaf0b2f | 258 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
259 | } |
260 | ||
261 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
262 | struct kvm_tlb_range *range) | |
263 | { | |
264 | int ret = -ENOTSUPP; | |
265 | ||
afaf0b2f | 266 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
b3646477 | 267 | ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range); |
40ef75a7 LT |
268 | |
269 | if (ret) | |
270 | kvm_flush_remote_tlbs(kvm); | |
271 | } | |
272 | ||
2f2fad08 | 273 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
274 | u64 start_gfn, u64 pages) |
275 | { | |
276 | struct kvm_tlb_range range; | |
277 | ||
278 | range.start_gfn = start_gfn; | |
279 | range.pages = pages; | |
280 | ||
281 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
282 | } | |
283 | ||
8f79b064 BG |
284 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
285 | unsigned int access) | |
286 | { | |
c236d962 | 287 | u64 spte = make_mmio_spte(vcpu, gfn, access); |
8f79b064 | 288 | |
c236d962 SC |
289 | trace_mark_mmio_spte(sptep, gfn, spte); |
290 | mmu_spte_set(sptep, spte); | |
ce88decf XG |
291 | } |
292 | ||
ce88decf XG |
293 | static gfn_t get_mmio_spte_gfn(u64 spte) |
294 | { | |
daa07cbc | 295 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 296 | |
8a967d65 | 297 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
298 | & shadow_nonpresent_or_rsvd_mask; |
299 | ||
300 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
301 | } |
302 | ||
303 | static unsigned get_mmio_spte_access(u64 spte) | |
304 | { | |
4af77151 | 305 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
306 | } |
307 | ||
54bf36aa | 308 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 309 | { |
cae7ed3c | 310 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 311 | |
cae7ed3c SC |
312 | gen = kvm_vcpu_memslots(vcpu)->generation; |
313 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
314 | return false; | |
089504c0 | 315 | |
cae7ed3c | 316 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
317 | spte_gen = get_mmio_spte_generation(spte); |
318 | ||
319 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
320 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
321 | } |
322 | ||
cd313569 MG |
323 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
324 | struct x86_exception *exception) | |
325 | { | |
ec7771ab | 326 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 327 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
328 | exception->error_code |= PFERR_RSVD_MASK; |
329 | return UNMAPPED_GVA; | |
330 | } | |
331 | ||
cd313569 MG |
332 | return gpa; |
333 | } | |
334 | ||
6aa8b732 AK |
335 | static int is_cpuid_PSE36(void) |
336 | { | |
337 | return 1; | |
338 | } | |
339 | ||
da928521 AK |
340 | static gfn_t pse36_gfn_delta(u32 gpte) |
341 | { | |
342 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
343 | ||
344 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
345 | } | |
346 | ||
603e0651 | 347 | #ifdef CONFIG_X86_64 |
d555c333 | 348 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 349 | { |
b19ee2ff | 350 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
351 | } |
352 | ||
603e0651 | 353 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 354 | { |
b19ee2ff | 355 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
356 | } |
357 | ||
358 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
359 | { | |
360 | return xchg(sptep, spte); | |
361 | } | |
c2a2ac2b XG |
362 | |
363 | static u64 __get_spte_lockless(u64 *sptep) | |
364 | { | |
6aa7de05 | 365 | return READ_ONCE(*sptep); |
c2a2ac2b | 366 | } |
a9221dd5 | 367 | #else |
603e0651 XG |
368 | union split_spte { |
369 | struct { | |
370 | u32 spte_low; | |
371 | u32 spte_high; | |
372 | }; | |
373 | u64 spte; | |
374 | }; | |
a9221dd5 | 375 | |
c2a2ac2b XG |
376 | static void count_spte_clear(u64 *sptep, u64 spte) |
377 | { | |
57354682 | 378 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
379 | |
380 | if (is_shadow_present_pte(spte)) | |
381 | return; | |
382 | ||
383 | /* Ensure the spte is completely set before we increase the count */ | |
384 | smp_wmb(); | |
385 | sp->clear_spte_count++; | |
386 | } | |
387 | ||
603e0651 XG |
388 | static void __set_spte(u64 *sptep, u64 spte) |
389 | { | |
390 | union split_spte *ssptep, sspte; | |
a9221dd5 | 391 | |
603e0651 XG |
392 | ssptep = (union split_spte *)sptep; |
393 | sspte = (union split_spte)spte; | |
394 | ||
395 | ssptep->spte_high = sspte.spte_high; | |
396 | ||
397 | /* | |
398 | * If we map the spte from nonpresent to present, We should store | |
399 | * the high bits firstly, then set present bit, so cpu can not | |
400 | * fetch this spte while we are setting the spte. | |
401 | */ | |
402 | smp_wmb(); | |
403 | ||
b19ee2ff | 404 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
405 | } |
406 | ||
603e0651 XG |
407 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
408 | { | |
409 | union split_spte *ssptep, sspte; | |
410 | ||
411 | ssptep = (union split_spte *)sptep; | |
412 | sspte = (union split_spte)spte; | |
413 | ||
b19ee2ff | 414 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
415 | |
416 | /* | |
417 | * If we map the spte from present to nonpresent, we should clear | |
418 | * present bit firstly to avoid vcpu fetch the old high bits. | |
419 | */ | |
420 | smp_wmb(); | |
421 | ||
422 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 423 | count_spte_clear(sptep, spte); |
603e0651 XG |
424 | } |
425 | ||
426 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
427 | { | |
428 | union split_spte *ssptep, sspte, orig; | |
429 | ||
430 | ssptep = (union split_spte *)sptep; | |
431 | sspte = (union split_spte)spte; | |
432 | ||
433 | /* xchg acts as a barrier before the setting of the high bits */ | |
434 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
435 | orig.spte_high = ssptep->spte_high; |
436 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 437 | count_spte_clear(sptep, spte); |
603e0651 XG |
438 | |
439 | return orig.spte; | |
440 | } | |
c2a2ac2b XG |
441 | |
442 | /* | |
443 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 444 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
445 | * |
446 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
447 | * coalesces them and we are running out of the MMU lock. Therefore | |
448 | * we need to protect against in-progress updates of the spte. | |
449 | * | |
450 | * Reading the spte while an update is in progress may get the old value | |
451 | * for the high part of the spte. The race is fine for a present->non-present | |
452 | * change (because the high part of the spte is ignored for non-present spte), | |
453 | * but for a present->present change we must reread the spte. | |
454 | * | |
455 | * All such changes are done in two steps (present->non-present and | |
456 | * non-present->present), hence it is enough to count the number of | |
457 | * present->non-present updates: if it changed while reading the spte, | |
458 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
459 | */ |
460 | static u64 __get_spte_lockless(u64 *sptep) | |
461 | { | |
57354682 | 462 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
463 | union split_spte spte, *orig = (union split_spte *)sptep; |
464 | int count; | |
465 | ||
466 | retry: | |
467 | count = sp->clear_spte_count; | |
468 | smp_rmb(); | |
469 | ||
470 | spte.spte_low = orig->spte_low; | |
471 | smp_rmb(); | |
472 | ||
473 | spte.spte_high = orig->spte_high; | |
474 | smp_rmb(); | |
475 | ||
476 | if (unlikely(spte.spte_low != orig->spte_low || | |
477 | count != sp->clear_spte_count)) | |
478 | goto retry; | |
479 | ||
480 | return spte.spte; | |
481 | } | |
603e0651 XG |
482 | #endif |
483 | ||
8672b721 XG |
484 | static bool spte_has_volatile_bits(u64 spte) |
485 | { | |
f160c7b7 JS |
486 | if (!is_shadow_present_pte(spte)) |
487 | return false; | |
488 | ||
c7ba5b48 | 489 | /* |
6a6256f9 | 490 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
491 | * out of mmu-lock, it can ensure dirty bit is not lost, |
492 | * also, it can help us to get a stable is_writable_pte() | |
493 | * to ensure tlb flush is not missed. | |
494 | */ | |
f160c7b7 JS |
495 | if (spte_can_locklessly_be_made_writable(spte) || |
496 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
497 | return true; |
498 | ||
ac8d57e5 | 499 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
500 | if ((spte & shadow_accessed_mask) == 0 || |
501 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
502 | return true; | |
503 | } | |
8672b721 | 504 | |
f160c7b7 | 505 | return false; |
8672b721 XG |
506 | } |
507 | ||
1df9f2dc XG |
508 | /* Rules for using mmu_spte_set: |
509 | * Set the sptep from nonpresent to present. | |
510 | * Note: the sptep being assigned *must* be either not present | |
511 | * or in a state where the hardware will not attempt to update | |
512 | * the spte. | |
513 | */ | |
514 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
515 | { | |
516 | WARN_ON(is_shadow_present_pte(*sptep)); | |
517 | __set_spte(sptep, new_spte); | |
518 | } | |
519 | ||
f39a058d JS |
520 | /* |
521 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
522 | * accessed/dirty status. | |
1df9f2dc | 523 | */ |
f39a058d | 524 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 525 | { |
c7ba5b48 | 526 | u64 old_spte = *sptep; |
4132779b | 527 | |
afd28fe1 | 528 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 529 | |
6e7d0354 XG |
530 | if (!is_shadow_present_pte(old_spte)) { |
531 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 532 | return old_spte; |
6e7d0354 | 533 | } |
4132779b | 534 | |
c7ba5b48 | 535 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 536 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 537 | else |
603e0651 | 538 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 539 | |
83ef6c81 JS |
540 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
541 | ||
f39a058d JS |
542 | return old_spte; |
543 | } | |
544 | ||
545 | /* Rules for using mmu_spte_update: | |
546 | * Update the state bits, it means the mapped pfn is not changed. | |
547 | * | |
548 | * Whenever we overwrite a writable spte with a read-only one we | |
549 | * should flush remote TLBs. Otherwise rmap_write_protect | |
550 | * will find a read-only spte, even though the writable spte | |
551 | * might be cached on a CPU's TLB, the return value indicates this | |
552 | * case. | |
553 | * | |
554 | * Returns true if the TLB needs to be flushed | |
555 | */ | |
556 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
557 | { | |
558 | bool flush = false; | |
559 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
560 | ||
561 | if (!is_shadow_present_pte(old_spte)) | |
562 | return false; | |
563 | ||
c7ba5b48 XG |
564 | /* |
565 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 566 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
567 | * spte_has_volatile_bits(). |
568 | */ | |
ea4114bc | 569 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 570 | !is_writable_pte(new_spte)) |
83ef6c81 | 571 | flush = true; |
4132779b | 572 | |
7e71a59b | 573 | /* |
83ef6c81 | 574 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
575 | * to guarantee consistency between TLB and page tables. |
576 | */ | |
7e71a59b | 577 | |
83ef6c81 JS |
578 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
579 | flush = true; | |
4132779b | 580 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
581 | } |
582 | ||
583 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
584 | flush = true; | |
4132779b | 585 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 586 | } |
6e7d0354 | 587 | |
83ef6c81 | 588 | return flush; |
b79b93f9 AK |
589 | } |
590 | ||
1df9f2dc XG |
591 | /* |
592 | * Rules for using mmu_spte_clear_track_bits: | |
593 | * It sets the sptep from present to nonpresent, and track the | |
594 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 595 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
596 | */ |
597 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
598 | { | |
ba049e93 | 599 | kvm_pfn_t pfn; |
1df9f2dc XG |
600 | u64 old_spte = *sptep; |
601 | ||
602 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 603 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 604 | else |
603e0651 | 605 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 606 | |
afd28fe1 | 607 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
608 | return 0; |
609 | ||
610 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
611 | |
612 | /* | |
613 | * KVM does not hold the refcount of the page used by | |
614 | * kvm mmu, before reclaiming the page, we should | |
615 | * unmap it from mmu first. | |
616 | */ | |
bf4bea8e | 617 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 618 | |
83ef6c81 | 619 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 620 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
621 | |
622 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 623 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 624 | |
1df9f2dc XG |
625 | return 1; |
626 | } | |
627 | ||
628 | /* | |
629 | * Rules for using mmu_spte_clear_no_track: | |
630 | * Directly clear spte without caring the state bits of sptep, | |
631 | * it is used to set the upper level spte. | |
632 | */ | |
633 | static void mmu_spte_clear_no_track(u64 *sptep) | |
634 | { | |
603e0651 | 635 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
636 | } |
637 | ||
c2a2ac2b XG |
638 | static u64 mmu_spte_get_lockless(u64 *sptep) |
639 | { | |
640 | return __get_spte_lockless(sptep); | |
641 | } | |
642 | ||
d3e328f2 JS |
643 | /* Restore an acc-track PTE back to a regular PTE */ |
644 | static u64 restore_acc_track_spte(u64 spte) | |
645 | { | |
646 | u64 new_spte = spte; | |
8a967d65 PB |
647 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
648 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 649 | |
ac8d57e5 | 650 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
651 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
652 | ||
653 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
654 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
655 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
656 | new_spte |= saved_bits; |
657 | ||
658 | return new_spte; | |
659 | } | |
660 | ||
f160c7b7 JS |
661 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
662 | static bool mmu_spte_age(u64 *sptep) | |
663 | { | |
664 | u64 spte = mmu_spte_get_lockless(sptep); | |
665 | ||
666 | if (!is_accessed_spte(spte)) | |
667 | return false; | |
668 | ||
ac8d57e5 | 669 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
670 | clear_bit((ffs(shadow_accessed_mask) - 1), |
671 | (unsigned long *)sptep); | |
672 | } else { | |
673 | /* | |
674 | * Capture the dirty status of the page, so that it doesn't get | |
675 | * lost when the SPTE is marked for access tracking. | |
676 | */ | |
677 | if (is_writable_pte(spte)) | |
678 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
679 | ||
680 | spte = mark_spte_for_access_track(spte); | |
681 | mmu_spte_update_no_track(sptep, spte); | |
682 | } | |
683 | ||
684 | return true; | |
685 | } | |
686 | ||
c2a2ac2b XG |
687 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
688 | { | |
c142786c AK |
689 | /* |
690 | * Prevent page table teardown by making any free-er wait during | |
691 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
692 | */ | |
693 | local_irq_disable(); | |
36ca7e0a | 694 | |
c142786c AK |
695 | /* |
696 | * Make sure a following spte read is not reordered ahead of the write | |
697 | * to vcpu->mode. | |
698 | */ | |
36ca7e0a | 699 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
700 | } |
701 | ||
702 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
703 | { | |
c142786c AK |
704 | /* |
705 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 706 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
707 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
708 | */ | |
36ca7e0a | 709 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 710 | local_irq_enable(); |
c2a2ac2b XG |
711 | } |
712 | ||
378f5cd6 | 713 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 714 | { |
e2dec939 AK |
715 | int r; |
716 | ||
531281ad | 717 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
718 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
719 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 720 | if (r) |
284aa868 | 721 | return r; |
94ce87ef SC |
722 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
723 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 724 | if (r) |
171a90d7 | 725 | return r; |
378f5cd6 | 726 | if (maybe_indirect) { |
94ce87ef SC |
727 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
728 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
729 | if (r) |
730 | return r; | |
731 | } | |
94ce87ef SC |
732 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
733 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
734 | } |
735 | ||
736 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
737 | { | |
94ce87ef SC |
738 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
739 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
740 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
741 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
742 | } |
743 | ||
53c07b18 | 744 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 745 | { |
94ce87ef | 746 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
747 | } |
748 | ||
53c07b18 | 749 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 750 | { |
53c07b18 | 751 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
752 | } |
753 | ||
2032a93d LJ |
754 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
755 | { | |
756 | if (!sp->role.direct) | |
757 | return sp->gfns[index]; | |
758 | ||
759 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
760 | } | |
761 | ||
762 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
763 | { | |
e9f2a760 | 764 | if (!sp->role.direct) { |
2032a93d | 765 | sp->gfns[index] = gfn; |
e9f2a760 PB |
766 | return; |
767 | } | |
768 | ||
769 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
770 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
771 | "(expected %llx, got %llx)\n", | |
772 | sp->gfn, | |
773 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
774 | } |
775 | ||
05da4558 | 776 | /* |
d4dbf470 TY |
777 | * Return the pointer to the large page information for a given gfn, |
778 | * handling slots that are not large page aligned. | |
05da4558 | 779 | */ |
d4dbf470 | 780 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
8ca6f063 | 781 | const struct kvm_memory_slot *slot, int level) |
05da4558 MT |
782 | { |
783 | unsigned long idx; | |
784 | ||
fb03cb6f | 785 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 786 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
787 | } |
788 | ||
547ffaed XG |
789 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
790 | gfn_t gfn, int count) | |
791 | { | |
792 | struct kvm_lpage_info *linfo; | |
793 | int i; | |
794 | ||
3bae0459 | 795 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
796 | linfo = lpage_info_slot(gfn, slot, i); |
797 | linfo->disallow_lpage += count; | |
798 | WARN_ON(linfo->disallow_lpage < 0); | |
799 | } | |
800 | } | |
801 | ||
802 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
803 | { | |
804 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
805 | } | |
806 | ||
807 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
808 | { | |
809 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
810 | } | |
811 | ||
3ed1a478 | 812 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 813 | { |
699023e2 | 814 | struct kvm_memslots *slots; |
d25797b2 | 815 | struct kvm_memory_slot *slot; |
3ed1a478 | 816 | gfn_t gfn; |
05da4558 | 817 | |
56ca57f9 | 818 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 819 | gfn = sp->gfn; |
699023e2 PB |
820 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
821 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
822 | |
823 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 824 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
825 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
826 | KVM_PAGE_TRACK_WRITE); | |
827 | ||
547ffaed | 828 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
829 | } |
830 | ||
29cf0f50 | 831 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
832 | { |
833 | if (sp->lpage_disallowed) | |
834 | return; | |
835 | ||
836 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
837 | list_add_tail(&sp->lpage_disallowed_link, |
838 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
839 | sp->lpage_disallowed = true; |
840 | } | |
841 | ||
3ed1a478 | 842 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 843 | { |
699023e2 | 844 | struct kvm_memslots *slots; |
d25797b2 | 845 | struct kvm_memory_slot *slot; |
3ed1a478 | 846 | gfn_t gfn; |
05da4558 | 847 | |
56ca57f9 | 848 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 849 | gfn = sp->gfn; |
699023e2 PB |
850 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
851 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 852 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
853 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
854 | KVM_PAGE_TRACK_WRITE); | |
855 | ||
547ffaed | 856 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
857 | } |
858 | ||
29cf0f50 | 859 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
860 | { |
861 | --kvm->stat.nx_lpage_splits; | |
862 | sp->lpage_disallowed = false; | |
1aa9b957 | 863 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
864 | } |
865 | ||
5d163b1c XG |
866 | static struct kvm_memory_slot * |
867 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
868 | bool no_dirty_log) | |
05da4558 MT |
869 | { |
870 | struct kvm_memory_slot *slot; | |
5d163b1c | 871 | |
54bf36aa | 872 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
873 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
874 | return NULL; | |
044c59c4 | 875 | if (no_dirty_log && kvm_slot_dirty_track_enabled(slot)) |
91b0d268 | 876 | return NULL; |
5d163b1c XG |
877 | |
878 | return slot; | |
879 | } | |
880 | ||
290fc38d | 881 | /* |
018aabb5 | 882 | * About rmap_head encoding: |
cd4a4e53 | 883 | * |
018aabb5 TY |
884 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
885 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 886 | * pte_list_desc containing more mappings. |
018aabb5 TY |
887 | */ |
888 | ||
889 | /* | |
890 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 891 | */ |
53c07b18 | 892 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 893 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 894 | { |
53c07b18 | 895 | struct pte_list_desc *desc; |
53a27b39 | 896 | int i, count = 0; |
cd4a4e53 | 897 | |
018aabb5 | 898 | if (!rmap_head->val) { |
805a0f83 | 899 | rmap_printk("%p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
900 | rmap_head->val = (unsigned long)spte; |
901 | } else if (!(rmap_head->val & 1)) { | |
805a0f83 | 902 | rmap_printk("%p %llx 1->many\n", spte, *spte); |
53c07b18 | 903 | desc = mmu_alloc_pte_list_desc(vcpu); |
018aabb5 | 904 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 905 | desc->sptes[1] = spte; |
018aabb5 | 906 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 907 | ++count; |
cd4a4e53 | 908 | } else { |
805a0f83 | 909 | rmap_printk("%p %llx many->many\n", spte, *spte); |
018aabb5 | 910 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
c6c4f961 | 911 | while (desc->sptes[PTE_LIST_EXT-1]) { |
53c07b18 | 912 | count += PTE_LIST_EXT; |
c6c4f961 LR |
913 | |
914 | if (!desc->more) { | |
915 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
916 | desc = desc->more; | |
917 | break; | |
918 | } | |
cd4a4e53 AK |
919 | desc = desc->more; |
920 | } | |
d555c333 | 921 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 922 | ++count; |
d555c333 | 923 | desc->sptes[i] = spte; |
cd4a4e53 | 924 | } |
53a27b39 | 925 | return count; |
cd4a4e53 AK |
926 | } |
927 | ||
53c07b18 | 928 | static void |
018aabb5 TY |
929 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
930 | struct pte_list_desc *desc, int i, | |
931 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
932 | { |
933 | int j; | |
934 | ||
53c07b18 | 935 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 936 | ; |
d555c333 AK |
937 | desc->sptes[i] = desc->sptes[j]; |
938 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
939 | if (j != 0) |
940 | return; | |
941 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 942 | rmap_head->val = 0; |
cd4a4e53 AK |
943 | else |
944 | if (prev_desc) | |
945 | prev_desc->more = desc->more; | |
946 | else | |
018aabb5 | 947 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 948 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
949 | } |
950 | ||
8daf3462 | 951 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 952 | { |
53c07b18 XG |
953 | struct pte_list_desc *desc; |
954 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
955 | int i; |
956 | ||
018aabb5 | 957 | if (!rmap_head->val) { |
8daf3462 | 958 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 959 | BUG(); |
018aabb5 | 960 | } else if (!(rmap_head->val & 1)) { |
805a0f83 | 961 | rmap_printk("%p 1->0\n", spte); |
018aabb5 | 962 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 963 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
964 | BUG(); |
965 | } | |
018aabb5 | 966 | rmap_head->val = 0; |
cd4a4e53 | 967 | } else { |
805a0f83 | 968 | rmap_printk("%p many->many\n", spte); |
018aabb5 | 969 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
970 | prev_desc = NULL; |
971 | while (desc) { | |
018aabb5 | 972 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 973 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
974 | pte_list_desc_remove_entry(rmap_head, |
975 | desc, i, prev_desc); | |
cd4a4e53 AK |
976 | return; |
977 | } | |
018aabb5 | 978 | } |
cd4a4e53 AK |
979 | prev_desc = desc; |
980 | desc = desc->more; | |
981 | } | |
8daf3462 | 982 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
983 | BUG(); |
984 | } | |
985 | } | |
986 | ||
e7912386 WY |
987 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
988 | { | |
989 | mmu_spte_clear_track_bits(sptep); | |
990 | __pte_list_remove(sptep, rmap_head); | |
991 | } | |
992 | ||
018aabb5 TY |
993 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
994 | struct kvm_memory_slot *slot) | |
53c07b18 | 995 | { |
77d11309 | 996 | unsigned long idx; |
53c07b18 | 997 | |
77d11309 | 998 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 999 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
1000 | } |
1001 | ||
018aabb5 TY |
1002 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1003 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1004 | { |
699023e2 | 1005 | struct kvm_memslots *slots; |
9b9b1492 TY |
1006 | struct kvm_memory_slot *slot; |
1007 | ||
699023e2 PB |
1008 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1009 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1010 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1011 | } |
1012 | ||
f759e2b4 XG |
1013 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1014 | { | |
356ec69a | 1015 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 1016 | |
356ec69a | 1017 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 1018 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
1019 | } |
1020 | ||
53c07b18 XG |
1021 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1022 | { | |
1023 | struct kvm_mmu_page *sp; | |
018aabb5 | 1024 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1025 | |
57354682 | 1026 | sp = sptep_to_sp(spte); |
53c07b18 | 1027 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
1028 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1029 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1030 | } |
1031 | ||
53c07b18 XG |
1032 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1033 | { | |
1034 | struct kvm_mmu_page *sp; | |
1035 | gfn_t gfn; | |
018aabb5 | 1036 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1037 | |
57354682 | 1038 | sp = sptep_to_sp(spte); |
53c07b18 | 1039 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 1040 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1041 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1042 | } |
1043 | ||
1e3f42f0 TY |
1044 | /* |
1045 | * Used by the following functions to iterate through the sptes linked by a | |
1046 | * rmap. All fields are private and not assumed to be used outside. | |
1047 | */ | |
1048 | struct rmap_iterator { | |
1049 | /* private fields */ | |
1050 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1051 | int pos; /* index of the sptep */ | |
1052 | }; | |
1053 | ||
1054 | /* | |
1055 | * Iteration must be started by this function. This should also be used after | |
1056 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1057 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1058 | * |
1059 | * Returns sptep if found, NULL otherwise. | |
1060 | */ | |
018aabb5 TY |
1061 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1062 | struct rmap_iterator *iter) | |
1e3f42f0 | 1063 | { |
77fbbbd2 TY |
1064 | u64 *sptep; |
1065 | ||
018aabb5 | 1066 | if (!rmap_head->val) |
1e3f42f0 TY |
1067 | return NULL; |
1068 | ||
018aabb5 | 1069 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1070 | iter->desc = NULL; |
77fbbbd2 TY |
1071 | sptep = (u64 *)rmap_head->val; |
1072 | goto out; | |
1e3f42f0 TY |
1073 | } |
1074 | ||
018aabb5 | 1075 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1076 | iter->pos = 0; |
77fbbbd2 TY |
1077 | sptep = iter->desc->sptes[iter->pos]; |
1078 | out: | |
1079 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1080 | return sptep; | |
1e3f42f0 TY |
1081 | } |
1082 | ||
1083 | /* | |
1084 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1085 | * | |
1086 | * Returns sptep if found, NULL otherwise. | |
1087 | */ | |
1088 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1089 | { | |
77fbbbd2 TY |
1090 | u64 *sptep; |
1091 | ||
1e3f42f0 TY |
1092 | if (iter->desc) { |
1093 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1094 | ++iter->pos; |
1095 | sptep = iter->desc->sptes[iter->pos]; | |
1096 | if (sptep) | |
77fbbbd2 | 1097 | goto out; |
1e3f42f0 TY |
1098 | } |
1099 | ||
1100 | iter->desc = iter->desc->more; | |
1101 | ||
1102 | if (iter->desc) { | |
1103 | iter->pos = 0; | |
1104 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1105 | sptep = iter->desc->sptes[iter->pos]; |
1106 | goto out; | |
1e3f42f0 TY |
1107 | } |
1108 | } | |
1109 | ||
1110 | return NULL; | |
77fbbbd2 TY |
1111 | out: |
1112 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1113 | return sptep; | |
1e3f42f0 TY |
1114 | } |
1115 | ||
018aabb5 TY |
1116 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1117 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1118 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1119 | |
c3707958 | 1120 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1121 | { |
1df9f2dc | 1122 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1123 | rmap_remove(kvm, sptep); |
be38d276 AK |
1124 | } |
1125 | ||
8e22f955 XG |
1126 | |
1127 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1128 | { | |
1129 | if (is_large_pte(*sptep)) { | |
57354682 | 1130 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1131 | drop_spte(kvm, sptep); |
1132 | --kvm->stat.lpages; | |
1133 | return true; | |
1134 | } | |
1135 | ||
1136 | return false; | |
1137 | } | |
1138 | ||
1139 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1140 | { | |
c3134ce2 | 1141 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1142 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1143 | |
1144 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1145 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1146 | } | |
8e22f955 XG |
1147 | } |
1148 | ||
1149 | /* | |
49fde340 | 1150 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1151 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1152 | * |
b4619660 | 1153 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1154 | * protection: |
1155 | * - for dirty logging, the spte can be set to writable at anytime if | |
1156 | * its dirty bitmap is properly set. | |
1157 | * - for spte protection, the spte can be writable only after unsync-ing | |
1158 | * shadow page. | |
8e22f955 | 1159 | * |
c126d94f | 1160 | * Return true if tlb need be flushed. |
8e22f955 | 1161 | */ |
c4f138b4 | 1162 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1163 | { |
1164 | u64 spte = *sptep; | |
1165 | ||
49fde340 | 1166 | if (!is_writable_pte(spte) && |
ea4114bc | 1167 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1168 | return false; |
1169 | ||
805a0f83 | 1170 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
d13bc5b5 | 1171 | |
49fde340 | 1172 | if (pt_protect) |
5fc3424f | 1173 | spte &= ~shadow_mmu_writable_mask; |
d13bc5b5 | 1174 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1175 | |
c126d94f | 1176 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1177 | } |
1178 | ||
018aabb5 TY |
1179 | static bool __rmap_write_protect(struct kvm *kvm, |
1180 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1181 | bool pt_protect) |
98348e95 | 1182 | { |
1e3f42f0 TY |
1183 | u64 *sptep; |
1184 | struct rmap_iterator iter; | |
d13bc5b5 | 1185 | bool flush = false; |
374cbac0 | 1186 | |
018aabb5 | 1187 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1188 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1189 | |
d13bc5b5 | 1190 | return flush; |
a0ed4607 TY |
1191 | } |
1192 | ||
c4f138b4 | 1193 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1194 | { |
1195 | u64 spte = *sptep; | |
1196 | ||
805a0f83 | 1197 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
f4b4b180 | 1198 | |
1f4e5fc8 | 1199 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1200 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1201 | return mmu_spte_update(sptep, spte); |
1202 | } | |
1203 | ||
1f4e5fc8 | 1204 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1205 | { |
1206 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1207 | (unsigned long *)sptep); | |
1f4e5fc8 | 1208 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1209 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1210 | ||
1211 | return was_writable; | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1216 | * - D bit on ad-enabled SPTEs, and | |
1217 | * - W bit on ad-disabled SPTEs. | |
1218 | * Returns true iff any D or W bits were cleared. | |
1219 | */ | |
0a234f5d SC |
1220 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1221 | struct kvm_memory_slot *slot) | |
f4b4b180 KH |
1222 | { |
1223 | u64 *sptep; | |
1224 | struct rmap_iterator iter; | |
1225 | bool flush = false; | |
1226 | ||
018aabb5 | 1227 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1228 | if (spte_ad_need_write_protect(*sptep)) |
1229 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1230 | else |
1f4e5fc8 | 1231 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1232 | |
1233 | return flush; | |
1234 | } | |
1235 | ||
5dc99b23 | 1236 | /** |
3b0f1d01 | 1237 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1238 | * @kvm: kvm instance |
1239 | * @slot: slot to protect | |
1240 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1241 | * @mask: indicates which pages we should protect | |
1242 | * | |
89212919 | 1243 | * Used when we do not need to care about huge page mappings. |
5dc99b23 | 1244 | */ |
3b0f1d01 | 1245 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1246 | struct kvm_memory_slot *slot, |
1247 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1248 | { |
018aabb5 | 1249 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1250 | |
897218ff | 1251 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1252 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1253 | slot->base_gfn + gfn_offset, mask, true); | |
e2209710 BG |
1254 | |
1255 | if (!kvm_memslots_have_rmaps(kvm)) | |
1256 | return; | |
1257 | ||
5dc99b23 | 1258 | while (mask) { |
018aabb5 | 1259 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1260 | PG_LEVEL_4K, slot); |
018aabb5 | 1261 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1262 | |
5dc99b23 TY |
1263 | /* clear the first set bit */ |
1264 | mask &= mask - 1; | |
1265 | } | |
374cbac0 AK |
1266 | } |
1267 | ||
f4b4b180 | 1268 | /** |
ac8d57e5 PF |
1269 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1270 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1271 | * @kvm: kvm instance |
1272 | * @slot: slot to clear D-bit | |
1273 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1274 | * @mask: indicates which pages we should clear D-bit | |
1275 | * | |
1276 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1277 | */ | |
a018eba5 SC |
1278 | static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, |
1279 | struct kvm_memory_slot *slot, | |
1280 | gfn_t gfn_offset, unsigned long mask) | |
f4b4b180 | 1281 | { |
018aabb5 | 1282 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1283 | |
897218ff | 1284 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1285 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1286 | slot->base_gfn + gfn_offset, mask, false); | |
e2209710 BG |
1287 | |
1288 | if (!kvm_memslots_have_rmaps(kvm)) | |
1289 | return; | |
1290 | ||
f4b4b180 | 1291 | while (mask) { |
018aabb5 | 1292 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1293 | PG_LEVEL_4K, slot); |
0a234f5d | 1294 | __rmap_clear_dirty(kvm, rmap_head, slot); |
f4b4b180 KH |
1295 | |
1296 | /* clear the first set bit */ | |
1297 | mask &= mask - 1; | |
1298 | } | |
1299 | } | |
f4b4b180 | 1300 | |
3b0f1d01 KH |
1301 | /** |
1302 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1303 | * PT level pages. | |
1304 | * | |
1305 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1306 | * enable dirty logging for them. | |
1307 | * | |
89212919 KZ |
1308 | * We need to care about huge page mappings: e.g. during dirty logging we may |
1309 | * have such mappings. | |
3b0f1d01 KH |
1310 | */ |
1311 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1312 | struct kvm_memory_slot *slot, | |
1313 | gfn_t gfn_offset, unsigned long mask) | |
1314 | { | |
89212919 KZ |
1315 | /* |
1316 | * Huge pages are NOT write protected when we start dirty logging in | |
1317 | * initially-all-set mode; must write protect them here so that they | |
1318 | * are split to 4K on the first write. | |
1319 | * | |
1320 | * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn | |
1321 | * of memslot has no such restriction, so the range can cross two large | |
1322 | * pages. | |
1323 | */ | |
1324 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
1325 | gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask); | |
1326 | gfn_t end = slot->base_gfn + gfn_offset + __fls(mask); | |
1327 | ||
1328 | kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M); | |
1329 | ||
1330 | /* Cross two large pages? */ | |
1331 | if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) != | |
1332 | ALIGN(end << PAGE_SHIFT, PMD_SIZE)) | |
1333 | kvm_mmu_slot_gfn_write_protect(kvm, slot, end, | |
1334 | PG_LEVEL_2M); | |
1335 | } | |
1336 | ||
1337 | /* Now handle 4K PTEs. */ | |
a018eba5 SC |
1338 | if (kvm_x86_ops.cpu_dirty_log_size) |
1339 | kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask); | |
88178fd4 KH |
1340 | else |
1341 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1342 | } |
1343 | ||
fb04a1ed PX |
1344 | int kvm_cpu_dirty_log_size(void) |
1345 | { | |
6dd03800 | 1346 | return kvm_x86_ops.cpu_dirty_log_size; |
fb04a1ed PX |
1347 | } |
1348 | ||
aeecee2e | 1349 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
3ad93562 KZ |
1350 | struct kvm_memory_slot *slot, u64 gfn, |
1351 | int min_level) | |
95d4c16c | 1352 | { |
018aabb5 | 1353 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1354 | int i; |
2f84569f | 1355 | bool write_protected = false; |
95d4c16c | 1356 | |
e2209710 BG |
1357 | if (kvm_memslots_have_rmaps(kvm)) { |
1358 | for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { | |
1359 | rmap_head = __gfn_to_rmap(gfn, i, slot); | |
1360 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); | |
1361 | } | |
5dc99b23 TY |
1362 | } |
1363 | ||
897218ff | 1364 | if (is_tdp_mmu_enabled(kvm)) |
46044f72 | 1365 | write_protected |= |
3ad93562 | 1366 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level); |
46044f72 | 1367 | |
5dc99b23 | 1368 | return write_protected; |
95d4c16c TY |
1369 | } |
1370 | ||
aeecee2e XG |
1371 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1372 | { | |
1373 | struct kvm_memory_slot *slot; | |
1374 | ||
1375 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
3ad93562 | 1376 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K); |
aeecee2e XG |
1377 | } |
1378 | ||
0a234f5d SC |
1379 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1380 | struct kvm_memory_slot *slot) | |
e930bffe | 1381 | { |
1e3f42f0 TY |
1382 | u64 *sptep; |
1383 | struct rmap_iterator iter; | |
6a49f85c | 1384 | bool flush = false; |
e930bffe | 1385 | |
018aabb5 | 1386 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
805a0f83 | 1387 | rmap_printk("spte %p %llx.\n", sptep, *sptep); |
1e3f42f0 | 1388 | |
e7912386 | 1389 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1390 | flush = true; |
e930bffe | 1391 | } |
1e3f42f0 | 1392 | |
6a49f85c XG |
1393 | return flush; |
1394 | } | |
1395 | ||
3039bcc7 SC |
1396 | static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1397 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1398 | pte_t unused) | |
6a49f85c | 1399 | { |
0a234f5d | 1400 | return kvm_zap_rmapp(kvm, rmap_head, slot); |
e930bffe AA |
1401 | } |
1402 | ||
3039bcc7 SC |
1403 | static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1404 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1405 | pte_t pte) | |
3da0dd43 | 1406 | { |
1e3f42f0 TY |
1407 | u64 *sptep; |
1408 | struct rmap_iterator iter; | |
3da0dd43 | 1409 | int need_flush = 0; |
1e3f42f0 | 1410 | u64 new_spte; |
ba049e93 | 1411 | kvm_pfn_t new_pfn; |
3da0dd43 | 1412 | |
3039bcc7 SC |
1413 | WARN_ON(pte_huge(pte)); |
1414 | new_pfn = pte_pfn(pte); | |
1e3f42f0 | 1415 | |
0d536790 | 1416 | restart: |
018aabb5 | 1417 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
805a0f83 | 1418 | rmap_printk("spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1419 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1420 | |
3da0dd43 | 1421 | need_flush = 1; |
1e3f42f0 | 1422 | |
3039bcc7 | 1423 | if (pte_write(pte)) { |
e7912386 | 1424 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1425 | goto restart; |
3da0dd43 | 1426 | } else { |
cb3eedab PB |
1427 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1428 | *sptep, new_pfn); | |
1e3f42f0 TY |
1429 | |
1430 | mmu_spte_clear_track_bits(sptep); | |
1431 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1432 | } |
1433 | } | |
1e3f42f0 | 1434 | |
3cc5ea94 LT |
1435 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1436 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1437 | return 0; | |
1438 | } | |
1439 | ||
0cf853c5 | 1440 | return need_flush; |
3da0dd43 IE |
1441 | } |
1442 | ||
6ce1f4e2 XG |
1443 | struct slot_rmap_walk_iterator { |
1444 | /* input fields. */ | |
1445 | struct kvm_memory_slot *slot; | |
1446 | gfn_t start_gfn; | |
1447 | gfn_t end_gfn; | |
1448 | int start_level; | |
1449 | int end_level; | |
1450 | ||
1451 | /* output fields. */ | |
1452 | gfn_t gfn; | |
018aabb5 | 1453 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1454 | int level; |
1455 | ||
1456 | /* private field. */ | |
018aabb5 | 1457 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1458 | }; |
1459 | ||
1460 | static void | |
1461 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1462 | { | |
1463 | iterator->level = level; | |
1464 | iterator->gfn = iterator->start_gfn; | |
1465 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1466 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1467 | iterator->slot); | |
1468 | } | |
1469 | ||
1470 | static void | |
1471 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1472 | struct kvm_memory_slot *slot, int start_level, | |
1473 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1474 | { | |
1475 | iterator->slot = slot; | |
1476 | iterator->start_level = start_level; | |
1477 | iterator->end_level = end_level; | |
1478 | iterator->start_gfn = start_gfn; | |
1479 | iterator->end_gfn = end_gfn; | |
1480 | ||
1481 | rmap_walk_init_level(iterator, iterator->start_level); | |
1482 | } | |
1483 | ||
1484 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1485 | { | |
1486 | return !!iterator->rmap; | |
1487 | } | |
1488 | ||
1489 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1490 | { | |
1491 | if (++iterator->rmap <= iterator->end_rmap) { | |
1492 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1493 | return; | |
1494 | } | |
1495 | ||
1496 | if (++iterator->level > iterator->end_level) { | |
1497 | iterator->rmap = NULL; | |
1498 | return; | |
1499 | } | |
1500 | ||
1501 | rmap_walk_init_level(iterator, iterator->level); | |
1502 | } | |
1503 | ||
1504 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1505 | _start_gfn, _end_gfn, _iter_) \ | |
1506 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1507 | _end_level_, _start_gfn, _end_gfn); \ | |
1508 | slot_rmap_walk_okay(_iter_); \ | |
1509 | slot_rmap_walk_next(_iter_)) | |
1510 | ||
3039bcc7 SC |
1511 | typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1512 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1513 | int level, pte_t pte); | |
c1b91493 | 1514 | |
3039bcc7 SC |
1515 | static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm, |
1516 | struct kvm_gfn_range *range, | |
1517 | rmap_handler_t handler) | |
e930bffe | 1518 | { |
6ce1f4e2 | 1519 | struct slot_rmap_walk_iterator iterator; |
3039bcc7 | 1520 | bool ret = false; |
e930bffe | 1521 | |
3039bcc7 SC |
1522 | for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL, |
1523 | range->start, range->end - 1, &iterator) | |
1524 | ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn, | |
1525 | iterator.level, range->pte); | |
e930bffe | 1526 | |
f395302e | 1527 | return ret; |
e930bffe AA |
1528 | } |
1529 | ||
3039bcc7 | 1530 | bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) |
84504ef3 | 1531 | { |
e2209710 | 1532 | bool flush = false; |
063afacd | 1533 | |
e2209710 BG |
1534 | if (kvm_memslots_have_rmaps(kvm)) |
1535 | flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp); | |
063afacd | 1536 | |
897218ff | 1537 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1538 | flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush); |
063afacd | 1539 | |
3039bcc7 | 1540 | return flush; |
b3ae2096 TY |
1541 | } |
1542 | ||
3039bcc7 | 1543 | bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
3da0dd43 | 1544 | { |
e2209710 | 1545 | bool flush = false; |
1d8dd6b3 | 1546 | |
e2209710 BG |
1547 | if (kvm_memslots_have_rmaps(kvm)) |
1548 | flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp); | |
1d8dd6b3 | 1549 | |
897218ff | 1550 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1551 | flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range); |
1d8dd6b3 | 1552 | |
3039bcc7 | 1553 | return flush; |
e930bffe AA |
1554 | } |
1555 | ||
3039bcc7 SC |
1556 | static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1557 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1558 | pte_t unused) | |
e930bffe | 1559 | { |
1e3f42f0 | 1560 | u64 *sptep; |
3f649ab7 | 1561 | struct rmap_iterator iter; |
e930bffe AA |
1562 | int young = 0; |
1563 | ||
f160c7b7 JS |
1564 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1565 | young |= mmu_spte_age(sptep); | |
0d536790 | 1566 | |
e930bffe AA |
1567 | return young; |
1568 | } | |
1569 | ||
3039bcc7 SC |
1570 | static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1571 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1572 | int level, pte_t unused) | |
8ee53820 | 1573 | { |
1e3f42f0 TY |
1574 | u64 *sptep; |
1575 | struct rmap_iterator iter; | |
8ee53820 | 1576 | |
83ef6c81 JS |
1577 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1578 | if (is_accessed_spte(*sptep)) | |
1579 | return 1; | |
83ef6c81 | 1580 | return 0; |
8ee53820 AA |
1581 | } |
1582 | ||
53a27b39 MT |
1583 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1584 | ||
852e3c19 | 1585 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1586 | { |
018aabb5 | 1587 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1588 | struct kvm_mmu_page *sp; |
1589 | ||
57354682 | 1590 | sp = sptep_to_sp(spte); |
53a27b39 | 1591 | |
018aabb5 | 1592 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1593 | |
3039bcc7 | 1594 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0)); |
c3134ce2 LT |
1595 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1596 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1597 | } |
1598 | ||
3039bcc7 | 1599 | bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
e930bffe | 1600 | { |
e2209710 | 1601 | bool young = false; |
3039bcc7 | 1602 | |
e2209710 BG |
1603 | if (kvm_memslots_have_rmaps(kvm)) |
1604 | young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp); | |
f8e14497 | 1605 | |
897218ff | 1606 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1607 | young |= kvm_tdp_mmu_age_gfn_range(kvm, range); |
f8e14497 BG |
1608 | |
1609 | return young; | |
e930bffe AA |
1610 | } |
1611 | ||
3039bcc7 | 1612 | bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
8ee53820 | 1613 | { |
e2209710 | 1614 | bool young = false; |
3039bcc7 | 1615 | |
e2209710 BG |
1616 | if (kvm_memslots_have_rmaps(kvm)) |
1617 | young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp); | |
f8e14497 | 1618 | |
897218ff | 1619 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1620 | young |= kvm_tdp_mmu_test_age_gfn(kvm, range); |
f8e14497 BG |
1621 | |
1622 | return young; | |
8ee53820 AA |
1623 | } |
1624 | ||
d6c69ee9 | 1625 | #ifdef MMU_DEBUG |
47ad8e68 | 1626 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1627 | { |
139bdb2d AK |
1628 | u64 *pos; |
1629 | u64 *end; | |
1630 | ||
47ad8e68 | 1631 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1632 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1633 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1634 | pos, *pos); |
6aa8b732 | 1635 | return 0; |
139bdb2d | 1636 | } |
6aa8b732 AK |
1637 | return 1; |
1638 | } | |
d6c69ee9 | 1639 | #endif |
6aa8b732 | 1640 | |
45221ab6 DH |
1641 | /* |
1642 | * This value is the sum of all of the kvm instances's | |
1643 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1644 | * aggregate version in order to make the slab shrinker | |
1645 | * faster | |
1646 | */ | |
bc8a3d89 | 1647 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1648 | { |
1649 | kvm->arch.n_used_mmu_pages += nr; | |
1650 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1651 | } | |
1652 | ||
834be0d8 | 1653 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1654 | { |
fa4a2c08 | 1655 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1656 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1657 | list_del(&sp->link); |
1658 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1659 | if (!sp->role.direct) |
1660 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1661 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1662 | } |
1663 | ||
cea0f0e7 AK |
1664 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1665 | { | |
114df303 | 1666 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1667 | } |
1668 | ||
714b93da | 1669 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1670 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1671 | { |
cea0f0e7 AK |
1672 | if (!parent_pte) |
1673 | return; | |
cea0f0e7 | 1674 | |
67052b35 | 1675 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1676 | } |
1677 | ||
4db35314 | 1678 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1679 | u64 *parent_pte) |
1680 | { | |
8daf3462 | 1681 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1682 | } |
1683 | ||
bcdd9a93 XG |
1684 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1685 | u64 *parent_pte) | |
1686 | { | |
1687 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1688 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1689 | } |
1690 | ||
47005792 | 1691 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1692 | { |
67052b35 | 1693 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1694 | |
94ce87ef SC |
1695 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1696 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1697 | if (!direct) |
94ce87ef | 1698 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1699 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1700 | |
1701 | /* | |
1702 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1703 | * depends on valid pages being added to the head of the list. See | |
1704 | * comments in kvm_zap_obsolete_pages(). | |
1705 | */ | |
ca333add | 1706 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1707 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1708 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1709 | return sp; | |
ad8cfbe3 MT |
1710 | } |
1711 | ||
67052b35 | 1712 | static void mark_unsync(u64 *spte); |
1047df1f | 1713 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1714 | { |
74c4e63a TY |
1715 | u64 *sptep; |
1716 | struct rmap_iterator iter; | |
1717 | ||
1718 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1719 | mark_unsync(sptep); | |
1720 | } | |
0074ff63 MT |
1721 | } |
1722 | ||
67052b35 | 1723 | static void mark_unsync(u64 *spte) |
0074ff63 | 1724 | { |
67052b35 | 1725 | struct kvm_mmu_page *sp; |
1047df1f | 1726 | unsigned int index; |
0074ff63 | 1727 | |
57354682 | 1728 | sp = sptep_to_sp(spte); |
1047df1f XG |
1729 | index = spte - sp->spt; |
1730 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1731 | return; |
1047df1f | 1732 | if (sp->unsync_children++) |
0074ff63 | 1733 | return; |
1047df1f | 1734 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1735 | } |
1736 | ||
e8bc217a | 1737 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1738 | struct kvm_mmu_page *sp) |
e8bc217a | 1739 | { |
1f50f1b3 | 1740 | return 0; |
e8bc217a MT |
1741 | } |
1742 | ||
60c8aec6 MT |
1743 | #define KVM_PAGE_ARRAY_NR 16 |
1744 | ||
1745 | struct kvm_mmu_pages { | |
1746 | struct mmu_page_and_offset { | |
1747 | struct kvm_mmu_page *sp; | |
1748 | unsigned int idx; | |
1749 | } page[KVM_PAGE_ARRAY_NR]; | |
1750 | unsigned int nr; | |
1751 | }; | |
1752 | ||
cded19f3 HE |
1753 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1754 | int idx) | |
4731d4c7 | 1755 | { |
60c8aec6 | 1756 | int i; |
4731d4c7 | 1757 | |
60c8aec6 MT |
1758 | if (sp->unsync) |
1759 | for (i=0; i < pvec->nr; i++) | |
1760 | if (pvec->page[i].sp == sp) | |
1761 | return 0; | |
1762 | ||
1763 | pvec->page[pvec->nr].sp = sp; | |
1764 | pvec->page[pvec->nr].idx = idx; | |
1765 | pvec->nr++; | |
1766 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1767 | } | |
1768 | ||
fd951457 TY |
1769 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1770 | { | |
1771 | --sp->unsync_children; | |
1772 | WARN_ON((int)sp->unsync_children < 0); | |
1773 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1774 | } | |
1775 | ||
60c8aec6 MT |
1776 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1777 | struct kvm_mmu_pages *pvec) | |
1778 | { | |
1779 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1780 | |
37178b8b | 1781 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1782 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1783 | u64 ent = sp->spt[i]; |
1784 | ||
fd951457 TY |
1785 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1786 | clear_unsync_child_bit(sp, i); | |
1787 | continue; | |
1788 | } | |
7a8f1a74 | 1789 | |
e47c4aee | 1790 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1791 | |
1792 | if (child->unsync_children) { | |
1793 | if (mmu_pages_add(pvec, child, i)) | |
1794 | return -ENOSPC; | |
1795 | ||
1796 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1797 | if (!ret) { |
1798 | clear_unsync_child_bit(sp, i); | |
1799 | continue; | |
1800 | } else if (ret > 0) { | |
7a8f1a74 | 1801 | nr_unsync_leaf += ret; |
fd951457 | 1802 | } else |
7a8f1a74 XG |
1803 | return ret; |
1804 | } else if (child->unsync) { | |
1805 | nr_unsync_leaf++; | |
1806 | if (mmu_pages_add(pvec, child, i)) | |
1807 | return -ENOSPC; | |
1808 | } else | |
fd951457 | 1809 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1810 | } |
1811 | ||
60c8aec6 MT |
1812 | return nr_unsync_leaf; |
1813 | } | |
1814 | ||
e23d3fef XG |
1815 | #define INVALID_INDEX (-1) |
1816 | ||
60c8aec6 MT |
1817 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1818 | struct kvm_mmu_pages *pvec) | |
1819 | { | |
0a47cd85 | 1820 | pvec->nr = 0; |
60c8aec6 MT |
1821 | if (!sp->unsync_children) |
1822 | return 0; | |
1823 | ||
e23d3fef | 1824 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1825 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1826 | } |
1827 | ||
4731d4c7 MT |
1828 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1829 | { | |
1830 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1831 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1832 | sp->unsync = 0; |
1833 | --kvm->stat.mmu_unsync; | |
1834 | } | |
1835 | ||
83cdb568 SC |
1836 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1837 | struct list_head *invalid_list); | |
7775834a XG |
1838 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1839 | struct list_head *invalid_list); | |
4731d4c7 | 1840 | |
ac101b7c SC |
1841 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1842 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1843 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1844 | } else |
1044b030 TY |
1845 | |
1846 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1847 | for_each_valid_sp(_kvm, _sp, \ |
1848 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1849 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1850 | |
479a1efc SC |
1851 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1852 | struct list_head *invalid_list) | |
4731d4c7 | 1853 | { |
2640b086 | 1854 | if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 1855 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1856 | return false; |
4731d4c7 MT |
1857 | } |
1858 | ||
1f50f1b3 | 1859 | return true; |
4731d4c7 MT |
1860 | } |
1861 | ||
a2113634 SC |
1862 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1863 | struct list_head *invalid_list, | |
1864 | bool remote_flush) | |
1865 | { | |
cfd32acf | 1866 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1867 | return false; |
1868 | ||
1869 | if (!list_empty(invalid_list)) | |
1870 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1871 | else | |
1872 | kvm_flush_remote_tlbs(kvm); | |
1873 | return true; | |
1874 | } | |
1875 | ||
35a70510 PB |
1876 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1877 | struct list_head *invalid_list, | |
1878 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1879 | { |
a2113634 | 1880 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1881 | return; |
d98ba053 | 1882 | |
a2113634 | 1883 | if (local_flush) |
8c8560b8 | 1884 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1885 | } |
1886 | ||
e37fa785 XG |
1887 | #ifdef CONFIG_KVM_MMU_AUDIT |
1888 | #include "mmu_audit.c" | |
1889 | #else | |
1890 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1891 | static void mmu_audit_disable(void) { } | |
1892 | #endif | |
1893 | ||
002c5f73 SC |
1894 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1895 | { | |
fac026da SC |
1896 | return sp->role.invalid || |
1897 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1898 | } |
1899 | ||
60c8aec6 | 1900 | struct mmu_page_path { |
2a7266a8 YZ |
1901 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1902 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1903 | }; |
1904 | ||
60c8aec6 | 1905 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1906 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1907 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1908 | i = mmu_pages_next(&pvec, &parents, i)) | |
1909 | ||
cded19f3 HE |
1910 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1911 | struct mmu_page_path *parents, | |
1912 | int i) | |
60c8aec6 MT |
1913 | { |
1914 | int n; | |
1915 | ||
1916 | for (n = i+1; n < pvec->nr; n++) { | |
1917 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1918 | unsigned idx = pvec->page[n].idx; |
1919 | int level = sp->role.level; | |
60c8aec6 | 1920 | |
0a47cd85 | 1921 | parents->idx[level-1] = idx; |
3bae0459 | 1922 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1923 | break; |
60c8aec6 | 1924 | |
0a47cd85 | 1925 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1926 | } |
1927 | ||
1928 | return n; | |
1929 | } | |
1930 | ||
0a47cd85 PB |
1931 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1932 | struct mmu_page_path *parents) | |
1933 | { | |
1934 | struct kvm_mmu_page *sp; | |
1935 | int level; | |
1936 | ||
1937 | if (pvec->nr == 0) | |
1938 | return 0; | |
1939 | ||
e23d3fef XG |
1940 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1941 | ||
0a47cd85 PB |
1942 | sp = pvec->page[0].sp; |
1943 | level = sp->role.level; | |
3bae0459 | 1944 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1945 | |
1946 | parents->parent[level-2] = sp; | |
1947 | ||
1948 | /* Also set up a sentinel. Further entries in pvec are all | |
1949 | * children of sp, so this element is never overwritten. | |
1950 | */ | |
1951 | parents->parent[level-1] = NULL; | |
1952 | return mmu_pages_next(pvec, parents, 0); | |
1953 | } | |
1954 | ||
cded19f3 | 1955 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1956 | { |
60c8aec6 MT |
1957 | struct kvm_mmu_page *sp; |
1958 | unsigned int level = 0; | |
1959 | ||
1960 | do { | |
1961 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1962 | sp = parents->parent[level]; |
1963 | if (!sp) | |
1964 | return; | |
1965 | ||
e23d3fef | 1966 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1967 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1968 | level++; |
0a47cd85 | 1969 | } while (!sp->unsync_children); |
60c8aec6 | 1970 | } |
4731d4c7 | 1971 | |
60c8aec6 MT |
1972 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1973 | struct kvm_mmu_page *parent) | |
1974 | { | |
1975 | int i; | |
1976 | struct kvm_mmu_page *sp; | |
1977 | struct mmu_page_path parents; | |
1978 | struct kvm_mmu_pages pages; | |
d98ba053 | 1979 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1980 | bool flush = false; |
60c8aec6 | 1981 | |
60c8aec6 | 1982 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1983 | bool protected = false; |
b1a36821 MT |
1984 | |
1985 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1986 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1987 | |
50c9e6f3 | 1988 | if (protected) { |
b1a36821 | 1989 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
1990 | flush = false; |
1991 | } | |
b1a36821 | 1992 | |
60c8aec6 | 1993 | for_each_sp(pages, sp, parents, i) { |
479a1efc | 1994 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1f50f1b3 | 1995 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1996 | mmu_pages_clear_parents(&parents); |
1997 | } | |
531810ca | 1998 | if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) { |
50c9e6f3 | 1999 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); |
531810ca | 2000 | cond_resched_rwlock_write(&vcpu->kvm->mmu_lock); |
50c9e6f3 PB |
2001 | flush = false; |
2002 | } | |
60c8aec6 | 2003 | } |
50c9e6f3 PB |
2004 | |
2005 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2006 | } |
2007 | ||
a30f47cb XG |
2008 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2009 | { | |
e5691a81 | 2010 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2011 | } |
2012 | ||
2013 | static void clear_sp_write_flooding_count(u64 *spte) | |
2014 | { | |
57354682 | 2015 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
2016 | } |
2017 | ||
cea0f0e7 AK |
2018 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2019 | gfn_t gfn, | |
2020 | gva_t gaddr, | |
2021 | unsigned level, | |
f6e2c02b | 2022 | int direct, |
0a2b64c5 | 2023 | unsigned int access) |
cea0f0e7 | 2024 | { |
fb58a9c3 | 2025 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2026 | union kvm_mmu_page_role role; |
ac101b7c | 2027 | struct hlist_head *sp_list; |
cea0f0e7 | 2028 | unsigned quadrant; |
9f1a122f | 2029 | struct kvm_mmu_page *sp; |
f3414bc7 | 2030 | int collisions = 0; |
2a74003a | 2031 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2032 | |
36d9594d | 2033 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2034 | role.level = level; |
f6e2c02b | 2035 | role.direct = direct; |
84b0c8c6 | 2036 | if (role.direct) |
47c42e6b | 2037 | role.gpte_is_8_bytes = true; |
41074d07 | 2038 | role.access = access; |
fb58a9c3 | 2039 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2040 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2041 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2042 | role.quadrant = quadrant; | |
2043 | } | |
ac101b7c SC |
2044 | |
2045 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2046 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2047 | if (sp->gfn != gfn) { |
2048 | collisions++; | |
2049 | continue; | |
2050 | } | |
2051 | ||
ddc16abb SC |
2052 | if (sp->role.word != role.word) { |
2053 | /* | |
2054 | * If the guest is creating an upper-level page, zap | |
2055 | * unsync pages for the same gfn. While it's possible | |
2056 | * the guest is using recursive page tables, in all | |
2057 | * likelihood the guest has stopped using the unsync | |
2058 | * page and is installing a completely unrelated page. | |
2059 | * Unsync pages must not be left as is, because the new | |
2060 | * upper-level page will be write-protected. | |
2061 | */ | |
2062 | if (level > PG_LEVEL_4K && sp->unsync) | |
2063 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, | |
2064 | &invalid_list); | |
7ae680eb | 2065 | continue; |
ddc16abb | 2066 | } |
4731d4c7 | 2067 | |
fb58a9c3 SC |
2068 | if (direct_mmu) |
2069 | goto trace_get_page; | |
2070 | ||
2a74003a | 2071 | if (sp->unsync) { |
07dc4f35 | 2072 | /* |
479a1efc | 2073 | * The page is good, but is stale. kvm_sync_page does |
07dc4f35 SC |
2074 | * get the latest guest state, but (unlike mmu_unsync_children) |
2075 | * it doesn't write-protect the page or mark it synchronized! | |
2076 | * This way the validity of the mapping is ensured, but the | |
2077 | * overhead of write protection is not incurred until the | |
2078 | * guest invalidates the TLB mapping. This allows multiple | |
2079 | * SPs for a single gfn to be unsync. | |
2080 | * | |
2081 | * If the sync fails, the page is zapped. If so, break | |
2082 | * in order to rebuild it. | |
2a74003a | 2083 | */ |
479a1efc | 2084 | if (!kvm_sync_page(vcpu, sp, &invalid_list)) |
2a74003a PB |
2085 | break; |
2086 | ||
2087 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2088 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2089 | } |
e02aa901 | 2090 | |
98bba238 | 2091 | if (sp->unsync_children) |
f6f6195b | 2092 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2093 | |
a30f47cb | 2094 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2095 | |
2096 | trace_get_page: | |
7ae680eb | 2097 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2098 | goto out; |
7ae680eb | 2099 | } |
47005792 | 2100 | |
dfc5aa00 | 2101 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2102 | |
2103 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2104 | ||
4db35314 AK |
2105 | sp->gfn = gfn; |
2106 | sp->role = role; | |
ac101b7c | 2107 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2108 | if (!direct) { |
56ca57f9 | 2109 | account_shadowed(vcpu->kvm, sp); |
3bae0459 | 2110 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2111 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
4731d4c7 | 2112 | } |
f691fe1d | 2113 | trace_kvm_mmu_get_page(sp, true); |
f3414bc7 | 2114 | out: |
ddc16abb SC |
2115 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
2116 | ||
f3414bc7 DM |
2117 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) |
2118 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2119 | return sp; |
cea0f0e7 AK |
2120 | } |
2121 | ||
7eb77e9f JS |
2122 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2123 | struct kvm_vcpu *vcpu, hpa_t root, | |
2124 | u64 addr) | |
2d11123a AK |
2125 | { |
2126 | iterator->addr = addr; | |
7eb77e9f | 2127 | iterator->shadow_addr = root; |
44dd3ffa | 2128 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2129 | |
2a7266a8 | 2130 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2131 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2132 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2133 | --iterator->level; |
2134 | ||
2d11123a | 2135 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2136 | /* |
2137 | * prev_root is currently only used for 64-bit hosts. So only | |
2138 | * the active root_hpa is valid here. | |
2139 | */ | |
44dd3ffa | 2140 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2141 | |
2d11123a | 2142 | iterator->shadow_addr |
44dd3ffa | 2143 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2144 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2145 | --iterator->level; | |
2146 | if (!iterator->shadow_addr) | |
2147 | iterator->level = 0; | |
2148 | } | |
2149 | } | |
2150 | ||
7eb77e9f JS |
2151 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2152 | struct kvm_vcpu *vcpu, u64 addr) | |
2153 | { | |
44dd3ffa | 2154 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2155 | addr); |
2156 | } | |
2157 | ||
2d11123a AK |
2158 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2159 | { | |
3bae0459 | 2160 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2161 | return false; |
4d88954d | 2162 | |
2d11123a AK |
2163 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2164 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2165 | return true; | |
2166 | } | |
2167 | ||
c2a2ac2b XG |
2168 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2169 | u64 spte) | |
2d11123a | 2170 | { |
c2a2ac2b | 2171 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2172 | iterator->level = 0; |
2173 | return; | |
2174 | } | |
2175 | ||
c2a2ac2b | 2176 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2177 | --iterator->level; |
2178 | } | |
2179 | ||
c2a2ac2b XG |
2180 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2181 | { | |
bb606a9b | 2182 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2183 | } |
2184 | ||
cc4674d0 BG |
2185 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2186 | struct kvm_mmu_page *sp) | |
2187 | { | |
2188 | u64 spte; | |
2189 | ||
2190 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2191 | ||
2192 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2193 | ||
1df9f2dc | 2194 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2195 | |
2196 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2197 | ||
2198 | if (sp->unsync_children || sp->unsync) | |
2199 | mark_unsync(sptep); | |
32ef26a3 AK |
2200 | } |
2201 | ||
a357bd22 AK |
2202 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2203 | unsigned direct_access) | |
2204 | { | |
2205 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2206 | struct kvm_mmu_page *child; | |
2207 | ||
2208 | /* | |
2209 | * For the direct sp, if the guest pte's dirty bit | |
2210 | * changed form clean to dirty, it will corrupt the | |
2211 | * sp's access: allow writable in the read-only sp, | |
2212 | * so we should update the spte at this point to get | |
2213 | * a new sp with the correct access. | |
2214 | */ | |
e47c4aee | 2215 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2216 | if (child->role.access == direct_access) |
2217 | return; | |
2218 | ||
bcdd9a93 | 2219 | drop_parent_pte(child, sptep); |
c3134ce2 | 2220 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2221 | } |
2222 | } | |
2223 | ||
2de4085c BG |
2224 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2225 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2226 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2227 | { |
2228 | u64 pte; | |
2229 | struct kvm_mmu_page *child; | |
2230 | ||
2231 | pte = *spte; | |
2232 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2233 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2234 | drop_spte(kvm, spte); |
505aef8f XG |
2235 | if (is_large_pte(pte)) |
2236 | --kvm->stat.lpages; | |
2237 | } else { | |
e47c4aee | 2238 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2239 | drop_parent_pte(child, spte); |
2de4085c BG |
2240 | |
2241 | /* | |
2242 | * Recursively zap nested TDP SPs, parentless SPs are | |
2243 | * unlikely to be used again in the near future. This | |
2244 | * avoids retaining a large number of stale nested SPs. | |
2245 | */ | |
2246 | if (tdp_enabled && invalid_list && | |
2247 | child->role.guest_mode && !child->parent_ptes.val) | |
2248 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2249 | invalid_list); | |
38e3b2b2 | 2250 | } |
ace569e0 | 2251 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2252 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2253 | } |
2de4085c | 2254 | return 0; |
38e3b2b2 XG |
2255 | } |
2256 | ||
2de4085c BG |
2257 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2258 | struct kvm_mmu_page *sp, | |
2259 | struct list_head *invalid_list) | |
a436036b | 2260 | { |
2de4085c | 2261 | int zapped = 0; |
697fe2e2 | 2262 | unsigned i; |
697fe2e2 | 2263 | |
38e3b2b2 | 2264 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2265 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2266 | ||
2267 | return zapped; | |
a436036b AK |
2268 | } |
2269 | ||
31aa2b44 | 2270 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2271 | { |
1e3f42f0 TY |
2272 | u64 *sptep; |
2273 | struct rmap_iterator iter; | |
a436036b | 2274 | |
018aabb5 | 2275 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2276 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2277 | } |
2278 | ||
60c8aec6 | 2279 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2280 | struct kvm_mmu_page *parent, |
2281 | struct list_head *invalid_list) | |
4731d4c7 | 2282 | { |
60c8aec6 MT |
2283 | int i, zapped = 0; |
2284 | struct mmu_page_path parents; | |
2285 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2286 | |
3bae0459 | 2287 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2288 | return 0; |
60c8aec6 | 2289 | |
60c8aec6 MT |
2290 | while (mmu_unsync_walk(parent, &pages)) { |
2291 | struct kvm_mmu_page *sp; | |
2292 | ||
2293 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2294 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2295 | mmu_pages_clear_parents(&parents); |
77662e00 | 2296 | zapped++; |
60c8aec6 | 2297 | } |
60c8aec6 MT |
2298 | } |
2299 | ||
2300 | return zapped; | |
4731d4c7 MT |
2301 | } |
2302 | ||
83cdb568 SC |
2303 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2304 | struct kvm_mmu_page *sp, | |
2305 | struct list_head *invalid_list, | |
2306 | int *nr_zapped) | |
31aa2b44 | 2307 | { |
83cdb568 | 2308 | bool list_unstable; |
f691fe1d | 2309 | |
7775834a | 2310 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2311 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2312 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2313 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2314 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2315 | |
83cdb568 SC |
2316 | /* Zapping children means active_mmu_pages has become unstable. */ |
2317 | list_unstable = *nr_zapped; | |
2318 | ||
f6e2c02b | 2319 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2320 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2321 | |
4731d4c7 MT |
2322 | if (sp->unsync) |
2323 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2324 | if (!sp->root_count) { |
54a4f023 | 2325 | /* Count self */ |
83cdb568 | 2326 | (*nr_zapped)++; |
f95eec9b SC |
2327 | |
2328 | /* | |
2329 | * Already invalid pages (previously active roots) are not on | |
2330 | * the active page list. See list_del() in the "else" case of | |
2331 | * !sp->root_count. | |
2332 | */ | |
2333 | if (sp->role.invalid) | |
2334 | list_add(&sp->link, invalid_list); | |
2335 | else | |
2336 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2337 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2338 | } else { |
f95eec9b SC |
2339 | /* |
2340 | * Remove the active root from the active page list, the root | |
2341 | * will be explicitly freed when the root_count hits zero. | |
2342 | */ | |
2343 | list_del(&sp->link); | |
05988d72 | 2344 | |
10605204 SC |
2345 | /* |
2346 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2347 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2348 | * treats invalid shadow pages as being obsolete. | |
2349 | */ | |
2350 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2351 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2352 | } |
7775834a | 2353 | |
b8e8c830 PB |
2354 | if (sp->lpage_disallowed) |
2355 | unaccount_huge_nx_page(kvm, sp); | |
2356 | ||
7775834a | 2357 | sp->role.invalid = 1; |
83cdb568 SC |
2358 | return list_unstable; |
2359 | } | |
2360 | ||
2361 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2362 | struct list_head *invalid_list) | |
2363 | { | |
2364 | int nr_zapped; | |
2365 | ||
2366 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2367 | return nr_zapped; | |
a436036b AK |
2368 | } |
2369 | ||
7775834a XG |
2370 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2371 | struct list_head *invalid_list) | |
2372 | { | |
945315b9 | 2373 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2374 | |
2375 | if (list_empty(invalid_list)) | |
2376 | return; | |
2377 | ||
c142786c | 2378 | /* |
9753f529 LT |
2379 | * We need to make sure everyone sees our modifications to |
2380 | * the page tables and see changes to vcpu->mode here. The barrier | |
2381 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2382 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2383 | * | |
2384 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2385 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2386 | */ |
2387 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2388 | |
945315b9 | 2389 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2390 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2391 | kvm_mmu_free_page(sp); |
945315b9 | 2392 | } |
7775834a XG |
2393 | } |
2394 | ||
6b82ef2c SC |
2395 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2396 | unsigned long nr_to_zap) | |
5da59607 | 2397 | { |
6b82ef2c SC |
2398 | unsigned long total_zapped = 0; |
2399 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2400 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2401 | bool unstable; |
2402 | int nr_zapped; | |
5da59607 TY |
2403 | |
2404 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2405 | return 0; |
2406 | ||
6b82ef2c | 2407 | restart: |
8fc51726 | 2408 | list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) { |
6b82ef2c SC |
2409 | /* |
2410 | * Don't zap active root pages, the page itself can't be freed | |
2411 | * and zapping it will just force vCPUs to realloc and reload. | |
2412 | */ | |
2413 | if (sp->root_count) | |
2414 | continue; | |
2415 | ||
2416 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2417 | &nr_zapped); | |
2418 | total_zapped += nr_zapped; | |
2419 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2420 | break; |
2421 | ||
6b82ef2c SC |
2422 | if (unstable) |
2423 | goto restart; | |
ba7888dd | 2424 | } |
5da59607 | 2425 | |
6b82ef2c SC |
2426 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2427 | ||
2428 | kvm->stat.mmu_recycled += total_zapped; | |
2429 | return total_zapped; | |
2430 | } | |
2431 | ||
afe8d7e6 SC |
2432 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2433 | { | |
2434 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2435 | return kvm->arch.n_max_mmu_pages - | |
2436 | kvm->arch.n_used_mmu_pages; | |
2437 | ||
2438 | return 0; | |
5da59607 TY |
2439 | } |
2440 | ||
ba7888dd SC |
2441 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2442 | { | |
6b82ef2c | 2443 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2444 | |
6b82ef2c | 2445 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2446 | return 0; |
2447 | ||
6b82ef2c | 2448 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd | 2449 | |
6e6ec584 SC |
2450 | /* |
2451 | * Note, this check is intentionally soft, it only guarantees that one | |
2452 | * page is available, while the caller may end up allocating as many as | |
2453 | * four pages, e.g. for PAE roots or for 5-level paging. Temporarily | |
2454 | * exceeding the (arbitrary by default) limit will not harm the host, | |
c4342633 | 2455 | * being too aggressive may unnecessarily kill the guest, and getting an |
6e6ec584 SC |
2456 | * exact count is far more trouble than it's worth, especially in the |
2457 | * page fault paths. | |
2458 | */ | |
ba7888dd SC |
2459 | if (!kvm_mmu_available_pages(vcpu->kvm)) |
2460 | return -ENOSPC; | |
2461 | return 0; | |
2462 | } | |
2463 | ||
82ce2c96 IE |
2464 | /* |
2465 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2466 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2467 | */ |
bc8a3d89 | 2468 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2469 | { |
531810ca | 2470 | write_lock(&kvm->mmu_lock); |
b34cb590 | 2471 | |
49d5ca26 | 2472 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2473 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2474 | goal_nr_mmu_pages); | |
82ce2c96 | 2475 | |
49d5ca26 | 2476 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2477 | } |
82ce2c96 | 2478 | |
49d5ca26 | 2479 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 | 2480 | |
531810ca | 2481 | write_unlock(&kvm->mmu_lock); |
82ce2c96 IE |
2482 | } |
2483 | ||
1cb3f3ae | 2484 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2485 | { |
4db35314 | 2486 | struct kvm_mmu_page *sp; |
d98ba053 | 2487 | LIST_HEAD(invalid_list); |
a436036b AK |
2488 | int r; |
2489 | ||
9ad17b10 | 2490 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2491 | r = 0; |
531810ca | 2492 | write_lock(&kvm->mmu_lock); |
b67bfe0d | 2493 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2494 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2495 | sp->role.word); |
2496 | r = 1; | |
f41d335a | 2497 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2498 | } |
d98ba053 | 2499 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 2500 | write_unlock(&kvm->mmu_lock); |
1cb3f3ae | 2501 | |
a436036b | 2502 | return r; |
cea0f0e7 | 2503 | } |
96ad91ae SC |
2504 | |
2505 | static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) | |
2506 | { | |
2507 | gpa_t gpa; | |
2508 | int r; | |
2509 | ||
2510 | if (vcpu->arch.mmu->direct_map) | |
2511 | return 0; | |
2512 | ||
2513 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); | |
2514 | ||
2515 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2516 | ||
2517 | return r; | |
2518 | } | |
cea0f0e7 | 2519 | |
5c520e90 | 2520 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2521 | { |
2522 | trace_kvm_mmu_unsync_page(sp); | |
2523 | ++vcpu->kvm->stat.mmu_unsync; | |
2524 | sp->unsync = 1; | |
2525 | ||
2526 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2527 | } |
2528 | ||
0337f585 SC |
2529 | /* |
2530 | * Attempt to unsync any shadow pages that can be reached by the specified gfn, | |
2531 | * KVM is creating a writable mapping for said gfn. Returns 0 if all pages | |
2532 | * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must | |
2533 | * be write-protected. | |
2534 | */ | |
2535 | int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync) | |
4731d4c7 | 2536 | { |
5c520e90 | 2537 | struct kvm_mmu_page *sp; |
4731d4c7 | 2538 | |
0337f585 SC |
2539 | /* |
2540 | * Force write-protection if the page is being tracked. Note, the page | |
2541 | * track machinery is used to write-protect upper-level shadow pages, | |
2542 | * i.e. this guards the role.level == 4K assertion below! | |
2543 | */ | |
3d0c27ad | 2544 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
0337f585 | 2545 | return -EPERM; |
9cf5cf5a | 2546 | |
0337f585 SC |
2547 | /* |
2548 | * The page is not write-tracked, mark existing shadow pages unsync | |
2549 | * unless KVM is synchronizing an unsync SP (can_unsync = false). In | |
2550 | * that case, KVM must complete emulation of the guest TLB flush before | |
2551 | * allowing shadow pages to become unsync (writable by the guest). | |
2552 | */ | |
5c520e90 | 2553 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2554 | if (!can_unsync) |
0337f585 | 2555 | return -EPERM; |
36a2e677 | 2556 | |
5c520e90 XG |
2557 | if (sp->unsync) |
2558 | continue; | |
9cf5cf5a | 2559 | |
3bae0459 | 2560 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2561 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2562 | } |
3d0c27ad | 2563 | |
578e1c4d JS |
2564 | /* |
2565 | * We need to ensure that the marking of unsync pages is visible | |
2566 | * before the SPTE is updated to allow writes because | |
2567 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2568 | * the MMU lock and so can race with this. If the SPTE was updated | |
2569 | * before the page had been marked as unsync-ed, something like the | |
2570 | * following could happen: | |
2571 | * | |
2572 | * CPU 1 CPU 2 | |
2573 | * --------------------------------------------------------------------- | |
2574 | * 1.2 Host updates SPTE | |
2575 | * to be writable | |
2576 | * 2.1 Guest writes a GPTE for GVA X. | |
2577 | * (GPTE being in the guest page table shadowed | |
2578 | * by the SP from CPU 1.) | |
2579 | * This reads SPTE during the page table walk. | |
2580 | * Since SPTE.W is read as 1, there is no | |
2581 | * fault. | |
2582 | * | |
2583 | * 2.2 Guest issues TLB flush. | |
2584 | * That causes a VM Exit. | |
2585 | * | |
0337f585 SC |
2586 | * 2.3 Walking of unsync pages sees sp->unsync is |
2587 | * false and skips the page. | |
578e1c4d JS |
2588 | * |
2589 | * 2.4 Guest accesses GVA X. | |
2590 | * Since the mapping in the SP was not updated, | |
2591 | * so the old mapping for GVA X incorrectly | |
2592 | * gets used. | |
2593 | * 1.1 Host marks SP | |
2594 | * as unsync | |
2595 | * (sp->unsync = true) | |
2596 | * | |
2597 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2598 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2599 | * pairs with this write barrier. | |
2600 | */ | |
2601 | smp_wmb(); | |
2602 | ||
0337f585 | 2603 | return 0; |
4731d4c7 MT |
2604 | } |
2605 | ||
799a4190 BG |
2606 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2607 | unsigned int pte_access, int level, | |
2608 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2609 | bool can_unsync, bool host_writable) | |
2610 | { | |
2611 | u64 spte; | |
2612 | struct kvm_mmu_page *sp; | |
2613 | int ret; | |
2614 | ||
799a4190 BG |
2615 | sp = sptep_to_sp(sptep); |
2616 | ||
2617 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2618 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2619 | ||
2620 | if (spte & PT_WRITABLE_MASK) | |
2621 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2622 | ||
12703759 SC |
2623 | if (*sptep == spte) |
2624 | ret |= SET_SPTE_SPURIOUS; | |
2625 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2626 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2627 | return ret; |
2628 | } | |
2629 | ||
0a2b64c5 | 2630 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2631 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2632 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2633 | bool host_writable) | |
1e73f9dd MT |
2634 | { |
2635 | int was_rmapped = 0; | |
53a27b39 | 2636 | int rmap_count; |
5ce4786f | 2637 | int set_spte_ret; |
c4371c2a | 2638 | int ret = RET_PF_FIXED; |
c2a4eadf | 2639 | bool flush = false; |
1e73f9dd | 2640 | |
f7616203 XG |
2641 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2642 | *sptep, write_fault, gfn); | |
1e73f9dd | 2643 | |
a54aa15c SC |
2644 | if (unlikely(is_noslot_pfn(pfn))) { |
2645 | mark_mmio_spte(vcpu, sptep, gfn, pte_access); | |
2646 | return RET_PF_EMULATE; | |
2647 | } | |
2648 | ||
afd28fe1 | 2649 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2650 | /* |
2651 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2652 | * the parent of the now unreachable PTE. | |
2653 | */ | |
3bae0459 | 2654 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2655 | struct kvm_mmu_page *child; |
d555c333 | 2656 | u64 pte = *sptep; |
1e73f9dd | 2657 | |
e47c4aee | 2658 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2659 | drop_parent_pte(child, sptep); |
c2a4eadf | 2660 | flush = true; |
d555c333 | 2661 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2662 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2663 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2664 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2665 | flush = true; |
6bed6b9e JR |
2666 | } else |
2667 | was_rmapped = 1; | |
1e73f9dd | 2668 | } |
852e3c19 | 2669 | |
5ce4786f JS |
2670 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2671 | speculative, true, host_writable); | |
2672 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2673 | if (write_fault) |
9b8ebbdb | 2674 | ret = RET_PF_EMULATE; |
8c8560b8 | 2675 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2676 | } |
c3134ce2 | 2677 | |
c2a4eadf | 2678 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2679 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2680 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2681 | |
12703759 SC |
2682 | /* |
2683 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2684 | * are identical, and emulation is not required. | |
2685 | */ | |
2686 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2687 | WARN_ON_ONCE(!was_rmapped); | |
2688 | return RET_PF_SPURIOUS; | |
2689 | } | |
2690 | ||
d555c333 | 2691 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2692 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2693 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2694 | ++vcpu->kvm->stat.lpages; |
2695 | ||
ffb61bb3 | 2696 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2697 | if (!was_rmapped) { |
2698 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2699 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2700 | rmap_recycle(vcpu, sptep, gfn); | |
2701 | } | |
1c4f1fd6 | 2702 | } |
cb9aaa30 | 2703 | |
9b8ebbdb | 2704 | return ret; |
1c4f1fd6 AK |
2705 | } |
2706 | ||
ba049e93 | 2707 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2708 | bool no_dirty_log) |
2709 | { | |
2710 | struct kvm_memory_slot *slot; | |
957ed9ef | 2711 | |
5d163b1c | 2712 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2713 | if (!slot) |
6c8ee57b | 2714 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2715 | |
037d92dc | 2716 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2717 | } |
2718 | ||
2719 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2720 | struct kvm_mmu_page *sp, | |
2721 | u64 *start, u64 *end) | |
2722 | { | |
2723 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2724 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2725 | unsigned int access = sp->role.access; |
957ed9ef XG |
2726 | int i, ret; |
2727 | gfn_t gfn; | |
2728 | ||
2729 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2730 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2731 | if (!slot) | |
957ed9ef XG |
2732 | return -1; |
2733 | ||
d9ef13c2 | 2734 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2735 | if (ret <= 0) |
2736 | return -1; | |
2737 | ||
43fdcda9 | 2738 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2739 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2740 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2741 | put_page(pages[i]); |
2742 | } | |
957ed9ef XG |
2743 | |
2744 | return 0; | |
2745 | } | |
2746 | ||
2747 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2748 | struct kvm_mmu_page *sp, u64 *sptep) | |
2749 | { | |
2750 | u64 *spte, *start = NULL; | |
2751 | int i; | |
2752 | ||
2753 | WARN_ON(!sp->role.direct); | |
2754 | ||
2755 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2756 | spte = sp->spt + i; | |
2757 | ||
2758 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2759 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2760 | if (!start) |
2761 | continue; | |
2762 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2763 | break; | |
2764 | start = NULL; | |
2765 | } else if (!start) | |
2766 | start = spte; | |
2767 | } | |
2768 | } | |
2769 | ||
2770 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2771 | { | |
2772 | struct kvm_mmu_page *sp; | |
2773 | ||
57354682 | 2774 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2775 | |
957ed9ef | 2776 | /* |
ac8d57e5 PF |
2777 | * Without accessed bits, there's no way to distinguish between |
2778 | * actually accessed translations and prefetched, so disable pte | |
2779 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2780 | */ |
ac8d57e5 | 2781 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2782 | return; |
2783 | ||
3bae0459 | 2784 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2785 | return; |
2786 | ||
4a42d848 DS |
2787 | /* |
2788 | * If addresses are being invalidated, skip prefetching to avoid | |
2789 | * accidentally prefetching those addresses. | |
2790 | */ | |
2791 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
2792 | return; | |
2793 | ||
957ed9ef XG |
2794 | __direct_pte_prefetch(vcpu, sp, sptep); |
2795 | } | |
2796 | ||
1b6d9d9e | 2797 | static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, |
8ca6f063 | 2798 | const struct kvm_memory_slot *slot) |
db543216 | 2799 | { |
db543216 SC |
2800 | unsigned long hva; |
2801 | pte_t *pte; | |
2802 | int level; | |
2803 | ||
e851265a | 2804 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2805 | return PG_LEVEL_4K; |
db543216 | 2806 | |
293e306e SC |
2807 | /* |
2808 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2809 | * is not solely for performance, it's also necessary to avoid the | |
2810 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2811 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2812 | * page fault steps have already verified the guest isn't writing a | |
2813 | * read-only memslot. | |
2814 | */ | |
db543216 SC |
2815 | hva = __gfn_to_hva_memslot(slot, gfn); |
2816 | ||
1b6d9d9e | 2817 | pte = lookup_address_in_mm(kvm->mm, hva, &level); |
db543216 | 2818 | if (unlikely(!pte)) |
3bae0459 | 2819 | return PG_LEVEL_4K; |
db543216 SC |
2820 | |
2821 | return level; | |
2822 | } | |
2823 | ||
8ca6f063 BG |
2824 | int kvm_mmu_max_mapping_level(struct kvm *kvm, |
2825 | const struct kvm_memory_slot *slot, gfn_t gfn, | |
2826 | kvm_pfn_t pfn, int max_level) | |
1b6d9d9e SC |
2827 | { |
2828 | struct kvm_lpage_info *linfo; | |
2829 | ||
2830 | max_level = min(max_level, max_huge_page_level); | |
2831 | for ( ; max_level > PG_LEVEL_4K; max_level--) { | |
2832 | linfo = lpage_info_slot(gfn, slot, max_level); | |
2833 | if (!linfo->disallow_lpage) | |
2834 | break; | |
2835 | } | |
2836 | ||
2837 | if (max_level == PG_LEVEL_4K) | |
2838 | return PG_LEVEL_4K; | |
2839 | ||
2840 | return host_pfn_mapping_level(kvm, gfn, pfn, slot); | |
2841 | } | |
2842 | ||
bb18842e BG |
2843 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2844 | int max_level, kvm_pfn_t *pfnp, | |
2845 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2846 | { |
293e306e | 2847 | struct kvm_memory_slot *slot; |
0885904d | 2848 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2849 | kvm_pfn_t mask; |
83f06fa7 | 2850 | int level; |
17eff019 | 2851 | |
3cf06612 SC |
2852 | *req_level = PG_LEVEL_4K; |
2853 | ||
3bae0459 SC |
2854 | if (unlikely(max_level == PG_LEVEL_4K)) |
2855 | return PG_LEVEL_4K; | |
17eff019 | 2856 | |
e851265a | 2857 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2858 | return PG_LEVEL_4K; |
17eff019 | 2859 | |
293e306e SC |
2860 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2861 | if (!slot) | |
3bae0459 | 2862 | return PG_LEVEL_4K; |
293e306e | 2863 | |
1b6d9d9e | 2864 | level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level); |
3bae0459 | 2865 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2866 | return level; |
17eff019 | 2867 | |
3cf06612 SC |
2868 | *req_level = level = min(level, max_level); |
2869 | ||
2870 | /* | |
2871 | * Enforce the iTLB multihit workaround after capturing the requested | |
2872 | * level, which will be used to do precise, accurate accounting. | |
2873 | */ | |
2874 | if (huge_page_disallowed) | |
2875 | return PG_LEVEL_4K; | |
0885904d SC |
2876 | |
2877 | /* | |
17eff019 SC |
2878 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2879 | * the pmd can't be split from under us. | |
0885904d | 2880 | */ |
17eff019 SC |
2881 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2882 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2883 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2884 | |
2885 | return level; | |
0885904d SC |
2886 | } |
2887 | ||
bb18842e BG |
2888 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2889 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2890 | { |
bb18842e | 2891 | int level = *goal_levelp; |
b8e8c830 | 2892 | |
7d945312 | 2893 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2894 | is_shadow_present_pte(spte) && |
2895 | !is_large_pte(spte)) { | |
2896 | /* | |
2897 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2898 | * and __direct_map would like to create a large PTE | |
2899 | * instead: just force them to go down another level, | |
2900 | * patching back for them into pfn the next 9 bits of | |
2901 | * the address. | |
2902 | */ | |
7d945312 BG |
2903 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2904 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2905 | *pfnp |= gfn & page_mask; |
bb18842e | 2906 | (*goal_levelp)--; |
b8e8c830 PB |
2907 | } |
2908 | } | |
2909 | ||
6c2fd34f | 2910 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2911 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2912 | bool prefault, bool is_tdp) |
140754bc | 2913 | { |
6c2fd34f SC |
2914 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2915 | bool write = error_code & PFERR_WRITE_MASK; | |
2916 | bool exec = error_code & PFERR_FETCH_MASK; | |
2917 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2918 | struct kvm_shadow_walk_iterator it; |
140754bc | 2919 | struct kvm_mmu_page *sp; |
3cf06612 | 2920 | int level, req_level, ret; |
3fcf2d1b PB |
2921 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2922 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2923 | |
3cf06612 SC |
2924 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2925 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2926 | |
335e192a | 2927 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2928 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2929 | /* |
2930 | * We cannot overwrite existing page tables with an NX | |
2931 | * large page, as the leaf could be executable. | |
2932 | */ | |
dcc70651 | 2933 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
2934 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
2935 | &pfn, &level); | |
b8e8c830 | 2936 | |
3fcf2d1b PB |
2937 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2938 | if (it.level == level) | |
9f652d21 | 2939 | break; |
6aa8b732 | 2940 | |
3fcf2d1b PB |
2941 | drop_large_spte(vcpu, it.sptep); |
2942 | if (!is_shadow_present_pte(*it.sptep)) { | |
2943 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2944 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2945 | |
3fcf2d1b | 2946 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2947 | if (is_tdp && huge_page_disallowed && |
2948 | req_level >= it.level) | |
b8e8c830 | 2949 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2950 | } |
2951 | } | |
3fcf2d1b PB |
2952 | |
2953 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2954 | write, level, base_gfn, pfn, prefault, | |
2955 | map_writable); | |
12703759 SC |
2956 | if (ret == RET_PF_SPURIOUS) |
2957 | return ret; | |
2958 | ||
3fcf2d1b PB |
2959 | direct_pte_prefetch(vcpu, it.sptep); |
2960 | ++vcpu->stat.pf_fixed; | |
2961 | return ret; | |
6aa8b732 AK |
2962 | } |
2963 | ||
77db5cbd | 2964 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2965 | { |
585a8b9b | 2966 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2967 | } |
2968 | ||
ba049e93 | 2969 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2970 | { |
4d8b81ab XG |
2971 | /* |
2972 | * Do not cache the mmio info caused by writing the readonly gfn | |
2973 | * into the spte otherwise read access on readonly gfn also can | |
2974 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2975 | */ |
2976 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2977 | return RET_PF_EMULATE; |
4d8b81ab | 2978 | |
e6c1502b | 2979 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2980 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2981 | return RET_PF_RETRY; |
d7c55201 | 2982 | } |
edba23e5 | 2983 | |
2c151b25 | 2984 | return -EFAULT; |
bf998156 HY |
2985 | } |
2986 | ||
d7c55201 | 2987 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2988 | kvm_pfn_t pfn, unsigned int access, |
2989 | int *ret_val) | |
d7c55201 | 2990 | { |
d7c55201 | 2991 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2992 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2993 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2994 | return true; |
d7c55201 XG |
2995 | } |
2996 | ||
30ab5901 | 2997 | if (unlikely(is_noslot_pfn(pfn))) { |
4af77151 SC |
2998 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2999 | access & shadow_mmio_access_mask); | |
30ab5901 SC |
3000 | /* |
3001 | * If MMIO caching is disabled, emulate immediately without | |
3002 | * touching the shadow page tables as attempting to install an | |
3003 | * MMIO SPTE will just be an expensive nop. | |
3004 | */ | |
3005 | if (unlikely(!shadow_mmio_value)) { | |
3006 | *ret_val = RET_PF_EMULATE; | |
3007 | return true; | |
3008 | } | |
3009 | } | |
d7c55201 | 3010 | |
798e88b3 | 3011 | return false; |
d7c55201 XG |
3012 | } |
3013 | ||
e5552fd2 | 3014 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3015 | { |
1c118b82 XG |
3016 | /* |
3017 | * Do not fix the mmio spte with invalid generation number which | |
3018 | * need to be updated by slow page fault path. | |
3019 | */ | |
3020 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3021 | return false; | |
3022 | ||
f160c7b7 JS |
3023 | /* See if the page fault is due to an NX violation */ |
3024 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3025 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3026 | return false; | |
3027 | ||
c7ba5b48 | 3028 | /* |
f160c7b7 JS |
3029 | * #PF can be fast if: |
3030 | * 1. The shadow page table entry is not present, which could mean that | |
3031 | * the fault is potentially caused by access tracking (if enabled). | |
3032 | * 2. The shadow page table entry is present and the fault | |
3033 | * is caused by write-protect, that means we just need change the W | |
3034 | * bit of the spte which can be done out of mmu-lock. | |
3035 | * | |
3036 | * However, if access tracking is disabled we know that a non-present | |
3037 | * page must be a genuine page fault where we have to create a new SPTE. | |
3038 | * So, if access tracking is disabled, we return true only for write | |
3039 | * accesses to a present page. | |
c7ba5b48 | 3040 | */ |
c7ba5b48 | 3041 | |
f160c7b7 JS |
3042 | return shadow_acc_track_mask != 0 || |
3043 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3044 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3045 | } |
3046 | ||
97dceba2 JS |
3047 | /* |
3048 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3049 | * someone else modified the SPTE from its original value. | |
3050 | */ | |
c7ba5b48 | 3051 | static bool |
92a476cb | 3052 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3053 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3054 | { |
c7ba5b48 XG |
3055 | gfn_t gfn; |
3056 | ||
3057 | WARN_ON(!sp->role.direct); | |
3058 | ||
9b51a630 KH |
3059 | /* |
3060 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3061 | * order to eliminate unnecessary PML logging. See comments in | |
3062 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3063 | * enabled, so we do not do this. This might result in the same GPA | |
3064 | * to be logged in PML buffer again when the write really happens, and | |
3065 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3066 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3067 | * so non-PML cases won't be impacted. | |
3068 | * | |
3069 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3070 | */ | |
f160c7b7 | 3071 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3072 | return false; |
3073 | ||
d3e328f2 | 3074 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3075 | /* |
3076 | * The gfn of direct spte is stable since it is | |
3077 | * calculated by sp->gfn. | |
3078 | */ | |
3079 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3080 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3081 | } | |
c7ba5b48 XG |
3082 | |
3083 | return true; | |
3084 | } | |
3085 | ||
d3e328f2 JS |
3086 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3087 | { | |
3088 | if (fault_err_code & PFERR_FETCH_MASK) | |
3089 | return is_executable_pte(spte); | |
3090 | ||
3091 | if (fault_err_code & PFERR_WRITE_MASK) | |
3092 | return is_writable_pte(spte); | |
3093 | ||
3094 | /* Fault was on Read access */ | |
3095 | return spte & PT_PRESENT_MASK; | |
3096 | } | |
3097 | ||
c7ba5b48 | 3098 | /* |
c4371c2a | 3099 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3100 | */ |
c4371c2a SC |
3101 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3102 | u32 error_code) | |
c7ba5b48 XG |
3103 | { |
3104 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3105 | struct kvm_mmu_page *sp; |
c4371c2a | 3106 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3107 | u64 spte = 0ull; |
97dceba2 | 3108 | uint retry_count = 0; |
c7ba5b48 | 3109 | |
e5552fd2 | 3110 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3111 | return ret; |
c7ba5b48 XG |
3112 | |
3113 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3114 | |
97dceba2 | 3115 | do { |
d3e328f2 | 3116 | u64 new_spte; |
c7ba5b48 | 3117 | |
736c291c | 3118 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3119 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3120 | break; |
3121 | ||
ec89e643 SC |
3122 | if (!is_shadow_present_pte(spte)) |
3123 | break; | |
3124 | ||
57354682 | 3125 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3126 | if (!is_last_spte(spte, sp->role.level)) |
3127 | break; | |
c7ba5b48 | 3128 | |
97dceba2 | 3129 | /* |
f160c7b7 JS |
3130 | * Check whether the memory access that caused the fault would |
3131 | * still cause it if it were to be performed right now. If not, | |
3132 | * then this is a spurious fault caused by TLB lazily flushed, | |
3133 | * or some other CPU has already fixed the PTE after the | |
3134 | * current CPU took the fault. | |
97dceba2 JS |
3135 | * |
3136 | * Need not check the access of upper level table entries since | |
3137 | * they are always ACC_ALL. | |
3138 | */ | |
d3e328f2 | 3139 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3140 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3141 | break; |
3142 | } | |
f160c7b7 | 3143 | |
d3e328f2 JS |
3144 | new_spte = spte; |
3145 | ||
3146 | if (is_access_track_spte(spte)) | |
3147 | new_spte = restore_acc_track_spte(new_spte); | |
3148 | ||
3149 | /* | |
3150 | * Currently, to simplify the code, write-protection can | |
3151 | * be removed in the fast path only if the SPTE was | |
3152 | * write-protected for dirty-logging or access tracking. | |
3153 | */ | |
3154 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3155 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3156 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3157 | |
3158 | /* | |
d3e328f2 JS |
3159 | * Do not fix write-permission on the large spte. Since |
3160 | * we only dirty the first page into the dirty-bitmap in | |
3161 | * fast_pf_fix_direct_spte(), other pages are missed | |
3162 | * if its slot has dirty logging enabled. | |
3163 | * | |
3164 | * Instead, we let the slow page fault path create a | |
3165 | * normal spte to fix the access. | |
3166 | * | |
3167 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3168 | */ |
3bae0459 | 3169 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3170 | break; |
97dceba2 | 3171 | } |
c7ba5b48 | 3172 | |
f160c7b7 | 3173 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3174 | if (new_spte == spte || |
3175 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3176 | break; |
3177 | ||
3178 | /* | |
3179 | * Currently, fast page fault only works for direct mapping | |
3180 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3181 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3182 | */ |
c4371c2a SC |
3183 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3184 | new_spte)) { | |
3185 | ret = RET_PF_FIXED; | |
97dceba2 | 3186 | break; |
c4371c2a | 3187 | } |
97dceba2 JS |
3188 | |
3189 | if (++retry_count > 4) { | |
3190 | printk_once(KERN_WARNING | |
3191 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3192 | break; | |
3193 | } | |
3194 | ||
97dceba2 | 3195 | } while (true); |
c126d94f | 3196 | |
736c291c | 3197 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3198 | spte, ret); |
c7ba5b48 XG |
3199 | walk_shadow_page_lockless_end(vcpu); |
3200 | ||
c4371c2a | 3201 | return ret; |
c7ba5b48 XG |
3202 | } |
3203 | ||
74b566e6 JS |
3204 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3205 | struct list_head *invalid_list) | |
17ac10ad | 3206 | { |
4db35314 | 3207 | struct kvm_mmu_page *sp; |
17ac10ad | 3208 | |
74b566e6 | 3209 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3210 | return; |
35af577a | 3211 | |
e47c4aee | 3212 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a | 3213 | |
2bdb3d84 | 3214 | if (is_tdp_mmu_page(sp)) |
6103bc07 | 3215 | kvm_tdp_mmu_put_root(kvm, sp, false); |
76eb54e7 BG |
3216 | else if (!--sp->root_count && sp->role.invalid) |
3217 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3218 | |
74b566e6 JS |
3219 | *root_hpa = INVALID_PAGE; |
3220 | } | |
3221 | ||
08fb59d8 | 3222 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3223 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3224 | ulong roots_to_free) | |
74b566e6 | 3225 | { |
4d710de9 | 3226 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3227 | int i; |
3228 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3229 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3230 | |
b94742c9 | 3231 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3232 | |
08fb59d8 | 3233 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3234 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3235 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3236 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3237 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3238 | break; | |
3239 | ||
3240 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3241 | return; | |
3242 | } | |
35af577a | 3243 | |
531810ca | 3244 | write_lock(&kvm->mmu_lock); |
17ac10ad | 3245 | |
b94742c9 JS |
3246 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3247 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3248 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3249 | &invalid_list); |
7c390d35 | 3250 | |
08fb59d8 JS |
3251 | if (free_active_root) { |
3252 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3253 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3254 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
04d45551 | 3255 | } else if (mmu->pae_root) { |
c834e5e4 SC |
3256 | for (i = 0; i < 4; ++i) { |
3257 | if (!IS_VALID_PAE_ROOT(mmu->pae_root[i])) | |
3258 | continue; | |
3259 | ||
3260 | mmu_free_root_page(kvm, &mmu->pae_root[i], | |
3261 | &invalid_list); | |
3262 | mmu->pae_root[i] = INVALID_PAE_ROOT; | |
3263 | } | |
08fb59d8 | 3264 | } |
04d45551 | 3265 | mmu->root_hpa = INVALID_PAGE; |
be01e8e2 | 3266 | mmu->root_pgd = 0; |
17ac10ad | 3267 | } |
74b566e6 | 3268 | |
4d710de9 | 3269 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 3270 | write_unlock(&kvm->mmu_lock); |
17ac10ad | 3271 | } |
74b566e6 | 3272 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3273 | |
25b62c62 SC |
3274 | void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3275 | { | |
3276 | unsigned long roots_to_free = 0; | |
3277 | hpa_t root_hpa; | |
3278 | int i; | |
3279 | ||
3280 | /* | |
3281 | * This should not be called while L2 is active, L2 can't invalidate | |
3282 | * _only_ its own roots, e.g. INVVPID unconditionally exits. | |
3283 | */ | |
3284 | WARN_ON_ONCE(mmu->mmu_role.base.guest_mode); | |
3285 | ||
3286 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
3287 | root_hpa = mmu->prev_roots[i].hpa; | |
3288 | if (!VALID_PAGE(root_hpa)) | |
3289 | continue; | |
3290 | ||
3291 | if (!to_shadow_page(root_hpa) || | |
3292 | to_shadow_page(root_hpa)->role.guest_mode) | |
3293 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
3294 | } | |
3295 | ||
3296 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
3297 | } | |
3298 | EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots); | |
3299 | ||
3300 | ||
8986ecc0 MT |
3301 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3302 | { | |
3303 | int ret = 0; | |
3304 | ||
995decb6 | 3305 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3306 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3307 | ret = 1; |
3308 | } | |
3309 | ||
3310 | return ret; | |
3311 | } | |
3312 | ||
8123f265 SC |
3313 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3314 | u8 level, bool direct) | |
651dd37a JR |
3315 | { |
3316 | struct kvm_mmu_page *sp; | |
8123f265 | 3317 | |
8123f265 SC |
3318 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); |
3319 | ++sp->root_count; | |
3320 | ||
8123f265 SC |
3321 | return __pa(sp->spt); |
3322 | } | |
3323 | ||
3324 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3325 | { | |
b37233c9 SC |
3326 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
3327 | u8 shadow_root_level = mmu->shadow_root_level; | |
8123f265 | 3328 | hpa_t root; |
7ebaf15e | 3329 | unsigned i; |
4a38162e PB |
3330 | int r; |
3331 | ||
3332 | write_lock(&vcpu->kvm->mmu_lock); | |
3333 | r = make_mmu_pages_available(vcpu); | |
3334 | if (r < 0) | |
3335 | goto out_unlock; | |
651dd37a | 3336 | |
897218ff | 3337 | if (is_tdp_mmu_enabled(vcpu->kvm)) { |
02c00b3a | 3338 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); |
b37233c9 | 3339 | mmu->root_hpa = root; |
02c00b3a | 3340 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { |
6e6ec584 | 3341 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true); |
b37233c9 | 3342 | mmu->root_hpa = root; |
8123f265 | 3343 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { |
4a38162e PB |
3344 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3345 | r = -EIO; | |
3346 | goto out_unlock; | |
3347 | } | |
73ad1606 | 3348 | |
651dd37a | 3349 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3350 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
651dd37a | 3351 | |
8123f265 SC |
3352 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3353 | i << 30, PT32_ROOT_LEVEL, true); | |
17e368d9 SC |
3354 | mmu->pae_root[i] = root | PT_PRESENT_MASK | |
3355 | shadow_me_mask; | |
651dd37a | 3356 | } |
b37233c9 | 3357 | mmu->root_hpa = __pa(mmu->pae_root); |
73ad1606 SC |
3358 | } else { |
3359 | WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level); | |
4a38162e PB |
3360 | r = -EIO; |
3361 | goto out_unlock; | |
73ad1606 | 3362 | } |
3651c7fc | 3363 | |
be01e8e2 | 3364 | /* root_pgd is ignored for direct MMUs. */ |
b37233c9 | 3365 | mmu->root_pgd = 0; |
4a38162e PB |
3366 | out_unlock: |
3367 | write_unlock(&vcpu->kvm->mmu_lock); | |
3368 | return r; | |
651dd37a JR |
3369 | } |
3370 | ||
3371 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3372 | { |
b37233c9 | 3373 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
6e0918ae | 3374 | u64 pdptrs[4], pm_mask; |
be01e8e2 | 3375 | gfn_t root_gfn, root_pgd; |
8123f265 | 3376 | hpa_t root; |
4a38162e PB |
3377 | unsigned i; |
3378 | int r; | |
3bb65a22 | 3379 | |
b37233c9 | 3380 | root_pgd = mmu->get_guest_pgd(vcpu); |
be01e8e2 | 3381 | root_gfn = root_pgd >> PAGE_SHIFT; |
17ac10ad | 3382 | |
651dd37a JR |
3383 | if (mmu_check_root(vcpu, root_gfn)) |
3384 | return 1; | |
3385 | ||
4a38162e PB |
3386 | /* |
3387 | * On SVM, reading PDPTRs might access guest memory, which might fault | |
3388 | * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock. | |
3389 | */ | |
6e0918ae SC |
3390 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
3391 | for (i = 0; i < 4; ++i) { | |
3392 | pdptrs[i] = mmu->get_pdptr(vcpu, i); | |
3393 | if (!(pdptrs[i] & PT_PRESENT_MASK)) | |
3394 | continue; | |
3395 | ||
3396 | if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT)) | |
3397 | return 1; | |
3398 | } | |
3399 | } | |
3400 | ||
d501f747 BG |
3401 | r = alloc_all_memslots_rmaps(vcpu->kvm); |
3402 | if (r) | |
3403 | return r; | |
3404 | ||
4a38162e PB |
3405 | write_lock(&vcpu->kvm->mmu_lock); |
3406 | r = make_mmu_pages_available(vcpu); | |
3407 | if (r < 0) | |
3408 | goto out_unlock; | |
3409 | ||
651dd37a JR |
3410 | /* |
3411 | * Do we shadow a long mode page table? If so we need to | |
3412 | * write-protect the guests page table root. | |
3413 | */ | |
b37233c9 | 3414 | if (mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3415 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
b37233c9 | 3416 | mmu->shadow_root_level, false); |
b37233c9 | 3417 | mmu->root_hpa = root; |
be01e8e2 | 3418 | goto set_root_pgd; |
17ac10ad | 3419 | } |
f87f9288 | 3420 | |
4a38162e PB |
3421 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3422 | r = -EIO; | |
3423 | goto out_unlock; | |
3424 | } | |
73ad1606 | 3425 | |
651dd37a JR |
3426 | /* |
3427 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3428 | * or a PAE 3-level page table. In either case we need to be aware that |
3429 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3430 | */ |
17e368d9 | 3431 | pm_mask = PT_PRESENT_MASK | shadow_me_mask; |
748e52b9 | 3432 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3433 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3434 | ||
03ca4589 | 3435 | if (WARN_ON_ONCE(!mmu->pml4_root)) { |
4a38162e PB |
3436 | r = -EIO; |
3437 | goto out_unlock; | |
3438 | } | |
73ad1606 | 3439 | |
03ca4589 | 3440 | mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask; |
04d45551 SC |
3441 | } |
3442 | ||
17ac10ad | 3443 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3444 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
6e6ec584 | 3445 | |
b37233c9 | 3446 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
6e0918ae | 3447 | if (!(pdptrs[i] & PT_PRESENT_MASK)) { |
c834e5e4 | 3448 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
417726a3 AK |
3449 | continue; |
3450 | } | |
6e0918ae | 3451 | root_gfn = pdptrs[i] >> PAGE_SHIFT; |
5a7388c2 | 3452 | } |
8facbbff | 3453 | |
8123f265 SC |
3454 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3455 | PT32_ROOT_LEVEL, false); | |
b37233c9 | 3456 | mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3457 | } |
81407ca5 | 3458 | |
ba0a194f | 3459 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
03ca4589 | 3460 | mmu->root_hpa = __pa(mmu->pml4_root); |
ba0a194f SC |
3461 | else |
3462 | mmu->root_hpa = __pa(mmu->pae_root); | |
81407ca5 | 3463 | |
be01e8e2 | 3464 | set_root_pgd: |
b37233c9 | 3465 | mmu->root_pgd = root_pgd; |
4a38162e PB |
3466 | out_unlock: |
3467 | write_unlock(&vcpu->kvm->mmu_lock); | |
ad7dc69a | 3468 | |
8986ecc0 | 3469 | return 0; |
17ac10ad AK |
3470 | } |
3471 | ||
748e52b9 SC |
3472 | static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) |
3473 | { | |
3474 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
03ca4589 | 3475 | u64 *pml4_root, *pae_root; |
81407ca5 JR |
3476 | |
3477 | /* | |
748e52b9 SC |
3478 | * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP |
3479 | * tables are allocated and initialized at root creation as there is no | |
3480 | * equivalent level in the guest's NPT to shadow. Allocate the tables | |
3481 | * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare. | |
81407ca5 | 3482 | */ |
748e52b9 SC |
3483 | if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL || |
3484 | mmu->shadow_root_level < PT64_ROOT_4LEVEL) | |
3485 | return 0; | |
81407ca5 | 3486 | |
748e52b9 SC |
3487 | /* |
3488 | * This mess only works with 4-level paging and needs to be updated to | |
3489 | * work with 5-level paging. | |
3490 | */ | |
3491 | if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) | |
3492 | return -EIO; | |
81407ca5 | 3493 | |
03ca4589 | 3494 | if (mmu->pae_root && mmu->pml4_root) |
748e52b9 | 3495 | return 0; |
81407ca5 | 3496 | |
748e52b9 SC |
3497 | /* |
3498 | * The special roots should always be allocated in concert. Yell and | |
3499 | * bail if KVM ends up in a state where only one of the roots is valid. | |
3500 | */ | |
03ca4589 | 3501 | if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) |
748e52b9 | 3502 | return -EIO; |
81407ca5 | 3503 | |
4a98623d SC |
3504 | /* |
3505 | * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and | |
3506 | * doesn't need to be decrypted. | |
3507 | */ | |
748e52b9 SC |
3508 | pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3509 | if (!pae_root) | |
3510 | return -ENOMEM; | |
81407ca5 | 3511 | |
03ca4589 SC |
3512 | pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3513 | if (!pml4_root) { | |
748e52b9 SC |
3514 | free_page((unsigned long)pae_root); |
3515 | return -ENOMEM; | |
81407ca5 JR |
3516 | } |
3517 | ||
748e52b9 | 3518 | mmu->pae_root = pae_root; |
03ca4589 | 3519 | mmu->pml4_root = pml4_root; |
ad7dc69a | 3520 | |
8986ecc0 | 3521 | return 0; |
17ac10ad AK |
3522 | } |
3523 | ||
578e1c4d | 3524 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3525 | { |
3526 | int i; | |
3527 | struct kvm_mmu_page *sp; | |
3528 | ||
44dd3ffa | 3529 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3530 | return; |
3531 | ||
44dd3ffa | 3532 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3533 | return; |
6903074c | 3534 | |
56f17dd3 | 3535 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3536 | |
44dd3ffa VK |
3537 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3538 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3539 | sp = to_shadow_page(root); |
578e1c4d JS |
3540 | |
3541 | /* | |
3542 | * Even if another CPU was marking the SP as unsync-ed | |
3543 | * simultaneously, any guest page table changes are not | |
3544 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3545 | * flush strictly after those changes are made. We only need to | |
3546 | * ensure that the other CPU sets these flags before any actual | |
3547 | * changes to the page tables are made. The comments in | |
0337f585 SC |
3548 | * mmu_try_to_unsync_pages() describe what could go wrong if |
3549 | * this requirement isn't satisfied. | |
578e1c4d JS |
3550 | */ |
3551 | if (!smp_load_acquire(&sp->unsync) && | |
3552 | !smp_load_acquire(&sp->unsync_children)) | |
3553 | return; | |
3554 | ||
531810ca | 3555 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3556 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3557 | ||
0ba73cda | 3558 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3559 | |
0375f7fa | 3560 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3561 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3562 | return; |
3563 | } | |
578e1c4d | 3564 | |
531810ca | 3565 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3566 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3567 | ||
0ba73cda | 3568 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3569 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3570 | |
c834e5e4 | 3571 | if (IS_VALID_PAE_ROOT(root)) { |
0ba73cda | 3572 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3573 | sp = to_shadow_page(root); |
0ba73cda MT |
3574 | mmu_sync_children(vcpu, sp); |
3575 | } | |
3576 | } | |
0ba73cda | 3577 | |
578e1c4d | 3578 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3579 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3580 | } |
3581 | ||
736c291c | 3582 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3583 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3584 | { |
ab9ae313 AK |
3585 | if (exception) |
3586 | exception->error_code = 0; | |
6aa8b732 AK |
3587 | return vaddr; |
3588 | } | |
3589 | ||
736c291c | 3590 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3591 | u32 access, |
3592 | struct x86_exception *exception) | |
6539e738 | 3593 | { |
ab9ae313 AK |
3594 | if (exception) |
3595 | exception->error_code = 0; | |
54987b7a | 3596 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3597 | } |
3598 | ||
ded58749 | 3599 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3600 | { |
9034e6e8 PB |
3601 | /* |
3602 | * A nested guest cannot use the MMIO cache if it is using nested | |
3603 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3604 | */ | |
3605 | if (mmu_is_nested(vcpu)) | |
3606 | return false; | |
3607 | ||
ce88decf XG |
3608 | if (direct) |
3609 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3610 | ||
3611 | return vcpu_match_mmio_gva(vcpu, addr); | |
3612 | } | |
3613 | ||
95fb5b02 BG |
3614 | /* |
3615 | * Return the level of the lowest level SPTE added to sptes. | |
3616 | * That SPTE may be non-present. | |
3617 | */ | |
39b4d43e | 3618 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level) |
ce88decf XG |
3619 | { |
3620 | struct kvm_shadow_walk_iterator iterator; | |
2aa07893 | 3621 | int leaf = -1; |
95fb5b02 | 3622 | u64 spte; |
ce88decf XG |
3623 | |
3624 | walk_shadow_page_lockless_begin(vcpu); | |
47ab8751 | 3625 | |
39b4d43e SC |
3626 | for (shadow_walk_init(&iterator, vcpu, addr), |
3627 | *root_level = iterator.level; | |
47ab8751 XG |
3628 | shadow_walk_okay(&iterator); |
3629 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3630 | leaf = iterator.level; |
47ab8751 XG |
3631 | spte = mmu_spte_get_lockless(iterator.sptep); |
3632 | ||
dde81f94 | 3633 | sptes[leaf] = spte; |
47ab8751 | 3634 | |
ce88decf XG |
3635 | if (!is_shadow_present_pte(spte)) |
3636 | break; | |
95fb5b02 BG |
3637 | } |
3638 | ||
3639 | walk_shadow_page_lockless_end(vcpu); | |
3640 | ||
3641 | return leaf; | |
3642 | } | |
3643 | ||
9aa41879 | 3644 | /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */ |
95fb5b02 BG |
3645 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) |
3646 | { | |
dde81f94 | 3647 | u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; |
95fb5b02 | 3648 | struct rsvd_bits_validate *rsvd_check; |
39b4d43e | 3649 | int root, leaf, level; |
95fb5b02 BG |
3650 | bool reserved = false; |
3651 | ||
63c0cac9 | 3652 | if (is_tdp_mmu(vcpu->arch.mmu)) |
39b4d43e | 3653 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3654 | else |
39b4d43e | 3655 | leaf = get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3656 | |
2aa07893 SC |
3657 | if (unlikely(leaf < 0)) { |
3658 | *sptep = 0ull; | |
3659 | return reserved; | |
3660 | } | |
3661 | ||
9aa41879 SC |
3662 | *sptep = sptes[leaf]; |
3663 | ||
3664 | /* | |
3665 | * Skip reserved bits checks on the terminal leaf if it's not a valid | |
3666 | * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by | |
3667 | * design, always have reserved bits set. The purpose of the checks is | |
3668 | * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs. | |
3669 | */ | |
3670 | if (!is_shadow_present_pte(sptes[leaf])) | |
3671 | leaf++; | |
95fb5b02 BG |
3672 | |
3673 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3674 | ||
9aa41879 | 3675 | for (level = root; level >= leaf; level--) |
961f8445 | 3676 | reserved |= is_rsvd_spte(rsvd_check, sptes[level], level); |
47ab8751 | 3677 | |
47ab8751 | 3678 | if (reserved) { |
bb4cdf3a | 3679 | pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n", |
47ab8751 | 3680 | __func__, addr); |
95fb5b02 | 3681 | for (level = root; level >= leaf; level--) |
bb4cdf3a SC |
3682 | pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx", |
3683 | sptes[level], level, | |
961f8445 | 3684 | get_rsvd_bits(rsvd_check, sptes[level], level)); |
47ab8751 | 3685 | } |
ddce6208 | 3686 | |
47ab8751 | 3687 | return reserved; |
ce88decf XG |
3688 | } |
3689 | ||
e08d26f0 | 3690 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3691 | { |
3692 | u64 spte; | |
47ab8751 | 3693 | bool reserved; |
ce88decf | 3694 | |
ded58749 | 3695 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3696 | return RET_PF_EMULATE; |
ce88decf | 3697 | |
95fb5b02 | 3698 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3699 | if (WARN_ON(reserved)) |
9b8ebbdb | 3700 | return -EINVAL; |
ce88decf XG |
3701 | |
3702 | if (is_mmio_spte(spte)) { | |
3703 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3704 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3705 | |
54bf36aa | 3706 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3707 | return RET_PF_INVALID; |
f8f55942 | 3708 | |
ce88decf XG |
3709 | if (direct) |
3710 | addr = 0; | |
4f022648 XG |
3711 | |
3712 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3713 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3714 | return RET_PF_EMULATE; |
ce88decf XG |
3715 | } |
3716 | ||
ce88decf XG |
3717 | /* |
3718 | * If the page table is zapped by other cpus, let CPU fault again on | |
3719 | * the address. | |
3720 | */ | |
9b8ebbdb | 3721 | return RET_PF_RETRY; |
ce88decf | 3722 | } |
ce88decf | 3723 | |
3d0c27ad XG |
3724 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3725 | u32 error_code, gfn_t gfn) | |
3726 | { | |
3727 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3728 | return false; | |
3729 | ||
3730 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3731 | !(error_code & PFERR_WRITE_MASK)) | |
3732 | return false; | |
3733 | ||
3734 | /* | |
3735 | * guest is writing the page which is write tracked which can | |
3736 | * not be fixed by page fault handler. | |
3737 | */ | |
3738 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3739 | return true; | |
3740 | ||
3741 | return false; | |
3742 | } | |
3743 | ||
e5691a81 XG |
3744 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3745 | { | |
3746 | struct kvm_shadow_walk_iterator iterator; | |
3747 | u64 spte; | |
3748 | ||
e5691a81 XG |
3749 | walk_shadow_page_lockless_begin(vcpu); |
3750 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3751 | clear_sp_write_flooding_count(iterator.sptep); | |
3752 | if (!is_shadow_present_pte(spte)) | |
3753 | break; | |
3754 | } | |
3755 | walk_shadow_page_lockless_end(vcpu); | |
3756 | } | |
3757 | ||
e8c22266 VK |
3758 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3759 | gfn_t gfn) | |
af585b92 GN |
3760 | { |
3761 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3762 | |
7c90705b | 3763 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3764 | arch.gfn = gfn; |
44dd3ffa | 3765 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3766 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3767 | |
9f1a8526 SC |
3768 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3769 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3770 | } |
3771 | ||
78b2c54a | 3772 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
4a42d848 DS |
3773 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva, |
3774 | bool write, bool *writable) | |
af585b92 | 3775 | { |
c36b7150 | 3776 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3777 | bool async; |
3778 | ||
e0c37868 SC |
3779 | /* |
3780 | * Retry the page fault if the gfn hit a memslot that is being deleted | |
3781 | * or moved. This ensures any existing SPTEs for the old memslot will | |
3782 | * be zapped before KVM inserts a new MMIO SPTE for the gfn. | |
3783 | */ | |
3784 | if (slot && (slot->flags & KVM_MEMSLOT_INVALID)) | |
3785 | return true; | |
3786 | ||
c36b7150 PB |
3787 | /* Don't expose private memslots to L2. */ |
3788 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3789 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3790 | *writable = false; |
3a2936de JM |
3791 | return false; |
3792 | } | |
3793 | ||
3520469d | 3794 | async = false; |
4a42d848 DS |
3795 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, |
3796 | write, writable, hva); | |
af585b92 GN |
3797 | if (!async) |
3798 | return false; /* *pfn has correct page already */ | |
3799 | ||
9bc1f09f | 3800 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3801 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3802 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3803 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3804 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3805 | return true; | |
9f1a8526 | 3806 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3807 | return true; |
3808 | } | |
3809 | ||
4a42d848 DS |
3810 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, |
3811 | write, writable, hva); | |
af585b92 GN |
3812 | return false; |
3813 | } | |
3814 | ||
0f90e1c1 SC |
3815 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3816 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3817 | { |
63c0cac9 | 3818 | bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu); |
367fd790 | 3819 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3820 | bool map_writable; |
6aa8b732 | 3821 | |
0f90e1c1 SC |
3822 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3823 | unsigned long mmu_seq; | |
3824 | kvm_pfn_t pfn; | |
4a42d848 | 3825 | hva_t hva; |
83f06fa7 | 3826 | int r; |
ce88decf | 3827 | |
3d0c27ad | 3828 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3829 | return RET_PF_EMULATE; |
ce88decf | 3830 | |
0b873fd7 | 3831 | if (!is_tdp_mmu_fault) { |
bb18842e BG |
3832 | r = fast_page_fault(vcpu, gpa, error_code); |
3833 | if (r != RET_PF_INVALID) | |
3834 | return r; | |
3835 | } | |
83291445 | 3836 | |
378f5cd6 | 3837 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3838 | if (r) |
3839 | return r; | |
714b93da | 3840 | |
367fd790 SC |
3841 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3842 | smp_rmb(); | |
3843 | ||
4a42d848 DS |
3844 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva, |
3845 | write, &map_writable)) | |
367fd790 SC |
3846 | return RET_PF_RETRY; |
3847 | ||
0f90e1c1 | 3848 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3849 | return r; |
6aa8b732 | 3850 | |
367fd790 | 3851 | r = RET_PF_RETRY; |
a2855afc | 3852 | |
0b873fd7 | 3853 | if (is_tdp_mmu_fault) |
a2855afc BG |
3854 | read_lock(&vcpu->kvm->mmu_lock); |
3855 | else | |
3856 | write_lock(&vcpu->kvm->mmu_lock); | |
3857 | ||
4a42d848 | 3858 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
367fd790 | 3859 | goto out_unlock; |
7bd7ded6 SC |
3860 | r = make_mmu_pages_available(vcpu); |
3861 | if (r) | |
367fd790 | 3862 | goto out_unlock; |
bb18842e | 3863 | |
0b873fd7 | 3864 | if (is_tdp_mmu_fault) |
bb18842e BG |
3865 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, |
3866 | pfn, prefault); | |
3867 | else | |
3868 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3869 | prefault, is_tdp); | |
0f90e1c1 | 3870 | |
367fd790 | 3871 | out_unlock: |
0b873fd7 | 3872 | if (is_tdp_mmu_fault) |
a2855afc BG |
3873 | read_unlock(&vcpu->kvm->mmu_lock); |
3874 | else | |
3875 | write_unlock(&vcpu->kvm->mmu_lock); | |
367fd790 SC |
3876 | kvm_release_pfn_clean(pfn); |
3877 | return r; | |
6aa8b732 AK |
3878 | } |
3879 | ||
0f90e1c1 SC |
3880 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3881 | u32 error_code, bool prefault) | |
3882 | { | |
3883 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3884 | ||
3885 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3886 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3887 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3888 | } |
3889 | ||
1261bfa3 | 3890 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3891 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3892 | { |
3893 | int r = 1; | |
9ce372b3 | 3894 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3895 | |
736c291c SC |
3896 | #ifndef CONFIG_X86_64 |
3897 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3898 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3899 | return -EFAULT; | |
3900 | #endif | |
3901 | ||
c595ceee | 3902 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3903 | if (!flags) { |
1261bfa3 WL |
3904 | trace_kvm_page_fault(fault_address, error_code); |
3905 | ||
d0006530 | 3906 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3907 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3908 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3909 | insn_len); | |
9ce372b3 | 3910 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3911 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3912 | local_irq_disable(); |
6bca69ad | 3913 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3914 | local_irq_enable(); |
9ce372b3 VK |
3915 | } else { |
3916 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3917 | } |
9ce372b3 | 3918 | |
1261bfa3 WL |
3919 | return r; |
3920 | } | |
3921 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3922 | ||
7a02674d SC |
3923 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3924 | bool prefault) | |
fb72d167 | 3925 | { |
cb9b88c6 | 3926 | int max_level; |
fb72d167 | 3927 | |
e662ec3e | 3928 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3929 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3930 | max_level--) { |
3931 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3932 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3933 | |
cb9b88c6 SC |
3934 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3935 | break; | |
fd136902 | 3936 | } |
852e3c19 | 3937 | |
0f90e1c1 SC |
3938 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3939 | max_level, true); | |
fb72d167 JR |
3940 | } |
3941 | ||
84a16226 | 3942 | static void nonpaging_init_context(struct kvm_mmu *context) |
6aa8b732 | 3943 | { |
6aa8b732 | 3944 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3945 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3946 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3947 | context->invlpg = NULL; |
c5a78f2b | 3948 | context->direct_map = true; |
6aa8b732 AK |
3949 | } |
3950 | ||
be01e8e2 | 3951 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3952 | union kvm_mmu_page_role role) |
3953 | { | |
be01e8e2 | 3954 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3955 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3956 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3957 | } |
3958 | ||
b94742c9 | 3959 | /* |
be01e8e2 | 3960 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3961 | * The current root is also inserted into the cache. |
3962 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3963 | * returned. | |
3964 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3965 | * false is returned. This root should now be freed by the caller. | |
3966 | */ | |
be01e8e2 | 3967 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3968 | union kvm_mmu_page_role new_role) |
3969 | { | |
3970 | uint i; | |
3971 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3972 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3973 | |
be01e8e2 | 3974 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3975 | root.hpa = mmu->root_hpa; |
3976 | ||
be01e8e2 | 3977 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3978 | return true; |
3979 | ||
b94742c9 JS |
3980 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3981 | swap(root, mmu->prev_roots[i]); | |
3982 | ||
be01e8e2 | 3983 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3984 | break; |
3985 | } | |
3986 | ||
3987 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3988 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
3989 | |
3990 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
3991 | } | |
3992 | ||
be01e8e2 | 3993 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 3994 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3995 | { |
44dd3ffa | 3996 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
3997 | |
3998 | /* | |
3999 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4000 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4001 | * later if necessary. | |
4002 | */ | |
4003 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 4004 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 4005 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
4006 | |
4007 | return false; | |
6aa8b732 AK |
4008 | } |
4009 | ||
be01e8e2 | 4010 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b5129100 | 4011 | union kvm_mmu_page_role new_role) |
6aa8b732 | 4012 | { |
be01e8e2 | 4013 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
4014 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
4015 | return; | |
4016 | } | |
4017 | ||
4018 | /* | |
4019 | * It's possible that the cached previous root page is obsolete because | |
4020 | * of a change in the MMU generation number. However, changing the | |
4021 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
4022 | * free the root set here and allocate a new one. | |
4023 | */ | |
4024 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
4025 | ||
b5129100 | 4026 | if (force_flush_and_sync_on_reuse) { |
b869855b SC |
4027 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
4028 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
b5129100 | 4029 | } |
b869855b SC |
4030 | |
4031 | /* | |
4032 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
4033 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
4034 | * valid. So clear any cached MMIO info even when we don't need to sync | |
4035 | * the shadow page tables. | |
4036 | */ | |
4037 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
4038 | ||
daa5b6c1 BG |
4039 | /* |
4040 | * If this is a direct root page, it doesn't have a write flooding | |
4041 | * count. Otherwise, clear the write flooding count. | |
4042 | */ | |
4043 | if (!new_role.direct) | |
4044 | __clear_sp_write_flooding_count( | |
4045 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
4046 | } |
4047 | ||
b5129100 | 4048 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) |
0aab33e4 | 4049 | { |
b5129100 | 4050 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu)); |
0aab33e4 | 4051 | } |
be01e8e2 | 4052 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 4053 | |
5777ed34 JR |
4054 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4055 | { | |
9f8fe504 | 4056 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4057 | } |
4058 | ||
54bf36aa | 4059 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 4060 | unsigned int access, int *nr_present) |
ce88decf XG |
4061 | { |
4062 | if (unlikely(is_mmio_spte(*sptep))) { | |
4063 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4064 | mmu_spte_clear_no_track(sptep); | |
4065 | return true; | |
4066 | } | |
4067 | ||
4068 | (*nr_present)++; | |
54bf36aa | 4069 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4070 | return true; |
4071 | } | |
4072 | ||
4073 | return false; | |
4074 | } | |
4075 | ||
37406aaa NHE |
4076 | #define PTTYPE_EPT 18 /* arbitrary */ |
4077 | #define PTTYPE PTTYPE_EPT | |
4078 | #include "paging_tmpl.h" | |
4079 | #undef PTTYPE | |
4080 | ||
6aa8b732 AK |
4081 | #define PTTYPE 64 |
4082 | #include "paging_tmpl.h" | |
4083 | #undef PTTYPE | |
4084 | ||
4085 | #define PTTYPE 32 | |
4086 | #include "paging_tmpl.h" | |
4087 | #undef PTTYPE | |
4088 | ||
6dc98b86 | 4089 | static void |
b705a277 | 4090 | __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check, |
5b7f575c | 4091 | u64 pa_bits_rsvd, int level, bool nx, bool gbpages, |
6fec2144 | 4092 | bool pse, bool amd) |
82725b20 | 4093 | { |
5f7dde7b | 4094 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4095 | u64 nonleaf_bit8_rsvd = 0; |
5b7f575c | 4096 | u64 high_bits_rsvd; |
82725b20 | 4097 | |
a0a64f50 | 4098 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4099 | |
6dc98b86 | 4100 | if (!gbpages) |
5f7dde7b | 4101 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 | 4102 | |
5b7f575c SC |
4103 | if (level == PT32E_ROOT_LEVEL) |
4104 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62); | |
4105 | else | |
4106 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); | |
4107 | ||
4108 | /* Note, NX doesn't exist in PDPTEs, this is handled below. */ | |
4109 | if (!nx) | |
4110 | high_bits_rsvd |= rsvd_bits(63, 63); | |
4111 | ||
a0c0feb5 PB |
4112 | /* |
4113 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4114 | * leaf entries) on AMD CPUs only. | |
4115 | */ | |
6fec2144 | 4116 | if (amd) |
a0c0feb5 PB |
4117 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4118 | ||
6dc98b86 | 4119 | switch (level) { |
82725b20 DE |
4120 | case PT32_ROOT_LEVEL: |
4121 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4122 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4123 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4124 | rsvd_check->rsvd_bits_mask[1][0] = | |
4125 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4126 | |
6dc98b86 | 4127 | if (!pse) { |
a0a64f50 | 4128 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4129 | break; |
4130 | } | |
4131 | ||
82725b20 DE |
4132 | if (is_cpuid_PSE36()) |
4133 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4134 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4135 | else |
4136 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4137 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4138 | break; |
4139 | case PT32E_ROOT_LEVEL: | |
5b7f575c SC |
4140 | rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) | |
4141 | high_bits_rsvd | | |
4142 | rsvd_bits(5, 8) | | |
4143 | rsvd_bits(1, 2); /* PDPTE */ | |
4144 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */ | |
4145 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */ | |
4146 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4147 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4148 | rsvd_check->rsvd_bits_mask[1][0] = |
4149 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4150 | break; |
855feb67 | 4151 | case PT64_ROOT_5LEVEL: |
5b7f575c SC |
4152 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | |
4153 | nonleaf_bit8_rsvd | | |
4154 | rsvd_bits(7, 7); | |
855feb67 YZ |
4155 | rsvd_check->rsvd_bits_mask[1][4] = |
4156 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4157 | fallthrough; |
2a7266a8 | 4158 | case PT64_ROOT_4LEVEL: |
5b7f575c SC |
4159 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | |
4160 | nonleaf_bit8_rsvd | | |
4161 | rsvd_bits(7, 7); | |
4162 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | | |
4163 | gbpages_bit_rsvd; | |
4164 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; | |
4165 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
a0a64f50 XG |
4166 | rsvd_check->rsvd_bits_mask[1][3] = |
4167 | rsvd_check->rsvd_bits_mask[0][3]; | |
5b7f575c SC |
4168 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | |
4169 | gbpages_bit_rsvd | | |
4170 | rsvd_bits(13, 29); | |
4171 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4172 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4173 | rsvd_check->rsvd_bits_mask[1][0] = |
4174 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4175 | break; |
4176 | } | |
4177 | } | |
4178 | ||
27de9250 SC |
4179 | static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu) |
4180 | { | |
4181 | /* | |
4182 | * If TDP is enabled, let the guest use GBPAGES if they're supported in | |
4183 | * hardware. The hardware page walker doesn't let KVM disable GBPAGES, | |
4184 | * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA | |
4185 | * walk for performance and complexity reasons. Not to mention KVM | |
4186 | * _can't_ solve the problem because GVA->GPA walks aren't visible to | |
4187 | * KVM once a TDP translation is installed. Mimic hardware behavior so | |
4188 | * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. | |
4189 | */ | |
4190 | return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : | |
4191 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); | |
4192 | } | |
4193 | ||
6dc98b86 XG |
4194 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4195 | struct kvm_mmu *context) | |
4196 | { | |
b705a277 | 4197 | __reset_rsvds_bits_mask(&context->guest_rsvd_check, |
5b7f575c | 4198 | vcpu->arch.reserved_gpa_bits, |
90599c28 | 4199 | context->root_level, is_efer_nx(context), |
27de9250 | 4200 | guest_can_use_gbpages(vcpu), |
4e9c0d80 | 4201 | is_cr4_pse(context), |
23493d0a | 4202 | guest_cpuid_is_amd_or_hygon(vcpu)); |
6dc98b86 XG |
4203 | } |
4204 | ||
81b8eebb XG |
4205 | static void |
4206 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4207 | u64 pa_bits_rsvd, bool execonly) |
25d92081 | 4208 | { |
5b7f575c | 4209 | u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); |
951f9fd7 | 4210 | u64 bad_mt_xwr; |
25d92081 | 4211 | |
5b7f575c SC |
4212 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7); |
4213 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7); | |
4214 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6); | |
4215 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6); | |
4216 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
25d92081 YZ |
4217 | |
4218 | /* large page */ | |
855feb67 | 4219 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 | 4220 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
5b7f575c SC |
4221 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29); |
4222 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20); | |
a0a64f50 | 4223 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4224 | |
951f9fd7 PB |
4225 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4226 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4227 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4228 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4229 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4230 | if (!execonly) { | |
4231 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4232 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4233 | } |
951f9fd7 | 4234 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4235 | } |
4236 | ||
81b8eebb XG |
4237 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4238 | struct kvm_mmu *context, bool execonly) | |
4239 | { | |
4240 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
5b7f575c | 4241 | vcpu->arch.reserved_gpa_bits, execonly); |
81b8eebb XG |
4242 | } |
4243 | ||
6f8e65a6 SC |
4244 | static inline u64 reserved_hpa_bits(void) |
4245 | { | |
4246 | return rsvd_bits(shadow_phys_bits, 63); | |
4247 | } | |
4248 | ||
c258b62b XG |
4249 | /* |
4250 | * the page table on host is the shadow page table for the page | |
4251 | * table in guest or amd nested guest, its mmu features completely | |
4252 | * follow the features in guest. | |
4253 | */ | |
16be1d12 SC |
4254 | static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, |
4255 | struct kvm_mmu *context) | |
c258b62b | 4256 | { |
112022bd SC |
4257 | /* |
4258 | * KVM uses NX when TDP is disabled to handle a variety of scenarios, | |
4259 | * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and | |
4260 | * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0. | |
4261 | * The iTLB multi-hit workaround can be toggled at any time, so assume | |
4262 | * NX can be used by any non-nested shadow MMU to avoid having to reset | |
4263 | * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled. | |
4264 | */ | |
90599c28 | 4265 | bool uses_nx = is_efer_nx(context) || !tdp_enabled; |
8c985b2d SC |
4266 | |
4267 | /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */ | |
4268 | bool is_amd = true; | |
4269 | /* KVM doesn't use 2-level page tables for the shadow MMU. */ | |
4270 | bool is_pse = false; | |
ea2800dd BS |
4271 | struct rsvd_bits_validate *shadow_zero_check; |
4272 | int i; | |
5f0b8199 | 4273 | |
8c985b2d SC |
4274 | WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL); |
4275 | ||
ea2800dd | 4276 | shadow_zero_check = &context->shadow_zero_check; |
b705a277 | 4277 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
5f0b8199 | 4278 | context->shadow_root_level, uses_nx, |
27de9250 | 4279 | guest_can_use_gbpages(vcpu), is_pse, is_amd); |
ea2800dd BS |
4280 | |
4281 | if (!shadow_me_mask) | |
4282 | return; | |
4283 | ||
4284 | for (i = context->shadow_root_level; --i >= 0;) { | |
4285 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4286 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4287 | } | |
4288 | ||
c258b62b | 4289 | } |
c258b62b | 4290 | |
6fec2144 PB |
4291 | static inline bool boot_cpu_is_amd(void) |
4292 | { | |
4293 | WARN_ON_ONCE(!tdp_enabled); | |
4294 | return shadow_x_mask == 0; | |
4295 | } | |
4296 | ||
c258b62b XG |
4297 | /* |
4298 | * the direct page table on host, use as much mmu features as | |
4299 | * possible, however, kvm currently does not do execution-protection. | |
4300 | */ | |
4301 | static void | |
4302 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4303 | struct kvm_mmu *context) | |
4304 | { | |
ea2800dd BS |
4305 | struct rsvd_bits_validate *shadow_zero_check; |
4306 | int i; | |
4307 | ||
4308 | shadow_zero_check = &context->shadow_zero_check; | |
4309 | ||
6fec2144 | 4310 | if (boot_cpu_is_amd()) |
b705a277 | 4311 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
c258b62b | 4312 | context->shadow_root_level, false, |
b8291adc | 4313 | boot_cpu_has(X86_FEATURE_GBPAGES), |
8c985b2d | 4314 | false, true); |
c258b62b | 4315 | else |
ea2800dd | 4316 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
6f8e65a6 | 4317 | reserved_hpa_bits(), false); |
c258b62b | 4318 | |
ea2800dd BS |
4319 | if (!shadow_me_mask) |
4320 | return; | |
4321 | ||
4322 | for (i = context->shadow_root_level; --i >= 0;) { | |
4323 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4324 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4325 | } | |
c258b62b XG |
4326 | } |
4327 | ||
4328 | /* | |
4329 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4330 | * is the shadow page table for intel nested guest. | |
4331 | */ | |
4332 | static void | |
4333 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4334 | struct kvm_mmu *context, bool execonly) | |
4335 | { | |
4336 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
6f8e65a6 | 4337 | reserved_hpa_bits(), execonly); |
c258b62b XG |
4338 | } |
4339 | ||
09f037aa PB |
4340 | #define BYTE_MASK(access) \ |
4341 | ((1 & (access) ? 2 : 0) | \ | |
4342 | (2 & (access) ? 4 : 0) | \ | |
4343 | (3 & (access) ? 8 : 0) | \ | |
4344 | (4 & (access) ? 16 : 0) | \ | |
4345 | (5 & (access) ? 32 : 0) | \ | |
4346 | (6 & (access) ? 64 : 0) | \ | |
4347 | (7 & (access) ? 128 : 0)) | |
4348 | ||
4349 | ||
c596f147 | 4350 | static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept) |
97d64b78 | 4351 | { |
09f037aa PB |
4352 | unsigned byte; |
4353 | ||
4354 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4355 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4356 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4357 | ||
c596f147 SC |
4358 | bool cr4_smep = is_cr4_smep(mmu); |
4359 | bool cr4_smap = is_cr4_smap(mmu); | |
4360 | bool cr0_wp = is_cr0_wp(mmu); | |
90599c28 | 4361 | bool efer_nx = is_efer_nx(mmu); |
97d64b78 | 4362 | |
97d64b78 | 4363 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4364 | unsigned pfec = byte << 1; |
4365 | ||
97ec8c06 | 4366 | /* |
09f037aa PB |
4367 | * Each "*f" variable has a 1 bit for each UWX value |
4368 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4369 | */ |
97d64b78 | 4370 | |
09f037aa | 4371 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4372 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4373 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4374 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4375 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4376 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4377 | /* Faults from kernel mode fetches of user pages */ |
4378 | u8 smepf = 0; | |
4379 | /* Faults from kernel mode accesses of user pages */ | |
4380 | u8 smapf = 0; | |
4381 | ||
4382 | if (!ept) { | |
4383 | /* Faults from kernel mode accesses to user pages */ | |
4384 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4385 | ||
4386 | /* Not really needed: !nx will cause pte.nx to fault */ | |
90599c28 | 4387 | if (!efer_nx) |
09f037aa PB |
4388 | ff = 0; |
4389 | ||
4390 | /* Allow supervisor writes if !cr0.wp */ | |
4391 | if (!cr0_wp) | |
4392 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4393 | ||
4394 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4395 | if (cr4_smep) | |
4396 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4397 | ||
4398 | /* | |
4399 | * SMAP:kernel-mode data accesses from user-mode | |
4400 | * mappings should fault. A fault is considered | |
4401 | * as a SMAP violation if all of the following | |
39337ad1 | 4402 | * conditions are true: |
09f037aa PB |
4403 | * - X86_CR4_SMAP is set in CR4 |
4404 | * - A user page is accessed | |
4405 | * - The access is not a fetch | |
4406 | * - Page fault in kernel mode | |
4407 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4408 | * | |
4409 | * Here, we cover the first three conditions. | |
4410 | * The fourth is computed dynamically in permission_fault(); | |
4411 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4412 | * *not* subject to SMAP restrictions. | |
4413 | */ | |
4414 | if (cr4_smap) | |
4415 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4416 | } |
09f037aa PB |
4417 | |
4418 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4419 | } |
4420 | } | |
4421 | ||
2d344105 HH |
4422 | /* |
4423 | * PKU is an additional mechanism by which the paging controls access to | |
4424 | * user-mode addresses based on the value in the PKRU register. Protection | |
4425 | * key violations are reported through a bit in the page fault error code. | |
4426 | * Unlike other bits of the error code, the PK bit is not known at the | |
4427 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4428 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4429 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4430 | * | |
4431 | * In particular the following conditions come from the error code, the | |
4432 | * page tables and the machine state: | |
4433 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4434 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4435 | * - PK is always zero if U=0 in the page tables | |
4436 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4437 | * | |
4438 | * The PKRU bitmask caches the result of these four conditions. The error | |
4439 | * code (minus the P bit) and the page table's U bit form an index into the | |
4440 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4441 | * with the two bits of the PKRU register corresponding to the protection key. | |
4442 | * For the first three conditions above the bits will be 00, thus masking | |
4443 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4444 | * only will be masked away. | |
4445 | */ | |
2e4c0661 | 4446 | static void update_pkru_bitmask(struct kvm_mmu *mmu) |
2d344105 HH |
4447 | { |
4448 | unsigned bit; | |
4449 | bool wp; | |
4450 | ||
2e4c0661 | 4451 | if (!is_cr4_pke(mmu)) { |
2d344105 HH |
4452 | mmu->pkru_mask = 0; |
4453 | return; | |
4454 | } | |
4455 | ||
2e4c0661 | 4456 | wp = is_cr0_wp(mmu); |
2d344105 HH |
4457 | |
4458 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4459 | unsigned pfec, pkey_bits; | |
4460 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4461 | ||
4462 | pfec = bit << 1; | |
4463 | ff = pfec & PFERR_FETCH_MASK; | |
4464 | uf = pfec & PFERR_USER_MASK; | |
4465 | wf = pfec & PFERR_WRITE_MASK; | |
4466 | ||
4467 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4468 | pte_user = pfec & PFERR_RSVD_MASK; | |
4469 | ||
4470 | /* | |
4471 | * Only need to check the access which is not an | |
4472 | * instruction fetch and is to a user page. | |
4473 | */ | |
4474 | check_pkey = (!ff && pte_user); | |
4475 | /* | |
4476 | * write access is controlled by PKRU if it is a | |
4477 | * user access or CR0.WP = 1. | |
4478 | */ | |
4479 | check_write = check_pkey && wf && (uf || wp); | |
4480 | ||
4481 | /* PKRU.AD stops both read and write access. */ | |
4482 | pkey_bits = !!check_pkey; | |
4483 | /* PKRU.WD stops write access. */ | |
4484 | pkey_bits |= (!!check_write) << 1; | |
4485 | ||
4486 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4487 | } | |
4488 | } | |
4489 | ||
533f9a4b SC |
4490 | static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu, |
4491 | struct kvm_mmu *mmu) | |
6fd01b71 | 4492 | { |
533f9a4b SC |
4493 | if (!is_cr0_pg(mmu)) |
4494 | return; | |
6bb69c9b | 4495 | |
533f9a4b SC |
4496 | reset_rsvds_bits_mask(vcpu, mmu); |
4497 | update_permission_bitmask(mmu, false); | |
4498 | update_pkru_bitmask(mmu); | |
6fd01b71 AK |
4499 | } |
4500 | ||
fe660f72 | 4501 | static void paging64_init_context(struct kvm_mmu *context) |
6aa8b732 | 4502 | { |
6aa8b732 | 4503 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4504 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4505 | context->sync_page = paging64_sync_page; |
a7052897 | 4506 | context->invlpg = paging64_invlpg; |
c5a78f2b | 4507 | context->direct_map = false; |
6aa8b732 AK |
4508 | } |
4509 | ||
84a16226 | 4510 | static void paging32_init_context(struct kvm_mmu *context) |
6aa8b732 | 4511 | { |
6aa8b732 | 4512 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4513 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4514 | context->sync_page = paging32_sync_page; |
a7052897 | 4515 | context->invlpg = paging32_invlpg; |
c5a78f2b | 4516 | context->direct_map = false; |
6aa8b732 AK |
4517 | } |
4518 | ||
8626c120 SC |
4519 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu, |
4520 | struct kvm_mmu_role_regs *regs) | |
a336282d VK |
4521 | { |
4522 | union kvm_mmu_extended_role ext = {0}; | |
4523 | ||
ca8d664f SC |
4524 | if (____is_cr0_pg(regs)) { |
4525 | ext.cr0_pg = 1; | |
4526 | ext.cr4_pae = ____is_cr4_pae(regs); | |
4527 | ext.cr4_smep = ____is_cr4_smep(regs); | |
4528 | ext.cr4_smap = ____is_cr4_smap(regs); | |
4529 | ext.cr4_pse = ____is_cr4_pse(regs); | |
84c679f5 SC |
4530 | |
4531 | /* PKEY and LA57 are active iff long mode is active. */ | |
4532 | ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs); | |
4533 | ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs); | |
ca8d664f | 4534 | } |
a336282d VK |
4535 | |
4536 | ext.valid = 1; | |
4537 | ||
4538 | return ext; | |
4539 | } | |
4540 | ||
7dcd5755 | 4541 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
8626c120 | 4542 | struct kvm_mmu_role_regs *regs, |
7dcd5755 VK |
4543 | bool base_only) |
4544 | { | |
4545 | union kvm_mmu_role role = {0}; | |
4546 | ||
4547 | role.base.access = ACC_ALL; | |
ca8d664f SC |
4548 | if (____is_cr0_pg(regs)) { |
4549 | role.base.efer_nx = ____is_efer_nx(regs); | |
4550 | role.base.cr0_wp = ____is_cr0_wp(regs); | |
4551 | } | |
7dcd5755 VK |
4552 | role.base.smm = is_smm(vcpu); |
4553 | role.base.guest_mode = is_guest_mode(vcpu); | |
4554 | ||
4555 | if (base_only) | |
4556 | return role; | |
4557 | ||
8626c120 | 4558 | role.ext = kvm_calc_mmu_role_ext(vcpu, regs); |
7dcd5755 VK |
4559 | |
4560 | return role; | |
4561 | } | |
4562 | ||
d468d94b SC |
4563 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4564 | { | |
4565 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4566 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4567 | return 4; |
4568 | ||
83013059 | 4569 | return max_tdp_level; |
d468d94b SC |
4570 | } |
4571 | ||
7dcd5755 | 4572 | static union kvm_mmu_role |
8626c120 SC |
4573 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4574 | struct kvm_mmu_role_regs *regs, bool base_only) | |
9fa72119 | 4575 | { |
8626c120 | 4576 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
9fa72119 | 4577 | |
7dcd5755 | 4578 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4579 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4580 | role.base.direct = true; |
47c42e6b | 4581 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4582 | |
4583 | return role; | |
4584 | } | |
4585 | ||
8a3c1a33 | 4586 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4587 | { |
8c008659 | 4588 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
8626c120 | 4589 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 | 4590 | union kvm_mmu_role new_role = |
8626c120 | 4591 | kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false); |
fb72d167 | 4592 | |
7dcd5755 VK |
4593 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4594 | return; | |
4595 | ||
4596 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4597 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4598 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4599 | context->invlpg = NULL; |
d468d94b | 4600 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4601 | context->direct_map = true; |
d8dd54e0 | 4602 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4603 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4604 | context->inject_page_fault = kvm_inject_page_fault; |
f4bd6f73 | 4605 | context->root_level = role_regs_to_root_level(®s); |
fb72d167 | 4606 | |
36f26787 | 4607 | if (!is_cr0_pg(context)) |
fb72d167 | 4608 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
36f26787 | 4609 | else if (is_cr4_pae(context)) |
4d6931c3 | 4610 | context->gva_to_gpa = paging64_gva_to_gpa; |
f4bd6f73 | 4611 | else |
4d6931c3 | 4612 | context->gva_to_gpa = paging32_gva_to_gpa; |
fb72d167 | 4613 | |
533f9a4b | 4614 | reset_guest_paging_metadata(vcpu, context); |
c258b62b | 4615 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4616 | } |
4617 | ||
7dcd5755 | 4618 | static union kvm_mmu_role |
8626c120 SC |
4619 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, |
4620 | struct kvm_mmu_role_regs *regs, bool base_only) | |
7dcd5755 | 4621 | { |
8626c120 | 4622 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
7dcd5755 | 4623 | |
8626c120 SC |
4624 | role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs); |
4625 | role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs); | |
ca8d664f | 4626 | role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs); |
9fa72119 | 4627 | |
59505b55 SC |
4628 | return role; |
4629 | } | |
4630 | ||
4631 | static union kvm_mmu_role | |
8626c120 SC |
4632 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4633 | struct kvm_mmu_role_regs *regs, bool base_only) | |
59505b55 SC |
4634 | { |
4635 | union kvm_mmu_role role = | |
8626c120 | 4636 | kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only); |
59505b55 | 4637 | |
8626c120 | 4638 | role.base.direct = !____is_cr0_pg(regs); |
59505b55 | 4639 | |
8626c120 | 4640 | if (!____is_efer_lma(regs)) |
7dcd5755 | 4641 | role.base.level = PT32E_ROOT_LEVEL; |
8626c120 | 4642 | else if (____is_cr4_la57(regs)) |
7dcd5755 | 4643 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4644 | else |
7dcd5755 | 4645 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4646 | |
4647 | return role; | |
4648 | } | |
4649 | ||
8c008659 | 4650 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
594e91a1 | 4651 | struct kvm_mmu_role_regs *regs, |
8c008659 | 4652 | union kvm_mmu_role new_role) |
9fa72119 | 4653 | { |
18db1b17 SC |
4654 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4655 | return; | |
a770f6f2 | 4656 | |
7dcd5755 | 4657 | context->mmu_role.as_u64 = new_role.as_u64; |
18db1b17 | 4658 | |
36f26787 | 4659 | if (!is_cr0_pg(context)) |
84a16226 | 4660 | nonpaging_init_context(context); |
36f26787 | 4661 | else if (is_cr4_pae(context)) |
fe660f72 | 4662 | paging64_init_context(context); |
6aa8b732 | 4663 | else |
84a16226 | 4664 | paging32_init_context(context); |
f4bd6f73 | 4665 | context->root_level = role_regs_to_root_level(regs); |
a770f6f2 | 4666 | |
533f9a4b | 4667 | reset_guest_paging_metadata(vcpu, context); |
d555f705 SC |
4668 | context->shadow_root_level = new_role.base.level; |
4669 | ||
c258b62b | 4670 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4671 | } |
0f04a2ac | 4672 | |
594e91a1 SC |
4673 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, |
4674 | struct kvm_mmu_role_regs *regs) | |
0f04a2ac | 4675 | { |
8c008659 | 4676 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac | 4677 | union kvm_mmu_role new_role = |
8626c120 | 4678 | kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false); |
0f04a2ac | 4679 | |
18db1b17 | 4680 | shadow_mmu_init_context(vcpu, context, regs, new_role); |
0f04a2ac VK |
4681 | } |
4682 | ||
59505b55 | 4683 | static union kvm_mmu_role |
8626c120 SC |
4684 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu, |
4685 | struct kvm_mmu_role_regs *regs) | |
59505b55 SC |
4686 | { |
4687 | union kvm_mmu_role role = | |
8626c120 | 4688 | kvm_calc_shadow_root_page_role_common(vcpu, regs, false); |
59505b55 SC |
4689 | |
4690 | role.base.direct = false; | |
d468d94b | 4691 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4692 | |
4693 | return role; | |
4694 | } | |
4695 | ||
dbc4739b SC |
4696 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, |
4697 | unsigned long cr4, u64 efer, gpa_t nested_cr3) | |
0f04a2ac | 4698 | { |
8c008659 | 4699 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
594e91a1 SC |
4700 | struct kvm_mmu_role_regs regs = { |
4701 | .cr0 = cr0, | |
4702 | .cr4 = cr4, | |
4703 | .efer = efer, | |
4704 | }; | |
8626c120 | 4705 | union kvm_mmu_role new_role; |
0f04a2ac | 4706 | |
8626c120 | 4707 | new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s); |
a506fdd2 | 4708 | |
b5129100 | 4709 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base); |
a3322d5c | 4710 | |
18db1b17 | 4711 | shadow_mmu_init_context(vcpu, context, ®s, new_role); |
0f04a2ac VK |
4712 | } |
4713 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4714 | |
a336282d VK |
4715 | static union kvm_mmu_role |
4716 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4717 | bool execonly, u8 level) |
9fa72119 | 4718 | { |
552c69b1 | 4719 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4720 | |
47c42e6b SC |
4721 | /* SMM flag is inherited from root_mmu */ |
4722 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4723 | |
bb1fcc70 | 4724 | role.base.level = level; |
47c42e6b | 4725 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4726 | role.base.direct = false; |
4727 | role.base.ad_disabled = !accessed_dirty; | |
4728 | role.base.guest_mode = true; | |
4729 | role.base.access = ACC_ALL; | |
9fa72119 | 4730 | |
cd6767c3 SC |
4731 | /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */ |
4732 | role.ext.word = 0; | |
a336282d | 4733 | role.ext.execonly = execonly; |
cd6767c3 | 4734 | role.ext.valid = 1; |
9fa72119 JS |
4735 | |
4736 | return role; | |
4737 | } | |
4738 | ||
ae1e2d10 | 4739 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4740 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4741 | { |
8c008659 | 4742 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4743 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4744 | union kvm_mmu_role new_role = |
4745 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4746 | execonly, level); |
a336282d | 4747 | |
b5129100 | 4748 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base); |
a336282d | 4749 | |
a336282d VK |
4750 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4751 | return; | |
ad896af0 | 4752 | |
18db1b17 SC |
4753 | context->mmu_role.as_u64 = new_role.as_u64; |
4754 | ||
bb1fcc70 | 4755 | context->shadow_root_level = level; |
155a97a3 | 4756 | |
ae1e2d10 | 4757 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4758 | context->page_fault = ept_page_fault; |
4759 | context->gva_to_gpa = ept_gva_to_gpa; | |
4760 | context->sync_page = ept_sync_page; | |
4761 | context->invlpg = ept_invlpg; | |
bb1fcc70 | 4762 | context->root_level = level; |
155a97a3 | 4763 | context->direct_map = false; |
3dc773e7 | 4764 | |
c596f147 | 4765 | update_permission_bitmask(context, true); |
2e4c0661 | 4766 | update_pkru_bitmask(context); |
155a97a3 | 4767 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4768 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4769 | } |
4770 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4771 | ||
8a3c1a33 | 4772 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4773 | { |
8c008659 | 4774 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
594e91a1 | 4775 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
ad896af0 | 4776 | |
594e91a1 | 4777 | kvm_init_shadow_mmu(vcpu, ®s); |
929d1cfa | 4778 | |
d8dd54e0 | 4779 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4780 | context->get_pdptr = kvm_pdptr_read; |
4781 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4782 | } |
4783 | ||
8626c120 SC |
4784 | static union kvm_mmu_role |
4785 | kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs) | |
654430ef | 4786 | { |
8626c120 SC |
4787 | union kvm_mmu_role role; |
4788 | ||
4789 | role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false); | |
654430ef SC |
4790 | |
4791 | /* | |
4792 | * Nested MMUs are used only for walking L2's gva->gpa, they never have | |
4793 | * shadow pages of their own and so "direct" has no meaning. Set it | |
4794 | * to "true" to try to detect bogus usage of the nested MMU. | |
4795 | */ | |
4796 | role.base.direct = true; | |
f4bd6f73 | 4797 | role.base.level = role_regs_to_root_level(regs); |
654430ef SC |
4798 | return role; |
4799 | } | |
4800 | ||
8a3c1a33 | 4801 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4802 | { |
8626c120 SC |
4803 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
4804 | union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s); | |
02f59dc9 JR |
4805 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4806 | ||
bf627a92 VK |
4807 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4808 | return; | |
4809 | ||
4810 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4811 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4812 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 | 4813 | g_context->inject_page_fault = kvm_inject_page_fault; |
5472fcd4 | 4814 | g_context->root_level = new_role.base.level; |
02f59dc9 | 4815 | |
5efac074 PB |
4816 | /* |
4817 | * L2 page tables are never shadowed, so there is no need to sync | |
4818 | * SPTEs. | |
4819 | */ | |
4820 | g_context->invlpg = NULL; | |
4821 | ||
02f59dc9 | 4822 | /* |
44dd3ffa | 4823 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4824 | * L1's nested page tables (e.g. EPT12). The nested translation |
4825 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4826 | * L2's page tables as the first level of translation and L1's | |
4827 | * nested page tables as the second level of translation. Basically | |
4828 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 | 4829 | */ |
fa4b5588 | 4830 | if (!is_paging(vcpu)) |
02f59dc9 | 4831 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; |
fa4b5588 | 4832 | else if (is_long_mode(vcpu)) |
02f59dc9 | 4833 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
fa4b5588 | 4834 | else if (is_pae(vcpu)) |
02f59dc9 | 4835 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
fa4b5588 | 4836 | else |
02f59dc9 | 4837 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
02f59dc9 | 4838 | |
533f9a4b | 4839 | reset_guest_paging_metadata(vcpu, g_context); |
02f59dc9 JR |
4840 | } |
4841 | ||
c9060662 | 4842 | void kvm_init_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4843 | { |
02f59dc9 | 4844 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4845 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4846 | else if (tdp_enabled) |
e0c6db3e | 4847 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4848 | else |
e0c6db3e | 4849 | init_kvm_softmmu(vcpu); |
fb72d167 | 4850 | } |
1c53da3f | 4851 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4852 | |
9fa72119 JS |
4853 | static union kvm_mmu_page_role |
4854 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4855 | { | |
8626c120 | 4856 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 VK |
4857 | union kvm_mmu_role role; |
4858 | ||
9fa72119 | 4859 | if (tdp_enabled) |
8626c120 | 4860 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true); |
9fa72119 | 4861 | else |
8626c120 | 4862 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true); |
7dcd5755 VK |
4863 | |
4864 | return role.base; | |
9fa72119 | 4865 | } |
fb72d167 | 4866 | |
49c6f875 SC |
4867 | void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu) |
4868 | { | |
4869 | /* | |
4870 | * Invalidate all MMU roles to force them to reinitialize as CPUID | |
4871 | * information is factored into reserved bit calculations. | |
4872 | */ | |
4873 | vcpu->arch.root_mmu.mmu_role.ext.valid = 0; | |
4874 | vcpu->arch.guest_mmu.mmu_role.ext.valid = 0; | |
4875 | vcpu->arch.nested_mmu.mmu_role.ext.valid = 0; | |
4876 | kvm_mmu_reset_context(vcpu); | |
63f5a190 SC |
4877 | |
4878 | /* | |
4879 | * KVM does not correctly handle changing guest CPUID after KVM_RUN, as | |
4880 | * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't | |
4881 | * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page | |
4882 | * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise | |
4883 | * sweep the problem under the rug. | |
4884 | * | |
4885 | * KVM's horrific CPUID ABI makes the problem all but impossible to | |
4886 | * solve, as correctly handling multiple vCPU models (with respect to | |
4887 | * paging and physical address properties) in a single VM would require | |
4888 | * tracking all relevant CPUID information in kvm_mmu_page_role. That | |
4889 | * is very undesirable as it would double the memory requirements for | |
4890 | * gfn_track (see struct kvm_mmu_page_role comments), and in practice | |
4891 | * no sane VMM mucks with the core vCPU model on the fly. | |
4892 | */ | |
4893 | if (vcpu->arch.last_vmentry_cpu != -1) { | |
4894 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n"); | |
4895 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n"); | |
4896 | } | |
49c6f875 SC |
4897 | } |
4898 | ||
8a3c1a33 | 4899 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4900 | { |
95f93af4 | 4901 | kvm_mmu_unload(vcpu); |
c9060662 | 4902 | kvm_init_mmu(vcpu); |
17c3ba9d | 4903 | } |
8668a3c4 | 4904 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4905 | |
4906 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4907 | { |
714b93da AK |
4908 | int r; |
4909 | ||
378f5cd6 | 4910 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
4911 | if (r) |
4912 | goto out; | |
748e52b9 | 4913 | r = mmu_alloc_special_roots(vcpu); |
17c3ba9d AK |
4914 | if (r) |
4915 | goto out; | |
4a38162e | 4916 | if (vcpu->arch.mmu->direct_map) |
6e6ec584 SC |
4917 | r = mmu_alloc_direct_roots(vcpu); |
4918 | else | |
4919 | r = mmu_alloc_shadow_roots(vcpu); | |
8986ecc0 MT |
4920 | if (r) |
4921 | goto out; | |
a91f387b SC |
4922 | |
4923 | kvm_mmu_sync_roots(vcpu); | |
4924 | ||
727a7e27 | 4925 | kvm_mmu_load_pgd(vcpu); |
b3646477 | 4926 | static_call(kvm_x86_tlb_flush_current)(vcpu); |
714b93da AK |
4927 | out: |
4928 | return r; | |
6aa8b732 | 4929 | } |
17c3ba9d AK |
4930 | |
4931 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4932 | { | |
14c07ad8 VK |
4933 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
4934 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
4935 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
4936 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 4937 | } |
6aa8b732 | 4938 | |
79539cec AK |
4939 | static bool need_remote_flush(u64 old, u64 new) |
4940 | { | |
4941 | if (!is_shadow_present_pte(old)) | |
4942 | return false; | |
4943 | if (!is_shadow_present_pte(new)) | |
4944 | return true; | |
4945 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4946 | return true; | |
53166229 GN |
4947 | old ^= shadow_nx_mask; |
4948 | new ^= shadow_nx_mask; | |
79539cec AK |
4949 | return (old & ~new & PT64_PERM_MASK) != 0; |
4950 | } | |
4951 | ||
889e5cbc | 4952 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 4953 | int *bytes) |
da4a00f0 | 4954 | { |
0e0fee5c | 4955 | u64 gentry = 0; |
889e5cbc | 4956 | int r; |
72016f3a | 4957 | |
72016f3a AK |
4958 | /* |
4959 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4960 | * as the current vcpu paging mode since we update the sptes only |
4961 | * when they have the same mode. | |
72016f3a | 4962 | */ |
889e5cbc | 4963 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4964 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4965 | *gpa &= ~(gpa_t)7; |
4966 | *bytes = 8; | |
08e850c6 AK |
4967 | } |
4968 | ||
0e0fee5c JS |
4969 | if (*bytes == 4 || *bytes == 8) { |
4970 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
4971 | if (r) | |
4972 | gentry = 0; | |
72016f3a AK |
4973 | } |
4974 | ||
889e5cbc XG |
4975 | return gentry; |
4976 | } | |
4977 | ||
4978 | /* | |
4979 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4980 | * or we may be forking, in which case it is better to unmap the page. | |
4981 | */ | |
a138fe75 | 4982 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4983 | { |
a30f47cb XG |
4984 | /* |
4985 | * Skip write-flooding detected for the sp whose level is 1, because | |
4986 | * it can become unsync, then the guest page is not write-protected. | |
4987 | */ | |
3bae0459 | 4988 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 4989 | return false; |
3246af0e | 4990 | |
e5691a81 XG |
4991 | atomic_inc(&sp->write_flooding_count); |
4992 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4993 | } |
4994 | ||
4995 | /* | |
4996 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4997 | * indicate a page is not used as a page table. | |
4998 | */ | |
4999 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5000 | int bytes) | |
5001 | { | |
5002 | unsigned offset, pte_size, misaligned; | |
5003 | ||
5004 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5005 | gpa, bytes, sp->role.word); | |
5006 | ||
5007 | offset = offset_in_page(gpa); | |
47c42e6b | 5008 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5009 | |
5010 | /* | |
5011 | * Sometimes, the OS only writes the last one bytes to update status | |
5012 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5013 | */ | |
5014 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5015 | return false; | |
5016 | ||
889e5cbc XG |
5017 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5018 | misaligned |= bytes < 4; | |
5019 | ||
5020 | return misaligned; | |
5021 | } | |
5022 | ||
5023 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5024 | { | |
5025 | unsigned page_offset, quadrant; | |
5026 | u64 *spte; | |
5027 | int level; | |
5028 | ||
5029 | page_offset = offset_in_page(gpa); | |
5030 | level = sp->role.level; | |
5031 | *nspte = 1; | |
47c42e6b | 5032 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5033 | page_offset <<= 1; /* 32->64 */ |
5034 | /* | |
5035 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5036 | * only 2MB. So we need to double the offset again | |
5037 | * and zap two pdes instead of one. | |
5038 | */ | |
5039 | if (level == PT32_ROOT_LEVEL) { | |
5040 | page_offset &= ~7; /* kill rounding error */ | |
5041 | page_offset <<= 1; | |
5042 | *nspte = 2; | |
5043 | } | |
5044 | quadrant = page_offset >> PAGE_SHIFT; | |
5045 | page_offset &= ~PAGE_MASK; | |
5046 | if (quadrant != sp->role.quadrant) | |
5047 | return NULL; | |
5048 | } | |
5049 | ||
5050 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5051 | return spte; | |
5052 | } | |
5053 | ||
13d268ca | 5054 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5055 | const u8 *new, int bytes, |
5056 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5057 | { |
5058 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5059 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5060 | LIST_HEAD(invalid_list); |
5061 | u64 entry, gentry, *spte; | |
5062 | int npte; | |
b8c67b7a | 5063 | bool remote_flush, local_flush; |
889e5cbc XG |
5064 | |
5065 | /* | |
5066 | * If we don't have indirect shadow pages, it means no page is | |
5067 | * write-protected, so we can exit simply. | |
5068 | */ | |
6aa7de05 | 5069 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5070 | return; |
5071 | ||
b8c67b7a | 5072 | remote_flush = local_flush = false; |
889e5cbc XG |
5073 | |
5074 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5075 | ||
889e5cbc XG |
5076 | /* |
5077 | * No need to care whether allocation memory is successful | |
d9f6e12f | 5078 | * or not since pte prefetch is skipped if it does not have |
889e5cbc XG |
5079 | * enough objects in the cache. |
5080 | */ | |
378f5cd6 | 5081 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc | 5082 | |
531810ca | 5083 | write_lock(&vcpu->kvm->mmu_lock); |
0e0fee5c JS |
5084 | |
5085 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5086 | ||
889e5cbc | 5087 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5088 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5089 | |
b67bfe0d | 5090 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5091 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5092 | detect_write_flooding(sp)) { |
b8c67b7a | 5093 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5094 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5095 | continue; |
5096 | } | |
889e5cbc XG |
5097 | |
5098 | spte = get_written_sptes(sp, gpa, &npte); | |
5099 | if (!spte) | |
5100 | continue; | |
5101 | ||
0671a8e7 | 5102 | local_flush = true; |
ac1b714e | 5103 | while (npte--) { |
79539cec | 5104 | entry = *spte; |
2de4085c | 5105 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
c5e2184d SC |
5106 | if (gentry && sp->role.level != PG_LEVEL_4K) |
5107 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
9bb4f6b1 | 5108 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5109 | remote_flush = true; |
ac1b714e | 5110 | ++spte; |
9b7a0325 | 5111 | } |
9b7a0325 | 5112 | } |
b8c67b7a | 5113 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5114 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
531810ca | 5115 | write_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5116 | } |
5117 | ||
736c291c | 5118 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5119 | void *insn, int insn_len) |
3067714c | 5120 | { |
92daa48b | 5121 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5122 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5123 | |
6948199a | 5124 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5125 | return RET_PF_RETRY; |
5126 | ||
9b8ebbdb | 5127 | r = RET_PF_INVALID; |
e9ee956e | 5128 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5129 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5130 | if (r == RET_PF_EMULATE) |
e9ee956e | 5131 | goto emulate; |
e9ee956e | 5132 | } |
3067714c | 5133 | |
9b8ebbdb | 5134 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5135 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5136 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5137 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5138 | return -EIO; | |
9b8ebbdb PB |
5139 | } |
5140 | ||
3067714c | 5141 | if (r < 0) |
e9ee956e | 5142 | return r; |
83a2ba4c SC |
5143 | if (r != RET_PF_EMULATE) |
5144 | return 1; | |
3067714c | 5145 | |
14727754 TL |
5146 | /* |
5147 | * Before emulating the instruction, check if the error code | |
5148 | * was due to a RO violation while translating the guest page. | |
5149 | * This can occur when using nested virtualization with nested | |
5150 | * paging in both guests. If true, we simply unprotect the page | |
5151 | * and resume the guest. | |
14727754 | 5152 | */ |
44dd3ffa | 5153 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5154 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5155 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5156 | return 1; |
5157 | } | |
5158 | ||
472faffa SC |
5159 | /* |
5160 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5161 | * optimistically try to just unprotect the page and let the processor | |
5162 | * re-execute the instruction that caused the page fault. Do not allow | |
5163 | * retrying MMIO emulation, as it's not only pointless but could also | |
5164 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5165 | * faulting on the non-existent MMIO address. Retrying an instruction |
5166 | * from a nested guest is also pointless and dangerous as we are only | |
5167 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5168 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5169 | */ |
736c291c | 5170 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5171 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5172 | emulate: |
736c291c | 5173 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5174 | insn_len); |
3067714c AK |
5175 | } |
5176 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5177 | ||
5efac074 PB |
5178 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5179 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5180 | { |
b94742c9 | 5181 | int i; |
7eb77e9f | 5182 | |
5efac074 PB |
5183 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5184 | if (mmu != &vcpu->arch.guest_mmu) { | |
5185 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5186 | if (is_noncanonical_address(gva, vcpu)) | |
5187 | return; | |
5188 | ||
b3646477 | 5189 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
5efac074 PB |
5190 | } |
5191 | ||
5192 | if (!mmu->invlpg) | |
faff8758 JS |
5193 | return; |
5194 | ||
5efac074 PB |
5195 | if (root_hpa == INVALID_PAGE) { |
5196 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5197 | |
5efac074 PB |
5198 | /* |
5199 | * INVLPG is required to invalidate any global mappings for the VA, | |
5200 | * irrespective of PCID. Since it would take us roughly similar amount | |
5201 | * of work to determine whether any of the prev_root mappings of the VA | |
5202 | * is marked global, or to just sync it blindly, so we might as well | |
5203 | * just always sync it. | |
5204 | * | |
5205 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5206 | * synced when switching to that cr3, so nothing needs to be done here | |
5207 | * for them. | |
5208 | */ | |
5209 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5210 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5211 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5212 | } else { | |
5213 | mmu->invlpg(vcpu, gva, root_hpa); | |
5214 | } | |
5215 | } | |
956bf353 | 5216 | |
5efac074 PB |
5217 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5218 | { | |
5219 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5220 | ++vcpu->stat.invlpg; |
5221 | } | |
5222 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5223 | ||
5efac074 | 5224 | |
eb4b248e JS |
5225 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5226 | { | |
44dd3ffa | 5227 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5228 | bool tlb_flush = false; |
b94742c9 | 5229 | uint i; |
eb4b248e JS |
5230 | |
5231 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5232 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5233 | tlb_flush = true; |
eb4b248e JS |
5234 | } |
5235 | ||
b94742c9 JS |
5236 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5237 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5238 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5239 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5240 | tlb_flush = true; | |
5241 | } | |
956bf353 | 5242 | } |
ade61e28 | 5243 | |
faff8758 | 5244 | if (tlb_flush) |
b3646477 | 5245 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
faff8758 | 5246 | |
eb4b248e JS |
5247 | ++vcpu->stat.invlpg; |
5248 | ||
5249 | /* | |
b94742c9 JS |
5250 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5251 | * synced when switching to that cr3, so nothing needs to be done here | |
5252 | * for them. | |
eb4b248e JS |
5253 | */ |
5254 | } | |
eb4b248e | 5255 | |
83013059 SC |
5256 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5257 | int tdp_huge_page_level) | |
18552672 | 5258 | { |
bde77235 | 5259 | tdp_enabled = enable_tdp; |
83013059 | 5260 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5261 | |
5262 | /* | |
1d92d2e8 | 5263 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5264 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5265 | * the kernel is not. But, KVM never creates a page size greater than | |
5266 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5267 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5268 | */ | |
5269 | if (tdp_enabled) | |
1d92d2e8 | 5270 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5271 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5272 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5273 | else |
1d92d2e8 | 5274 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5275 | } |
bde77235 | 5276 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5277 | |
5278 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
0a234f5d SC |
5279 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
5280 | struct kvm_memory_slot *slot); | |
85875a13 SC |
5281 | |
5282 | /* The caller should hold mmu-lock before calling this function. */ | |
5283 | static __always_inline bool | |
5284 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5285 | slot_level_handler fn, int start_level, int end_level, | |
1a61b7db SC |
5286 | gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield, |
5287 | bool flush) | |
85875a13 SC |
5288 | { |
5289 | struct slot_rmap_walk_iterator iterator; | |
85875a13 SC |
5290 | |
5291 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5292 | end_gfn, &iterator) { | |
5293 | if (iterator.rmap) | |
0a234f5d | 5294 | flush |= fn(kvm, iterator.rmap, memslot); |
85875a13 | 5295 | |
531810ca | 5296 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
302695a5 | 5297 | if (flush && flush_on_yield) { |
f285c633 BG |
5298 | kvm_flush_remote_tlbs_with_address(kvm, |
5299 | start_gfn, | |
5300 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5301 | flush = false; |
5302 | } | |
531810ca | 5303 | cond_resched_rwlock_write(&kvm->mmu_lock); |
85875a13 SC |
5304 | } |
5305 | } | |
5306 | ||
85875a13 SC |
5307 | return flush; |
5308 | } | |
5309 | ||
5310 | static __always_inline bool | |
5311 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5312 | slot_level_handler fn, int start_level, int end_level, | |
302695a5 | 5313 | bool flush_on_yield) |
85875a13 SC |
5314 | { |
5315 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5316 | end_level, memslot->base_gfn, | |
5317 | memslot->base_gfn + memslot->npages - 1, | |
1a61b7db | 5318 | flush_on_yield, false); |
85875a13 SC |
5319 | } |
5320 | ||
85875a13 SC |
5321 | static __always_inline bool |
5322 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
302695a5 | 5323 | slot_level_handler fn, bool flush_on_yield) |
85875a13 | 5324 | { |
3bae0459 | 5325 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
302695a5 | 5326 | PG_LEVEL_4K, flush_on_yield); |
85875a13 SC |
5327 | } |
5328 | ||
1cfff4d9 | 5329 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5330 | { |
4a98623d SC |
5331 | if (!tdp_enabled && mmu->pae_root) |
5332 | set_memory_encrypted((unsigned long)mmu->pae_root, 1); | |
1cfff4d9 | 5333 | free_page((unsigned long)mmu->pae_root); |
03ca4589 | 5334 | free_page((unsigned long)mmu->pml4_root); |
6aa8b732 AK |
5335 | } |
5336 | ||
04d28e37 | 5337 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5338 | { |
17ac10ad | 5339 | struct page *page; |
6aa8b732 AK |
5340 | int i; |
5341 | ||
04d28e37 SC |
5342 | mmu->root_hpa = INVALID_PAGE; |
5343 | mmu->root_pgd = 0; | |
5344 | mmu->translate_gpa = translate_gpa; | |
5345 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5346 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5347 | ||
17ac10ad | 5348 | /* |
b6b80c78 SC |
5349 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5350 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5351 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5352 | * x86_64. Therefore we need to allocate the PDP table in the first | |
04d45551 SC |
5353 | * 4GB of memory, which happens to fit the DMA32 zone. TDP paging |
5354 | * generally doesn't use PAE paging and can skip allocating the PDP | |
5355 | * table. The main exception, handled here, is SVM's 32-bit NPT. The | |
5356 | * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit | |
5357 | * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). | |
17ac10ad | 5358 | */ |
d468d94b | 5359 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5360 | return 0; |
5361 | ||
254272ce | 5362 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5363 | if (!page) |
d7fa6ab2 WY |
5364 | return -ENOMEM; |
5365 | ||
1cfff4d9 | 5366 | mmu->pae_root = page_address(page); |
4a98623d SC |
5367 | |
5368 | /* | |
5369 | * CR3 is only 32 bits when PAE paging is used, thus it's impossible to | |
5370 | * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so | |
5371 | * that KVM's writes and the CPU's reads get along. Note, this is | |
5372 | * only necessary when using shadow paging, as 64-bit NPT can get at | |
5373 | * the C-bit even when shadowing 32-bit NPT, and SME isn't supported | |
5374 | * by 32-bit kernels (when KVM itself uses 32-bit NPT). | |
5375 | */ | |
5376 | if (!tdp_enabled) | |
5377 | set_memory_decrypted((unsigned long)mmu->pae_root, 1); | |
5378 | else | |
5379 | WARN_ON_ONCE(shadow_me_mask); | |
5380 | ||
17ac10ad | 5381 | for (i = 0; i < 4; ++i) |
c834e5e4 | 5382 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
17ac10ad | 5383 | |
6aa8b732 | 5384 | return 0; |
6aa8b732 AK |
5385 | } |
5386 | ||
8018c27b | 5387 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5388 | { |
1cfff4d9 | 5389 | int ret; |
b94742c9 | 5390 | |
5962bfb7 | 5391 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5392 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5393 | ||
5962bfb7 | 5394 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5395 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5396 | |
96880883 SC |
5397 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5398 | ||
44dd3ffa VK |
5399 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5400 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5401 | |
14c07ad8 | 5402 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5403 | |
04d28e37 | 5404 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5405 | if (ret) |
5406 | return ret; | |
5407 | ||
04d28e37 | 5408 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5409 | if (ret) |
5410 | goto fail_allocate_root; | |
5411 | ||
5412 | return ret; | |
5413 | fail_allocate_root: | |
5414 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5415 | return ret; | |
6aa8b732 AK |
5416 | } |
5417 | ||
fbb158cb | 5418 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5419 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5420 | { | |
5421 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5422 | int nr_zapped, batch = 0; |
002c5f73 SC |
5423 | |
5424 | restart: | |
5425 | list_for_each_entry_safe_reverse(sp, node, | |
5426 | &kvm->arch.active_mmu_pages, link) { | |
5427 | /* | |
5428 | * No obsolete valid page exists before a newly created page | |
5429 | * since active_mmu_pages is a FIFO list. | |
5430 | */ | |
5431 | if (!is_obsolete_sp(kvm, sp)) | |
5432 | break; | |
5433 | ||
5434 | /* | |
f95eec9b SC |
5435 | * Invalid pages should never land back on the list of active |
5436 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5437 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5438 | */ |
f95eec9b | 5439 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5440 | continue; |
5441 | ||
4506ecf4 SC |
5442 | /* |
5443 | * No need to flush the TLB since we're only zapping shadow | |
5444 | * pages with an obsolete generation number and all vCPUS have | |
5445 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5446 | * be in active use by the guest. | |
5447 | */ | |
fbb158cb | 5448 | if (batch >= BATCH_ZAP_PAGES && |
531810ca | 5449 | cond_resched_rwlock_write(&kvm->mmu_lock)) { |
fbb158cb | 5450 | batch = 0; |
002c5f73 SC |
5451 | goto restart; |
5452 | } | |
5453 | ||
10605204 SC |
5454 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5455 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5456 | batch += nr_zapped; |
002c5f73 | 5457 | goto restart; |
fbb158cb | 5458 | } |
002c5f73 SC |
5459 | } |
5460 | ||
4506ecf4 SC |
5461 | /* |
5462 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5463 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5464 | * may reference the pages. | |
5465 | */ | |
10605204 | 5466 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5467 | } |
5468 | ||
5469 | /* | |
5470 | * Fast invalidate all shadow pages and use lock-break technique | |
5471 | * to zap obsolete pages. | |
5472 | * | |
5473 | * It's required when memslot is being deleted or VM is being | |
5474 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5475 | * not use any resource of the being-deleted slot or all slots | |
5476 | * after calling the function. | |
5477 | */ | |
5478 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5479 | { | |
ca333add SC |
5480 | lockdep_assert_held(&kvm->slots_lock); |
5481 | ||
531810ca | 5482 | write_lock(&kvm->mmu_lock); |
14a3c4f4 | 5483 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5484 | |
5485 | /* | |
5486 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5487 | * held for the entire duration of zapping obsolete pages, it's | |
5488 | * impossible for there to be multiple invalid generations associated | |
5489 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5490 | * one valid generation and (at most) one invalid generation. | |
5491 | */ | |
5492 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5493 | |
b7cccd39 BG |
5494 | /* In order to ensure all threads see this change when |
5495 | * handling the MMU reload signal, this must happen in the | |
5496 | * same critical section as kvm_reload_remote_mmus, and | |
5497 | * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages | |
5498 | * could drop the MMU lock and yield. | |
5499 | */ | |
5500 | if (is_tdp_mmu_enabled(kvm)) | |
5501 | kvm_tdp_mmu_invalidate_all_roots(kvm); | |
5502 | ||
4506ecf4 SC |
5503 | /* |
5504 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5505 | * Then all vcpus will switch to new shadow page table with the new | |
5506 | * mmu_valid_gen. | |
5507 | * | |
5508 | * Note: we need to do this under the protection of mmu_lock, | |
5509 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5510 | */ | |
5511 | kvm_reload_remote_mmus(kvm); | |
5512 | ||
002c5f73 | 5513 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 | 5514 | |
531810ca | 5515 | write_unlock(&kvm->mmu_lock); |
4c6654bd BG |
5516 | |
5517 | if (is_tdp_mmu_enabled(kvm)) { | |
5518 | read_lock(&kvm->mmu_lock); | |
5519 | kvm_tdp_mmu_zap_invalidated_roots(kvm); | |
5520 | read_unlock(&kvm->mmu_lock); | |
5521 | } | |
002c5f73 SC |
5522 | } |
5523 | ||
10605204 SC |
5524 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5525 | { | |
5526 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5527 | } | |
5528 | ||
b5f5fdca | 5529 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5530 | struct kvm_memory_slot *slot, |
5531 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5532 | { |
002c5f73 | 5533 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5534 | } |
5535 | ||
13d268ca | 5536 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5537 | { |
13d268ca | 5538 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5539 | |
d501f747 BG |
5540 | if (!kvm_mmu_init_tdp_mmu(kvm)) |
5541 | /* | |
5542 | * No smp_load/store wrappers needed here as we are in | |
5543 | * VM init and there cannot be any memslots / other threads | |
5544 | * accessing this struct kvm yet. | |
5545 | */ | |
5546 | kvm->arch.memslots_have_rmaps = true; | |
fe5db27d | 5547 | |
13d268ca | 5548 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5549 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5550 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5551 | } |
5552 | ||
13d268ca | 5553 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5554 | { |
13d268ca | 5555 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5556 | |
13d268ca | 5557 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5558 | |
5559 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5560 | } |
5561 | ||
efdfe536 XG |
5562 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5563 | { | |
5564 | struct kvm_memslots *slots; | |
5565 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5566 | int i; |
1a61b7db | 5567 | bool flush = false; |
efdfe536 | 5568 | |
e2209710 BG |
5569 | if (kvm_memslots_have_rmaps(kvm)) { |
5570 | write_lock(&kvm->mmu_lock); | |
5571 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
5572 | slots = __kvm_memslots(kvm, i); | |
5573 | kvm_for_each_memslot(memslot, slots) { | |
5574 | gfn_t start, end; | |
5575 | ||
5576 | start = max(gfn_start, memslot->base_gfn); | |
5577 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5578 | if (start >= end) | |
5579 | continue; | |
efdfe536 | 5580 | |
e2209710 BG |
5581 | flush = slot_handle_level_range(kvm, memslot, |
5582 | kvm_zap_rmapp, PG_LEVEL_4K, | |
5583 | KVM_MAX_HUGEPAGE_LEVEL, start, | |
5584 | end - 1, true, flush); | |
5585 | } | |
9da0e4d5 | 5586 | } |
e2209710 BG |
5587 | if (flush) |
5588 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end); | |
5589 | write_unlock(&kvm->mmu_lock); | |
efdfe536 XG |
5590 | } |
5591 | ||
897218ff | 5592 | if (is_tdp_mmu_enabled(kvm)) { |
6103bc07 BG |
5593 | flush = false; |
5594 | ||
5595 | read_lock(&kvm->mmu_lock); | |
5596 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) | |
5597 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start, | |
5598 | gfn_end, flush, true); | |
faaf05b0 | 5599 | if (flush) |
6103bc07 BG |
5600 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, |
5601 | gfn_end); | |
faaf05b0 | 5602 | |
6103bc07 BG |
5603 | read_unlock(&kvm->mmu_lock); |
5604 | } | |
efdfe536 XG |
5605 | } |
5606 | ||
018aabb5 | 5607 | static bool slot_rmap_write_protect(struct kvm *kvm, |
0a234f5d SC |
5608 | struct kvm_rmap_head *rmap_head, |
5609 | struct kvm_memory_slot *slot) | |
d77aa73c | 5610 | { |
018aabb5 | 5611 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5612 | } |
5613 | ||
1c91cad4 | 5614 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5615 | struct kvm_memory_slot *memslot, |
5616 | int start_level) | |
6aa8b732 | 5617 | { |
e2209710 | 5618 | bool flush = false; |
6aa8b732 | 5619 | |
e2209710 BG |
5620 | if (kvm_memslots_have_rmaps(kvm)) { |
5621 | write_lock(&kvm->mmu_lock); | |
5622 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, | |
5623 | start_level, KVM_MAX_HUGEPAGE_LEVEL, | |
5624 | false); | |
5625 | write_unlock(&kvm->mmu_lock); | |
5626 | } | |
198c74f4 | 5627 | |
24ae4cfa BG |
5628 | if (is_tdp_mmu_enabled(kvm)) { |
5629 | read_lock(&kvm->mmu_lock); | |
5630 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level); | |
5631 | read_unlock(&kvm->mmu_lock); | |
5632 | } | |
5633 | ||
198c74f4 XG |
5634 | /* |
5635 | * We can flush all the TLBs out of the mmu lock without TLB | |
5636 | * corruption since we just change the spte from writable to | |
5637 | * readonly so that we only need to care the case of changing | |
5638 | * spte from present to present (changing the spte from present | |
5639 | * to nonpresent will flush all the TLBs immediately), in other | |
5640 | * words, the only case we care is mmu_spte_update() where we | |
5fc3424f SC |
5641 | * have checked Host-writable | MMU-writable instead of |
5642 | * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK | |
5643 | * anymore. | |
198c74f4 | 5644 | */ |
d91ffee9 | 5645 | if (flush) |
7f42aa76 | 5646 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5647 | } |
37a7d8b0 | 5648 | |
3ea3b7fa | 5649 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
0a234f5d SC |
5650 | struct kvm_rmap_head *rmap_head, |
5651 | struct kvm_memory_slot *slot) | |
3ea3b7fa WL |
5652 | { |
5653 | u64 *sptep; | |
5654 | struct rmap_iterator iter; | |
5655 | int need_tlb_flush = 0; | |
ba049e93 | 5656 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5657 | struct kvm_mmu_page *sp; |
5658 | ||
0d536790 | 5659 | restart: |
018aabb5 | 5660 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5661 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5662 | pfn = spte_to_pfn(*sptep); |
5663 | ||
5664 | /* | |
decf6333 XG |
5665 | * We cannot do huge page mapping for indirect shadow pages, |
5666 | * which are found on the last rmap (level = 1) when not using | |
5667 | * tdp; such shadow pages are synced with the page table in | |
5668 | * the guest, and the guest page table is using 4K page size | |
5669 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5670 | */ |
a78986aa | 5671 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
9eba50f8 SC |
5672 | sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn, |
5673 | pfn, PG_LEVEL_NUM)) { | |
e7912386 | 5674 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5675 | |
5676 | if (kvm_available_flush_tlb_with_range()) | |
5677 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5678 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5679 | else | |
5680 | need_tlb_flush = 1; | |
5681 | ||
0d536790 XG |
5682 | goto restart; |
5683 | } | |
3ea3b7fa WL |
5684 | } |
5685 | ||
5686 | return need_tlb_flush; | |
5687 | } | |
5688 | ||
5689 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5690 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5691 | { |
f36f3f28 | 5692 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
9eba50f8 | 5693 | struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot; |
31c65657 | 5694 | bool flush = false; |
14881998 | 5695 | |
e2209710 BG |
5696 | if (kvm_memslots_have_rmaps(kvm)) { |
5697 | write_lock(&kvm->mmu_lock); | |
5698 | flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true); | |
5699 | if (flush) | |
5700 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5701 | write_unlock(&kvm->mmu_lock); | |
5702 | } | |
2db6f772 BG |
5703 | |
5704 | if (is_tdp_mmu_enabled(kvm)) { | |
2db6f772 BG |
5705 | read_lock(&kvm->mmu_lock); |
5706 | flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush); | |
5707 | if (flush) | |
5708 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5709 | read_unlock(&kvm->mmu_lock); | |
5710 | } | |
3ea3b7fa WL |
5711 | } |
5712 | ||
b3594ffb | 5713 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
6c9dd6d2 | 5714 | const struct kvm_memory_slot *memslot) |
b3594ffb SC |
5715 | { |
5716 | /* | |
7f42aa76 | 5717 | * All current use cases for flushing the TLBs for a specific memslot |
302695a5 | 5718 | * related to dirty logging, and many do the TLB flush out of mmu_lock. |
7f42aa76 SC |
5719 | * The interaction between the various operations on memslot must be |
5720 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5721 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5722 | */ |
5723 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5724 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5725 | memslot->npages); | |
b3594ffb SC |
5726 | } |
5727 | ||
f4b4b180 KH |
5728 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5729 | struct kvm_memory_slot *memslot) | |
5730 | { | |
e2209710 | 5731 | bool flush = false; |
f4b4b180 | 5732 | |
e2209710 BG |
5733 | if (kvm_memslots_have_rmaps(kvm)) { |
5734 | write_lock(&kvm->mmu_lock); | |
5735 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, | |
5736 | false); | |
5737 | write_unlock(&kvm->mmu_lock); | |
5738 | } | |
f4b4b180 | 5739 | |
24ae4cfa BG |
5740 | if (is_tdp_mmu_enabled(kvm)) { |
5741 | read_lock(&kvm->mmu_lock); | |
5742 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); | |
5743 | read_unlock(&kvm->mmu_lock); | |
5744 | } | |
5745 | ||
f4b4b180 KH |
5746 | /* |
5747 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5748 | * function is only used for dirty logging, in which case flushing TLB | |
5749 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5750 | * dirty_bitmap. | |
5751 | */ | |
5752 | if (flush) | |
7f42aa76 | 5753 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 | 5754 | } |
f4b4b180 | 5755 | |
92f58b5c | 5756 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5757 | { |
5758 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5759 | LIST_HEAD(invalid_list); |
83cdb568 | 5760 | int ign; |
5304b8d3 | 5761 | |
531810ca | 5762 | write_lock(&kvm->mmu_lock); |
5304b8d3 | 5763 | restart: |
8a674adc | 5764 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5765 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5766 | continue; |
92f58b5c | 5767 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5768 | goto restart; |
531810ca | 5769 | if (cond_resched_rwlock_write(&kvm->mmu_lock)) |
5304b8d3 XG |
5770 | goto restart; |
5771 | } | |
5772 | ||
4771450c | 5773 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 | 5774 | |
897218ff | 5775 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5776 | kvm_tdp_mmu_zap_all(kvm); |
5777 | ||
531810ca | 5778 | write_unlock(&kvm->mmu_lock); |
5304b8d3 XG |
5779 | } |
5780 | ||
15248258 | 5781 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5782 | { |
164bf7e5 | 5783 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5784 | |
164bf7e5 | 5785 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5786 | |
f8f55942 | 5787 | /* |
e1359e2b SC |
5788 | * Generation numbers are incremented in multiples of the number of |
5789 | * address spaces in order to provide unique generations across all | |
5790 | * address spaces. Strip what is effectively the address space | |
5791 | * modifier prior to checking for a wrap of the MMIO generation so | |
5792 | * that a wrap in any address space is detected. | |
5793 | */ | |
5794 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5795 | ||
f8f55942 | 5796 | /* |
e1359e2b | 5797 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5798 | * zap all shadow pages. |
f8f55942 | 5799 | */ |
e1359e2b | 5800 | if (unlikely(gen == 0)) { |
ae0f5499 | 5801 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5802 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5803 | } |
f8f55942 XG |
5804 | } |
5805 | ||
70534a73 DC |
5806 | static unsigned long |
5807 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5808 | { |
5809 | struct kvm *kvm; | |
1495f230 | 5810 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5811 | unsigned long freed = 0; |
3ee16c81 | 5812 | |
0d9ce162 | 5813 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5814 | |
5815 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5816 | int idx; |
d98ba053 | 5817 | LIST_HEAD(invalid_list); |
3ee16c81 | 5818 | |
35f2d16b TY |
5819 | /* |
5820 | * Never scan more than sc->nr_to_scan VM instances. | |
5821 | * Will not hit this condition practically since we do not try | |
5822 | * to shrink more than one VM and it is very unlikely to see | |
5823 | * !n_used_mmu_pages so many times. | |
5824 | */ | |
5825 | if (!nr_to_scan--) | |
5826 | break; | |
19526396 GN |
5827 | /* |
5828 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5829 | * here. We may skip a VM instance errorneosly, but we do not | |
5830 | * want to shrink a VM that only started to populate its MMU | |
5831 | * anyway. | |
5832 | */ | |
10605204 SC |
5833 | if (!kvm->arch.n_used_mmu_pages && |
5834 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5835 | continue; |
19526396 | 5836 | |
f656ce01 | 5837 | idx = srcu_read_lock(&kvm->srcu); |
531810ca | 5838 | write_lock(&kvm->mmu_lock); |
3ee16c81 | 5839 | |
10605204 SC |
5840 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5841 | kvm_mmu_commit_zap_page(kvm, | |
5842 | &kvm->arch.zapped_obsolete_pages); | |
5843 | goto unlock; | |
5844 | } | |
5845 | ||
ebdb292d | 5846 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5847 | |
10605204 | 5848 | unlock: |
531810ca | 5849 | write_unlock(&kvm->mmu_lock); |
f656ce01 | 5850 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5851 | |
70534a73 DC |
5852 | /* |
5853 | * unfair on small ones | |
5854 | * per-vm shrinkers cry out | |
5855 | * sadness comes quickly | |
5856 | */ | |
19526396 GN |
5857 | list_move_tail(&kvm->vm_list, &vm_list); |
5858 | break; | |
3ee16c81 | 5859 | } |
3ee16c81 | 5860 | |
0d9ce162 | 5861 | mutex_unlock(&kvm_lock); |
70534a73 | 5862 | return freed; |
70534a73 DC |
5863 | } |
5864 | ||
5865 | static unsigned long | |
5866 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5867 | { | |
45221ab6 | 5868 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5869 | } |
5870 | ||
5871 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5872 | .count_objects = mmu_shrink_count, |
5873 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5874 | .seeks = DEFAULT_SEEKS * 10, |
5875 | }; | |
5876 | ||
2ddfd20e | 5877 | static void mmu_destroy_caches(void) |
b5a33a75 | 5878 | { |
c1bd743e TH |
5879 | kmem_cache_destroy(pte_list_desc_cache); |
5880 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5881 | } |
5882 | ||
b8e8c830 PB |
5883 | static bool get_nx_auto_mode(void) |
5884 | { | |
5885 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5886 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5887 | } | |
5888 | ||
5889 | static void __set_nx_huge_pages(bool val) | |
5890 | { | |
5891 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5892 | } | |
5893 | ||
5894 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5895 | { | |
5896 | bool old_val = nx_huge_pages; | |
5897 | bool new_val; | |
5898 | ||
5899 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5900 | if (sysfs_streq(val, "off")) | |
5901 | new_val = 0; | |
5902 | else if (sysfs_streq(val, "force")) | |
5903 | new_val = 1; | |
5904 | else if (sysfs_streq(val, "auto")) | |
5905 | new_val = get_nx_auto_mode(); | |
5906 | else if (strtobool(val, &new_val) < 0) | |
5907 | return -EINVAL; | |
5908 | ||
5909 | __set_nx_huge_pages(new_val); | |
5910 | ||
5911 | if (new_val != old_val) { | |
5912 | struct kvm *kvm; | |
b8e8c830 PB |
5913 | |
5914 | mutex_lock(&kvm_lock); | |
5915 | ||
5916 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 5917 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 5918 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 5919 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
5920 | |
5921 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
5922 | } |
5923 | mutex_unlock(&kvm_lock); | |
5924 | } | |
5925 | ||
5926 | return 0; | |
5927 | } | |
5928 | ||
b5a33a75 AK |
5929 | int kvm_mmu_module_init(void) |
5930 | { | |
ab271bd4 AB |
5931 | int ret = -ENOMEM; |
5932 | ||
b8e8c830 PB |
5933 | if (nx_huge_pages == -1) |
5934 | __set_nx_huge_pages(get_nx_auto_mode()); | |
5935 | ||
36d9594d VK |
5936 | /* |
5937 | * MMU roles use union aliasing which is, generally speaking, an | |
5938 | * undefined behavior. However, we supposedly know how compilers behave | |
5939 | * and the current status quo is unlikely to change. Guardians below are | |
5940 | * supposed to let us know if the assumption becomes false. | |
5941 | */ | |
5942 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
5943 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
5944 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
5945 | ||
28a1f3ac | 5946 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 5947 | |
53c07b18 XG |
5948 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5949 | sizeof(struct pte_list_desc), | |
46bea48a | 5950 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5951 | if (!pte_list_desc_cache) |
ab271bd4 | 5952 | goto out; |
b5a33a75 | 5953 | |
d3d25b04 AK |
5954 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5955 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5956 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5957 | if (!mmu_page_header_cache) |
ab271bd4 | 5958 | goto out; |
d3d25b04 | 5959 | |
908c7f19 | 5960 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5961 | goto out; |
45bf21a8 | 5962 | |
ab271bd4 AB |
5963 | ret = register_shrinker(&mmu_shrinker); |
5964 | if (ret) | |
5965 | goto out; | |
3ee16c81 | 5966 | |
b5a33a75 AK |
5967 | return 0; |
5968 | ||
ab271bd4 | 5969 | out: |
3ee16c81 | 5970 | mmu_destroy_caches(); |
ab271bd4 | 5971 | return ret; |
b5a33a75 AK |
5972 | } |
5973 | ||
3ad82a7e | 5974 | /* |
39337ad1 | 5975 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 5976 | */ |
bc8a3d89 | 5977 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 5978 | { |
bc8a3d89 BG |
5979 | unsigned long nr_mmu_pages; |
5980 | unsigned long nr_pages = 0; | |
bc6678a3 | 5981 | struct kvm_memslots *slots; |
be6ba0f0 | 5982 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5983 | int i; |
3ad82a7e | 5984 | |
9da0e4d5 PB |
5985 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5986 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5987 | |
9da0e4d5 PB |
5988 | kvm_for_each_memslot(memslot, slots) |
5989 | nr_pages += memslot->npages; | |
5990 | } | |
3ad82a7e ZX |
5991 | |
5992 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 5993 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5994 | |
5995 | return nr_mmu_pages; | |
5996 | } | |
5997 | ||
c42fffe3 XG |
5998 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5999 | { | |
95f93af4 | 6000 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
6001 | free_mmu_pages(&vcpu->arch.root_mmu); |
6002 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 6003 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
6004 | } |
6005 | ||
b034cf01 XG |
6006 | void kvm_mmu_module_exit(void) |
6007 | { | |
6008 | mmu_destroy_caches(); | |
6009 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6010 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6011 | mmu_audit_disable(); |
6012 | } | |
1aa9b957 JS |
6013 | |
6014 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
6015 | { | |
6016 | unsigned int old_val; | |
6017 | int err; | |
6018 | ||
6019 | old_val = nx_huge_pages_recovery_ratio; | |
6020 | err = param_set_uint(val, kp); | |
6021 | if (err) | |
6022 | return err; | |
6023 | ||
6024 | if (READ_ONCE(nx_huge_pages) && | |
6025 | !old_val && nx_huge_pages_recovery_ratio) { | |
6026 | struct kvm *kvm; | |
6027 | ||
6028 | mutex_lock(&kvm_lock); | |
6029 | ||
6030 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6031 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
6032 | ||
6033 | mutex_unlock(&kvm_lock); | |
6034 | } | |
6035 | ||
6036 | return err; | |
6037 | } | |
6038 | ||
6039 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
6040 | { | |
ade74e14 | 6041 | unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits; |
1aa9b957 JS |
6042 | int rcu_idx; |
6043 | struct kvm_mmu_page *sp; | |
6044 | unsigned int ratio; | |
6045 | LIST_HEAD(invalid_list); | |
048f4980 | 6046 | bool flush = false; |
1aa9b957 JS |
6047 | ulong to_zap; |
6048 | ||
6049 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
531810ca | 6050 | write_lock(&kvm->mmu_lock); |
1aa9b957 JS |
6051 | |
6052 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
ade74e14 | 6053 | to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0; |
7d919c7a SC |
6054 | for ( ; to_zap; --to_zap) { |
6055 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
6056 | break; | |
6057 | ||
1aa9b957 JS |
6058 | /* |
6059 | * We use a separate list instead of just using active_mmu_pages | |
6060 | * because the number of lpage_disallowed pages is expected to | |
6061 | * be relatively small compared to the total. | |
6062 | */ | |
6063 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
6064 | struct kvm_mmu_page, | |
6065 | lpage_disallowed_link); | |
6066 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
897218ff | 6067 | if (is_tdp_mmu_page(sp)) { |
315f02c6 | 6068 | flush |= kvm_tdp_mmu_zap_sp(kvm, sp); |
8d1a182e | 6069 | } else { |
29cf0f50 BG |
6070 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
6071 | WARN_ON_ONCE(sp->lpage_disallowed); | |
6072 | } | |
1aa9b957 | 6073 | |
531810ca | 6074 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
048f4980 | 6075 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
531810ca | 6076 | cond_resched_rwlock_write(&kvm->mmu_lock); |
048f4980 | 6077 | flush = false; |
1aa9b957 JS |
6078 | } |
6079 | } | |
048f4980 | 6080 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
1aa9b957 | 6081 | |
531810ca | 6082 | write_unlock(&kvm->mmu_lock); |
1aa9b957 JS |
6083 | srcu_read_unlock(&kvm->srcu, rcu_idx); |
6084 | } | |
6085 | ||
6086 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6087 | { | |
6088 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6089 | ? start_time + 60 * HZ - get_jiffies_64() | |
6090 | : MAX_SCHEDULE_TIMEOUT; | |
6091 | } | |
6092 | ||
6093 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6094 | { | |
6095 | u64 start_time; | |
6096 | long remaining_time; | |
6097 | ||
6098 | while (true) { | |
6099 | start_time = get_jiffies_64(); | |
6100 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6101 | ||
6102 | set_current_state(TASK_INTERRUPTIBLE); | |
6103 | while (!kthread_should_stop() && remaining_time > 0) { | |
6104 | schedule_timeout(remaining_time); | |
6105 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6106 | set_current_state(TASK_INTERRUPTIBLE); | |
6107 | } | |
6108 | ||
6109 | set_current_state(TASK_RUNNING); | |
6110 | ||
6111 | if (kthread_should_stop()) | |
6112 | return 0; | |
6113 | ||
6114 | kvm_recover_nx_lpages(kvm); | |
6115 | } | |
6116 | } | |
6117 | ||
6118 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6119 | { | |
6120 | int err; | |
6121 | ||
6122 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6123 | "kvm-nx-lpage-recovery", | |
6124 | &kvm->arch.nx_lpage_recovery_thread); | |
6125 | if (!err) | |
6126 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6127 | ||
6128 | return err; | |
6129 | } | |
6130 | ||
6131 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6132 | { | |
6133 | if (kvm->arch.nx_lpage_recovery_thread) | |
6134 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6135 | } |