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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
4a98623d | 51 | #include <asm/set_memory.h> |
13673a90 | 52 | #include <asm/vmx.h> |
3d0c27ad | 53 | #include <asm/kvm_page_track.h> |
1261bfa3 | 54 | #include "trace.h" |
6aa8b732 | 55 | |
b8e8c830 PB |
56 | extern bool itlb_multihit_kvm_mitigation; |
57 | ||
a9d6496d | 58 | int __read_mostly nx_huge_pages = -1; |
13fb5927 PB |
59 | #ifdef CONFIG_PREEMPT_RT |
60 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
61 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
62 | #else | |
1aa9b957 | 63 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 64 | #endif |
b8e8c830 PB |
65 | |
66 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 67 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 68 | |
d5d6c18d | 69 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
70 | .set = set_nx_huge_pages, |
71 | .get = param_get_bool, | |
72 | }; | |
73 | ||
d5d6c18d | 74 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
75 | .set = set_nx_huge_pages_recovery_ratio, |
76 | .get = param_get_uint, | |
77 | }; | |
78 | ||
b8e8c830 PB |
79 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
80 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
81 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
82 | &nx_huge_pages_recovery_ratio, 0644); | |
83 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 84 | |
71fe7013 SC |
85 | static bool __read_mostly force_flush_and_sync_on_reuse; |
86 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
87 | ||
18552672 JR |
88 | /* |
89 | * When setting this variable to true it enables Two-Dimensional-Paging | |
90 | * where the hardware walks 2 page tables: | |
91 | * 1. the guest-virtual to guest-physical | |
92 | * 2. while doing 1. it walks guest-physical to host-physical | |
93 | * If the hardware supports that we don't need to do shadow paging. | |
94 | */ | |
2f333bcb | 95 | bool tdp_enabled = false; |
18552672 | 96 | |
1d92d2e8 | 97 | static int max_huge_page_level __read_mostly; |
83013059 | 98 | static int max_tdp_level __read_mostly; |
703c335d | 99 | |
8b1fe17c XG |
100 | enum { |
101 | AUDIT_PRE_PAGE_FAULT, | |
102 | AUDIT_POST_PAGE_FAULT, | |
103 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
104 | AUDIT_POST_PTE_WRITE, |
105 | AUDIT_PRE_SYNC, | |
106 | AUDIT_POST_SYNC | |
8b1fe17c | 107 | }; |
37a7d8b0 | 108 | |
37a7d8b0 | 109 | #ifdef MMU_DEBUG |
5a9624af | 110 | bool dbg = 0; |
fa4a2c08 | 111 | module_param(dbg, bool, 0644); |
d6c69ee9 | 112 | #endif |
6aa8b732 | 113 | |
957ed9ef XG |
114 | #define PTE_PREFETCH_NUM 8 |
115 | ||
6aa8b732 AK |
116 | #define PT32_LEVEL_BITS 10 |
117 | ||
118 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 119 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 120 | |
e04da980 JR |
121 | #define PT32_LVL_OFFSET_MASK(level) \ |
122 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
124 | |
125 | #define PT32_INDEX(address, level)\ | |
126 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
127 | ||
128 | ||
6aa8b732 AK |
129 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
130 | #define PT32_DIR_BASE_ADDR_MASK \ | |
131 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
132 | #define PT32_LVL_ADDR_MASK(level) \ |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
134 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 135 | |
90bb6fc5 AK |
136 | #include <trace/events/kvm.h> |
137 | ||
220f773a TY |
138 | /* make pte_list_desc fit well in cache line */ |
139 | #define PTE_LIST_EXT 3 | |
140 | ||
53c07b18 XG |
141 | struct pte_list_desc { |
142 | u64 *sptes[PTE_LIST_EXT]; | |
143 | struct pte_list_desc *more; | |
cd4a4e53 AK |
144 | }; |
145 | ||
2d11123a AK |
146 | struct kvm_shadow_walk_iterator { |
147 | u64 addr; | |
148 | hpa_t shadow_addr; | |
2d11123a | 149 | u64 *sptep; |
dd3bfd59 | 150 | int level; |
2d11123a AK |
151 | unsigned index; |
152 | }; | |
153 | ||
7eb77e9f JS |
154 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
155 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
156 | (_root), (_addr)); \ | |
157 | shadow_walk_okay(&(_walker)); \ | |
158 | shadow_walk_next(&(_walker))) | |
159 | ||
160 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
161 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
162 | shadow_walk_okay(&(_walker)); \ | |
163 | shadow_walk_next(&(_walker))) | |
164 | ||
c2a2ac2b XG |
165 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
166 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
167 | shadow_walk_okay(&(_walker)) && \ | |
168 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
169 | __shadow_walk_next(&(_walker), spte)) | |
170 | ||
53c07b18 | 171 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 172 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 173 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 174 | |
ce88decf | 175 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
176 | static union kvm_mmu_page_role |
177 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 178 | |
335e192a PB |
179 | #define CREATE_TRACE_POINTS |
180 | #include "mmutrace.h" | |
181 | ||
40ef75a7 LT |
182 | |
183 | static inline bool kvm_available_flush_tlb_with_range(void) | |
184 | { | |
afaf0b2f | 185 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
186 | } |
187 | ||
188 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
189 | struct kvm_tlb_range *range) | |
190 | { | |
191 | int ret = -ENOTSUPP; | |
192 | ||
afaf0b2f | 193 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
b3646477 | 194 | ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range); |
40ef75a7 LT |
195 | |
196 | if (ret) | |
197 | kvm_flush_remote_tlbs(kvm); | |
198 | } | |
199 | ||
2f2fad08 | 200 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
201 | u64 start_gfn, u64 pages) |
202 | { | |
203 | struct kvm_tlb_range range; | |
204 | ||
205 | range.start_gfn = start_gfn; | |
206 | range.pages = pages; | |
207 | ||
208 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
209 | } | |
210 | ||
8f79b064 BG |
211 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
212 | unsigned int access) | |
213 | { | |
c236d962 | 214 | u64 spte = make_mmio_spte(vcpu, gfn, access); |
8f79b064 | 215 | |
c236d962 SC |
216 | trace_mark_mmio_spte(sptep, gfn, spte); |
217 | mmu_spte_set(sptep, spte); | |
ce88decf XG |
218 | } |
219 | ||
ce88decf XG |
220 | static gfn_t get_mmio_spte_gfn(u64 spte) |
221 | { | |
daa07cbc | 222 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 223 | |
8a967d65 | 224 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
225 | & shadow_nonpresent_or_rsvd_mask; |
226 | ||
227 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
228 | } |
229 | ||
230 | static unsigned get_mmio_spte_access(u64 spte) | |
231 | { | |
4af77151 | 232 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
233 | } |
234 | ||
54bf36aa | 235 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 236 | { |
cae7ed3c | 237 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 238 | |
cae7ed3c SC |
239 | gen = kvm_vcpu_memslots(vcpu)->generation; |
240 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
241 | return false; | |
089504c0 | 242 | |
cae7ed3c | 243 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
244 | spte_gen = get_mmio_spte_generation(spte); |
245 | ||
246 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
247 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
248 | } |
249 | ||
cd313569 MG |
250 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
251 | struct x86_exception *exception) | |
252 | { | |
ec7771ab | 253 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 254 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
255 | exception->error_code |= PFERR_RSVD_MASK; |
256 | return UNMAPPED_GVA; | |
257 | } | |
258 | ||
cd313569 MG |
259 | return gpa; |
260 | } | |
261 | ||
6aa8b732 AK |
262 | static int is_cpuid_PSE36(void) |
263 | { | |
264 | return 1; | |
265 | } | |
266 | ||
73b1087e AK |
267 | static int is_nx(struct kvm_vcpu *vcpu) |
268 | { | |
f6801dff | 269 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
270 | } |
271 | ||
da928521 AK |
272 | static gfn_t pse36_gfn_delta(u32 gpte) |
273 | { | |
274 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
275 | ||
276 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
277 | } | |
278 | ||
603e0651 | 279 | #ifdef CONFIG_X86_64 |
d555c333 | 280 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 281 | { |
b19ee2ff | 282 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
283 | } |
284 | ||
603e0651 | 285 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 286 | { |
b19ee2ff | 287 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
288 | } |
289 | ||
290 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
291 | { | |
292 | return xchg(sptep, spte); | |
293 | } | |
c2a2ac2b XG |
294 | |
295 | static u64 __get_spte_lockless(u64 *sptep) | |
296 | { | |
6aa7de05 | 297 | return READ_ONCE(*sptep); |
c2a2ac2b | 298 | } |
a9221dd5 | 299 | #else |
603e0651 XG |
300 | union split_spte { |
301 | struct { | |
302 | u32 spte_low; | |
303 | u32 spte_high; | |
304 | }; | |
305 | u64 spte; | |
306 | }; | |
a9221dd5 | 307 | |
c2a2ac2b XG |
308 | static void count_spte_clear(u64 *sptep, u64 spte) |
309 | { | |
57354682 | 310 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
311 | |
312 | if (is_shadow_present_pte(spte)) | |
313 | return; | |
314 | ||
315 | /* Ensure the spte is completely set before we increase the count */ | |
316 | smp_wmb(); | |
317 | sp->clear_spte_count++; | |
318 | } | |
319 | ||
603e0651 XG |
320 | static void __set_spte(u64 *sptep, u64 spte) |
321 | { | |
322 | union split_spte *ssptep, sspte; | |
a9221dd5 | 323 | |
603e0651 XG |
324 | ssptep = (union split_spte *)sptep; |
325 | sspte = (union split_spte)spte; | |
326 | ||
327 | ssptep->spte_high = sspte.spte_high; | |
328 | ||
329 | /* | |
330 | * If we map the spte from nonpresent to present, We should store | |
331 | * the high bits firstly, then set present bit, so cpu can not | |
332 | * fetch this spte while we are setting the spte. | |
333 | */ | |
334 | smp_wmb(); | |
335 | ||
b19ee2ff | 336 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
337 | } |
338 | ||
603e0651 XG |
339 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
340 | { | |
341 | union split_spte *ssptep, sspte; | |
342 | ||
343 | ssptep = (union split_spte *)sptep; | |
344 | sspte = (union split_spte)spte; | |
345 | ||
b19ee2ff | 346 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
347 | |
348 | /* | |
349 | * If we map the spte from present to nonpresent, we should clear | |
350 | * present bit firstly to avoid vcpu fetch the old high bits. | |
351 | */ | |
352 | smp_wmb(); | |
353 | ||
354 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 355 | count_spte_clear(sptep, spte); |
603e0651 XG |
356 | } |
357 | ||
358 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
359 | { | |
360 | union split_spte *ssptep, sspte, orig; | |
361 | ||
362 | ssptep = (union split_spte *)sptep; | |
363 | sspte = (union split_spte)spte; | |
364 | ||
365 | /* xchg acts as a barrier before the setting of the high bits */ | |
366 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
367 | orig.spte_high = ssptep->spte_high; |
368 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 369 | count_spte_clear(sptep, spte); |
603e0651 XG |
370 | |
371 | return orig.spte; | |
372 | } | |
c2a2ac2b XG |
373 | |
374 | /* | |
375 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 376 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
377 | * |
378 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
379 | * coalesces them and we are running out of the MMU lock. Therefore | |
380 | * we need to protect against in-progress updates of the spte. | |
381 | * | |
382 | * Reading the spte while an update is in progress may get the old value | |
383 | * for the high part of the spte. The race is fine for a present->non-present | |
384 | * change (because the high part of the spte is ignored for non-present spte), | |
385 | * but for a present->present change we must reread the spte. | |
386 | * | |
387 | * All such changes are done in two steps (present->non-present and | |
388 | * non-present->present), hence it is enough to count the number of | |
389 | * present->non-present updates: if it changed while reading the spte, | |
390 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
391 | */ |
392 | static u64 __get_spte_lockless(u64 *sptep) | |
393 | { | |
57354682 | 394 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
395 | union split_spte spte, *orig = (union split_spte *)sptep; |
396 | int count; | |
397 | ||
398 | retry: | |
399 | count = sp->clear_spte_count; | |
400 | smp_rmb(); | |
401 | ||
402 | spte.spte_low = orig->spte_low; | |
403 | smp_rmb(); | |
404 | ||
405 | spte.spte_high = orig->spte_high; | |
406 | smp_rmb(); | |
407 | ||
408 | if (unlikely(spte.spte_low != orig->spte_low || | |
409 | count != sp->clear_spte_count)) | |
410 | goto retry; | |
411 | ||
412 | return spte.spte; | |
413 | } | |
603e0651 XG |
414 | #endif |
415 | ||
8672b721 XG |
416 | static bool spte_has_volatile_bits(u64 spte) |
417 | { | |
f160c7b7 JS |
418 | if (!is_shadow_present_pte(spte)) |
419 | return false; | |
420 | ||
c7ba5b48 | 421 | /* |
6a6256f9 | 422 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
423 | * out of mmu-lock, it can ensure dirty bit is not lost, |
424 | * also, it can help us to get a stable is_writable_pte() | |
425 | * to ensure tlb flush is not missed. | |
426 | */ | |
f160c7b7 JS |
427 | if (spte_can_locklessly_be_made_writable(spte) || |
428 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
429 | return true; |
430 | ||
ac8d57e5 | 431 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
432 | if ((spte & shadow_accessed_mask) == 0 || |
433 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
434 | return true; | |
435 | } | |
8672b721 | 436 | |
f160c7b7 | 437 | return false; |
8672b721 XG |
438 | } |
439 | ||
1df9f2dc XG |
440 | /* Rules for using mmu_spte_set: |
441 | * Set the sptep from nonpresent to present. | |
442 | * Note: the sptep being assigned *must* be either not present | |
443 | * or in a state where the hardware will not attempt to update | |
444 | * the spte. | |
445 | */ | |
446 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
447 | { | |
448 | WARN_ON(is_shadow_present_pte(*sptep)); | |
449 | __set_spte(sptep, new_spte); | |
450 | } | |
451 | ||
f39a058d JS |
452 | /* |
453 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
454 | * accessed/dirty status. | |
1df9f2dc | 455 | */ |
f39a058d | 456 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 457 | { |
c7ba5b48 | 458 | u64 old_spte = *sptep; |
4132779b | 459 | |
afd28fe1 | 460 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 461 | |
6e7d0354 XG |
462 | if (!is_shadow_present_pte(old_spte)) { |
463 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 464 | return old_spte; |
6e7d0354 | 465 | } |
4132779b | 466 | |
c7ba5b48 | 467 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 468 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 469 | else |
603e0651 | 470 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 471 | |
83ef6c81 JS |
472 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
473 | ||
f39a058d JS |
474 | return old_spte; |
475 | } | |
476 | ||
477 | /* Rules for using mmu_spte_update: | |
478 | * Update the state bits, it means the mapped pfn is not changed. | |
479 | * | |
480 | * Whenever we overwrite a writable spte with a read-only one we | |
481 | * should flush remote TLBs. Otherwise rmap_write_protect | |
482 | * will find a read-only spte, even though the writable spte | |
483 | * might be cached on a CPU's TLB, the return value indicates this | |
484 | * case. | |
485 | * | |
486 | * Returns true if the TLB needs to be flushed | |
487 | */ | |
488 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
489 | { | |
490 | bool flush = false; | |
491 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
492 | ||
493 | if (!is_shadow_present_pte(old_spte)) | |
494 | return false; | |
495 | ||
c7ba5b48 XG |
496 | /* |
497 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 498 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
499 | * spte_has_volatile_bits(). |
500 | */ | |
ea4114bc | 501 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 502 | !is_writable_pte(new_spte)) |
83ef6c81 | 503 | flush = true; |
4132779b | 504 | |
7e71a59b | 505 | /* |
83ef6c81 | 506 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
507 | * to guarantee consistency between TLB and page tables. |
508 | */ | |
7e71a59b | 509 | |
83ef6c81 JS |
510 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
511 | flush = true; | |
4132779b | 512 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
513 | } |
514 | ||
515 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
516 | flush = true; | |
4132779b | 517 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 518 | } |
6e7d0354 | 519 | |
83ef6c81 | 520 | return flush; |
b79b93f9 AK |
521 | } |
522 | ||
1df9f2dc XG |
523 | /* |
524 | * Rules for using mmu_spte_clear_track_bits: | |
525 | * It sets the sptep from present to nonpresent, and track the | |
526 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 527 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
528 | */ |
529 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
530 | { | |
ba049e93 | 531 | kvm_pfn_t pfn; |
1df9f2dc XG |
532 | u64 old_spte = *sptep; |
533 | ||
534 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 535 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 536 | else |
603e0651 | 537 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 538 | |
afd28fe1 | 539 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
540 | return 0; |
541 | ||
542 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
543 | |
544 | /* | |
545 | * KVM does not hold the refcount of the page used by | |
546 | * kvm mmu, before reclaiming the page, we should | |
547 | * unmap it from mmu first. | |
548 | */ | |
bf4bea8e | 549 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 550 | |
83ef6c81 | 551 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 552 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
553 | |
554 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 555 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 556 | |
1df9f2dc XG |
557 | return 1; |
558 | } | |
559 | ||
560 | /* | |
561 | * Rules for using mmu_spte_clear_no_track: | |
562 | * Directly clear spte without caring the state bits of sptep, | |
563 | * it is used to set the upper level spte. | |
564 | */ | |
565 | static void mmu_spte_clear_no_track(u64 *sptep) | |
566 | { | |
603e0651 | 567 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
568 | } |
569 | ||
c2a2ac2b XG |
570 | static u64 mmu_spte_get_lockless(u64 *sptep) |
571 | { | |
572 | return __get_spte_lockless(sptep); | |
573 | } | |
574 | ||
d3e328f2 JS |
575 | /* Restore an acc-track PTE back to a regular PTE */ |
576 | static u64 restore_acc_track_spte(u64 spte) | |
577 | { | |
578 | u64 new_spte = spte; | |
8a967d65 PB |
579 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
580 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 581 | |
ac8d57e5 | 582 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
583 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
584 | ||
585 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
586 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
587 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
588 | new_spte |= saved_bits; |
589 | ||
590 | return new_spte; | |
591 | } | |
592 | ||
f160c7b7 JS |
593 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
594 | static bool mmu_spte_age(u64 *sptep) | |
595 | { | |
596 | u64 spte = mmu_spte_get_lockless(sptep); | |
597 | ||
598 | if (!is_accessed_spte(spte)) | |
599 | return false; | |
600 | ||
ac8d57e5 | 601 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
602 | clear_bit((ffs(shadow_accessed_mask) - 1), |
603 | (unsigned long *)sptep); | |
604 | } else { | |
605 | /* | |
606 | * Capture the dirty status of the page, so that it doesn't get | |
607 | * lost when the SPTE is marked for access tracking. | |
608 | */ | |
609 | if (is_writable_pte(spte)) | |
610 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
611 | ||
612 | spte = mark_spte_for_access_track(spte); | |
613 | mmu_spte_update_no_track(sptep, spte); | |
614 | } | |
615 | ||
616 | return true; | |
617 | } | |
618 | ||
c2a2ac2b XG |
619 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
620 | { | |
c142786c AK |
621 | /* |
622 | * Prevent page table teardown by making any free-er wait during | |
623 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
624 | */ | |
625 | local_irq_disable(); | |
36ca7e0a | 626 | |
c142786c AK |
627 | /* |
628 | * Make sure a following spte read is not reordered ahead of the write | |
629 | * to vcpu->mode. | |
630 | */ | |
36ca7e0a | 631 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
632 | } |
633 | ||
634 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
635 | { | |
c142786c AK |
636 | /* |
637 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 638 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
639 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
640 | */ | |
36ca7e0a | 641 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 642 | local_irq_enable(); |
c2a2ac2b XG |
643 | } |
644 | ||
378f5cd6 | 645 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 646 | { |
e2dec939 AK |
647 | int r; |
648 | ||
531281ad | 649 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
650 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
651 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 652 | if (r) |
284aa868 | 653 | return r; |
94ce87ef SC |
654 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
655 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 656 | if (r) |
171a90d7 | 657 | return r; |
378f5cd6 | 658 | if (maybe_indirect) { |
94ce87ef SC |
659 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
660 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
661 | if (r) |
662 | return r; | |
663 | } | |
94ce87ef SC |
664 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
665 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
666 | } |
667 | ||
668 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
669 | { | |
94ce87ef SC |
670 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
671 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
672 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
673 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
674 | } |
675 | ||
53c07b18 | 676 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 677 | { |
94ce87ef | 678 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
679 | } |
680 | ||
53c07b18 | 681 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 682 | { |
53c07b18 | 683 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
684 | } |
685 | ||
2032a93d LJ |
686 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
687 | { | |
688 | if (!sp->role.direct) | |
689 | return sp->gfns[index]; | |
690 | ||
691 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
692 | } | |
693 | ||
694 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
695 | { | |
e9f2a760 | 696 | if (!sp->role.direct) { |
2032a93d | 697 | sp->gfns[index] = gfn; |
e9f2a760 PB |
698 | return; |
699 | } | |
700 | ||
701 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
702 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
703 | "(expected %llx, got %llx)\n", | |
704 | sp->gfn, | |
705 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
706 | } |
707 | ||
05da4558 | 708 | /* |
d4dbf470 TY |
709 | * Return the pointer to the large page information for a given gfn, |
710 | * handling slots that are not large page aligned. | |
05da4558 | 711 | */ |
d4dbf470 | 712 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
8ca6f063 | 713 | const struct kvm_memory_slot *slot, int level) |
05da4558 MT |
714 | { |
715 | unsigned long idx; | |
716 | ||
fb03cb6f | 717 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 718 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
719 | } |
720 | ||
547ffaed XG |
721 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
722 | gfn_t gfn, int count) | |
723 | { | |
724 | struct kvm_lpage_info *linfo; | |
725 | int i; | |
726 | ||
3bae0459 | 727 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
728 | linfo = lpage_info_slot(gfn, slot, i); |
729 | linfo->disallow_lpage += count; | |
730 | WARN_ON(linfo->disallow_lpage < 0); | |
731 | } | |
732 | } | |
733 | ||
734 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
735 | { | |
736 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
737 | } | |
738 | ||
739 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
740 | { | |
741 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
742 | } | |
743 | ||
3ed1a478 | 744 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 745 | { |
699023e2 | 746 | struct kvm_memslots *slots; |
d25797b2 | 747 | struct kvm_memory_slot *slot; |
3ed1a478 | 748 | gfn_t gfn; |
05da4558 | 749 | |
56ca57f9 | 750 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 751 | gfn = sp->gfn; |
699023e2 PB |
752 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
753 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
754 | |
755 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 756 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
757 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
758 | KVM_PAGE_TRACK_WRITE); | |
759 | ||
547ffaed | 760 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
761 | } |
762 | ||
29cf0f50 | 763 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
764 | { |
765 | if (sp->lpage_disallowed) | |
766 | return; | |
767 | ||
768 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
769 | list_add_tail(&sp->lpage_disallowed_link, |
770 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
771 | sp->lpage_disallowed = true; |
772 | } | |
773 | ||
3ed1a478 | 774 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 775 | { |
699023e2 | 776 | struct kvm_memslots *slots; |
d25797b2 | 777 | struct kvm_memory_slot *slot; |
3ed1a478 | 778 | gfn_t gfn; |
05da4558 | 779 | |
56ca57f9 | 780 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 781 | gfn = sp->gfn; |
699023e2 PB |
782 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
783 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 784 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
785 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
786 | KVM_PAGE_TRACK_WRITE); | |
787 | ||
547ffaed | 788 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
789 | } |
790 | ||
29cf0f50 | 791 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
792 | { |
793 | --kvm->stat.nx_lpage_splits; | |
794 | sp->lpage_disallowed = false; | |
1aa9b957 | 795 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
796 | } |
797 | ||
5d163b1c XG |
798 | static struct kvm_memory_slot * |
799 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
800 | bool no_dirty_log) | |
05da4558 MT |
801 | { |
802 | struct kvm_memory_slot *slot; | |
5d163b1c | 803 | |
54bf36aa | 804 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
805 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
806 | return NULL; | |
044c59c4 | 807 | if (no_dirty_log && kvm_slot_dirty_track_enabled(slot)) |
91b0d268 | 808 | return NULL; |
5d163b1c XG |
809 | |
810 | return slot; | |
811 | } | |
812 | ||
290fc38d | 813 | /* |
018aabb5 | 814 | * About rmap_head encoding: |
cd4a4e53 | 815 | * |
018aabb5 TY |
816 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
817 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 818 | * pte_list_desc containing more mappings. |
018aabb5 TY |
819 | */ |
820 | ||
821 | /* | |
822 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 823 | */ |
53c07b18 | 824 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 825 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 826 | { |
53c07b18 | 827 | struct pte_list_desc *desc; |
53a27b39 | 828 | int i, count = 0; |
cd4a4e53 | 829 | |
018aabb5 | 830 | if (!rmap_head->val) { |
805a0f83 | 831 | rmap_printk("%p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
832 | rmap_head->val = (unsigned long)spte; |
833 | } else if (!(rmap_head->val & 1)) { | |
805a0f83 | 834 | rmap_printk("%p %llx 1->many\n", spte, *spte); |
53c07b18 | 835 | desc = mmu_alloc_pte_list_desc(vcpu); |
018aabb5 | 836 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 837 | desc->sptes[1] = spte; |
018aabb5 | 838 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 839 | ++count; |
cd4a4e53 | 840 | } else { |
805a0f83 | 841 | rmap_printk("%p %llx many->many\n", spte, *spte); |
018aabb5 | 842 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
c6c4f961 | 843 | while (desc->sptes[PTE_LIST_EXT-1]) { |
53c07b18 | 844 | count += PTE_LIST_EXT; |
c6c4f961 LR |
845 | |
846 | if (!desc->more) { | |
847 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
848 | desc = desc->more; | |
849 | break; | |
850 | } | |
cd4a4e53 AK |
851 | desc = desc->more; |
852 | } | |
d555c333 | 853 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 854 | ++count; |
d555c333 | 855 | desc->sptes[i] = spte; |
cd4a4e53 | 856 | } |
53a27b39 | 857 | return count; |
cd4a4e53 AK |
858 | } |
859 | ||
53c07b18 | 860 | static void |
018aabb5 TY |
861 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
862 | struct pte_list_desc *desc, int i, | |
863 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
864 | { |
865 | int j; | |
866 | ||
53c07b18 | 867 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 868 | ; |
d555c333 AK |
869 | desc->sptes[i] = desc->sptes[j]; |
870 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
871 | if (j != 0) |
872 | return; | |
873 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 874 | rmap_head->val = 0; |
cd4a4e53 AK |
875 | else |
876 | if (prev_desc) | |
877 | prev_desc->more = desc->more; | |
878 | else | |
018aabb5 | 879 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 880 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
881 | } |
882 | ||
8daf3462 | 883 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 884 | { |
53c07b18 XG |
885 | struct pte_list_desc *desc; |
886 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
887 | int i; |
888 | ||
018aabb5 | 889 | if (!rmap_head->val) { |
8daf3462 | 890 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 891 | BUG(); |
018aabb5 | 892 | } else if (!(rmap_head->val & 1)) { |
805a0f83 | 893 | rmap_printk("%p 1->0\n", spte); |
018aabb5 | 894 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 895 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
896 | BUG(); |
897 | } | |
018aabb5 | 898 | rmap_head->val = 0; |
cd4a4e53 | 899 | } else { |
805a0f83 | 900 | rmap_printk("%p many->many\n", spte); |
018aabb5 | 901 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
902 | prev_desc = NULL; |
903 | while (desc) { | |
018aabb5 | 904 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 905 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
906 | pte_list_desc_remove_entry(rmap_head, |
907 | desc, i, prev_desc); | |
cd4a4e53 AK |
908 | return; |
909 | } | |
018aabb5 | 910 | } |
cd4a4e53 AK |
911 | prev_desc = desc; |
912 | desc = desc->more; | |
913 | } | |
8daf3462 | 914 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
915 | BUG(); |
916 | } | |
917 | } | |
918 | ||
e7912386 WY |
919 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
920 | { | |
921 | mmu_spte_clear_track_bits(sptep); | |
922 | __pte_list_remove(sptep, rmap_head); | |
923 | } | |
924 | ||
018aabb5 TY |
925 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
926 | struct kvm_memory_slot *slot) | |
53c07b18 | 927 | { |
77d11309 | 928 | unsigned long idx; |
53c07b18 | 929 | |
77d11309 | 930 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 931 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
932 | } |
933 | ||
018aabb5 TY |
934 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
935 | struct kvm_mmu_page *sp) | |
9b9b1492 | 936 | { |
699023e2 | 937 | struct kvm_memslots *slots; |
9b9b1492 TY |
938 | struct kvm_memory_slot *slot; |
939 | ||
699023e2 PB |
940 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
941 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 942 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
943 | } |
944 | ||
f759e2b4 XG |
945 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
946 | { | |
356ec69a | 947 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 948 | |
356ec69a | 949 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 950 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
951 | } |
952 | ||
53c07b18 XG |
953 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
954 | { | |
955 | struct kvm_mmu_page *sp; | |
018aabb5 | 956 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 957 | |
57354682 | 958 | sp = sptep_to_sp(spte); |
53c07b18 | 959 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
960 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
961 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
962 | } |
963 | ||
53c07b18 XG |
964 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
965 | { | |
966 | struct kvm_mmu_page *sp; | |
967 | gfn_t gfn; | |
018aabb5 | 968 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 969 | |
57354682 | 970 | sp = sptep_to_sp(spte); |
53c07b18 | 971 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 972 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 973 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
974 | } |
975 | ||
1e3f42f0 TY |
976 | /* |
977 | * Used by the following functions to iterate through the sptes linked by a | |
978 | * rmap. All fields are private and not assumed to be used outside. | |
979 | */ | |
980 | struct rmap_iterator { | |
981 | /* private fields */ | |
982 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
983 | int pos; /* index of the sptep */ | |
984 | }; | |
985 | ||
986 | /* | |
987 | * Iteration must be started by this function. This should also be used after | |
988 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 989 | * information in the iterator may not be valid. |
1e3f42f0 TY |
990 | * |
991 | * Returns sptep if found, NULL otherwise. | |
992 | */ | |
018aabb5 TY |
993 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
994 | struct rmap_iterator *iter) | |
1e3f42f0 | 995 | { |
77fbbbd2 TY |
996 | u64 *sptep; |
997 | ||
018aabb5 | 998 | if (!rmap_head->val) |
1e3f42f0 TY |
999 | return NULL; |
1000 | ||
018aabb5 | 1001 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1002 | iter->desc = NULL; |
77fbbbd2 TY |
1003 | sptep = (u64 *)rmap_head->val; |
1004 | goto out; | |
1e3f42f0 TY |
1005 | } |
1006 | ||
018aabb5 | 1007 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1008 | iter->pos = 0; |
77fbbbd2 TY |
1009 | sptep = iter->desc->sptes[iter->pos]; |
1010 | out: | |
1011 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1012 | return sptep; | |
1e3f42f0 TY |
1013 | } |
1014 | ||
1015 | /* | |
1016 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1017 | * | |
1018 | * Returns sptep if found, NULL otherwise. | |
1019 | */ | |
1020 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1021 | { | |
77fbbbd2 TY |
1022 | u64 *sptep; |
1023 | ||
1e3f42f0 TY |
1024 | if (iter->desc) { |
1025 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1026 | ++iter->pos; |
1027 | sptep = iter->desc->sptes[iter->pos]; | |
1028 | if (sptep) | |
77fbbbd2 | 1029 | goto out; |
1e3f42f0 TY |
1030 | } |
1031 | ||
1032 | iter->desc = iter->desc->more; | |
1033 | ||
1034 | if (iter->desc) { | |
1035 | iter->pos = 0; | |
1036 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1037 | sptep = iter->desc->sptes[iter->pos]; |
1038 | goto out; | |
1e3f42f0 TY |
1039 | } |
1040 | } | |
1041 | ||
1042 | return NULL; | |
77fbbbd2 TY |
1043 | out: |
1044 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1045 | return sptep; | |
1e3f42f0 TY |
1046 | } |
1047 | ||
018aabb5 TY |
1048 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1049 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1050 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1051 | |
c3707958 | 1052 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1053 | { |
1df9f2dc | 1054 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1055 | rmap_remove(kvm, sptep); |
be38d276 AK |
1056 | } |
1057 | ||
8e22f955 XG |
1058 | |
1059 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1060 | { | |
1061 | if (is_large_pte(*sptep)) { | |
57354682 | 1062 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1063 | drop_spte(kvm, sptep); |
1064 | --kvm->stat.lpages; | |
1065 | return true; | |
1066 | } | |
1067 | ||
1068 | return false; | |
1069 | } | |
1070 | ||
1071 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1072 | { | |
c3134ce2 | 1073 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1074 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1075 | |
1076 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1077 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1078 | } | |
8e22f955 XG |
1079 | } |
1080 | ||
1081 | /* | |
49fde340 | 1082 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1083 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1084 | * |
b4619660 | 1085 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1086 | * protection: |
1087 | * - for dirty logging, the spte can be set to writable at anytime if | |
1088 | * its dirty bitmap is properly set. | |
1089 | * - for spte protection, the spte can be writable only after unsync-ing | |
1090 | * shadow page. | |
8e22f955 | 1091 | * |
c126d94f | 1092 | * Return true if tlb need be flushed. |
8e22f955 | 1093 | */ |
c4f138b4 | 1094 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1095 | { |
1096 | u64 spte = *sptep; | |
1097 | ||
49fde340 | 1098 | if (!is_writable_pte(spte) && |
ea4114bc | 1099 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1100 | return false; |
1101 | ||
805a0f83 | 1102 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
d13bc5b5 | 1103 | |
49fde340 | 1104 | if (pt_protect) |
5fc3424f | 1105 | spte &= ~shadow_mmu_writable_mask; |
d13bc5b5 | 1106 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1107 | |
c126d94f | 1108 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1109 | } |
1110 | ||
018aabb5 TY |
1111 | static bool __rmap_write_protect(struct kvm *kvm, |
1112 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1113 | bool pt_protect) |
98348e95 | 1114 | { |
1e3f42f0 TY |
1115 | u64 *sptep; |
1116 | struct rmap_iterator iter; | |
d13bc5b5 | 1117 | bool flush = false; |
374cbac0 | 1118 | |
018aabb5 | 1119 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1120 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1121 | |
d13bc5b5 | 1122 | return flush; |
a0ed4607 TY |
1123 | } |
1124 | ||
c4f138b4 | 1125 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1126 | { |
1127 | u64 spte = *sptep; | |
1128 | ||
805a0f83 | 1129 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
f4b4b180 | 1130 | |
1f4e5fc8 | 1131 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1132 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1133 | return mmu_spte_update(sptep, spte); |
1134 | } | |
1135 | ||
1f4e5fc8 | 1136 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1137 | { |
1138 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1139 | (unsigned long *)sptep); | |
1f4e5fc8 | 1140 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1141 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1142 | ||
1143 | return was_writable; | |
1144 | } | |
1145 | ||
1146 | /* | |
1147 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1148 | * - D bit on ad-enabled SPTEs, and | |
1149 | * - W bit on ad-disabled SPTEs. | |
1150 | * Returns true iff any D or W bits were cleared. | |
1151 | */ | |
0a234f5d SC |
1152 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1153 | struct kvm_memory_slot *slot) | |
f4b4b180 KH |
1154 | { |
1155 | u64 *sptep; | |
1156 | struct rmap_iterator iter; | |
1157 | bool flush = false; | |
1158 | ||
018aabb5 | 1159 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1160 | if (spte_ad_need_write_protect(*sptep)) |
1161 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1162 | else |
1f4e5fc8 | 1163 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1164 | |
1165 | return flush; | |
1166 | } | |
1167 | ||
5dc99b23 | 1168 | /** |
3b0f1d01 | 1169 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1170 | * @kvm: kvm instance |
1171 | * @slot: slot to protect | |
1172 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1173 | * @mask: indicates which pages we should protect | |
1174 | * | |
89212919 | 1175 | * Used when we do not need to care about huge page mappings. |
5dc99b23 | 1176 | */ |
3b0f1d01 | 1177 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1178 | struct kvm_memory_slot *slot, |
1179 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1180 | { |
018aabb5 | 1181 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1182 | |
897218ff | 1183 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1184 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1185 | slot->base_gfn + gfn_offset, mask, true); | |
e2209710 BG |
1186 | |
1187 | if (!kvm_memslots_have_rmaps(kvm)) | |
1188 | return; | |
1189 | ||
5dc99b23 | 1190 | while (mask) { |
018aabb5 | 1191 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1192 | PG_LEVEL_4K, slot); |
018aabb5 | 1193 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1194 | |
5dc99b23 TY |
1195 | /* clear the first set bit */ |
1196 | mask &= mask - 1; | |
1197 | } | |
374cbac0 AK |
1198 | } |
1199 | ||
f4b4b180 | 1200 | /** |
ac8d57e5 PF |
1201 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1202 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1203 | * @kvm: kvm instance |
1204 | * @slot: slot to clear D-bit | |
1205 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1206 | * @mask: indicates which pages we should clear D-bit | |
1207 | * | |
1208 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1209 | */ | |
a018eba5 SC |
1210 | static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, |
1211 | struct kvm_memory_slot *slot, | |
1212 | gfn_t gfn_offset, unsigned long mask) | |
f4b4b180 | 1213 | { |
018aabb5 | 1214 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1215 | |
897218ff | 1216 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1217 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1218 | slot->base_gfn + gfn_offset, mask, false); | |
e2209710 BG |
1219 | |
1220 | if (!kvm_memslots_have_rmaps(kvm)) | |
1221 | return; | |
1222 | ||
f4b4b180 | 1223 | while (mask) { |
018aabb5 | 1224 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1225 | PG_LEVEL_4K, slot); |
0a234f5d | 1226 | __rmap_clear_dirty(kvm, rmap_head, slot); |
f4b4b180 KH |
1227 | |
1228 | /* clear the first set bit */ | |
1229 | mask &= mask - 1; | |
1230 | } | |
1231 | } | |
f4b4b180 | 1232 | |
3b0f1d01 KH |
1233 | /** |
1234 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1235 | * PT level pages. | |
1236 | * | |
1237 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1238 | * enable dirty logging for them. | |
1239 | * | |
89212919 KZ |
1240 | * We need to care about huge page mappings: e.g. during dirty logging we may |
1241 | * have such mappings. | |
3b0f1d01 KH |
1242 | */ |
1243 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1244 | struct kvm_memory_slot *slot, | |
1245 | gfn_t gfn_offset, unsigned long mask) | |
1246 | { | |
89212919 KZ |
1247 | /* |
1248 | * Huge pages are NOT write protected when we start dirty logging in | |
1249 | * initially-all-set mode; must write protect them here so that they | |
1250 | * are split to 4K on the first write. | |
1251 | * | |
1252 | * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn | |
1253 | * of memslot has no such restriction, so the range can cross two large | |
1254 | * pages. | |
1255 | */ | |
1256 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
1257 | gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask); | |
1258 | gfn_t end = slot->base_gfn + gfn_offset + __fls(mask); | |
1259 | ||
1260 | kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M); | |
1261 | ||
1262 | /* Cross two large pages? */ | |
1263 | if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) != | |
1264 | ALIGN(end << PAGE_SHIFT, PMD_SIZE)) | |
1265 | kvm_mmu_slot_gfn_write_protect(kvm, slot, end, | |
1266 | PG_LEVEL_2M); | |
1267 | } | |
1268 | ||
1269 | /* Now handle 4K PTEs. */ | |
a018eba5 SC |
1270 | if (kvm_x86_ops.cpu_dirty_log_size) |
1271 | kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask); | |
88178fd4 KH |
1272 | else |
1273 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1274 | } |
1275 | ||
fb04a1ed PX |
1276 | int kvm_cpu_dirty_log_size(void) |
1277 | { | |
6dd03800 | 1278 | return kvm_x86_ops.cpu_dirty_log_size; |
fb04a1ed PX |
1279 | } |
1280 | ||
aeecee2e | 1281 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
3ad93562 KZ |
1282 | struct kvm_memory_slot *slot, u64 gfn, |
1283 | int min_level) | |
95d4c16c | 1284 | { |
018aabb5 | 1285 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1286 | int i; |
2f84569f | 1287 | bool write_protected = false; |
95d4c16c | 1288 | |
e2209710 BG |
1289 | if (kvm_memslots_have_rmaps(kvm)) { |
1290 | for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { | |
1291 | rmap_head = __gfn_to_rmap(gfn, i, slot); | |
1292 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); | |
1293 | } | |
5dc99b23 TY |
1294 | } |
1295 | ||
897218ff | 1296 | if (is_tdp_mmu_enabled(kvm)) |
46044f72 | 1297 | write_protected |= |
3ad93562 | 1298 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level); |
46044f72 | 1299 | |
5dc99b23 | 1300 | return write_protected; |
95d4c16c TY |
1301 | } |
1302 | ||
aeecee2e XG |
1303 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1304 | { | |
1305 | struct kvm_memory_slot *slot; | |
1306 | ||
1307 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
3ad93562 | 1308 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K); |
aeecee2e XG |
1309 | } |
1310 | ||
0a234f5d SC |
1311 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1312 | struct kvm_memory_slot *slot) | |
e930bffe | 1313 | { |
1e3f42f0 TY |
1314 | u64 *sptep; |
1315 | struct rmap_iterator iter; | |
6a49f85c | 1316 | bool flush = false; |
e930bffe | 1317 | |
018aabb5 | 1318 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
805a0f83 | 1319 | rmap_printk("spte %p %llx.\n", sptep, *sptep); |
1e3f42f0 | 1320 | |
e7912386 | 1321 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1322 | flush = true; |
e930bffe | 1323 | } |
1e3f42f0 | 1324 | |
6a49f85c XG |
1325 | return flush; |
1326 | } | |
1327 | ||
3039bcc7 SC |
1328 | static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1329 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1330 | pte_t unused) | |
6a49f85c | 1331 | { |
0a234f5d | 1332 | return kvm_zap_rmapp(kvm, rmap_head, slot); |
e930bffe AA |
1333 | } |
1334 | ||
3039bcc7 SC |
1335 | static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1336 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1337 | pte_t pte) | |
3da0dd43 | 1338 | { |
1e3f42f0 TY |
1339 | u64 *sptep; |
1340 | struct rmap_iterator iter; | |
3da0dd43 | 1341 | int need_flush = 0; |
1e3f42f0 | 1342 | u64 new_spte; |
ba049e93 | 1343 | kvm_pfn_t new_pfn; |
3da0dd43 | 1344 | |
3039bcc7 SC |
1345 | WARN_ON(pte_huge(pte)); |
1346 | new_pfn = pte_pfn(pte); | |
1e3f42f0 | 1347 | |
0d536790 | 1348 | restart: |
018aabb5 | 1349 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
805a0f83 | 1350 | rmap_printk("spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1351 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1352 | |
3da0dd43 | 1353 | need_flush = 1; |
1e3f42f0 | 1354 | |
3039bcc7 | 1355 | if (pte_write(pte)) { |
e7912386 | 1356 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1357 | goto restart; |
3da0dd43 | 1358 | } else { |
cb3eedab PB |
1359 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1360 | *sptep, new_pfn); | |
1e3f42f0 TY |
1361 | |
1362 | mmu_spte_clear_track_bits(sptep); | |
1363 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1364 | } |
1365 | } | |
1e3f42f0 | 1366 | |
3cc5ea94 LT |
1367 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1368 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1369 | return 0; | |
1370 | } | |
1371 | ||
0cf853c5 | 1372 | return need_flush; |
3da0dd43 IE |
1373 | } |
1374 | ||
6ce1f4e2 XG |
1375 | struct slot_rmap_walk_iterator { |
1376 | /* input fields. */ | |
1377 | struct kvm_memory_slot *slot; | |
1378 | gfn_t start_gfn; | |
1379 | gfn_t end_gfn; | |
1380 | int start_level; | |
1381 | int end_level; | |
1382 | ||
1383 | /* output fields. */ | |
1384 | gfn_t gfn; | |
018aabb5 | 1385 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1386 | int level; |
1387 | ||
1388 | /* private field. */ | |
018aabb5 | 1389 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1390 | }; |
1391 | ||
1392 | static void | |
1393 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1394 | { | |
1395 | iterator->level = level; | |
1396 | iterator->gfn = iterator->start_gfn; | |
1397 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1398 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1399 | iterator->slot); | |
1400 | } | |
1401 | ||
1402 | static void | |
1403 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1404 | struct kvm_memory_slot *slot, int start_level, | |
1405 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1406 | { | |
1407 | iterator->slot = slot; | |
1408 | iterator->start_level = start_level; | |
1409 | iterator->end_level = end_level; | |
1410 | iterator->start_gfn = start_gfn; | |
1411 | iterator->end_gfn = end_gfn; | |
1412 | ||
1413 | rmap_walk_init_level(iterator, iterator->start_level); | |
1414 | } | |
1415 | ||
1416 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1417 | { | |
1418 | return !!iterator->rmap; | |
1419 | } | |
1420 | ||
1421 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1422 | { | |
1423 | if (++iterator->rmap <= iterator->end_rmap) { | |
1424 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1425 | return; | |
1426 | } | |
1427 | ||
1428 | if (++iterator->level > iterator->end_level) { | |
1429 | iterator->rmap = NULL; | |
1430 | return; | |
1431 | } | |
1432 | ||
1433 | rmap_walk_init_level(iterator, iterator->level); | |
1434 | } | |
1435 | ||
1436 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1437 | _start_gfn, _end_gfn, _iter_) \ | |
1438 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1439 | _end_level_, _start_gfn, _end_gfn); \ | |
1440 | slot_rmap_walk_okay(_iter_); \ | |
1441 | slot_rmap_walk_next(_iter_)) | |
1442 | ||
3039bcc7 SC |
1443 | typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1444 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1445 | int level, pte_t pte); | |
c1b91493 | 1446 | |
3039bcc7 SC |
1447 | static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm, |
1448 | struct kvm_gfn_range *range, | |
1449 | rmap_handler_t handler) | |
e930bffe | 1450 | { |
6ce1f4e2 | 1451 | struct slot_rmap_walk_iterator iterator; |
3039bcc7 | 1452 | bool ret = false; |
e930bffe | 1453 | |
3039bcc7 SC |
1454 | for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL, |
1455 | range->start, range->end - 1, &iterator) | |
1456 | ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn, | |
1457 | iterator.level, range->pte); | |
e930bffe | 1458 | |
f395302e | 1459 | return ret; |
e930bffe AA |
1460 | } |
1461 | ||
3039bcc7 | 1462 | bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) |
84504ef3 | 1463 | { |
e2209710 | 1464 | bool flush = false; |
063afacd | 1465 | |
e2209710 BG |
1466 | if (kvm_memslots_have_rmaps(kvm)) |
1467 | flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp); | |
063afacd | 1468 | |
897218ff | 1469 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1470 | flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush); |
063afacd | 1471 | |
3039bcc7 | 1472 | return flush; |
b3ae2096 TY |
1473 | } |
1474 | ||
3039bcc7 | 1475 | bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
3da0dd43 | 1476 | { |
e2209710 | 1477 | bool flush = false; |
1d8dd6b3 | 1478 | |
e2209710 BG |
1479 | if (kvm_memslots_have_rmaps(kvm)) |
1480 | flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp); | |
1d8dd6b3 | 1481 | |
897218ff | 1482 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1483 | flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range); |
1d8dd6b3 | 1484 | |
3039bcc7 | 1485 | return flush; |
e930bffe AA |
1486 | } |
1487 | ||
3039bcc7 SC |
1488 | static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1489 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1490 | pte_t unused) | |
e930bffe | 1491 | { |
1e3f42f0 | 1492 | u64 *sptep; |
3f649ab7 | 1493 | struct rmap_iterator iter; |
e930bffe AA |
1494 | int young = 0; |
1495 | ||
f160c7b7 JS |
1496 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1497 | young |= mmu_spte_age(sptep); | |
0d536790 | 1498 | |
e930bffe AA |
1499 | return young; |
1500 | } | |
1501 | ||
3039bcc7 SC |
1502 | static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1503 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1504 | int level, pte_t unused) | |
8ee53820 | 1505 | { |
1e3f42f0 TY |
1506 | u64 *sptep; |
1507 | struct rmap_iterator iter; | |
8ee53820 | 1508 | |
83ef6c81 JS |
1509 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1510 | if (is_accessed_spte(*sptep)) | |
1511 | return 1; | |
83ef6c81 | 1512 | return 0; |
8ee53820 AA |
1513 | } |
1514 | ||
53a27b39 MT |
1515 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1516 | ||
852e3c19 | 1517 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1518 | { |
018aabb5 | 1519 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1520 | struct kvm_mmu_page *sp; |
1521 | ||
57354682 | 1522 | sp = sptep_to_sp(spte); |
53a27b39 | 1523 | |
018aabb5 | 1524 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1525 | |
3039bcc7 | 1526 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0)); |
c3134ce2 LT |
1527 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1528 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1529 | } |
1530 | ||
3039bcc7 | 1531 | bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
e930bffe | 1532 | { |
e2209710 | 1533 | bool young = false; |
3039bcc7 | 1534 | |
e2209710 BG |
1535 | if (kvm_memslots_have_rmaps(kvm)) |
1536 | young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp); | |
f8e14497 | 1537 | |
897218ff | 1538 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1539 | young |= kvm_tdp_mmu_age_gfn_range(kvm, range); |
f8e14497 BG |
1540 | |
1541 | return young; | |
e930bffe AA |
1542 | } |
1543 | ||
3039bcc7 | 1544 | bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
8ee53820 | 1545 | { |
e2209710 | 1546 | bool young = false; |
3039bcc7 | 1547 | |
e2209710 BG |
1548 | if (kvm_memslots_have_rmaps(kvm)) |
1549 | young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp); | |
f8e14497 | 1550 | |
897218ff | 1551 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1552 | young |= kvm_tdp_mmu_test_age_gfn(kvm, range); |
f8e14497 BG |
1553 | |
1554 | return young; | |
8ee53820 AA |
1555 | } |
1556 | ||
d6c69ee9 | 1557 | #ifdef MMU_DEBUG |
47ad8e68 | 1558 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1559 | { |
139bdb2d AK |
1560 | u64 *pos; |
1561 | u64 *end; | |
1562 | ||
47ad8e68 | 1563 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1564 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1565 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1566 | pos, *pos); |
6aa8b732 | 1567 | return 0; |
139bdb2d | 1568 | } |
6aa8b732 AK |
1569 | return 1; |
1570 | } | |
d6c69ee9 | 1571 | #endif |
6aa8b732 | 1572 | |
45221ab6 DH |
1573 | /* |
1574 | * This value is the sum of all of the kvm instances's | |
1575 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1576 | * aggregate version in order to make the slab shrinker | |
1577 | * faster | |
1578 | */ | |
bc8a3d89 | 1579 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1580 | { |
1581 | kvm->arch.n_used_mmu_pages += nr; | |
1582 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1583 | } | |
1584 | ||
834be0d8 | 1585 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1586 | { |
fa4a2c08 | 1587 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1588 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1589 | list_del(&sp->link); |
1590 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1591 | if (!sp->role.direct) |
1592 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1593 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1594 | } |
1595 | ||
cea0f0e7 AK |
1596 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1597 | { | |
114df303 | 1598 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1599 | } |
1600 | ||
714b93da | 1601 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1602 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1603 | { |
cea0f0e7 AK |
1604 | if (!parent_pte) |
1605 | return; | |
cea0f0e7 | 1606 | |
67052b35 | 1607 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1608 | } |
1609 | ||
4db35314 | 1610 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1611 | u64 *parent_pte) |
1612 | { | |
8daf3462 | 1613 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1614 | } |
1615 | ||
bcdd9a93 XG |
1616 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1617 | u64 *parent_pte) | |
1618 | { | |
1619 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1620 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1621 | } |
1622 | ||
47005792 | 1623 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1624 | { |
67052b35 | 1625 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1626 | |
94ce87ef SC |
1627 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1628 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1629 | if (!direct) |
94ce87ef | 1630 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1631 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1632 | |
1633 | /* | |
1634 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1635 | * depends on valid pages being added to the head of the list. See | |
1636 | * comments in kvm_zap_obsolete_pages(). | |
1637 | */ | |
ca333add | 1638 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1639 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1640 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1641 | return sp; | |
ad8cfbe3 MT |
1642 | } |
1643 | ||
67052b35 | 1644 | static void mark_unsync(u64 *spte); |
1047df1f | 1645 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1646 | { |
74c4e63a TY |
1647 | u64 *sptep; |
1648 | struct rmap_iterator iter; | |
1649 | ||
1650 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1651 | mark_unsync(sptep); | |
1652 | } | |
0074ff63 MT |
1653 | } |
1654 | ||
67052b35 | 1655 | static void mark_unsync(u64 *spte) |
0074ff63 | 1656 | { |
67052b35 | 1657 | struct kvm_mmu_page *sp; |
1047df1f | 1658 | unsigned int index; |
0074ff63 | 1659 | |
57354682 | 1660 | sp = sptep_to_sp(spte); |
1047df1f XG |
1661 | index = spte - sp->spt; |
1662 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1663 | return; |
1047df1f | 1664 | if (sp->unsync_children++) |
0074ff63 | 1665 | return; |
1047df1f | 1666 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1667 | } |
1668 | ||
e8bc217a | 1669 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1670 | struct kvm_mmu_page *sp) |
e8bc217a | 1671 | { |
1f50f1b3 | 1672 | return 0; |
e8bc217a MT |
1673 | } |
1674 | ||
60c8aec6 MT |
1675 | #define KVM_PAGE_ARRAY_NR 16 |
1676 | ||
1677 | struct kvm_mmu_pages { | |
1678 | struct mmu_page_and_offset { | |
1679 | struct kvm_mmu_page *sp; | |
1680 | unsigned int idx; | |
1681 | } page[KVM_PAGE_ARRAY_NR]; | |
1682 | unsigned int nr; | |
1683 | }; | |
1684 | ||
cded19f3 HE |
1685 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1686 | int idx) | |
4731d4c7 | 1687 | { |
60c8aec6 | 1688 | int i; |
4731d4c7 | 1689 | |
60c8aec6 MT |
1690 | if (sp->unsync) |
1691 | for (i=0; i < pvec->nr; i++) | |
1692 | if (pvec->page[i].sp == sp) | |
1693 | return 0; | |
1694 | ||
1695 | pvec->page[pvec->nr].sp = sp; | |
1696 | pvec->page[pvec->nr].idx = idx; | |
1697 | pvec->nr++; | |
1698 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1699 | } | |
1700 | ||
fd951457 TY |
1701 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1702 | { | |
1703 | --sp->unsync_children; | |
1704 | WARN_ON((int)sp->unsync_children < 0); | |
1705 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1706 | } | |
1707 | ||
60c8aec6 MT |
1708 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1709 | struct kvm_mmu_pages *pvec) | |
1710 | { | |
1711 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1712 | |
37178b8b | 1713 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1714 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1715 | u64 ent = sp->spt[i]; |
1716 | ||
fd951457 TY |
1717 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1718 | clear_unsync_child_bit(sp, i); | |
1719 | continue; | |
1720 | } | |
7a8f1a74 | 1721 | |
e47c4aee | 1722 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1723 | |
1724 | if (child->unsync_children) { | |
1725 | if (mmu_pages_add(pvec, child, i)) | |
1726 | return -ENOSPC; | |
1727 | ||
1728 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1729 | if (!ret) { |
1730 | clear_unsync_child_bit(sp, i); | |
1731 | continue; | |
1732 | } else if (ret > 0) { | |
7a8f1a74 | 1733 | nr_unsync_leaf += ret; |
fd951457 | 1734 | } else |
7a8f1a74 XG |
1735 | return ret; |
1736 | } else if (child->unsync) { | |
1737 | nr_unsync_leaf++; | |
1738 | if (mmu_pages_add(pvec, child, i)) | |
1739 | return -ENOSPC; | |
1740 | } else | |
fd951457 | 1741 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1742 | } |
1743 | ||
60c8aec6 MT |
1744 | return nr_unsync_leaf; |
1745 | } | |
1746 | ||
e23d3fef XG |
1747 | #define INVALID_INDEX (-1) |
1748 | ||
60c8aec6 MT |
1749 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1750 | struct kvm_mmu_pages *pvec) | |
1751 | { | |
0a47cd85 | 1752 | pvec->nr = 0; |
60c8aec6 MT |
1753 | if (!sp->unsync_children) |
1754 | return 0; | |
1755 | ||
e23d3fef | 1756 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1757 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1758 | } |
1759 | ||
4731d4c7 MT |
1760 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1761 | { | |
1762 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1763 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1764 | sp->unsync = 0; |
1765 | --kvm->stat.mmu_unsync; | |
1766 | } | |
1767 | ||
83cdb568 SC |
1768 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1769 | struct list_head *invalid_list); | |
7775834a XG |
1770 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1771 | struct list_head *invalid_list); | |
4731d4c7 | 1772 | |
ac101b7c SC |
1773 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1774 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1775 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1776 | } else |
1044b030 TY |
1777 | |
1778 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1779 | for_each_valid_sp(_kvm, _sp, \ |
1780 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1781 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1782 | |
f918b443 | 1783 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
1784 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1785 | struct list_head *invalid_list) | |
4731d4c7 | 1786 | { |
2640b086 | 1787 | if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 1788 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1789 | return false; |
4731d4c7 MT |
1790 | } |
1791 | ||
1f50f1b3 | 1792 | return true; |
4731d4c7 MT |
1793 | } |
1794 | ||
a2113634 SC |
1795 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1796 | struct list_head *invalid_list, | |
1797 | bool remote_flush) | |
1798 | { | |
cfd32acf | 1799 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1800 | return false; |
1801 | ||
1802 | if (!list_empty(invalid_list)) | |
1803 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1804 | else | |
1805 | kvm_flush_remote_tlbs(kvm); | |
1806 | return true; | |
1807 | } | |
1808 | ||
35a70510 PB |
1809 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1810 | struct list_head *invalid_list, | |
1811 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1812 | { |
a2113634 | 1813 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1814 | return; |
d98ba053 | 1815 | |
a2113634 | 1816 | if (local_flush) |
8c8560b8 | 1817 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1818 | } |
1819 | ||
e37fa785 XG |
1820 | #ifdef CONFIG_KVM_MMU_AUDIT |
1821 | #include "mmu_audit.c" | |
1822 | #else | |
1823 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1824 | static void mmu_audit_disable(void) { } | |
1825 | #endif | |
1826 | ||
002c5f73 SC |
1827 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1828 | { | |
fac026da SC |
1829 | return sp->role.invalid || |
1830 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1831 | } |
1832 | ||
1f50f1b3 | 1833 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1834 | struct list_head *invalid_list) |
1d9dc7e0 | 1835 | { |
9a43c5d9 PB |
1836 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1837 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
1838 | } |
1839 | ||
60c8aec6 | 1840 | struct mmu_page_path { |
2a7266a8 YZ |
1841 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1842 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1843 | }; |
1844 | ||
60c8aec6 | 1845 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1846 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1847 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1848 | i = mmu_pages_next(&pvec, &parents, i)) | |
1849 | ||
cded19f3 HE |
1850 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1851 | struct mmu_page_path *parents, | |
1852 | int i) | |
60c8aec6 MT |
1853 | { |
1854 | int n; | |
1855 | ||
1856 | for (n = i+1; n < pvec->nr; n++) { | |
1857 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1858 | unsigned idx = pvec->page[n].idx; |
1859 | int level = sp->role.level; | |
60c8aec6 | 1860 | |
0a47cd85 | 1861 | parents->idx[level-1] = idx; |
3bae0459 | 1862 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1863 | break; |
60c8aec6 | 1864 | |
0a47cd85 | 1865 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1866 | } |
1867 | ||
1868 | return n; | |
1869 | } | |
1870 | ||
0a47cd85 PB |
1871 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1872 | struct mmu_page_path *parents) | |
1873 | { | |
1874 | struct kvm_mmu_page *sp; | |
1875 | int level; | |
1876 | ||
1877 | if (pvec->nr == 0) | |
1878 | return 0; | |
1879 | ||
e23d3fef XG |
1880 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1881 | ||
0a47cd85 PB |
1882 | sp = pvec->page[0].sp; |
1883 | level = sp->role.level; | |
3bae0459 | 1884 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1885 | |
1886 | parents->parent[level-2] = sp; | |
1887 | ||
1888 | /* Also set up a sentinel. Further entries in pvec are all | |
1889 | * children of sp, so this element is never overwritten. | |
1890 | */ | |
1891 | parents->parent[level-1] = NULL; | |
1892 | return mmu_pages_next(pvec, parents, 0); | |
1893 | } | |
1894 | ||
cded19f3 | 1895 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1896 | { |
60c8aec6 MT |
1897 | struct kvm_mmu_page *sp; |
1898 | unsigned int level = 0; | |
1899 | ||
1900 | do { | |
1901 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1902 | sp = parents->parent[level]; |
1903 | if (!sp) | |
1904 | return; | |
1905 | ||
e23d3fef | 1906 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1907 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1908 | level++; |
0a47cd85 | 1909 | } while (!sp->unsync_children); |
60c8aec6 | 1910 | } |
4731d4c7 | 1911 | |
60c8aec6 MT |
1912 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1913 | struct kvm_mmu_page *parent) | |
1914 | { | |
1915 | int i; | |
1916 | struct kvm_mmu_page *sp; | |
1917 | struct mmu_page_path parents; | |
1918 | struct kvm_mmu_pages pages; | |
d98ba053 | 1919 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1920 | bool flush = false; |
60c8aec6 | 1921 | |
60c8aec6 | 1922 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1923 | bool protected = false; |
b1a36821 MT |
1924 | |
1925 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1926 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1927 | |
50c9e6f3 | 1928 | if (protected) { |
b1a36821 | 1929 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
1930 | flush = false; |
1931 | } | |
b1a36821 | 1932 | |
60c8aec6 | 1933 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 1934 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1935 | mmu_pages_clear_parents(&parents); |
1936 | } | |
531810ca | 1937 | if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) { |
50c9e6f3 | 1938 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); |
531810ca | 1939 | cond_resched_rwlock_write(&vcpu->kvm->mmu_lock); |
50c9e6f3 PB |
1940 | flush = false; |
1941 | } | |
60c8aec6 | 1942 | } |
50c9e6f3 PB |
1943 | |
1944 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
1945 | } |
1946 | ||
a30f47cb XG |
1947 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1948 | { | |
e5691a81 | 1949 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
1950 | } |
1951 | ||
1952 | static void clear_sp_write_flooding_count(u64 *spte) | |
1953 | { | |
57354682 | 1954 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
1955 | } |
1956 | ||
cea0f0e7 AK |
1957 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1958 | gfn_t gfn, | |
1959 | gva_t gaddr, | |
1960 | unsigned level, | |
f6e2c02b | 1961 | int direct, |
0a2b64c5 | 1962 | unsigned int access) |
cea0f0e7 | 1963 | { |
fb58a9c3 | 1964 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 1965 | union kvm_mmu_page_role role; |
ac101b7c | 1966 | struct hlist_head *sp_list; |
cea0f0e7 | 1967 | unsigned quadrant; |
9f1a122f | 1968 | struct kvm_mmu_page *sp; |
f3414bc7 | 1969 | int collisions = 0; |
2a74003a | 1970 | LIST_HEAD(invalid_list); |
cea0f0e7 | 1971 | |
36d9594d | 1972 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 1973 | role.level = level; |
f6e2c02b | 1974 | role.direct = direct; |
84b0c8c6 | 1975 | if (role.direct) |
47c42e6b | 1976 | role.gpte_is_8_bytes = true; |
41074d07 | 1977 | role.access = access; |
fb58a9c3 | 1978 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1979 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1980 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1981 | role.quadrant = quadrant; | |
1982 | } | |
ac101b7c SC |
1983 | |
1984 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
1985 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
1986 | if (sp->gfn != gfn) { |
1987 | collisions++; | |
1988 | continue; | |
1989 | } | |
1990 | ||
ddc16abb SC |
1991 | if (sp->role.word != role.word) { |
1992 | /* | |
1993 | * If the guest is creating an upper-level page, zap | |
1994 | * unsync pages for the same gfn. While it's possible | |
1995 | * the guest is using recursive page tables, in all | |
1996 | * likelihood the guest has stopped using the unsync | |
1997 | * page and is installing a completely unrelated page. | |
1998 | * Unsync pages must not be left as is, because the new | |
1999 | * upper-level page will be write-protected. | |
2000 | */ | |
2001 | if (level > PG_LEVEL_4K && sp->unsync) | |
2002 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, | |
2003 | &invalid_list); | |
7ae680eb | 2004 | continue; |
ddc16abb | 2005 | } |
4731d4c7 | 2006 | |
fb58a9c3 SC |
2007 | if (direct_mmu) |
2008 | goto trace_get_page; | |
2009 | ||
2a74003a PB |
2010 | if (sp->unsync) { |
2011 | /* The page is good, but __kvm_sync_page might still end | |
2012 | * up zapping it. If so, break in order to rebuild it. | |
2013 | */ | |
2014 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2015 | break; | |
2016 | ||
2017 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2018 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2019 | } |
e02aa901 | 2020 | |
98bba238 | 2021 | if (sp->unsync_children) |
f6f6195b | 2022 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2023 | |
a30f47cb | 2024 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2025 | |
2026 | trace_get_page: | |
7ae680eb | 2027 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2028 | goto out; |
7ae680eb | 2029 | } |
47005792 | 2030 | |
dfc5aa00 | 2031 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2032 | |
2033 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2034 | ||
4db35314 AK |
2035 | sp->gfn = gfn; |
2036 | sp->role = role; | |
ac101b7c | 2037 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2038 | if (!direct) { |
56ca57f9 | 2039 | account_shadowed(vcpu->kvm, sp); |
3bae0459 | 2040 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2041 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
4731d4c7 | 2042 | } |
f691fe1d | 2043 | trace_kvm_mmu_get_page(sp, true); |
f3414bc7 | 2044 | out: |
ddc16abb SC |
2045 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
2046 | ||
f3414bc7 DM |
2047 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) |
2048 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2049 | return sp; |
cea0f0e7 AK |
2050 | } |
2051 | ||
7eb77e9f JS |
2052 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2053 | struct kvm_vcpu *vcpu, hpa_t root, | |
2054 | u64 addr) | |
2d11123a AK |
2055 | { |
2056 | iterator->addr = addr; | |
7eb77e9f | 2057 | iterator->shadow_addr = root; |
44dd3ffa | 2058 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2059 | |
2a7266a8 | 2060 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2061 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2062 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2063 | --iterator->level; |
2064 | ||
2d11123a | 2065 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2066 | /* |
2067 | * prev_root is currently only used for 64-bit hosts. So only | |
2068 | * the active root_hpa is valid here. | |
2069 | */ | |
44dd3ffa | 2070 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2071 | |
2d11123a | 2072 | iterator->shadow_addr |
44dd3ffa | 2073 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2074 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2075 | --iterator->level; | |
2076 | if (!iterator->shadow_addr) | |
2077 | iterator->level = 0; | |
2078 | } | |
2079 | } | |
2080 | ||
7eb77e9f JS |
2081 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2082 | struct kvm_vcpu *vcpu, u64 addr) | |
2083 | { | |
44dd3ffa | 2084 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2085 | addr); |
2086 | } | |
2087 | ||
2d11123a AK |
2088 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2089 | { | |
3bae0459 | 2090 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2091 | return false; |
4d88954d | 2092 | |
2d11123a AK |
2093 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2094 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2095 | return true; | |
2096 | } | |
2097 | ||
c2a2ac2b XG |
2098 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2099 | u64 spte) | |
2d11123a | 2100 | { |
c2a2ac2b | 2101 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2102 | iterator->level = 0; |
2103 | return; | |
2104 | } | |
2105 | ||
c2a2ac2b | 2106 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2107 | --iterator->level; |
2108 | } | |
2109 | ||
c2a2ac2b XG |
2110 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2111 | { | |
bb606a9b | 2112 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2113 | } |
2114 | ||
cc4674d0 BG |
2115 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2116 | struct kvm_mmu_page *sp) | |
2117 | { | |
2118 | u64 spte; | |
2119 | ||
2120 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2121 | ||
2122 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2123 | ||
1df9f2dc | 2124 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2125 | |
2126 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2127 | ||
2128 | if (sp->unsync_children || sp->unsync) | |
2129 | mark_unsync(sptep); | |
32ef26a3 AK |
2130 | } |
2131 | ||
a357bd22 AK |
2132 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2133 | unsigned direct_access) | |
2134 | { | |
2135 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2136 | struct kvm_mmu_page *child; | |
2137 | ||
2138 | /* | |
2139 | * For the direct sp, if the guest pte's dirty bit | |
2140 | * changed form clean to dirty, it will corrupt the | |
2141 | * sp's access: allow writable in the read-only sp, | |
2142 | * so we should update the spte at this point to get | |
2143 | * a new sp with the correct access. | |
2144 | */ | |
e47c4aee | 2145 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2146 | if (child->role.access == direct_access) |
2147 | return; | |
2148 | ||
bcdd9a93 | 2149 | drop_parent_pte(child, sptep); |
c3134ce2 | 2150 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2151 | } |
2152 | } | |
2153 | ||
2de4085c BG |
2154 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2155 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2156 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2157 | { |
2158 | u64 pte; | |
2159 | struct kvm_mmu_page *child; | |
2160 | ||
2161 | pte = *spte; | |
2162 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2163 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2164 | drop_spte(kvm, spte); |
505aef8f XG |
2165 | if (is_large_pte(pte)) |
2166 | --kvm->stat.lpages; | |
2167 | } else { | |
e47c4aee | 2168 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2169 | drop_parent_pte(child, spte); |
2de4085c BG |
2170 | |
2171 | /* | |
2172 | * Recursively zap nested TDP SPs, parentless SPs are | |
2173 | * unlikely to be used again in the near future. This | |
2174 | * avoids retaining a large number of stale nested SPs. | |
2175 | */ | |
2176 | if (tdp_enabled && invalid_list && | |
2177 | child->role.guest_mode && !child->parent_ptes.val) | |
2178 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2179 | invalid_list); | |
38e3b2b2 | 2180 | } |
ace569e0 | 2181 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2182 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2183 | } |
2de4085c | 2184 | return 0; |
38e3b2b2 XG |
2185 | } |
2186 | ||
2de4085c BG |
2187 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2188 | struct kvm_mmu_page *sp, | |
2189 | struct list_head *invalid_list) | |
a436036b | 2190 | { |
2de4085c | 2191 | int zapped = 0; |
697fe2e2 | 2192 | unsigned i; |
697fe2e2 | 2193 | |
38e3b2b2 | 2194 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2195 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2196 | ||
2197 | return zapped; | |
a436036b AK |
2198 | } |
2199 | ||
31aa2b44 | 2200 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2201 | { |
1e3f42f0 TY |
2202 | u64 *sptep; |
2203 | struct rmap_iterator iter; | |
a436036b | 2204 | |
018aabb5 | 2205 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2206 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2207 | } |
2208 | ||
60c8aec6 | 2209 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2210 | struct kvm_mmu_page *parent, |
2211 | struct list_head *invalid_list) | |
4731d4c7 | 2212 | { |
60c8aec6 MT |
2213 | int i, zapped = 0; |
2214 | struct mmu_page_path parents; | |
2215 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2216 | |
3bae0459 | 2217 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2218 | return 0; |
60c8aec6 | 2219 | |
60c8aec6 MT |
2220 | while (mmu_unsync_walk(parent, &pages)) { |
2221 | struct kvm_mmu_page *sp; | |
2222 | ||
2223 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2224 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2225 | mmu_pages_clear_parents(&parents); |
77662e00 | 2226 | zapped++; |
60c8aec6 | 2227 | } |
60c8aec6 MT |
2228 | } |
2229 | ||
2230 | return zapped; | |
4731d4c7 MT |
2231 | } |
2232 | ||
83cdb568 SC |
2233 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2234 | struct kvm_mmu_page *sp, | |
2235 | struct list_head *invalid_list, | |
2236 | int *nr_zapped) | |
31aa2b44 | 2237 | { |
83cdb568 | 2238 | bool list_unstable; |
f691fe1d | 2239 | |
7775834a | 2240 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2241 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2242 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2243 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2244 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2245 | |
83cdb568 SC |
2246 | /* Zapping children means active_mmu_pages has become unstable. */ |
2247 | list_unstable = *nr_zapped; | |
2248 | ||
f6e2c02b | 2249 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2250 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2251 | |
4731d4c7 MT |
2252 | if (sp->unsync) |
2253 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2254 | if (!sp->root_count) { |
54a4f023 | 2255 | /* Count self */ |
83cdb568 | 2256 | (*nr_zapped)++; |
f95eec9b SC |
2257 | |
2258 | /* | |
2259 | * Already invalid pages (previously active roots) are not on | |
2260 | * the active page list. See list_del() in the "else" case of | |
2261 | * !sp->root_count. | |
2262 | */ | |
2263 | if (sp->role.invalid) | |
2264 | list_add(&sp->link, invalid_list); | |
2265 | else | |
2266 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2267 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2268 | } else { |
f95eec9b SC |
2269 | /* |
2270 | * Remove the active root from the active page list, the root | |
2271 | * will be explicitly freed when the root_count hits zero. | |
2272 | */ | |
2273 | list_del(&sp->link); | |
05988d72 | 2274 | |
10605204 SC |
2275 | /* |
2276 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2277 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2278 | * treats invalid shadow pages as being obsolete. | |
2279 | */ | |
2280 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2281 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2282 | } |
7775834a | 2283 | |
b8e8c830 PB |
2284 | if (sp->lpage_disallowed) |
2285 | unaccount_huge_nx_page(kvm, sp); | |
2286 | ||
7775834a | 2287 | sp->role.invalid = 1; |
83cdb568 SC |
2288 | return list_unstable; |
2289 | } | |
2290 | ||
2291 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2292 | struct list_head *invalid_list) | |
2293 | { | |
2294 | int nr_zapped; | |
2295 | ||
2296 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2297 | return nr_zapped; | |
a436036b AK |
2298 | } |
2299 | ||
7775834a XG |
2300 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2301 | struct list_head *invalid_list) | |
2302 | { | |
945315b9 | 2303 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2304 | |
2305 | if (list_empty(invalid_list)) | |
2306 | return; | |
2307 | ||
c142786c | 2308 | /* |
9753f529 LT |
2309 | * We need to make sure everyone sees our modifications to |
2310 | * the page tables and see changes to vcpu->mode here. The barrier | |
2311 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2312 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2313 | * | |
2314 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2315 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2316 | */ |
2317 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2318 | |
945315b9 | 2319 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2320 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2321 | kvm_mmu_free_page(sp); |
945315b9 | 2322 | } |
7775834a XG |
2323 | } |
2324 | ||
6b82ef2c SC |
2325 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2326 | unsigned long nr_to_zap) | |
5da59607 | 2327 | { |
6b82ef2c SC |
2328 | unsigned long total_zapped = 0; |
2329 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2330 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2331 | bool unstable; |
2332 | int nr_zapped; | |
5da59607 TY |
2333 | |
2334 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2335 | return 0; |
2336 | ||
6b82ef2c | 2337 | restart: |
8fc51726 | 2338 | list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) { |
6b82ef2c SC |
2339 | /* |
2340 | * Don't zap active root pages, the page itself can't be freed | |
2341 | * and zapping it will just force vCPUs to realloc and reload. | |
2342 | */ | |
2343 | if (sp->root_count) | |
2344 | continue; | |
2345 | ||
2346 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2347 | &nr_zapped); | |
2348 | total_zapped += nr_zapped; | |
2349 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2350 | break; |
2351 | ||
6b82ef2c SC |
2352 | if (unstable) |
2353 | goto restart; | |
ba7888dd | 2354 | } |
5da59607 | 2355 | |
6b82ef2c SC |
2356 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2357 | ||
2358 | kvm->stat.mmu_recycled += total_zapped; | |
2359 | return total_zapped; | |
2360 | } | |
2361 | ||
afe8d7e6 SC |
2362 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2363 | { | |
2364 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2365 | return kvm->arch.n_max_mmu_pages - | |
2366 | kvm->arch.n_used_mmu_pages; | |
2367 | ||
2368 | return 0; | |
5da59607 TY |
2369 | } |
2370 | ||
ba7888dd SC |
2371 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2372 | { | |
6b82ef2c | 2373 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2374 | |
6b82ef2c | 2375 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2376 | return 0; |
2377 | ||
6b82ef2c | 2378 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd | 2379 | |
6e6ec584 SC |
2380 | /* |
2381 | * Note, this check is intentionally soft, it only guarantees that one | |
2382 | * page is available, while the caller may end up allocating as many as | |
2383 | * four pages, e.g. for PAE roots or for 5-level paging. Temporarily | |
2384 | * exceeding the (arbitrary by default) limit will not harm the host, | |
2385 | * being too agressive may unnecessarily kill the guest, and getting an | |
2386 | * exact count is far more trouble than it's worth, especially in the | |
2387 | * page fault paths. | |
2388 | */ | |
ba7888dd SC |
2389 | if (!kvm_mmu_available_pages(vcpu->kvm)) |
2390 | return -ENOSPC; | |
2391 | return 0; | |
2392 | } | |
2393 | ||
82ce2c96 IE |
2394 | /* |
2395 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2396 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2397 | */ |
bc8a3d89 | 2398 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2399 | { |
531810ca | 2400 | write_lock(&kvm->mmu_lock); |
b34cb590 | 2401 | |
49d5ca26 | 2402 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2403 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2404 | goal_nr_mmu_pages); | |
82ce2c96 | 2405 | |
49d5ca26 | 2406 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2407 | } |
82ce2c96 | 2408 | |
49d5ca26 | 2409 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 | 2410 | |
531810ca | 2411 | write_unlock(&kvm->mmu_lock); |
82ce2c96 IE |
2412 | } |
2413 | ||
1cb3f3ae | 2414 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2415 | { |
4db35314 | 2416 | struct kvm_mmu_page *sp; |
d98ba053 | 2417 | LIST_HEAD(invalid_list); |
a436036b AK |
2418 | int r; |
2419 | ||
9ad17b10 | 2420 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2421 | r = 0; |
531810ca | 2422 | write_lock(&kvm->mmu_lock); |
b67bfe0d | 2423 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2424 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2425 | sp->role.word); |
2426 | r = 1; | |
f41d335a | 2427 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2428 | } |
d98ba053 | 2429 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 2430 | write_unlock(&kvm->mmu_lock); |
1cb3f3ae | 2431 | |
a436036b | 2432 | return r; |
cea0f0e7 | 2433 | } |
96ad91ae SC |
2434 | |
2435 | static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) | |
2436 | { | |
2437 | gpa_t gpa; | |
2438 | int r; | |
2439 | ||
2440 | if (vcpu->arch.mmu->direct_map) | |
2441 | return 0; | |
2442 | ||
2443 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); | |
2444 | ||
2445 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2446 | ||
2447 | return r; | |
2448 | } | |
cea0f0e7 | 2449 | |
5c520e90 | 2450 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2451 | { |
2452 | trace_kvm_mmu_unsync_page(sp); | |
2453 | ++vcpu->kvm->stat.mmu_unsync; | |
2454 | sp->unsync = 1; | |
2455 | ||
2456 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2457 | } |
2458 | ||
5a9624af PB |
2459 | bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2460 | bool can_unsync) | |
4731d4c7 | 2461 | { |
5c520e90 | 2462 | struct kvm_mmu_page *sp; |
4731d4c7 | 2463 | |
3d0c27ad XG |
2464 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2465 | return true; | |
9cf5cf5a | 2466 | |
5c520e90 | 2467 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2468 | if (!can_unsync) |
3d0c27ad | 2469 | return true; |
36a2e677 | 2470 | |
5c520e90 XG |
2471 | if (sp->unsync) |
2472 | continue; | |
9cf5cf5a | 2473 | |
3bae0459 | 2474 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2475 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2476 | } |
3d0c27ad | 2477 | |
578e1c4d JS |
2478 | /* |
2479 | * We need to ensure that the marking of unsync pages is visible | |
2480 | * before the SPTE is updated to allow writes because | |
2481 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2482 | * the MMU lock and so can race with this. If the SPTE was updated | |
2483 | * before the page had been marked as unsync-ed, something like the | |
2484 | * following could happen: | |
2485 | * | |
2486 | * CPU 1 CPU 2 | |
2487 | * --------------------------------------------------------------------- | |
2488 | * 1.2 Host updates SPTE | |
2489 | * to be writable | |
2490 | * 2.1 Guest writes a GPTE for GVA X. | |
2491 | * (GPTE being in the guest page table shadowed | |
2492 | * by the SP from CPU 1.) | |
2493 | * This reads SPTE during the page table walk. | |
2494 | * Since SPTE.W is read as 1, there is no | |
2495 | * fault. | |
2496 | * | |
2497 | * 2.2 Guest issues TLB flush. | |
2498 | * That causes a VM Exit. | |
2499 | * | |
2500 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2501 | * Since it is false, so it just returns. | |
2502 | * | |
2503 | * 2.4 Guest accesses GVA X. | |
2504 | * Since the mapping in the SP was not updated, | |
2505 | * so the old mapping for GVA X incorrectly | |
2506 | * gets used. | |
2507 | * 1.1 Host marks SP | |
2508 | * as unsync | |
2509 | * (sp->unsync = true) | |
2510 | * | |
2511 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2512 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2513 | * pairs with this write barrier. | |
2514 | */ | |
2515 | smp_wmb(); | |
2516 | ||
3d0c27ad | 2517 | return false; |
4731d4c7 MT |
2518 | } |
2519 | ||
799a4190 BG |
2520 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2521 | unsigned int pte_access, int level, | |
2522 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2523 | bool can_unsync, bool host_writable) | |
2524 | { | |
2525 | u64 spte; | |
2526 | struct kvm_mmu_page *sp; | |
2527 | int ret; | |
2528 | ||
799a4190 BG |
2529 | sp = sptep_to_sp(sptep); |
2530 | ||
2531 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2532 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2533 | ||
2534 | if (spte & PT_WRITABLE_MASK) | |
2535 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2536 | ||
12703759 SC |
2537 | if (*sptep == spte) |
2538 | ret |= SET_SPTE_SPURIOUS; | |
2539 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2540 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2541 | return ret; |
2542 | } | |
2543 | ||
0a2b64c5 | 2544 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2545 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2546 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2547 | bool host_writable) | |
1e73f9dd MT |
2548 | { |
2549 | int was_rmapped = 0; | |
53a27b39 | 2550 | int rmap_count; |
5ce4786f | 2551 | int set_spte_ret; |
c4371c2a | 2552 | int ret = RET_PF_FIXED; |
c2a4eadf | 2553 | bool flush = false; |
1e73f9dd | 2554 | |
f7616203 XG |
2555 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2556 | *sptep, write_fault, gfn); | |
1e73f9dd | 2557 | |
a54aa15c SC |
2558 | if (unlikely(is_noslot_pfn(pfn))) { |
2559 | mark_mmio_spte(vcpu, sptep, gfn, pte_access); | |
2560 | return RET_PF_EMULATE; | |
2561 | } | |
2562 | ||
afd28fe1 | 2563 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2564 | /* |
2565 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2566 | * the parent of the now unreachable PTE. | |
2567 | */ | |
3bae0459 | 2568 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2569 | struct kvm_mmu_page *child; |
d555c333 | 2570 | u64 pte = *sptep; |
1e73f9dd | 2571 | |
e47c4aee | 2572 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2573 | drop_parent_pte(child, sptep); |
c2a4eadf | 2574 | flush = true; |
d555c333 | 2575 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2576 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2577 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2578 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2579 | flush = true; |
6bed6b9e JR |
2580 | } else |
2581 | was_rmapped = 1; | |
1e73f9dd | 2582 | } |
852e3c19 | 2583 | |
5ce4786f JS |
2584 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2585 | speculative, true, host_writable); | |
2586 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2587 | if (write_fault) |
9b8ebbdb | 2588 | ret = RET_PF_EMULATE; |
8c8560b8 | 2589 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2590 | } |
c3134ce2 | 2591 | |
c2a4eadf | 2592 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2593 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2594 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2595 | |
12703759 SC |
2596 | /* |
2597 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2598 | * are identical, and emulation is not required. | |
2599 | */ | |
2600 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2601 | WARN_ON_ONCE(!was_rmapped); | |
2602 | return RET_PF_SPURIOUS; | |
2603 | } | |
2604 | ||
d555c333 | 2605 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2606 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2607 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2608 | ++vcpu->kvm->stat.lpages; |
2609 | ||
ffb61bb3 | 2610 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2611 | if (!was_rmapped) { |
2612 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2613 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2614 | rmap_recycle(vcpu, sptep, gfn); | |
2615 | } | |
1c4f1fd6 | 2616 | } |
cb9aaa30 | 2617 | |
9b8ebbdb | 2618 | return ret; |
1c4f1fd6 AK |
2619 | } |
2620 | ||
ba049e93 | 2621 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2622 | bool no_dirty_log) |
2623 | { | |
2624 | struct kvm_memory_slot *slot; | |
957ed9ef | 2625 | |
5d163b1c | 2626 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2627 | if (!slot) |
6c8ee57b | 2628 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2629 | |
037d92dc | 2630 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2631 | } |
2632 | ||
2633 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2634 | struct kvm_mmu_page *sp, | |
2635 | u64 *start, u64 *end) | |
2636 | { | |
2637 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2638 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2639 | unsigned int access = sp->role.access; |
957ed9ef XG |
2640 | int i, ret; |
2641 | gfn_t gfn; | |
2642 | ||
2643 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2644 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2645 | if (!slot) | |
957ed9ef XG |
2646 | return -1; |
2647 | ||
d9ef13c2 | 2648 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2649 | if (ret <= 0) |
2650 | return -1; | |
2651 | ||
43fdcda9 | 2652 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2653 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2654 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2655 | put_page(pages[i]); |
2656 | } | |
957ed9ef XG |
2657 | |
2658 | return 0; | |
2659 | } | |
2660 | ||
2661 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2662 | struct kvm_mmu_page *sp, u64 *sptep) | |
2663 | { | |
2664 | u64 *spte, *start = NULL; | |
2665 | int i; | |
2666 | ||
2667 | WARN_ON(!sp->role.direct); | |
2668 | ||
2669 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2670 | spte = sp->spt + i; | |
2671 | ||
2672 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2673 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2674 | if (!start) |
2675 | continue; | |
2676 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2677 | break; | |
2678 | start = NULL; | |
2679 | } else if (!start) | |
2680 | start = spte; | |
2681 | } | |
2682 | } | |
2683 | ||
2684 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2685 | { | |
2686 | struct kvm_mmu_page *sp; | |
2687 | ||
57354682 | 2688 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2689 | |
957ed9ef | 2690 | /* |
ac8d57e5 PF |
2691 | * Without accessed bits, there's no way to distinguish between |
2692 | * actually accessed translations and prefetched, so disable pte | |
2693 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2694 | */ |
ac8d57e5 | 2695 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2696 | return; |
2697 | ||
3bae0459 | 2698 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2699 | return; |
2700 | ||
4a42d848 DS |
2701 | /* |
2702 | * If addresses are being invalidated, skip prefetching to avoid | |
2703 | * accidentally prefetching those addresses. | |
2704 | */ | |
2705 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
2706 | return; | |
2707 | ||
957ed9ef XG |
2708 | __direct_pte_prefetch(vcpu, sp, sptep); |
2709 | } | |
2710 | ||
1b6d9d9e | 2711 | static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, |
8ca6f063 | 2712 | const struct kvm_memory_slot *slot) |
db543216 | 2713 | { |
db543216 SC |
2714 | unsigned long hva; |
2715 | pte_t *pte; | |
2716 | int level; | |
2717 | ||
e851265a | 2718 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2719 | return PG_LEVEL_4K; |
db543216 | 2720 | |
293e306e SC |
2721 | /* |
2722 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2723 | * is not solely for performance, it's also necessary to avoid the | |
2724 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2725 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2726 | * page fault steps have already verified the guest isn't writing a | |
2727 | * read-only memslot. | |
2728 | */ | |
db543216 SC |
2729 | hva = __gfn_to_hva_memslot(slot, gfn); |
2730 | ||
1b6d9d9e | 2731 | pte = lookup_address_in_mm(kvm->mm, hva, &level); |
db543216 | 2732 | if (unlikely(!pte)) |
3bae0459 | 2733 | return PG_LEVEL_4K; |
db543216 SC |
2734 | |
2735 | return level; | |
2736 | } | |
2737 | ||
8ca6f063 BG |
2738 | int kvm_mmu_max_mapping_level(struct kvm *kvm, |
2739 | const struct kvm_memory_slot *slot, gfn_t gfn, | |
2740 | kvm_pfn_t pfn, int max_level) | |
1b6d9d9e SC |
2741 | { |
2742 | struct kvm_lpage_info *linfo; | |
2743 | ||
2744 | max_level = min(max_level, max_huge_page_level); | |
2745 | for ( ; max_level > PG_LEVEL_4K; max_level--) { | |
2746 | linfo = lpage_info_slot(gfn, slot, max_level); | |
2747 | if (!linfo->disallow_lpage) | |
2748 | break; | |
2749 | } | |
2750 | ||
2751 | if (max_level == PG_LEVEL_4K) | |
2752 | return PG_LEVEL_4K; | |
2753 | ||
2754 | return host_pfn_mapping_level(kvm, gfn, pfn, slot); | |
2755 | } | |
2756 | ||
bb18842e BG |
2757 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2758 | int max_level, kvm_pfn_t *pfnp, | |
2759 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2760 | { |
293e306e | 2761 | struct kvm_memory_slot *slot; |
0885904d | 2762 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2763 | kvm_pfn_t mask; |
83f06fa7 | 2764 | int level; |
17eff019 | 2765 | |
3cf06612 SC |
2766 | *req_level = PG_LEVEL_4K; |
2767 | ||
3bae0459 SC |
2768 | if (unlikely(max_level == PG_LEVEL_4K)) |
2769 | return PG_LEVEL_4K; | |
17eff019 | 2770 | |
e851265a | 2771 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2772 | return PG_LEVEL_4K; |
17eff019 | 2773 | |
293e306e SC |
2774 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2775 | if (!slot) | |
3bae0459 | 2776 | return PG_LEVEL_4K; |
293e306e | 2777 | |
1b6d9d9e | 2778 | level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level); |
3bae0459 | 2779 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2780 | return level; |
17eff019 | 2781 | |
3cf06612 SC |
2782 | *req_level = level = min(level, max_level); |
2783 | ||
2784 | /* | |
2785 | * Enforce the iTLB multihit workaround after capturing the requested | |
2786 | * level, which will be used to do precise, accurate accounting. | |
2787 | */ | |
2788 | if (huge_page_disallowed) | |
2789 | return PG_LEVEL_4K; | |
0885904d SC |
2790 | |
2791 | /* | |
17eff019 SC |
2792 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2793 | * the pmd can't be split from under us. | |
0885904d | 2794 | */ |
17eff019 SC |
2795 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2796 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2797 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2798 | |
2799 | return level; | |
0885904d SC |
2800 | } |
2801 | ||
bb18842e BG |
2802 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2803 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2804 | { |
bb18842e | 2805 | int level = *goal_levelp; |
b8e8c830 | 2806 | |
7d945312 | 2807 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2808 | is_shadow_present_pte(spte) && |
2809 | !is_large_pte(spte)) { | |
2810 | /* | |
2811 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2812 | * and __direct_map would like to create a large PTE | |
2813 | * instead: just force them to go down another level, | |
2814 | * patching back for them into pfn the next 9 bits of | |
2815 | * the address. | |
2816 | */ | |
7d945312 BG |
2817 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2818 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2819 | *pfnp |= gfn & page_mask; |
bb18842e | 2820 | (*goal_levelp)--; |
b8e8c830 PB |
2821 | } |
2822 | } | |
2823 | ||
6c2fd34f | 2824 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2825 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2826 | bool prefault, bool is_tdp) |
140754bc | 2827 | { |
6c2fd34f SC |
2828 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2829 | bool write = error_code & PFERR_WRITE_MASK; | |
2830 | bool exec = error_code & PFERR_FETCH_MASK; | |
2831 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2832 | struct kvm_shadow_walk_iterator it; |
140754bc | 2833 | struct kvm_mmu_page *sp; |
3cf06612 | 2834 | int level, req_level, ret; |
3fcf2d1b PB |
2835 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2836 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2837 | |
3cf06612 SC |
2838 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2839 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2840 | |
335e192a | 2841 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2842 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2843 | /* |
2844 | * We cannot overwrite existing page tables with an NX | |
2845 | * large page, as the leaf could be executable. | |
2846 | */ | |
dcc70651 | 2847 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
2848 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
2849 | &pfn, &level); | |
b8e8c830 | 2850 | |
3fcf2d1b PB |
2851 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2852 | if (it.level == level) | |
9f652d21 | 2853 | break; |
6aa8b732 | 2854 | |
3fcf2d1b PB |
2855 | drop_large_spte(vcpu, it.sptep); |
2856 | if (!is_shadow_present_pte(*it.sptep)) { | |
2857 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2858 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2859 | |
3fcf2d1b | 2860 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2861 | if (is_tdp && huge_page_disallowed && |
2862 | req_level >= it.level) | |
b8e8c830 | 2863 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2864 | } |
2865 | } | |
3fcf2d1b PB |
2866 | |
2867 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2868 | write, level, base_gfn, pfn, prefault, | |
2869 | map_writable); | |
12703759 SC |
2870 | if (ret == RET_PF_SPURIOUS) |
2871 | return ret; | |
2872 | ||
3fcf2d1b PB |
2873 | direct_pte_prefetch(vcpu, it.sptep); |
2874 | ++vcpu->stat.pf_fixed; | |
2875 | return ret; | |
6aa8b732 AK |
2876 | } |
2877 | ||
77db5cbd | 2878 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2879 | { |
585a8b9b | 2880 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2881 | } |
2882 | ||
ba049e93 | 2883 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2884 | { |
4d8b81ab XG |
2885 | /* |
2886 | * Do not cache the mmio info caused by writing the readonly gfn | |
2887 | * into the spte otherwise read access on readonly gfn also can | |
2888 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2889 | */ |
2890 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2891 | return RET_PF_EMULATE; |
4d8b81ab | 2892 | |
e6c1502b | 2893 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2894 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2895 | return RET_PF_RETRY; |
d7c55201 | 2896 | } |
edba23e5 | 2897 | |
2c151b25 | 2898 | return -EFAULT; |
bf998156 HY |
2899 | } |
2900 | ||
d7c55201 | 2901 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2902 | kvm_pfn_t pfn, unsigned int access, |
2903 | int *ret_val) | |
d7c55201 | 2904 | { |
d7c55201 | 2905 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2906 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2907 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2908 | return true; |
d7c55201 XG |
2909 | } |
2910 | ||
30ab5901 | 2911 | if (unlikely(is_noslot_pfn(pfn))) { |
4af77151 SC |
2912 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2913 | access & shadow_mmio_access_mask); | |
30ab5901 SC |
2914 | /* |
2915 | * If MMIO caching is disabled, emulate immediately without | |
2916 | * touching the shadow page tables as attempting to install an | |
2917 | * MMIO SPTE will just be an expensive nop. | |
2918 | */ | |
2919 | if (unlikely(!shadow_mmio_value)) { | |
2920 | *ret_val = RET_PF_EMULATE; | |
2921 | return true; | |
2922 | } | |
2923 | } | |
d7c55201 | 2924 | |
798e88b3 | 2925 | return false; |
d7c55201 XG |
2926 | } |
2927 | ||
e5552fd2 | 2928 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2929 | { |
1c118b82 XG |
2930 | /* |
2931 | * Do not fix the mmio spte with invalid generation number which | |
2932 | * need to be updated by slow page fault path. | |
2933 | */ | |
2934 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2935 | return false; | |
2936 | ||
f160c7b7 JS |
2937 | /* See if the page fault is due to an NX violation */ |
2938 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
2939 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
2940 | return false; | |
2941 | ||
c7ba5b48 | 2942 | /* |
f160c7b7 JS |
2943 | * #PF can be fast if: |
2944 | * 1. The shadow page table entry is not present, which could mean that | |
2945 | * the fault is potentially caused by access tracking (if enabled). | |
2946 | * 2. The shadow page table entry is present and the fault | |
2947 | * is caused by write-protect, that means we just need change the W | |
2948 | * bit of the spte which can be done out of mmu-lock. | |
2949 | * | |
2950 | * However, if access tracking is disabled we know that a non-present | |
2951 | * page must be a genuine page fault where we have to create a new SPTE. | |
2952 | * So, if access tracking is disabled, we return true only for write | |
2953 | * accesses to a present page. | |
c7ba5b48 | 2954 | */ |
c7ba5b48 | 2955 | |
f160c7b7 JS |
2956 | return shadow_acc_track_mask != 0 || |
2957 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
2958 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
2959 | } |
2960 | ||
97dceba2 JS |
2961 | /* |
2962 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
2963 | * someone else modified the SPTE from its original value. | |
2964 | */ | |
c7ba5b48 | 2965 | static bool |
92a476cb | 2966 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 2967 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 2968 | { |
c7ba5b48 XG |
2969 | gfn_t gfn; |
2970 | ||
2971 | WARN_ON(!sp->role.direct); | |
2972 | ||
9b51a630 KH |
2973 | /* |
2974 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
2975 | * order to eliminate unnecessary PML logging. See comments in | |
2976 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
2977 | * enabled, so we do not do this. This might result in the same GPA | |
2978 | * to be logged in PML buffer again when the write really happens, and | |
2979 | * eventually to be called by mark_page_dirty twice. But it's also no | |
2980 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
2981 | * so non-PML cases won't be impacted. | |
2982 | * | |
2983 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
2984 | */ | |
f160c7b7 | 2985 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
2986 | return false; |
2987 | ||
d3e328f2 | 2988 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
2989 | /* |
2990 | * The gfn of direct spte is stable since it is | |
2991 | * calculated by sp->gfn. | |
2992 | */ | |
2993 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2994 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2995 | } | |
c7ba5b48 XG |
2996 | |
2997 | return true; | |
2998 | } | |
2999 | ||
d3e328f2 JS |
3000 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3001 | { | |
3002 | if (fault_err_code & PFERR_FETCH_MASK) | |
3003 | return is_executable_pte(spte); | |
3004 | ||
3005 | if (fault_err_code & PFERR_WRITE_MASK) | |
3006 | return is_writable_pte(spte); | |
3007 | ||
3008 | /* Fault was on Read access */ | |
3009 | return spte & PT_PRESENT_MASK; | |
3010 | } | |
3011 | ||
c7ba5b48 | 3012 | /* |
c4371c2a | 3013 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3014 | */ |
c4371c2a SC |
3015 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3016 | u32 error_code) | |
c7ba5b48 XG |
3017 | { |
3018 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3019 | struct kvm_mmu_page *sp; |
c4371c2a | 3020 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3021 | u64 spte = 0ull; |
97dceba2 | 3022 | uint retry_count = 0; |
c7ba5b48 | 3023 | |
e5552fd2 | 3024 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3025 | return ret; |
c7ba5b48 XG |
3026 | |
3027 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3028 | |
97dceba2 | 3029 | do { |
d3e328f2 | 3030 | u64 new_spte; |
c7ba5b48 | 3031 | |
736c291c | 3032 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3033 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3034 | break; |
3035 | ||
ec89e643 SC |
3036 | if (!is_shadow_present_pte(spte)) |
3037 | break; | |
3038 | ||
57354682 | 3039 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3040 | if (!is_last_spte(spte, sp->role.level)) |
3041 | break; | |
c7ba5b48 | 3042 | |
97dceba2 | 3043 | /* |
f160c7b7 JS |
3044 | * Check whether the memory access that caused the fault would |
3045 | * still cause it if it were to be performed right now. If not, | |
3046 | * then this is a spurious fault caused by TLB lazily flushed, | |
3047 | * or some other CPU has already fixed the PTE after the | |
3048 | * current CPU took the fault. | |
97dceba2 JS |
3049 | * |
3050 | * Need not check the access of upper level table entries since | |
3051 | * they are always ACC_ALL. | |
3052 | */ | |
d3e328f2 | 3053 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3054 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3055 | break; |
3056 | } | |
f160c7b7 | 3057 | |
d3e328f2 JS |
3058 | new_spte = spte; |
3059 | ||
3060 | if (is_access_track_spte(spte)) | |
3061 | new_spte = restore_acc_track_spte(new_spte); | |
3062 | ||
3063 | /* | |
3064 | * Currently, to simplify the code, write-protection can | |
3065 | * be removed in the fast path only if the SPTE was | |
3066 | * write-protected for dirty-logging or access tracking. | |
3067 | */ | |
3068 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3069 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3070 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3071 | |
3072 | /* | |
d3e328f2 JS |
3073 | * Do not fix write-permission on the large spte. Since |
3074 | * we only dirty the first page into the dirty-bitmap in | |
3075 | * fast_pf_fix_direct_spte(), other pages are missed | |
3076 | * if its slot has dirty logging enabled. | |
3077 | * | |
3078 | * Instead, we let the slow page fault path create a | |
3079 | * normal spte to fix the access. | |
3080 | * | |
3081 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3082 | */ |
3bae0459 | 3083 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3084 | break; |
97dceba2 | 3085 | } |
c7ba5b48 | 3086 | |
f160c7b7 | 3087 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3088 | if (new_spte == spte || |
3089 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3090 | break; |
3091 | ||
3092 | /* | |
3093 | * Currently, fast page fault only works for direct mapping | |
3094 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3095 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3096 | */ |
c4371c2a SC |
3097 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3098 | new_spte)) { | |
3099 | ret = RET_PF_FIXED; | |
97dceba2 | 3100 | break; |
c4371c2a | 3101 | } |
97dceba2 JS |
3102 | |
3103 | if (++retry_count > 4) { | |
3104 | printk_once(KERN_WARNING | |
3105 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3106 | break; | |
3107 | } | |
3108 | ||
97dceba2 | 3109 | } while (true); |
c126d94f | 3110 | |
736c291c | 3111 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3112 | spte, ret); |
c7ba5b48 XG |
3113 | walk_shadow_page_lockless_end(vcpu); |
3114 | ||
c4371c2a | 3115 | return ret; |
c7ba5b48 XG |
3116 | } |
3117 | ||
74b566e6 JS |
3118 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3119 | struct list_head *invalid_list) | |
17ac10ad | 3120 | { |
4db35314 | 3121 | struct kvm_mmu_page *sp; |
17ac10ad | 3122 | |
74b566e6 | 3123 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3124 | return; |
35af577a | 3125 | |
e47c4aee | 3126 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a | 3127 | |
2bdb3d84 | 3128 | if (is_tdp_mmu_page(sp)) |
6103bc07 | 3129 | kvm_tdp_mmu_put_root(kvm, sp, false); |
76eb54e7 BG |
3130 | else if (!--sp->root_count && sp->role.invalid) |
3131 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3132 | |
74b566e6 JS |
3133 | *root_hpa = INVALID_PAGE; |
3134 | } | |
3135 | ||
08fb59d8 | 3136 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3137 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3138 | ulong roots_to_free) | |
74b566e6 | 3139 | { |
4d710de9 | 3140 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3141 | int i; |
3142 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3143 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3144 | |
b94742c9 | 3145 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3146 | |
08fb59d8 | 3147 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3148 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3149 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3150 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3151 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3152 | break; | |
3153 | ||
3154 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3155 | return; | |
3156 | } | |
35af577a | 3157 | |
531810ca | 3158 | write_lock(&kvm->mmu_lock); |
17ac10ad | 3159 | |
b94742c9 JS |
3160 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3161 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3162 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3163 | &invalid_list); |
7c390d35 | 3164 | |
08fb59d8 JS |
3165 | if (free_active_root) { |
3166 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3167 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3168 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
04d45551 | 3169 | } else if (mmu->pae_root) { |
c834e5e4 SC |
3170 | for (i = 0; i < 4; ++i) { |
3171 | if (!IS_VALID_PAE_ROOT(mmu->pae_root[i])) | |
3172 | continue; | |
3173 | ||
3174 | mmu_free_root_page(kvm, &mmu->pae_root[i], | |
3175 | &invalid_list); | |
3176 | mmu->pae_root[i] = INVALID_PAE_ROOT; | |
3177 | } | |
08fb59d8 | 3178 | } |
04d45551 | 3179 | mmu->root_hpa = INVALID_PAGE; |
be01e8e2 | 3180 | mmu->root_pgd = 0; |
17ac10ad | 3181 | } |
74b566e6 | 3182 | |
4d710de9 | 3183 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 3184 | write_unlock(&kvm->mmu_lock); |
17ac10ad | 3185 | } |
74b566e6 | 3186 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3187 | |
25b62c62 SC |
3188 | void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3189 | { | |
3190 | unsigned long roots_to_free = 0; | |
3191 | hpa_t root_hpa; | |
3192 | int i; | |
3193 | ||
3194 | /* | |
3195 | * This should not be called while L2 is active, L2 can't invalidate | |
3196 | * _only_ its own roots, e.g. INVVPID unconditionally exits. | |
3197 | */ | |
3198 | WARN_ON_ONCE(mmu->mmu_role.base.guest_mode); | |
3199 | ||
3200 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
3201 | root_hpa = mmu->prev_roots[i].hpa; | |
3202 | if (!VALID_PAGE(root_hpa)) | |
3203 | continue; | |
3204 | ||
3205 | if (!to_shadow_page(root_hpa) || | |
3206 | to_shadow_page(root_hpa)->role.guest_mode) | |
3207 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
3208 | } | |
3209 | ||
3210 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
3211 | } | |
3212 | EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots); | |
3213 | ||
3214 | ||
8986ecc0 MT |
3215 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3216 | { | |
3217 | int ret = 0; | |
3218 | ||
995decb6 | 3219 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3220 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3221 | ret = 1; |
3222 | } | |
3223 | ||
3224 | return ret; | |
3225 | } | |
3226 | ||
8123f265 SC |
3227 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3228 | u8 level, bool direct) | |
651dd37a JR |
3229 | { |
3230 | struct kvm_mmu_page *sp; | |
8123f265 | 3231 | |
8123f265 SC |
3232 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); |
3233 | ++sp->root_count; | |
3234 | ||
8123f265 SC |
3235 | return __pa(sp->spt); |
3236 | } | |
3237 | ||
3238 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3239 | { | |
b37233c9 SC |
3240 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
3241 | u8 shadow_root_level = mmu->shadow_root_level; | |
8123f265 | 3242 | hpa_t root; |
7ebaf15e | 3243 | unsigned i; |
4a38162e PB |
3244 | int r; |
3245 | ||
3246 | write_lock(&vcpu->kvm->mmu_lock); | |
3247 | r = make_mmu_pages_available(vcpu); | |
3248 | if (r < 0) | |
3249 | goto out_unlock; | |
651dd37a | 3250 | |
897218ff | 3251 | if (is_tdp_mmu_enabled(vcpu->kvm)) { |
02c00b3a | 3252 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); |
b37233c9 | 3253 | mmu->root_hpa = root; |
02c00b3a | 3254 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { |
6e6ec584 | 3255 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true); |
b37233c9 | 3256 | mmu->root_hpa = root; |
8123f265 | 3257 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { |
4a38162e PB |
3258 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3259 | r = -EIO; | |
3260 | goto out_unlock; | |
3261 | } | |
73ad1606 | 3262 | |
651dd37a | 3263 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3264 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
651dd37a | 3265 | |
8123f265 SC |
3266 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3267 | i << 30, PT32_ROOT_LEVEL, true); | |
17e368d9 SC |
3268 | mmu->pae_root[i] = root | PT_PRESENT_MASK | |
3269 | shadow_me_mask; | |
651dd37a | 3270 | } |
b37233c9 | 3271 | mmu->root_hpa = __pa(mmu->pae_root); |
73ad1606 SC |
3272 | } else { |
3273 | WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level); | |
4a38162e PB |
3274 | r = -EIO; |
3275 | goto out_unlock; | |
73ad1606 | 3276 | } |
3651c7fc | 3277 | |
be01e8e2 | 3278 | /* root_pgd is ignored for direct MMUs. */ |
b37233c9 | 3279 | mmu->root_pgd = 0; |
4a38162e PB |
3280 | out_unlock: |
3281 | write_unlock(&vcpu->kvm->mmu_lock); | |
3282 | return r; | |
651dd37a JR |
3283 | } |
3284 | ||
3285 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3286 | { |
b37233c9 | 3287 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
6e0918ae | 3288 | u64 pdptrs[4], pm_mask; |
be01e8e2 | 3289 | gfn_t root_gfn, root_pgd; |
8123f265 | 3290 | hpa_t root; |
4a38162e PB |
3291 | unsigned i; |
3292 | int r; | |
3bb65a22 | 3293 | |
b37233c9 | 3294 | root_pgd = mmu->get_guest_pgd(vcpu); |
be01e8e2 | 3295 | root_gfn = root_pgd >> PAGE_SHIFT; |
17ac10ad | 3296 | |
651dd37a JR |
3297 | if (mmu_check_root(vcpu, root_gfn)) |
3298 | return 1; | |
3299 | ||
4a38162e PB |
3300 | /* |
3301 | * On SVM, reading PDPTRs might access guest memory, which might fault | |
3302 | * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock. | |
3303 | */ | |
6e0918ae SC |
3304 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
3305 | for (i = 0; i < 4; ++i) { | |
3306 | pdptrs[i] = mmu->get_pdptr(vcpu, i); | |
3307 | if (!(pdptrs[i] & PT_PRESENT_MASK)) | |
3308 | continue; | |
3309 | ||
3310 | if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT)) | |
3311 | return 1; | |
3312 | } | |
3313 | } | |
3314 | ||
d501f747 BG |
3315 | r = alloc_all_memslots_rmaps(vcpu->kvm); |
3316 | if (r) | |
3317 | return r; | |
3318 | ||
4a38162e PB |
3319 | write_lock(&vcpu->kvm->mmu_lock); |
3320 | r = make_mmu_pages_available(vcpu); | |
3321 | if (r < 0) | |
3322 | goto out_unlock; | |
3323 | ||
651dd37a JR |
3324 | /* |
3325 | * Do we shadow a long mode page table? If so we need to | |
3326 | * write-protect the guests page table root. | |
3327 | */ | |
b37233c9 | 3328 | if (mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3329 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
b37233c9 | 3330 | mmu->shadow_root_level, false); |
b37233c9 | 3331 | mmu->root_hpa = root; |
be01e8e2 | 3332 | goto set_root_pgd; |
17ac10ad | 3333 | } |
f87f9288 | 3334 | |
4a38162e PB |
3335 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3336 | r = -EIO; | |
3337 | goto out_unlock; | |
3338 | } | |
73ad1606 | 3339 | |
651dd37a JR |
3340 | /* |
3341 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3342 | * or a PAE 3-level page table. In either case we need to be aware that |
3343 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3344 | */ |
17e368d9 | 3345 | pm_mask = PT_PRESENT_MASK | shadow_me_mask; |
748e52b9 | 3346 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3347 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3348 | ||
03ca4589 | 3349 | if (WARN_ON_ONCE(!mmu->pml4_root)) { |
4a38162e PB |
3350 | r = -EIO; |
3351 | goto out_unlock; | |
3352 | } | |
73ad1606 | 3353 | |
03ca4589 | 3354 | mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask; |
04d45551 SC |
3355 | } |
3356 | ||
17ac10ad | 3357 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3358 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
6e6ec584 | 3359 | |
b37233c9 | 3360 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
6e0918ae | 3361 | if (!(pdptrs[i] & PT_PRESENT_MASK)) { |
c834e5e4 | 3362 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
417726a3 AK |
3363 | continue; |
3364 | } | |
6e0918ae | 3365 | root_gfn = pdptrs[i] >> PAGE_SHIFT; |
5a7388c2 | 3366 | } |
8facbbff | 3367 | |
8123f265 SC |
3368 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3369 | PT32_ROOT_LEVEL, false); | |
b37233c9 | 3370 | mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3371 | } |
81407ca5 | 3372 | |
ba0a194f | 3373 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
03ca4589 | 3374 | mmu->root_hpa = __pa(mmu->pml4_root); |
ba0a194f SC |
3375 | else |
3376 | mmu->root_hpa = __pa(mmu->pae_root); | |
81407ca5 | 3377 | |
be01e8e2 | 3378 | set_root_pgd: |
b37233c9 | 3379 | mmu->root_pgd = root_pgd; |
4a38162e PB |
3380 | out_unlock: |
3381 | write_unlock(&vcpu->kvm->mmu_lock); | |
ad7dc69a | 3382 | |
8986ecc0 | 3383 | return 0; |
17ac10ad AK |
3384 | } |
3385 | ||
748e52b9 SC |
3386 | static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) |
3387 | { | |
3388 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
03ca4589 | 3389 | u64 *pml4_root, *pae_root; |
81407ca5 JR |
3390 | |
3391 | /* | |
748e52b9 SC |
3392 | * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP |
3393 | * tables are allocated and initialized at root creation as there is no | |
3394 | * equivalent level in the guest's NPT to shadow. Allocate the tables | |
3395 | * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare. | |
81407ca5 | 3396 | */ |
748e52b9 SC |
3397 | if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL || |
3398 | mmu->shadow_root_level < PT64_ROOT_4LEVEL) | |
3399 | return 0; | |
81407ca5 | 3400 | |
748e52b9 SC |
3401 | /* |
3402 | * This mess only works with 4-level paging and needs to be updated to | |
3403 | * work with 5-level paging. | |
3404 | */ | |
3405 | if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) | |
3406 | return -EIO; | |
81407ca5 | 3407 | |
03ca4589 | 3408 | if (mmu->pae_root && mmu->pml4_root) |
748e52b9 | 3409 | return 0; |
81407ca5 | 3410 | |
748e52b9 SC |
3411 | /* |
3412 | * The special roots should always be allocated in concert. Yell and | |
3413 | * bail if KVM ends up in a state where only one of the roots is valid. | |
3414 | */ | |
03ca4589 | 3415 | if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) |
748e52b9 | 3416 | return -EIO; |
81407ca5 | 3417 | |
4a98623d SC |
3418 | /* |
3419 | * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and | |
3420 | * doesn't need to be decrypted. | |
3421 | */ | |
748e52b9 SC |
3422 | pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3423 | if (!pae_root) | |
3424 | return -ENOMEM; | |
81407ca5 | 3425 | |
03ca4589 SC |
3426 | pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3427 | if (!pml4_root) { | |
748e52b9 SC |
3428 | free_page((unsigned long)pae_root); |
3429 | return -ENOMEM; | |
81407ca5 JR |
3430 | } |
3431 | ||
748e52b9 | 3432 | mmu->pae_root = pae_root; |
03ca4589 | 3433 | mmu->pml4_root = pml4_root; |
ad7dc69a | 3434 | |
8986ecc0 | 3435 | return 0; |
17ac10ad AK |
3436 | } |
3437 | ||
578e1c4d | 3438 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3439 | { |
3440 | int i; | |
3441 | struct kvm_mmu_page *sp; | |
3442 | ||
44dd3ffa | 3443 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3444 | return; |
3445 | ||
44dd3ffa | 3446 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3447 | return; |
6903074c | 3448 | |
56f17dd3 | 3449 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3450 | |
44dd3ffa VK |
3451 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3452 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3453 | sp = to_shadow_page(root); |
578e1c4d JS |
3454 | |
3455 | /* | |
3456 | * Even if another CPU was marking the SP as unsync-ed | |
3457 | * simultaneously, any guest page table changes are not | |
3458 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3459 | * flush strictly after those changes are made. We only need to | |
3460 | * ensure that the other CPU sets these flags before any actual | |
3461 | * changes to the page tables are made. The comments in | |
3462 | * mmu_need_write_protect() describe what could go wrong if this | |
3463 | * requirement isn't satisfied. | |
3464 | */ | |
3465 | if (!smp_load_acquire(&sp->unsync) && | |
3466 | !smp_load_acquire(&sp->unsync_children)) | |
3467 | return; | |
3468 | ||
531810ca | 3469 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3470 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3471 | ||
0ba73cda | 3472 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3473 | |
0375f7fa | 3474 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3475 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3476 | return; |
3477 | } | |
578e1c4d | 3478 | |
531810ca | 3479 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3480 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3481 | ||
0ba73cda | 3482 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3483 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3484 | |
c834e5e4 | 3485 | if (IS_VALID_PAE_ROOT(root)) { |
0ba73cda | 3486 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3487 | sp = to_shadow_page(root); |
0ba73cda MT |
3488 | mmu_sync_children(vcpu, sp); |
3489 | } | |
3490 | } | |
0ba73cda | 3491 | |
578e1c4d | 3492 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3493 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3494 | } |
3495 | ||
736c291c | 3496 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3497 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3498 | { |
ab9ae313 AK |
3499 | if (exception) |
3500 | exception->error_code = 0; | |
6aa8b732 AK |
3501 | return vaddr; |
3502 | } | |
3503 | ||
736c291c | 3504 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3505 | u32 access, |
3506 | struct x86_exception *exception) | |
6539e738 | 3507 | { |
ab9ae313 AK |
3508 | if (exception) |
3509 | exception->error_code = 0; | |
54987b7a | 3510 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3511 | } |
3512 | ||
d625b155 XG |
3513 | static bool |
3514 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3515 | { | |
b5c3c1b3 | 3516 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3517 | |
b5c3c1b3 | 3518 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3519 | } |
3520 | ||
b5c3c1b3 | 3521 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3522 | { |
b5c3c1b3 | 3523 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3524 | } |
3525 | ||
ded58749 | 3526 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3527 | { |
9034e6e8 PB |
3528 | /* |
3529 | * A nested guest cannot use the MMIO cache if it is using nested | |
3530 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3531 | */ | |
3532 | if (mmu_is_nested(vcpu)) | |
3533 | return false; | |
3534 | ||
ce88decf XG |
3535 | if (direct) |
3536 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3537 | ||
3538 | return vcpu_match_mmio_gva(vcpu, addr); | |
3539 | } | |
3540 | ||
95fb5b02 BG |
3541 | /* |
3542 | * Return the level of the lowest level SPTE added to sptes. | |
3543 | * That SPTE may be non-present. | |
3544 | */ | |
39b4d43e | 3545 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level) |
ce88decf XG |
3546 | { |
3547 | struct kvm_shadow_walk_iterator iterator; | |
2aa07893 | 3548 | int leaf = -1; |
95fb5b02 | 3549 | u64 spte; |
ce88decf XG |
3550 | |
3551 | walk_shadow_page_lockless_begin(vcpu); | |
47ab8751 | 3552 | |
39b4d43e SC |
3553 | for (shadow_walk_init(&iterator, vcpu, addr), |
3554 | *root_level = iterator.level; | |
47ab8751 XG |
3555 | shadow_walk_okay(&iterator); |
3556 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3557 | leaf = iterator.level; |
47ab8751 XG |
3558 | spte = mmu_spte_get_lockless(iterator.sptep); |
3559 | ||
dde81f94 | 3560 | sptes[leaf] = spte; |
47ab8751 | 3561 | |
ce88decf XG |
3562 | if (!is_shadow_present_pte(spte)) |
3563 | break; | |
95fb5b02 BG |
3564 | } |
3565 | ||
3566 | walk_shadow_page_lockless_end(vcpu); | |
3567 | ||
3568 | return leaf; | |
3569 | } | |
3570 | ||
9aa41879 | 3571 | /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */ |
95fb5b02 BG |
3572 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) |
3573 | { | |
dde81f94 | 3574 | u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; |
95fb5b02 | 3575 | struct rsvd_bits_validate *rsvd_check; |
39b4d43e | 3576 | int root, leaf, level; |
95fb5b02 BG |
3577 | bool reserved = false; |
3578 | ||
63c0cac9 | 3579 | if (is_tdp_mmu(vcpu->arch.mmu)) |
39b4d43e | 3580 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3581 | else |
39b4d43e | 3582 | leaf = get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3583 | |
2aa07893 SC |
3584 | if (unlikely(leaf < 0)) { |
3585 | *sptep = 0ull; | |
3586 | return reserved; | |
3587 | } | |
3588 | ||
9aa41879 SC |
3589 | *sptep = sptes[leaf]; |
3590 | ||
3591 | /* | |
3592 | * Skip reserved bits checks on the terminal leaf if it's not a valid | |
3593 | * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by | |
3594 | * design, always have reserved bits set. The purpose of the checks is | |
3595 | * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs. | |
3596 | */ | |
3597 | if (!is_shadow_present_pte(sptes[leaf])) | |
3598 | leaf++; | |
95fb5b02 BG |
3599 | |
3600 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3601 | ||
9aa41879 | 3602 | for (level = root; level >= leaf; level--) |
b5c3c1b3 SC |
3603 | /* |
3604 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3605 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3606 | * adding a Jcc in the loop. | |
3607 | */ | |
dde81f94 SC |
3608 | reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) | |
3609 | __is_rsvd_bits_set(rsvd_check, sptes[level], level); | |
47ab8751 | 3610 | |
47ab8751 | 3611 | if (reserved) { |
bb4cdf3a | 3612 | pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n", |
47ab8751 | 3613 | __func__, addr); |
95fb5b02 | 3614 | for (level = root; level >= leaf; level--) |
bb4cdf3a SC |
3615 | pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx", |
3616 | sptes[level], level, | |
3617 | rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]); | |
47ab8751 | 3618 | } |
ddce6208 | 3619 | |
47ab8751 | 3620 | return reserved; |
ce88decf XG |
3621 | } |
3622 | ||
e08d26f0 | 3623 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3624 | { |
3625 | u64 spte; | |
47ab8751 | 3626 | bool reserved; |
ce88decf | 3627 | |
ded58749 | 3628 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3629 | return RET_PF_EMULATE; |
ce88decf | 3630 | |
95fb5b02 | 3631 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3632 | if (WARN_ON(reserved)) |
9b8ebbdb | 3633 | return -EINVAL; |
ce88decf XG |
3634 | |
3635 | if (is_mmio_spte(spte)) { | |
3636 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3637 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3638 | |
54bf36aa | 3639 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3640 | return RET_PF_INVALID; |
f8f55942 | 3641 | |
ce88decf XG |
3642 | if (direct) |
3643 | addr = 0; | |
4f022648 XG |
3644 | |
3645 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3646 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3647 | return RET_PF_EMULATE; |
ce88decf XG |
3648 | } |
3649 | ||
ce88decf XG |
3650 | /* |
3651 | * If the page table is zapped by other cpus, let CPU fault again on | |
3652 | * the address. | |
3653 | */ | |
9b8ebbdb | 3654 | return RET_PF_RETRY; |
ce88decf | 3655 | } |
ce88decf | 3656 | |
3d0c27ad XG |
3657 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3658 | u32 error_code, gfn_t gfn) | |
3659 | { | |
3660 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3661 | return false; | |
3662 | ||
3663 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3664 | !(error_code & PFERR_WRITE_MASK)) | |
3665 | return false; | |
3666 | ||
3667 | /* | |
3668 | * guest is writing the page which is write tracked which can | |
3669 | * not be fixed by page fault handler. | |
3670 | */ | |
3671 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3672 | return true; | |
3673 | ||
3674 | return false; | |
3675 | } | |
3676 | ||
e5691a81 XG |
3677 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3678 | { | |
3679 | struct kvm_shadow_walk_iterator iterator; | |
3680 | u64 spte; | |
3681 | ||
e5691a81 XG |
3682 | walk_shadow_page_lockless_begin(vcpu); |
3683 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3684 | clear_sp_write_flooding_count(iterator.sptep); | |
3685 | if (!is_shadow_present_pte(spte)) | |
3686 | break; | |
3687 | } | |
3688 | walk_shadow_page_lockless_end(vcpu); | |
3689 | } | |
3690 | ||
e8c22266 VK |
3691 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3692 | gfn_t gfn) | |
af585b92 GN |
3693 | { |
3694 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3695 | |
7c90705b | 3696 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3697 | arch.gfn = gfn; |
44dd3ffa | 3698 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3699 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3700 | |
9f1a8526 SC |
3701 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3702 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3703 | } |
3704 | ||
78b2c54a | 3705 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
4a42d848 DS |
3706 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva, |
3707 | bool write, bool *writable) | |
af585b92 | 3708 | { |
c36b7150 | 3709 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3710 | bool async; |
3711 | ||
e0c37868 SC |
3712 | /* |
3713 | * Retry the page fault if the gfn hit a memslot that is being deleted | |
3714 | * or moved. This ensures any existing SPTEs for the old memslot will | |
3715 | * be zapped before KVM inserts a new MMIO SPTE for the gfn. | |
3716 | */ | |
3717 | if (slot && (slot->flags & KVM_MEMSLOT_INVALID)) | |
3718 | return true; | |
3719 | ||
c36b7150 PB |
3720 | /* Don't expose private memslots to L2. */ |
3721 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3722 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3723 | *writable = false; |
3a2936de JM |
3724 | return false; |
3725 | } | |
3726 | ||
3520469d | 3727 | async = false; |
4a42d848 DS |
3728 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, |
3729 | write, writable, hva); | |
af585b92 GN |
3730 | if (!async) |
3731 | return false; /* *pfn has correct page already */ | |
3732 | ||
9bc1f09f | 3733 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3734 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3735 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3736 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3737 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3738 | return true; | |
9f1a8526 | 3739 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3740 | return true; |
3741 | } | |
3742 | ||
4a42d848 DS |
3743 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, |
3744 | write, writable, hva); | |
af585b92 GN |
3745 | return false; |
3746 | } | |
3747 | ||
0f90e1c1 SC |
3748 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3749 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3750 | { |
63c0cac9 | 3751 | bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu); |
367fd790 | 3752 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3753 | bool map_writable; |
6aa8b732 | 3754 | |
0f90e1c1 SC |
3755 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3756 | unsigned long mmu_seq; | |
3757 | kvm_pfn_t pfn; | |
4a42d848 | 3758 | hva_t hva; |
83f06fa7 | 3759 | int r; |
ce88decf | 3760 | |
3d0c27ad | 3761 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3762 | return RET_PF_EMULATE; |
ce88decf | 3763 | |
0b873fd7 | 3764 | if (!is_tdp_mmu_fault) { |
bb18842e BG |
3765 | r = fast_page_fault(vcpu, gpa, error_code); |
3766 | if (r != RET_PF_INVALID) | |
3767 | return r; | |
3768 | } | |
83291445 | 3769 | |
378f5cd6 | 3770 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3771 | if (r) |
3772 | return r; | |
714b93da | 3773 | |
367fd790 SC |
3774 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3775 | smp_rmb(); | |
3776 | ||
4a42d848 DS |
3777 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva, |
3778 | write, &map_writable)) | |
367fd790 SC |
3779 | return RET_PF_RETRY; |
3780 | ||
0f90e1c1 | 3781 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3782 | return r; |
6aa8b732 | 3783 | |
367fd790 | 3784 | r = RET_PF_RETRY; |
a2855afc | 3785 | |
0b873fd7 | 3786 | if (is_tdp_mmu_fault) |
a2855afc BG |
3787 | read_lock(&vcpu->kvm->mmu_lock); |
3788 | else | |
3789 | write_lock(&vcpu->kvm->mmu_lock); | |
3790 | ||
4a42d848 | 3791 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
367fd790 | 3792 | goto out_unlock; |
7bd7ded6 SC |
3793 | r = make_mmu_pages_available(vcpu); |
3794 | if (r) | |
367fd790 | 3795 | goto out_unlock; |
bb18842e | 3796 | |
0b873fd7 | 3797 | if (is_tdp_mmu_fault) |
bb18842e BG |
3798 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, |
3799 | pfn, prefault); | |
3800 | else | |
3801 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3802 | prefault, is_tdp); | |
0f90e1c1 | 3803 | |
367fd790 | 3804 | out_unlock: |
0b873fd7 | 3805 | if (is_tdp_mmu_fault) |
a2855afc BG |
3806 | read_unlock(&vcpu->kvm->mmu_lock); |
3807 | else | |
3808 | write_unlock(&vcpu->kvm->mmu_lock); | |
367fd790 SC |
3809 | kvm_release_pfn_clean(pfn); |
3810 | return r; | |
6aa8b732 AK |
3811 | } |
3812 | ||
0f90e1c1 SC |
3813 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3814 | u32 error_code, bool prefault) | |
3815 | { | |
3816 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3817 | ||
3818 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3819 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3820 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3821 | } |
3822 | ||
1261bfa3 | 3823 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3824 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3825 | { |
3826 | int r = 1; | |
9ce372b3 | 3827 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3828 | |
736c291c SC |
3829 | #ifndef CONFIG_X86_64 |
3830 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3831 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3832 | return -EFAULT; | |
3833 | #endif | |
3834 | ||
c595ceee | 3835 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3836 | if (!flags) { |
1261bfa3 WL |
3837 | trace_kvm_page_fault(fault_address, error_code); |
3838 | ||
d0006530 | 3839 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3840 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3841 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3842 | insn_len); | |
9ce372b3 | 3843 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3844 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3845 | local_irq_disable(); |
6bca69ad | 3846 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3847 | local_irq_enable(); |
9ce372b3 VK |
3848 | } else { |
3849 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3850 | } |
9ce372b3 | 3851 | |
1261bfa3 WL |
3852 | return r; |
3853 | } | |
3854 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3855 | ||
7a02674d SC |
3856 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3857 | bool prefault) | |
fb72d167 | 3858 | { |
cb9b88c6 | 3859 | int max_level; |
fb72d167 | 3860 | |
e662ec3e | 3861 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3862 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3863 | max_level--) { |
3864 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3865 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3866 | |
cb9b88c6 SC |
3867 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3868 | break; | |
fd136902 | 3869 | } |
852e3c19 | 3870 | |
0f90e1c1 SC |
3871 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3872 | max_level, true); | |
fb72d167 JR |
3873 | } |
3874 | ||
8a3c1a33 PB |
3875 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3876 | struct kvm_mmu *context) | |
6aa8b732 | 3877 | { |
6aa8b732 | 3878 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3879 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3880 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3881 | context->invlpg = NULL; |
cea0f0e7 | 3882 | context->root_level = 0; |
6aa8b732 | 3883 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 3884 | context->direct_map = true; |
2d48a985 | 3885 | context->nx = false; |
6aa8b732 AK |
3886 | } |
3887 | ||
be01e8e2 | 3888 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3889 | union kvm_mmu_page_role role) |
3890 | { | |
be01e8e2 | 3891 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3892 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3893 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3894 | } |
3895 | ||
b94742c9 | 3896 | /* |
be01e8e2 | 3897 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3898 | * The current root is also inserted into the cache. |
3899 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3900 | * returned. | |
3901 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3902 | * false is returned. This root should now be freed by the caller. | |
3903 | */ | |
be01e8e2 | 3904 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3905 | union kvm_mmu_page_role new_role) |
3906 | { | |
3907 | uint i; | |
3908 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3909 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3910 | |
be01e8e2 | 3911 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3912 | root.hpa = mmu->root_hpa; |
3913 | ||
be01e8e2 | 3914 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3915 | return true; |
3916 | ||
b94742c9 JS |
3917 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3918 | swap(root, mmu->prev_roots[i]); | |
3919 | ||
be01e8e2 | 3920 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3921 | break; |
3922 | } | |
3923 | ||
3924 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3925 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
3926 | |
3927 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
3928 | } | |
3929 | ||
be01e8e2 | 3930 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 3931 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3932 | { |
44dd3ffa | 3933 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
3934 | |
3935 | /* | |
3936 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
3937 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
3938 | * later if necessary. | |
3939 | */ | |
3940 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 3941 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 3942 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
3943 | |
3944 | return false; | |
6aa8b732 AK |
3945 | } |
3946 | ||
be01e8e2 | 3947 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b5129100 | 3948 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3949 | { |
be01e8e2 | 3950 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
3951 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
3952 | return; | |
3953 | } | |
3954 | ||
3955 | /* | |
3956 | * It's possible that the cached previous root page is obsolete because | |
3957 | * of a change in the MMU generation number. However, changing the | |
3958 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
3959 | * free the root set here and allocate a new one. | |
3960 | */ | |
3961 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
3962 | ||
b5129100 | 3963 | if (force_flush_and_sync_on_reuse) { |
b869855b SC |
3964 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
3965 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
b5129100 | 3966 | } |
b869855b SC |
3967 | |
3968 | /* | |
3969 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
3970 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
3971 | * valid. So clear any cached MMIO info even when we don't need to sync | |
3972 | * the shadow page tables. | |
3973 | */ | |
3974 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
3975 | ||
daa5b6c1 BG |
3976 | /* |
3977 | * If this is a direct root page, it doesn't have a write flooding | |
3978 | * count. Otherwise, clear the write flooding count. | |
3979 | */ | |
3980 | if (!new_role.direct) | |
3981 | __clear_sp_write_flooding_count( | |
3982 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
3983 | } |
3984 | ||
b5129100 | 3985 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) |
0aab33e4 | 3986 | { |
b5129100 | 3987 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu)); |
0aab33e4 | 3988 | } |
be01e8e2 | 3989 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 3990 | |
5777ed34 JR |
3991 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3992 | { | |
9f8fe504 | 3993 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3994 | } |
3995 | ||
54bf36aa | 3996 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 3997 | unsigned int access, int *nr_present) |
ce88decf XG |
3998 | { |
3999 | if (unlikely(is_mmio_spte(*sptep))) { | |
4000 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4001 | mmu_spte_clear_no_track(sptep); | |
4002 | return true; | |
4003 | } | |
4004 | ||
4005 | (*nr_present)++; | |
54bf36aa | 4006 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4007 | return true; |
4008 | } | |
4009 | ||
4010 | return false; | |
4011 | } | |
4012 | ||
6bb69c9b PB |
4013 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4014 | unsigned level, unsigned gpte) | |
6fd01b71 | 4015 | { |
6bb69c9b PB |
4016 | /* |
4017 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4018 | * If it is clear, there are no large pages at this level, so clear | |
4019 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4020 | */ | |
4021 | gpte &= level - mmu->last_nonleaf_level; | |
4022 | ||
829ee279 | 4023 | /* |
3bae0459 SC |
4024 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set |
4025 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
4026 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
829ee279 | 4027 | */ |
3bae0459 | 4028 | gpte |= level - PG_LEVEL_4K - 1; |
829ee279 | 4029 | |
6bb69c9b | 4030 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4031 | } |
4032 | ||
37406aaa NHE |
4033 | #define PTTYPE_EPT 18 /* arbitrary */ |
4034 | #define PTTYPE PTTYPE_EPT | |
4035 | #include "paging_tmpl.h" | |
4036 | #undef PTTYPE | |
4037 | ||
6aa8b732 AK |
4038 | #define PTTYPE 64 |
4039 | #include "paging_tmpl.h" | |
4040 | #undef PTTYPE | |
4041 | ||
4042 | #define PTTYPE 32 | |
4043 | #include "paging_tmpl.h" | |
4044 | #undef PTTYPE | |
4045 | ||
6dc98b86 XG |
4046 | static void |
4047 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4048 | struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4049 | u64 pa_bits_rsvd, int level, bool nx, bool gbpages, |
6fec2144 | 4050 | bool pse, bool amd) |
82725b20 | 4051 | { |
5f7dde7b | 4052 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4053 | u64 nonleaf_bit8_rsvd = 0; |
5b7f575c | 4054 | u64 high_bits_rsvd; |
82725b20 | 4055 | |
a0a64f50 | 4056 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4057 | |
6dc98b86 | 4058 | if (!gbpages) |
5f7dde7b | 4059 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 | 4060 | |
5b7f575c SC |
4061 | if (level == PT32E_ROOT_LEVEL) |
4062 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62); | |
4063 | else | |
4064 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); | |
4065 | ||
4066 | /* Note, NX doesn't exist in PDPTEs, this is handled below. */ | |
4067 | if (!nx) | |
4068 | high_bits_rsvd |= rsvd_bits(63, 63); | |
4069 | ||
a0c0feb5 PB |
4070 | /* |
4071 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4072 | * leaf entries) on AMD CPUs only. | |
4073 | */ | |
6fec2144 | 4074 | if (amd) |
a0c0feb5 PB |
4075 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4076 | ||
6dc98b86 | 4077 | switch (level) { |
82725b20 DE |
4078 | case PT32_ROOT_LEVEL: |
4079 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4080 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4081 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4082 | rsvd_check->rsvd_bits_mask[1][0] = | |
4083 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4084 | |
6dc98b86 | 4085 | if (!pse) { |
a0a64f50 | 4086 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4087 | break; |
4088 | } | |
4089 | ||
82725b20 DE |
4090 | if (is_cpuid_PSE36()) |
4091 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4092 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4093 | else |
4094 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4095 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4096 | break; |
4097 | case PT32E_ROOT_LEVEL: | |
5b7f575c SC |
4098 | rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) | |
4099 | high_bits_rsvd | | |
4100 | rsvd_bits(5, 8) | | |
4101 | rsvd_bits(1, 2); /* PDPTE */ | |
4102 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */ | |
4103 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */ | |
4104 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4105 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4106 | rsvd_check->rsvd_bits_mask[1][0] = |
4107 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4108 | break; |
855feb67 | 4109 | case PT64_ROOT_5LEVEL: |
5b7f575c SC |
4110 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | |
4111 | nonleaf_bit8_rsvd | | |
4112 | rsvd_bits(7, 7); | |
855feb67 YZ |
4113 | rsvd_check->rsvd_bits_mask[1][4] = |
4114 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4115 | fallthrough; |
2a7266a8 | 4116 | case PT64_ROOT_4LEVEL: |
5b7f575c SC |
4117 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | |
4118 | nonleaf_bit8_rsvd | | |
4119 | rsvd_bits(7, 7); | |
4120 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | | |
4121 | gbpages_bit_rsvd; | |
4122 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; | |
4123 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
a0a64f50 XG |
4124 | rsvd_check->rsvd_bits_mask[1][3] = |
4125 | rsvd_check->rsvd_bits_mask[0][3]; | |
5b7f575c SC |
4126 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | |
4127 | gbpages_bit_rsvd | | |
4128 | rsvd_bits(13, 29); | |
4129 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4130 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4131 | rsvd_check->rsvd_bits_mask[1][0] = |
4132 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4133 | break; |
4134 | } | |
4135 | } | |
4136 | ||
6dc98b86 XG |
4137 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4138 | struct kvm_mmu *context) | |
4139 | { | |
4140 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
5b7f575c SC |
4141 | vcpu->arch.reserved_gpa_bits, |
4142 | context->root_level, context->nx, | |
d6321d49 | 4143 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
23493d0a SC |
4144 | is_pse(vcpu), |
4145 | guest_cpuid_is_amd_or_hygon(vcpu)); | |
6dc98b86 XG |
4146 | } |
4147 | ||
81b8eebb XG |
4148 | static void |
4149 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4150 | u64 pa_bits_rsvd, bool execonly) |
25d92081 | 4151 | { |
5b7f575c | 4152 | u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); |
951f9fd7 | 4153 | u64 bad_mt_xwr; |
25d92081 | 4154 | |
5b7f575c SC |
4155 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7); |
4156 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7); | |
4157 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6); | |
4158 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6); | |
4159 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
25d92081 YZ |
4160 | |
4161 | /* large page */ | |
855feb67 | 4162 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 | 4163 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
5b7f575c SC |
4164 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29); |
4165 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20); | |
a0a64f50 | 4166 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4167 | |
951f9fd7 PB |
4168 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4169 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4170 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4171 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4172 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4173 | if (!execonly) { | |
4174 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4175 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4176 | } |
951f9fd7 | 4177 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4178 | } |
4179 | ||
81b8eebb XG |
4180 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4181 | struct kvm_mmu *context, bool execonly) | |
4182 | { | |
4183 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
5b7f575c | 4184 | vcpu->arch.reserved_gpa_bits, execonly); |
81b8eebb XG |
4185 | } |
4186 | ||
6f8e65a6 SC |
4187 | static inline u64 reserved_hpa_bits(void) |
4188 | { | |
4189 | return rsvd_bits(shadow_phys_bits, 63); | |
4190 | } | |
4191 | ||
c258b62b XG |
4192 | /* |
4193 | * the page table on host is the shadow page table for the page | |
4194 | * table in guest or amd nested guest, its mmu features completely | |
4195 | * follow the features in guest. | |
4196 | */ | |
4197 | void | |
4198 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4199 | { | |
112022bd SC |
4200 | /* |
4201 | * KVM uses NX when TDP is disabled to handle a variety of scenarios, | |
4202 | * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and | |
4203 | * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0. | |
4204 | * The iTLB multi-hit workaround can be toggled at any time, so assume | |
4205 | * NX can be used by any non-nested shadow MMU to avoid having to reset | |
4206 | * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled. | |
4207 | */ | |
4208 | bool uses_nx = context->nx || !tdp_enabled || | |
36d9594d | 4209 | context->mmu_role.base.smep_andnot_wp; |
ea2800dd BS |
4210 | struct rsvd_bits_validate *shadow_zero_check; |
4211 | int i; | |
5f0b8199 | 4212 | |
6fec2144 PB |
4213 | /* |
4214 | * Passing "true" to the last argument is okay; it adds a check | |
4215 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4216 | */ | |
ea2800dd BS |
4217 | shadow_zero_check = &context->shadow_zero_check; |
4218 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
6f8e65a6 | 4219 | reserved_hpa_bits(), |
5f0b8199 | 4220 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4221 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4222 | is_pse(vcpu), true); | |
ea2800dd BS |
4223 | |
4224 | if (!shadow_me_mask) | |
4225 | return; | |
4226 | ||
4227 | for (i = context->shadow_root_level; --i >= 0;) { | |
4228 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4229 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4230 | } | |
4231 | ||
c258b62b XG |
4232 | } |
4233 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4234 | ||
6fec2144 PB |
4235 | static inline bool boot_cpu_is_amd(void) |
4236 | { | |
4237 | WARN_ON_ONCE(!tdp_enabled); | |
4238 | return shadow_x_mask == 0; | |
4239 | } | |
4240 | ||
c258b62b XG |
4241 | /* |
4242 | * the direct page table on host, use as much mmu features as | |
4243 | * possible, however, kvm currently does not do execution-protection. | |
4244 | */ | |
4245 | static void | |
4246 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4247 | struct kvm_mmu *context) | |
4248 | { | |
ea2800dd BS |
4249 | struct rsvd_bits_validate *shadow_zero_check; |
4250 | int i; | |
4251 | ||
4252 | shadow_zero_check = &context->shadow_zero_check; | |
4253 | ||
6fec2144 | 4254 | if (boot_cpu_is_amd()) |
ea2800dd | 4255 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
6f8e65a6 | 4256 | reserved_hpa_bits(), |
c258b62b | 4257 | context->shadow_root_level, false, |
b8291adc BP |
4258 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4259 | true, true); | |
c258b62b | 4260 | else |
ea2800dd | 4261 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
6f8e65a6 | 4262 | reserved_hpa_bits(), false); |
c258b62b | 4263 | |
ea2800dd BS |
4264 | if (!shadow_me_mask) |
4265 | return; | |
4266 | ||
4267 | for (i = context->shadow_root_level; --i >= 0;) { | |
4268 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4269 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4270 | } | |
c258b62b XG |
4271 | } |
4272 | ||
4273 | /* | |
4274 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4275 | * is the shadow page table for intel nested guest. | |
4276 | */ | |
4277 | static void | |
4278 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4279 | struct kvm_mmu *context, bool execonly) | |
4280 | { | |
4281 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
6f8e65a6 | 4282 | reserved_hpa_bits(), execonly); |
c258b62b XG |
4283 | } |
4284 | ||
09f037aa PB |
4285 | #define BYTE_MASK(access) \ |
4286 | ((1 & (access) ? 2 : 0) | \ | |
4287 | (2 & (access) ? 4 : 0) | \ | |
4288 | (3 & (access) ? 8 : 0) | \ | |
4289 | (4 & (access) ? 16 : 0) | \ | |
4290 | (5 & (access) ? 32 : 0) | \ | |
4291 | (6 & (access) ? 64 : 0) | \ | |
4292 | (7 & (access) ? 128 : 0)) | |
4293 | ||
4294 | ||
edc90b7d XG |
4295 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4296 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4297 | { |
09f037aa PB |
4298 | unsigned byte; |
4299 | ||
4300 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4301 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4302 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4303 | ||
4304 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4305 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4306 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4307 | |
97d64b78 | 4308 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4309 | unsigned pfec = byte << 1; |
4310 | ||
97ec8c06 | 4311 | /* |
09f037aa PB |
4312 | * Each "*f" variable has a 1 bit for each UWX value |
4313 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4314 | */ |
97d64b78 | 4315 | |
09f037aa | 4316 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4317 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4318 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4319 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4320 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4321 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4322 | /* Faults from kernel mode fetches of user pages */ |
4323 | u8 smepf = 0; | |
4324 | /* Faults from kernel mode accesses of user pages */ | |
4325 | u8 smapf = 0; | |
4326 | ||
4327 | if (!ept) { | |
4328 | /* Faults from kernel mode accesses to user pages */ | |
4329 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4330 | ||
4331 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4332 | if (!mmu->nx) | |
4333 | ff = 0; | |
4334 | ||
4335 | /* Allow supervisor writes if !cr0.wp */ | |
4336 | if (!cr0_wp) | |
4337 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4338 | ||
4339 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4340 | if (cr4_smep) | |
4341 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4342 | ||
4343 | /* | |
4344 | * SMAP:kernel-mode data accesses from user-mode | |
4345 | * mappings should fault. A fault is considered | |
4346 | * as a SMAP violation if all of the following | |
39337ad1 | 4347 | * conditions are true: |
09f037aa PB |
4348 | * - X86_CR4_SMAP is set in CR4 |
4349 | * - A user page is accessed | |
4350 | * - The access is not a fetch | |
4351 | * - Page fault in kernel mode | |
4352 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4353 | * | |
4354 | * Here, we cover the first three conditions. | |
4355 | * The fourth is computed dynamically in permission_fault(); | |
4356 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4357 | * *not* subject to SMAP restrictions. | |
4358 | */ | |
4359 | if (cr4_smap) | |
4360 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4361 | } |
09f037aa PB |
4362 | |
4363 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4364 | } |
4365 | } | |
4366 | ||
2d344105 HH |
4367 | /* |
4368 | * PKU is an additional mechanism by which the paging controls access to | |
4369 | * user-mode addresses based on the value in the PKRU register. Protection | |
4370 | * key violations are reported through a bit in the page fault error code. | |
4371 | * Unlike other bits of the error code, the PK bit is not known at the | |
4372 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4373 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4374 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4375 | * | |
4376 | * In particular the following conditions come from the error code, the | |
4377 | * page tables and the machine state: | |
4378 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4379 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4380 | * - PK is always zero if U=0 in the page tables | |
4381 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4382 | * | |
4383 | * The PKRU bitmask caches the result of these four conditions. The error | |
4384 | * code (minus the P bit) and the page table's U bit form an index into the | |
4385 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4386 | * with the two bits of the PKRU register corresponding to the protection key. | |
4387 | * For the first three conditions above the bits will be 00, thus masking | |
4388 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4389 | * only will be masked away. | |
4390 | */ | |
4391 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4392 | bool ept) | |
4393 | { | |
4394 | unsigned bit; | |
4395 | bool wp; | |
4396 | ||
4397 | if (ept) { | |
4398 | mmu->pkru_mask = 0; | |
4399 | return; | |
4400 | } | |
4401 | ||
4402 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4403 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4404 | mmu->pkru_mask = 0; | |
4405 | return; | |
4406 | } | |
4407 | ||
4408 | wp = is_write_protection(vcpu); | |
4409 | ||
4410 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4411 | unsigned pfec, pkey_bits; | |
4412 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4413 | ||
4414 | pfec = bit << 1; | |
4415 | ff = pfec & PFERR_FETCH_MASK; | |
4416 | uf = pfec & PFERR_USER_MASK; | |
4417 | wf = pfec & PFERR_WRITE_MASK; | |
4418 | ||
4419 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4420 | pte_user = pfec & PFERR_RSVD_MASK; | |
4421 | ||
4422 | /* | |
4423 | * Only need to check the access which is not an | |
4424 | * instruction fetch and is to a user page. | |
4425 | */ | |
4426 | check_pkey = (!ff && pte_user); | |
4427 | /* | |
4428 | * write access is controlled by PKRU if it is a | |
4429 | * user access or CR0.WP = 1. | |
4430 | */ | |
4431 | check_write = check_pkey && wf && (uf || wp); | |
4432 | ||
4433 | /* PKRU.AD stops both read and write access. */ | |
4434 | pkey_bits = !!check_pkey; | |
4435 | /* PKRU.WD stops write access. */ | |
4436 | pkey_bits |= (!!check_write) << 1; | |
4437 | ||
4438 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4439 | } | |
4440 | } | |
4441 | ||
6bb69c9b | 4442 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4443 | { |
6bb69c9b PB |
4444 | unsigned root_level = mmu->root_level; |
4445 | ||
4446 | mmu->last_nonleaf_level = root_level; | |
4447 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4448 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4449 | } |
4450 | ||
8a3c1a33 PB |
4451 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4452 | struct kvm_mmu *context, | |
4453 | int level) | |
6aa8b732 | 4454 | { |
2d48a985 | 4455 | context->nx = is_nx(vcpu); |
4d6931c3 | 4456 | context->root_level = level; |
2d48a985 | 4457 | |
4d6931c3 | 4458 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4459 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4460 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4461 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4462 | |
fa4a2c08 | 4463 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4464 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4465 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4466 | context->sync_page = paging64_sync_page; |
a7052897 | 4467 | context->invlpg = paging64_invlpg; |
17ac10ad | 4468 | context->shadow_root_level = level; |
c5a78f2b | 4469 | context->direct_map = false; |
6aa8b732 AK |
4470 | } |
4471 | ||
8a3c1a33 PB |
4472 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4473 | struct kvm_mmu *context) | |
17ac10ad | 4474 | { |
855feb67 YZ |
4475 | int root_level = is_la57_mode(vcpu) ? |
4476 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4477 | ||
4478 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4479 | } |
4480 | ||
8a3c1a33 PB |
4481 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4482 | struct kvm_mmu *context) | |
6aa8b732 | 4483 | { |
2d48a985 | 4484 | context->nx = false; |
4d6931c3 | 4485 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4486 | |
4d6931c3 | 4487 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4488 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4489 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4490 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4491 | |
6aa8b732 | 4492 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4493 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4494 | context->sync_page = paging32_sync_page; |
a7052897 | 4495 | context->invlpg = paging32_invlpg; |
6aa8b732 | 4496 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4497 | context->direct_map = false; |
6aa8b732 AK |
4498 | } |
4499 | ||
8a3c1a33 PB |
4500 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4501 | struct kvm_mmu *context) | |
6aa8b732 | 4502 | { |
8a3c1a33 | 4503 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4504 | } |
4505 | ||
a336282d VK |
4506 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4507 | { | |
4508 | union kvm_mmu_extended_role ext = {0}; | |
4509 | ||
7dcd5755 | 4510 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4511 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4512 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4513 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4514 | ext.cr4_pse = !!is_pse(vcpu); | |
4515 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
f71a53d1 | 4516 | ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57); |
a336282d VK |
4517 | |
4518 | ext.valid = 1; | |
4519 | ||
4520 | return ext; | |
4521 | } | |
4522 | ||
7dcd5755 VK |
4523 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4524 | bool base_only) | |
4525 | { | |
4526 | union kvm_mmu_role role = {0}; | |
4527 | ||
4528 | role.base.access = ACC_ALL; | |
4529 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4530 | role.base.cr0_wp = is_write_protection(vcpu); |
4531 | role.base.smm = is_smm(vcpu); | |
4532 | role.base.guest_mode = is_guest_mode(vcpu); | |
4533 | ||
4534 | if (base_only) | |
4535 | return role; | |
4536 | ||
4537 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4538 | ||
4539 | return role; | |
4540 | } | |
4541 | ||
d468d94b SC |
4542 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4543 | { | |
4544 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4545 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4546 | return 4; |
4547 | ||
83013059 | 4548 | return max_tdp_level; |
d468d94b SC |
4549 | } |
4550 | ||
7dcd5755 VK |
4551 | static union kvm_mmu_role |
4552 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4553 | { |
7dcd5755 | 4554 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4555 | |
7dcd5755 | 4556 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4557 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4558 | role.base.direct = true; |
47c42e6b | 4559 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4560 | |
4561 | return role; | |
4562 | } | |
4563 | ||
8a3c1a33 | 4564 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4565 | { |
8c008659 | 4566 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
7dcd5755 VK |
4567 | union kvm_mmu_role new_role = |
4568 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4569 | |
7dcd5755 VK |
4570 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4571 | return; | |
4572 | ||
4573 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4574 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4575 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4576 | context->invlpg = NULL; |
d468d94b | 4577 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4578 | context->direct_map = true; |
d8dd54e0 | 4579 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4580 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4581 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4582 | |
4583 | if (!is_paging(vcpu)) { | |
2d48a985 | 4584 | context->nx = false; |
fb72d167 JR |
4585 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4586 | context->root_level = 0; | |
4587 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4588 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4589 | context->root_level = is_la57_mode(vcpu) ? |
4590 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4591 | reset_rsvds_bits_mask(vcpu, context); |
4592 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4593 | } else if (is_pae(vcpu)) { |
2d48a985 | 4594 | context->nx = is_nx(vcpu); |
fb72d167 | 4595 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4596 | reset_rsvds_bits_mask(vcpu, context); |
4597 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4598 | } else { |
2d48a985 | 4599 | context->nx = false; |
fb72d167 | 4600 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4601 | reset_rsvds_bits_mask(vcpu, context); |
4602 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4603 | } |
4604 | ||
25d92081 | 4605 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4606 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4607 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4608 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4609 | } |
4610 | ||
7dcd5755 | 4611 | static union kvm_mmu_role |
59505b55 | 4612 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only) |
7dcd5755 VK |
4613 | { |
4614 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4615 | ||
4616 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4617 | !is_write_protection(vcpu); | |
4618 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4619 | !is_write_protection(vcpu); | |
47c42e6b | 4620 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 | 4621 | |
59505b55 SC |
4622 | return role; |
4623 | } | |
4624 | ||
4625 | static union kvm_mmu_role | |
4626 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4627 | { | |
4628 | union kvm_mmu_role role = | |
4629 | kvm_calc_shadow_root_page_role_common(vcpu, base_only); | |
4630 | ||
4631 | role.base.direct = !is_paging(vcpu); | |
4632 | ||
9fa72119 | 4633 | if (!is_long_mode(vcpu)) |
7dcd5755 | 4634 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4635 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4636 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4637 | else |
7dcd5755 | 4638 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4639 | |
4640 | return role; | |
4641 | } | |
4642 | ||
8c008659 PB |
4643 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
4644 | u32 cr0, u32 cr4, u32 efer, | |
4645 | union kvm_mmu_role new_role) | |
9fa72119 | 4646 | { |
929d1cfa | 4647 | if (!(cr0 & X86_CR0_PG)) |
8a3c1a33 | 4648 | nonpaging_init_context(vcpu, context); |
929d1cfa | 4649 | else if (efer & EFER_LMA) |
8a3c1a33 | 4650 | paging64_init_context(vcpu, context); |
929d1cfa | 4651 | else if (cr4 & X86_CR4_PAE) |
8a3c1a33 | 4652 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4653 | else |
8a3c1a33 | 4654 | paging32_init_context(vcpu, context); |
a770f6f2 | 4655 | |
7dcd5755 | 4656 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4657 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4658 | } |
0f04a2ac VK |
4659 | |
4660 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer) | |
4661 | { | |
8c008659 | 4662 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac VK |
4663 | union kvm_mmu_role new_role = |
4664 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4665 | ||
4666 | if (new_role.as_u64 != context->mmu_role.as_u64) | |
8c008659 | 4667 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4668 | } |
4669 | ||
59505b55 SC |
4670 | static union kvm_mmu_role |
4671 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu) | |
4672 | { | |
4673 | union kvm_mmu_role role = | |
4674 | kvm_calc_shadow_root_page_role_common(vcpu, false); | |
4675 | ||
4676 | role.base.direct = false; | |
d468d94b | 4677 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4678 | |
4679 | return role; | |
4680 | } | |
4681 | ||
0f04a2ac VK |
4682 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer, |
4683 | gpa_t nested_cr3) | |
4684 | { | |
8c008659 | 4685 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
59505b55 | 4686 | union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu); |
0f04a2ac | 4687 | |
b5129100 | 4688 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base); |
a506fdd2 | 4689 | |
a3322d5c | 4690 | if (new_role.as_u64 != context->mmu_role.as_u64) { |
8c008659 | 4691 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
a3322d5c SC |
4692 | |
4693 | /* | |
4694 | * Override the level set by the common init helper, nested TDP | |
4695 | * always uses the host's TDP configuration. | |
4696 | */ | |
4697 | context->shadow_root_level = new_role.base.level; | |
4698 | } | |
0f04a2ac VK |
4699 | } |
4700 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4701 | |
a336282d VK |
4702 | static union kvm_mmu_role |
4703 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4704 | bool execonly, u8 level) |
9fa72119 | 4705 | { |
552c69b1 | 4706 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4707 | |
47c42e6b SC |
4708 | /* SMM flag is inherited from root_mmu */ |
4709 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4710 | |
bb1fcc70 | 4711 | role.base.level = level; |
47c42e6b | 4712 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4713 | role.base.direct = false; |
4714 | role.base.ad_disabled = !accessed_dirty; | |
4715 | role.base.guest_mode = true; | |
4716 | role.base.access = ACC_ALL; | |
9fa72119 | 4717 | |
552c69b1 | 4718 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 4719 | role.ext.execonly = execonly; |
9fa72119 JS |
4720 | |
4721 | return role; | |
4722 | } | |
4723 | ||
ae1e2d10 | 4724 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4725 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4726 | { |
8c008659 | 4727 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4728 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4729 | union kvm_mmu_role new_role = |
4730 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4731 | execonly, level); |
a336282d | 4732 | |
b5129100 | 4733 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base); |
a336282d | 4734 | |
a336282d VK |
4735 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4736 | return; | |
ad896af0 | 4737 | |
bb1fcc70 | 4738 | context->shadow_root_level = level; |
155a97a3 NHE |
4739 | |
4740 | context->nx = true; | |
ae1e2d10 | 4741 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4742 | context->page_fault = ept_page_fault; |
4743 | context->gva_to_gpa = ept_gva_to_gpa; | |
4744 | context->sync_page = ept_sync_page; | |
4745 | context->invlpg = ept_invlpg; | |
bb1fcc70 | 4746 | context->root_level = level; |
155a97a3 | 4747 | context->direct_map = false; |
a336282d | 4748 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4749 | |
155a97a3 | 4750 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4751 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4752 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4753 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4754 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4755 | } |
4756 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4757 | ||
8a3c1a33 | 4758 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4759 | { |
8c008659 | 4760 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
ad896af0 | 4761 | |
929d1cfa PB |
4762 | kvm_init_shadow_mmu(vcpu, |
4763 | kvm_read_cr0_bits(vcpu, X86_CR0_PG), | |
4764 | kvm_read_cr4_bits(vcpu, X86_CR4_PAE), | |
4765 | vcpu->arch.efer); | |
4766 | ||
d8dd54e0 | 4767 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4768 | context->get_pdptr = kvm_pdptr_read; |
4769 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4770 | } |
4771 | ||
654430ef SC |
4772 | static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu) |
4773 | { | |
4774 | union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false); | |
4775 | ||
4776 | /* | |
4777 | * Nested MMUs are used only for walking L2's gva->gpa, they never have | |
4778 | * shadow pages of their own and so "direct" has no meaning. Set it | |
4779 | * to "true" to try to detect bogus usage of the nested MMU. | |
4780 | */ | |
4781 | role.base.direct = true; | |
4782 | ||
4783 | if (!is_paging(vcpu)) | |
4784 | role.base.level = 0; | |
4785 | else if (is_long_mode(vcpu)) | |
4786 | role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL : | |
4787 | PT64_ROOT_4LEVEL; | |
4788 | else if (is_pae(vcpu)) | |
4789 | role.base.level = PT32E_ROOT_LEVEL; | |
4790 | else | |
4791 | role.base.level = PT32_ROOT_LEVEL; | |
4792 | ||
4793 | return role; | |
4794 | } | |
4795 | ||
8a3c1a33 | 4796 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4797 | { |
654430ef | 4798 | union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu); |
02f59dc9 JR |
4799 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4800 | ||
bf627a92 VK |
4801 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4802 | return; | |
4803 | ||
4804 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4805 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4806 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4807 | g_context->inject_page_fault = kvm_inject_page_fault; |
4808 | ||
5efac074 PB |
4809 | /* |
4810 | * L2 page tables are never shadowed, so there is no need to sync | |
4811 | * SPTEs. | |
4812 | */ | |
4813 | g_context->invlpg = NULL; | |
4814 | ||
02f59dc9 | 4815 | /* |
44dd3ffa | 4816 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4817 | * L1's nested page tables (e.g. EPT12). The nested translation |
4818 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4819 | * L2's page tables as the first level of translation and L1's | |
4820 | * nested page tables as the second level of translation. Basically | |
4821 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4822 | */ |
4823 | if (!is_paging(vcpu)) { | |
2d48a985 | 4824 | g_context->nx = false; |
02f59dc9 JR |
4825 | g_context->root_level = 0; |
4826 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4827 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4828 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4829 | g_context->root_level = is_la57_mode(vcpu) ? |
4830 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4831 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4832 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4833 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4834 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4835 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4836 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4837 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4838 | } else { | |
2d48a985 | 4839 | g_context->nx = false; |
02f59dc9 | 4840 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4841 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4842 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4843 | } | |
4844 | ||
25d92081 | 4845 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4846 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4847 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4848 | } |
4849 | ||
c9060662 | 4850 | void kvm_init_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4851 | { |
02f59dc9 | 4852 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4853 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4854 | else if (tdp_enabled) |
e0c6db3e | 4855 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4856 | else |
e0c6db3e | 4857 | init_kvm_softmmu(vcpu); |
fb72d167 | 4858 | } |
1c53da3f | 4859 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4860 | |
9fa72119 JS |
4861 | static union kvm_mmu_page_role |
4862 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4863 | { | |
7dcd5755 VK |
4864 | union kvm_mmu_role role; |
4865 | ||
9fa72119 | 4866 | if (tdp_enabled) |
7dcd5755 | 4867 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 4868 | else |
7dcd5755 VK |
4869 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
4870 | ||
4871 | return role.base; | |
9fa72119 | 4872 | } |
fb72d167 | 4873 | |
49c6f875 SC |
4874 | void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu) |
4875 | { | |
4876 | /* | |
4877 | * Invalidate all MMU roles to force them to reinitialize as CPUID | |
4878 | * information is factored into reserved bit calculations. | |
4879 | */ | |
4880 | vcpu->arch.root_mmu.mmu_role.ext.valid = 0; | |
4881 | vcpu->arch.guest_mmu.mmu_role.ext.valid = 0; | |
4882 | vcpu->arch.nested_mmu.mmu_role.ext.valid = 0; | |
4883 | kvm_mmu_reset_context(vcpu); | |
63f5a190 SC |
4884 | |
4885 | /* | |
4886 | * KVM does not correctly handle changing guest CPUID after KVM_RUN, as | |
4887 | * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't | |
4888 | * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page | |
4889 | * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise | |
4890 | * sweep the problem under the rug. | |
4891 | * | |
4892 | * KVM's horrific CPUID ABI makes the problem all but impossible to | |
4893 | * solve, as correctly handling multiple vCPU models (with respect to | |
4894 | * paging and physical address properties) in a single VM would require | |
4895 | * tracking all relevant CPUID information in kvm_mmu_page_role. That | |
4896 | * is very undesirable as it would double the memory requirements for | |
4897 | * gfn_track (see struct kvm_mmu_page_role comments), and in practice | |
4898 | * no sane VMM mucks with the core vCPU model on the fly. | |
4899 | */ | |
4900 | if (vcpu->arch.last_vmentry_cpu != -1) { | |
4901 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n"); | |
4902 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n"); | |
4903 | } | |
49c6f875 SC |
4904 | } |
4905 | ||
8a3c1a33 | 4906 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4907 | { |
95f93af4 | 4908 | kvm_mmu_unload(vcpu); |
c9060662 | 4909 | kvm_init_mmu(vcpu); |
17c3ba9d | 4910 | } |
8668a3c4 | 4911 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4912 | |
4913 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4914 | { |
714b93da AK |
4915 | int r; |
4916 | ||
378f5cd6 | 4917 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
4918 | if (r) |
4919 | goto out; | |
748e52b9 | 4920 | r = mmu_alloc_special_roots(vcpu); |
17c3ba9d AK |
4921 | if (r) |
4922 | goto out; | |
4a38162e | 4923 | if (vcpu->arch.mmu->direct_map) |
6e6ec584 SC |
4924 | r = mmu_alloc_direct_roots(vcpu); |
4925 | else | |
4926 | r = mmu_alloc_shadow_roots(vcpu); | |
8986ecc0 MT |
4927 | if (r) |
4928 | goto out; | |
a91f387b SC |
4929 | |
4930 | kvm_mmu_sync_roots(vcpu); | |
4931 | ||
727a7e27 | 4932 | kvm_mmu_load_pgd(vcpu); |
b3646477 | 4933 | static_call(kvm_x86_tlb_flush_current)(vcpu); |
714b93da AK |
4934 | out: |
4935 | return r; | |
6aa8b732 | 4936 | } |
17c3ba9d AK |
4937 | |
4938 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4939 | { | |
14c07ad8 VK |
4940 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
4941 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
4942 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
4943 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 4944 | } |
6aa8b732 | 4945 | |
79539cec AK |
4946 | static bool need_remote_flush(u64 old, u64 new) |
4947 | { | |
4948 | if (!is_shadow_present_pte(old)) | |
4949 | return false; | |
4950 | if (!is_shadow_present_pte(new)) | |
4951 | return true; | |
4952 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4953 | return true; | |
53166229 GN |
4954 | old ^= shadow_nx_mask; |
4955 | new ^= shadow_nx_mask; | |
79539cec AK |
4956 | return (old & ~new & PT64_PERM_MASK) != 0; |
4957 | } | |
4958 | ||
889e5cbc | 4959 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 4960 | int *bytes) |
da4a00f0 | 4961 | { |
0e0fee5c | 4962 | u64 gentry = 0; |
889e5cbc | 4963 | int r; |
72016f3a | 4964 | |
72016f3a AK |
4965 | /* |
4966 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4967 | * as the current vcpu paging mode since we update the sptes only |
4968 | * when they have the same mode. | |
72016f3a | 4969 | */ |
889e5cbc | 4970 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4971 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4972 | *gpa &= ~(gpa_t)7; |
4973 | *bytes = 8; | |
08e850c6 AK |
4974 | } |
4975 | ||
0e0fee5c JS |
4976 | if (*bytes == 4 || *bytes == 8) { |
4977 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
4978 | if (r) | |
4979 | gentry = 0; | |
72016f3a AK |
4980 | } |
4981 | ||
889e5cbc XG |
4982 | return gentry; |
4983 | } | |
4984 | ||
4985 | /* | |
4986 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4987 | * or we may be forking, in which case it is better to unmap the page. | |
4988 | */ | |
a138fe75 | 4989 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4990 | { |
a30f47cb XG |
4991 | /* |
4992 | * Skip write-flooding detected for the sp whose level is 1, because | |
4993 | * it can become unsync, then the guest page is not write-protected. | |
4994 | */ | |
3bae0459 | 4995 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 4996 | return false; |
3246af0e | 4997 | |
e5691a81 XG |
4998 | atomic_inc(&sp->write_flooding_count); |
4999 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5000 | } |
5001 | ||
5002 | /* | |
5003 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5004 | * indicate a page is not used as a page table. | |
5005 | */ | |
5006 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5007 | int bytes) | |
5008 | { | |
5009 | unsigned offset, pte_size, misaligned; | |
5010 | ||
5011 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5012 | gpa, bytes, sp->role.word); | |
5013 | ||
5014 | offset = offset_in_page(gpa); | |
47c42e6b | 5015 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5016 | |
5017 | /* | |
5018 | * Sometimes, the OS only writes the last one bytes to update status | |
5019 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5020 | */ | |
5021 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5022 | return false; | |
5023 | ||
889e5cbc XG |
5024 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5025 | misaligned |= bytes < 4; | |
5026 | ||
5027 | return misaligned; | |
5028 | } | |
5029 | ||
5030 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5031 | { | |
5032 | unsigned page_offset, quadrant; | |
5033 | u64 *spte; | |
5034 | int level; | |
5035 | ||
5036 | page_offset = offset_in_page(gpa); | |
5037 | level = sp->role.level; | |
5038 | *nspte = 1; | |
47c42e6b | 5039 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5040 | page_offset <<= 1; /* 32->64 */ |
5041 | /* | |
5042 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5043 | * only 2MB. So we need to double the offset again | |
5044 | * and zap two pdes instead of one. | |
5045 | */ | |
5046 | if (level == PT32_ROOT_LEVEL) { | |
5047 | page_offset &= ~7; /* kill rounding error */ | |
5048 | page_offset <<= 1; | |
5049 | *nspte = 2; | |
5050 | } | |
5051 | quadrant = page_offset >> PAGE_SHIFT; | |
5052 | page_offset &= ~PAGE_MASK; | |
5053 | if (quadrant != sp->role.quadrant) | |
5054 | return NULL; | |
5055 | } | |
5056 | ||
5057 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5058 | return spte; | |
5059 | } | |
5060 | ||
13d268ca | 5061 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5062 | const u8 *new, int bytes, |
5063 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5064 | { |
5065 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5066 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5067 | LIST_HEAD(invalid_list); |
5068 | u64 entry, gentry, *spte; | |
5069 | int npte; | |
b8c67b7a | 5070 | bool remote_flush, local_flush; |
889e5cbc XG |
5071 | |
5072 | /* | |
5073 | * If we don't have indirect shadow pages, it means no page is | |
5074 | * write-protected, so we can exit simply. | |
5075 | */ | |
6aa7de05 | 5076 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5077 | return; |
5078 | ||
b8c67b7a | 5079 | remote_flush = local_flush = false; |
889e5cbc XG |
5080 | |
5081 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5082 | ||
889e5cbc XG |
5083 | /* |
5084 | * No need to care whether allocation memory is successful | |
d9f6e12f | 5085 | * or not since pte prefetch is skipped if it does not have |
889e5cbc XG |
5086 | * enough objects in the cache. |
5087 | */ | |
378f5cd6 | 5088 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc | 5089 | |
531810ca | 5090 | write_lock(&vcpu->kvm->mmu_lock); |
0e0fee5c JS |
5091 | |
5092 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5093 | ||
889e5cbc | 5094 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5095 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5096 | |
b67bfe0d | 5097 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5098 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5099 | detect_write_flooding(sp)) { |
b8c67b7a | 5100 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5101 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5102 | continue; |
5103 | } | |
889e5cbc XG |
5104 | |
5105 | spte = get_written_sptes(sp, gpa, &npte); | |
5106 | if (!spte) | |
5107 | continue; | |
5108 | ||
0671a8e7 | 5109 | local_flush = true; |
ac1b714e | 5110 | while (npte--) { |
79539cec | 5111 | entry = *spte; |
2de4085c | 5112 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
c5e2184d SC |
5113 | if (gentry && sp->role.level != PG_LEVEL_4K) |
5114 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
9bb4f6b1 | 5115 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5116 | remote_flush = true; |
ac1b714e | 5117 | ++spte; |
9b7a0325 | 5118 | } |
9b7a0325 | 5119 | } |
b8c67b7a | 5120 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5121 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
531810ca | 5122 | write_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5123 | } |
5124 | ||
736c291c | 5125 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5126 | void *insn, int insn_len) |
3067714c | 5127 | { |
92daa48b | 5128 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5129 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5130 | |
6948199a | 5131 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5132 | return RET_PF_RETRY; |
5133 | ||
9b8ebbdb | 5134 | r = RET_PF_INVALID; |
e9ee956e | 5135 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5136 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5137 | if (r == RET_PF_EMULATE) |
e9ee956e | 5138 | goto emulate; |
e9ee956e | 5139 | } |
3067714c | 5140 | |
9b8ebbdb | 5141 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5142 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5143 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5144 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5145 | return -EIO; | |
9b8ebbdb PB |
5146 | } |
5147 | ||
3067714c | 5148 | if (r < 0) |
e9ee956e | 5149 | return r; |
83a2ba4c SC |
5150 | if (r != RET_PF_EMULATE) |
5151 | return 1; | |
3067714c | 5152 | |
14727754 TL |
5153 | /* |
5154 | * Before emulating the instruction, check if the error code | |
5155 | * was due to a RO violation while translating the guest page. | |
5156 | * This can occur when using nested virtualization with nested | |
5157 | * paging in both guests. If true, we simply unprotect the page | |
5158 | * and resume the guest. | |
14727754 | 5159 | */ |
44dd3ffa | 5160 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5161 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5162 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5163 | return 1; |
5164 | } | |
5165 | ||
472faffa SC |
5166 | /* |
5167 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5168 | * optimistically try to just unprotect the page and let the processor | |
5169 | * re-execute the instruction that caused the page fault. Do not allow | |
5170 | * retrying MMIO emulation, as it's not only pointless but could also | |
5171 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5172 | * faulting on the non-existent MMIO address. Retrying an instruction |
5173 | * from a nested guest is also pointless and dangerous as we are only | |
5174 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5175 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5176 | */ |
736c291c | 5177 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5178 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5179 | emulate: |
736c291c | 5180 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5181 | insn_len); |
3067714c AK |
5182 | } |
5183 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5184 | ||
5efac074 PB |
5185 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5186 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5187 | { |
b94742c9 | 5188 | int i; |
7eb77e9f | 5189 | |
5efac074 PB |
5190 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5191 | if (mmu != &vcpu->arch.guest_mmu) { | |
5192 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5193 | if (is_noncanonical_address(gva, vcpu)) | |
5194 | return; | |
5195 | ||
b3646477 | 5196 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
5efac074 PB |
5197 | } |
5198 | ||
5199 | if (!mmu->invlpg) | |
faff8758 JS |
5200 | return; |
5201 | ||
5efac074 PB |
5202 | if (root_hpa == INVALID_PAGE) { |
5203 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5204 | |
5efac074 PB |
5205 | /* |
5206 | * INVLPG is required to invalidate any global mappings for the VA, | |
5207 | * irrespective of PCID. Since it would take us roughly similar amount | |
5208 | * of work to determine whether any of the prev_root mappings of the VA | |
5209 | * is marked global, or to just sync it blindly, so we might as well | |
5210 | * just always sync it. | |
5211 | * | |
5212 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5213 | * synced when switching to that cr3, so nothing needs to be done here | |
5214 | * for them. | |
5215 | */ | |
5216 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5217 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5218 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5219 | } else { | |
5220 | mmu->invlpg(vcpu, gva, root_hpa); | |
5221 | } | |
5222 | } | |
956bf353 | 5223 | |
5efac074 PB |
5224 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5225 | { | |
5226 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5227 | ++vcpu->stat.invlpg; |
5228 | } | |
5229 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5230 | ||
5efac074 | 5231 | |
eb4b248e JS |
5232 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5233 | { | |
44dd3ffa | 5234 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5235 | bool tlb_flush = false; |
b94742c9 | 5236 | uint i; |
eb4b248e JS |
5237 | |
5238 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5239 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5240 | tlb_flush = true; |
eb4b248e JS |
5241 | } |
5242 | ||
b94742c9 JS |
5243 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5244 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5245 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5246 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5247 | tlb_flush = true; | |
5248 | } | |
956bf353 | 5249 | } |
ade61e28 | 5250 | |
faff8758 | 5251 | if (tlb_flush) |
b3646477 | 5252 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
faff8758 | 5253 | |
eb4b248e JS |
5254 | ++vcpu->stat.invlpg; |
5255 | ||
5256 | /* | |
b94742c9 JS |
5257 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5258 | * synced when switching to that cr3, so nothing needs to be done here | |
5259 | * for them. | |
eb4b248e JS |
5260 | */ |
5261 | } | |
eb4b248e | 5262 | |
83013059 SC |
5263 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5264 | int tdp_huge_page_level) | |
18552672 | 5265 | { |
bde77235 | 5266 | tdp_enabled = enable_tdp; |
83013059 | 5267 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5268 | |
5269 | /* | |
1d92d2e8 | 5270 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5271 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5272 | * the kernel is not. But, KVM never creates a page size greater than | |
5273 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5274 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5275 | */ | |
5276 | if (tdp_enabled) | |
1d92d2e8 | 5277 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5278 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5279 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5280 | else |
1d92d2e8 | 5281 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5282 | } |
bde77235 | 5283 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5284 | |
5285 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
0a234f5d SC |
5286 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
5287 | struct kvm_memory_slot *slot); | |
85875a13 SC |
5288 | |
5289 | /* The caller should hold mmu-lock before calling this function. */ | |
5290 | static __always_inline bool | |
5291 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5292 | slot_level_handler fn, int start_level, int end_level, | |
1a61b7db SC |
5293 | gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield, |
5294 | bool flush) | |
85875a13 SC |
5295 | { |
5296 | struct slot_rmap_walk_iterator iterator; | |
85875a13 SC |
5297 | |
5298 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5299 | end_gfn, &iterator) { | |
5300 | if (iterator.rmap) | |
0a234f5d | 5301 | flush |= fn(kvm, iterator.rmap, memslot); |
85875a13 | 5302 | |
531810ca | 5303 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
302695a5 | 5304 | if (flush && flush_on_yield) { |
f285c633 BG |
5305 | kvm_flush_remote_tlbs_with_address(kvm, |
5306 | start_gfn, | |
5307 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5308 | flush = false; |
5309 | } | |
531810ca | 5310 | cond_resched_rwlock_write(&kvm->mmu_lock); |
85875a13 SC |
5311 | } |
5312 | } | |
5313 | ||
85875a13 SC |
5314 | return flush; |
5315 | } | |
5316 | ||
5317 | static __always_inline bool | |
5318 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5319 | slot_level_handler fn, int start_level, int end_level, | |
302695a5 | 5320 | bool flush_on_yield) |
85875a13 SC |
5321 | { |
5322 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5323 | end_level, memslot->base_gfn, | |
5324 | memslot->base_gfn + memslot->npages - 1, | |
1a61b7db | 5325 | flush_on_yield, false); |
85875a13 SC |
5326 | } |
5327 | ||
85875a13 SC |
5328 | static __always_inline bool |
5329 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
302695a5 | 5330 | slot_level_handler fn, bool flush_on_yield) |
85875a13 | 5331 | { |
3bae0459 | 5332 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
302695a5 | 5333 | PG_LEVEL_4K, flush_on_yield); |
85875a13 SC |
5334 | } |
5335 | ||
1cfff4d9 | 5336 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5337 | { |
4a98623d SC |
5338 | if (!tdp_enabled && mmu->pae_root) |
5339 | set_memory_encrypted((unsigned long)mmu->pae_root, 1); | |
1cfff4d9 | 5340 | free_page((unsigned long)mmu->pae_root); |
03ca4589 | 5341 | free_page((unsigned long)mmu->pml4_root); |
6aa8b732 AK |
5342 | } |
5343 | ||
04d28e37 | 5344 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5345 | { |
17ac10ad | 5346 | struct page *page; |
6aa8b732 AK |
5347 | int i; |
5348 | ||
04d28e37 SC |
5349 | mmu->root_hpa = INVALID_PAGE; |
5350 | mmu->root_pgd = 0; | |
5351 | mmu->translate_gpa = translate_gpa; | |
5352 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5353 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5354 | ||
17ac10ad | 5355 | /* |
b6b80c78 SC |
5356 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5357 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5358 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5359 | * x86_64. Therefore we need to allocate the PDP table in the first | |
04d45551 SC |
5360 | * 4GB of memory, which happens to fit the DMA32 zone. TDP paging |
5361 | * generally doesn't use PAE paging and can skip allocating the PDP | |
5362 | * table. The main exception, handled here, is SVM's 32-bit NPT. The | |
5363 | * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit | |
5364 | * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). | |
17ac10ad | 5365 | */ |
d468d94b | 5366 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5367 | return 0; |
5368 | ||
254272ce | 5369 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5370 | if (!page) |
d7fa6ab2 WY |
5371 | return -ENOMEM; |
5372 | ||
1cfff4d9 | 5373 | mmu->pae_root = page_address(page); |
4a98623d SC |
5374 | |
5375 | /* | |
5376 | * CR3 is only 32 bits when PAE paging is used, thus it's impossible to | |
5377 | * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so | |
5378 | * that KVM's writes and the CPU's reads get along. Note, this is | |
5379 | * only necessary when using shadow paging, as 64-bit NPT can get at | |
5380 | * the C-bit even when shadowing 32-bit NPT, and SME isn't supported | |
5381 | * by 32-bit kernels (when KVM itself uses 32-bit NPT). | |
5382 | */ | |
5383 | if (!tdp_enabled) | |
5384 | set_memory_decrypted((unsigned long)mmu->pae_root, 1); | |
5385 | else | |
5386 | WARN_ON_ONCE(shadow_me_mask); | |
5387 | ||
17ac10ad | 5388 | for (i = 0; i < 4; ++i) |
c834e5e4 | 5389 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
17ac10ad | 5390 | |
6aa8b732 | 5391 | return 0; |
6aa8b732 AK |
5392 | } |
5393 | ||
8018c27b | 5394 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5395 | { |
1cfff4d9 | 5396 | int ret; |
b94742c9 | 5397 | |
5962bfb7 | 5398 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5399 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5400 | ||
5962bfb7 | 5401 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5402 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5403 | |
96880883 SC |
5404 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5405 | ||
44dd3ffa VK |
5406 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5407 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5408 | |
14c07ad8 | 5409 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5410 | |
04d28e37 | 5411 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5412 | if (ret) |
5413 | return ret; | |
5414 | ||
04d28e37 | 5415 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5416 | if (ret) |
5417 | goto fail_allocate_root; | |
5418 | ||
5419 | return ret; | |
5420 | fail_allocate_root: | |
5421 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5422 | return ret; | |
6aa8b732 AK |
5423 | } |
5424 | ||
fbb158cb | 5425 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5426 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5427 | { | |
5428 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5429 | int nr_zapped, batch = 0; |
002c5f73 SC |
5430 | |
5431 | restart: | |
5432 | list_for_each_entry_safe_reverse(sp, node, | |
5433 | &kvm->arch.active_mmu_pages, link) { | |
5434 | /* | |
5435 | * No obsolete valid page exists before a newly created page | |
5436 | * since active_mmu_pages is a FIFO list. | |
5437 | */ | |
5438 | if (!is_obsolete_sp(kvm, sp)) | |
5439 | break; | |
5440 | ||
5441 | /* | |
f95eec9b SC |
5442 | * Invalid pages should never land back on the list of active |
5443 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5444 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5445 | */ |
f95eec9b | 5446 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5447 | continue; |
5448 | ||
4506ecf4 SC |
5449 | /* |
5450 | * No need to flush the TLB since we're only zapping shadow | |
5451 | * pages with an obsolete generation number and all vCPUS have | |
5452 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5453 | * be in active use by the guest. | |
5454 | */ | |
fbb158cb | 5455 | if (batch >= BATCH_ZAP_PAGES && |
531810ca | 5456 | cond_resched_rwlock_write(&kvm->mmu_lock)) { |
fbb158cb | 5457 | batch = 0; |
002c5f73 SC |
5458 | goto restart; |
5459 | } | |
5460 | ||
10605204 SC |
5461 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5462 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5463 | batch += nr_zapped; |
002c5f73 | 5464 | goto restart; |
fbb158cb | 5465 | } |
002c5f73 SC |
5466 | } |
5467 | ||
4506ecf4 SC |
5468 | /* |
5469 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5470 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5471 | * may reference the pages. | |
5472 | */ | |
10605204 | 5473 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5474 | } |
5475 | ||
5476 | /* | |
5477 | * Fast invalidate all shadow pages and use lock-break technique | |
5478 | * to zap obsolete pages. | |
5479 | * | |
5480 | * It's required when memslot is being deleted or VM is being | |
5481 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5482 | * not use any resource of the being-deleted slot or all slots | |
5483 | * after calling the function. | |
5484 | */ | |
5485 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5486 | { | |
ca333add SC |
5487 | lockdep_assert_held(&kvm->slots_lock); |
5488 | ||
531810ca | 5489 | write_lock(&kvm->mmu_lock); |
14a3c4f4 | 5490 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5491 | |
5492 | /* | |
5493 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5494 | * held for the entire duration of zapping obsolete pages, it's | |
5495 | * impossible for there to be multiple invalid generations associated | |
5496 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5497 | * one valid generation and (at most) one invalid generation. | |
5498 | */ | |
5499 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5500 | |
b7cccd39 BG |
5501 | /* In order to ensure all threads see this change when |
5502 | * handling the MMU reload signal, this must happen in the | |
5503 | * same critical section as kvm_reload_remote_mmus, and | |
5504 | * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages | |
5505 | * could drop the MMU lock and yield. | |
5506 | */ | |
5507 | if (is_tdp_mmu_enabled(kvm)) | |
5508 | kvm_tdp_mmu_invalidate_all_roots(kvm); | |
5509 | ||
4506ecf4 SC |
5510 | /* |
5511 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5512 | * Then all vcpus will switch to new shadow page table with the new | |
5513 | * mmu_valid_gen. | |
5514 | * | |
5515 | * Note: we need to do this under the protection of mmu_lock, | |
5516 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5517 | */ | |
5518 | kvm_reload_remote_mmus(kvm); | |
5519 | ||
002c5f73 | 5520 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 | 5521 | |
531810ca | 5522 | write_unlock(&kvm->mmu_lock); |
4c6654bd BG |
5523 | |
5524 | if (is_tdp_mmu_enabled(kvm)) { | |
5525 | read_lock(&kvm->mmu_lock); | |
5526 | kvm_tdp_mmu_zap_invalidated_roots(kvm); | |
5527 | read_unlock(&kvm->mmu_lock); | |
5528 | } | |
002c5f73 SC |
5529 | } |
5530 | ||
10605204 SC |
5531 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5532 | { | |
5533 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5534 | } | |
5535 | ||
b5f5fdca | 5536 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5537 | struct kvm_memory_slot *slot, |
5538 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5539 | { |
002c5f73 | 5540 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5541 | } |
5542 | ||
13d268ca | 5543 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5544 | { |
13d268ca | 5545 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5546 | |
d501f747 BG |
5547 | if (!kvm_mmu_init_tdp_mmu(kvm)) |
5548 | /* | |
5549 | * No smp_load/store wrappers needed here as we are in | |
5550 | * VM init and there cannot be any memslots / other threads | |
5551 | * accessing this struct kvm yet. | |
5552 | */ | |
5553 | kvm->arch.memslots_have_rmaps = true; | |
a2557408 | 5554 | |
13d268ca | 5555 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5556 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5557 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5558 | } |
5559 | ||
13d268ca | 5560 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5561 | { |
13d268ca | 5562 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5563 | |
13d268ca | 5564 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5565 | |
5566 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5567 | } |
5568 | ||
efdfe536 XG |
5569 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5570 | { | |
5571 | struct kvm_memslots *slots; | |
5572 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5573 | int i; |
1a61b7db | 5574 | bool flush = false; |
efdfe536 | 5575 | |
e2209710 BG |
5576 | if (kvm_memslots_have_rmaps(kvm)) { |
5577 | write_lock(&kvm->mmu_lock); | |
5578 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
5579 | slots = __kvm_memslots(kvm, i); | |
5580 | kvm_for_each_memslot(memslot, slots) { | |
5581 | gfn_t start, end; | |
5582 | ||
5583 | start = max(gfn_start, memslot->base_gfn); | |
5584 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5585 | if (start >= end) | |
5586 | continue; | |
efdfe536 | 5587 | |
e2209710 BG |
5588 | flush = slot_handle_level_range(kvm, memslot, |
5589 | kvm_zap_rmapp, PG_LEVEL_4K, | |
5590 | KVM_MAX_HUGEPAGE_LEVEL, start, | |
5591 | end - 1, true, flush); | |
5592 | } | |
9da0e4d5 | 5593 | } |
e2209710 BG |
5594 | if (flush) |
5595 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end); | |
5596 | write_unlock(&kvm->mmu_lock); | |
efdfe536 XG |
5597 | } |
5598 | ||
897218ff | 5599 | if (is_tdp_mmu_enabled(kvm)) { |
6103bc07 BG |
5600 | flush = false; |
5601 | ||
5602 | read_lock(&kvm->mmu_lock); | |
5603 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) | |
5604 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start, | |
5605 | gfn_end, flush, true); | |
faaf05b0 | 5606 | if (flush) |
6103bc07 BG |
5607 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, |
5608 | gfn_end); | |
faaf05b0 | 5609 | |
6103bc07 BG |
5610 | read_unlock(&kvm->mmu_lock); |
5611 | } | |
efdfe536 XG |
5612 | } |
5613 | ||
018aabb5 | 5614 | static bool slot_rmap_write_protect(struct kvm *kvm, |
0a234f5d SC |
5615 | struct kvm_rmap_head *rmap_head, |
5616 | struct kvm_memory_slot *slot) | |
d77aa73c | 5617 | { |
018aabb5 | 5618 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5619 | } |
5620 | ||
1c91cad4 | 5621 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5622 | struct kvm_memory_slot *memslot, |
5623 | int start_level) | |
6aa8b732 | 5624 | { |
e2209710 | 5625 | bool flush = false; |
6aa8b732 | 5626 | |
e2209710 BG |
5627 | if (kvm_memslots_have_rmaps(kvm)) { |
5628 | write_lock(&kvm->mmu_lock); | |
5629 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, | |
5630 | start_level, KVM_MAX_HUGEPAGE_LEVEL, | |
5631 | false); | |
5632 | write_unlock(&kvm->mmu_lock); | |
5633 | } | |
198c74f4 | 5634 | |
24ae4cfa BG |
5635 | if (is_tdp_mmu_enabled(kvm)) { |
5636 | read_lock(&kvm->mmu_lock); | |
5637 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level); | |
5638 | read_unlock(&kvm->mmu_lock); | |
5639 | } | |
5640 | ||
198c74f4 XG |
5641 | /* |
5642 | * We can flush all the TLBs out of the mmu lock without TLB | |
5643 | * corruption since we just change the spte from writable to | |
5644 | * readonly so that we only need to care the case of changing | |
5645 | * spte from present to present (changing the spte from present | |
5646 | * to nonpresent will flush all the TLBs immediately), in other | |
5647 | * words, the only case we care is mmu_spte_update() where we | |
5fc3424f SC |
5648 | * have checked Host-writable | MMU-writable instead of |
5649 | * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK | |
5650 | * anymore. | |
198c74f4 | 5651 | */ |
d91ffee9 | 5652 | if (flush) |
7f42aa76 | 5653 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5654 | } |
37a7d8b0 | 5655 | |
3ea3b7fa | 5656 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
0a234f5d SC |
5657 | struct kvm_rmap_head *rmap_head, |
5658 | struct kvm_memory_slot *slot) | |
3ea3b7fa WL |
5659 | { |
5660 | u64 *sptep; | |
5661 | struct rmap_iterator iter; | |
5662 | int need_tlb_flush = 0; | |
ba049e93 | 5663 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5664 | struct kvm_mmu_page *sp; |
5665 | ||
0d536790 | 5666 | restart: |
018aabb5 | 5667 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5668 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5669 | pfn = spte_to_pfn(*sptep); |
5670 | ||
5671 | /* | |
decf6333 XG |
5672 | * We cannot do huge page mapping for indirect shadow pages, |
5673 | * which are found on the last rmap (level = 1) when not using | |
5674 | * tdp; such shadow pages are synced with the page table in | |
5675 | * the guest, and the guest page table is using 4K page size | |
5676 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5677 | */ |
a78986aa | 5678 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
9eba50f8 SC |
5679 | sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn, |
5680 | pfn, PG_LEVEL_NUM)) { | |
e7912386 | 5681 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5682 | |
5683 | if (kvm_available_flush_tlb_with_range()) | |
5684 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5685 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5686 | else | |
5687 | need_tlb_flush = 1; | |
5688 | ||
0d536790 XG |
5689 | goto restart; |
5690 | } | |
3ea3b7fa WL |
5691 | } |
5692 | ||
5693 | return need_tlb_flush; | |
5694 | } | |
5695 | ||
5696 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5697 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5698 | { |
f36f3f28 | 5699 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
9eba50f8 | 5700 | struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot; |
31c65657 | 5701 | bool flush = false; |
9eba50f8 | 5702 | |
e2209710 BG |
5703 | if (kvm_memslots_have_rmaps(kvm)) { |
5704 | write_lock(&kvm->mmu_lock); | |
5705 | flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true); | |
5706 | if (flush) | |
5707 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5708 | write_unlock(&kvm->mmu_lock); | |
5709 | } | |
2db6f772 BG |
5710 | |
5711 | if (is_tdp_mmu_enabled(kvm)) { | |
2db6f772 BG |
5712 | read_lock(&kvm->mmu_lock); |
5713 | flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush); | |
5714 | if (flush) | |
5715 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5716 | read_unlock(&kvm->mmu_lock); | |
5717 | } | |
3ea3b7fa WL |
5718 | } |
5719 | ||
b3594ffb | 5720 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
6c9dd6d2 | 5721 | const struct kvm_memory_slot *memslot) |
b3594ffb SC |
5722 | { |
5723 | /* | |
7f42aa76 | 5724 | * All current use cases for flushing the TLBs for a specific memslot |
302695a5 | 5725 | * related to dirty logging, and many do the TLB flush out of mmu_lock. |
7f42aa76 SC |
5726 | * The interaction between the various operations on memslot must be |
5727 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5728 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5729 | */ |
5730 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5731 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5732 | memslot->npages); | |
b3594ffb SC |
5733 | } |
5734 | ||
f4b4b180 KH |
5735 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5736 | struct kvm_memory_slot *memslot) | |
5737 | { | |
e2209710 | 5738 | bool flush = false; |
f4b4b180 | 5739 | |
e2209710 BG |
5740 | if (kvm_memslots_have_rmaps(kvm)) { |
5741 | write_lock(&kvm->mmu_lock); | |
5742 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, | |
5743 | false); | |
5744 | write_unlock(&kvm->mmu_lock); | |
5745 | } | |
f4b4b180 | 5746 | |
24ae4cfa BG |
5747 | if (is_tdp_mmu_enabled(kvm)) { |
5748 | read_lock(&kvm->mmu_lock); | |
5749 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); | |
5750 | read_unlock(&kvm->mmu_lock); | |
5751 | } | |
5752 | ||
f4b4b180 KH |
5753 | /* |
5754 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5755 | * function is only used for dirty logging, in which case flushing TLB | |
5756 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5757 | * dirty_bitmap. | |
5758 | */ | |
5759 | if (flush) | |
7f42aa76 | 5760 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 | 5761 | } |
f4b4b180 | 5762 | |
92f58b5c | 5763 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5764 | { |
5765 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5766 | LIST_HEAD(invalid_list); |
83cdb568 | 5767 | int ign; |
5304b8d3 | 5768 | |
531810ca | 5769 | write_lock(&kvm->mmu_lock); |
5304b8d3 | 5770 | restart: |
8a674adc | 5771 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5772 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5773 | continue; |
92f58b5c | 5774 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5775 | goto restart; |
531810ca | 5776 | if (cond_resched_rwlock_write(&kvm->mmu_lock)) |
5304b8d3 XG |
5777 | goto restart; |
5778 | } | |
5779 | ||
4771450c | 5780 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 | 5781 | |
897218ff | 5782 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5783 | kvm_tdp_mmu_zap_all(kvm); |
5784 | ||
531810ca | 5785 | write_unlock(&kvm->mmu_lock); |
5304b8d3 XG |
5786 | } |
5787 | ||
15248258 | 5788 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5789 | { |
164bf7e5 | 5790 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5791 | |
164bf7e5 | 5792 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5793 | |
f8f55942 | 5794 | /* |
e1359e2b SC |
5795 | * Generation numbers are incremented in multiples of the number of |
5796 | * address spaces in order to provide unique generations across all | |
5797 | * address spaces. Strip what is effectively the address space | |
5798 | * modifier prior to checking for a wrap of the MMIO generation so | |
5799 | * that a wrap in any address space is detected. | |
5800 | */ | |
5801 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5802 | ||
f8f55942 | 5803 | /* |
e1359e2b | 5804 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5805 | * zap all shadow pages. |
f8f55942 | 5806 | */ |
e1359e2b | 5807 | if (unlikely(gen == 0)) { |
ae0f5499 | 5808 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5809 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5810 | } |
f8f55942 XG |
5811 | } |
5812 | ||
70534a73 DC |
5813 | static unsigned long |
5814 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5815 | { |
5816 | struct kvm *kvm; | |
1495f230 | 5817 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5818 | unsigned long freed = 0; |
3ee16c81 | 5819 | |
0d9ce162 | 5820 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5821 | |
5822 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5823 | int idx; |
d98ba053 | 5824 | LIST_HEAD(invalid_list); |
3ee16c81 | 5825 | |
35f2d16b TY |
5826 | /* |
5827 | * Never scan more than sc->nr_to_scan VM instances. | |
5828 | * Will not hit this condition practically since we do not try | |
5829 | * to shrink more than one VM and it is very unlikely to see | |
5830 | * !n_used_mmu_pages so many times. | |
5831 | */ | |
5832 | if (!nr_to_scan--) | |
5833 | break; | |
19526396 GN |
5834 | /* |
5835 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5836 | * here. We may skip a VM instance errorneosly, but we do not | |
5837 | * want to shrink a VM that only started to populate its MMU | |
5838 | * anyway. | |
5839 | */ | |
10605204 SC |
5840 | if (!kvm->arch.n_used_mmu_pages && |
5841 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5842 | continue; |
19526396 | 5843 | |
f656ce01 | 5844 | idx = srcu_read_lock(&kvm->srcu); |
531810ca | 5845 | write_lock(&kvm->mmu_lock); |
3ee16c81 | 5846 | |
10605204 SC |
5847 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5848 | kvm_mmu_commit_zap_page(kvm, | |
5849 | &kvm->arch.zapped_obsolete_pages); | |
5850 | goto unlock; | |
5851 | } | |
5852 | ||
ebdb292d | 5853 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5854 | |
10605204 | 5855 | unlock: |
531810ca | 5856 | write_unlock(&kvm->mmu_lock); |
f656ce01 | 5857 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5858 | |
70534a73 DC |
5859 | /* |
5860 | * unfair on small ones | |
5861 | * per-vm shrinkers cry out | |
5862 | * sadness comes quickly | |
5863 | */ | |
19526396 GN |
5864 | list_move_tail(&kvm->vm_list, &vm_list); |
5865 | break; | |
3ee16c81 | 5866 | } |
3ee16c81 | 5867 | |
0d9ce162 | 5868 | mutex_unlock(&kvm_lock); |
70534a73 | 5869 | return freed; |
70534a73 DC |
5870 | } |
5871 | ||
5872 | static unsigned long | |
5873 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5874 | { | |
45221ab6 | 5875 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5876 | } |
5877 | ||
5878 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5879 | .count_objects = mmu_shrink_count, |
5880 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5881 | .seeks = DEFAULT_SEEKS * 10, |
5882 | }; | |
5883 | ||
2ddfd20e | 5884 | static void mmu_destroy_caches(void) |
b5a33a75 | 5885 | { |
c1bd743e TH |
5886 | kmem_cache_destroy(pte_list_desc_cache); |
5887 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5888 | } |
5889 | ||
b8e8c830 PB |
5890 | static bool get_nx_auto_mode(void) |
5891 | { | |
5892 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5893 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5894 | } | |
5895 | ||
5896 | static void __set_nx_huge_pages(bool val) | |
5897 | { | |
5898 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5899 | } | |
5900 | ||
5901 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5902 | { | |
5903 | bool old_val = nx_huge_pages; | |
5904 | bool new_val; | |
5905 | ||
5906 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5907 | if (sysfs_streq(val, "off")) | |
5908 | new_val = 0; | |
5909 | else if (sysfs_streq(val, "force")) | |
5910 | new_val = 1; | |
5911 | else if (sysfs_streq(val, "auto")) | |
5912 | new_val = get_nx_auto_mode(); | |
5913 | else if (strtobool(val, &new_val) < 0) | |
5914 | return -EINVAL; | |
5915 | ||
5916 | __set_nx_huge_pages(new_val); | |
5917 | ||
5918 | if (new_val != old_val) { | |
5919 | struct kvm *kvm; | |
b8e8c830 PB |
5920 | |
5921 | mutex_lock(&kvm_lock); | |
5922 | ||
5923 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 5924 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 5925 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 5926 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
5927 | |
5928 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
5929 | } |
5930 | mutex_unlock(&kvm_lock); | |
5931 | } | |
5932 | ||
5933 | return 0; | |
5934 | } | |
5935 | ||
b5a33a75 AK |
5936 | int kvm_mmu_module_init(void) |
5937 | { | |
ab271bd4 AB |
5938 | int ret = -ENOMEM; |
5939 | ||
b8e8c830 PB |
5940 | if (nx_huge_pages == -1) |
5941 | __set_nx_huge_pages(get_nx_auto_mode()); | |
5942 | ||
36d9594d VK |
5943 | /* |
5944 | * MMU roles use union aliasing which is, generally speaking, an | |
5945 | * undefined behavior. However, we supposedly know how compilers behave | |
5946 | * and the current status quo is unlikely to change. Guardians below are | |
5947 | * supposed to let us know if the assumption becomes false. | |
5948 | */ | |
5949 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
5950 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
5951 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
5952 | ||
28a1f3ac | 5953 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 5954 | |
53c07b18 XG |
5955 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5956 | sizeof(struct pte_list_desc), | |
46bea48a | 5957 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5958 | if (!pte_list_desc_cache) |
ab271bd4 | 5959 | goto out; |
b5a33a75 | 5960 | |
d3d25b04 AK |
5961 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5962 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5963 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5964 | if (!mmu_page_header_cache) |
ab271bd4 | 5965 | goto out; |
d3d25b04 | 5966 | |
908c7f19 | 5967 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5968 | goto out; |
45bf21a8 | 5969 | |
ab271bd4 AB |
5970 | ret = register_shrinker(&mmu_shrinker); |
5971 | if (ret) | |
5972 | goto out; | |
3ee16c81 | 5973 | |
b5a33a75 AK |
5974 | return 0; |
5975 | ||
ab271bd4 | 5976 | out: |
3ee16c81 | 5977 | mmu_destroy_caches(); |
ab271bd4 | 5978 | return ret; |
b5a33a75 AK |
5979 | } |
5980 | ||
3ad82a7e | 5981 | /* |
39337ad1 | 5982 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 5983 | */ |
bc8a3d89 | 5984 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 5985 | { |
bc8a3d89 BG |
5986 | unsigned long nr_mmu_pages; |
5987 | unsigned long nr_pages = 0; | |
bc6678a3 | 5988 | struct kvm_memslots *slots; |
be6ba0f0 | 5989 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5990 | int i; |
3ad82a7e | 5991 | |
9da0e4d5 PB |
5992 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5993 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5994 | |
9da0e4d5 PB |
5995 | kvm_for_each_memslot(memslot, slots) |
5996 | nr_pages += memslot->npages; | |
5997 | } | |
3ad82a7e ZX |
5998 | |
5999 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 6000 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6001 | |
6002 | return nr_mmu_pages; | |
6003 | } | |
6004 | ||
c42fffe3 XG |
6005 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6006 | { | |
95f93af4 | 6007 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
6008 | free_mmu_pages(&vcpu->arch.root_mmu); |
6009 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 6010 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
6011 | } |
6012 | ||
b034cf01 XG |
6013 | void kvm_mmu_module_exit(void) |
6014 | { | |
6015 | mmu_destroy_caches(); | |
6016 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6017 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6018 | mmu_audit_disable(); |
6019 | } | |
1aa9b957 JS |
6020 | |
6021 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
6022 | { | |
6023 | unsigned int old_val; | |
6024 | int err; | |
6025 | ||
6026 | old_val = nx_huge_pages_recovery_ratio; | |
6027 | err = param_set_uint(val, kp); | |
6028 | if (err) | |
6029 | return err; | |
6030 | ||
6031 | if (READ_ONCE(nx_huge_pages) && | |
6032 | !old_val && nx_huge_pages_recovery_ratio) { | |
6033 | struct kvm *kvm; | |
6034 | ||
6035 | mutex_lock(&kvm_lock); | |
6036 | ||
6037 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6038 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
6039 | ||
6040 | mutex_unlock(&kvm_lock); | |
6041 | } | |
6042 | ||
6043 | return err; | |
6044 | } | |
6045 | ||
6046 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
6047 | { | |
ade74e14 | 6048 | unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits; |
1aa9b957 JS |
6049 | int rcu_idx; |
6050 | struct kvm_mmu_page *sp; | |
6051 | unsigned int ratio; | |
6052 | LIST_HEAD(invalid_list); | |
048f4980 | 6053 | bool flush = false; |
1aa9b957 JS |
6054 | ulong to_zap; |
6055 | ||
6056 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
531810ca | 6057 | write_lock(&kvm->mmu_lock); |
1aa9b957 JS |
6058 | |
6059 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
ade74e14 | 6060 | to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0; |
7d919c7a SC |
6061 | for ( ; to_zap; --to_zap) { |
6062 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
6063 | break; | |
6064 | ||
1aa9b957 JS |
6065 | /* |
6066 | * We use a separate list instead of just using active_mmu_pages | |
6067 | * because the number of lpage_disallowed pages is expected to | |
6068 | * be relatively small compared to the total. | |
6069 | */ | |
6070 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
6071 | struct kvm_mmu_page, | |
6072 | lpage_disallowed_link); | |
6073 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
897218ff | 6074 | if (is_tdp_mmu_page(sp)) { |
315f02c6 | 6075 | flush |= kvm_tdp_mmu_zap_sp(kvm, sp); |
8d1a182e | 6076 | } else { |
29cf0f50 BG |
6077 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
6078 | WARN_ON_ONCE(sp->lpage_disallowed); | |
6079 | } | |
1aa9b957 | 6080 | |
531810ca | 6081 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
048f4980 | 6082 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
531810ca | 6083 | cond_resched_rwlock_write(&kvm->mmu_lock); |
048f4980 | 6084 | flush = false; |
1aa9b957 JS |
6085 | } |
6086 | } | |
048f4980 | 6087 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
1aa9b957 | 6088 | |
531810ca | 6089 | write_unlock(&kvm->mmu_lock); |
1aa9b957 JS |
6090 | srcu_read_unlock(&kvm->srcu, rcu_idx); |
6091 | } | |
6092 | ||
6093 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6094 | { | |
6095 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6096 | ? start_time + 60 * HZ - get_jiffies_64() | |
6097 | : MAX_SCHEDULE_TIMEOUT; | |
6098 | } | |
6099 | ||
6100 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6101 | { | |
6102 | u64 start_time; | |
6103 | long remaining_time; | |
6104 | ||
6105 | while (true) { | |
6106 | start_time = get_jiffies_64(); | |
6107 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6108 | ||
6109 | set_current_state(TASK_INTERRUPTIBLE); | |
6110 | while (!kthread_should_stop() && remaining_time > 0) { | |
6111 | schedule_timeout(remaining_time); | |
6112 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6113 | set_current_state(TASK_INTERRUPTIBLE); | |
6114 | } | |
6115 | ||
6116 | set_current_state(TASK_RUNNING); | |
6117 | ||
6118 | if (kthread_should_stop()) | |
6119 | return 0; | |
6120 | ||
6121 | kvm_recover_nx_lpages(kvm); | |
6122 | } | |
6123 | } | |
6124 | ||
6125 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6126 | { | |
6127 | int err; | |
6128 | ||
6129 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6130 | "kvm-nx-lpage-recovery", | |
6131 | &kvm->arch.nx_lpage_recovery_thread); | |
6132 | if (!err) | |
6133 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6134 | ||
6135 | return err; | |
6136 | } | |
6137 | ||
6138 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6139 | { | |
6140 | if (kvm->arch.nx_lpage_recovery_thread) | |
6141 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6142 | } |