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KVM: const-ify all relevant uses of struct kvm_memory_slot
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20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
9611c187 11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
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12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
6aa8b732 16 */
e495606d 17
af585b92 18#include "irq.h"
88197e6a 19#include "ioapic.h"
1d737c8a 20#include "mmu.h"
6ca9a6f3 21#include "mmu_internal.h"
fe5db27d 22#include "tdp_mmu.h"
836a1b3c 23#include "x86.h"
6de4f3ad 24#include "kvm_cache_regs.h"
2f728d66 25#include "kvm_emulate.h"
5f7dde7b 26#include "cpuid.h"
5a9624af 27#include "spte.h"
e495606d 28
edf88417 29#include <linux/kvm_host.h>
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30#include <linux/types.h>
31#include <linux/string.h>
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32#include <linux/mm.h>
33#include <linux/highmem.h>
1767e931
PG
34#include <linux/moduleparam.h>
35#include <linux/export.h>
448353ca 36#include <linux/swap.h>
05da4558 37#include <linux/hugetlb.h>
2f333bcb 38#include <linux/compiler.h>
bc6678a3 39#include <linux/srcu.h>
5a0e3ad6 40#include <linux/slab.h>
3f07c014 41#include <linux/sched/signal.h>
bf998156 42#include <linux/uaccess.h>
114df303 43#include <linux/hash.h>
f160c7b7 44#include <linux/kern_levels.h>
1aa9b957 45#include <linux/kthread.h>
6aa8b732 46
e495606d 47#include <asm/page.h>
eb243d1d 48#include <asm/memtype.h>
e495606d 49#include <asm/cmpxchg.h>
4e542370 50#include <asm/io.h>
4a98623d 51#include <asm/set_memory.h>
13673a90 52#include <asm/vmx.h>
3d0c27ad 53#include <asm/kvm_page_track.h>
1261bfa3 54#include "trace.h"
6aa8b732 55
fc9bf2e0
SC
56#include "paging.h"
57
b8e8c830
PB
58extern bool itlb_multihit_kvm_mitigation;
59
a9d6496d 60int __read_mostly nx_huge_pages = -1;
13fb5927
PB
61#ifdef CONFIG_PREEMPT_RT
62/* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
64#else
1aa9b957 65static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
13fb5927 66#endif
b8e8c830
PB
67
68static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
1aa9b957 69static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
b8e8c830 70
d5d6c18d 71static const struct kernel_param_ops nx_huge_pages_ops = {
b8e8c830
PB
72 .set = set_nx_huge_pages,
73 .get = param_get_bool,
74};
75
d5d6c18d 76static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
1aa9b957
JS
77 .set = set_nx_huge_pages_recovery_ratio,
78 .get = param_get_uint,
79};
80
b8e8c830
PB
81module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
82__MODULE_PARM_TYPE(nx_huge_pages, "bool");
1aa9b957
JS
83module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
84 &nx_huge_pages_recovery_ratio, 0644);
85__MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
b8e8c830 86
71fe7013
SC
87static bool __read_mostly force_flush_and_sync_on_reuse;
88module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89
18552672
JR
90/*
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
96 */
2f333bcb 97bool tdp_enabled = false;
18552672 98
1d92d2e8 99static int max_huge_page_level __read_mostly;
83013059 100static int max_tdp_level __read_mostly;
703c335d 101
8b1fe17c
XG
102enum {
103 AUDIT_PRE_PAGE_FAULT,
104 AUDIT_POST_PAGE_FAULT,
105 AUDIT_PRE_PTE_WRITE,
6903074c
XG
106 AUDIT_POST_PTE_WRITE,
107 AUDIT_PRE_SYNC,
108 AUDIT_POST_SYNC
8b1fe17c 109};
37a7d8b0 110
37a7d8b0 111#ifdef MMU_DEBUG
5a9624af 112bool dbg = 0;
fa4a2c08 113module_param(dbg, bool, 0644);
d6c69ee9 114#endif
6aa8b732 115
957ed9ef
XG
116#define PTE_PREFETCH_NUM 8
117
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118#define PT32_LEVEL_BITS 10
119
120#define PT32_LEVEL_SHIFT(level) \
d77c26fc 121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732 122
e04da980
JR
123#define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
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126
127#define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129
130
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131#define PT32_BASE_ADDR_MASK PAGE_MASK
132#define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR
134#define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
6aa8b732 137
90bb6fc5
AK
138#include <trace/events/kvm.h>
139
220f773a
TY
140/* make pte_list_desc fit well in cache line */
141#define PTE_LIST_EXT 3
142
53c07b18
XG
143struct pte_list_desc {
144 u64 *sptes[PTE_LIST_EXT];
145 struct pte_list_desc *more;
cd4a4e53
AK
146};
147
2d11123a
AK
148struct kvm_shadow_walk_iterator {
149 u64 addr;
150 hpa_t shadow_addr;
2d11123a 151 u64 *sptep;
dd3bfd59 152 int level;
2d11123a
AK
153 unsigned index;
154};
155
7eb77e9f
JS
156#define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
157 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
158 (_root), (_addr)); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
161
162#define for_each_shadow_entry(_vcpu, _addr, _walker) \
2d11123a
AK
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)); \
165 shadow_walk_next(&(_walker)))
166
c2a2ac2b
XG
167#define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
168 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
169 shadow_walk_okay(&(_walker)) && \
170 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
171 __shadow_walk_next(&(_walker), spte))
172
53c07b18 173static struct kmem_cache *pte_list_desc_cache;
02c00b3a 174struct kmem_cache *mmu_page_header_cache;
45221ab6 175static struct percpu_counter kvm_total_used_mmu_pages;
b5a33a75 176
ce88decf 177static void mmu_spte_set(u64 *sptep, u64 spte);
9fa72119
JS
178static union kvm_mmu_page_role
179kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
ce88decf 180
594e91a1
SC
181struct kvm_mmu_role_regs {
182 const unsigned long cr0;
183 const unsigned long cr4;
184 const u64 efer;
185};
186
335e192a
PB
187#define CREATE_TRACE_POINTS
188#include "mmutrace.h"
189
594e91a1
SC
190/*
191 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
192 * reading from the role_regs. Once the mmu_role is constructed, it becomes
193 * the single source of truth for the MMU's state.
194 */
195#define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
196static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
197{ \
198 return !!(regs->reg & flag); \
199}
200BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
201BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
202BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
203BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
204BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
205BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
206BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
207BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
208BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
209BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
210
60667724
SC
211/*
212 * The MMU itself (with a valid role) is the single source of truth for the
213 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
214 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
215 * and the vCPU may be incorrect/irrelevant.
216 */
217#define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
218static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
219{ \
220 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
221}
222BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
223BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
224BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
225BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
226BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
227BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
228BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
229BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
230BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
231
594e91a1
SC
232static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
233{
234 struct kvm_mmu_role_regs regs = {
235 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
236 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
237 .efer = vcpu->arch.efer,
238 };
239
240 return regs;
241}
40ef75a7 242
f4bd6f73
SC
243static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
244{
245 if (!____is_cr0_pg(regs))
246 return 0;
247 else if (____is_efer_lma(regs))
248 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
249 PT64_ROOT_4LEVEL;
250 else if (____is_cr4_pae(regs))
251 return PT32E_ROOT_LEVEL;
252 else
253 return PT32_ROOT_LEVEL;
254}
40ef75a7
LT
255
256static inline bool kvm_available_flush_tlb_with_range(void)
257{
afaf0b2f 258 return kvm_x86_ops.tlb_remote_flush_with_range;
40ef75a7
LT
259}
260
261static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
262 struct kvm_tlb_range *range)
263{
264 int ret = -ENOTSUPP;
265
afaf0b2f 266 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
b3646477 267 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
40ef75a7
LT
268
269 if (ret)
270 kvm_flush_remote_tlbs(kvm);
271}
272
2f2fad08 273void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
40ef75a7
LT
274 u64 start_gfn, u64 pages)
275{
276 struct kvm_tlb_range range;
277
278 range.start_gfn = start_gfn;
279 range.pages = pages;
280
281 kvm_flush_remote_tlbs_with_range(kvm, &range);
282}
283
8f79b064
BG
284static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
285 unsigned int access)
286{
c236d962 287 u64 spte = make_mmio_spte(vcpu, gfn, access);
8f79b064 288
c236d962
SC
289 trace_mark_mmio_spte(sptep, gfn, spte);
290 mmu_spte_set(sptep, spte);
ce88decf
XG
291}
292
ce88decf
XG
293static gfn_t get_mmio_spte_gfn(u64 spte)
294{
daa07cbc 295 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
28a1f3ac 296
8a967d65 297 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
28a1f3ac
JS
298 & shadow_nonpresent_or_rsvd_mask;
299
300 return gpa >> PAGE_SHIFT;
ce88decf
XG
301}
302
303static unsigned get_mmio_spte_access(u64 spte)
304{
4af77151 305 return spte & shadow_mmio_access_mask;
ce88decf
XG
306}
307
54bf36aa 308static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
f8f55942 309{
cae7ed3c 310 u64 kvm_gen, spte_gen, gen;
089504c0 311
cae7ed3c
SC
312 gen = kvm_vcpu_memslots(vcpu)->generation;
313 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
314 return false;
089504c0 315
cae7ed3c 316 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
089504c0
XG
317 spte_gen = get_mmio_spte_generation(spte);
318
319 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
320 return likely(kvm_gen == spte_gen);
f8f55942
XG
321}
322
cd313569
MG
323static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
324 struct x86_exception *exception)
325{
ec7771ab 326 /* Check if guest physical address doesn't exceed guest maximum */
dc46515c 327 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
ec7771ab
MG
328 exception->error_code |= PFERR_RSVD_MASK;
329 return UNMAPPED_GVA;
330 }
331
cd313569
MG
332 return gpa;
333}
334
6aa8b732
AK
335static int is_cpuid_PSE36(void)
336{
337 return 1;
338}
339
da928521
AK
340static gfn_t pse36_gfn_delta(u32 gpte)
341{
342 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
343
344 return (gpte & PT32_DIR_PSE36_MASK) << shift;
345}
346
603e0651 347#ifdef CONFIG_X86_64
d555c333 348static void __set_spte(u64 *sptep, u64 spte)
e663ee64 349{
b19ee2ff 350 WRITE_ONCE(*sptep, spte);
e663ee64
AK
351}
352
603e0651 353static void __update_clear_spte_fast(u64 *sptep, u64 spte)
a9221dd5 354{
b19ee2ff 355 WRITE_ONCE(*sptep, spte);
603e0651
XG
356}
357
358static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
359{
360 return xchg(sptep, spte);
361}
c2a2ac2b
XG
362
363static u64 __get_spte_lockless(u64 *sptep)
364{
6aa7de05 365 return READ_ONCE(*sptep);
c2a2ac2b 366}
a9221dd5 367#else
603e0651
XG
368union split_spte {
369 struct {
370 u32 spte_low;
371 u32 spte_high;
372 };
373 u64 spte;
374};
a9221dd5 375
c2a2ac2b
XG
376static void count_spte_clear(u64 *sptep, u64 spte)
377{
57354682 378 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
c2a2ac2b
XG
379
380 if (is_shadow_present_pte(spte))
381 return;
382
383 /* Ensure the spte is completely set before we increase the count */
384 smp_wmb();
385 sp->clear_spte_count++;
386}
387
603e0651
XG
388static void __set_spte(u64 *sptep, u64 spte)
389{
390 union split_spte *ssptep, sspte;
a9221dd5 391
603e0651
XG
392 ssptep = (union split_spte *)sptep;
393 sspte = (union split_spte)spte;
394
395 ssptep->spte_high = sspte.spte_high;
396
397 /*
398 * If we map the spte from nonpresent to present, We should store
399 * the high bits firstly, then set present bit, so cpu can not
400 * fetch this spte while we are setting the spte.
401 */
402 smp_wmb();
403
b19ee2ff 404 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
a9221dd5
AK
405}
406
603e0651
XG
407static void __update_clear_spte_fast(u64 *sptep, u64 spte)
408{
409 union split_spte *ssptep, sspte;
410
411 ssptep = (union split_spte *)sptep;
412 sspte = (union split_spte)spte;
413
b19ee2ff 414 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
603e0651
XG
415
416 /*
417 * If we map the spte from present to nonpresent, we should clear
418 * present bit firstly to avoid vcpu fetch the old high bits.
419 */
420 smp_wmb();
421
422 ssptep->spte_high = sspte.spte_high;
c2a2ac2b 423 count_spte_clear(sptep, spte);
603e0651
XG
424}
425
426static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
427{
428 union split_spte *ssptep, sspte, orig;
429
430 ssptep = (union split_spte *)sptep;
431 sspte = (union split_spte)spte;
432
433 /* xchg acts as a barrier before the setting of the high bits */
434 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
41bc3186
ZJ
435 orig.spte_high = ssptep->spte_high;
436 ssptep->spte_high = sspte.spte_high;
c2a2ac2b 437 count_spte_clear(sptep, spte);
603e0651
XG
438
439 return orig.spte;
440}
c2a2ac2b
XG
441
442/*
443 * The idea using the light way get the spte on x86_32 guest is from
39656e83 444 * gup_get_pte (mm/gup.c).
accaefe0
XG
445 *
446 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
447 * coalesces them and we are running out of the MMU lock. Therefore
448 * we need to protect against in-progress updates of the spte.
449 *
450 * Reading the spte while an update is in progress may get the old value
451 * for the high part of the spte. The race is fine for a present->non-present
452 * change (because the high part of the spte is ignored for non-present spte),
453 * but for a present->present change we must reread the spte.
454 *
455 * All such changes are done in two steps (present->non-present and
456 * non-present->present), hence it is enough to count the number of
457 * present->non-present updates: if it changed while reading the spte,
458 * we might have hit the race. This is done using clear_spte_count.
c2a2ac2b
XG
459 */
460static u64 __get_spte_lockless(u64 *sptep)
461{
57354682 462 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
c2a2ac2b
XG
463 union split_spte spte, *orig = (union split_spte *)sptep;
464 int count;
465
466retry:
467 count = sp->clear_spte_count;
468 smp_rmb();
469
470 spte.spte_low = orig->spte_low;
471 smp_rmb();
472
473 spte.spte_high = orig->spte_high;
474 smp_rmb();
475
476 if (unlikely(spte.spte_low != orig->spte_low ||
477 count != sp->clear_spte_count))
478 goto retry;
479
480 return spte.spte;
481}
603e0651
XG
482#endif
483
8672b721
XG
484static bool spte_has_volatile_bits(u64 spte)
485{
f160c7b7
JS
486 if (!is_shadow_present_pte(spte))
487 return false;
488
c7ba5b48 489 /*
6a6256f9 490 * Always atomically update spte if it can be updated
c7ba5b48
XG
491 * out of mmu-lock, it can ensure dirty bit is not lost,
492 * also, it can help us to get a stable is_writable_pte()
493 * to ensure tlb flush is not missed.
494 */
f160c7b7
JS
495 if (spte_can_locklessly_be_made_writable(spte) ||
496 is_access_track_spte(spte))
c7ba5b48
XG
497 return true;
498
ac8d57e5 499 if (spte_ad_enabled(spte)) {
f160c7b7
JS
500 if ((spte & shadow_accessed_mask) == 0 ||
501 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
502 return true;
503 }
8672b721 504
f160c7b7 505 return false;
8672b721
XG
506}
507
1df9f2dc
XG
508/* Rules for using mmu_spte_set:
509 * Set the sptep from nonpresent to present.
510 * Note: the sptep being assigned *must* be either not present
511 * or in a state where the hardware will not attempt to update
512 * the spte.
513 */
514static void mmu_spte_set(u64 *sptep, u64 new_spte)
515{
516 WARN_ON(is_shadow_present_pte(*sptep));
517 __set_spte(sptep, new_spte);
518}
519
f39a058d
JS
520/*
521 * Update the SPTE (excluding the PFN), but do not track changes in its
522 * accessed/dirty status.
1df9f2dc 523 */
f39a058d 524static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
b79b93f9 525{
c7ba5b48 526 u64 old_spte = *sptep;
4132779b 527
afd28fe1 528 WARN_ON(!is_shadow_present_pte(new_spte));
b79b93f9 529
6e7d0354
XG
530 if (!is_shadow_present_pte(old_spte)) {
531 mmu_spte_set(sptep, new_spte);
f39a058d 532 return old_spte;
6e7d0354 533 }
4132779b 534
c7ba5b48 535 if (!spte_has_volatile_bits(old_spte))
603e0651 536 __update_clear_spte_fast(sptep, new_spte);
4132779b 537 else
603e0651 538 old_spte = __update_clear_spte_slow(sptep, new_spte);
4132779b 539
83ef6c81
JS
540 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
541
f39a058d
JS
542 return old_spte;
543}
544
545/* Rules for using mmu_spte_update:
546 * Update the state bits, it means the mapped pfn is not changed.
547 *
548 * Whenever we overwrite a writable spte with a read-only one we
549 * should flush remote TLBs. Otherwise rmap_write_protect
550 * will find a read-only spte, even though the writable spte
551 * might be cached on a CPU's TLB, the return value indicates this
552 * case.
553 *
554 * Returns true if the TLB needs to be flushed
555 */
556static bool mmu_spte_update(u64 *sptep, u64 new_spte)
557{
558 bool flush = false;
559 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
560
561 if (!is_shadow_present_pte(old_spte))
562 return false;
563
c7ba5b48
XG
564 /*
565 * For the spte updated out of mmu-lock is safe, since
6a6256f9 566 * we always atomically update it, see the comments in
c7ba5b48
XG
567 * spte_has_volatile_bits().
568 */
ea4114bc 569 if (spte_can_locklessly_be_made_writable(old_spte) &&
7f31c959 570 !is_writable_pte(new_spte))
83ef6c81 571 flush = true;
4132779b 572
7e71a59b 573 /*
83ef6c81 574 * Flush TLB when accessed/dirty states are changed in the page tables,
7e71a59b
KH
575 * to guarantee consistency between TLB and page tables.
576 */
7e71a59b 577
83ef6c81
JS
578 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
579 flush = true;
4132779b 580 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
83ef6c81
JS
581 }
582
583 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
584 flush = true;
4132779b 585 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
83ef6c81 586 }
6e7d0354 587
83ef6c81 588 return flush;
b79b93f9
AK
589}
590
1df9f2dc
XG
591/*
592 * Rules for using mmu_spte_clear_track_bits:
593 * It sets the sptep from present to nonpresent, and track the
594 * state bits, it is used to clear the last level sptep.
7fa2a347 595 * Returns the old PTE.
1df9f2dc 596 */
7fa2a347 597static u64 mmu_spte_clear_track_bits(u64 *sptep)
1df9f2dc 598{
ba049e93 599 kvm_pfn_t pfn;
1df9f2dc
XG
600 u64 old_spte = *sptep;
601
602 if (!spte_has_volatile_bits(old_spte))
603e0651 603 __update_clear_spte_fast(sptep, 0ull);
1df9f2dc 604 else
603e0651 605 old_spte = __update_clear_spte_slow(sptep, 0ull);
1df9f2dc 606
afd28fe1 607 if (!is_shadow_present_pte(old_spte))
7fa2a347 608 return old_spte;
1df9f2dc
XG
609
610 pfn = spte_to_pfn(old_spte);
86fde74c
XG
611
612 /*
613 * KVM does not hold the refcount of the page used by
614 * kvm mmu, before reclaiming the page, we should
615 * unmap it from mmu first.
616 */
bf4bea8e 617 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
86fde74c 618
83ef6c81 619 if (is_accessed_spte(old_spte))
1df9f2dc 620 kvm_set_pfn_accessed(pfn);
83ef6c81
JS
621
622 if (is_dirty_spte(old_spte))
1df9f2dc 623 kvm_set_pfn_dirty(pfn);
83ef6c81 624
7fa2a347 625 return old_spte;
1df9f2dc
XG
626}
627
628/*
629 * Rules for using mmu_spte_clear_no_track:
630 * Directly clear spte without caring the state bits of sptep,
631 * it is used to set the upper level spte.
632 */
633static void mmu_spte_clear_no_track(u64 *sptep)
634{
603e0651 635 __update_clear_spte_fast(sptep, 0ull);
1df9f2dc
XG
636}
637
c2a2ac2b
XG
638static u64 mmu_spte_get_lockless(u64 *sptep)
639{
640 return __get_spte_lockless(sptep);
641}
642
d3e328f2
JS
643/* Restore an acc-track PTE back to a regular PTE */
644static u64 restore_acc_track_spte(u64 spte)
645{
646 u64 new_spte = spte;
8a967d65
PB
647 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
648 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
d3e328f2 649
ac8d57e5 650 WARN_ON_ONCE(spte_ad_enabled(spte));
d3e328f2
JS
651 WARN_ON_ONCE(!is_access_track_spte(spte));
652
653 new_spte &= ~shadow_acc_track_mask;
8a967d65
PB
654 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
655 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
d3e328f2
JS
656 new_spte |= saved_bits;
657
658 return new_spte;
659}
660
f160c7b7
JS
661/* Returns the Accessed status of the PTE and resets it at the same time. */
662static bool mmu_spte_age(u64 *sptep)
663{
664 u64 spte = mmu_spte_get_lockless(sptep);
665
666 if (!is_accessed_spte(spte))
667 return false;
668
ac8d57e5 669 if (spte_ad_enabled(spte)) {
f160c7b7
JS
670 clear_bit((ffs(shadow_accessed_mask) - 1),
671 (unsigned long *)sptep);
672 } else {
673 /*
674 * Capture the dirty status of the page, so that it doesn't get
675 * lost when the SPTE is marked for access tracking.
676 */
677 if (is_writable_pte(spte))
678 kvm_set_pfn_dirty(spte_to_pfn(spte));
679
680 spte = mark_spte_for_access_track(spte);
681 mmu_spte_update_no_track(sptep, spte);
682 }
683
684 return true;
685}
686
c2a2ac2b
XG
687static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
688{
c5c8c7c5
DM
689 if (is_tdp_mmu(vcpu->arch.mmu)) {
690 kvm_tdp_mmu_walk_lockless_begin();
691 } else {
692 /*
693 * Prevent page table teardown by making any free-er wait during
694 * kvm_flush_remote_tlbs() IPI to all active vcpus.
695 */
696 local_irq_disable();
36ca7e0a 697
c5c8c7c5
DM
698 /*
699 * Make sure a following spte read is not reordered ahead of the write
700 * to vcpu->mode.
701 */
702 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
703 }
c2a2ac2b
XG
704}
705
706static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
707{
c5c8c7c5
DM
708 if (is_tdp_mmu(vcpu->arch.mmu)) {
709 kvm_tdp_mmu_walk_lockless_end();
710 } else {
711 /*
712 * Make sure the write to vcpu->mode is not reordered in front of
713 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
714 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
715 */
716 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
717 local_irq_enable();
718 }
c2a2ac2b
XG
719}
720
378f5cd6 721static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
714b93da 722{
e2dec939
AK
723 int r;
724
531281ad 725 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
94ce87ef
SC
726 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
727 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
d3d25b04 728 if (r)
284aa868 729 return r;
94ce87ef
SC
730 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
731 PT64_ROOT_MAX_LEVEL);
d3d25b04 732 if (r)
171a90d7 733 return r;
378f5cd6 734 if (maybe_indirect) {
94ce87ef
SC
735 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
736 PT64_ROOT_MAX_LEVEL);
378f5cd6
SC
737 if (r)
738 return r;
739 }
94ce87ef
SC
740 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
741 PT64_ROOT_MAX_LEVEL);
714b93da
AK
742}
743
744static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
745{
94ce87ef
SC
746 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
747 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
748 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
749 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK
750}
751
53c07b18 752static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
714b93da 753{
94ce87ef 754 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
714b93da
AK
755}
756
53c07b18 757static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
714b93da 758{
53c07b18 759 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
714b93da
AK
760}
761
2032a93d
LJ
762static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
763{
764 if (!sp->role.direct)
765 return sp->gfns[index];
766
767 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
768}
769
770static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
771{
e9f2a760 772 if (!sp->role.direct) {
2032a93d 773 sp->gfns[index] = gfn;
e9f2a760
PB
774 return;
775 }
776
777 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
778 pr_err_ratelimited("gfn mismatch under direct page %llx "
779 "(expected %llx, got %llx)\n",
780 sp->gfn,
781 kvm_mmu_page_get_gfn(sp, index), gfn);
2032a93d
LJ
782}
783
05da4558 784/*
d4dbf470
TY
785 * Return the pointer to the large page information for a given gfn,
786 * handling slots that are not large page aligned.
05da4558 787 */
d4dbf470 788static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
8ca6f063 789 const struct kvm_memory_slot *slot, int level)
05da4558
MT
790{
791 unsigned long idx;
792
fb03cb6f 793 idx = gfn_to_index(gfn, slot->base_gfn, level);
db3fe4eb 794 return &slot->arch.lpage_info[level - 2][idx];
05da4558
MT
795}
796
269e9552 797static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot *slot,
547ffaed
XG
798 gfn_t gfn, int count)
799{
800 struct kvm_lpage_info *linfo;
801 int i;
802
3bae0459 803 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
547ffaed
XG
804 linfo = lpage_info_slot(gfn, slot, i);
805 linfo->disallow_lpage += count;
806 WARN_ON(linfo->disallow_lpage < 0);
807 }
808}
809
269e9552 810void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
547ffaed
XG
811{
812 update_gfn_disallow_lpage_count(slot, gfn, 1);
813}
814
269e9552 815void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
547ffaed
XG
816{
817 update_gfn_disallow_lpage_count(slot, gfn, -1);
818}
819
3ed1a478 820static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
05da4558 821{
699023e2 822 struct kvm_memslots *slots;
d25797b2 823 struct kvm_memory_slot *slot;
3ed1a478 824 gfn_t gfn;
05da4558 825
56ca57f9 826 kvm->arch.indirect_shadow_pages++;
3ed1a478 827 gfn = sp->gfn;
699023e2
PB
828 slots = kvm_memslots_for_spte_role(kvm, sp->role);
829 slot = __gfn_to_memslot(slots, gfn);
56ca57f9
XG
830
831 /* the non-leaf shadow pages are keeping readonly. */
3bae0459 832 if (sp->role.level > PG_LEVEL_4K)
56ca57f9
XG
833 return kvm_slot_page_track_add_page(kvm, slot, gfn,
834 KVM_PAGE_TRACK_WRITE);
835
547ffaed 836 kvm_mmu_gfn_disallow_lpage(slot, gfn);
05da4558
MT
837}
838
29cf0f50 839void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
b8e8c830
PB
840{
841 if (sp->lpage_disallowed)
842 return;
843
844 ++kvm->stat.nx_lpage_splits;
1aa9b957
JS
845 list_add_tail(&sp->lpage_disallowed_link,
846 &kvm->arch.lpage_disallowed_mmu_pages);
b8e8c830
PB
847 sp->lpage_disallowed = true;
848}
849
3ed1a478 850static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
05da4558 851{
699023e2 852 struct kvm_memslots *slots;
d25797b2 853 struct kvm_memory_slot *slot;
3ed1a478 854 gfn_t gfn;
05da4558 855
56ca57f9 856 kvm->arch.indirect_shadow_pages--;
3ed1a478 857 gfn = sp->gfn;
699023e2
PB
858 slots = kvm_memslots_for_spte_role(kvm, sp->role);
859 slot = __gfn_to_memslot(slots, gfn);
3bae0459 860 if (sp->role.level > PG_LEVEL_4K)
56ca57f9
XG
861 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
862 KVM_PAGE_TRACK_WRITE);
863
547ffaed 864 kvm_mmu_gfn_allow_lpage(slot, gfn);
05da4558
MT
865}
866
29cf0f50 867void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
b8e8c830
PB
868{
869 --kvm->stat.nx_lpage_splits;
870 sp->lpage_disallowed = false;
1aa9b957 871 list_del(&sp->lpage_disallowed_link);
b8e8c830
PB
872}
873
5d163b1c
XG
874static struct kvm_memory_slot *
875gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
876 bool no_dirty_log)
05da4558
MT
877{
878 struct kvm_memory_slot *slot;
5d163b1c 879
54bf36aa 880 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
91b0d268
PB
881 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
882 return NULL;
044c59c4 883 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
91b0d268 884 return NULL;
5d163b1c
XG
885
886 return slot;
887}
888
290fc38d 889/*
018aabb5 890 * About rmap_head encoding:
cd4a4e53 891 *
018aabb5
TY
892 * If the bit zero of rmap_head->val is clear, then it points to the only spte
893 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
53c07b18 894 * pte_list_desc containing more mappings.
018aabb5
TY
895 */
896
897/*
898 * Returns the number of pointers in the rmap chain, not counting the new one.
cd4a4e53 899 */
53c07b18 900static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
018aabb5 901 struct kvm_rmap_head *rmap_head)
cd4a4e53 902{
53c07b18 903 struct pte_list_desc *desc;
53a27b39 904 int i, count = 0;
cd4a4e53 905
018aabb5 906 if (!rmap_head->val) {
805a0f83 907 rmap_printk("%p %llx 0->1\n", spte, *spte);
018aabb5
TY
908 rmap_head->val = (unsigned long)spte;
909 } else if (!(rmap_head->val & 1)) {
805a0f83 910 rmap_printk("%p %llx 1->many\n", spte, *spte);
53c07b18 911 desc = mmu_alloc_pte_list_desc(vcpu);
018aabb5 912 desc->sptes[0] = (u64 *)rmap_head->val;
d555c333 913 desc->sptes[1] = spte;
018aabb5 914 rmap_head->val = (unsigned long)desc | 1;
cb16a7b3 915 ++count;
cd4a4e53 916 } else {
805a0f83 917 rmap_printk("%p %llx many->many\n", spte, *spte);
018aabb5 918 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
c6c4f961 919 while (desc->sptes[PTE_LIST_EXT-1]) {
53c07b18 920 count += PTE_LIST_EXT;
c6c4f961
LR
921
922 if (!desc->more) {
923 desc->more = mmu_alloc_pte_list_desc(vcpu);
924 desc = desc->more;
925 break;
926 }
cd4a4e53
AK
927 desc = desc->more;
928 }
d555c333 929 for (i = 0; desc->sptes[i]; ++i)
cb16a7b3 930 ++count;
d555c333 931 desc->sptes[i] = spte;
cd4a4e53 932 }
53a27b39 933 return count;
cd4a4e53
AK
934}
935
53c07b18 936static void
018aabb5
TY
937pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
938 struct pte_list_desc *desc, int i,
939 struct pte_list_desc *prev_desc)
cd4a4e53
AK
940{
941 int j;
942
53c07b18 943 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 944 ;
d555c333
AK
945 desc->sptes[i] = desc->sptes[j];
946 desc->sptes[j] = NULL;
cd4a4e53
AK
947 if (j != 0)
948 return;
949 if (!prev_desc && !desc->more)
fe3c2b4c 950 rmap_head->val = 0;
cd4a4e53
AK
951 else
952 if (prev_desc)
953 prev_desc->more = desc->more;
954 else
018aabb5 955 rmap_head->val = (unsigned long)desc->more | 1;
53c07b18 956 mmu_free_pte_list_desc(desc);
cd4a4e53
AK
957}
958
8daf3462 959static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
cd4a4e53 960{
53c07b18
XG
961 struct pte_list_desc *desc;
962 struct pte_list_desc *prev_desc;
cd4a4e53
AK
963 int i;
964
018aabb5 965 if (!rmap_head->val) {
8daf3462 966 pr_err("%s: %p 0->BUG\n", __func__, spte);
cd4a4e53 967 BUG();
018aabb5 968 } else if (!(rmap_head->val & 1)) {
805a0f83 969 rmap_printk("%p 1->0\n", spte);
018aabb5 970 if ((u64 *)rmap_head->val != spte) {
8daf3462 971 pr_err("%s: %p 1->BUG\n", __func__, spte);
cd4a4e53
AK
972 BUG();
973 }
018aabb5 974 rmap_head->val = 0;
cd4a4e53 975 } else {
805a0f83 976 rmap_printk("%p many->many\n", spte);
018aabb5 977 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
cd4a4e53
AK
978 prev_desc = NULL;
979 while (desc) {
018aabb5 980 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
d555c333 981 if (desc->sptes[i] == spte) {
018aabb5
TY
982 pte_list_desc_remove_entry(rmap_head,
983 desc, i, prev_desc);
cd4a4e53
AK
984 return;
985 }
018aabb5 986 }
cd4a4e53
AK
987 prev_desc = desc;
988 desc = desc->more;
989 }
8daf3462 990 pr_err("%s: %p many->many\n", __func__, spte);
cd4a4e53
AK
991 BUG();
992 }
993}
994
e7912386
WY
995static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
996{
997 mmu_spte_clear_track_bits(sptep);
998 __pte_list_remove(sptep, rmap_head);
999}
1000
018aabb5 1001static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
269e9552 1002 const struct kvm_memory_slot *slot)
53c07b18 1003{
77d11309 1004 unsigned long idx;
53c07b18 1005
77d11309 1006 idx = gfn_to_index(gfn, slot->base_gfn, level);
3bae0459 1007 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
53c07b18
XG
1008}
1009
018aabb5
TY
1010static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1011 struct kvm_mmu_page *sp)
9b9b1492 1012{
699023e2 1013 struct kvm_memslots *slots;
9b9b1492
TY
1014 struct kvm_memory_slot *slot;
1015
699023e2
PB
1016 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1017 slot = __gfn_to_memslot(slots, gfn);
e4cd1da9 1018 return __gfn_to_rmap(gfn, sp->role.level, slot);
9b9b1492
TY
1019}
1020
f759e2b4
XG
1021static bool rmap_can_add(struct kvm_vcpu *vcpu)
1022{
356ec69a 1023 struct kvm_mmu_memory_cache *mc;
f759e2b4 1024
356ec69a 1025 mc = &vcpu->arch.mmu_pte_list_desc_cache;
94ce87ef 1026 return kvm_mmu_memory_cache_nr_free_objects(mc);
f759e2b4
XG
1027}
1028
53c07b18
XG
1029static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1030{
1031 struct kvm_mmu_page *sp;
018aabb5 1032 struct kvm_rmap_head *rmap_head;
53c07b18 1033
57354682 1034 sp = sptep_to_sp(spte);
53c07b18 1035 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
018aabb5
TY
1036 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1037 return pte_list_add(vcpu, spte, rmap_head);
53c07b18
XG
1038}
1039
53c07b18
XG
1040static void rmap_remove(struct kvm *kvm, u64 *spte)
1041{
1042 struct kvm_mmu_page *sp;
1043 gfn_t gfn;
018aabb5 1044 struct kvm_rmap_head *rmap_head;
53c07b18 1045
57354682 1046 sp = sptep_to_sp(spte);
53c07b18 1047 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
018aabb5 1048 rmap_head = gfn_to_rmap(kvm, gfn, sp);
8daf3462 1049 __pte_list_remove(spte, rmap_head);
53c07b18
XG
1050}
1051
1e3f42f0
TY
1052/*
1053 * Used by the following functions to iterate through the sptes linked by a
1054 * rmap. All fields are private and not assumed to be used outside.
1055 */
1056struct rmap_iterator {
1057 /* private fields */
1058 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1059 int pos; /* index of the sptep */
1060};
1061
1062/*
1063 * Iteration must be started by this function. This should also be used after
1064 * removing/dropping sptes from the rmap link because in such cases the
0a03cbda 1065 * information in the iterator may not be valid.
1e3f42f0
TY
1066 *
1067 * Returns sptep if found, NULL otherwise.
1068 */
018aabb5
TY
1069static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1070 struct rmap_iterator *iter)
1e3f42f0 1071{
77fbbbd2
TY
1072 u64 *sptep;
1073
018aabb5 1074 if (!rmap_head->val)
1e3f42f0
TY
1075 return NULL;
1076
018aabb5 1077 if (!(rmap_head->val & 1)) {
1e3f42f0 1078 iter->desc = NULL;
77fbbbd2
TY
1079 sptep = (u64 *)rmap_head->val;
1080 goto out;
1e3f42f0
TY
1081 }
1082
018aabb5 1083 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1e3f42f0 1084 iter->pos = 0;
77fbbbd2
TY
1085 sptep = iter->desc->sptes[iter->pos];
1086out:
1087 BUG_ON(!is_shadow_present_pte(*sptep));
1088 return sptep;
1e3f42f0
TY
1089}
1090
1091/*
1092 * Must be used with a valid iterator: e.g. after rmap_get_first().
1093 *
1094 * Returns sptep if found, NULL otherwise.
1095 */
1096static u64 *rmap_get_next(struct rmap_iterator *iter)
1097{
77fbbbd2
TY
1098 u64 *sptep;
1099
1e3f42f0
TY
1100 if (iter->desc) {
1101 if (iter->pos < PTE_LIST_EXT - 1) {
1e3f42f0
TY
1102 ++iter->pos;
1103 sptep = iter->desc->sptes[iter->pos];
1104 if (sptep)
77fbbbd2 1105 goto out;
1e3f42f0
TY
1106 }
1107
1108 iter->desc = iter->desc->more;
1109
1110 if (iter->desc) {
1111 iter->pos = 0;
1112 /* desc->sptes[0] cannot be NULL */
77fbbbd2
TY
1113 sptep = iter->desc->sptes[iter->pos];
1114 goto out;
1e3f42f0
TY
1115 }
1116 }
1117
1118 return NULL;
77fbbbd2
TY
1119out:
1120 BUG_ON(!is_shadow_present_pte(*sptep));
1121 return sptep;
1e3f42f0
TY
1122}
1123
018aabb5
TY
1124#define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1125 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
77fbbbd2 1126 _spte_; _spte_ = rmap_get_next(_iter_))
0d536790 1127
c3707958 1128static void drop_spte(struct kvm *kvm, u64 *sptep)
e4b502ea 1129{
7fa2a347
SC
1130 u64 old_spte = mmu_spte_clear_track_bits(sptep);
1131
1132 if (is_shadow_present_pte(old_spte))
eb45fda4 1133 rmap_remove(kvm, sptep);
be38d276
AK
1134}
1135
8e22f955
XG
1136
1137static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1138{
1139 if (is_large_pte(*sptep)) {
57354682 1140 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
8e22f955
XG
1141 drop_spte(kvm, sptep);
1142 --kvm->stat.lpages;
1143 return true;
1144 }
1145
1146 return false;
1147}
1148
1149static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1150{
c3134ce2 1151 if (__drop_large_spte(vcpu->kvm, sptep)) {
57354682 1152 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
c3134ce2
LT
1153
1154 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1155 KVM_PAGES_PER_HPAGE(sp->role.level));
1156 }
8e22f955
XG
1157}
1158
1159/*
49fde340 1160 * Write-protect on the specified @sptep, @pt_protect indicates whether
c126d94f 1161 * spte write-protection is caused by protecting shadow page table.
49fde340 1162 *
b4619660 1163 * Note: write protection is difference between dirty logging and spte
49fde340
XG
1164 * protection:
1165 * - for dirty logging, the spte can be set to writable at anytime if
1166 * its dirty bitmap is properly set.
1167 * - for spte protection, the spte can be writable only after unsync-ing
1168 * shadow page.
8e22f955 1169 *
c126d94f 1170 * Return true if tlb need be flushed.
8e22f955 1171 */
c4f138b4 1172static bool spte_write_protect(u64 *sptep, bool pt_protect)
d13bc5b5
XG
1173{
1174 u64 spte = *sptep;
1175
49fde340 1176 if (!is_writable_pte(spte) &&
ea4114bc 1177 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
d13bc5b5
XG
1178 return false;
1179
805a0f83 1180 rmap_printk("spte %p %llx\n", sptep, *sptep);
d13bc5b5 1181
49fde340 1182 if (pt_protect)
5fc3424f 1183 spte &= ~shadow_mmu_writable_mask;
d13bc5b5 1184 spte = spte & ~PT_WRITABLE_MASK;
49fde340 1185
c126d94f 1186 return mmu_spte_update(sptep, spte);
d13bc5b5
XG
1187}
1188
018aabb5
TY
1189static bool __rmap_write_protect(struct kvm *kvm,
1190 struct kvm_rmap_head *rmap_head,
245c3912 1191 bool pt_protect)
98348e95 1192{
1e3f42f0
TY
1193 u64 *sptep;
1194 struct rmap_iterator iter;
d13bc5b5 1195 bool flush = false;
374cbac0 1196
018aabb5 1197 for_each_rmap_spte(rmap_head, &iter, sptep)
c4f138b4 1198 flush |= spte_write_protect(sptep, pt_protect);
855149aa 1199
d13bc5b5 1200 return flush;
a0ed4607
TY
1201}
1202
c4f138b4 1203static bool spte_clear_dirty(u64 *sptep)
f4b4b180
KH
1204{
1205 u64 spte = *sptep;
1206
805a0f83 1207 rmap_printk("spte %p %llx\n", sptep, *sptep);
f4b4b180 1208
1f4e5fc8 1209 MMU_WARN_ON(!spte_ad_enabled(spte));
f4b4b180 1210 spte &= ~shadow_dirty_mask;
f4b4b180
KH
1211 return mmu_spte_update(sptep, spte);
1212}
1213
1f4e5fc8 1214static bool spte_wrprot_for_clear_dirty(u64 *sptep)
ac8d57e5
PF
1215{
1216 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1217 (unsigned long *)sptep);
1f4e5fc8 1218 if (was_writable && !spte_ad_enabled(*sptep))
ac8d57e5
PF
1219 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1220
1221 return was_writable;
1222}
1223
1224/*
1225 * Gets the GFN ready for another round of dirty logging by clearing the
1226 * - D bit on ad-enabled SPTEs, and
1227 * - W bit on ad-disabled SPTEs.
1228 * Returns true iff any D or W bits were cleared.
1229 */
0a234f5d 1230static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
269e9552 1231 const struct kvm_memory_slot *slot)
f4b4b180
KH
1232{
1233 u64 *sptep;
1234 struct rmap_iterator iter;
1235 bool flush = false;
1236
018aabb5 1237 for_each_rmap_spte(rmap_head, &iter, sptep)
1f4e5fc8
PB
1238 if (spte_ad_need_write_protect(*sptep))
1239 flush |= spte_wrprot_for_clear_dirty(sptep);
ac8d57e5 1240 else
1f4e5fc8 1241 flush |= spte_clear_dirty(sptep);
f4b4b180
KH
1242
1243 return flush;
1244}
1245
5dc99b23 1246/**
3b0f1d01 1247 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
5dc99b23
TY
1248 * @kvm: kvm instance
1249 * @slot: slot to protect
1250 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1251 * @mask: indicates which pages we should protect
1252 *
89212919 1253 * Used when we do not need to care about huge page mappings.
5dc99b23 1254 */
3b0f1d01 1255static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
5dc99b23
TY
1256 struct kvm_memory_slot *slot,
1257 gfn_t gfn_offset, unsigned long mask)
a0ed4607 1258{
018aabb5 1259 struct kvm_rmap_head *rmap_head;
a0ed4607 1260
897218ff 1261 if (is_tdp_mmu_enabled(kvm))
a6a0b05d
BG
1262 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1263 slot->base_gfn + gfn_offset, mask, true);
e2209710
BG
1264
1265 if (!kvm_memslots_have_rmaps(kvm))
1266 return;
1267
5dc99b23 1268 while (mask) {
018aabb5 1269 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
3bae0459 1270 PG_LEVEL_4K, slot);
018aabb5 1271 __rmap_write_protect(kvm, rmap_head, false);
05da4558 1272
5dc99b23
TY
1273 /* clear the first set bit */
1274 mask &= mask - 1;
1275 }
374cbac0
AK
1276}
1277
f4b4b180 1278/**
ac8d57e5
PF
1279 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1280 * protect the page if the D-bit isn't supported.
f4b4b180
KH
1281 * @kvm: kvm instance
1282 * @slot: slot to clear D-bit
1283 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1284 * @mask: indicates which pages we should clear D-bit
1285 *
1286 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1287 */
a018eba5
SC
1288static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1289 struct kvm_memory_slot *slot,
1290 gfn_t gfn_offset, unsigned long mask)
f4b4b180 1291{
018aabb5 1292 struct kvm_rmap_head *rmap_head;
f4b4b180 1293
897218ff 1294 if (is_tdp_mmu_enabled(kvm))
a6a0b05d
BG
1295 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1296 slot->base_gfn + gfn_offset, mask, false);
e2209710
BG
1297
1298 if (!kvm_memslots_have_rmaps(kvm))
1299 return;
1300
f4b4b180 1301 while (mask) {
018aabb5 1302 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
3bae0459 1303 PG_LEVEL_4K, slot);
0a234f5d 1304 __rmap_clear_dirty(kvm, rmap_head, slot);
f4b4b180
KH
1305
1306 /* clear the first set bit */
1307 mask &= mask - 1;
1308 }
1309}
f4b4b180 1310
3b0f1d01
KH
1311/**
1312 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1313 * PT level pages.
1314 *
1315 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1316 * enable dirty logging for them.
1317 *
89212919
KZ
1318 * We need to care about huge page mappings: e.g. during dirty logging we may
1319 * have such mappings.
3b0f1d01
KH
1320 */
1321void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1322 struct kvm_memory_slot *slot,
1323 gfn_t gfn_offset, unsigned long mask)
1324{
89212919
KZ
1325 /*
1326 * Huge pages are NOT write protected when we start dirty logging in
1327 * initially-all-set mode; must write protect them here so that they
1328 * are split to 4K on the first write.
1329 *
1330 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1331 * of memslot has no such restriction, so the range can cross two large
1332 * pages.
1333 */
1334 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1335 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1336 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1337
1338 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1339
1340 /* Cross two large pages? */
1341 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1342 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1343 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1344 PG_LEVEL_2M);
1345 }
1346
1347 /* Now handle 4K PTEs. */
a018eba5
SC
1348 if (kvm_x86_ops.cpu_dirty_log_size)
1349 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
88178fd4
KH
1350 else
1351 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
3b0f1d01
KH
1352}
1353
fb04a1ed
PX
1354int kvm_cpu_dirty_log_size(void)
1355{
6dd03800 1356 return kvm_x86_ops.cpu_dirty_log_size;
fb04a1ed
PX
1357}
1358
aeecee2e 1359bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
3ad93562
KZ
1360 struct kvm_memory_slot *slot, u64 gfn,
1361 int min_level)
95d4c16c 1362{
018aabb5 1363 struct kvm_rmap_head *rmap_head;
5dc99b23 1364 int i;
2f84569f 1365 bool write_protected = false;
95d4c16c 1366
e2209710
BG
1367 if (kvm_memslots_have_rmaps(kvm)) {
1368 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1369 rmap_head = __gfn_to_rmap(gfn, i, slot);
1370 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1371 }
5dc99b23
TY
1372 }
1373
897218ff 1374 if (is_tdp_mmu_enabled(kvm))
46044f72 1375 write_protected |=
3ad93562 1376 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
46044f72 1377
5dc99b23 1378 return write_protected;
95d4c16c
TY
1379}
1380
aeecee2e
XG
1381static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1382{
1383 struct kvm_memory_slot *slot;
1384
1385 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3ad93562 1386 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
aeecee2e
XG
1387}
1388
0a234f5d 1389static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
269e9552 1390 const struct kvm_memory_slot *slot)
e930bffe 1391{
1e3f42f0
TY
1392 u64 *sptep;
1393 struct rmap_iterator iter;
6a49f85c 1394 bool flush = false;
e930bffe 1395
018aabb5 1396 while ((sptep = rmap_get_first(rmap_head, &iter))) {
805a0f83 1397 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1e3f42f0 1398
e7912386 1399 pte_list_remove(rmap_head, sptep);
6a49f85c 1400 flush = true;
e930bffe 1401 }
1e3f42f0 1402
6a49f85c
XG
1403 return flush;
1404}
1405
3039bcc7
SC
1406static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1407 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1408 pte_t unused)
6a49f85c 1409{
0a234f5d 1410 return kvm_zap_rmapp(kvm, rmap_head, slot);
e930bffe
AA
1411}
1412
3039bcc7
SC
1413static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1414 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1415 pte_t pte)
3da0dd43 1416{
1e3f42f0
TY
1417 u64 *sptep;
1418 struct rmap_iterator iter;
3da0dd43 1419 int need_flush = 0;
1e3f42f0 1420 u64 new_spte;
ba049e93 1421 kvm_pfn_t new_pfn;
3da0dd43 1422
3039bcc7
SC
1423 WARN_ON(pte_huge(pte));
1424 new_pfn = pte_pfn(pte);
1e3f42f0 1425
0d536790 1426restart:
018aabb5 1427 for_each_rmap_spte(rmap_head, &iter, sptep) {
805a0f83 1428 rmap_printk("spte %p %llx gfn %llx (%d)\n",
f160c7b7 1429 sptep, *sptep, gfn, level);
1e3f42f0 1430
3da0dd43 1431 need_flush = 1;
1e3f42f0 1432
3039bcc7 1433 if (pte_write(pte)) {
e7912386 1434 pte_list_remove(rmap_head, sptep);
0d536790 1435 goto restart;
3da0dd43 1436 } else {
cb3eedab
PB
1437 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1438 *sptep, new_pfn);
1e3f42f0
TY
1439
1440 mmu_spte_clear_track_bits(sptep);
1441 mmu_spte_set(sptep, new_spte);
3da0dd43
IE
1442 }
1443 }
1e3f42f0 1444
3cc5ea94
LT
1445 if (need_flush && kvm_available_flush_tlb_with_range()) {
1446 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1447 return 0;
1448 }
1449
0cf853c5 1450 return need_flush;
3da0dd43
IE
1451}
1452
6ce1f4e2
XG
1453struct slot_rmap_walk_iterator {
1454 /* input fields. */
269e9552 1455 const struct kvm_memory_slot *slot;
6ce1f4e2
XG
1456 gfn_t start_gfn;
1457 gfn_t end_gfn;
1458 int start_level;
1459 int end_level;
1460
1461 /* output fields. */
1462 gfn_t gfn;
018aabb5 1463 struct kvm_rmap_head *rmap;
6ce1f4e2
XG
1464 int level;
1465
1466 /* private field. */
018aabb5 1467 struct kvm_rmap_head *end_rmap;
6ce1f4e2
XG
1468};
1469
1470static void
1471rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1472{
1473 iterator->level = level;
1474 iterator->gfn = iterator->start_gfn;
1475 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1476 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1477 iterator->slot);
1478}
1479
1480static void
1481slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
269e9552 1482 const struct kvm_memory_slot *slot, int start_level,
6ce1f4e2
XG
1483 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1484{
1485 iterator->slot = slot;
1486 iterator->start_level = start_level;
1487 iterator->end_level = end_level;
1488 iterator->start_gfn = start_gfn;
1489 iterator->end_gfn = end_gfn;
1490
1491 rmap_walk_init_level(iterator, iterator->start_level);
1492}
1493
1494static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1495{
1496 return !!iterator->rmap;
1497}
1498
1499static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1500{
1501 if (++iterator->rmap <= iterator->end_rmap) {
1502 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1503 return;
1504 }
1505
1506 if (++iterator->level > iterator->end_level) {
1507 iterator->rmap = NULL;
1508 return;
1509 }
1510
1511 rmap_walk_init_level(iterator, iterator->level);
1512}
1513
1514#define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1515 _start_gfn, _end_gfn, _iter_) \
1516 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1517 _end_level_, _start_gfn, _end_gfn); \
1518 slot_rmap_walk_okay(_iter_); \
1519 slot_rmap_walk_next(_iter_))
1520
3039bcc7
SC
1521typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1522 struct kvm_memory_slot *slot, gfn_t gfn,
1523 int level, pte_t pte);
c1b91493 1524
3039bcc7
SC
1525static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1526 struct kvm_gfn_range *range,
1527 rmap_handler_t handler)
e930bffe 1528{
6ce1f4e2 1529 struct slot_rmap_walk_iterator iterator;
3039bcc7 1530 bool ret = false;
e930bffe 1531
3039bcc7
SC
1532 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1533 range->start, range->end - 1, &iterator)
1534 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1535 iterator.level, range->pte);
e930bffe 1536
f395302e 1537 return ret;
e930bffe
AA
1538}
1539
3039bcc7 1540bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
84504ef3 1541{
e2209710 1542 bool flush = false;
063afacd 1543
e2209710
BG
1544 if (kvm_memslots_have_rmaps(kvm))
1545 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
063afacd 1546
897218ff 1547 if (is_tdp_mmu_enabled(kvm))
3039bcc7 1548 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
063afacd 1549
3039bcc7 1550 return flush;
b3ae2096
TY
1551}
1552
3039bcc7 1553bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
3da0dd43 1554{
e2209710 1555 bool flush = false;
1d8dd6b3 1556
e2209710
BG
1557 if (kvm_memslots_have_rmaps(kvm))
1558 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1d8dd6b3 1559
897218ff 1560 if (is_tdp_mmu_enabled(kvm))
3039bcc7 1561 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1d8dd6b3 1562
3039bcc7 1563 return flush;
e930bffe
AA
1564}
1565
3039bcc7
SC
1566static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1567 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1568 pte_t unused)
e930bffe 1569{
1e3f42f0 1570 u64 *sptep;
3f649ab7 1571 struct rmap_iterator iter;
e930bffe
AA
1572 int young = 0;
1573
f160c7b7
JS
1574 for_each_rmap_spte(rmap_head, &iter, sptep)
1575 young |= mmu_spte_age(sptep);
0d536790 1576
e930bffe
AA
1577 return young;
1578}
1579
3039bcc7
SC
1580static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1581 struct kvm_memory_slot *slot, gfn_t gfn,
1582 int level, pte_t unused)
8ee53820 1583{
1e3f42f0
TY
1584 u64 *sptep;
1585 struct rmap_iterator iter;
8ee53820 1586
83ef6c81
JS
1587 for_each_rmap_spte(rmap_head, &iter, sptep)
1588 if (is_accessed_spte(*sptep))
1589 return 1;
83ef6c81 1590 return 0;
8ee53820
AA
1591}
1592
53a27b39
MT
1593#define RMAP_RECYCLE_THRESHOLD 1000
1594
852e3c19 1595static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39 1596{
018aabb5 1597 struct kvm_rmap_head *rmap_head;
852e3c19
JR
1598 struct kvm_mmu_page *sp;
1599
57354682 1600 sp = sptep_to_sp(spte);
53a27b39 1601
018aabb5 1602 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
53a27b39 1603
3039bcc7 1604 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
c3134ce2
LT
1605 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1606 KVM_PAGES_PER_HPAGE(sp->role.level));
53a27b39
MT
1607}
1608
3039bcc7 1609bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
e930bffe 1610{
e2209710 1611 bool young = false;
3039bcc7 1612
e2209710
BG
1613 if (kvm_memslots_have_rmaps(kvm))
1614 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
f8e14497 1615
897218ff 1616 if (is_tdp_mmu_enabled(kvm))
3039bcc7 1617 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
f8e14497
BG
1618
1619 return young;
e930bffe
AA
1620}
1621
3039bcc7 1622bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
8ee53820 1623{
e2209710 1624 bool young = false;
3039bcc7 1625
e2209710
BG
1626 if (kvm_memslots_have_rmaps(kvm))
1627 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
f8e14497 1628
897218ff 1629 if (is_tdp_mmu_enabled(kvm))
3039bcc7 1630 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
f8e14497
BG
1631
1632 return young;
8ee53820
AA
1633}
1634
d6c69ee9 1635#ifdef MMU_DEBUG
47ad8e68 1636static int is_empty_shadow_page(u64 *spt)
6aa8b732 1637{
139bdb2d
AK
1638 u64 *pos;
1639 u64 *end;
1640
47ad8e68 1641 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 1642 if (is_shadow_present_pte(*pos)) {
b8688d51 1643 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 1644 pos, *pos);
6aa8b732 1645 return 0;
139bdb2d 1646 }
6aa8b732
AK
1647 return 1;
1648}
d6c69ee9 1649#endif
6aa8b732 1650
45221ab6
DH
1651/*
1652 * This value is the sum of all of the kvm instances's
1653 * kvm->arch.n_used_mmu_pages values. We need a global,
1654 * aggregate version in order to make the slab shrinker
1655 * faster
1656 */
bc8a3d89 1657static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
45221ab6
DH
1658{
1659 kvm->arch.n_used_mmu_pages += nr;
1660 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1661}
1662
834be0d8 1663static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
260746c0 1664{
fa4a2c08 1665 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
7775834a 1666 hlist_del(&sp->hash_link);
bd4c86ea
XG
1667 list_del(&sp->link);
1668 free_page((unsigned long)sp->spt);
834be0d8
GN
1669 if (!sp->role.direct)
1670 free_page((unsigned long)sp->gfns);
e8ad9a70 1671 kmem_cache_free(mmu_page_header_cache, sp);
260746c0
AK
1672}
1673
cea0f0e7
AK
1674static unsigned kvm_page_table_hashfn(gfn_t gfn)
1675{
114df303 1676 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
cea0f0e7
AK
1677}
1678
714b93da 1679static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 1680 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1681{
cea0f0e7
AK
1682 if (!parent_pte)
1683 return;
cea0f0e7 1684
67052b35 1685 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
cea0f0e7
AK
1686}
1687
4db35314 1688static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK
1689 u64 *parent_pte)
1690{
8daf3462 1691 __pte_list_remove(parent_pte, &sp->parent_ptes);
cea0f0e7
AK
1692}
1693
bcdd9a93
XG
1694static void drop_parent_pte(struct kvm_mmu_page *sp,
1695 u64 *parent_pte)
1696{
1697 mmu_page_remove_parent_pte(sp, parent_pte);
1df9f2dc 1698 mmu_spte_clear_no_track(parent_pte);
bcdd9a93
XG
1699}
1700
47005792 1701static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
ad8cfbe3 1702{
67052b35 1703 struct kvm_mmu_page *sp;
7ddca7e4 1704
94ce87ef
SC
1705 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1706 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
67052b35 1707 if (!direct)
94ce87ef 1708 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
67052b35 1709 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
002c5f73
SC
1710
1711 /*
1712 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1713 * depends on valid pages being added to the head of the list. See
1714 * comments in kvm_zap_obsolete_pages().
1715 */
ca333add 1716 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
67052b35 1717 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
67052b35
XG
1718 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1719 return sp;
ad8cfbe3
MT
1720}
1721
67052b35 1722static void mark_unsync(u64 *spte);
1047df1f 1723static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1724{
74c4e63a
TY
1725 u64 *sptep;
1726 struct rmap_iterator iter;
1727
1728 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1729 mark_unsync(sptep);
1730 }
0074ff63
MT
1731}
1732
67052b35 1733static void mark_unsync(u64 *spte)
0074ff63 1734{
67052b35 1735 struct kvm_mmu_page *sp;
1047df1f 1736 unsigned int index;
0074ff63 1737
57354682 1738 sp = sptep_to_sp(spte);
1047df1f
XG
1739 index = spte - sp->spt;
1740 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
0074ff63 1741 return;
1047df1f 1742 if (sp->unsync_children++)
0074ff63 1743 return;
1047df1f 1744 kvm_mmu_mark_parents_unsync(sp);
0074ff63
MT
1745}
1746
e8bc217a 1747static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
a4a8e6f7 1748 struct kvm_mmu_page *sp)
e8bc217a 1749{
1f50f1b3 1750 return 0;
e8bc217a
MT
1751}
1752
60c8aec6
MT
1753#define KVM_PAGE_ARRAY_NR 16
1754
1755struct kvm_mmu_pages {
1756 struct mmu_page_and_offset {
1757 struct kvm_mmu_page *sp;
1758 unsigned int idx;
1759 } page[KVM_PAGE_ARRAY_NR];
1760 unsigned int nr;
1761};
1762
cded19f3
HE
1763static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1764 int idx)
4731d4c7 1765{
60c8aec6 1766 int i;
4731d4c7 1767
60c8aec6
MT
1768 if (sp->unsync)
1769 for (i=0; i < pvec->nr; i++)
1770 if (pvec->page[i].sp == sp)
1771 return 0;
1772
1773 pvec->page[pvec->nr].sp = sp;
1774 pvec->page[pvec->nr].idx = idx;
1775 pvec->nr++;
1776 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1777}
1778
fd951457
TY
1779static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1780{
1781 --sp->unsync_children;
1782 WARN_ON((int)sp->unsync_children < 0);
1783 __clear_bit(idx, sp->unsync_child_bitmap);
1784}
1785
60c8aec6
MT
1786static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1787 struct kvm_mmu_pages *pvec)
1788{
1789 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1790
37178b8b 1791 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
7a8f1a74 1792 struct kvm_mmu_page *child;
4731d4c7
MT
1793 u64 ent = sp->spt[i];
1794
fd951457
TY
1795 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1796 clear_unsync_child_bit(sp, i);
1797 continue;
1798 }
7a8f1a74 1799
e47c4aee 1800 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
7a8f1a74
XG
1801
1802 if (child->unsync_children) {
1803 if (mmu_pages_add(pvec, child, i))
1804 return -ENOSPC;
1805
1806 ret = __mmu_unsync_walk(child, pvec);
fd951457
TY
1807 if (!ret) {
1808 clear_unsync_child_bit(sp, i);
1809 continue;
1810 } else if (ret > 0) {
7a8f1a74 1811 nr_unsync_leaf += ret;
fd951457 1812 } else
7a8f1a74
XG
1813 return ret;
1814 } else if (child->unsync) {
1815 nr_unsync_leaf++;
1816 if (mmu_pages_add(pvec, child, i))
1817 return -ENOSPC;
1818 } else
fd951457 1819 clear_unsync_child_bit(sp, i);
4731d4c7
MT
1820 }
1821
60c8aec6
MT
1822 return nr_unsync_leaf;
1823}
1824
e23d3fef
XG
1825#define INVALID_INDEX (-1)
1826
60c8aec6
MT
1827static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1828 struct kvm_mmu_pages *pvec)
1829{
0a47cd85 1830 pvec->nr = 0;
60c8aec6
MT
1831 if (!sp->unsync_children)
1832 return 0;
1833
e23d3fef 1834 mmu_pages_add(pvec, sp, INVALID_INDEX);
60c8aec6 1835 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT
1836}
1837
4731d4c7
MT
1838static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1839{
1840 WARN_ON(!sp->unsync);
5e1b3ddb 1841 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT
1842 sp->unsync = 0;
1843 --kvm->stat.mmu_unsync;
1844}
1845
83cdb568
SC
1846static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1847 struct list_head *invalid_list);
7775834a
XG
1848static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1849 struct list_head *invalid_list);
4731d4c7 1850
ac101b7c
SC
1851#define for_each_valid_sp(_kvm, _sp, _list) \
1852 hlist_for_each_entry(_sp, _list, hash_link) \
fac026da 1853 if (is_obsolete_sp((_kvm), (_sp))) { \
f3414bc7 1854 } else
1044b030
TY
1855
1856#define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
ac101b7c
SC
1857 for_each_valid_sp(_kvm, _sp, \
1858 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
f3414bc7 1859 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
7ae680eb 1860
479a1efc
SC
1861static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1862 struct list_head *invalid_list)
4731d4c7 1863{
2640b086 1864 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
d98ba053 1865 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1f50f1b3 1866 return false;
4731d4c7
MT
1867 }
1868
1f50f1b3 1869 return true;
4731d4c7
MT
1870}
1871
a2113634
SC
1872static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1873 struct list_head *invalid_list,
1874 bool remote_flush)
1875{
cfd32acf 1876 if (!remote_flush && list_empty(invalid_list))
a2113634
SC
1877 return false;
1878
1879 if (!list_empty(invalid_list))
1880 kvm_mmu_commit_zap_page(kvm, invalid_list);
1881 else
1882 kvm_flush_remote_tlbs(kvm);
1883 return true;
1884}
1885
35a70510
PB
1886static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1887 struct list_head *invalid_list,
1888 bool remote_flush, bool local_flush)
1d9dc7e0 1889{
a2113634 1890 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
35a70510 1891 return;
d98ba053 1892
a2113634 1893 if (local_flush)
8c8560b8 1894 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1d9dc7e0
XG
1895}
1896
e37fa785
XG
1897#ifdef CONFIG_KVM_MMU_AUDIT
1898#include "mmu_audit.c"
1899#else
1900static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1901static void mmu_audit_disable(void) { }
1902#endif
1903
002c5f73
SC
1904static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1905{
fac026da
SC
1906 return sp->role.invalid ||
1907 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
002c5f73
SC
1908}
1909
60c8aec6 1910struct mmu_page_path {
2a7266a8
YZ
1911 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1912 unsigned int idx[PT64_ROOT_MAX_LEVEL];
4731d4c7
MT
1913};
1914
60c8aec6 1915#define for_each_sp(pvec, sp, parents, i) \
0a47cd85 1916 for (i = mmu_pages_first(&pvec, &parents); \
60c8aec6
MT
1917 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1918 i = mmu_pages_next(&pvec, &parents, i))
1919
cded19f3
HE
1920static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1921 struct mmu_page_path *parents,
1922 int i)
60c8aec6
MT
1923{
1924 int n;
1925
1926 for (n = i+1; n < pvec->nr; n++) {
1927 struct kvm_mmu_page *sp = pvec->page[n].sp;
0a47cd85
PB
1928 unsigned idx = pvec->page[n].idx;
1929 int level = sp->role.level;
60c8aec6 1930
0a47cd85 1931 parents->idx[level-1] = idx;
3bae0459 1932 if (level == PG_LEVEL_4K)
0a47cd85 1933 break;
60c8aec6 1934
0a47cd85 1935 parents->parent[level-2] = sp;
60c8aec6
MT
1936 }
1937
1938 return n;
1939}
1940
0a47cd85
PB
1941static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1942 struct mmu_page_path *parents)
1943{
1944 struct kvm_mmu_page *sp;
1945 int level;
1946
1947 if (pvec->nr == 0)
1948 return 0;
1949
e23d3fef
XG
1950 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1951
0a47cd85
PB
1952 sp = pvec->page[0].sp;
1953 level = sp->role.level;
3bae0459 1954 WARN_ON(level == PG_LEVEL_4K);
0a47cd85
PB
1955
1956 parents->parent[level-2] = sp;
1957
1958 /* Also set up a sentinel. Further entries in pvec are all
1959 * children of sp, so this element is never overwritten.
1960 */
1961 parents->parent[level-1] = NULL;
1962 return mmu_pages_next(pvec, parents, 0);
1963}
1964
cded19f3 1965static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1966{
60c8aec6
MT
1967 struct kvm_mmu_page *sp;
1968 unsigned int level = 0;
1969
1970 do {
1971 unsigned int idx = parents->idx[level];
60c8aec6
MT
1972 sp = parents->parent[level];
1973 if (!sp)
1974 return;
1975
e23d3fef 1976 WARN_ON(idx == INVALID_INDEX);
fd951457 1977 clear_unsync_child_bit(sp, idx);
60c8aec6 1978 level++;
0a47cd85 1979 } while (!sp->unsync_children);
60c8aec6 1980}
4731d4c7 1981
60c8aec6
MT
1982static void mmu_sync_children(struct kvm_vcpu *vcpu,
1983 struct kvm_mmu_page *parent)
1984{
1985 int i;
1986 struct kvm_mmu_page *sp;
1987 struct mmu_page_path parents;
1988 struct kvm_mmu_pages pages;
d98ba053 1989 LIST_HEAD(invalid_list);
50c9e6f3 1990 bool flush = false;
60c8aec6 1991
60c8aec6 1992 while (mmu_unsync_walk(parent, &pages)) {
2f84569f 1993 bool protected = false;
b1a36821
MT
1994
1995 for_each_sp(pages, sp, parents, i)
54bf36aa 1996 protected |= rmap_write_protect(vcpu, sp->gfn);
b1a36821 1997
50c9e6f3 1998 if (protected) {
b1a36821 1999 kvm_flush_remote_tlbs(vcpu->kvm);
50c9e6f3
PB
2000 flush = false;
2001 }
b1a36821 2002
60c8aec6 2003 for_each_sp(pages, sp, parents, i) {
479a1efc 2004 kvm_unlink_unsync_page(vcpu->kvm, sp);
1f50f1b3 2005 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
60c8aec6
MT
2006 mmu_pages_clear_parents(&parents);
2007 }
531810ca 2008 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
50c9e6f3 2009 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
531810ca 2010 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
50c9e6f3
PB
2011 flush = false;
2012 }
60c8aec6 2013 }
50c9e6f3
PB
2014
2015 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
4731d4c7
MT
2016}
2017
a30f47cb
XG
2018static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2019{
e5691a81 2020 atomic_set(&sp->write_flooding_count, 0);
a30f47cb
XG
2021}
2022
2023static void clear_sp_write_flooding_count(u64 *spte)
2024{
57354682 2025 __clear_sp_write_flooding_count(sptep_to_sp(spte));
a30f47cb
XG
2026}
2027
cea0f0e7
AK
2028static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2029 gfn_t gfn,
2030 gva_t gaddr,
2031 unsigned level,
f6e2c02b 2032 int direct,
0a2b64c5 2033 unsigned int access)
cea0f0e7 2034{
fb58a9c3 2035 bool direct_mmu = vcpu->arch.mmu->direct_map;
cea0f0e7 2036 union kvm_mmu_page_role role;
ac101b7c 2037 struct hlist_head *sp_list;
cea0f0e7 2038 unsigned quadrant;
9f1a122f 2039 struct kvm_mmu_page *sp;
f3414bc7 2040 int collisions = 0;
2a74003a 2041 LIST_HEAD(invalid_list);
cea0f0e7 2042
36d9594d 2043 role = vcpu->arch.mmu->mmu_role.base;
cea0f0e7 2044 role.level = level;
f6e2c02b 2045 role.direct = direct;
84b0c8c6 2046 if (role.direct)
47c42e6b 2047 role.gpte_is_8_bytes = true;
41074d07 2048 role.access = access;
fb58a9c3 2049 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK
2050 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2051 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2052 role.quadrant = quadrant;
2053 }
ac101b7c
SC
2054
2055 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2056 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
f3414bc7
DM
2057 if (sp->gfn != gfn) {
2058 collisions++;
2059 continue;
2060 }
2061
ddc16abb
SC
2062 if (sp->role.word != role.word) {
2063 /*
2064 * If the guest is creating an upper-level page, zap
2065 * unsync pages for the same gfn. While it's possible
2066 * the guest is using recursive page tables, in all
2067 * likelihood the guest has stopped using the unsync
2068 * page and is installing a completely unrelated page.
2069 * Unsync pages must not be left as is, because the new
2070 * upper-level page will be write-protected.
2071 */
2072 if (level > PG_LEVEL_4K && sp->unsync)
2073 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2074 &invalid_list);
7ae680eb 2075 continue;
ddc16abb 2076 }
4731d4c7 2077
fb58a9c3
SC
2078 if (direct_mmu)
2079 goto trace_get_page;
2080
2a74003a 2081 if (sp->unsync) {
07dc4f35 2082 /*
479a1efc 2083 * The page is good, but is stale. kvm_sync_page does
07dc4f35
SC
2084 * get the latest guest state, but (unlike mmu_unsync_children)
2085 * it doesn't write-protect the page or mark it synchronized!
2086 * This way the validity of the mapping is ensured, but the
2087 * overhead of write protection is not incurred until the
2088 * guest invalidates the TLB mapping. This allows multiple
2089 * SPs for a single gfn to be unsync.
2090 *
2091 * If the sync fails, the page is zapped. If so, break
2092 * in order to rebuild it.
2a74003a 2093 */
479a1efc 2094 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2a74003a
PB
2095 break;
2096
2097 WARN_ON(!list_empty(&invalid_list));
8c8560b8 2098 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2a74003a 2099 }
e02aa901 2100
98bba238 2101 if (sp->unsync_children)
f6f6195b 2102 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
e02aa901 2103
a30f47cb 2104 __clear_sp_write_flooding_count(sp);
fb58a9c3
SC
2105
2106trace_get_page:
7ae680eb 2107 trace_kvm_mmu_get_page(sp, false);
f3414bc7 2108 goto out;
7ae680eb 2109 }
47005792 2110
dfc5aa00 2111 ++vcpu->kvm->stat.mmu_cache_miss;
47005792
TY
2112
2113 sp = kvm_mmu_alloc_page(vcpu, direct);
2114
4db35314
AK
2115 sp->gfn = gfn;
2116 sp->role = role;
ac101b7c 2117 hlist_add_head(&sp->hash_link, sp_list);
f6e2c02b 2118 if (!direct) {
56ca57f9 2119 account_shadowed(vcpu->kvm, sp);
3bae0459 2120 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
c3134ce2 2121 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
4731d4c7 2122 }
f691fe1d 2123 trace_kvm_mmu_get_page(sp, true);
f3414bc7 2124out:
ddc16abb
SC
2125 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2126
f3414bc7
DM
2127 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2128 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
4db35314 2129 return sp;
cea0f0e7
AK
2130}
2131
7eb77e9f
JS
2132static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2133 struct kvm_vcpu *vcpu, hpa_t root,
2134 u64 addr)
2d11123a
AK
2135{
2136 iterator->addr = addr;
7eb77e9f 2137 iterator->shadow_addr = root;
44dd3ffa 2138 iterator->level = vcpu->arch.mmu->shadow_root_level;
81407ca5 2139
2a7266a8 2140 if (iterator->level == PT64_ROOT_4LEVEL &&
44dd3ffa
VK
2141 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2142 !vcpu->arch.mmu->direct_map)
81407ca5
JR
2143 --iterator->level;
2144
2d11123a 2145 if (iterator->level == PT32E_ROOT_LEVEL) {
7eb77e9f
JS
2146 /*
2147 * prev_root is currently only used for 64-bit hosts. So only
2148 * the active root_hpa is valid here.
2149 */
44dd3ffa 2150 BUG_ON(root != vcpu->arch.mmu->root_hpa);
7eb77e9f 2151
2d11123a 2152 iterator->shadow_addr
44dd3ffa 2153 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2d11123a
AK
2154 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2155 --iterator->level;
2156 if (!iterator->shadow_addr)
2157 iterator->level = 0;
2158 }
2159}
2160
7eb77e9f
JS
2161static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2162 struct kvm_vcpu *vcpu, u64 addr)
2163{
44dd3ffa 2164 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
7eb77e9f
JS
2165 addr);
2166}
2167
2d11123a
AK
2168static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2169{
3bae0459 2170 if (iterator->level < PG_LEVEL_4K)
2d11123a 2171 return false;
4d88954d 2172
2d11123a
AK
2173 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2174 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2175 return true;
2176}
2177
c2a2ac2b
XG
2178static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2179 u64 spte)
2d11123a 2180{
c2a2ac2b 2181 if (is_last_spte(spte, iterator->level)) {
052331be
XG
2182 iterator->level = 0;
2183 return;
2184 }
2185
c2a2ac2b 2186 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2d11123a
AK
2187 --iterator->level;
2188}
2189
c2a2ac2b
XG
2190static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2191{
bb606a9b 2192 __shadow_walk_next(iterator, *iterator->sptep);
c2a2ac2b
XG
2193}
2194
cc4674d0
BG
2195static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2196 struct kvm_mmu_page *sp)
2197{
2198 u64 spte;
2199
2200 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2201
2202 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2203
1df9f2dc 2204 mmu_spte_set(sptep, spte);
98bba238
TY
2205
2206 mmu_page_add_parent_pte(vcpu, sp, sptep);
2207
2208 if (sp->unsync_children || sp->unsync)
2209 mark_unsync(sptep);
32ef26a3
AK
2210}
2211
a357bd22
AK
2212static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2213 unsigned direct_access)
2214{
2215 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2216 struct kvm_mmu_page *child;
2217
2218 /*
2219 * For the direct sp, if the guest pte's dirty bit
2220 * changed form clean to dirty, it will corrupt the
2221 * sp's access: allow writable in the read-only sp,
2222 * so we should update the spte at this point to get
2223 * a new sp with the correct access.
2224 */
e47c4aee 2225 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
a357bd22
AK
2226 if (child->role.access == direct_access)
2227 return;
2228
bcdd9a93 2229 drop_parent_pte(child, sptep);
c3134ce2 2230 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
a357bd22
AK
2231 }
2232}
2233
2de4085c
BG
2234/* Returns the number of zapped non-leaf child shadow pages. */
2235static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2236 u64 *spte, struct list_head *invalid_list)
38e3b2b2
XG
2237{
2238 u64 pte;
2239 struct kvm_mmu_page *child;
2240
2241 pte = *spte;
2242 if (is_shadow_present_pte(pte)) {
505aef8f 2243 if (is_last_spte(pte, sp->role.level)) {
c3707958 2244 drop_spte(kvm, spte);
505aef8f
XG
2245 if (is_large_pte(pte))
2246 --kvm->stat.lpages;
2247 } else {
e47c4aee 2248 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 2249 drop_parent_pte(child, spte);
2de4085c
BG
2250
2251 /*
2252 * Recursively zap nested TDP SPs, parentless SPs are
2253 * unlikely to be used again in the near future. This
2254 * avoids retaining a large number of stale nested SPs.
2255 */
2256 if (tdp_enabled && invalid_list &&
2257 child->role.guest_mode && !child->parent_ptes.val)
2258 return kvm_mmu_prepare_zap_page(kvm, child,
2259 invalid_list);
38e3b2b2 2260 }
ace569e0 2261 } else if (is_mmio_spte(pte)) {
ce88decf 2262 mmu_spte_clear_no_track(spte);
ace569e0 2263 }
2de4085c 2264 return 0;
38e3b2b2
XG
2265}
2266
2de4085c
BG
2267static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2268 struct kvm_mmu_page *sp,
2269 struct list_head *invalid_list)
a436036b 2270{
2de4085c 2271 int zapped = 0;
697fe2e2 2272 unsigned i;
697fe2e2 2273
38e3b2b2 2274 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2de4085c
BG
2275 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2276
2277 return zapped;
a436036b
AK
2278}
2279
31aa2b44 2280static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b 2281{
1e3f42f0
TY
2282 u64 *sptep;
2283 struct rmap_iterator iter;
a436036b 2284
018aabb5 2285 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
1e3f42f0 2286 drop_parent_pte(sp, sptep);
31aa2b44
AK
2287}
2288
60c8aec6 2289static int mmu_zap_unsync_children(struct kvm *kvm,
7775834a
XG
2290 struct kvm_mmu_page *parent,
2291 struct list_head *invalid_list)
4731d4c7 2292{
60c8aec6
MT
2293 int i, zapped = 0;
2294 struct mmu_page_path parents;
2295 struct kvm_mmu_pages pages;
4731d4c7 2296
3bae0459 2297 if (parent->role.level == PG_LEVEL_4K)
4731d4c7 2298 return 0;
60c8aec6 2299
60c8aec6
MT
2300 while (mmu_unsync_walk(parent, &pages)) {
2301 struct kvm_mmu_page *sp;
2302
2303 for_each_sp(pages, sp, parents, i) {
7775834a 2304 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
60c8aec6 2305 mmu_pages_clear_parents(&parents);
77662e00 2306 zapped++;
60c8aec6 2307 }
60c8aec6
MT
2308 }
2309
2310 return zapped;
4731d4c7
MT
2311}
2312
83cdb568
SC
2313static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2314 struct kvm_mmu_page *sp,
2315 struct list_head *invalid_list,
2316 int *nr_zapped)
31aa2b44 2317{
83cdb568 2318 bool list_unstable;
f691fe1d 2319
7775834a 2320 trace_kvm_mmu_prepare_zap_page(sp);
31aa2b44 2321 ++kvm->stat.mmu_shadow_zapped;
83cdb568 2322 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2de4085c 2323 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
31aa2b44 2324 kvm_mmu_unlink_parents(kvm, sp);
5304b8d3 2325
83cdb568
SC
2326 /* Zapping children means active_mmu_pages has become unstable. */
2327 list_unstable = *nr_zapped;
2328
f6e2c02b 2329 if (!sp->role.invalid && !sp->role.direct)
3ed1a478 2330 unaccount_shadowed(kvm, sp);
5304b8d3 2331
4731d4c7
MT
2332 if (sp->unsync)
2333 kvm_unlink_unsync_page(kvm, sp);
4db35314 2334 if (!sp->root_count) {
54a4f023 2335 /* Count self */
83cdb568 2336 (*nr_zapped)++;
f95eec9b
SC
2337
2338 /*
2339 * Already invalid pages (previously active roots) are not on
2340 * the active page list. See list_del() in the "else" case of
2341 * !sp->root_count.
2342 */
2343 if (sp->role.invalid)
2344 list_add(&sp->link, invalid_list);
2345 else
2346 list_move(&sp->link, invalid_list);
aa6bd187 2347 kvm_mod_used_mmu_pages(kvm, -1);
2e53d63a 2348 } else {
f95eec9b
SC
2349 /*
2350 * Remove the active root from the active page list, the root
2351 * will be explicitly freed when the root_count hits zero.
2352 */
2353 list_del(&sp->link);
05988d72 2354
10605204
SC
2355 /*
2356 * Obsolete pages cannot be used on any vCPUs, see the comment
2357 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2358 * treats invalid shadow pages as being obsolete.
2359 */
2360 if (!is_obsolete_sp(kvm, sp))
05988d72 2361 kvm_reload_remote_mmus(kvm);
2e53d63a 2362 }
7775834a 2363
b8e8c830
PB
2364 if (sp->lpage_disallowed)
2365 unaccount_huge_nx_page(kvm, sp);
2366
7775834a 2367 sp->role.invalid = 1;
83cdb568
SC
2368 return list_unstable;
2369}
2370
2371static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2372 struct list_head *invalid_list)
2373{
2374 int nr_zapped;
2375
2376 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2377 return nr_zapped;
a436036b
AK
2378}
2379
7775834a
XG
2380static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2381 struct list_head *invalid_list)
2382{
945315b9 2383 struct kvm_mmu_page *sp, *nsp;
7775834a
XG
2384
2385 if (list_empty(invalid_list))
2386 return;
2387
c142786c 2388 /*
9753f529
LT
2389 * We need to make sure everyone sees our modifications to
2390 * the page tables and see changes to vcpu->mode here. The barrier
2391 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2392 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2393 *
2394 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2395 * guest mode and/or lockless shadow page table walks.
c142786c
AK
2396 */
2397 kvm_flush_remote_tlbs(kvm);
c2a2ac2b 2398
945315b9 2399 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
7775834a 2400 WARN_ON(!sp->role.invalid || sp->root_count);
aa6bd187 2401 kvm_mmu_free_page(sp);
945315b9 2402 }
7775834a
XG
2403}
2404
6b82ef2c
SC
2405static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2406 unsigned long nr_to_zap)
5da59607 2407{
6b82ef2c
SC
2408 unsigned long total_zapped = 0;
2409 struct kvm_mmu_page *sp, *tmp;
ba7888dd 2410 LIST_HEAD(invalid_list);
6b82ef2c
SC
2411 bool unstable;
2412 int nr_zapped;
5da59607
TY
2413
2414 if (list_empty(&kvm->arch.active_mmu_pages))
ba7888dd
SC
2415 return 0;
2416
6b82ef2c 2417restart:
8fc51726 2418 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
6b82ef2c
SC
2419 /*
2420 * Don't zap active root pages, the page itself can't be freed
2421 * and zapping it will just force vCPUs to realloc and reload.
2422 */
2423 if (sp->root_count)
2424 continue;
2425
2426 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2427 &nr_zapped);
2428 total_zapped += nr_zapped;
2429 if (total_zapped >= nr_to_zap)
ba7888dd
SC
2430 break;
2431
6b82ef2c
SC
2432 if (unstable)
2433 goto restart;
ba7888dd 2434 }
5da59607 2435
6b82ef2c
SC
2436 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2437
2438 kvm->stat.mmu_recycled += total_zapped;
2439 return total_zapped;
2440}
2441
afe8d7e6
SC
2442static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2443{
2444 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2445 return kvm->arch.n_max_mmu_pages -
2446 kvm->arch.n_used_mmu_pages;
2447
2448 return 0;
5da59607
TY
2449}
2450
ba7888dd
SC
2451static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2452{
6b82ef2c 2453 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
ba7888dd 2454
6b82ef2c 2455 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
ba7888dd
SC
2456 return 0;
2457
6b82ef2c 2458 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
ba7888dd 2459
6e6ec584
SC
2460 /*
2461 * Note, this check is intentionally soft, it only guarantees that one
2462 * page is available, while the caller may end up allocating as many as
2463 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2464 * exceeding the (arbitrary by default) limit will not harm the host,
c4342633 2465 * being too aggressive may unnecessarily kill the guest, and getting an
6e6ec584
SC
2466 * exact count is far more trouble than it's worth, especially in the
2467 * page fault paths.
2468 */
ba7888dd
SC
2469 if (!kvm_mmu_available_pages(vcpu->kvm))
2470 return -ENOSPC;
2471 return 0;
2472}
2473
82ce2c96
IE
2474/*
2475 * Changing the number of mmu pages allocated to the vm
49d5ca26 2476 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
82ce2c96 2477 */
bc8a3d89 2478void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
82ce2c96 2479{
531810ca 2480 write_lock(&kvm->mmu_lock);
b34cb590 2481
49d5ca26 2482 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
6b82ef2c
SC
2483 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2484 goal_nr_mmu_pages);
82ce2c96 2485
49d5ca26 2486 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
82ce2c96 2487 }
82ce2c96 2488
49d5ca26 2489 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
b34cb590 2490
531810ca 2491 write_unlock(&kvm->mmu_lock);
82ce2c96
IE
2492}
2493
1cb3f3ae 2494int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b 2495{
4db35314 2496 struct kvm_mmu_page *sp;
d98ba053 2497 LIST_HEAD(invalid_list);
a436036b
AK
2498 int r;
2499
9ad17b10 2500 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
a436036b 2501 r = 0;
531810ca 2502 write_lock(&kvm->mmu_lock);
b67bfe0d 2503 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
9ad17b10 2504 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
7ae680eb
XG
2505 sp->role.word);
2506 r = 1;
f41d335a 2507 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
7ae680eb 2508 }
d98ba053 2509 kvm_mmu_commit_zap_page(kvm, &invalid_list);
531810ca 2510 write_unlock(&kvm->mmu_lock);
1cb3f3ae 2511
a436036b 2512 return r;
cea0f0e7 2513}
96ad91ae
SC
2514
2515static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2516{
2517 gpa_t gpa;
2518 int r;
2519
2520 if (vcpu->arch.mmu->direct_map)
2521 return 0;
2522
2523 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2524
2525 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2526
2527 return r;
2528}
cea0f0e7 2529
5c520e90 2530static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
9cf5cf5a
XG
2531{
2532 trace_kvm_mmu_unsync_page(sp);
2533 ++vcpu->kvm->stat.mmu_unsync;
2534 sp->unsync = 1;
2535
2536 kvm_mmu_mark_parents_unsync(sp);
9cf5cf5a
XG
2537}
2538
0337f585
SC
2539/*
2540 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2541 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2542 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2543 * be write-protected.
2544 */
2545int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
4731d4c7 2546{
5c520e90 2547 struct kvm_mmu_page *sp;
4731d4c7 2548
0337f585
SC
2549 /*
2550 * Force write-protection if the page is being tracked. Note, the page
2551 * track machinery is used to write-protect upper-level shadow pages,
2552 * i.e. this guards the role.level == 4K assertion below!
2553 */
3d0c27ad 2554 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
0337f585 2555 return -EPERM;
9cf5cf5a 2556
0337f585
SC
2557 /*
2558 * The page is not write-tracked, mark existing shadow pages unsync
2559 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2560 * that case, KVM must complete emulation of the guest TLB flush before
2561 * allowing shadow pages to become unsync (writable by the guest).
2562 */
5c520e90 2563 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
36a2e677 2564 if (!can_unsync)
0337f585 2565 return -EPERM;
36a2e677 2566
5c520e90
XG
2567 if (sp->unsync)
2568 continue;
9cf5cf5a 2569
3bae0459 2570 WARN_ON(sp->role.level != PG_LEVEL_4K);
5c520e90 2571 kvm_unsync_page(vcpu, sp);
4731d4c7 2572 }
3d0c27ad 2573
578e1c4d
JS
2574 /*
2575 * We need to ensure that the marking of unsync pages is visible
2576 * before the SPTE is updated to allow writes because
2577 * kvm_mmu_sync_roots() checks the unsync flags without holding
2578 * the MMU lock and so can race with this. If the SPTE was updated
2579 * before the page had been marked as unsync-ed, something like the
2580 * following could happen:
2581 *
2582 * CPU 1 CPU 2
2583 * ---------------------------------------------------------------------
2584 * 1.2 Host updates SPTE
2585 * to be writable
2586 * 2.1 Guest writes a GPTE for GVA X.
2587 * (GPTE being in the guest page table shadowed
2588 * by the SP from CPU 1.)
2589 * This reads SPTE during the page table walk.
2590 * Since SPTE.W is read as 1, there is no
2591 * fault.
2592 *
2593 * 2.2 Guest issues TLB flush.
2594 * That causes a VM Exit.
2595 *
0337f585
SC
2596 * 2.3 Walking of unsync pages sees sp->unsync is
2597 * false and skips the page.
578e1c4d
JS
2598 *
2599 * 2.4 Guest accesses GVA X.
2600 * Since the mapping in the SP was not updated,
2601 * so the old mapping for GVA X incorrectly
2602 * gets used.
2603 * 1.1 Host marks SP
2604 * as unsync
2605 * (sp->unsync = true)
2606 *
2607 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2608 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2609 * pairs with this write barrier.
2610 */
2611 smp_wmb();
2612
0337f585 2613 return 0;
4731d4c7
MT
2614}
2615
799a4190
BG
2616static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2617 unsigned int pte_access, int level,
2618 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2619 bool can_unsync, bool host_writable)
2620{
2621 u64 spte;
2622 struct kvm_mmu_page *sp;
2623 int ret;
2624
799a4190
BG
2625 sp = sptep_to_sp(sptep);
2626
2627 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2628 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2629
2630 if (spte & PT_WRITABLE_MASK)
2631 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2632
12703759
SC
2633 if (*sptep == spte)
2634 ret |= SET_SPTE_SPURIOUS;
2635 else if (mmu_spte_update(sptep, spte))
5ce4786f 2636 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
1e73f9dd
MT
2637 return ret;
2638}
2639
0a2b64c5 2640static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
e88b8093 2641 unsigned int pte_access, bool write_fault, int level,
0a2b64c5
BG
2642 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2643 bool host_writable)
1e73f9dd
MT
2644{
2645 int was_rmapped = 0;
53a27b39 2646 int rmap_count;
5ce4786f 2647 int set_spte_ret;
c4371c2a 2648 int ret = RET_PF_FIXED;
c2a4eadf 2649 bool flush = false;
1e73f9dd 2650
f7616203
XG
2651 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2652 *sptep, write_fault, gfn);
1e73f9dd 2653
a54aa15c
SC
2654 if (unlikely(is_noslot_pfn(pfn))) {
2655 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2656 return RET_PF_EMULATE;
2657 }
2658
afd28fe1 2659 if (is_shadow_present_pte(*sptep)) {
1e73f9dd
MT
2660 /*
2661 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2662 * the parent of the now unreachable PTE.
2663 */
3bae0459 2664 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
1e73f9dd 2665 struct kvm_mmu_page *child;
d555c333 2666 u64 pte = *sptep;
1e73f9dd 2667
e47c4aee 2668 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 2669 drop_parent_pte(child, sptep);
c2a4eadf 2670 flush = true;
d555c333 2671 } else if (pfn != spte_to_pfn(*sptep)) {
9ad17b10 2672 pgprintk("hfn old %llx new %llx\n",
d555c333 2673 spte_to_pfn(*sptep), pfn);
c3707958 2674 drop_spte(vcpu->kvm, sptep);
c2a4eadf 2675 flush = true;
6bed6b9e
JR
2676 } else
2677 was_rmapped = 1;
1e73f9dd 2678 }
852e3c19 2679
5ce4786f
JS
2680 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2681 speculative, true, host_writable);
2682 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
1e73f9dd 2683 if (write_fault)
9b8ebbdb 2684 ret = RET_PF_EMULATE;
8c8560b8 2685 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
a378b4e6 2686 }
c3134ce2 2687
c2a4eadf 2688 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
c3134ce2
LT
2689 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2690 KVM_PAGES_PER_HPAGE(level));
1e73f9dd 2691
12703759
SC
2692 /*
2693 * The fault is fully spurious if and only if the new SPTE and old SPTE
2694 * are identical, and emulation is not required.
2695 */
2696 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2697 WARN_ON_ONCE(!was_rmapped);
2698 return RET_PF_SPURIOUS;
2699 }
2700
d555c333 2701 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
335e192a 2702 trace_kvm_mmu_set_spte(level, gfn, sptep);
d555c333 2703 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT
2704 ++vcpu->kvm->stat.lpages;
2705
ffb61bb3 2706 if (is_shadow_present_pte(*sptep)) {
ffb61bb3
XG
2707 if (!was_rmapped) {
2708 rmap_count = rmap_add(vcpu, sptep, gfn);
ec1cf69c
PX
2709 if (rmap_count > vcpu->kvm->stat.max_mmu_rmap_size)
2710 vcpu->kvm->stat.max_mmu_rmap_size = rmap_count;
ffb61bb3
XG
2711 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2712 rmap_recycle(vcpu, sptep, gfn);
2713 }
1c4f1fd6 2714 }
cb9aaa30 2715
9b8ebbdb 2716 return ret;
1c4f1fd6
AK
2717}
2718
ba049e93 2719static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
957ed9ef
XG
2720 bool no_dirty_log)
2721{
2722 struct kvm_memory_slot *slot;
957ed9ef 2723
5d163b1c 2724 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
903816fa 2725 if (!slot)
6c8ee57b 2726 return KVM_PFN_ERR_FAULT;
957ed9ef 2727
037d92dc 2728 return gfn_to_pfn_memslot_atomic(slot, gfn);
957ed9ef
XG
2729}
2730
2731static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2732 struct kvm_mmu_page *sp,
2733 u64 *start, u64 *end)
2734{
2735 struct page *pages[PTE_PREFETCH_NUM];
d9ef13c2 2736 struct kvm_memory_slot *slot;
0a2b64c5 2737 unsigned int access = sp->role.access;
957ed9ef
XG
2738 int i, ret;
2739 gfn_t gfn;
2740
2741 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
d9ef13c2
PB
2742 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2743 if (!slot)
957ed9ef
XG
2744 return -1;
2745
d9ef13c2 2746 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
957ed9ef
XG
2747 if (ret <= 0)
2748 return -1;
2749
43fdcda9 2750 for (i = 0; i < ret; i++, gfn++, start++) {
e88b8093 2751 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
029499b4 2752 page_to_pfn(pages[i]), true, true);
43fdcda9
JS
2753 put_page(pages[i]);
2754 }
957ed9ef
XG
2755
2756 return 0;
2757}
2758
2759static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2760 struct kvm_mmu_page *sp, u64 *sptep)
2761{
2762 u64 *spte, *start = NULL;
2763 int i;
2764
2765 WARN_ON(!sp->role.direct);
2766
2767 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2768 spte = sp->spt + i;
2769
2770 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
c3707958 2771 if (is_shadow_present_pte(*spte) || spte == sptep) {
957ed9ef
XG
2772 if (!start)
2773 continue;
2774 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2775 break;
2776 start = NULL;
2777 } else if (!start)
2778 start = spte;
2779 }
2780}
2781
2782static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2783{
2784 struct kvm_mmu_page *sp;
2785
57354682 2786 sp = sptep_to_sp(sptep);
ac8d57e5 2787
957ed9ef 2788 /*
ac8d57e5
PF
2789 * Without accessed bits, there's no way to distinguish between
2790 * actually accessed translations and prefetched, so disable pte
2791 * prefetch if accessed bits aren't available.
957ed9ef 2792 */
ac8d57e5 2793 if (sp_ad_disabled(sp))
957ed9ef
XG
2794 return;
2795
3bae0459 2796 if (sp->role.level > PG_LEVEL_4K)
957ed9ef
XG
2797 return;
2798
4a42d848
DS
2799 /*
2800 * If addresses are being invalidated, skip prefetching to avoid
2801 * accidentally prefetching those addresses.
2802 */
2803 if (unlikely(vcpu->kvm->mmu_notifier_count))
2804 return;
2805
957ed9ef
XG
2806 __direct_pte_prefetch(vcpu, sp, sptep);
2807}
2808
1b6d9d9e 2809static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
8ca6f063 2810 const struct kvm_memory_slot *slot)
db543216 2811{
db543216
SC
2812 unsigned long hva;
2813 pte_t *pte;
2814 int level;
2815
e851265a 2816 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
3bae0459 2817 return PG_LEVEL_4K;
db543216 2818
293e306e
SC
2819 /*
2820 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2821 * is not solely for performance, it's also necessary to avoid the
2822 * "writable" check in __gfn_to_hva_many(), which will always fail on
2823 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2824 * page fault steps have already verified the guest isn't writing a
2825 * read-only memslot.
2826 */
db543216
SC
2827 hva = __gfn_to_hva_memslot(slot, gfn);
2828
1b6d9d9e 2829 pte = lookup_address_in_mm(kvm->mm, hva, &level);
db543216 2830 if (unlikely(!pte))
3bae0459 2831 return PG_LEVEL_4K;
db543216
SC
2832
2833 return level;
2834}
2835
8ca6f063
BG
2836int kvm_mmu_max_mapping_level(struct kvm *kvm,
2837 const struct kvm_memory_slot *slot, gfn_t gfn,
2838 kvm_pfn_t pfn, int max_level)
1b6d9d9e
SC
2839{
2840 struct kvm_lpage_info *linfo;
2841
2842 max_level = min(max_level, max_huge_page_level);
2843 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2844 linfo = lpage_info_slot(gfn, slot, max_level);
2845 if (!linfo->disallow_lpage)
2846 break;
2847 }
2848
2849 if (max_level == PG_LEVEL_4K)
2850 return PG_LEVEL_4K;
2851
2852 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2853}
2854
bb18842e
BG
2855int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2856 int max_level, kvm_pfn_t *pfnp,
2857 bool huge_page_disallowed, int *req_level)
0885904d 2858{
293e306e 2859 struct kvm_memory_slot *slot;
0885904d 2860 kvm_pfn_t pfn = *pfnp;
17eff019 2861 kvm_pfn_t mask;
83f06fa7 2862 int level;
17eff019 2863
3cf06612
SC
2864 *req_level = PG_LEVEL_4K;
2865
3bae0459
SC
2866 if (unlikely(max_level == PG_LEVEL_4K))
2867 return PG_LEVEL_4K;
17eff019 2868
e851265a 2869 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
3bae0459 2870 return PG_LEVEL_4K;
17eff019 2871
293e306e
SC
2872 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2873 if (!slot)
3bae0459 2874 return PG_LEVEL_4K;
293e306e 2875
1b6d9d9e 2876 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
3bae0459 2877 if (level == PG_LEVEL_4K)
83f06fa7 2878 return level;
17eff019 2879
3cf06612
SC
2880 *req_level = level = min(level, max_level);
2881
2882 /*
2883 * Enforce the iTLB multihit workaround after capturing the requested
2884 * level, which will be used to do precise, accurate accounting.
2885 */
2886 if (huge_page_disallowed)
2887 return PG_LEVEL_4K;
0885904d
SC
2888
2889 /*
17eff019
SC
2890 * mmu_notifier_retry() was successful and mmu_lock is held, so
2891 * the pmd can't be split from under us.
0885904d 2892 */
17eff019
SC
2893 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2894 VM_BUG_ON((gfn & mask) != (pfn & mask));
2895 *pfnp = pfn & ~mask;
83f06fa7
SC
2896
2897 return level;
0885904d
SC
2898}
2899
bb18842e
BG
2900void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2901 kvm_pfn_t *pfnp, int *goal_levelp)
b8e8c830 2902{
bb18842e 2903 int level = *goal_levelp;
b8e8c830 2904
7d945312 2905 if (cur_level == level && level > PG_LEVEL_4K &&
b8e8c830
PB
2906 is_shadow_present_pte(spte) &&
2907 !is_large_pte(spte)) {
2908 /*
2909 * A small SPTE exists for this pfn, but FNAME(fetch)
2910 * and __direct_map would like to create a large PTE
2911 * instead: just force them to go down another level,
2912 * patching back for them into pfn the next 9 bits of
2913 * the address.
2914 */
7d945312
BG
2915 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2916 KVM_PAGES_PER_HPAGE(level - 1);
b8e8c830 2917 *pfnp |= gfn & page_mask;
bb18842e 2918 (*goal_levelp)--;
b8e8c830
PB
2919 }
2920}
2921
6c2fd34f 2922static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
83f06fa7 2923 int map_writable, int max_level, kvm_pfn_t pfn,
6c2fd34f 2924 bool prefault, bool is_tdp)
140754bc 2925{
6c2fd34f
SC
2926 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2927 bool write = error_code & PFERR_WRITE_MASK;
2928 bool exec = error_code & PFERR_FETCH_MASK;
2929 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
3fcf2d1b 2930 struct kvm_shadow_walk_iterator it;
140754bc 2931 struct kvm_mmu_page *sp;
3cf06612 2932 int level, req_level, ret;
3fcf2d1b
PB
2933 gfn_t gfn = gpa >> PAGE_SHIFT;
2934 gfn_t base_gfn = gfn;
6aa8b732 2935
3cf06612
SC
2936 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2937 huge_page_disallowed, &req_level);
4cd071d1 2938
335e192a 2939 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3fcf2d1b 2940 for_each_shadow_entry(vcpu, gpa, it) {
b8e8c830
PB
2941 /*
2942 * We cannot overwrite existing page tables with an NX
2943 * large page, as the leaf could be executable.
2944 */
dcc70651 2945 if (nx_huge_page_workaround_enabled)
7d945312
BG
2946 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2947 &pfn, &level);
b8e8c830 2948
3fcf2d1b
PB
2949 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2950 if (it.level == level)
9f652d21 2951 break;
6aa8b732 2952
3fcf2d1b 2953 drop_large_spte(vcpu, it.sptep);
03fffc54
SC
2954 if (is_shadow_present_pte(*it.sptep))
2955 continue;
2956
2957 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2958 it.level - 1, true, ACC_ALL);
2959
2960 link_shadow_page(vcpu, it.sptep, sp);
2961 if (is_tdp && huge_page_disallowed &&
2962 req_level >= it.level)
2963 account_huge_nx_page(vcpu->kvm, sp);
9f652d21 2964 }
3fcf2d1b
PB
2965
2966 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2967 write, level, base_gfn, pfn, prefault,
2968 map_writable);
12703759
SC
2969 if (ret == RET_PF_SPURIOUS)
2970 return ret;
2971
3fcf2d1b
PB
2972 direct_pte_prefetch(vcpu, it.sptep);
2973 ++vcpu->stat.pf_fixed;
2974 return ret;
6aa8b732
AK
2975}
2976
77db5cbd 2977static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
bf998156 2978{
585a8b9b 2979 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
bf998156
HY
2980}
2981
ba049e93 2982static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
bf998156 2983{
4d8b81ab
XG
2984 /*
2985 * Do not cache the mmio info caused by writing the readonly gfn
2986 * into the spte otherwise read access on readonly gfn also can
2987 * caused mmio page fault and treat it as mmio access.
4d8b81ab
XG
2988 */
2989 if (pfn == KVM_PFN_ERR_RO_FAULT)
9b8ebbdb 2990 return RET_PF_EMULATE;
4d8b81ab 2991
e6c1502b 2992 if (pfn == KVM_PFN_ERR_HWPOISON) {
54bf36aa 2993 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
9b8ebbdb 2994 return RET_PF_RETRY;
d7c55201 2995 }
edba23e5 2996
2c151b25 2997 return -EFAULT;
bf998156
HY
2998}
2999
d7c55201 3000static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
0a2b64c5
BG
3001 kvm_pfn_t pfn, unsigned int access,
3002 int *ret_val)
d7c55201 3003{
d7c55201 3004 /* The pfn is invalid, report the error! */
81c52c56 3005 if (unlikely(is_error_pfn(pfn))) {
d7c55201 3006 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
798e88b3 3007 return true;
d7c55201
XG
3008 }
3009
30ab5901 3010 if (unlikely(is_noslot_pfn(pfn))) {
4af77151
SC
3011 vcpu_cache_mmio_info(vcpu, gva, gfn,
3012 access & shadow_mmio_access_mask);
30ab5901
SC
3013 /*
3014 * If MMIO caching is disabled, emulate immediately without
3015 * touching the shadow page tables as attempting to install an
3016 * MMIO SPTE will just be an expensive nop.
3017 */
3018 if (unlikely(!shadow_mmio_value)) {
3019 *ret_val = RET_PF_EMULATE;
3020 return true;
3021 }
3022 }
d7c55201 3023
798e88b3 3024 return false;
d7c55201
XG
3025}
3026
e5552fd2 3027static bool page_fault_can_be_fast(u32 error_code)
c7ba5b48 3028{
1c118b82
XG
3029 /*
3030 * Do not fix the mmio spte with invalid generation number which
3031 * need to be updated by slow page fault path.
3032 */
3033 if (unlikely(error_code & PFERR_RSVD_MASK))
3034 return false;
3035
f160c7b7
JS
3036 /* See if the page fault is due to an NX violation */
3037 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3038 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3039 return false;
3040
c7ba5b48 3041 /*
f160c7b7
JS
3042 * #PF can be fast if:
3043 * 1. The shadow page table entry is not present, which could mean that
3044 * the fault is potentially caused by access tracking (if enabled).
3045 * 2. The shadow page table entry is present and the fault
3046 * is caused by write-protect, that means we just need change the W
3047 * bit of the spte which can be done out of mmu-lock.
3048 *
3049 * However, if access tracking is disabled we know that a non-present
3050 * page must be a genuine page fault where we have to create a new SPTE.
3051 * So, if access tracking is disabled, we return true only for write
3052 * accesses to a present page.
c7ba5b48 3053 */
c7ba5b48 3054
f160c7b7
JS
3055 return shadow_acc_track_mask != 0 ||
3056 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3057 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
c7ba5b48
XG
3058}
3059
97dceba2
JS
3060/*
3061 * Returns true if the SPTE was fixed successfully. Otherwise,
3062 * someone else modified the SPTE from its original value.
3063 */
c7ba5b48 3064static bool
92a476cb 3065fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d3e328f2 3066 u64 *sptep, u64 old_spte, u64 new_spte)
c7ba5b48 3067{
c7ba5b48
XG
3068 gfn_t gfn;
3069
3070 WARN_ON(!sp->role.direct);
3071
9b51a630
KH
3072 /*
3073 * Theoretically we could also set dirty bit (and flush TLB) here in
3074 * order to eliminate unnecessary PML logging. See comments in
3075 * set_spte. But fast_page_fault is very unlikely to happen with PML
3076 * enabled, so we do not do this. This might result in the same GPA
3077 * to be logged in PML buffer again when the write really happens, and
3078 * eventually to be called by mark_page_dirty twice. But it's also no
3079 * harm. This also avoids the TLB flush needed after setting dirty bit
3080 * so non-PML cases won't be impacted.
3081 *
3082 * Compare with set_spte where instead shadow_dirty_mask is set.
3083 */
f160c7b7 3084 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
97dceba2
JS
3085 return false;
3086
d3e328f2 3087 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
f160c7b7
JS
3088 /*
3089 * The gfn of direct spte is stable since it is
3090 * calculated by sp->gfn.
3091 */
3092 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3093 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3094 }
c7ba5b48
XG
3095
3096 return true;
3097}
3098
d3e328f2
JS
3099static bool is_access_allowed(u32 fault_err_code, u64 spte)
3100{
3101 if (fault_err_code & PFERR_FETCH_MASK)
3102 return is_executable_pte(spte);
3103
3104 if (fault_err_code & PFERR_WRITE_MASK)
3105 return is_writable_pte(spte);
3106
3107 /* Fault was on Read access */
3108 return spte & PT_PRESENT_MASK;
3109}
3110
6e8eb206
DM
3111/*
3112 * Returns the last level spte pointer of the shadow page walk for the given
3113 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3114 * walk could be performed, returns NULL and *spte does not contain valid data.
3115 *
3116 * Contract:
3117 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3118 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3119 */
3120static u64 *fast_pf_get_last_sptep(struct kvm_vcpu *vcpu, gpa_t gpa, u64 *spte)
3121{
3122 struct kvm_shadow_walk_iterator iterator;
3123 u64 old_spte;
3124 u64 *sptep = NULL;
3125
3126 for_each_shadow_entry_lockless(vcpu, gpa, iterator, old_spte) {
3127 sptep = iterator.sptep;
3128 *spte = old_spte;
3129
3130 if (!is_shadow_present_pte(old_spte))
3131 break;
3132 }
3133
3134 return sptep;
3135}
3136
c7ba5b48 3137/*
c4371c2a 3138 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
c7ba5b48 3139 */
76cd325e 3140static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code)
c7ba5b48 3141{
92a476cb 3142 struct kvm_mmu_page *sp;
c4371c2a 3143 int ret = RET_PF_INVALID;
c7ba5b48 3144 u64 spte = 0ull;
6e8eb206 3145 u64 *sptep = NULL;
97dceba2 3146 uint retry_count = 0;
c7ba5b48 3147
e5552fd2 3148 if (!page_fault_can_be_fast(error_code))
c4371c2a 3149 return ret;
c7ba5b48
XG
3150
3151 walk_shadow_page_lockless_begin(vcpu);
c7ba5b48 3152
97dceba2 3153 do {
d3e328f2 3154 u64 new_spte;
c7ba5b48 3155
6e8eb206
DM
3156 if (is_tdp_mmu(vcpu->arch.mmu))
3157 sptep = kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu, gpa, &spte);
3158 else
3159 sptep = fast_pf_get_last_sptep(vcpu, gpa, &spte);
d162f30a 3160
ec89e643
SC
3161 if (!is_shadow_present_pte(spte))
3162 break;
3163
6e8eb206 3164 sp = sptep_to_sp(sptep);
97dceba2
JS
3165 if (!is_last_spte(spte, sp->role.level))
3166 break;
c7ba5b48 3167
97dceba2 3168 /*
f160c7b7
JS
3169 * Check whether the memory access that caused the fault would
3170 * still cause it if it were to be performed right now. If not,
3171 * then this is a spurious fault caused by TLB lazily flushed,
3172 * or some other CPU has already fixed the PTE after the
3173 * current CPU took the fault.
97dceba2
JS
3174 *
3175 * Need not check the access of upper level table entries since
3176 * they are always ACC_ALL.
3177 */
d3e328f2 3178 if (is_access_allowed(error_code, spte)) {
c4371c2a 3179 ret = RET_PF_SPURIOUS;
d3e328f2
JS
3180 break;
3181 }
f160c7b7 3182
d3e328f2
JS
3183 new_spte = spte;
3184
3185 if (is_access_track_spte(spte))
3186 new_spte = restore_acc_track_spte(new_spte);
3187
3188 /*
3189 * Currently, to simplify the code, write-protection can
3190 * be removed in the fast path only if the SPTE was
3191 * write-protected for dirty-logging or access tracking.
3192 */
3193 if ((error_code & PFERR_WRITE_MASK) &&
e6302698 3194 spte_can_locklessly_be_made_writable(spte)) {
d3e328f2 3195 new_spte |= PT_WRITABLE_MASK;
f160c7b7
JS
3196
3197 /*
d3e328f2
JS
3198 * Do not fix write-permission on the large spte. Since
3199 * we only dirty the first page into the dirty-bitmap in
3200 * fast_pf_fix_direct_spte(), other pages are missed
3201 * if its slot has dirty logging enabled.
3202 *
3203 * Instead, we let the slow page fault path create a
3204 * normal spte to fix the access.
3205 *
3206 * See the comments in kvm_arch_commit_memory_region().
f160c7b7 3207 */
3bae0459 3208 if (sp->role.level > PG_LEVEL_4K)
f160c7b7 3209 break;
97dceba2 3210 }
c7ba5b48 3211
f160c7b7 3212 /* Verify that the fault can be handled in the fast path */
d3e328f2
JS
3213 if (new_spte == spte ||
3214 !is_access_allowed(error_code, new_spte))
97dceba2
JS
3215 break;
3216
3217 /*
3218 * Currently, fast page fault only works for direct mapping
3219 * since the gfn is not stable for indirect shadow page. See
3ecad8c2 3220 * Documentation/virt/kvm/locking.rst to get more detail.
97dceba2 3221 */
6e8eb206 3222 if (fast_pf_fix_direct_spte(vcpu, sp, sptep, spte, new_spte)) {
c4371c2a 3223 ret = RET_PF_FIXED;
97dceba2 3224 break;
c4371c2a 3225 }
97dceba2
JS
3226
3227 if (++retry_count > 4) {
3228 printk_once(KERN_WARNING
3229 "kvm: Fast #PF retrying more than 4 times.\n");
3230 break;
3231 }
3232
97dceba2 3233 } while (true);
c126d94f 3234
6e8eb206 3235 trace_fast_page_fault(vcpu, gpa, error_code, sptep, spte, ret);
c7ba5b48
XG
3236 walk_shadow_page_lockless_end(vcpu);
3237
c4371c2a 3238 return ret;
c7ba5b48
XG
3239}
3240
74b566e6
JS
3241static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3242 struct list_head *invalid_list)
17ac10ad 3243{
4db35314 3244 struct kvm_mmu_page *sp;
17ac10ad 3245
74b566e6 3246 if (!VALID_PAGE(*root_hpa))
7b53aa56 3247 return;
35af577a 3248
e47c4aee 3249 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
02c00b3a 3250
2bdb3d84 3251 if (is_tdp_mmu_page(sp))
6103bc07 3252 kvm_tdp_mmu_put_root(kvm, sp, false);
76eb54e7
BG
3253 else if (!--sp->root_count && sp->role.invalid)
3254 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
17ac10ad 3255
74b566e6
JS
3256 *root_hpa = INVALID_PAGE;
3257}
3258
08fb59d8 3259/* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
6a82cd1c
VK
3260void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3261 ulong roots_to_free)
74b566e6 3262{
4d710de9 3263 struct kvm *kvm = vcpu->kvm;
74b566e6
JS
3264 int i;
3265 LIST_HEAD(invalid_list);
08fb59d8 3266 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
74b566e6 3267
b94742c9 3268 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
74b566e6 3269
08fb59d8 3270 /* Before acquiring the MMU lock, see if we need to do any real work. */
b94742c9
JS
3271 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3272 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3273 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3274 VALID_PAGE(mmu->prev_roots[i].hpa))
3275 break;
3276
3277 if (i == KVM_MMU_NUM_PREV_ROOTS)
3278 return;
3279 }
35af577a 3280
531810ca 3281 write_lock(&kvm->mmu_lock);
17ac10ad 3282
b94742c9
JS
3283 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3284 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
4d710de9 3285 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
b94742c9 3286 &invalid_list);
7c390d35 3287
08fb59d8
JS
3288 if (free_active_root) {
3289 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3290 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
4d710de9 3291 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
04d45551 3292 } else if (mmu->pae_root) {
c834e5e4
SC
3293 for (i = 0; i < 4; ++i) {
3294 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3295 continue;
3296
3297 mmu_free_root_page(kvm, &mmu->pae_root[i],
3298 &invalid_list);
3299 mmu->pae_root[i] = INVALID_PAE_ROOT;
3300 }
08fb59d8 3301 }
04d45551 3302 mmu->root_hpa = INVALID_PAGE;
be01e8e2 3303 mmu->root_pgd = 0;
17ac10ad 3304 }
74b566e6 3305
4d710de9 3306 kvm_mmu_commit_zap_page(kvm, &invalid_list);
531810ca 3307 write_unlock(&kvm->mmu_lock);
17ac10ad 3308}
74b566e6 3309EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
17ac10ad 3310
25b62c62
SC
3311void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3312{
3313 unsigned long roots_to_free = 0;
3314 hpa_t root_hpa;
3315 int i;
3316
3317 /*
3318 * This should not be called while L2 is active, L2 can't invalidate
3319 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3320 */
3321 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3322
3323 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3324 root_hpa = mmu->prev_roots[i].hpa;
3325 if (!VALID_PAGE(root_hpa))
3326 continue;
3327
3328 if (!to_shadow_page(root_hpa) ||
3329 to_shadow_page(root_hpa)->role.guest_mode)
3330 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3331 }
3332
3333 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3334}
3335EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3336
3337
8986ecc0
MT
3338static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3339{
3340 int ret = 0;
3341
995decb6 3342 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
a8eeb04a 3343 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8986ecc0
MT
3344 ret = 1;
3345 }
3346
3347 return ret;
3348}
3349
8123f265
SC
3350static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3351 u8 level, bool direct)
651dd37a
JR
3352{
3353 struct kvm_mmu_page *sp;
8123f265 3354
8123f265
SC
3355 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3356 ++sp->root_count;
3357
8123f265
SC
3358 return __pa(sp->spt);
3359}
3360
3361static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3362{
b37233c9
SC
3363 struct kvm_mmu *mmu = vcpu->arch.mmu;
3364 u8 shadow_root_level = mmu->shadow_root_level;
8123f265 3365 hpa_t root;
7ebaf15e 3366 unsigned i;
4a38162e
PB
3367 int r;
3368
3369 write_lock(&vcpu->kvm->mmu_lock);
3370 r = make_mmu_pages_available(vcpu);
3371 if (r < 0)
3372 goto out_unlock;
651dd37a 3373
897218ff 3374 if (is_tdp_mmu_enabled(vcpu->kvm)) {
02c00b3a 3375 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
b37233c9 3376 mmu->root_hpa = root;
02c00b3a 3377 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
6e6ec584 3378 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
b37233c9 3379 mmu->root_hpa = root;
8123f265 3380 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
4a38162e
PB
3381 if (WARN_ON_ONCE(!mmu->pae_root)) {
3382 r = -EIO;
3383 goto out_unlock;
3384 }
73ad1606 3385
651dd37a 3386 for (i = 0; i < 4; ++i) {
c834e5e4 3387 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
651dd37a 3388
8123f265
SC
3389 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3390 i << 30, PT32_ROOT_LEVEL, true);
17e368d9
SC
3391 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3392 shadow_me_mask;
651dd37a 3393 }
b37233c9 3394 mmu->root_hpa = __pa(mmu->pae_root);
73ad1606
SC
3395 } else {
3396 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
4a38162e
PB
3397 r = -EIO;
3398 goto out_unlock;
73ad1606 3399 }
3651c7fc 3400
be01e8e2 3401 /* root_pgd is ignored for direct MMUs. */
b37233c9 3402 mmu->root_pgd = 0;
4a38162e
PB
3403out_unlock:
3404 write_unlock(&vcpu->kvm->mmu_lock);
3405 return r;
651dd37a
JR
3406}
3407
3408static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
17ac10ad 3409{
b37233c9 3410 struct kvm_mmu *mmu = vcpu->arch.mmu;
6e0918ae 3411 u64 pdptrs[4], pm_mask;
be01e8e2 3412 gfn_t root_gfn, root_pgd;
8123f265 3413 hpa_t root;
4a38162e
PB
3414 unsigned i;
3415 int r;
3bb65a22 3416
b37233c9 3417 root_pgd = mmu->get_guest_pgd(vcpu);
be01e8e2 3418 root_gfn = root_pgd >> PAGE_SHIFT;
17ac10ad 3419
651dd37a
JR
3420 if (mmu_check_root(vcpu, root_gfn))
3421 return 1;
3422
4a38162e
PB
3423 /*
3424 * On SVM, reading PDPTRs might access guest memory, which might fault
3425 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3426 */
6e0918ae
SC
3427 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3428 for (i = 0; i < 4; ++i) {
3429 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3430 if (!(pdptrs[i] & PT_PRESENT_MASK))
3431 continue;
3432
3433 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3434 return 1;
3435 }
3436 }
3437
d501f747
BG
3438 r = alloc_all_memslots_rmaps(vcpu->kvm);
3439 if (r)
3440 return r;
3441
4a38162e
PB
3442 write_lock(&vcpu->kvm->mmu_lock);
3443 r = make_mmu_pages_available(vcpu);
3444 if (r < 0)
3445 goto out_unlock;
3446
651dd37a
JR
3447 /*
3448 * Do we shadow a long mode page table? If so we need to
3449 * write-protect the guests page table root.
3450 */
b37233c9 3451 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
8123f265 3452 root = mmu_alloc_root(vcpu, root_gfn, 0,
b37233c9 3453 mmu->shadow_root_level, false);
b37233c9 3454 mmu->root_hpa = root;
be01e8e2 3455 goto set_root_pgd;
17ac10ad 3456 }
f87f9288 3457
4a38162e
PB
3458 if (WARN_ON_ONCE(!mmu->pae_root)) {
3459 r = -EIO;
3460 goto out_unlock;
3461 }
73ad1606 3462
651dd37a
JR
3463 /*
3464 * We shadow a 32 bit page table. This may be a legacy 2-level
81407ca5
JR
3465 * or a PAE 3-level page table. In either case we need to be aware that
3466 * the shadow page table may be a PAE or a long mode page table.
651dd37a 3467 */
17e368d9 3468 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
748e52b9 3469 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
81407ca5
JR
3470 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3471
03ca4589 3472 if (WARN_ON_ONCE(!mmu->pml4_root)) {
4a38162e
PB
3473 r = -EIO;
3474 goto out_unlock;
3475 }
73ad1606 3476
03ca4589 3477 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
04d45551
SC
3478 }
3479
17ac10ad 3480 for (i = 0; i < 4; ++i) {
c834e5e4 3481 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
6e6ec584 3482
b37233c9 3483 if (mmu->root_level == PT32E_ROOT_LEVEL) {
6e0918ae 3484 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
c834e5e4 3485 mmu->pae_root[i] = INVALID_PAE_ROOT;
417726a3
AK
3486 continue;
3487 }
6e0918ae 3488 root_gfn = pdptrs[i] >> PAGE_SHIFT;
5a7388c2 3489 }
8facbbff 3490
8123f265
SC
3491 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3492 PT32_ROOT_LEVEL, false);
b37233c9 3493 mmu->pae_root[i] = root | pm_mask;
17ac10ad 3494 }
81407ca5 3495
ba0a194f 3496 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
03ca4589 3497 mmu->root_hpa = __pa(mmu->pml4_root);
ba0a194f
SC
3498 else
3499 mmu->root_hpa = __pa(mmu->pae_root);
81407ca5 3500
be01e8e2 3501set_root_pgd:
b37233c9 3502 mmu->root_pgd = root_pgd;
4a38162e
PB
3503out_unlock:
3504 write_unlock(&vcpu->kvm->mmu_lock);
ad7dc69a 3505
8986ecc0 3506 return 0;
17ac10ad
AK
3507}
3508
748e52b9
SC
3509static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3510{
3511 struct kvm_mmu *mmu = vcpu->arch.mmu;
03ca4589 3512 u64 *pml4_root, *pae_root;
81407ca5
JR
3513
3514 /*
748e52b9
SC
3515 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3516 * tables are allocated and initialized at root creation as there is no
3517 * equivalent level in the guest's NPT to shadow. Allocate the tables
3518 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
81407ca5 3519 */
748e52b9
SC
3520 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3521 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3522 return 0;
81407ca5 3523
748e52b9
SC
3524 /*
3525 * This mess only works with 4-level paging and needs to be updated to
3526 * work with 5-level paging.
3527 */
3528 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3529 return -EIO;
81407ca5 3530
03ca4589 3531 if (mmu->pae_root && mmu->pml4_root)
748e52b9 3532 return 0;
81407ca5 3533
748e52b9
SC
3534 /*
3535 * The special roots should always be allocated in concert. Yell and
3536 * bail if KVM ends up in a state where only one of the roots is valid.
3537 */
03ca4589 3538 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
748e52b9 3539 return -EIO;
81407ca5 3540
4a98623d
SC
3541 /*
3542 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3543 * doesn't need to be decrypted.
3544 */
748e52b9
SC
3545 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3546 if (!pae_root)
3547 return -ENOMEM;
81407ca5 3548
03ca4589
SC
3549 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3550 if (!pml4_root) {
748e52b9
SC
3551 free_page((unsigned long)pae_root);
3552 return -ENOMEM;
81407ca5
JR
3553 }
3554
748e52b9 3555 mmu->pae_root = pae_root;
03ca4589 3556 mmu->pml4_root = pml4_root;
ad7dc69a 3557
8986ecc0 3558 return 0;
17ac10ad
AK
3559}
3560
578e1c4d 3561void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
0ba73cda
MT
3562{
3563 int i;
3564 struct kvm_mmu_page *sp;
3565
44dd3ffa 3566 if (vcpu->arch.mmu->direct_map)
81407ca5
JR
3567 return;
3568
44dd3ffa 3569 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
0ba73cda 3570 return;
6903074c 3571
56f17dd3 3572 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
578e1c4d 3573
44dd3ffa
VK
3574 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3575 hpa_t root = vcpu->arch.mmu->root_hpa;
e47c4aee 3576 sp = to_shadow_page(root);
578e1c4d
JS
3577
3578 /*
3579 * Even if another CPU was marking the SP as unsync-ed
3580 * simultaneously, any guest page table changes are not
3581 * guaranteed to be visible anyway until this VCPU issues a TLB
3582 * flush strictly after those changes are made. We only need to
3583 * ensure that the other CPU sets these flags before any actual
3584 * changes to the page tables are made. The comments in
0337f585
SC
3585 * mmu_try_to_unsync_pages() describe what could go wrong if
3586 * this requirement isn't satisfied.
578e1c4d
JS
3587 */
3588 if (!smp_load_acquire(&sp->unsync) &&
3589 !smp_load_acquire(&sp->unsync_children))
3590 return;
3591
531810ca 3592 write_lock(&vcpu->kvm->mmu_lock);
578e1c4d
JS
3593 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3594
0ba73cda 3595 mmu_sync_children(vcpu, sp);
578e1c4d 3596
0375f7fa 3597 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
531810ca 3598 write_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT
3599 return;
3600 }
578e1c4d 3601
531810ca 3602 write_lock(&vcpu->kvm->mmu_lock);
578e1c4d
JS
3603 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3604
0ba73cda 3605 for (i = 0; i < 4; ++i) {
44dd3ffa 3606 hpa_t root = vcpu->arch.mmu->pae_root[i];
0ba73cda 3607
c834e5e4 3608 if (IS_VALID_PAE_ROOT(root)) {
0ba73cda 3609 root &= PT64_BASE_ADDR_MASK;
e47c4aee 3610 sp = to_shadow_page(root);
0ba73cda
MT
3611 mmu_sync_children(vcpu, sp);
3612 }
3613 }
0ba73cda 3614
578e1c4d 3615 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
531810ca 3616 write_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT
3617}
3618
736c291c 3619static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
ab9ae313 3620 u32 access, struct x86_exception *exception)
6aa8b732 3621{
ab9ae313
AK
3622 if (exception)
3623 exception->error_code = 0;
6aa8b732
AK
3624 return vaddr;
3625}
3626
736c291c 3627static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
ab9ae313
AK
3628 u32 access,
3629 struct x86_exception *exception)
6539e738 3630{
ab9ae313
AK
3631 if (exception)
3632 exception->error_code = 0;
54987b7a 3633 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
6539e738
JR
3634}
3635
ded58749 3636static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
ce88decf 3637{
9034e6e8
PB
3638 /*
3639 * A nested guest cannot use the MMIO cache if it is using nested
3640 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3641 */
3642 if (mmu_is_nested(vcpu))
3643 return false;
3644
ce88decf
XG
3645 if (direct)
3646 return vcpu_match_mmio_gpa(vcpu, addr);
3647
3648 return vcpu_match_mmio_gva(vcpu, addr);
3649}
3650
95fb5b02
BG
3651/*
3652 * Return the level of the lowest level SPTE added to sptes.
3653 * That SPTE may be non-present.
c5c8c7c5
DM
3654 *
3655 * Must be called between walk_shadow_page_lockless_{begin,end}.
95fb5b02 3656 */
39b4d43e 3657static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
ce88decf
XG
3658{
3659 struct kvm_shadow_walk_iterator iterator;
2aa07893 3660 int leaf = -1;
95fb5b02 3661 u64 spte;
ce88decf 3662
39b4d43e
SC
3663 for (shadow_walk_init(&iterator, vcpu, addr),
3664 *root_level = iterator.level;
47ab8751
XG
3665 shadow_walk_okay(&iterator);
3666 __shadow_walk_next(&iterator, spte)) {
95fb5b02 3667 leaf = iterator.level;
47ab8751
XG
3668 spte = mmu_spte_get_lockless(iterator.sptep);
3669
dde81f94 3670 sptes[leaf] = spte;
47ab8751 3671
ce88decf
XG
3672 if (!is_shadow_present_pte(spte))
3673 break;
95fb5b02
BG
3674 }
3675
95fb5b02
BG
3676 return leaf;
3677}
3678
9aa41879 3679/* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
95fb5b02
BG
3680static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3681{
dde81f94 3682 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
95fb5b02 3683 struct rsvd_bits_validate *rsvd_check;
39b4d43e 3684 int root, leaf, level;
95fb5b02
BG
3685 bool reserved = false;
3686
c5c8c7c5
DM
3687 walk_shadow_page_lockless_begin(vcpu);
3688
63c0cac9 3689 if (is_tdp_mmu(vcpu->arch.mmu))
39b4d43e 3690 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
95fb5b02 3691 else
39b4d43e 3692 leaf = get_walk(vcpu, addr, sptes, &root);
95fb5b02 3693
c5c8c7c5
DM
3694 walk_shadow_page_lockless_end(vcpu);
3695
2aa07893
SC
3696 if (unlikely(leaf < 0)) {
3697 *sptep = 0ull;
3698 return reserved;
3699 }
3700
9aa41879
SC
3701 *sptep = sptes[leaf];
3702
3703 /*
3704 * Skip reserved bits checks on the terminal leaf if it's not a valid
3705 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3706 * design, always have reserved bits set. The purpose of the checks is
3707 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3708 */
3709 if (!is_shadow_present_pte(sptes[leaf]))
3710 leaf++;
95fb5b02
BG
3711
3712 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3713
9aa41879 3714 for (level = root; level >= leaf; level--)
961f8445 3715 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
47ab8751 3716
47ab8751 3717 if (reserved) {
bb4cdf3a 3718 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
47ab8751 3719 __func__, addr);
95fb5b02 3720 for (level = root; level >= leaf; level--)
bb4cdf3a
SC
3721 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3722 sptes[level], level,
961f8445 3723 get_rsvd_bits(rsvd_check, sptes[level], level));
47ab8751 3724 }
ddce6208 3725
47ab8751 3726 return reserved;
ce88decf
XG
3727}
3728
e08d26f0 3729static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
ce88decf
XG
3730{
3731 u64 spte;
47ab8751 3732 bool reserved;
ce88decf 3733
ded58749 3734 if (mmio_info_in_cache(vcpu, addr, direct))
9b8ebbdb 3735 return RET_PF_EMULATE;
ce88decf 3736
95fb5b02 3737 reserved = get_mmio_spte(vcpu, addr, &spte);
450869d6 3738 if (WARN_ON(reserved))
9b8ebbdb 3739 return -EINVAL;
ce88decf
XG
3740
3741 if (is_mmio_spte(spte)) {
3742 gfn_t gfn = get_mmio_spte_gfn(spte);
0a2b64c5 3743 unsigned int access = get_mmio_spte_access(spte);
ce88decf 3744
54bf36aa 3745 if (!check_mmio_spte(vcpu, spte))
9b8ebbdb 3746 return RET_PF_INVALID;
f8f55942 3747
ce88decf
XG
3748 if (direct)
3749 addr = 0;
4f022648
XG
3750
3751 trace_handle_mmio_page_fault(addr, gfn, access);
ce88decf 3752 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
9b8ebbdb 3753 return RET_PF_EMULATE;
ce88decf
XG
3754 }
3755
ce88decf
XG
3756 /*
3757 * If the page table is zapped by other cpus, let CPU fault again on
3758 * the address.
3759 */
9b8ebbdb 3760 return RET_PF_RETRY;
ce88decf 3761}
ce88decf 3762
3d0c27ad
XG
3763static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3764 u32 error_code, gfn_t gfn)
3765{
3766 if (unlikely(error_code & PFERR_RSVD_MASK))
3767 return false;
3768
3769 if (!(error_code & PFERR_PRESENT_MASK) ||
3770 !(error_code & PFERR_WRITE_MASK))
3771 return false;
3772
3773 /*
3774 * guest is writing the page which is write tracked which can
3775 * not be fixed by page fault handler.
3776 */
3777 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3778 return true;
3779
3780 return false;
3781}
3782
e5691a81
XG
3783static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3784{
3785 struct kvm_shadow_walk_iterator iterator;
3786 u64 spte;
3787
e5691a81
XG
3788 walk_shadow_page_lockless_begin(vcpu);
3789 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3790 clear_sp_write_flooding_count(iterator.sptep);
3791 if (!is_shadow_present_pte(spte))
3792 break;
3793 }
3794 walk_shadow_page_lockless_end(vcpu);
3795}
3796
e8c22266
VK
3797static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3798 gfn_t gfn)
af585b92
GN
3799{
3800 struct kvm_arch_async_pf arch;
fb67e14f 3801
7c90705b 3802 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
af585b92 3803 arch.gfn = gfn;
44dd3ffa 3804 arch.direct_map = vcpu->arch.mmu->direct_map;
d8dd54e0 3805 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
af585b92 3806
9f1a8526
SC
3807 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3808 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
af585b92
GN
3809}
3810
78b2c54a 3811static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4a42d848
DS
3812 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3813 bool write, bool *writable)
af585b92 3814{
c36b7150 3815 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
af585b92
GN
3816 bool async;
3817
e0c37868
SC
3818 /*
3819 * Retry the page fault if the gfn hit a memslot that is being deleted
3820 * or moved. This ensures any existing SPTEs for the old memslot will
3821 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3822 */
3823 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3824 return true;
3825
c36b7150
PB
3826 /* Don't expose private memslots to L2. */
3827 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3a2936de 3828 *pfn = KVM_PFN_NOSLOT;
c583eed6 3829 *writable = false;
3a2936de
JM
3830 return false;
3831 }
3832
3520469d 3833 async = false;
4a42d848
DS
3834 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3835 write, writable, hva);
af585b92
GN
3836 if (!async)
3837 return false; /* *pfn has correct page already */
3838
9bc1f09f 3839 if (!prefault && kvm_can_do_async_pf(vcpu)) {
9f1a8526 3840 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
af585b92 3841 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
9f1a8526 3842 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
af585b92
GN
3843 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3844 return true;
9f1a8526 3845 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
af585b92
GN
3846 return true;
3847 }
3848
4a42d848
DS
3849 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3850 write, writable, hva);
af585b92
GN
3851 return false;
3852}
3853
0f90e1c1
SC
3854static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3855 bool prefault, int max_level, bool is_tdp)
6aa8b732 3856{
63c0cac9 3857 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
367fd790 3858 bool write = error_code & PFERR_WRITE_MASK;
0f90e1c1 3859 bool map_writable;
6aa8b732 3860
0f90e1c1
SC
3861 gfn_t gfn = gpa >> PAGE_SHIFT;
3862 unsigned long mmu_seq;
3863 kvm_pfn_t pfn;
4a42d848 3864 hva_t hva;
83f06fa7 3865 int r;
ce88decf 3866
3d0c27ad 3867 if (page_fault_handle_page_track(vcpu, error_code, gfn))
9b8ebbdb 3868 return RET_PF_EMULATE;
ce88decf 3869
6e8eb206
DM
3870 r = fast_page_fault(vcpu, gpa, error_code);
3871 if (r != RET_PF_INVALID)
3872 return r;
83291445 3873
378f5cd6 3874 r = mmu_topup_memory_caches(vcpu, false);
e2dec939
AK
3875 if (r)
3876 return r;
714b93da 3877
367fd790
SC
3878 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3879 smp_rmb();
3880
4a42d848
DS
3881 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3882 write, &map_writable))
367fd790
SC
3883 return RET_PF_RETRY;
3884
0f90e1c1 3885 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
367fd790 3886 return r;
6aa8b732 3887
367fd790 3888 r = RET_PF_RETRY;
a2855afc 3889
0b873fd7 3890 if (is_tdp_mmu_fault)
a2855afc
BG
3891 read_lock(&vcpu->kvm->mmu_lock);
3892 else
3893 write_lock(&vcpu->kvm->mmu_lock);
3894
4a42d848 3895 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
367fd790 3896 goto out_unlock;
7bd7ded6
SC
3897 r = make_mmu_pages_available(vcpu);
3898 if (r)
367fd790 3899 goto out_unlock;
bb18842e 3900
0b873fd7 3901 if (is_tdp_mmu_fault)
bb18842e
BG
3902 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3903 pfn, prefault);
3904 else
3905 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3906 prefault, is_tdp);
0f90e1c1 3907
367fd790 3908out_unlock:
0b873fd7 3909 if (is_tdp_mmu_fault)
a2855afc
BG
3910 read_unlock(&vcpu->kvm->mmu_lock);
3911 else
3912 write_unlock(&vcpu->kvm->mmu_lock);
367fd790
SC
3913 kvm_release_pfn_clean(pfn);
3914 return r;
6aa8b732
AK
3915}
3916
0f90e1c1
SC
3917static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3918 u32 error_code, bool prefault)
3919{
3920 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3921
3922 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3923 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3bae0459 3924 PG_LEVEL_2M, false);
0f90e1c1
SC
3925}
3926
1261bfa3 3927int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
d0006530 3928 u64 fault_address, char *insn, int insn_len)
1261bfa3
WL
3929{
3930 int r = 1;
9ce372b3 3931 u32 flags = vcpu->arch.apf.host_apf_flags;
1261bfa3 3932
736c291c
SC
3933#ifndef CONFIG_X86_64
3934 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3935 if (WARN_ON_ONCE(fault_address >> 32))
3936 return -EFAULT;
3937#endif
3938
c595ceee 3939 vcpu->arch.l1tf_flush_l1d = true;
9ce372b3 3940 if (!flags) {
1261bfa3
WL
3941 trace_kvm_page_fault(fault_address, error_code);
3942
d0006530 3943 if (kvm_event_needs_reinjection(vcpu))
1261bfa3
WL
3944 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3945 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3946 insn_len);
9ce372b3 3947 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
68fd66f1 3948 vcpu->arch.apf.host_apf_flags = 0;
1261bfa3 3949 local_irq_disable();
6bca69ad 3950 kvm_async_pf_task_wait_schedule(fault_address);
1261bfa3 3951 local_irq_enable();
9ce372b3
VK
3952 } else {
3953 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
1261bfa3 3954 }
9ce372b3 3955
1261bfa3
WL
3956 return r;
3957}
3958EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3959
7a02674d
SC
3960int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3961 bool prefault)
fb72d167 3962{
cb9b88c6 3963 int max_level;
fb72d167 3964
e662ec3e 3965 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3bae0459 3966 max_level > PG_LEVEL_4K;
cb9b88c6
SC
3967 max_level--) {
3968 int page_num = KVM_PAGES_PER_HPAGE(max_level);
0f90e1c1 3969 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
ce88decf 3970
cb9b88c6
SC
3971 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3972 break;
fd136902 3973 }
852e3c19 3974
0f90e1c1
SC
3975 return direct_page_fault(vcpu, gpa, error_code, prefault,
3976 max_level, true);
fb72d167
JR
3977}
3978
84a16226 3979static void nonpaging_init_context(struct kvm_mmu *context)
6aa8b732 3980{
6aa8b732 3981 context->page_fault = nonpaging_page_fault;
6aa8b732 3982 context->gva_to_gpa = nonpaging_gva_to_gpa;
e8bc217a 3983 context->sync_page = nonpaging_sync_page;
5efac074 3984 context->invlpg = NULL;
c5a78f2b 3985 context->direct_map = true;
6aa8b732
AK
3986}
3987
be01e8e2 3988static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
0be44352
SC
3989 union kvm_mmu_page_role role)
3990{
be01e8e2 3991 return (role.direct || pgd == root->pgd) &&
e47c4aee
SC
3992 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3993 role.word == to_shadow_page(root->hpa)->role.word;
0be44352
SC
3994}
3995
b94742c9 3996/*
be01e8e2 3997 * Find out if a previously cached root matching the new pgd/role is available.
b94742c9
JS
3998 * The current root is also inserted into the cache.
3999 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4000 * returned.
4001 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4002 * false is returned. This root should now be freed by the caller.
4003 */
be01e8e2 4004static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
b94742c9
JS
4005 union kvm_mmu_page_role new_role)
4006{
4007 uint i;
4008 struct kvm_mmu_root_info root;
44dd3ffa 4009 struct kvm_mmu *mmu = vcpu->arch.mmu;
b94742c9 4010
be01e8e2 4011 root.pgd = mmu->root_pgd;
b94742c9
JS
4012 root.hpa = mmu->root_hpa;
4013
be01e8e2 4014 if (is_root_usable(&root, new_pgd, new_role))
0be44352
SC
4015 return true;
4016
b94742c9
JS
4017 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4018 swap(root, mmu->prev_roots[i]);
4019
be01e8e2 4020 if (is_root_usable(&root, new_pgd, new_role))
b94742c9
JS
4021 break;
4022 }
4023
4024 mmu->root_hpa = root.hpa;
be01e8e2 4025 mmu->root_pgd = root.pgd;
b94742c9
JS
4026
4027 return i < KVM_MMU_NUM_PREV_ROOTS;
4028}
4029
be01e8e2 4030static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
b869855b 4031 union kvm_mmu_page_role new_role)
6aa8b732 4032{
44dd3ffa 4033 struct kvm_mmu *mmu = vcpu->arch.mmu;
7c390d35
JS
4034
4035 /*
4036 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4037 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4038 * later if necessary.
4039 */
4040 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
b869855b 4041 mmu->root_level >= PT64_ROOT_4LEVEL)
fe9304d3 4042 return cached_root_available(vcpu, new_pgd, new_role);
7c390d35
JS
4043
4044 return false;
6aa8b732
AK
4045}
4046
be01e8e2 4047static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
b5129100 4048 union kvm_mmu_page_role new_role)
6aa8b732 4049{
be01e8e2 4050 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
b869855b
SC
4051 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4052 return;
4053 }
4054
4055 /*
4056 * It's possible that the cached previous root page is obsolete because
4057 * of a change in the MMU generation number. However, changing the
4058 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4059 * free the root set here and allocate a new one.
4060 */
4061 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4062
b5129100 4063 if (force_flush_and_sync_on_reuse) {
b869855b
SC
4064 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4065 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
b5129100 4066 }
b869855b
SC
4067
4068 /*
4069 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4070 * switching to a new CR3, that GVA->GPA mapping may no longer be
4071 * valid. So clear any cached MMIO info even when we don't need to sync
4072 * the shadow page tables.
4073 */
4074 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4075
daa5b6c1
BG
4076 /*
4077 * If this is a direct root page, it doesn't have a write flooding
4078 * count. Otherwise, clear the write flooding count.
4079 */
4080 if (!new_role.direct)
4081 __clear_sp_write_flooding_count(
4082 to_shadow_page(vcpu->arch.mmu->root_hpa));
6aa8b732
AK
4083}
4084
b5129100 4085void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
0aab33e4 4086{
b5129100 4087 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
0aab33e4 4088}
be01e8e2 4089EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
0aab33e4 4090
5777ed34
JR
4091static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4092{
9f8fe504 4093 return kvm_read_cr3(vcpu);
5777ed34
JR
4094}
4095
54bf36aa 4096static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
0a2b64c5 4097 unsigned int access, int *nr_present)
ce88decf
XG
4098{
4099 if (unlikely(is_mmio_spte(*sptep))) {
4100 if (gfn != get_mmio_spte_gfn(*sptep)) {
4101 mmu_spte_clear_no_track(sptep);
4102 return true;
4103 }
4104
4105 (*nr_present)++;
54bf36aa 4106 mark_mmio_spte(vcpu, sptep, gfn, access);
ce88decf
XG
4107 return true;
4108 }
4109
4110 return false;
4111}
4112
37406aaa
NHE
4113#define PTTYPE_EPT 18 /* arbitrary */
4114#define PTTYPE PTTYPE_EPT
4115#include "paging_tmpl.h"
4116#undef PTTYPE
4117
6aa8b732
AK
4118#define PTTYPE 64
4119#include "paging_tmpl.h"
4120#undef PTTYPE
4121
4122#define PTTYPE 32
4123#include "paging_tmpl.h"
4124#undef PTTYPE
4125
6dc98b86 4126static void
b705a277 4127__reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
5b7f575c 4128 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
6fec2144 4129 bool pse, bool amd)
82725b20 4130{
5f7dde7b 4131 u64 gbpages_bit_rsvd = 0;
a0c0feb5 4132 u64 nonleaf_bit8_rsvd = 0;
5b7f575c 4133 u64 high_bits_rsvd;
82725b20 4134
a0a64f50 4135 rsvd_check->bad_mt_xwr = 0;
25d92081 4136
6dc98b86 4137 if (!gbpages)
5f7dde7b 4138 gbpages_bit_rsvd = rsvd_bits(7, 7);
a0c0feb5 4139
5b7f575c
SC
4140 if (level == PT32E_ROOT_LEVEL)
4141 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4142 else
4143 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4144
4145 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4146 if (!nx)
4147 high_bits_rsvd |= rsvd_bits(63, 63);
4148
a0c0feb5
PB
4149 /*
4150 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4151 * leaf entries) on AMD CPUs only.
4152 */
6fec2144 4153 if (amd)
a0c0feb5
PB
4154 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4155
6dc98b86 4156 switch (level) {
82725b20
DE
4157 case PT32_ROOT_LEVEL:
4158 /* no rsvd bits for 2 level 4K page table entries */
a0a64f50
XG
4159 rsvd_check->rsvd_bits_mask[0][1] = 0;
4160 rsvd_check->rsvd_bits_mask[0][0] = 0;
4161 rsvd_check->rsvd_bits_mask[1][0] =
4162 rsvd_check->rsvd_bits_mask[0][0];
f815bce8 4163
6dc98b86 4164 if (!pse) {
a0a64f50 4165 rsvd_check->rsvd_bits_mask[1][1] = 0;
f815bce8
XG
4166 break;
4167 }
4168
82725b20
DE
4169 if (is_cpuid_PSE36())
4170 /* 36bits PSE 4MB page */
a0a64f50 4171 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
82725b20
DE
4172 else
4173 /* 32 bits PSE 4MB page */
a0a64f50 4174 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE
4175 break;
4176 case PT32E_ROOT_LEVEL:
5b7f575c
SC
4177 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4178 high_bits_rsvd |
4179 rsvd_bits(5, 8) |
4180 rsvd_bits(1, 2); /* PDPTE */
4181 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4182 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4183 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4184 rsvd_bits(13, 20); /* large page */
a0a64f50
XG
4185 rsvd_check->rsvd_bits_mask[1][0] =
4186 rsvd_check->rsvd_bits_mask[0][0];
82725b20 4187 break;
855feb67 4188 case PT64_ROOT_5LEVEL:
5b7f575c
SC
4189 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4190 nonleaf_bit8_rsvd |
4191 rsvd_bits(7, 7);
855feb67
YZ
4192 rsvd_check->rsvd_bits_mask[1][4] =
4193 rsvd_check->rsvd_bits_mask[0][4];
df561f66 4194 fallthrough;
2a7266a8 4195 case PT64_ROOT_4LEVEL:
5b7f575c
SC
4196 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4197 nonleaf_bit8_rsvd |
4198 rsvd_bits(7, 7);
4199 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4200 gbpages_bit_rsvd;
4201 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4202 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
a0a64f50
XG
4203 rsvd_check->rsvd_bits_mask[1][3] =
4204 rsvd_check->rsvd_bits_mask[0][3];
5b7f575c
SC
4205 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4206 gbpages_bit_rsvd |
4207 rsvd_bits(13, 29);
4208 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4209 rsvd_bits(13, 20); /* large page */
a0a64f50
XG
4210 rsvd_check->rsvd_bits_mask[1][0] =
4211 rsvd_check->rsvd_bits_mask[0][0];
82725b20
DE
4212 break;
4213 }
4214}
4215
27de9250
SC
4216static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu)
4217{
4218 /*
4219 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4220 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4221 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4222 * walk for performance and complexity reasons. Not to mention KVM
4223 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4224 * KVM once a TDP translation is installed. Mimic hardware behavior so
4225 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4226 */
4227 return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
4228 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
4229}
4230
6dc98b86
XG
4231static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4232 struct kvm_mmu *context)
4233{
b705a277 4234 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
5b7f575c 4235 vcpu->arch.reserved_gpa_bits,
90599c28 4236 context->root_level, is_efer_nx(context),
27de9250 4237 guest_can_use_gbpages(vcpu),
4e9c0d80 4238 is_cr4_pse(context),
23493d0a 4239 guest_cpuid_is_amd_or_hygon(vcpu));
6dc98b86
XG
4240}
4241
81b8eebb
XG
4242static void
4243__reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
5b7f575c 4244 u64 pa_bits_rsvd, bool execonly)
25d92081 4245{
5b7f575c 4246 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
951f9fd7 4247 u64 bad_mt_xwr;
25d92081 4248
5b7f575c
SC
4249 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4250 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4251 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4252 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4253 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
25d92081
YZ
4254
4255 /* large page */
855feb67 4256 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
a0a64f50 4257 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
5b7f575c
SC
4258 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4259 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
a0a64f50 4260 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
25d92081 4261
951f9fd7
PB
4262 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4263 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4264 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4265 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4266 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4267 if (!execonly) {
4268 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4269 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
25d92081 4270 }
951f9fd7 4271 rsvd_check->bad_mt_xwr = bad_mt_xwr;
25d92081
YZ
4272}
4273
81b8eebb
XG
4274static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4275 struct kvm_mmu *context, bool execonly)
4276{
4277 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
5b7f575c 4278 vcpu->arch.reserved_gpa_bits, execonly);
81b8eebb
XG
4279}
4280
6f8e65a6
SC
4281static inline u64 reserved_hpa_bits(void)
4282{
4283 return rsvd_bits(shadow_phys_bits, 63);
4284}
4285
c258b62b
XG
4286/*
4287 * the page table on host is the shadow page table for the page
4288 * table in guest or amd nested guest, its mmu features completely
4289 * follow the features in guest.
4290 */
16be1d12
SC
4291static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4292 struct kvm_mmu *context)
c258b62b 4293{
112022bd
SC
4294 /*
4295 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4296 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4297 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4298 * The iTLB multi-hit workaround can be toggled at any time, so assume
4299 * NX can be used by any non-nested shadow MMU to avoid having to reset
4300 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4301 */
90599c28 4302 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
8c985b2d
SC
4303
4304 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4305 bool is_amd = true;
4306 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4307 bool is_pse = false;
ea2800dd
BS
4308 struct rsvd_bits_validate *shadow_zero_check;
4309 int i;
5f0b8199 4310
8c985b2d
SC
4311 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4312
ea2800dd 4313 shadow_zero_check = &context->shadow_zero_check;
b705a277 4314 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
5f0b8199 4315 context->shadow_root_level, uses_nx,
27de9250 4316 guest_can_use_gbpages(vcpu), is_pse, is_amd);
ea2800dd
BS
4317
4318 if (!shadow_me_mask)
4319 return;
4320
4321 for (i = context->shadow_root_level; --i >= 0;) {
4322 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4323 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4324 }
4325
c258b62b 4326}
c258b62b 4327
6fec2144
PB
4328static inline bool boot_cpu_is_amd(void)
4329{
4330 WARN_ON_ONCE(!tdp_enabled);
4331 return shadow_x_mask == 0;
4332}
4333
c258b62b
XG
4334/*
4335 * the direct page table on host, use as much mmu features as
4336 * possible, however, kvm currently does not do execution-protection.
4337 */
4338static void
4339reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4340 struct kvm_mmu *context)
4341{
ea2800dd
BS
4342 struct rsvd_bits_validate *shadow_zero_check;
4343 int i;
4344
4345 shadow_zero_check = &context->shadow_zero_check;
4346
6fec2144 4347 if (boot_cpu_is_amd())
b705a277 4348 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
c258b62b 4349 context->shadow_root_level, false,
b8291adc 4350 boot_cpu_has(X86_FEATURE_GBPAGES),
8c985b2d 4351 false, true);
c258b62b 4352 else
ea2800dd 4353 __reset_rsvds_bits_mask_ept(shadow_zero_check,
6f8e65a6 4354 reserved_hpa_bits(), false);
c258b62b 4355
ea2800dd
BS
4356 if (!shadow_me_mask)
4357 return;
4358
4359 for (i = context->shadow_root_level; --i >= 0;) {
4360 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4361 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4362 }
c258b62b
XG
4363}
4364
4365/*
4366 * as the comments in reset_shadow_zero_bits_mask() except it
4367 * is the shadow page table for intel nested guest.
4368 */
4369static void
4370reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4371 struct kvm_mmu *context, bool execonly)
4372{
4373 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
6f8e65a6 4374 reserved_hpa_bits(), execonly);
c258b62b
XG
4375}
4376
09f037aa
PB
4377#define BYTE_MASK(access) \
4378 ((1 & (access) ? 2 : 0) | \
4379 (2 & (access) ? 4 : 0) | \
4380 (3 & (access) ? 8 : 0) | \
4381 (4 & (access) ? 16 : 0) | \
4382 (5 & (access) ? 32 : 0) | \
4383 (6 & (access) ? 64 : 0) | \
4384 (7 & (access) ? 128 : 0))
4385
4386
c596f147 4387static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
97d64b78 4388{
09f037aa
PB
4389 unsigned byte;
4390
4391 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4392 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4393 const u8 u = BYTE_MASK(ACC_USER_MASK);
4394
c596f147
SC
4395 bool cr4_smep = is_cr4_smep(mmu);
4396 bool cr4_smap = is_cr4_smap(mmu);
4397 bool cr0_wp = is_cr0_wp(mmu);
90599c28 4398 bool efer_nx = is_efer_nx(mmu);
97d64b78 4399
97d64b78 4400 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
09f037aa
PB
4401 unsigned pfec = byte << 1;
4402
97ec8c06 4403 /*
09f037aa
PB
4404 * Each "*f" variable has a 1 bit for each UWX value
4405 * that causes a fault with the given PFEC.
97ec8c06 4406 */
97d64b78 4407
09f037aa 4408 /* Faults from writes to non-writable pages */
a6a6d3b1 4409 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
09f037aa 4410 /* Faults from user mode accesses to supervisor pages */
a6a6d3b1 4411 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
09f037aa 4412 /* Faults from fetches of non-executable pages*/
a6a6d3b1 4413 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
09f037aa
PB
4414 /* Faults from kernel mode fetches of user pages */
4415 u8 smepf = 0;
4416 /* Faults from kernel mode accesses of user pages */
4417 u8 smapf = 0;
4418
4419 if (!ept) {
4420 /* Faults from kernel mode accesses to user pages */
4421 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4422
4423 /* Not really needed: !nx will cause pte.nx to fault */
90599c28 4424 if (!efer_nx)
09f037aa
PB
4425 ff = 0;
4426
4427 /* Allow supervisor writes if !cr0.wp */
4428 if (!cr0_wp)
4429 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4430
4431 /* Disallow supervisor fetches of user code if cr4.smep */
4432 if (cr4_smep)
4433 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4434
4435 /*
4436 * SMAP:kernel-mode data accesses from user-mode
4437 * mappings should fault. A fault is considered
4438 * as a SMAP violation if all of the following
39337ad1 4439 * conditions are true:
09f037aa
PB
4440 * - X86_CR4_SMAP is set in CR4
4441 * - A user page is accessed
4442 * - The access is not a fetch
4443 * - Page fault in kernel mode
4444 * - if CPL = 3 or X86_EFLAGS_AC is clear
4445 *
4446 * Here, we cover the first three conditions.
4447 * The fourth is computed dynamically in permission_fault();
4448 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4449 * *not* subject to SMAP restrictions.
4450 */
4451 if (cr4_smap)
4452 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
97d64b78 4453 }
09f037aa
PB
4454
4455 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
97d64b78
AK
4456 }
4457}
4458
2d344105
HH
4459/*
4460* PKU is an additional mechanism by which the paging controls access to
4461* user-mode addresses based on the value in the PKRU register. Protection
4462* key violations are reported through a bit in the page fault error code.
4463* Unlike other bits of the error code, the PK bit is not known at the
4464* call site of e.g. gva_to_gpa; it must be computed directly in
4465* permission_fault based on two bits of PKRU, on some machine state (CR4,
4466* CR0, EFER, CPL), and on other bits of the error code and the page tables.
4467*
4468* In particular the following conditions come from the error code, the
4469* page tables and the machine state:
4470* - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4471* - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4472* - PK is always zero if U=0 in the page tables
4473* - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4474*
4475* The PKRU bitmask caches the result of these four conditions. The error
4476* code (minus the P bit) and the page table's U bit form an index into the
4477* PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4478* with the two bits of the PKRU register corresponding to the protection key.
4479* For the first three conditions above the bits will be 00, thus masking
4480* away both AD and WD. For all reads or if the last condition holds, WD
4481* only will be masked away.
4482*/
2e4c0661 4483static void update_pkru_bitmask(struct kvm_mmu *mmu)
2d344105
HH
4484{
4485 unsigned bit;
4486 bool wp;
4487
2e4c0661 4488 if (!is_cr4_pke(mmu)) {
2d344105
HH
4489 mmu->pkru_mask = 0;
4490 return;
4491 }
4492
2e4c0661 4493 wp = is_cr0_wp(mmu);
2d344105
HH
4494
4495 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4496 unsigned pfec, pkey_bits;
4497 bool check_pkey, check_write, ff, uf, wf, pte_user;
4498
4499 pfec = bit << 1;
4500 ff = pfec & PFERR_FETCH_MASK;
4501 uf = pfec & PFERR_USER_MASK;
4502 wf = pfec & PFERR_WRITE_MASK;
4503
4504 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4505 pte_user = pfec & PFERR_RSVD_MASK;
4506
4507 /*
4508 * Only need to check the access which is not an
4509 * instruction fetch and is to a user page.
4510 */
4511 check_pkey = (!ff && pte_user);
4512 /*
4513 * write access is controlled by PKRU if it is a
4514 * user access or CR0.WP = 1.
4515 */
4516 check_write = check_pkey && wf && (uf || wp);
4517
4518 /* PKRU.AD stops both read and write access. */
4519 pkey_bits = !!check_pkey;
4520 /* PKRU.WD stops write access. */
4521 pkey_bits |= (!!check_write) << 1;
4522
4523 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4524 }
4525}
4526
533f9a4b
SC
4527static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4528 struct kvm_mmu *mmu)
6fd01b71 4529{
533f9a4b
SC
4530 if (!is_cr0_pg(mmu))
4531 return;
6bb69c9b 4532
533f9a4b
SC
4533 reset_rsvds_bits_mask(vcpu, mmu);
4534 update_permission_bitmask(mmu, false);
4535 update_pkru_bitmask(mmu);
6fd01b71
AK
4536}
4537
fe660f72 4538static void paging64_init_context(struct kvm_mmu *context)
6aa8b732 4539{
6aa8b732 4540 context->page_fault = paging64_page_fault;
6aa8b732 4541 context->gva_to_gpa = paging64_gva_to_gpa;
e8bc217a 4542 context->sync_page = paging64_sync_page;
a7052897 4543 context->invlpg = paging64_invlpg;
c5a78f2b 4544 context->direct_map = false;
6aa8b732
AK
4545}
4546
84a16226 4547static void paging32_init_context(struct kvm_mmu *context)
6aa8b732 4548{
6aa8b732 4549 context->page_fault = paging32_page_fault;
6aa8b732 4550 context->gva_to_gpa = paging32_gva_to_gpa;
e8bc217a 4551 context->sync_page = paging32_sync_page;
a7052897 4552 context->invlpg = paging32_invlpg;
c5a78f2b 4553 context->direct_map = false;
6aa8b732
AK
4554}
4555
8626c120
SC
4556static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4557 struct kvm_mmu_role_regs *regs)
a336282d
VK
4558{
4559 union kvm_mmu_extended_role ext = {0};
4560
ca8d664f
SC
4561 if (____is_cr0_pg(regs)) {
4562 ext.cr0_pg = 1;
4563 ext.cr4_pae = ____is_cr4_pae(regs);
4564 ext.cr4_smep = ____is_cr4_smep(regs);
4565 ext.cr4_smap = ____is_cr4_smap(regs);
4566 ext.cr4_pse = ____is_cr4_pse(regs);
84c679f5
SC
4567
4568 /* PKEY and LA57 are active iff long mode is active. */
4569 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4570 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
ca8d664f 4571 }
a336282d
VK
4572
4573 ext.valid = 1;
4574
4575 return ext;
4576}
4577
7dcd5755 4578static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
8626c120 4579 struct kvm_mmu_role_regs *regs,
7dcd5755
VK
4580 bool base_only)
4581{
4582 union kvm_mmu_role role = {0};
4583
4584 role.base.access = ACC_ALL;
ca8d664f
SC
4585 if (____is_cr0_pg(regs)) {
4586 role.base.efer_nx = ____is_efer_nx(regs);
4587 role.base.cr0_wp = ____is_cr0_wp(regs);
4588 }
7dcd5755
VK
4589 role.base.smm = is_smm(vcpu);
4590 role.base.guest_mode = is_guest_mode(vcpu);
4591
4592 if (base_only)
4593 return role;
4594
8626c120 4595 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
7dcd5755
VK
4596
4597 return role;
4598}
4599
d468d94b
SC
4600static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4601{
4602 /* Use 5-level TDP if and only if it's useful/necessary. */
83013059 4603 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
d468d94b
SC
4604 return 4;
4605
83013059 4606 return max_tdp_level;
d468d94b
SC
4607}
4608
7dcd5755 4609static union kvm_mmu_role
8626c120
SC
4610kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4611 struct kvm_mmu_role_regs *regs, bool base_only)
9fa72119 4612{
8626c120 4613 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
9fa72119 4614
7dcd5755 4615 role.base.ad_disabled = (shadow_accessed_mask == 0);
d468d94b 4616 role.base.level = kvm_mmu_get_tdp_level(vcpu);
7dcd5755 4617 role.base.direct = true;
47c42e6b 4618 role.base.gpte_is_8_bytes = true;
9fa72119
JS
4619
4620 return role;
4621}
4622
8a3c1a33 4623static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
fb72d167 4624{
8c008659 4625 struct kvm_mmu *context = &vcpu->arch.root_mmu;
8626c120 4626 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
7dcd5755 4627 union kvm_mmu_role new_role =
8626c120 4628 kvm_calc_tdp_mmu_root_page_role(vcpu, &regs, false);
fb72d167 4629
7dcd5755
VK
4630 if (new_role.as_u64 == context->mmu_role.as_u64)
4631 return;
4632
4633 context->mmu_role.as_u64 = new_role.as_u64;
7a02674d 4634 context->page_fault = kvm_tdp_page_fault;
e8bc217a 4635 context->sync_page = nonpaging_sync_page;
5efac074 4636 context->invlpg = NULL;
d468d94b 4637 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
c5a78f2b 4638 context->direct_map = true;
d8dd54e0 4639 context->get_guest_pgd = get_cr3;
e4e517b4 4640 context->get_pdptr = kvm_pdptr_read;
cb659db8 4641 context->inject_page_fault = kvm_inject_page_fault;
f4bd6f73 4642 context->root_level = role_regs_to_root_level(&regs);
fb72d167 4643
36f26787 4644 if (!is_cr0_pg(context))
fb72d167 4645 context->gva_to_gpa = nonpaging_gva_to_gpa;
36f26787 4646 else if (is_cr4_pae(context))
4d6931c3 4647 context->gva_to_gpa = paging64_gva_to_gpa;
f4bd6f73 4648 else
4d6931c3 4649 context->gva_to_gpa = paging32_gva_to_gpa;
fb72d167 4650
533f9a4b 4651 reset_guest_paging_metadata(vcpu, context);
c258b62b 4652 reset_tdp_shadow_zero_bits_mask(vcpu, context);
fb72d167
JR
4653}
4654
7dcd5755 4655static union kvm_mmu_role
8626c120
SC
4656kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4657 struct kvm_mmu_role_regs *regs, bool base_only)
7dcd5755 4658{
8626c120 4659 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
7dcd5755 4660
8626c120
SC
4661 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4662 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
ca8d664f 4663 role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs);
9fa72119 4664
59505b55
SC
4665 return role;
4666}
4667
4668static union kvm_mmu_role
8626c120
SC
4669kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4670 struct kvm_mmu_role_regs *regs, bool base_only)
59505b55
SC
4671{
4672 union kvm_mmu_role role =
8626c120 4673 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
59505b55 4674
8626c120 4675 role.base.direct = !____is_cr0_pg(regs);
59505b55 4676
8626c120 4677 if (!____is_efer_lma(regs))
7dcd5755 4678 role.base.level = PT32E_ROOT_LEVEL;
8626c120 4679 else if (____is_cr4_la57(regs))
7dcd5755 4680 role.base.level = PT64_ROOT_5LEVEL;
9fa72119 4681 else
7dcd5755 4682 role.base.level = PT64_ROOT_4LEVEL;
9fa72119
JS
4683
4684 return role;
4685}
4686
8c008659 4687static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
594e91a1 4688 struct kvm_mmu_role_regs *regs,
8c008659 4689 union kvm_mmu_role new_role)
9fa72119 4690{
18db1b17
SC
4691 if (new_role.as_u64 == context->mmu_role.as_u64)
4692 return;
a770f6f2 4693
7dcd5755 4694 context->mmu_role.as_u64 = new_role.as_u64;
18db1b17 4695
36f26787 4696 if (!is_cr0_pg(context))
84a16226 4697 nonpaging_init_context(context);
36f26787 4698 else if (is_cr4_pae(context))
fe660f72 4699 paging64_init_context(context);
6aa8b732 4700 else
84a16226 4701 paging32_init_context(context);
f4bd6f73 4702 context->root_level = role_regs_to_root_level(regs);
a770f6f2 4703
533f9a4b 4704 reset_guest_paging_metadata(vcpu, context);
d555f705
SC
4705 context->shadow_root_level = new_role.base.level;
4706
c258b62b 4707 reset_shadow_zero_bits_mask(vcpu, context);
52fde8df 4708}
0f04a2ac 4709
594e91a1
SC
4710static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4711 struct kvm_mmu_role_regs *regs)
0f04a2ac 4712{
8c008659 4713 struct kvm_mmu *context = &vcpu->arch.root_mmu;
0f04a2ac 4714 union kvm_mmu_role new_role =
8626c120 4715 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
0f04a2ac 4716
18db1b17 4717 shadow_mmu_init_context(vcpu, context, regs, new_role);
0f04a2ac
VK
4718}
4719
59505b55 4720static union kvm_mmu_role
8626c120
SC
4721kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4722 struct kvm_mmu_role_regs *regs)
59505b55
SC
4723{
4724 union kvm_mmu_role role =
8626c120 4725 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
59505b55
SC
4726
4727 role.base.direct = false;
d468d94b 4728 role.base.level = kvm_mmu_get_tdp_level(vcpu);
59505b55
SC
4729
4730 return role;
4731}
4732
dbc4739b
SC
4733void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4734 unsigned long cr4, u64 efer, gpa_t nested_cr3)
0f04a2ac 4735{
8c008659 4736 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
594e91a1
SC
4737 struct kvm_mmu_role_regs regs = {
4738 .cr0 = cr0,
4739 .cr4 = cr4,
4740 .efer = efer,
4741 };
8626c120 4742 union kvm_mmu_role new_role;
0f04a2ac 4743
8626c120 4744 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, &regs);
a506fdd2 4745
b5129100 4746 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
a3322d5c 4747
18db1b17 4748 shadow_mmu_init_context(vcpu, context, &regs, new_role);
0f04a2ac
VK
4749}
4750EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
52fde8df 4751
a336282d
VK
4752static union kvm_mmu_role
4753kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
bb1fcc70 4754 bool execonly, u8 level)
9fa72119 4755{
552c69b1 4756 union kvm_mmu_role role = {0};
14c07ad8 4757
47c42e6b
SC
4758 /* SMM flag is inherited from root_mmu */
4759 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
9fa72119 4760
bb1fcc70 4761 role.base.level = level;
47c42e6b 4762 role.base.gpte_is_8_bytes = true;
a336282d
VK
4763 role.base.direct = false;
4764 role.base.ad_disabled = !accessed_dirty;
4765 role.base.guest_mode = true;
4766 role.base.access = ACC_ALL;
9fa72119 4767
cd6767c3
SC
4768 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4769 role.ext.word = 0;
a336282d 4770 role.ext.execonly = execonly;
cd6767c3 4771 role.ext.valid = 1;
9fa72119
JS
4772
4773 return role;
4774}
4775
ae1e2d10 4776void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
50c28f21 4777 bool accessed_dirty, gpa_t new_eptp)
155a97a3 4778{
8c008659 4779 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
bb1fcc70 4780 u8 level = vmx_eptp_page_walk_level(new_eptp);
a336282d
VK
4781 union kvm_mmu_role new_role =
4782 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
bb1fcc70 4783 execonly, level);
a336282d 4784
b5129100 4785 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
a336282d 4786
a336282d
VK
4787 if (new_role.as_u64 == context->mmu_role.as_u64)
4788 return;
ad896af0 4789
18db1b17
SC
4790 context->mmu_role.as_u64 = new_role.as_u64;
4791
bb1fcc70 4792 context->shadow_root_level = level;
155a97a3 4793
ae1e2d10 4794 context->ept_ad = accessed_dirty;
155a97a3
NHE
4795 context->page_fault = ept_page_fault;
4796 context->gva_to_gpa = ept_gva_to_gpa;
4797 context->sync_page = ept_sync_page;
4798 context->invlpg = ept_invlpg;
bb1fcc70 4799 context->root_level = level;
155a97a3 4800 context->direct_map = false;
3dc773e7 4801
c596f147 4802 update_permission_bitmask(context, true);
2e4c0661 4803 update_pkru_bitmask(context);
155a97a3 4804 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
c258b62b 4805 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
155a97a3
NHE
4806}
4807EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4808
8a3c1a33 4809static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
52fde8df 4810{
8c008659 4811 struct kvm_mmu *context = &vcpu->arch.root_mmu;
594e91a1 4812 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
ad896af0 4813
594e91a1 4814 kvm_init_shadow_mmu(vcpu, &regs);
929d1cfa 4815
d8dd54e0 4816 context->get_guest_pgd = get_cr3;
ad896af0
PB
4817 context->get_pdptr = kvm_pdptr_read;
4818 context->inject_page_fault = kvm_inject_page_fault;
6aa8b732
AK
4819}
4820
8626c120
SC
4821static union kvm_mmu_role
4822kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
654430ef 4823{
8626c120
SC
4824 union kvm_mmu_role role;
4825
4826 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
654430ef
SC
4827
4828 /*
4829 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4830 * shadow pages of their own and so "direct" has no meaning. Set it
4831 * to "true" to try to detect bogus usage of the nested MMU.
4832 */
4833 role.base.direct = true;
f4bd6f73 4834 role.base.level = role_regs_to_root_level(regs);
654430ef
SC
4835 return role;
4836}
4837
8a3c1a33 4838static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
02f59dc9 4839{
8626c120
SC
4840 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4841 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, &regs);
02f59dc9
JR
4842 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4843
bf627a92
VK
4844 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4845 return;
4846
4847 g_context->mmu_role.as_u64 = new_role.as_u64;
d8dd54e0 4848 g_context->get_guest_pgd = get_cr3;
e4e517b4 4849 g_context->get_pdptr = kvm_pdptr_read;
02f59dc9 4850 g_context->inject_page_fault = kvm_inject_page_fault;
5472fcd4 4851 g_context->root_level = new_role.base.level;
02f59dc9 4852
5efac074
PB
4853 /*
4854 * L2 page tables are never shadowed, so there is no need to sync
4855 * SPTEs.
4856 */
4857 g_context->invlpg = NULL;
4858
02f59dc9 4859 /*
44dd3ffa 4860 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
0af2593b
DM
4861 * L1's nested page tables (e.g. EPT12). The nested translation
4862 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4863 * L2's page tables as the first level of translation and L1's
4864 * nested page tables as the second level of translation. Basically
4865 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
02f59dc9 4866 */
fa4b5588 4867 if (!is_paging(vcpu))
02f59dc9 4868 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
fa4b5588 4869 else if (is_long_mode(vcpu))
02f59dc9 4870 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
fa4b5588 4871 else if (is_pae(vcpu))
02f59dc9 4872 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
fa4b5588 4873 else
02f59dc9 4874 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
02f59dc9 4875
533f9a4b 4876 reset_guest_paging_metadata(vcpu, g_context);
02f59dc9
JR
4877}
4878
c9060662 4879void kvm_init_mmu(struct kvm_vcpu *vcpu)
fb72d167 4880{
02f59dc9 4881 if (mmu_is_nested(vcpu))
e0c6db3e 4882 init_kvm_nested_mmu(vcpu);
02f59dc9 4883 else if (tdp_enabled)
e0c6db3e 4884 init_kvm_tdp_mmu(vcpu);
fb72d167 4885 else
e0c6db3e 4886 init_kvm_softmmu(vcpu);
fb72d167 4887}
1c53da3f 4888EXPORT_SYMBOL_GPL(kvm_init_mmu);
fb72d167 4889
9fa72119
JS
4890static union kvm_mmu_page_role
4891kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4892{
8626c120 4893 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
7dcd5755
VK
4894 union kvm_mmu_role role;
4895
9fa72119 4896 if (tdp_enabled)
8626c120 4897 role = kvm_calc_tdp_mmu_root_page_role(vcpu, &regs, true);
9fa72119 4898 else
8626c120 4899 role = kvm_calc_shadow_mmu_root_page_role(vcpu, &regs, true);
7dcd5755
VK
4900
4901 return role.base;
9fa72119 4902}
fb72d167 4903
49c6f875
SC
4904void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4905{
4906 /*
4907 * Invalidate all MMU roles to force them to reinitialize as CPUID
4908 * information is factored into reserved bit calculations.
4909 */
4910 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4911 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4912 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4913 kvm_mmu_reset_context(vcpu);
63f5a190
SC
4914
4915 /*
4916 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4917 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4918 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4919 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4920 * sweep the problem under the rug.
4921 *
4922 * KVM's horrific CPUID ABI makes the problem all but impossible to
4923 * solve, as correctly handling multiple vCPU models (with respect to
4924 * paging and physical address properties) in a single VM would require
4925 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4926 * is very undesirable as it would double the memory requirements for
4927 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4928 * no sane VMM mucks with the core vCPU model on the fly.
4929 */
4930 if (vcpu->arch.last_vmentry_cpu != -1) {
4931 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4932 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4933 }
49c6f875
SC
4934}
4935
8a3c1a33 4936void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
6aa8b732 4937{
95f93af4 4938 kvm_mmu_unload(vcpu);
c9060662 4939 kvm_init_mmu(vcpu);
17c3ba9d 4940}
8668a3c4 4941EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK
4942
4943int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 4944{
714b93da
AK
4945 int r;
4946
378f5cd6 4947 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
17c3ba9d
AK
4948 if (r)
4949 goto out;
748e52b9 4950 r = mmu_alloc_special_roots(vcpu);
17c3ba9d
AK
4951 if (r)
4952 goto out;
4a38162e 4953 if (vcpu->arch.mmu->direct_map)
6e6ec584
SC
4954 r = mmu_alloc_direct_roots(vcpu);
4955 else
4956 r = mmu_alloc_shadow_roots(vcpu);
8986ecc0
MT
4957 if (r)
4958 goto out;
a91f387b
SC
4959
4960 kvm_mmu_sync_roots(vcpu);
4961
727a7e27 4962 kvm_mmu_load_pgd(vcpu);
b3646477 4963 static_call(kvm_x86_tlb_flush_current)(vcpu);
714b93da
AK
4964out:
4965 return r;
6aa8b732 4966}
17c3ba9d
AK
4967
4968void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4969{
14c07ad8
VK
4970 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4971 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4972 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4973 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
17c3ba9d 4974}
6aa8b732 4975
79539cec
AK
4976static bool need_remote_flush(u64 old, u64 new)
4977{
4978 if (!is_shadow_present_pte(old))
4979 return false;
4980 if (!is_shadow_present_pte(new))
4981 return true;
4982 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4983 return true;
53166229
GN
4984 old ^= shadow_nx_mask;
4985 new ^= shadow_nx_mask;
79539cec
AK
4986 return (old & ~new & PT64_PERM_MASK) != 0;
4987}
4988
889e5cbc 4989static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
0e0fee5c 4990 int *bytes)
da4a00f0 4991{
0e0fee5c 4992 u64 gentry = 0;
889e5cbc 4993 int r;
72016f3a 4994
72016f3a
AK
4995 /*
4996 * Assume that the pte write on a page table of the same type
49b26e26
XG
4997 * as the current vcpu paging mode since we update the sptes only
4998 * when they have the same mode.
72016f3a 4999 */
889e5cbc 5000 if (is_pae(vcpu) && *bytes == 4) {
72016f3a 5001 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
889e5cbc
XG
5002 *gpa &= ~(gpa_t)7;
5003 *bytes = 8;
08e850c6
AK
5004 }
5005
0e0fee5c
JS
5006 if (*bytes == 4 || *bytes == 8) {
5007 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5008 if (r)
5009 gentry = 0;
72016f3a
AK
5010 }
5011
889e5cbc
XG
5012 return gentry;
5013}
5014
5015/*
5016 * If we're seeing too many writes to a page, it may no longer be a page table,
5017 * or we may be forking, in which case it is better to unmap the page.
5018 */
a138fe75 5019static bool detect_write_flooding(struct kvm_mmu_page *sp)
889e5cbc 5020{
a30f47cb
XG
5021 /*
5022 * Skip write-flooding detected for the sp whose level is 1, because
5023 * it can become unsync, then the guest page is not write-protected.
5024 */
3bae0459 5025 if (sp->role.level == PG_LEVEL_4K)
a30f47cb 5026 return false;
3246af0e 5027
e5691a81
XG
5028 atomic_inc(&sp->write_flooding_count);
5029 return atomic_read(&sp->write_flooding_count) >= 3;
889e5cbc
XG
5030}
5031
5032/*
5033 * Misaligned accesses are too much trouble to fix up; also, they usually
5034 * indicate a page is not used as a page table.
5035 */
5036static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5037 int bytes)
5038{
5039 unsigned offset, pte_size, misaligned;
5040
5041 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5042 gpa, bytes, sp->role.word);
5043
5044 offset = offset_in_page(gpa);
47c42e6b 5045 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5d9ca30e
XG
5046
5047 /*
5048 * Sometimes, the OS only writes the last one bytes to update status
5049 * bits, for example, in linux, andb instruction is used in clear_bit().
5050 */
5051 if (!(offset & (pte_size - 1)) && bytes == 1)
5052 return false;
5053
889e5cbc
XG
5054 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5055 misaligned |= bytes < 4;
5056
5057 return misaligned;
5058}
5059
5060static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5061{
5062 unsigned page_offset, quadrant;
5063 u64 *spte;
5064 int level;
5065
5066 page_offset = offset_in_page(gpa);
5067 level = sp->role.level;
5068 *nspte = 1;
47c42e6b 5069 if (!sp->role.gpte_is_8_bytes) {
889e5cbc
XG
5070 page_offset <<= 1; /* 32->64 */
5071 /*
5072 * A 32-bit pde maps 4MB while the shadow pdes map
5073 * only 2MB. So we need to double the offset again
5074 * and zap two pdes instead of one.
5075 */
5076 if (level == PT32_ROOT_LEVEL) {
5077 page_offset &= ~7; /* kill rounding error */
5078 page_offset <<= 1;
5079 *nspte = 2;
5080 }
5081 quadrant = page_offset >> PAGE_SHIFT;
5082 page_offset &= ~PAGE_MASK;
5083 if (quadrant != sp->role.quadrant)
5084 return NULL;
5085 }
5086
5087 spte = &sp->spt[page_offset / sizeof(*spte)];
5088 return spte;
5089}
5090
13d268ca 5091static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
d126363d
JS
5092 const u8 *new, int bytes,
5093 struct kvm_page_track_notifier_node *node)
889e5cbc
XG
5094{
5095 gfn_t gfn = gpa >> PAGE_SHIFT;
889e5cbc 5096 struct kvm_mmu_page *sp;
889e5cbc
XG
5097 LIST_HEAD(invalid_list);
5098 u64 entry, gentry, *spte;
5099 int npte;
b8c67b7a 5100 bool remote_flush, local_flush;
889e5cbc
XG
5101
5102 /*
5103 * If we don't have indirect shadow pages, it means no page is
5104 * write-protected, so we can exit simply.
5105 */
6aa7de05 5106 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
889e5cbc
XG
5107 return;
5108
b8c67b7a 5109 remote_flush = local_flush = false;
889e5cbc
XG
5110
5111 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5112
889e5cbc
XG
5113 /*
5114 * No need to care whether allocation memory is successful
d9f6e12f 5115 * or not since pte prefetch is skipped if it does not have
889e5cbc
XG
5116 * enough objects in the cache.
5117 */
378f5cd6 5118 mmu_topup_memory_caches(vcpu, true);
889e5cbc 5119
531810ca 5120 write_lock(&vcpu->kvm->mmu_lock);
0e0fee5c
JS
5121
5122 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5123
889e5cbc 5124 ++vcpu->kvm->stat.mmu_pte_write;
0375f7fa 5125 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
889e5cbc 5126
b67bfe0d 5127 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
a30f47cb 5128 if (detect_write_misaligned(sp, gpa, bytes) ||
a138fe75 5129 detect_write_flooding(sp)) {
b8c67b7a 5130 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4cee5764 5131 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK
5132 continue;
5133 }
889e5cbc
XG
5134
5135 spte = get_written_sptes(sp, gpa, &npte);
5136 if (!spte)
5137 continue;
5138
0671a8e7 5139 local_flush = true;
ac1b714e 5140 while (npte--) {
79539cec 5141 entry = *spte;
2de4085c 5142 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
c5e2184d
SC
5143 if (gentry && sp->role.level != PG_LEVEL_4K)
5144 ++vcpu->kvm->stat.mmu_pde_zapped;
9bb4f6b1 5145 if (need_remote_flush(entry, *spte))
0671a8e7 5146 remote_flush = true;
ac1b714e 5147 ++spte;
9b7a0325 5148 }
9b7a0325 5149 }
b8c67b7a 5150 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
0375f7fa 5151 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
531810ca 5152 write_unlock(&vcpu->kvm->mmu_lock);
da4a00f0
AK
5153}
5154
736c291c 5155int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
dc25e89e 5156 void *insn, int insn_len)
3067714c 5157{
92daa48b 5158 int r, emulation_type = EMULTYPE_PF;
44dd3ffa 5159 bool direct = vcpu->arch.mmu->direct_map;
3067714c 5160
6948199a 5161 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
ddce6208
SC
5162 return RET_PF_RETRY;
5163
9b8ebbdb 5164 r = RET_PF_INVALID;
e9ee956e 5165 if (unlikely(error_code & PFERR_RSVD_MASK)) {
736c291c 5166 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
472faffa 5167 if (r == RET_PF_EMULATE)
e9ee956e 5168 goto emulate;
e9ee956e 5169 }
3067714c 5170
9b8ebbdb 5171 if (r == RET_PF_INVALID) {
7a02674d
SC
5172 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5173 lower_32_bits(error_code), false);
19025e7b 5174 if (KVM_BUG_ON(r == RET_PF_INVALID, vcpu->kvm))
7b367bc9 5175 return -EIO;
9b8ebbdb
PB
5176 }
5177
3067714c 5178 if (r < 0)
e9ee956e 5179 return r;
83a2ba4c
SC
5180 if (r != RET_PF_EMULATE)
5181 return 1;
3067714c 5182
14727754
TL
5183 /*
5184 * Before emulating the instruction, check if the error code
5185 * was due to a RO violation while translating the guest page.
5186 * This can occur when using nested virtualization with nested
5187 * paging in both guests. If true, we simply unprotect the page
5188 * and resume the guest.
14727754 5189 */
44dd3ffa 5190 if (vcpu->arch.mmu->direct_map &&
eebed243 5191 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
736c291c 5192 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
14727754
TL
5193 return 1;
5194 }
5195
472faffa
SC
5196 /*
5197 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5198 * optimistically try to just unprotect the page and let the processor
5199 * re-execute the instruction that caused the page fault. Do not allow
5200 * retrying MMIO emulation, as it's not only pointless but could also
5201 * cause us to enter an infinite loop because the processor will keep
6c3dfeb6
SC
5202 * faulting on the non-existent MMIO address. Retrying an instruction
5203 * from a nested guest is also pointless and dangerous as we are only
5204 * explicitly shadowing L1's page tables, i.e. unprotecting something
5205 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
472faffa 5206 */
736c291c 5207 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
92daa48b 5208 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
e9ee956e 5209emulate:
736c291c 5210 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
60fc3d02 5211 insn_len);
3067714c
AK
5212}
5213EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5214
5efac074
PB
5215void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5216 gva_t gva, hpa_t root_hpa)
a7052897 5217{
b94742c9 5218 int i;
7eb77e9f 5219
5efac074
PB
5220 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5221 if (mmu != &vcpu->arch.guest_mmu) {
5222 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5223 if (is_noncanonical_address(gva, vcpu))
5224 return;
5225
b3646477 5226 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5efac074
PB
5227 }
5228
5229 if (!mmu->invlpg)
faff8758
JS
5230 return;
5231
5efac074
PB
5232 if (root_hpa == INVALID_PAGE) {
5233 mmu->invlpg(vcpu, gva, mmu->root_hpa);
956bf353 5234
5efac074
PB
5235 /*
5236 * INVLPG is required to invalidate any global mappings for the VA,
5237 * irrespective of PCID. Since it would take us roughly similar amount
5238 * of work to determine whether any of the prev_root mappings of the VA
5239 * is marked global, or to just sync it blindly, so we might as well
5240 * just always sync it.
5241 *
5242 * Mappings not reachable via the current cr3 or the prev_roots will be
5243 * synced when switching to that cr3, so nothing needs to be done here
5244 * for them.
5245 */
5246 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5247 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5248 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5249 } else {
5250 mmu->invlpg(vcpu, gva, root_hpa);
5251 }
5252}
956bf353 5253
5efac074
PB
5254void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5255{
5256 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
a7052897
MT
5257 ++vcpu->stat.invlpg;
5258}
5259EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5260
5efac074 5261
eb4b248e
JS
5262void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5263{
44dd3ffa 5264 struct kvm_mmu *mmu = vcpu->arch.mmu;
faff8758 5265 bool tlb_flush = false;
b94742c9 5266 uint i;
eb4b248e
JS
5267
5268 if (pcid == kvm_get_active_pcid(vcpu)) {
7eb77e9f 5269 mmu->invlpg(vcpu, gva, mmu->root_hpa);
faff8758 5270 tlb_flush = true;
eb4b248e
JS
5271 }
5272
b94742c9
JS
5273 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5274 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
be01e8e2 5275 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
b94742c9
JS
5276 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5277 tlb_flush = true;
5278 }
956bf353 5279 }
ade61e28 5280
faff8758 5281 if (tlb_flush)
b3646477 5282 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
faff8758 5283
eb4b248e
JS
5284 ++vcpu->stat.invlpg;
5285
5286 /*
b94742c9
JS
5287 * Mappings not reachable via the current cr3 or the prev_roots will be
5288 * synced when switching to that cr3, so nothing needs to be done here
5289 * for them.
eb4b248e
JS
5290 */
5291}
eb4b248e 5292
83013059
SC
5293void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5294 int tdp_huge_page_level)
18552672 5295{
bde77235 5296 tdp_enabled = enable_tdp;
83013059 5297 max_tdp_level = tdp_max_root_level;
703c335d
SC
5298
5299 /*
1d92d2e8 5300 * max_huge_page_level reflects KVM's MMU capabilities irrespective
703c335d
SC
5301 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5302 * the kernel is not. But, KVM never creates a page size greater than
5303 * what is used by the kernel for any given HVA, i.e. the kernel's
5304 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5305 */
5306 if (tdp_enabled)
1d92d2e8 5307 max_huge_page_level = tdp_huge_page_level;
703c335d 5308 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
1d92d2e8 5309 max_huge_page_level = PG_LEVEL_1G;
703c335d 5310 else
1d92d2e8 5311 max_huge_page_level = PG_LEVEL_2M;
18552672 5312}
bde77235 5313EXPORT_SYMBOL_GPL(kvm_configure_mmu);
85875a13
SC
5314
5315/* The return value indicates if tlb flush on all vcpus is needed. */
269e9552
HM
5316typedef bool (*slot_level_handler) (struct kvm *kvm,
5317 struct kvm_rmap_head *rmap_head,
5318 const struct kvm_memory_slot *slot);
85875a13
SC
5319
5320/* The caller should hold mmu-lock before calling this function. */
5321static __always_inline bool
269e9552 5322slot_handle_level_range(struct kvm *kvm, const struct kvm_memory_slot *memslot,
85875a13 5323 slot_level_handler fn, int start_level, int end_level,
1a61b7db
SC
5324 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5325 bool flush)
85875a13
SC
5326{
5327 struct slot_rmap_walk_iterator iterator;
85875a13
SC
5328
5329 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5330 end_gfn, &iterator) {
5331 if (iterator.rmap)
0a234f5d 5332 flush |= fn(kvm, iterator.rmap, memslot);
85875a13 5333
531810ca 5334 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
302695a5 5335 if (flush && flush_on_yield) {
f285c633
BG
5336 kvm_flush_remote_tlbs_with_address(kvm,
5337 start_gfn,
5338 iterator.gfn - start_gfn + 1);
85875a13
SC
5339 flush = false;
5340 }
531810ca 5341 cond_resched_rwlock_write(&kvm->mmu_lock);
85875a13
SC
5342 }
5343 }
5344
85875a13
SC
5345 return flush;
5346}
5347
5348static __always_inline bool
269e9552 5349slot_handle_level(struct kvm *kvm, const struct kvm_memory_slot *memslot,
85875a13 5350 slot_level_handler fn, int start_level, int end_level,
302695a5 5351 bool flush_on_yield)
85875a13
SC
5352{
5353 return slot_handle_level_range(kvm, memslot, fn, start_level,
5354 end_level, memslot->base_gfn,
5355 memslot->base_gfn + memslot->npages - 1,
1a61b7db 5356 flush_on_yield, false);
85875a13
SC
5357}
5358
85875a13 5359static __always_inline bool
269e9552 5360slot_handle_leaf(struct kvm *kvm, const struct kvm_memory_slot *memslot,
302695a5 5361 slot_level_handler fn, bool flush_on_yield)
85875a13 5362{
3bae0459 5363 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
302695a5 5364 PG_LEVEL_4K, flush_on_yield);
85875a13
SC
5365}
5366
1cfff4d9 5367static void free_mmu_pages(struct kvm_mmu *mmu)
6aa8b732 5368{
4a98623d
SC
5369 if (!tdp_enabled && mmu->pae_root)
5370 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
1cfff4d9 5371 free_page((unsigned long)mmu->pae_root);
03ca4589 5372 free_page((unsigned long)mmu->pml4_root);
6aa8b732
AK
5373}
5374
04d28e37 5375static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
6aa8b732 5376{
17ac10ad 5377 struct page *page;
6aa8b732
AK
5378 int i;
5379
04d28e37
SC
5380 mmu->root_hpa = INVALID_PAGE;
5381 mmu->root_pgd = 0;
5382 mmu->translate_gpa = translate_gpa;
5383 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5384 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5385
17ac10ad 5386 /*
b6b80c78
SC
5387 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5388 * while the PDP table is a per-vCPU construct that's allocated at MMU
5389 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5390 * x86_64. Therefore we need to allocate the PDP table in the first
04d45551
SC
5391 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5392 * generally doesn't use PAE paging and can skip allocating the PDP
5393 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5394 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5395 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
17ac10ad 5396 */
d468d94b 5397 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
b6b80c78
SC
5398 return 0;
5399
254272ce 5400 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
17ac10ad 5401 if (!page)
d7fa6ab2
WY
5402 return -ENOMEM;
5403
1cfff4d9 5404 mmu->pae_root = page_address(page);
4a98623d
SC
5405
5406 /*
5407 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5408 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5409 * that KVM's writes and the CPU's reads get along. Note, this is
5410 * only necessary when using shadow paging, as 64-bit NPT can get at
5411 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5412 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5413 */
5414 if (!tdp_enabled)
5415 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5416 else
5417 WARN_ON_ONCE(shadow_me_mask);
5418
17ac10ad 5419 for (i = 0; i < 4; ++i)
c834e5e4 5420 mmu->pae_root[i] = INVALID_PAE_ROOT;
17ac10ad 5421
6aa8b732 5422 return 0;
6aa8b732
AK
5423}
5424
8018c27b 5425int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 5426{
1cfff4d9 5427 int ret;
b94742c9 5428
5962bfb7 5429 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5f6078f9
SC
5430 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5431
5962bfb7 5432 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5f6078f9 5433 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5962bfb7 5434
96880883
SC
5435 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5436
44dd3ffa
VK
5437 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5438 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
6aa8b732 5439
14c07ad8 5440 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
1cfff4d9 5441
04d28e37 5442 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
1cfff4d9
JP
5443 if (ret)
5444 return ret;
5445
04d28e37 5446 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
1cfff4d9
JP
5447 if (ret)
5448 goto fail_allocate_root;
5449
5450 return ret;
5451 fail_allocate_root:
5452 free_mmu_pages(&vcpu->arch.guest_mmu);
5453 return ret;
6aa8b732
AK
5454}
5455
fbb158cb 5456#define BATCH_ZAP_PAGES 10
002c5f73
SC
5457static void kvm_zap_obsolete_pages(struct kvm *kvm)
5458{
5459 struct kvm_mmu_page *sp, *node;
fbb158cb 5460 int nr_zapped, batch = 0;
002c5f73
SC
5461
5462restart:
5463 list_for_each_entry_safe_reverse(sp, node,
5464 &kvm->arch.active_mmu_pages, link) {
5465 /*
5466 * No obsolete valid page exists before a newly created page
5467 * since active_mmu_pages is a FIFO list.
5468 */
5469 if (!is_obsolete_sp(kvm, sp))
5470 break;
5471
5472 /*
f95eec9b
SC
5473 * Invalid pages should never land back on the list of active
5474 * pages. Skip the bogus page, otherwise we'll get stuck in an
5475 * infinite loop if the page gets put back on the list (again).
002c5f73 5476 */
f95eec9b 5477 if (WARN_ON(sp->role.invalid))
002c5f73
SC
5478 continue;
5479
4506ecf4
SC
5480 /*
5481 * No need to flush the TLB since we're only zapping shadow
5482 * pages with an obsolete generation number and all vCPUS have
5483 * loaded a new root, i.e. the shadow pages being zapped cannot
5484 * be in active use by the guest.
5485 */
fbb158cb 5486 if (batch >= BATCH_ZAP_PAGES &&
531810ca 5487 cond_resched_rwlock_write(&kvm->mmu_lock)) {
fbb158cb 5488 batch = 0;
002c5f73
SC
5489 goto restart;
5490 }
5491
10605204
SC
5492 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5493 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
fbb158cb 5494 batch += nr_zapped;
002c5f73 5495 goto restart;
fbb158cb 5496 }
002c5f73
SC
5497 }
5498
4506ecf4
SC
5499 /*
5500 * Trigger a remote TLB flush before freeing the page tables to ensure
5501 * KVM is not in the middle of a lockless shadow page table walk, which
5502 * may reference the pages.
5503 */
10605204 5504 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
002c5f73
SC
5505}
5506
5507/*
5508 * Fast invalidate all shadow pages and use lock-break technique
5509 * to zap obsolete pages.
5510 *
5511 * It's required when memslot is being deleted or VM is being
5512 * destroyed, in these cases, we should ensure that KVM MMU does
5513 * not use any resource of the being-deleted slot or all slots
5514 * after calling the function.
5515 */
5516static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5517{
ca333add
SC
5518 lockdep_assert_held(&kvm->slots_lock);
5519
531810ca 5520 write_lock(&kvm->mmu_lock);
14a3c4f4 5521 trace_kvm_mmu_zap_all_fast(kvm);
ca333add
SC
5522
5523 /*
5524 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5525 * held for the entire duration of zapping obsolete pages, it's
5526 * impossible for there to be multiple invalid generations associated
5527 * with *valid* shadow pages at any given time, i.e. there is exactly
5528 * one valid generation and (at most) one invalid generation.
5529 */
5530 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
002c5f73 5531
b7cccd39
BG
5532 /* In order to ensure all threads see this change when
5533 * handling the MMU reload signal, this must happen in the
5534 * same critical section as kvm_reload_remote_mmus, and
5535 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5536 * could drop the MMU lock and yield.
5537 */
5538 if (is_tdp_mmu_enabled(kvm))
5539 kvm_tdp_mmu_invalidate_all_roots(kvm);
5540
4506ecf4
SC
5541 /*
5542 * Notify all vcpus to reload its shadow page table and flush TLB.
5543 * Then all vcpus will switch to new shadow page table with the new
5544 * mmu_valid_gen.
5545 *
5546 * Note: we need to do this under the protection of mmu_lock,
5547 * otherwise, vcpu would purge shadow page but miss tlb flush.
5548 */
5549 kvm_reload_remote_mmus(kvm);
5550
002c5f73 5551 kvm_zap_obsolete_pages(kvm);
faaf05b0 5552
531810ca 5553 write_unlock(&kvm->mmu_lock);
4c6654bd
BG
5554
5555 if (is_tdp_mmu_enabled(kvm)) {
5556 read_lock(&kvm->mmu_lock);
5557 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5558 read_unlock(&kvm->mmu_lock);
5559 }
002c5f73
SC
5560}
5561
10605204
SC
5562static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5563{
5564 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5565}
5566
b5f5fdca 5567static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
d126363d
JS
5568 struct kvm_memory_slot *slot,
5569 struct kvm_page_track_notifier_node *node)
b5f5fdca 5570{
002c5f73 5571 kvm_mmu_zap_all_fast(kvm);
1bad2b2a
XG
5572}
5573
13d268ca 5574void kvm_mmu_init_vm(struct kvm *kvm)
1bad2b2a 5575{
13d268ca 5576 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
1bad2b2a 5577
d501f747
BG
5578 if (!kvm_mmu_init_tdp_mmu(kvm))
5579 /*
5580 * No smp_load/store wrappers needed here as we are in
5581 * VM init and there cannot be any memslots / other threads
5582 * accessing this struct kvm yet.
5583 */
5584 kvm->arch.memslots_have_rmaps = true;
fe5db27d 5585
13d268ca 5586 node->track_write = kvm_mmu_pte_write;
b5f5fdca 5587 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
13d268ca 5588 kvm_page_track_register_notifier(kvm, node);
1bad2b2a
XG
5589}
5590
13d268ca 5591void kvm_mmu_uninit_vm(struct kvm *kvm)
1bad2b2a 5592{
13d268ca 5593 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
1bad2b2a 5594
13d268ca 5595 kvm_page_track_unregister_notifier(kvm, node);
fe5db27d
BG
5596
5597 kvm_mmu_uninit_tdp_mmu(kvm);
1bad2b2a
XG
5598}
5599
efdfe536
XG
5600void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5601{
5602 struct kvm_memslots *slots;
5603 struct kvm_memory_slot *memslot;
9da0e4d5 5604 int i;
1a61b7db 5605 bool flush = false;
efdfe536 5606
e2209710
BG
5607 if (kvm_memslots_have_rmaps(kvm)) {
5608 write_lock(&kvm->mmu_lock);
5609 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5610 slots = __kvm_memslots(kvm, i);
5611 kvm_for_each_memslot(memslot, slots) {
5612 gfn_t start, end;
5613
5614 start = max(gfn_start, memslot->base_gfn);
5615 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5616 if (start >= end)
5617 continue;
efdfe536 5618
269e9552
HM
5619 flush = slot_handle_level_range(kvm,
5620 (const struct kvm_memory_slot *) memslot,
e2209710
BG
5621 kvm_zap_rmapp, PG_LEVEL_4K,
5622 KVM_MAX_HUGEPAGE_LEVEL, start,
5623 end - 1, true, flush);
5624 }
9da0e4d5 5625 }
e2209710
BG
5626 if (flush)
5627 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5628 write_unlock(&kvm->mmu_lock);
efdfe536
XG
5629 }
5630
897218ff 5631 if (is_tdp_mmu_enabled(kvm)) {
6103bc07
BG
5632 flush = false;
5633
5634 read_lock(&kvm->mmu_lock);
5635 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5636 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5637 gfn_end, flush, true);
faaf05b0 5638 if (flush)
6103bc07
BG
5639 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5640 gfn_end);
faaf05b0 5641
6103bc07
BG
5642 read_unlock(&kvm->mmu_lock);
5643 }
efdfe536
XG
5644}
5645
018aabb5 5646static bool slot_rmap_write_protect(struct kvm *kvm,
0a234f5d 5647 struct kvm_rmap_head *rmap_head,
269e9552 5648 const struct kvm_memory_slot *slot)
d77aa73c 5649{
018aabb5 5650 return __rmap_write_protect(kvm, rmap_head, false);
d77aa73c
XG
5651}
5652
1c91cad4 5653void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
269e9552 5654 const struct kvm_memory_slot *memslot,
3c9bd400 5655 int start_level)
6aa8b732 5656{
e2209710 5657 bool flush = false;
6aa8b732 5658
e2209710
BG
5659 if (kvm_memslots_have_rmaps(kvm)) {
5660 write_lock(&kvm->mmu_lock);
5661 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5662 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5663 false);
5664 write_unlock(&kvm->mmu_lock);
5665 }
198c74f4 5666
24ae4cfa
BG
5667 if (is_tdp_mmu_enabled(kvm)) {
5668 read_lock(&kvm->mmu_lock);
5669 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5670 read_unlock(&kvm->mmu_lock);
5671 }
5672
198c74f4
XG
5673 /*
5674 * We can flush all the TLBs out of the mmu lock without TLB
5675 * corruption since we just change the spte from writable to
5676 * readonly so that we only need to care the case of changing
5677 * spte from present to present (changing the spte from present
5678 * to nonpresent will flush all the TLBs immediately), in other
5679 * words, the only case we care is mmu_spte_update() where we
5fc3424f
SC
5680 * have checked Host-writable | MMU-writable instead of
5681 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5682 * anymore.
198c74f4 5683 */
d91ffee9 5684 if (flush)
7f42aa76 5685 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
6aa8b732 5686}
37a7d8b0 5687
3ea3b7fa 5688static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
0a234f5d 5689 struct kvm_rmap_head *rmap_head,
269e9552 5690 const struct kvm_memory_slot *slot)
3ea3b7fa
WL
5691{
5692 u64 *sptep;
5693 struct rmap_iterator iter;
5694 int need_tlb_flush = 0;
ba049e93 5695 kvm_pfn_t pfn;
3ea3b7fa
WL
5696 struct kvm_mmu_page *sp;
5697
0d536790 5698restart:
018aabb5 5699 for_each_rmap_spte(rmap_head, &iter, sptep) {
57354682 5700 sp = sptep_to_sp(sptep);
3ea3b7fa
WL
5701 pfn = spte_to_pfn(*sptep);
5702
5703 /*
decf6333
XG
5704 * We cannot do huge page mapping for indirect shadow pages,
5705 * which are found on the last rmap (level = 1) when not using
5706 * tdp; such shadow pages are synced with the page table in
5707 * the guest, and the guest page table is using 4K page size
5708 * mapping if the indirect sp has level = 1.
3ea3b7fa 5709 */
a78986aa 5710 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
9eba50f8
SC
5711 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5712 pfn, PG_LEVEL_NUM)) {
e7912386 5713 pte_list_remove(rmap_head, sptep);
40ef75a7
LT
5714
5715 if (kvm_available_flush_tlb_with_range())
5716 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5717 KVM_PAGES_PER_HPAGE(sp->role.level));
5718 else
5719 need_tlb_flush = 1;
5720
0d536790
XG
5721 goto restart;
5722 }
3ea3b7fa
WL
5723 }
5724
5725 return need_tlb_flush;
5726}
5727
5728void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
269e9552 5729 const struct kvm_memory_slot *slot)
3ea3b7fa 5730{
31c65657 5731 bool flush = false;
14881998 5732
e2209710
BG
5733 if (kvm_memslots_have_rmaps(kvm)) {
5734 write_lock(&kvm->mmu_lock);
5735 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5736 if (flush)
5737 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5738 write_unlock(&kvm->mmu_lock);
5739 }
2db6f772
BG
5740
5741 if (is_tdp_mmu_enabled(kvm)) {
2db6f772
BG
5742 read_lock(&kvm->mmu_lock);
5743 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5744 if (flush)
5745 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5746 read_unlock(&kvm->mmu_lock);
5747 }
3ea3b7fa
WL
5748}
5749
b3594ffb 5750void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
6c9dd6d2 5751 const struct kvm_memory_slot *memslot)
b3594ffb
SC
5752{
5753 /*
7f42aa76 5754 * All current use cases for flushing the TLBs for a specific memslot
302695a5 5755 * related to dirty logging, and many do the TLB flush out of mmu_lock.
7f42aa76
SC
5756 * The interaction between the various operations on memslot must be
5757 * serialized by slots_locks to ensure the TLB flush from one operation
5758 * is observed by any other operation on the same memslot.
b3594ffb
SC
5759 */
5760 lockdep_assert_held(&kvm->slots_lock);
cec37648
SC
5761 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5762 memslot->npages);
b3594ffb
SC
5763}
5764
f4b4b180 5765void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
269e9552 5766 const struct kvm_memory_slot *memslot)
f4b4b180 5767{
e2209710 5768 bool flush = false;
f4b4b180 5769
e2209710
BG
5770 if (kvm_memslots_have_rmaps(kvm)) {
5771 write_lock(&kvm->mmu_lock);
5772 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5773 false);
5774 write_unlock(&kvm->mmu_lock);
5775 }
f4b4b180 5776
24ae4cfa
BG
5777 if (is_tdp_mmu_enabled(kvm)) {
5778 read_lock(&kvm->mmu_lock);
5779 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5780 read_unlock(&kvm->mmu_lock);
5781 }
5782
f4b4b180
KH
5783 /*
5784 * It's also safe to flush TLBs out of mmu lock here as currently this
5785 * function is only used for dirty logging, in which case flushing TLB
5786 * out of mmu lock also guarantees no dirty pages will be lost in
5787 * dirty_bitmap.
5788 */
5789 if (flush)
7f42aa76 5790 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
f4b4b180 5791}
f4b4b180 5792
92f58b5c 5793void kvm_mmu_zap_all(struct kvm *kvm)
5304b8d3
XG
5794{
5795 struct kvm_mmu_page *sp, *node;
7390de1e 5796 LIST_HEAD(invalid_list);
83cdb568 5797 int ign;
5304b8d3 5798
531810ca 5799 write_lock(&kvm->mmu_lock);
5304b8d3 5800restart:
8a674adc 5801 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
f95eec9b 5802 if (WARN_ON(sp->role.invalid))
4771450c 5803 continue;
92f58b5c 5804 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5304b8d3 5805 goto restart;
531810ca 5806 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5304b8d3
XG
5807 goto restart;
5808 }
5809
4771450c 5810 kvm_mmu_commit_zap_page(kvm, &invalid_list);
faaf05b0 5811
897218ff 5812 if (is_tdp_mmu_enabled(kvm))
faaf05b0
BG
5813 kvm_tdp_mmu_zap_all(kvm);
5814
531810ca 5815 write_unlock(&kvm->mmu_lock);
5304b8d3
XG
5816}
5817
15248258 5818void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
f8f55942 5819{
164bf7e5 5820 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
e1359e2b 5821
164bf7e5 5822 gen &= MMIO_SPTE_GEN_MASK;
e1359e2b 5823
f8f55942 5824 /*
e1359e2b
SC
5825 * Generation numbers are incremented in multiples of the number of
5826 * address spaces in order to provide unique generations across all
5827 * address spaces. Strip what is effectively the address space
5828 * modifier prior to checking for a wrap of the MMIO generation so
5829 * that a wrap in any address space is detected.
5830 */
5831 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5832
f8f55942 5833 /*
e1359e2b 5834 * The very rare case: if the MMIO generation number has wrapped,
f8f55942 5835 * zap all shadow pages.
f8f55942 5836 */
e1359e2b 5837 if (unlikely(gen == 0)) {
ae0f5499 5838 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
92f58b5c 5839 kvm_mmu_zap_all_fast(kvm);
7a2e8aaf 5840 }
f8f55942
XG
5841}
5842
70534a73
DC
5843static unsigned long
5844mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
3ee16c81
IE
5845{
5846 struct kvm *kvm;
1495f230 5847 int nr_to_scan = sc->nr_to_scan;
70534a73 5848 unsigned long freed = 0;
3ee16c81 5849
0d9ce162 5850 mutex_lock(&kvm_lock);
3ee16c81
IE
5851
5852 list_for_each_entry(kvm, &vm_list, vm_list) {
3d56cbdf 5853 int idx;
d98ba053 5854 LIST_HEAD(invalid_list);
3ee16c81 5855
35f2d16b
TY
5856 /*
5857 * Never scan more than sc->nr_to_scan VM instances.
5858 * Will not hit this condition practically since we do not try
5859 * to shrink more than one VM and it is very unlikely to see
5860 * !n_used_mmu_pages so many times.
5861 */
5862 if (!nr_to_scan--)
5863 break;
19526396
GN
5864 /*
5865 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5866 * here. We may skip a VM instance errorneosly, but we do not
5867 * want to shrink a VM that only started to populate its MMU
5868 * anyway.
5869 */
10605204
SC
5870 if (!kvm->arch.n_used_mmu_pages &&
5871 !kvm_has_zapped_obsolete_pages(kvm))
19526396 5872 continue;
19526396 5873
f656ce01 5874 idx = srcu_read_lock(&kvm->srcu);
531810ca 5875 write_lock(&kvm->mmu_lock);
3ee16c81 5876
10605204
SC
5877 if (kvm_has_zapped_obsolete_pages(kvm)) {
5878 kvm_mmu_commit_zap_page(kvm,
5879 &kvm->arch.zapped_obsolete_pages);
5880 goto unlock;
5881 }
5882
ebdb292d 5883 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
19526396 5884
10605204 5885unlock:
531810ca 5886 write_unlock(&kvm->mmu_lock);
f656ce01 5887 srcu_read_unlock(&kvm->srcu, idx);
19526396 5888
70534a73
DC
5889 /*
5890 * unfair on small ones
5891 * per-vm shrinkers cry out
5892 * sadness comes quickly
5893 */
19526396
GN
5894 list_move_tail(&kvm->vm_list, &vm_list);
5895 break;
3ee16c81 5896 }
3ee16c81 5897
0d9ce162 5898 mutex_unlock(&kvm_lock);
70534a73 5899 return freed;
70534a73
DC
5900}
5901
5902static unsigned long
5903mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5904{
45221ab6 5905 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3ee16c81
IE
5906}
5907
5908static struct shrinker mmu_shrinker = {
70534a73
DC
5909 .count_objects = mmu_shrink_count,
5910 .scan_objects = mmu_shrink_scan,
3ee16c81
IE
5911 .seeks = DEFAULT_SEEKS * 10,
5912};
5913
2ddfd20e 5914static void mmu_destroy_caches(void)
b5a33a75 5915{
c1bd743e
TH
5916 kmem_cache_destroy(pte_list_desc_cache);
5917 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
5918}
5919
b8e8c830
PB
5920static bool get_nx_auto_mode(void)
5921{
5922 /* Return true when CPU has the bug, and mitigations are ON */
5923 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5924}
5925
5926static void __set_nx_huge_pages(bool val)
5927{
5928 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5929}
5930
5931static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5932{
5933 bool old_val = nx_huge_pages;
5934 bool new_val;
5935
5936 /* In "auto" mode deploy workaround only if CPU has the bug. */
5937 if (sysfs_streq(val, "off"))
5938 new_val = 0;
5939 else if (sysfs_streq(val, "force"))
5940 new_val = 1;
5941 else if (sysfs_streq(val, "auto"))
5942 new_val = get_nx_auto_mode();
5943 else if (strtobool(val, &new_val) < 0)
5944 return -EINVAL;
5945
5946 __set_nx_huge_pages(new_val);
5947
5948 if (new_val != old_val) {
5949 struct kvm *kvm;
b8e8c830
PB
5950
5951 mutex_lock(&kvm_lock);
5952
5953 list_for_each_entry(kvm, &vm_list, vm_list) {
ed69a6cb 5954 mutex_lock(&kvm->slots_lock);
b8e8c830 5955 kvm_mmu_zap_all_fast(kvm);
ed69a6cb 5956 mutex_unlock(&kvm->slots_lock);
1aa9b957
JS
5957
5958 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
b8e8c830
PB
5959 }
5960 mutex_unlock(&kvm_lock);
5961 }
5962
5963 return 0;
5964}
5965
b5a33a75
AK
5966int kvm_mmu_module_init(void)
5967{
ab271bd4
AB
5968 int ret = -ENOMEM;
5969
b8e8c830
PB
5970 if (nx_huge_pages == -1)
5971 __set_nx_huge_pages(get_nx_auto_mode());
5972
36d9594d
VK
5973 /*
5974 * MMU roles use union aliasing which is, generally speaking, an
5975 * undefined behavior. However, we supposedly know how compilers behave
5976 * and the current status quo is unlikely to change. Guardians below are
5977 * supposed to let us know if the assumption becomes false.
5978 */
5979 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5980 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5981 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5982
28a1f3ac 5983 kvm_mmu_reset_all_pte_masks();
f160c7b7 5984
53c07b18
XG
5985 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5986 sizeof(struct pte_list_desc),
46bea48a 5987 0, SLAB_ACCOUNT, NULL);
53c07b18 5988 if (!pte_list_desc_cache)
ab271bd4 5989 goto out;
b5a33a75 5990
d3d25b04
AK
5991 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5992 sizeof(struct kvm_mmu_page),
46bea48a 5993 0, SLAB_ACCOUNT, NULL);
d3d25b04 5994 if (!mmu_page_header_cache)
ab271bd4 5995 goto out;
d3d25b04 5996
908c7f19 5997 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
ab271bd4 5998 goto out;
45bf21a8 5999
ab271bd4
AB
6000 ret = register_shrinker(&mmu_shrinker);
6001 if (ret)
6002 goto out;
3ee16c81 6003
b5a33a75
AK
6004 return 0;
6005
ab271bd4 6006out:
3ee16c81 6007 mmu_destroy_caches();
ab271bd4 6008 return ret;
b5a33a75
AK
6009}
6010
3ad82a7e 6011/*
39337ad1 6012 * Calculate mmu pages needed for kvm.
3ad82a7e 6013 */
bc8a3d89 6014unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
3ad82a7e 6015{
bc8a3d89
BG
6016 unsigned long nr_mmu_pages;
6017 unsigned long nr_pages = 0;
bc6678a3 6018 struct kvm_memslots *slots;
be6ba0f0 6019 struct kvm_memory_slot *memslot;
9da0e4d5 6020 int i;
3ad82a7e 6021
9da0e4d5
PB
6022 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6023 slots = __kvm_memslots(kvm, i);
90d83dc3 6024
9da0e4d5
PB
6025 kvm_for_each_memslot(memslot, slots)
6026 nr_pages += memslot->npages;
6027 }
3ad82a7e
ZX
6028
6029 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
bc8a3d89 6030 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
3ad82a7e
ZX
6031
6032 return nr_mmu_pages;
6033}
6034
c42fffe3
XG
6035void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6036{
95f93af4 6037 kvm_mmu_unload(vcpu);
1cfff4d9
JP
6038 free_mmu_pages(&vcpu->arch.root_mmu);
6039 free_mmu_pages(&vcpu->arch.guest_mmu);
c42fffe3 6040 mmu_free_memory_caches(vcpu);
b034cf01
XG
6041}
6042
b034cf01
XG
6043void kvm_mmu_module_exit(void)
6044{
6045 mmu_destroy_caches();
6046 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6047 unregister_shrinker(&mmu_shrinker);
c42fffe3
XG
6048 mmu_audit_disable();
6049}
1aa9b957
JS
6050
6051static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6052{
6053 unsigned int old_val;
6054 int err;
6055
6056 old_val = nx_huge_pages_recovery_ratio;
6057 err = param_set_uint(val, kp);
6058 if (err)
6059 return err;
6060
6061 if (READ_ONCE(nx_huge_pages) &&
6062 !old_val && nx_huge_pages_recovery_ratio) {
6063 struct kvm *kvm;
6064
6065 mutex_lock(&kvm_lock);
6066
6067 list_for_each_entry(kvm, &vm_list, vm_list)
6068 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6069
6070 mutex_unlock(&kvm_lock);
6071 }
6072
6073 return err;
6074}
6075
6076static void kvm_recover_nx_lpages(struct kvm *kvm)
6077{
ade74e14 6078 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
1aa9b957
JS
6079 int rcu_idx;
6080 struct kvm_mmu_page *sp;
6081 unsigned int ratio;
6082 LIST_HEAD(invalid_list);
048f4980 6083 bool flush = false;
1aa9b957
JS
6084 ulong to_zap;
6085
6086 rcu_idx = srcu_read_lock(&kvm->srcu);
531810ca 6087 write_lock(&kvm->mmu_lock);
1aa9b957
JS
6088
6089 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
ade74e14 6090 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
7d919c7a
SC
6091 for ( ; to_zap; --to_zap) {
6092 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6093 break;
6094
1aa9b957
JS
6095 /*
6096 * We use a separate list instead of just using active_mmu_pages
6097 * because the number of lpage_disallowed pages is expected to
6098 * be relatively small compared to the total.
6099 */
6100 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6101 struct kvm_mmu_page,
6102 lpage_disallowed_link);
6103 WARN_ON_ONCE(!sp->lpage_disallowed);
897218ff 6104 if (is_tdp_mmu_page(sp)) {
315f02c6 6105 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
8d1a182e 6106 } else {
29cf0f50
BG
6107 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6108 WARN_ON_ONCE(sp->lpage_disallowed);
6109 }
1aa9b957 6110
531810ca 6111 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
048f4980 6112 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
531810ca 6113 cond_resched_rwlock_write(&kvm->mmu_lock);
048f4980 6114 flush = false;
1aa9b957
JS
6115 }
6116 }
048f4980 6117 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
1aa9b957 6118
531810ca 6119 write_unlock(&kvm->mmu_lock);
1aa9b957
JS
6120 srcu_read_unlock(&kvm->srcu, rcu_idx);
6121}
6122
6123static long get_nx_lpage_recovery_timeout(u64 start_time)
6124{
6125 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6126 ? start_time + 60 * HZ - get_jiffies_64()
6127 : MAX_SCHEDULE_TIMEOUT;
6128}
6129
6130static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6131{
6132 u64 start_time;
6133 long remaining_time;
6134
6135 while (true) {
6136 start_time = get_jiffies_64();
6137 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6138
6139 set_current_state(TASK_INTERRUPTIBLE);
6140 while (!kthread_should_stop() && remaining_time > 0) {
6141 schedule_timeout(remaining_time);
6142 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6143 set_current_state(TASK_INTERRUPTIBLE);
6144 }
6145
6146 set_current_state(TASK_RUNNING);
6147
6148 if (kthread_should_stop())
6149 return 0;
6150
6151 kvm_recover_nx_lpages(kvm);
6152 }
6153}
6154
6155int kvm_mmu_post_init_vm(struct kvm *kvm)
6156{
6157 int err;
6158
6159 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6160 "kvm-nx-lpage-recovery",
6161 &kvm->arch.nx_lpage_recovery_thread);
6162 if (!err)
6163 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6164
6165 return err;
6166}
6167
6168void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6169{
6170 if (kvm->arch.nx_lpage_recovery_thread)
6171 kthread_stop(kvm->arch.nx_lpage_recovery_thread);
6172}