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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
4a98623d | 51 | #include <asm/set_memory.h> |
13673a90 | 52 | #include <asm/vmx.h> |
3d0c27ad | 53 | #include <asm/kvm_page_track.h> |
1261bfa3 | 54 | #include "trace.h" |
6aa8b732 | 55 | |
b8e8c830 PB |
56 | extern bool itlb_multihit_kvm_mitigation; |
57 | ||
a9d6496d | 58 | int __read_mostly nx_huge_pages = -1; |
13fb5927 PB |
59 | #ifdef CONFIG_PREEMPT_RT |
60 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
61 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
62 | #else | |
1aa9b957 | 63 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 64 | #endif |
b8e8c830 PB |
65 | |
66 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 67 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 68 | |
d5d6c18d | 69 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
70 | .set = set_nx_huge_pages, |
71 | .get = param_get_bool, | |
72 | }; | |
73 | ||
d5d6c18d | 74 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
75 | .set = set_nx_huge_pages_recovery_ratio, |
76 | .get = param_get_uint, | |
77 | }; | |
78 | ||
b8e8c830 PB |
79 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
80 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
81 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
82 | &nx_huge_pages_recovery_ratio, 0644); | |
83 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 84 | |
71fe7013 SC |
85 | static bool __read_mostly force_flush_and_sync_on_reuse; |
86 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
87 | ||
18552672 JR |
88 | /* |
89 | * When setting this variable to true it enables Two-Dimensional-Paging | |
90 | * where the hardware walks 2 page tables: | |
91 | * 1. the guest-virtual to guest-physical | |
92 | * 2. while doing 1. it walks guest-physical to host-physical | |
93 | * If the hardware supports that we don't need to do shadow paging. | |
94 | */ | |
2f333bcb | 95 | bool tdp_enabled = false; |
18552672 | 96 | |
1d92d2e8 | 97 | static int max_huge_page_level __read_mostly; |
83013059 | 98 | static int max_tdp_level __read_mostly; |
703c335d | 99 | |
8b1fe17c XG |
100 | enum { |
101 | AUDIT_PRE_PAGE_FAULT, | |
102 | AUDIT_POST_PAGE_FAULT, | |
103 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
104 | AUDIT_POST_PTE_WRITE, |
105 | AUDIT_PRE_SYNC, | |
106 | AUDIT_POST_SYNC | |
8b1fe17c | 107 | }; |
37a7d8b0 | 108 | |
37a7d8b0 | 109 | #ifdef MMU_DEBUG |
5a9624af | 110 | bool dbg = 0; |
fa4a2c08 | 111 | module_param(dbg, bool, 0644); |
d6c69ee9 | 112 | #endif |
6aa8b732 | 113 | |
957ed9ef XG |
114 | #define PTE_PREFETCH_NUM 8 |
115 | ||
6aa8b732 AK |
116 | #define PT32_LEVEL_BITS 10 |
117 | ||
118 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 119 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 120 | |
e04da980 JR |
121 | #define PT32_LVL_OFFSET_MASK(level) \ |
122 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
124 | |
125 | #define PT32_INDEX(address, level)\ | |
126 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
127 | ||
128 | ||
6aa8b732 AK |
129 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
130 | #define PT32_DIR_BASE_ADDR_MASK \ | |
131 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
132 | #define PT32_LVL_ADDR_MASK(level) \ |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
134 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 135 | |
90bb6fc5 AK |
136 | #include <trace/events/kvm.h> |
137 | ||
220f773a TY |
138 | /* make pte_list_desc fit well in cache line */ |
139 | #define PTE_LIST_EXT 3 | |
140 | ||
53c07b18 XG |
141 | struct pte_list_desc { |
142 | u64 *sptes[PTE_LIST_EXT]; | |
143 | struct pte_list_desc *more; | |
cd4a4e53 AK |
144 | }; |
145 | ||
2d11123a AK |
146 | struct kvm_shadow_walk_iterator { |
147 | u64 addr; | |
148 | hpa_t shadow_addr; | |
2d11123a | 149 | u64 *sptep; |
dd3bfd59 | 150 | int level; |
2d11123a AK |
151 | unsigned index; |
152 | }; | |
153 | ||
7eb77e9f JS |
154 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
155 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
156 | (_root), (_addr)); \ | |
157 | shadow_walk_okay(&(_walker)); \ | |
158 | shadow_walk_next(&(_walker))) | |
159 | ||
160 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
161 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
162 | shadow_walk_okay(&(_walker)); \ | |
163 | shadow_walk_next(&(_walker))) | |
164 | ||
c2a2ac2b XG |
165 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
166 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
167 | shadow_walk_okay(&(_walker)) && \ | |
168 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
169 | __shadow_walk_next(&(_walker), spte)) | |
170 | ||
53c07b18 | 171 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 172 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 173 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 174 | |
ce88decf | 175 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
176 | static union kvm_mmu_page_role |
177 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 178 | |
594e91a1 SC |
179 | struct kvm_mmu_role_regs { |
180 | const unsigned long cr0; | |
181 | const unsigned long cr4; | |
182 | const u64 efer; | |
183 | }; | |
184 | ||
335e192a PB |
185 | #define CREATE_TRACE_POINTS |
186 | #include "mmutrace.h" | |
187 | ||
594e91a1 SC |
188 | /* |
189 | * Yes, lot's of underscores. They're a hint that you probably shouldn't be | |
190 | * reading from the role_regs. Once the mmu_role is constructed, it becomes | |
191 | * the single source of truth for the MMU's state. | |
192 | */ | |
193 | #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \ | |
194 | static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\ | |
195 | { \ | |
196 | return !!(regs->reg & flag); \ | |
197 | } | |
198 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG); | |
199 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP); | |
200 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE); | |
201 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE); | |
202 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP); | |
203 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP); | |
204 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE); | |
205 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57); | |
206 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX); | |
207 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA); | |
208 | ||
60667724 SC |
209 | /* |
210 | * The MMU itself (with a valid role) is the single source of truth for the | |
211 | * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The | |
212 | * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1, | |
213 | * and the vCPU may be incorrect/irrelevant. | |
214 | */ | |
215 | #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \ | |
216 | static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \ | |
217 | { \ | |
218 | return !!(mmu->mmu_role. base_or_ext . reg##_##name); \ | |
219 | } | |
220 | BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg); | |
221 | BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp); | |
222 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse); | |
223 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae); | |
224 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep); | |
225 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap); | |
226 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke); | |
227 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57); | |
228 | BUILD_MMU_ROLE_ACCESSOR(base, efer, nx); | |
229 | ||
594e91a1 SC |
230 | static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu) |
231 | { | |
232 | struct kvm_mmu_role_regs regs = { | |
233 | .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS), | |
234 | .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS), | |
235 | .efer = vcpu->arch.efer, | |
236 | }; | |
237 | ||
238 | return regs; | |
239 | } | |
40ef75a7 LT |
240 | |
241 | static inline bool kvm_available_flush_tlb_with_range(void) | |
242 | { | |
afaf0b2f | 243 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
244 | } |
245 | ||
246 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
247 | struct kvm_tlb_range *range) | |
248 | { | |
249 | int ret = -ENOTSUPP; | |
250 | ||
afaf0b2f | 251 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
b3646477 | 252 | ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range); |
40ef75a7 LT |
253 | |
254 | if (ret) | |
255 | kvm_flush_remote_tlbs(kvm); | |
256 | } | |
257 | ||
2f2fad08 | 258 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
259 | u64 start_gfn, u64 pages) |
260 | { | |
261 | struct kvm_tlb_range range; | |
262 | ||
263 | range.start_gfn = start_gfn; | |
264 | range.pages = pages; | |
265 | ||
266 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
267 | } | |
268 | ||
8f79b064 BG |
269 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
270 | unsigned int access) | |
271 | { | |
c236d962 | 272 | u64 spte = make_mmio_spte(vcpu, gfn, access); |
8f79b064 | 273 | |
c236d962 SC |
274 | trace_mark_mmio_spte(sptep, gfn, spte); |
275 | mmu_spte_set(sptep, spte); | |
ce88decf XG |
276 | } |
277 | ||
ce88decf XG |
278 | static gfn_t get_mmio_spte_gfn(u64 spte) |
279 | { | |
daa07cbc | 280 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 281 | |
8a967d65 | 282 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
283 | & shadow_nonpresent_or_rsvd_mask; |
284 | ||
285 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
286 | } |
287 | ||
288 | static unsigned get_mmio_spte_access(u64 spte) | |
289 | { | |
4af77151 | 290 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
291 | } |
292 | ||
54bf36aa | 293 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 294 | { |
cae7ed3c | 295 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 296 | |
cae7ed3c SC |
297 | gen = kvm_vcpu_memslots(vcpu)->generation; |
298 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
299 | return false; | |
089504c0 | 300 | |
cae7ed3c | 301 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
302 | spte_gen = get_mmio_spte_generation(spte); |
303 | ||
304 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
305 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
306 | } |
307 | ||
cd313569 MG |
308 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
309 | struct x86_exception *exception) | |
310 | { | |
ec7771ab | 311 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 312 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
313 | exception->error_code |= PFERR_RSVD_MASK; |
314 | return UNMAPPED_GVA; | |
315 | } | |
316 | ||
cd313569 MG |
317 | return gpa; |
318 | } | |
319 | ||
6aa8b732 AK |
320 | static int is_cpuid_PSE36(void) |
321 | { | |
322 | return 1; | |
323 | } | |
324 | ||
73b1087e AK |
325 | static int is_nx(struct kvm_vcpu *vcpu) |
326 | { | |
f6801dff | 327 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
328 | } |
329 | ||
da928521 AK |
330 | static gfn_t pse36_gfn_delta(u32 gpte) |
331 | { | |
332 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
333 | ||
334 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
335 | } | |
336 | ||
603e0651 | 337 | #ifdef CONFIG_X86_64 |
d555c333 | 338 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 339 | { |
b19ee2ff | 340 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
341 | } |
342 | ||
603e0651 | 343 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 344 | { |
b19ee2ff | 345 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
346 | } |
347 | ||
348 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
349 | { | |
350 | return xchg(sptep, spte); | |
351 | } | |
c2a2ac2b XG |
352 | |
353 | static u64 __get_spte_lockless(u64 *sptep) | |
354 | { | |
6aa7de05 | 355 | return READ_ONCE(*sptep); |
c2a2ac2b | 356 | } |
a9221dd5 | 357 | #else |
603e0651 XG |
358 | union split_spte { |
359 | struct { | |
360 | u32 spte_low; | |
361 | u32 spte_high; | |
362 | }; | |
363 | u64 spte; | |
364 | }; | |
a9221dd5 | 365 | |
c2a2ac2b XG |
366 | static void count_spte_clear(u64 *sptep, u64 spte) |
367 | { | |
57354682 | 368 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
369 | |
370 | if (is_shadow_present_pte(spte)) | |
371 | return; | |
372 | ||
373 | /* Ensure the spte is completely set before we increase the count */ | |
374 | smp_wmb(); | |
375 | sp->clear_spte_count++; | |
376 | } | |
377 | ||
603e0651 XG |
378 | static void __set_spte(u64 *sptep, u64 spte) |
379 | { | |
380 | union split_spte *ssptep, sspte; | |
a9221dd5 | 381 | |
603e0651 XG |
382 | ssptep = (union split_spte *)sptep; |
383 | sspte = (union split_spte)spte; | |
384 | ||
385 | ssptep->spte_high = sspte.spte_high; | |
386 | ||
387 | /* | |
388 | * If we map the spte from nonpresent to present, We should store | |
389 | * the high bits firstly, then set present bit, so cpu can not | |
390 | * fetch this spte while we are setting the spte. | |
391 | */ | |
392 | smp_wmb(); | |
393 | ||
b19ee2ff | 394 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
395 | } |
396 | ||
603e0651 XG |
397 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
398 | { | |
399 | union split_spte *ssptep, sspte; | |
400 | ||
401 | ssptep = (union split_spte *)sptep; | |
402 | sspte = (union split_spte)spte; | |
403 | ||
b19ee2ff | 404 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
405 | |
406 | /* | |
407 | * If we map the spte from present to nonpresent, we should clear | |
408 | * present bit firstly to avoid vcpu fetch the old high bits. | |
409 | */ | |
410 | smp_wmb(); | |
411 | ||
412 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 413 | count_spte_clear(sptep, spte); |
603e0651 XG |
414 | } |
415 | ||
416 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
417 | { | |
418 | union split_spte *ssptep, sspte, orig; | |
419 | ||
420 | ssptep = (union split_spte *)sptep; | |
421 | sspte = (union split_spte)spte; | |
422 | ||
423 | /* xchg acts as a barrier before the setting of the high bits */ | |
424 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
425 | orig.spte_high = ssptep->spte_high; |
426 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 427 | count_spte_clear(sptep, spte); |
603e0651 XG |
428 | |
429 | return orig.spte; | |
430 | } | |
c2a2ac2b XG |
431 | |
432 | /* | |
433 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 434 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
435 | * |
436 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
437 | * coalesces them and we are running out of the MMU lock. Therefore | |
438 | * we need to protect against in-progress updates of the spte. | |
439 | * | |
440 | * Reading the spte while an update is in progress may get the old value | |
441 | * for the high part of the spte. The race is fine for a present->non-present | |
442 | * change (because the high part of the spte is ignored for non-present spte), | |
443 | * but for a present->present change we must reread the spte. | |
444 | * | |
445 | * All such changes are done in two steps (present->non-present and | |
446 | * non-present->present), hence it is enough to count the number of | |
447 | * present->non-present updates: if it changed while reading the spte, | |
448 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
449 | */ |
450 | static u64 __get_spte_lockless(u64 *sptep) | |
451 | { | |
57354682 | 452 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
453 | union split_spte spte, *orig = (union split_spte *)sptep; |
454 | int count; | |
455 | ||
456 | retry: | |
457 | count = sp->clear_spte_count; | |
458 | smp_rmb(); | |
459 | ||
460 | spte.spte_low = orig->spte_low; | |
461 | smp_rmb(); | |
462 | ||
463 | spte.spte_high = orig->spte_high; | |
464 | smp_rmb(); | |
465 | ||
466 | if (unlikely(spte.spte_low != orig->spte_low || | |
467 | count != sp->clear_spte_count)) | |
468 | goto retry; | |
469 | ||
470 | return spte.spte; | |
471 | } | |
603e0651 XG |
472 | #endif |
473 | ||
8672b721 XG |
474 | static bool spte_has_volatile_bits(u64 spte) |
475 | { | |
f160c7b7 JS |
476 | if (!is_shadow_present_pte(spte)) |
477 | return false; | |
478 | ||
c7ba5b48 | 479 | /* |
6a6256f9 | 480 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
481 | * out of mmu-lock, it can ensure dirty bit is not lost, |
482 | * also, it can help us to get a stable is_writable_pte() | |
483 | * to ensure tlb flush is not missed. | |
484 | */ | |
f160c7b7 JS |
485 | if (spte_can_locklessly_be_made_writable(spte) || |
486 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
487 | return true; |
488 | ||
ac8d57e5 | 489 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
490 | if ((spte & shadow_accessed_mask) == 0 || |
491 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
492 | return true; | |
493 | } | |
8672b721 | 494 | |
f160c7b7 | 495 | return false; |
8672b721 XG |
496 | } |
497 | ||
1df9f2dc XG |
498 | /* Rules for using mmu_spte_set: |
499 | * Set the sptep from nonpresent to present. | |
500 | * Note: the sptep being assigned *must* be either not present | |
501 | * or in a state where the hardware will not attempt to update | |
502 | * the spte. | |
503 | */ | |
504 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
505 | { | |
506 | WARN_ON(is_shadow_present_pte(*sptep)); | |
507 | __set_spte(sptep, new_spte); | |
508 | } | |
509 | ||
f39a058d JS |
510 | /* |
511 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
512 | * accessed/dirty status. | |
1df9f2dc | 513 | */ |
f39a058d | 514 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 515 | { |
c7ba5b48 | 516 | u64 old_spte = *sptep; |
4132779b | 517 | |
afd28fe1 | 518 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 519 | |
6e7d0354 XG |
520 | if (!is_shadow_present_pte(old_spte)) { |
521 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 522 | return old_spte; |
6e7d0354 | 523 | } |
4132779b | 524 | |
c7ba5b48 | 525 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 526 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 527 | else |
603e0651 | 528 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 529 | |
83ef6c81 JS |
530 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
531 | ||
f39a058d JS |
532 | return old_spte; |
533 | } | |
534 | ||
535 | /* Rules for using mmu_spte_update: | |
536 | * Update the state bits, it means the mapped pfn is not changed. | |
537 | * | |
538 | * Whenever we overwrite a writable spte with a read-only one we | |
539 | * should flush remote TLBs. Otherwise rmap_write_protect | |
540 | * will find a read-only spte, even though the writable spte | |
541 | * might be cached on a CPU's TLB, the return value indicates this | |
542 | * case. | |
543 | * | |
544 | * Returns true if the TLB needs to be flushed | |
545 | */ | |
546 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
547 | { | |
548 | bool flush = false; | |
549 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
550 | ||
551 | if (!is_shadow_present_pte(old_spte)) | |
552 | return false; | |
553 | ||
c7ba5b48 XG |
554 | /* |
555 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 556 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
557 | * spte_has_volatile_bits(). |
558 | */ | |
ea4114bc | 559 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 560 | !is_writable_pte(new_spte)) |
83ef6c81 | 561 | flush = true; |
4132779b | 562 | |
7e71a59b | 563 | /* |
83ef6c81 | 564 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
565 | * to guarantee consistency between TLB and page tables. |
566 | */ | |
7e71a59b | 567 | |
83ef6c81 JS |
568 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
569 | flush = true; | |
4132779b | 570 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
571 | } |
572 | ||
573 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
574 | flush = true; | |
4132779b | 575 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 576 | } |
6e7d0354 | 577 | |
83ef6c81 | 578 | return flush; |
b79b93f9 AK |
579 | } |
580 | ||
1df9f2dc XG |
581 | /* |
582 | * Rules for using mmu_spte_clear_track_bits: | |
583 | * It sets the sptep from present to nonpresent, and track the | |
584 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 585 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
586 | */ |
587 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
588 | { | |
ba049e93 | 589 | kvm_pfn_t pfn; |
1df9f2dc XG |
590 | u64 old_spte = *sptep; |
591 | ||
592 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 593 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 594 | else |
603e0651 | 595 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 596 | |
afd28fe1 | 597 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
598 | return 0; |
599 | ||
600 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
601 | |
602 | /* | |
603 | * KVM does not hold the refcount of the page used by | |
604 | * kvm mmu, before reclaiming the page, we should | |
605 | * unmap it from mmu first. | |
606 | */ | |
bf4bea8e | 607 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 608 | |
83ef6c81 | 609 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 610 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
611 | |
612 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 613 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 614 | |
1df9f2dc XG |
615 | return 1; |
616 | } | |
617 | ||
618 | /* | |
619 | * Rules for using mmu_spte_clear_no_track: | |
620 | * Directly clear spte without caring the state bits of sptep, | |
621 | * it is used to set the upper level spte. | |
622 | */ | |
623 | static void mmu_spte_clear_no_track(u64 *sptep) | |
624 | { | |
603e0651 | 625 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
626 | } |
627 | ||
c2a2ac2b XG |
628 | static u64 mmu_spte_get_lockless(u64 *sptep) |
629 | { | |
630 | return __get_spte_lockless(sptep); | |
631 | } | |
632 | ||
d3e328f2 JS |
633 | /* Restore an acc-track PTE back to a regular PTE */ |
634 | static u64 restore_acc_track_spte(u64 spte) | |
635 | { | |
636 | u64 new_spte = spte; | |
8a967d65 PB |
637 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
638 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 639 | |
ac8d57e5 | 640 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
641 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
642 | ||
643 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
644 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
645 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
646 | new_spte |= saved_bits; |
647 | ||
648 | return new_spte; | |
649 | } | |
650 | ||
f160c7b7 JS |
651 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
652 | static bool mmu_spte_age(u64 *sptep) | |
653 | { | |
654 | u64 spte = mmu_spte_get_lockless(sptep); | |
655 | ||
656 | if (!is_accessed_spte(spte)) | |
657 | return false; | |
658 | ||
ac8d57e5 | 659 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
660 | clear_bit((ffs(shadow_accessed_mask) - 1), |
661 | (unsigned long *)sptep); | |
662 | } else { | |
663 | /* | |
664 | * Capture the dirty status of the page, so that it doesn't get | |
665 | * lost when the SPTE is marked for access tracking. | |
666 | */ | |
667 | if (is_writable_pte(spte)) | |
668 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
669 | ||
670 | spte = mark_spte_for_access_track(spte); | |
671 | mmu_spte_update_no_track(sptep, spte); | |
672 | } | |
673 | ||
674 | return true; | |
675 | } | |
676 | ||
c2a2ac2b XG |
677 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
678 | { | |
c142786c AK |
679 | /* |
680 | * Prevent page table teardown by making any free-er wait during | |
681 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
682 | */ | |
683 | local_irq_disable(); | |
36ca7e0a | 684 | |
c142786c AK |
685 | /* |
686 | * Make sure a following spte read is not reordered ahead of the write | |
687 | * to vcpu->mode. | |
688 | */ | |
36ca7e0a | 689 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
690 | } |
691 | ||
692 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
693 | { | |
c142786c AK |
694 | /* |
695 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 696 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
697 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
698 | */ | |
36ca7e0a | 699 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 700 | local_irq_enable(); |
c2a2ac2b XG |
701 | } |
702 | ||
378f5cd6 | 703 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 704 | { |
e2dec939 AK |
705 | int r; |
706 | ||
531281ad | 707 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
708 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
709 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 710 | if (r) |
284aa868 | 711 | return r; |
94ce87ef SC |
712 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
713 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 714 | if (r) |
171a90d7 | 715 | return r; |
378f5cd6 | 716 | if (maybe_indirect) { |
94ce87ef SC |
717 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
718 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
719 | if (r) |
720 | return r; | |
721 | } | |
94ce87ef SC |
722 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
723 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
724 | } |
725 | ||
726 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
727 | { | |
94ce87ef SC |
728 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
729 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
730 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
731 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
732 | } |
733 | ||
53c07b18 | 734 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 735 | { |
94ce87ef | 736 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
737 | } |
738 | ||
53c07b18 | 739 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 740 | { |
53c07b18 | 741 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
742 | } |
743 | ||
2032a93d LJ |
744 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
745 | { | |
746 | if (!sp->role.direct) | |
747 | return sp->gfns[index]; | |
748 | ||
749 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
750 | } | |
751 | ||
752 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
753 | { | |
e9f2a760 | 754 | if (!sp->role.direct) { |
2032a93d | 755 | sp->gfns[index] = gfn; |
e9f2a760 PB |
756 | return; |
757 | } | |
758 | ||
759 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
760 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
761 | "(expected %llx, got %llx)\n", | |
762 | sp->gfn, | |
763 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
764 | } |
765 | ||
05da4558 | 766 | /* |
d4dbf470 TY |
767 | * Return the pointer to the large page information for a given gfn, |
768 | * handling slots that are not large page aligned. | |
05da4558 | 769 | */ |
d4dbf470 | 770 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
8ca6f063 | 771 | const struct kvm_memory_slot *slot, int level) |
05da4558 MT |
772 | { |
773 | unsigned long idx; | |
774 | ||
fb03cb6f | 775 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 776 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
777 | } |
778 | ||
547ffaed XG |
779 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
780 | gfn_t gfn, int count) | |
781 | { | |
782 | struct kvm_lpage_info *linfo; | |
783 | int i; | |
784 | ||
3bae0459 | 785 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
786 | linfo = lpage_info_slot(gfn, slot, i); |
787 | linfo->disallow_lpage += count; | |
788 | WARN_ON(linfo->disallow_lpage < 0); | |
789 | } | |
790 | } | |
791 | ||
792 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
793 | { | |
794 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
795 | } | |
796 | ||
797 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
798 | { | |
799 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
800 | } | |
801 | ||
3ed1a478 | 802 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 803 | { |
699023e2 | 804 | struct kvm_memslots *slots; |
d25797b2 | 805 | struct kvm_memory_slot *slot; |
3ed1a478 | 806 | gfn_t gfn; |
05da4558 | 807 | |
56ca57f9 | 808 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 809 | gfn = sp->gfn; |
699023e2 PB |
810 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
811 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
812 | |
813 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 814 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
815 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
816 | KVM_PAGE_TRACK_WRITE); | |
817 | ||
547ffaed | 818 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
819 | } |
820 | ||
29cf0f50 | 821 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
822 | { |
823 | if (sp->lpage_disallowed) | |
824 | return; | |
825 | ||
826 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
827 | list_add_tail(&sp->lpage_disallowed_link, |
828 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
829 | sp->lpage_disallowed = true; |
830 | } | |
831 | ||
3ed1a478 | 832 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 833 | { |
699023e2 | 834 | struct kvm_memslots *slots; |
d25797b2 | 835 | struct kvm_memory_slot *slot; |
3ed1a478 | 836 | gfn_t gfn; |
05da4558 | 837 | |
56ca57f9 | 838 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 839 | gfn = sp->gfn; |
699023e2 PB |
840 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
841 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 842 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
843 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
844 | KVM_PAGE_TRACK_WRITE); | |
845 | ||
547ffaed | 846 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
847 | } |
848 | ||
29cf0f50 | 849 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
850 | { |
851 | --kvm->stat.nx_lpage_splits; | |
852 | sp->lpage_disallowed = false; | |
1aa9b957 | 853 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
854 | } |
855 | ||
5d163b1c XG |
856 | static struct kvm_memory_slot * |
857 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
858 | bool no_dirty_log) | |
05da4558 MT |
859 | { |
860 | struct kvm_memory_slot *slot; | |
5d163b1c | 861 | |
54bf36aa | 862 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
863 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
864 | return NULL; | |
044c59c4 | 865 | if (no_dirty_log && kvm_slot_dirty_track_enabled(slot)) |
91b0d268 | 866 | return NULL; |
5d163b1c XG |
867 | |
868 | return slot; | |
869 | } | |
870 | ||
290fc38d | 871 | /* |
018aabb5 | 872 | * About rmap_head encoding: |
cd4a4e53 | 873 | * |
018aabb5 TY |
874 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
875 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 876 | * pte_list_desc containing more mappings. |
018aabb5 TY |
877 | */ |
878 | ||
879 | /* | |
880 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 881 | */ |
53c07b18 | 882 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 883 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 884 | { |
53c07b18 | 885 | struct pte_list_desc *desc; |
53a27b39 | 886 | int i, count = 0; |
cd4a4e53 | 887 | |
018aabb5 | 888 | if (!rmap_head->val) { |
805a0f83 | 889 | rmap_printk("%p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
890 | rmap_head->val = (unsigned long)spte; |
891 | } else if (!(rmap_head->val & 1)) { | |
805a0f83 | 892 | rmap_printk("%p %llx 1->many\n", spte, *spte); |
53c07b18 | 893 | desc = mmu_alloc_pte_list_desc(vcpu); |
018aabb5 | 894 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 895 | desc->sptes[1] = spte; |
018aabb5 | 896 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 897 | ++count; |
cd4a4e53 | 898 | } else { |
805a0f83 | 899 | rmap_printk("%p %llx many->many\n", spte, *spte); |
018aabb5 | 900 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
c6c4f961 | 901 | while (desc->sptes[PTE_LIST_EXT-1]) { |
53c07b18 | 902 | count += PTE_LIST_EXT; |
c6c4f961 LR |
903 | |
904 | if (!desc->more) { | |
905 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
906 | desc = desc->more; | |
907 | break; | |
908 | } | |
cd4a4e53 AK |
909 | desc = desc->more; |
910 | } | |
d555c333 | 911 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 912 | ++count; |
d555c333 | 913 | desc->sptes[i] = spte; |
cd4a4e53 | 914 | } |
53a27b39 | 915 | return count; |
cd4a4e53 AK |
916 | } |
917 | ||
53c07b18 | 918 | static void |
018aabb5 TY |
919 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
920 | struct pte_list_desc *desc, int i, | |
921 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
922 | { |
923 | int j; | |
924 | ||
53c07b18 | 925 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 926 | ; |
d555c333 AK |
927 | desc->sptes[i] = desc->sptes[j]; |
928 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
929 | if (j != 0) |
930 | return; | |
931 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 932 | rmap_head->val = 0; |
cd4a4e53 AK |
933 | else |
934 | if (prev_desc) | |
935 | prev_desc->more = desc->more; | |
936 | else | |
018aabb5 | 937 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 938 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
939 | } |
940 | ||
8daf3462 | 941 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 942 | { |
53c07b18 XG |
943 | struct pte_list_desc *desc; |
944 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
945 | int i; |
946 | ||
018aabb5 | 947 | if (!rmap_head->val) { |
8daf3462 | 948 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 949 | BUG(); |
018aabb5 | 950 | } else if (!(rmap_head->val & 1)) { |
805a0f83 | 951 | rmap_printk("%p 1->0\n", spte); |
018aabb5 | 952 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 953 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
954 | BUG(); |
955 | } | |
018aabb5 | 956 | rmap_head->val = 0; |
cd4a4e53 | 957 | } else { |
805a0f83 | 958 | rmap_printk("%p many->many\n", spte); |
018aabb5 | 959 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
960 | prev_desc = NULL; |
961 | while (desc) { | |
018aabb5 | 962 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 963 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
964 | pte_list_desc_remove_entry(rmap_head, |
965 | desc, i, prev_desc); | |
cd4a4e53 AK |
966 | return; |
967 | } | |
018aabb5 | 968 | } |
cd4a4e53 AK |
969 | prev_desc = desc; |
970 | desc = desc->more; | |
971 | } | |
8daf3462 | 972 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
973 | BUG(); |
974 | } | |
975 | } | |
976 | ||
e7912386 WY |
977 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
978 | { | |
979 | mmu_spte_clear_track_bits(sptep); | |
980 | __pte_list_remove(sptep, rmap_head); | |
981 | } | |
982 | ||
018aabb5 TY |
983 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
984 | struct kvm_memory_slot *slot) | |
53c07b18 | 985 | { |
77d11309 | 986 | unsigned long idx; |
53c07b18 | 987 | |
77d11309 | 988 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 989 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
990 | } |
991 | ||
018aabb5 TY |
992 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
993 | struct kvm_mmu_page *sp) | |
9b9b1492 | 994 | { |
699023e2 | 995 | struct kvm_memslots *slots; |
9b9b1492 TY |
996 | struct kvm_memory_slot *slot; |
997 | ||
699023e2 PB |
998 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
999 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1000 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1001 | } |
1002 | ||
f759e2b4 XG |
1003 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1004 | { | |
356ec69a | 1005 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 1006 | |
356ec69a | 1007 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 1008 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
1009 | } |
1010 | ||
53c07b18 XG |
1011 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1012 | { | |
1013 | struct kvm_mmu_page *sp; | |
018aabb5 | 1014 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1015 | |
57354682 | 1016 | sp = sptep_to_sp(spte); |
53c07b18 | 1017 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
1018 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1019 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1020 | } |
1021 | ||
53c07b18 XG |
1022 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1023 | { | |
1024 | struct kvm_mmu_page *sp; | |
1025 | gfn_t gfn; | |
018aabb5 | 1026 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1027 | |
57354682 | 1028 | sp = sptep_to_sp(spte); |
53c07b18 | 1029 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 1030 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1031 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1032 | } |
1033 | ||
1e3f42f0 TY |
1034 | /* |
1035 | * Used by the following functions to iterate through the sptes linked by a | |
1036 | * rmap. All fields are private and not assumed to be used outside. | |
1037 | */ | |
1038 | struct rmap_iterator { | |
1039 | /* private fields */ | |
1040 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1041 | int pos; /* index of the sptep */ | |
1042 | }; | |
1043 | ||
1044 | /* | |
1045 | * Iteration must be started by this function. This should also be used after | |
1046 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1047 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1048 | * |
1049 | * Returns sptep if found, NULL otherwise. | |
1050 | */ | |
018aabb5 TY |
1051 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1052 | struct rmap_iterator *iter) | |
1e3f42f0 | 1053 | { |
77fbbbd2 TY |
1054 | u64 *sptep; |
1055 | ||
018aabb5 | 1056 | if (!rmap_head->val) |
1e3f42f0 TY |
1057 | return NULL; |
1058 | ||
018aabb5 | 1059 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1060 | iter->desc = NULL; |
77fbbbd2 TY |
1061 | sptep = (u64 *)rmap_head->val; |
1062 | goto out; | |
1e3f42f0 TY |
1063 | } |
1064 | ||
018aabb5 | 1065 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1066 | iter->pos = 0; |
77fbbbd2 TY |
1067 | sptep = iter->desc->sptes[iter->pos]; |
1068 | out: | |
1069 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1070 | return sptep; | |
1e3f42f0 TY |
1071 | } |
1072 | ||
1073 | /* | |
1074 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1075 | * | |
1076 | * Returns sptep if found, NULL otherwise. | |
1077 | */ | |
1078 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1079 | { | |
77fbbbd2 TY |
1080 | u64 *sptep; |
1081 | ||
1e3f42f0 TY |
1082 | if (iter->desc) { |
1083 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1084 | ++iter->pos; |
1085 | sptep = iter->desc->sptes[iter->pos]; | |
1086 | if (sptep) | |
77fbbbd2 | 1087 | goto out; |
1e3f42f0 TY |
1088 | } |
1089 | ||
1090 | iter->desc = iter->desc->more; | |
1091 | ||
1092 | if (iter->desc) { | |
1093 | iter->pos = 0; | |
1094 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1095 | sptep = iter->desc->sptes[iter->pos]; |
1096 | goto out; | |
1e3f42f0 TY |
1097 | } |
1098 | } | |
1099 | ||
1100 | return NULL; | |
77fbbbd2 TY |
1101 | out: |
1102 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1103 | return sptep; | |
1e3f42f0 TY |
1104 | } |
1105 | ||
018aabb5 TY |
1106 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1107 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1108 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1109 | |
c3707958 | 1110 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1111 | { |
1df9f2dc | 1112 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1113 | rmap_remove(kvm, sptep); |
be38d276 AK |
1114 | } |
1115 | ||
8e22f955 XG |
1116 | |
1117 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1118 | { | |
1119 | if (is_large_pte(*sptep)) { | |
57354682 | 1120 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1121 | drop_spte(kvm, sptep); |
1122 | --kvm->stat.lpages; | |
1123 | return true; | |
1124 | } | |
1125 | ||
1126 | return false; | |
1127 | } | |
1128 | ||
1129 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1130 | { | |
c3134ce2 | 1131 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1132 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1133 | |
1134 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1135 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1136 | } | |
8e22f955 XG |
1137 | } |
1138 | ||
1139 | /* | |
49fde340 | 1140 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1141 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1142 | * |
b4619660 | 1143 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1144 | * protection: |
1145 | * - for dirty logging, the spte can be set to writable at anytime if | |
1146 | * its dirty bitmap is properly set. | |
1147 | * - for spte protection, the spte can be writable only after unsync-ing | |
1148 | * shadow page. | |
8e22f955 | 1149 | * |
c126d94f | 1150 | * Return true if tlb need be flushed. |
8e22f955 | 1151 | */ |
c4f138b4 | 1152 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1153 | { |
1154 | u64 spte = *sptep; | |
1155 | ||
49fde340 | 1156 | if (!is_writable_pte(spte) && |
ea4114bc | 1157 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1158 | return false; |
1159 | ||
805a0f83 | 1160 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
d13bc5b5 | 1161 | |
49fde340 | 1162 | if (pt_protect) |
5fc3424f | 1163 | spte &= ~shadow_mmu_writable_mask; |
d13bc5b5 | 1164 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1165 | |
c126d94f | 1166 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1167 | } |
1168 | ||
018aabb5 TY |
1169 | static bool __rmap_write_protect(struct kvm *kvm, |
1170 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1171 | bool pt_protect) |
98348e95 | 1172 | { |
1e3f42f0 TY |
1173 | u64 *sptep; |
1174 | struct rmap_iterator iter; | |
d13bc5b5 | 1175 | bool flush = false; |
374cbac0 | 1176 | |
018aabb5 | 1177 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1178 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1179 | |
d13bc5b5 | 1180 | return flush; |
a0ed4607 TY |
1181 | } |
1182 | ||
c4f138b4 | 1183 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1184 | { |
1185 | u64 spte = *sptep; | |
1186 | ||
805a0f83 | 1187 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
f4b4b180 | 1188 | |
1f4e5fc8 | 1189 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1190 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1191 | return mmu_spte_update(sptep, spte); |
1192 | } | |
1193 | ||
1f4e5fc8 | 1194 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1195 | { |
1196 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1197 | (unsigned long *)sptep); | |
1f4e5fc8 | 1198 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1199 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1200 | ||
1201 | return was_writable; | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1206 | * - D bit on ad-enabled SPTEs, and | |
1207 | * - W bit on ad-disabled SPTEs. | |
1208 | * Returns true iff any D or W bits were cleared. | |
1209 | */ | |
0a234f5d SC |
1210 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1211 | struct kvm_memory_slot *slot) | |
f4b4b180 KH |
1212 | { |
1213 | u64 *sptep; | |
1214 | struct rmap_iterator iter; | |
1215 | bool flush = false; | |
1216 | ||
018aabb5 | 1217 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1218 | if (spte_ad_need_write_protect(*sptep)) |
1219 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1220 | else |
1f4e5fc8 | 1221 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1222 | |
1223 | return flush; | |
1224 | } | |
1225 | ||
5dc99b23 | 1226 | /** |
3b0f1d01 | 1227 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1228 | * @kvm: kvm instance |
1229 | * @slot: slot to protect | |
1230 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1231 | * @mask: indicates which pages we should protect | |
1232 | * | |
89212919 | 1233 | * Used when we do not need to care about huge page mappings. |
5dc99b23 | 1234 | */ |
3b0f1d01 | 1235 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1236 | struct kvm_memory_slot *slot, |
1237 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1238 | { |
018aabb5 | 1239 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1240 | |
897218ff | 1241 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1242 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1243 | slot->base_gfn + gfn_offset, mask, true); | |
e2209710 BG |
1244 | |
1245 | if (!kvm_memslots_have_rmaps(kvm)) | |
1246 | return; | |
1247 | ||
5dc99b23 | 1248 | while (mask) { |
018aabb5 | 1249 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1250 | PG_LEVEL_4K, slot); |
018aabb5 | 1251 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1252 | |
5dc99b23 TY |
1253 | /* clear the first set bit */ |
1254 | mask &= mask - 1; | |
1255 | } | |
374cbac0 AK |
1256 | } |
1257 | ||
f4b4b180 | 1258 | /** |
ac8d57e5 PF |
1259 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1260 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1261 | * @kvm: kvm instance |
1262 | * @slot: slot to clear D-bit | |
1263 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1264 | * @mask: indicates which pages we should clear D-bit | |
1265 | * | |
1266 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1267 | */ | |
a018eba5 SC |
1268 | static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, |
1269 | struct kvm_memory_slot *slot, | |
1270 | gfn_t gfn_offset, unsigned long mask) | |
f4b4b180 | 1271 | { |
018aabb5 | 1272 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1273 | |
897218ff | 1274 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1275 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1276 | slot->base_gfn + gfn_offset, mask, false); | |
e2209710 BG |
1277 | |
1278 | if (!kvm_memslots_have_rmaps(kvm)) | |
1279 | return; | |
1280 | ||
f4b4b180 | 1281 | while (mask) { |
018aabb5 | 1282 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1283 | PG_LEVEL_4K, slot); |
0a234f5d | 1284 | __rmap_clear_dirty(kvm, rmap_head, slot); |
f4b4b180 KH |
1285 | |
1286 | /* clear the first set bit */ | |
1287 | mask &= mask - 1; | |
1288 | } | |
1289 | } | |
f4b4b180 | 1290 | |
3b0f1d01 KH |
1291 | /** |
1292 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1293 | * PT level pages. | |
1294 | * | |
1295 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1296 | * enable dirty logging for them. | |
1297 | * | |
89212919 KZ |
1298 | * We need to care about huge page mappings: e.g. during dirty logging we may |
1299 | * have such mappings. | |
3b0f1d01 KH |
1300 | */ |
1301 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1302 | struct kvm_memory_slot *slot, | |
1303 | gfn_t gfn_offset, unsigned long mask) | |
1304 | { | |
89212919 KZ |
1305 | /* |
1306 | * Huge pages are NOT write protected when we start dirty logging in | |
1307 | * initially-all-set mode; must write protect them here so that they | |
1308 | * are split to 4K on the first write. | |
1309 | * | |
1310 | * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn | |
1311 | * of memslot has no such restriction, so the range can cross two large | |
1312 | * pages. | |
1313 | */ | |
1314 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
1315 | gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask); | |
1316 | gfn_t end = slot->base_gfn + gfn_offset + __fls(mask); | |
1317 | ||
1318 | kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M); | |
1319 | ||
1320 | /* Cross two large pages? */ | |
1321 | if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) != | |
1322 | ALIGN(end << PAGE_SHIFT, PMD_SIZE)) | |
1323 | kvm_mmu_slot_gfn_write_protect(kvm, slot, end, | |
1324 | PG_LEVEL_2M); | |
1325 | } | |
1326 | ||
1327 | /* Now handle 4K PTEs. */ | |
a018eba5 SC |
1328 | if (kvm_x86_ops.cpu_dirty_log_size) |
1329 | kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask); | |
88178fd4 KH |
1330 | else |
1331 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1332 | } |
1333 | ||
fb04a1ed PX |
1334 | int kvm_cpu_dirty_log_size(void) |
1335 | { | |
6dd03800 | 1336 | return kvm_x86_ops.cpu_dirty_log_size; |
fb04a1ed PX |
1337 | } |
1338 | ||
aeecee2e | 1339 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
3ad93562 KZ |
1340 | struct kvm_memory_slot *slot, u64 gfn, |
1341 | int min_level) | |
95d4c16c | 1342 | { |
018aabb5 | 1343 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1344 | int i; |
2f84569f | 1345 | bool write_protected = false; |
95d4c16c | 1346 | |
e2209710 BG |
1347 | if (kvm_memslots_have_rmaps(kvm)) { |
1348 | for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { | |
1349 | rmap_head = __gfn_to_rmap(gfn, i, slot); | |
1350 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); | |
1351 | } | |
5dc99b23 TY |
1352 | } |
1353 | ||
897218ff | 1354 | if (is_tdp_mmu_enabled(kvm)) |
46044f72 | 1355 | write_protected |= |
3ad93562 | 1356 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level); |
46044f72 | 1357 | |
5dc99b23 | 1358 | return write_protected; |
95d4c16c TY |
1359 | } |
1360 | ||
aeecee2e XG |
1361 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1362 | { | |
1363 | struct kvm_memory_slot *slot; | |
1364 | ||
1365 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
3ad93562 | 1366 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K); |
aeecee2e XG |
1367 | } |
1368 | ||
0a234f5d SC |
1369 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1370 | struct kvm_memory_slot *slot) | |
e930bffe | 1371 | { |
1e3f42f0 TY |
1372 | u64 *sptep; |
1373 | struct rmap_iterator iter; | |
6a49f85c | 1374 | bool flush = false; |
e930bffe | 1375 | |
018aabb5 | 1376 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
805a0f83 | 1377 | rmap_printk("spte %p %llx.\n", sptep, *sptep); |
1e3f42f0 | 1378 | |
e7912386 | 1379 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1380 | flush = true; |
e930bffe | 1381 | } |
1e3f42f0 | 1382 | |
6a49f85c XG |
1383 | return flush; |
1384 | } | |
1385 | ||
3039bcc7 SC |
1386 | static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1387 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1388 | pte_t unused) | |
6a49f85c | 1389 | { |
0a234f5d | 1390 | return kvm_zap_rmapp(kvm, rmap_head, slot); |
e930bffe AA |
1391 | } |
1392 | ||
3039bcc7 SC |
1393 | static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1394 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1395 | pte_t pte) | |
3da0dd43 | 1396 | { |
1e3f42f0 TY |
1397 | u64 *sptep; |
1398 | struct rmap_iterator iter; | |
3da0dd43 | 1399 | int need_flush = 0; |
1e3f42f0 | 1400 | u64 new_spte; |
ba049e93 | 1401 | kvm_pfn_t new_pfn; |
3da0dd43 | 1402 | |
3039bcc7 SC |
1403 | WARN_ON(pte_huge(pte)); |
1404 | new_pfn = pte_pfn(pte); | |
1e3f42f0 | 1405 | |
0d536790 | 1406 | restart: |
018aabb5 | 1407 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
805a0f83 | 1408 | rmap_printk("spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1409 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1410 | |
3da0dd43 | 1411 | need_flush = 1; |
1e3f42f0 | 1412 | |
3039bcc7 | 1413 | if (pte_write(pte)) { |
e7912386 | 1414 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1415 | goto restart; |
3da0dd43 | 1416 | } else { |
cb3eedab PB |
1417 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1418 | *sptep, new_pfn); | |
1e3f42f0 TY |
1419 | |
1420 | mmu_spte_clear_track_bits(sptep); | |
1421 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1422 | } |
1423 | } | |
1e3f42f0 | 1424 | |
3cc5ea94 LT |
1425 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1426 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1427 | return 0; | |
1428 | } | |
1429 | ||
0cf853c5 | 1430 | return need_flush; |
3da0dd43 IE |
1431 | } |
1432 | ||
6ce1f4e2 XG |
1433 | struct slot_rmap_walk_iterator { |
1434 | /* input fields. */ | |
1435 | struct kvm_memory_slot *slot; | |
1436 | gfn_t start_gfn; | |
1437 | gfn_t end_gfn; | |
1438 | int start_level; | |
1439 | int end_level; | |
1440 | ||
1441 | /* output fields. */ | |
1442 | gfn_t gfn; | |
018aabb5 | 1443 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1444 | int level; |
1445 | ||
1446 | /* private field. */ | |
018aabb5 | 1447 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1448 | }; |
1449 | ||
1450 | static void | |
1451 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1452 | { | |
1453 | iterator->level = level; | |
1454 | iterator->gfn = iterator->start_gfn; | |
1455 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1456 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1457 | iterator->slot); | |
1458 | } | |
1459 | ||
1460 | static void | |
1461 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1462 | struct kvm_memory_slot *slot, int start_level, | |
1463 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1464 | { | |
1465 | iterator->slot = slot; | |
1466 | iterator->start_level = start_level; | |
1467 | iterator->end_level = end_level; | |
1468 | iterator->start_gfn = start_gfn; | |
1469 | iterator->end_gfn = end_gfn; | |
1470 | ||
1471 | rmap_walk_init_level(iterator, iterator->start_level); | |
1472 | } | |
1473 | ||
1474 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1475 | { | |
1476 | return !!iterator->rmap; | |
1477 | } | |
1478 | ||
1479 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1480 | { | |
1481 | if (++iterator->rmap <= iterator->end_rmap) { | |
1482 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1483 | return; | |
1484 | } | |
1485 | ||
1486 | if (++iterator->level > iterator->end_level) { | |
1487 | iterator->rmap = NULL; | |
1488 | return; | |
1489 | } | |
1490 | ||
1491 | rmap_walk_init_level(iterator, iterator->level); | |
1492 | } | |
1493 | ||
1494 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1495 | _start_gfn, _end_gfn, _iter_) \ | |
1496 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1497 | _end_level_, _start_gfn, _end_gfn); \ | |
1498 | slot_rmap_walk_okay(_iter_); \ | |
1499 | slot_rmap_walk_next(_iter_)) | |
1500 | ||
3039bcc7 SC |
1501 | typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1502 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1503 | int level, pte_t pte); | |
c1b91493 | 1504 | |
3039bcc7 SC |
1505 | static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm, |
1506 | struct kvm_gfn_range *range, | |
1507 | rmap_handler_t handler) | |
e930bffe | 1508 | { |
6ce1f4e2 | 1509 | struct slot_rmap_walk_iterator iterator; |
3039bcc7 | 1510 | bool ret = false; |
e930bffe | 1511 | |
3039bcc7 SC |
1512 | for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL, |
1513 | range->start, range->end - 1, &iterator) | |
1514 | ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn, | |
1515 | iterator.level, range->pte); | |
e930bffe | 1516 | |
f395302e | 1517 | return ret; |
e930bffe AA |
1518 | } |
1519 | ||
3039bcc7 | 1520 | bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) |
84504ef3 | 1521 | { |
e2209710 | 1522 | bool flush = false; |
063afacd | 1523 | |
e2209710 BG |
1524 | if (kvm_memslots_have_rmaps(kvm)) |
1525 | flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp); | |
063afacd | 1526 | |
897218ff | 1527 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1528 | flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush); |
063afacd | 1529 | |
3039bcc7 | 1530 | return flush; |
b3ae2096 TY |
1531 | } |
1532 | ||
3039bcc7 | 1533 | bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
3da0dd43 | 1534 | { |
e2209710 | 1535 | bool flush = false; |
1d8dd6b3 | 1536 | |
e2209710 BG |
1537 | if (kvm_memslots_have_rmaps(kvm)) |
1538 | flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp); | |
1d8dd6b3 | 1539 | |
897218ff | 1540 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1541 | flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range); |
1d8dd6b3 | 1542 | |
3039bcc7 | 1543 | return flush; |
e930bffe AA |
1544 | } |
1545 | ||
3039bcc7 SC |
1546 | static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1547 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1548 | pte_t unused) | |
e930bffe | 1549 | { |
1e3f42f0 | 1550 | u64 *sptep; |
3f649ab7 | 1551 | struct rmap_iterator iter; |
e930bffe AA |
1552 | int young = 0; |
1553 | ||
f160c7b7 JS |
1554 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1555 | young |= mmu_spte_age(sptep); | |
0d536790 | 1556 | |
e930bffe AA |
1557 | return young; |
1558 | } | |
1559 | ||
3039bcc7 SC |
1560 | static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1561 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1562 | int level, pte_t unused) | |
8ee53820 | 1563 | { |
1e3f42f0 TY |
1564 | u64 *sptep; |
1565 | struct rmap_iterator iter; | |
8ee53820 | 1566 | |
83ef6c81 JS |
1567 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1568 | if (is_accessed_spte(*sptep)) | |
1569 | return 1; | |
83ef6c81 | 1570 | return 0; |
8ee53820 AA |
1571 | } |
1572 | ||
53a27b39 MT |
1573 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1574 | ||
852e3c19 | 1575 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1576 | { |
018aabb5 | 1577 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1578 | struct kvm_mmu_page *sp; |
1579 | ||
57354682 | 1580 | sp = sptep_to_sp(spte); |
53a27b39 | 1581 | |
018aabb5 | 1582 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1583 | |
3039bcc7 | 1584 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0)); |
c3134ce2 LT |
1585 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1586 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1587 | } |
1588 | ||
3039bcc7 | 1589 | bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
e930bffe | 1590 | { |
e2209710 | 1591 | bool young = false; |
3039bcc7 | 1592 | |
e2209710 BG |
1593 | if (kvm_memslots_have_rmaps(kvm)) |
1594 | young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp); | |
f8e14497 | 1595 | |
897218ff | 1596 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1597 | young |= kvm_tdp_mmu_age_gfn_range(kvm, range); |
f8e14497 BG |
1598 | |
1599 | return young; | |
e930bffe AA |
1600 | } |
1601 | ||
3039bcc7 | 1602 | bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
8ee53820 | 1603 | { |
e2209710 | 1604 | bool young = false; |
3039bcc7 | 1605 | |
e2209710 BG |
1606 | if (kvm_memslots_have_rmaps(kvm)) |
1607 | young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp); | |
f8e14497 | 1608 | |
897218ff | 1609 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1610 | young |= kvm_tdp_mmu_test_age_gfn(kvm, range); |
f8e14497 BG |
1611 | |
1612 | return young; | |
8ee53820 AA |
1613 | } |
1614 | ||
d6c69ee9 | 1615 | #ifdef MMU_DEBUG |
47ad8e68 | 1616 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1617 | { |
139bdb2d AK |
1618 | u64 *pos; |
1619 | u64 *end; | |
1620 | ||
47ad8e68 | 1621 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1622 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1623 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1624 | pos, *pos); |
6aa8b732 | 1625 | return 0; |
139bdb2d | 1626 | } |
6aa8b732 AK |
1627 | return 1; |
1628 | } | |
d6c69ee9 | 1629 | #endif |
6aa8b732 | 1630 | |
45221ab6 DH |
1631 | /* |
1632 | * This value is the sum of all of the kvm instances's | |
1633 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1634 | * aggregate version in order to make the slab shrinker | |
1635 | * faster | |
1636 | */ | |
bc8a3d89 | 1637 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1638 | { |
1639 | kvm->arch.n_used_mmu_pages += nr; | |
1640 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1641 | } | |
1642 | ||
834be0d8 | 1643 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1644 | { |
fa4a2c08 | 1645 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1646 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1647 | list_del(&sp->link); |
1648 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1649 | if (!sp->role.direct) |
1650 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1651 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1652 | } |
1653 | ||
cea0f0e7 AK |
1654 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1655 | { | |
114df303 | 1656 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1657 | } |
1658 | ||
714b93da | 1659 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1660 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1661 | { |
cea0f0e7 AK |
1662 | if (!parent_pte) |
1663 | return; | |
cea0f0e7 | 1664 | |
67052b35 | 1665 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1666 | } |
1667 | ||
4db35314 | 1668 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1669 | u64 *parent_pte) |
1670 | { | |
8daf3462 | 1671 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1672 | } |
1673 | ||
bcdd9a93 XG |
1674 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1675 | u64 *parent_pte) | |
1676 | { | |
1677 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1678 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1679 | } |
1680 | ||
47005792 | 1681 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1682 | { |
67052b35 | 1683 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1684 | |
94ce87ef SC |
1685 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1686 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1687 | if (!direct) |
94ce87ef | 1688 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1689 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1690 | |
1691 | /* | |
1692 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1693 | * depends on valid pages being added to the head of the list. See | |
1694 | * comments in kvm_zap_obsolete_pages(). | |
1695 | */ | |
ca333add | 1696 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1697 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1698 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1699 | return sp; | |
ad8cfbe3 MT |
1700 | } |
1701 | ||
67052b35 | 1702 | static void mark_unsync(u64 *spte); |
1047df1f | 1703 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1704 | { |
74c4e63a TY |
1705 | u64 *sptep; |
1706 | struct rmap_iterator iter; | |
1707 | ||
1708 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1709 | mark_unsync(sptep); | |
1710 | } | |
0074ff63 MT |
1711 | } |
1712 | ||
67052b35 | 1713 | static void mark_unsync(u64 *spte) |
0074ff63 | 1714 | { |
67052b35 | 1715 | struct kvm_mmu_page *sp; |
1047df1f | 1716 | unsigned int index; |
0074ff63 | 1717 | |
57354682 | 1718 | sp = sptep_to_sp(spte); |
1047df1f XG |
1719 | index = spte - sp->spt; |
1720 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1721 | return; |
1047df1f | 1722 | if (sp->unsync_children++) |
0074ff63 | 1723 | return; |
1047df1f | 1724 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1725 | } |
1726 | ||
e8bc217a | 1727 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1728 | struct kvm_mmu_page *sp) |
e8bc217a | 1729 | { |
1f50f1b3 | 1730 | return 0; |
e8bc217a MT |
1731 | } |
1732 | ||
60c8aec6 MT |
1733 | #define KVM_PAGE_ARRAY_NR 16 |
1734 | ||
1735 | struct kvm_mmu_pages { | |
1736 | struct mmu_page_and_offset { | |
1737 | struct kvm_mmu_page *sp; | |
1738 | unsigned int idx; | |
1739 | } page[KVM_PAGE_ARRAY_NR]; | |
1740 | unsigned int nr; | |
1741 | }; | |
1742 | ||
cded19f3 HE |
1743 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1744 | int idx) | |
4731d4c7 | 1745 | { |
60c8aec6 | 1746 | int i; |
4731d4c7 | 1747 | |
60c8aec6 MT |
1748 | if (sp->unsync) |
1749 | for (i=0; i < pvec->nr; i++) | |
1750 | if (pvec->page[i].sp == sp) | |
1751 | return 0; | |
1752 | ||
1753 | pvec->page[pvec->nr].sp = sp; | |
1754 | pvec->page[pvec->nr].idx = idx; | |
1755 | pvec->nr++; | |
1756 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1757 | } | |
1758 | ||
fd951457 TY |
1759 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1760 | { | |
1761 | --sp->unsync_children; | |
1762 | WARN_ON((int)sp->unsync_children < 0); | |
1763 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1764 | } | |
1765 | ||
60c8aec6 MT |
1766 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1767 | struct kvm_mmu_pages *pvec) | |
1768 | { | |
1769 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1770 | |
37178b8b | 1771 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1772 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1773 | u64 ent = sp->spt[i]; |
1774 | ||
fd951457 TY |
1775 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1776 | clear_unsync_child_bit(sp, i); | |
1777 | continue; | |
1778 | } | |
7a8f1a74 | 1779 | |
e47c4aee | 1780 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1781 | |
1782 | if (child->unsync_children) { | |
1783 | if (mmu_pages_add(pvec, child, i)) | |
1784 | return -ENOSPC; | |
1785 | ||
1786 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1787 | if (!ret) { |
1788 | clear_unsync_child_bit(sp, i); | |
1789 | continue; | |
1790 | } else if (ret > 0) { | |
7a8f1a74 | 1791 | nr_unsync_leaf += ret; |
fd951457 | 1792 | } else |
7a8f1a74 XG |
1793 | return ret; |
1794 | } else if (child->unsync) { | |
1795 | nr_unsync_leaf++; | |
1796 | if (mmu_pages_add(pvec, child, i)) | |
1797 | return -ENOSPC; | |
1798 | } else | |
fd951457 | 1799 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1800 | } |
1801 | ||
60c8aec6 MT |
1802 | return nr_unsync_leaf; |
1803 | } | |
1804 | ||
e23d3fef XG |
1805 | #define INVALID_INDEX (-1) |
1806 | ||
60c8aec6 MT |
1807 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1808 | struct kvm_mmu_pages *pvec) | |
1809 | { | |
0a47cd85 | 1810 | pvec->nr = 0; |
60c8aec6 MT |
1811 | if (!sp->unsync_children) |
1812 | return 0; | |
1813 | ||
e23d3fef | 1814 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1815 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1816 | } |
1817 | ||
4731d4c7 MT |
1818 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1819 | { | |
1820 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1821 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1822 | sp->unsync = 0; |
1823 | --kvm->stat.mmu_unsync; | |
1824 | } | |
1825 | ||
83cdb568 SC |
1826 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1827 | struct list_head *invalid_list); | |
7775834a XG |
1828 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1829 | struct list_head *invalid_list); | |
4731d4c7 | 1830 | |
ac101b7c SC |
1831 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1832 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1833 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1834 | } else |
1044b030 TY |
1835 | |
1836 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1837 | for_each_valid_sp(_kvm, _sp, \ |
1838 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1839 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1840 | |
479a1efc SC |
1841 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1842 | struct list_head *invalid_list) | |
4731d4c7 | 1843 | { |
2640b086 | 1844 | if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 1845 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1846 | return false; |
4731d4c7 MT |
1847 | } |
1848 | ||
1f50f1b3 | 1849 | return true; |
4731d4c7 MT |
1850 | } |
1851 | ||
a2113634 SC |
1852 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1853 | struct list_head *invalid_list, | |
1854 | bool remote_flush) | |
1855 | { | |
cfd32acf | 1856 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1857 | return false; |
1858 | ||
1859 | if (!list_empty(invalid_list)) | |
1860 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1861 | else | |
1862 | kvm_flush_remote_tlbs(kvm); | |
1863 | return true; | |
1864 | } | |
1865 | ||
35a70510 PB |
1866 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1867 | struct list_head *invalid_list, | |
1868 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1869 | { |
a2113634 | 1870 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1871 | return; |
d98ba053 | 1872 | |
a2113634 | 1873 | if (local_flush) |
8c8560b8 | 1874 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1875 | } |
1876 | ||
e37fa785 XG |
1877 | #ifdef CONFIG_KVM_MMU_AUDIT |
1878 | #include "mmu_audit.c" | |
1879 | #else | |
1880 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1881 | static void mmu_audit_disable(void) { } | |
1882 | #endif | |
1883 | ||
002c5f73 SC |
1884 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1885 | { | |
fac026da SC |
1886 | return sp->role.invalid || |
1887 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1888 | } |
1889 | ||
60c8aec6 | 1890 | struct mmu_page_path { |
2a7266a8 YZ |
1891 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1892 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1893 | }; |
1894 | ||
60c8aec6 | 1895 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1896 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1897 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1898 | i = mmu_pages_next(&pvec, &parents, i)) | |
1899 | ||
cded19f3 HE |
1900 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1901 | struct mmu_page_path *parents, | |
1902 | int i) | |
60c8aec6 MT |
1903 | { |
1904 | int n; | |
1905 | ||
1906 | for (n = i+1; n < pvec->nr; n++) { | |
1907 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1908 | unsigned idx = pvec->page[n].idx; |
1909 | int level = sp->role.level; | |
60c8aec6 | 1910 | |
0a47cd85 | 1911 | parents->idx[level-1] = idx; |
3bae0459 | 1912 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1913 | break; |
60c8aec6 | 1914 | |
0a47cd85 | 1915 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1916 | } |
1917 | ||
1918 | return n; | |
1919 | } | |
1920 | ||
0a47cd85 PB |
1921 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1922 | struct mmu_page_path *parents) | |
1923 | { | |
1924 | struct kvm_mmu_page *sp; | |
1925 | int level; | |
1926 | ||
1927 | if (pvec->nr == 0) | |
1928 | return 0; | |
1929 | ||
e23d3fef XG |
1930 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1931 | ||
0a47cd85 PB |
1932 | sp = pvec->page[0].sp; |
1933 | level = sp->role.level; | |
3bae0459 | 1934 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1935 | |
1936 | parents->parent[level-2] = sp; | |
1937 | ||
1938 | /* Also set up a sentinel. Further entries in pvec are all | |
1939 | * children of sp, so this element is never overwritten. | |
1940 | */ | |
1941 | parents->parent[level-1] = NULL; | |
1942 | return mmu_pages_next(pvec, parents, 0); | |
1943 | } | |
1944 | ||
cded19f3 | 1945 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1946 | { |
60c8aec6 MT |
1947 | struct kvm_mmu_page *sp; |
1948 | unsigned int level = 0; | |
1949 | ||
1950 | do { | |
1951 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1952 | sp = parents->parent[level]; |
1953 | if (!sp) | |
1954 | return; | |
1955 | ||
e23d3fef | 1956 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1957 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1958 | level++; |
0a47cd85 | 1959 | } while (!sp->unsync_children); |
60c8aec6 | 1960 | } |
4731d4c7 | 1961 | |
60c8aec6 MT |
1962 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1963 | struct kvm_mmu_page *parent) | |
1964 | { | |
1965 | int i; | |
1966 | struct kvm_mmu_page *sp; | |
1967 | struct mmu_page_path parents; | |
1968 | struct kvm_mmu_pages pages; | |
d98ba053 | 1969 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1970 | bool flush = false; |
60c8aec6 | 1971 | |
60c8aec6 | 1972 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1973 | bool protected = false; |
b1a36821 MT |
1974 | |
1975 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1976 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1977 | |
50c9e6f3 | 1978 | if (protected) { |
b1a36821 | 1979 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
1980 | flush = false; |
1981 | } | |
b1a36821 | 1982 | |
60c8aec6 | 1983 | for_each_sp(pages, sp, parents, i) { |
479a1efc | 1984 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1f50f1b3 | 1985 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1986 | mmu_pages_clear_parents(&parents); |
1987 | } | |
531810ca | 1988 | if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) { |
50c9e6f3 | 1989 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); |
531810ca | 1990 | cond_resched_rwlock_write(&vcpu->kvm->mmu_lock); |
50c9e6f3 PB |
1991 | flush = false; |
1992 | } | |
60c8aec6 | 1993 | } |
50c9e6f3 PB |
1994 | |
1995 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
1996 | } |
1997 | ||
a30f47cb XG |
1998 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1999 | { | |
e5691a81 | 2000 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2001 | } |
2002 | ||
2003 | static void clear_sp_write_flooding_count(u64 *spte) | |
2004 | { | |
57354682 | 2005 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
2006 | } |
2007 | ||
cea0f0e7 AK |
2008 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2009 | gfn_t gfn, | |
2010 | gva_t gaddr, | |
2011 | unsigned level, | |
f6e2c02b | 2012 | int direct, |
0a2b64c5 | 2013 | unsigned int access) |
cea0f0e7 | 2014 | { |
fb58a9c3 | 2015 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2016 | union kvm_mmu_page_role role; |
ac101b7c | 2017 | struct hlist_head *sp_list; |
cea0f0e7 | 2018 | unsigned quadrant; |
9f1a122f | 2019 | struct kvm_mmu_page *sp; |
f3414bc7 | 2020 | int collisions = 0; |
2a74003a | 2021 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2022 | |
36d9594d | 2023 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2024 | role.level = level; |
f6e2c02b | 2025 | role.direct = direct; |
84b0c8c6 | 2026 | if (role.direct) |
47c42e6b | 2027 | role.gpte_is_8_bytes = true; |
41074d07 | 2028 | role.access = access; |
fb58a9c3 | 2029 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2030 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2031 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2032 | role.quadrant = quadrant; | |
2033 | } | |
ac101b7c SC |
2034 | |
2035 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2036 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2037 | if (sp->gfn != gfn) { |
2038 | collisions++; | |
2039 | continue; | |
2040 | } | |
2041 | ||
ddc16abb SC |
2042 | if (sp->role.word != role.word) { |
2043 | /* | |
2044 | * If the guest is creating an upper-level page, zap | |
2045 | * unsync pages for the same gfn. While it's possible | |
2046 | * the guest is using recursive page tables, in all | |
2047 | * likelihood the guest has stopped using the unsync | |
2048 | * page and is installing a completely unrelated page. | |
2049 | * Unsync pages must not be left as is, because the new | |
2050 | * upper-level page will be write-protected. | |
2051 | */ | |
2052 | if (level > PG_LEVEL_4K && sp->unsync) | |
2053 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, | |
2054 | &invalid_list); | |
7ae680eb | 2055 | continue; |
ddc16abb | 2056 | } |
4731d4c7 | 2057 | |
fb58a9c3 SC |
2058 | if (direct_mmu) |
2059 | goto trace_get_page; | |
2060 | ||
2a74003a | 2061 | if (sp->unsync) { |
07dc4f35 | 2062 | /* |
479a1efc | 2063 | * The page is good, but is stale. kvm_sync_page does |
07dc4f35 SC |
2064 | * get the latest guest state, but (unlike mmu_unsync_children) |
2065 | * it doesn't write-protect the page or mark it synchronized! | |
2066 | * This way the validity of the mapping is ensured, but the | |
2067 | * overhead of write protection is not incurred until the | |
2068 | * guest invalidates the TLB mapping. This allows multiple | |
2069 | * SPs for a single gfn to be unsync. | |
2070 | * | |
2071 | * If the sync fails, the page is zapped. If so, break | |
2072 | * in order to rebuild it. | |
2a74003a | 2073 | */ |
479a1efc | 2074 | if (!kvm_sync_page(vcpu, sp, &invalid_list)) |
2a74003a PB |
2075 | break; |
2076 | ||
2077 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2078 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2079 | } |
e02aa901 | 2080 | |
98bba238 | 2081 | if (sp->unsync_children) |
f6f6195b | 2082 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2083 | |
a30f47cb | 2084 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2085 | |
2086 | trace_get_page: | |
7ae680eb | 2087 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2088 | goto out; |
7ae680eb | 2089 | } |
47005792 | 2090 | |
dfc5aa00 | 2091 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2092 | |
2093 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2094 | ||
4db35314 AK |
2095 | sp->gfn = gfn; |
2096 | sp->role = role; | |
ac101b7c | 2097 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2098 | if (!direct) { |
56ca57f9 | 2099 | account_shadowed(vcpu->kvm, sp); |
3bae0459 | 2100 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2101 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
4731d4c7 | 2102 | } |
f691fe1d | 2103 | trace_kvm_mmu_get_page(sp, true); |
f3414bc7 | 2104 | out: |
ddc16abb SC |
2105 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
2106 | ||
f3414bc7 DM |
2107 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) |
2108 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2109 | return sp; |
cea0f0e7 AK |
2110 | } |
2111 | ||
7eb77e9f JS |
2112 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2113 | struct kvm_vcpu *vcpu, hpa_t root, | |
2114 | u64 addr) | |
2d11123a AK |
2115 | { |
2116 | iterator->addr = addr; | |
7eb77e9f | 2117 | iterator->shadow_addr = root; |
44dd3ffa | 2118 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2119 | |
2a7266a8 | 2120 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2121 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2122 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2123 | --iterator->level; |
2124 | ||
2d11123a | 2125 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2126 | /* |
2127 | * prev_root is currently only used for 64-bit hosts. So only | |
2128 | * the active root_hpa is valid here. | |
2129 | */ | |
44dd3ffa | 2130 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2131 | |
2d11123a | 2132 | iterator->shadow_addr |
44dd3ffa | 2133 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2134 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2135 | --iterator->level; | |
2136 | if (!iterator->shadow_addr) | |
2137 | iterator->level = 0; | |
2138 | } | |
2139 | } | |
2140 | ||
7eb77e9f JS |
2141 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2142 | struct kvm_vcpu *vcpu, u64 addr) | |
2143 | { | |
44dd3ffa | 2144 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2145 | addr); |
2146 | } | |
2147 | ||
2d11123a AK |
2148 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2149 | { | |
3bae0459 | 2150 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2151 | return false; |
4d88954d | 2152 | |
2d11123a AK |
2153 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2154 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2155 | return true; | |
2156 | } | |
2157 | ||
c2a2ac2b XG |
2158 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2159 | u64 spte) | |
2d11123a | 2160 | { |
c2a2ac2b | 2161 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2162 | iterator->level = 0; |
2163 | return; | |
2164 | } | |
2165 | ||
c2a2ac2b | 2166 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2167 | --iterator->level; |
2168 | } | |
2169 | ||
c2a2ac2b XG |
2170 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2171 | { | |
bb606a9b | 2172 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2173 | } |
2174 | ||
cc4674d0 BG |
2175 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2176 | struct kvm_mmu_page *sp) | |
2177 | { | |
2178 | u64 spte; | |
2179 | ||
2180 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2181 | ||
2182 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2183 | ||
1df9f2dc | 2184 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2185 | |
2186 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2187 | ||
2188 | if (sp->unsync_children || sp->unsync) | |
2189 | mark_unsync(sptep); | |
32ef26a3 AK |
2190 | } |
2191 | ||
a357bd22 AK |
2192 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2193 | unsigned direct_access) | |
2194 | { | |
2195 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2196 | struct kvm_mmu_page *child; | |
2197 | ||
2198 | /* | |
2199 | * For the direct sp, if the guest pte's dirty bit | |
2200 | * changed form clean to dirty, it will corrupt the | |
2201 | * sp's access: allow writable in the read-only sp, | |
2202 | * so we should update the spte at this point to get | |
2203 | * a new sp with the correct access. | |
2204 | */ | |
e47c4aee | 2205 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2206 | if (child->role.access == direct_access) |
2207 | return; | |
2208 | ||
bcdd9a93 | 2209 | drop_parent_pte(child, sptep); |
c3134ce2 | 2210 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2211 | } |
2212 | } | |
2213 | ||
2de4085c BG |
2214 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2215 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2216 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2217 | { |
2218 | u64 pte; | |
2219 | struct kvm_mmu_page *child; | |
2220 | ||
2221 | pte = *spte; | |
2222 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2223 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2224 | drop_spte(kvm, spte); |
505aef8f XG |
2225 | if (is_large_pte(pte)) |
2226 | --kvm->stat.lpages; | |
2227 | } else { | |
e47c4aee | 2228 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2229 | drop_parent_pte(child, spte); |
2de4085c BG |
2230 | |
2231 | /* | |
2232 | * Recursively zap nested TDP SPs, parentless SPs are | |
2233 | * unlikely to be used again in the near future. This | |
2234 | * avoids retaining a large number of stale nested SPs. | |
2235 | */ | |
2236 | if (tdp_enabled && invalid_list && | |
2237 | child->role.guest_mode && !child->parent_ptes.val) | |
2238 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2239 | invalid_list); | |
38e3b2b2 | 2240 | } |
ace569e0 | 2241 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2242 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2243 | } |
2de4085c | 2244 | return 0; |
38e3b2b2 XG |
2245 | } |
2246 | ||
2de4085c BG |
2247 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2248 | struct kvm_mmu_page *sp, | |
2249 | struct list_head *invalid_list) | |
a436036b | 2250 | { |
2de4085c | 2251 | int zapped = 0; |
697fe2e2 | 2252 | unsigned i; |
697fe2e2 | 2253 | |
38e3b2b2 | 2254 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2255 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2256 | ||
2257 | return zapped; | |
a436036b AK |
2258 | } |
2259 | ||
31aa2b44 | 2260 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2261 | { |
1e3f42f0 TY |
2262 | u64 *sptep; |
2263 | struct rmap_iterator iter; | |
a436036b | 2264 | |
018aabb5 | 2265 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2266 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2267 | } |
2268 | ||
60c8aec6 | 2269 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2270 | struct kvm_mmu_page *parent, |
2271 | struct list_head *invalid_list) | |
4731d4c7 | 2272 | { |
60c8aec6 MT |
2273 | int i, zapped = 0; |
2274 | struct mmu_page_path parents; | |
2275 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2276 | |
3bae0459 | 2277 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2278 | return 0; |
60c8aec6 | 2279 | |
60c8aec6 MT |
2280 | while (mmu_unsync_walk(parent, &pages)) { |
2281 | struct kvm_mmu_page *sp; | |
2282 | ||
2283 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2284 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2285 | mmu_pages_clear_parents(&parents); |
77662e00 | 2286 | zapped++; |
60c8aec6 | 2287 | } |
60c8aec6 MT |
2288 | } |
2289 | ||
2290 | return zapped; | |
4731d4c7 MT |
2291 | } |
2292 | ||
83cdb568 SC |
2293 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2294 | struct kvm_mmu_page *sp, | |
2295 | struct list_head *invalid_list, | |
2296 | int *nr_zapped) | |
31aa2b44 | 2297 | { |
83cdb568 | 2298 | bool list_unstable; |
f691fe1d | 2299 | |
7775834a | 2300 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2301 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2302 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2303 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2304 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2305 | |
83cdb568 SC |
2306 | /* Zapping children means active_mmu_pages has become unstable. */ |
2307 | list_unstable = *nr_zapped; | |
2308 | ||
f6e2c02b | 2309 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2310 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2311 | |
4731d4c7 MT |
2312 | if (sp->unsync) |
2313 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2314 | if (!sp->root_count) { |
54a4f023 | 2315 | /* Count self */ |
83cdb568 | 2316 | (*nr_zapped)++; |
f95eec9b SC |
2317 | |
2318 | /* | |
2319 | * Already invalid pages (previously active roots) are not on | |
2320 | * the active page list. See list_del() in the "else" case of | |
2321 | * !sp->root_count. | |
2322 | */ | |
2323 | if (sp->role.invalid) | |
2324 | list_add(&sp->link, invalid_list); | |
2325 | else | |
2326 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2327 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2328 | } else { |
f95eec9b SC |
2329 | /* |
2330 | * Remove the active root from the active page list, the root | |
2331 | * will be explicitly freed when the root_count hits zero. | |
2332 | */ | |
2333 | list_del(&sp->link); | |
05988d72 | 2334 | |
10605204 SC |
2335 | /* |
2336 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2337 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2338 | * treats invalid shadow pages as being obsolete. | |
2339 | */ | |
2340 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2341 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2342 | } |
7775834a | 2343 | |
b8e8c830 PB |
2344 | if (sp->lpage_disallowed) |
2345 | unaccount_huge_nx_page(kvm, sp); | |
2346 | ||
7775834a | 2347 | sp->role.invalid = 1; |
83cdb568 SC |
2348 | return list_unstable; |
2349 | } | |
2350 | ||
2351 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2352 | struct list_head *invalid_list) | |
2353 | { | |
2354 | int nr_zapped; | |
2355 | ||
2356 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2357 | return nr_zapped; | |
a436036b AK |
2358 | } |
2359 | ||
7775834a XG |
2360 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2361 | struct list_head *invalid_list) | |
2362 | { | |
945315b9 | 2363 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2364 | |
2365 | if (list_empty(invalid_list)) | |
2366 | return; | |
2367 | ||
c142786c | 2368 | /* |
9753f529 LT |
2369 | * We need to make sure everyone sees our modifications to |
2370 | * the page tables and see changes to vcpu->mode here. The barrier | |
2371 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2372 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2373 | * | |
2374 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2375 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2376 | */ |
2377 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2378 | |
945315b9 | 2379 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2380 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2381 | kvm_mmu_free_page(sp); |
945315b9 | 2382 | } |
7775834a XG |
2383 | } |
2384 | ||
6b82ef2c SC |
2385 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2386 | unsigned long nr_to_zap) | |
5da59607 | 2387 | { |
6b82ef2c SC |
2388 | unsigned long total_zapped = 0; |
2389 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2390 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2391 | bool unstable; |
2392 | int nr_zapped; | |
5da59607 TY |
2393 | |
2394 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2395 | return 0; |
2396 | ||
6b82ef2c | 2397 | restart: |
8fc51726 | 2398 | list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) { |
6b82ef2c SC |
2399 | /* |
2400 | * Don't zap active root pages, the page itself can't be freed | |
2401 | * and zapping it will just force vCPUs to realloc and reload. | |
2402 | */ | |
2403 | if (sp->root_count) | |
2404 | continue; | |
2405 | ||
2406 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2407 | &nr_zapped); | |
2408 | total_zapped += nr_zapped; | |
2409 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2410 | break; |
2411 | ||
6b82ef2c SC |
2412 | if (unstable) |
2413 | goto restart; | |
ba7888dd | 2414 | } |
5da59607 | 2415 | |
6b82ef2c SC |
2416 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2417 | ||
2418 | kvm->stat.mmu_recycled += total_zapped; | |
2419 | return total_zapped; | |
2420 | } | |
2421 | ||
afe8d7e6 SC |
2422 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2423 | { | |
2424 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2425 | return kvm->arch.n_max_mmu_pages - | |
2426 | kvm->arch.n_used_mmu_pages; | |
2427 | ||
2428 | return 0; | |
5da59607 TY |
2429 | } |
2430 | ||
ba7888dd SC |
2431 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2432 | { | |
6b82ef2c | 2433 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2434 | |
6b82ef2c | 2435 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2436 | return 0; |
2437 | ||
6b82ef2c | 2438 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd | 2439 | |
6e6ec584 SC |
2440 | /* |
2441 | * Note, this check is intentionally soft, it only guarantees that one | |
2442 | * page is available, while the caller may end up allocating as many as | |
2443 | * four pages, e.g. for PAE roots or for 5-level paging. Temporarily | |
2444 | * exceeding the (arbitrary by default) limit will not harm the host, | |
2445 | * being too agressive may unnecessarily kill the guest, and getting an | |
2446 | * exact count is far more trouble than it's worth, especially in the | |
2447 | * page fault paths. | |
2448 | */ | |
ba7888dd SC |
2449 | if (!kvm_mmu_available_pages(vcpu->kvm)) |
2450 | return -ENOSPC; | |
2451 | return 0; | |
2452 | } | |
2453 | ||
82ce2c96 IE |
2454 | /* |
2455 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2456 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2457 | */ |
bc8a3d89 | 2458 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2459 | { |
531810ca | 2460 | write_lock(&kvm->mmu_lock); |
b34cb590 | 2461 | |
49d5ca26 | 2462 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2463 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2464 | goal_nr_mmu_pages); | |
82ce2c96 | 2465 | |
49d5ca26 | 2466 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2467 | } |
82ce2c96 | 2468 | |
49d5ca26 | 2469 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 | 2470 | |
531810ca | 2471 | write_unlock(&kvm->mmu_lock); |
82ce2c96 IE |
2472 | } |
2473 | ||
1cb3f3ae | 2474 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2475 | { |
4db35314 | 2476 | struct kvm_mmu_page *sp; |
d98ba053 | 2477 | LIST_HEAD(invalid_list); |
a436036b AK |
2478 | int r; |
2479 | ||
9ad17b10 | 2480 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2481 | r = 0; |
531810ca | 2482 | write_lock(&kvm->mmu_lock); |
b67bfe0d | 2483 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2484 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2485 | sp->role.word); |
2486 | r = 1; | |
f41d335a | 2487 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2488 | } |
d98ba053 | 2489 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 2490 | write_unlock(&kvm->mmu_lock); |
1cb3f3ae | 2491 | |
a436036b | 2492 | return r; |
cea0f0e7 | 2493 | } |
96ad91ae SC |
2494 | |
2495 | static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) | |
2496 | { | |
2497 | gpa_t gpa; | |
2498 | int r; | |
2499 | ||
2500 | if (vcpu->arch.mmu->direct_map) | |
2501 | return 0; | |
2502 | ||
2503 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); | |
2504 | ||
2505 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2506 | ||
2507 | return r; | |
2508 | } | |
cea0f0e7 | 2509 | |
5c520e90 | 2510 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2511 | { |
2512 | trace_kvm_mmu_unsync_page(sp); | |
2513 | ++vcpu->kvm->stat.mmu_unsync; | |
2514 | sp->unsync = 1; | |
2515 | ||
2516 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2517 | } |
2518 | ||
0337f585 SC |
2519 | /* |
2520 | * Attempt to unsync any shadow pages that can be reached by the specified gfn, | |
2521 | * KVM is creating a writable mapping for said gfn. Returns 0 if all pages | |
2522 | * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must | |
2523 | * be write-protected. | |
2524 | */ | |
2525 | int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync) | |
4731d4c7 | 2526 | { |
5c520e90 | 2527 | struct kvm_mmu_page *sp; |
4731d4c7 | 2528 | |
0337f585 SC |
2529 | /* |
2530 | * Force write-protection if the page is being tracked. Note, the page | |
2531 | * track machinery is used to write-protect upper-level shadow pages, | |
2532 | * i.e. this guards the role.level == 4K assertion below! | |
2533 | */ | |
3d0c27ad | 2534 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
0337f585 | 2535 | return -EPERM; |
9cf5cf5a | 2536 | |
0337f585 SC |
2537 | /* |
2538 | * The page is not write-tracked, mark existing shadow pages unsync | |
2539 | * unless KVM is synchronizing an unsync SP (can_unsync = false). In | |
2540 | * that case, KVM must complete emulation of the guest TLB flush before | |
2541 | * allowing shadow pages to become unsync (writable by the guest). | |
2542 | */ | |
5c520e90 | 2543 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2544 | if (!can_unsync) |
0337f585 | 2545 | return -EPERM; |
36a2e677 | 2546 | |
5c520e90 XG |
2547 | if (sp->unsync) |
2548 | continue; | |
9cf5cf5a | 2549 | |
3bae0459 | 2550 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2551 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2552 | } |
3d0c27ad | 2553 | |
578e1c4d JS |
2554 | /* |
2555 | * We need to ensure that the marking of unsync pages is visible | |
2556 | * before the SPTE is updated to allow writes because | |
2557 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2558 | * the MMU lock and so can race with this. If the SPTE was updated | |
2559 | * before the page had been marked as unsync-ed, something like the | |
2560 | * following could happen: | |
2561 | * | |
2562 | * CPU 1 CPU 2 | |
2563 | * --------------------------------------------------------------------- | |
2564 | * 1.2 Host updates SPTE | |
2565 | * to be writable | |
2566 | * 2.1 Guest writes a GPTE for GVA X. | |
2567 | * (GPTE being in the guest page table shadowed | |
2568 | * by the SP from CPU 1.) | |
2569 | * This reads SPTE during the page table walk. | |
2570 | * Since SPTE.W is read as 1, there is no | |
2571 | * fault. | |
2572 | * | |
2573 | * 2.2 Guest issues TLB flush. | |
2574 | * That causes a VM Exit. | |
2575 | * | |
0337f585 SC |
2576 | * 2.3 Walking of unsync pages sees sp->unsync is |
2577 | * false and skips the page. | |
578e1c4d JS |
2578 | * |
2579 | * 2.4 Guest accesses GVA X. | |
2580 | * Since the mapping in the SP was not updated, | |
2581 | * so the old mapping for GVA X incorrectly | |
2582 | * gets used. | |
2583 | * 1.1 Host marks SP | |
2584 | * as unsync | |
2585 | * (sp->unsync = true) | |
2586 | * | |
2587 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2588 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2589 | * pairs with this write barrier. | |
2590 | */ | |
2591 | smp_wmb(); | |
2592 | ||
0337f585 | 2593 | return 0; |
4731d4c7 MT |
2594 | } |
2595 | ||
799a4190 BG |
2596 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2597 | unsigned int pte_access, int level, | |
2598 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2599 | bool can_unsync, bool host_writable) | |
2600 | { | |
2601 | u64 spte; | |
2602 | struct kvm_mmu_page *sp; | |
2603 | int ret; | |
2604 | ||
799a4190 BG |
2605 | sp = sptep_to_sp(sptep); |
2606 | ||
2607 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2608 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2609 | ||
2610 | if (spte & PT_WRITABLE_MASK) | |
2611 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2612 | ||
12703759 SC |
2613 | if (*sptep == spte) |
2614 | ret |= SET_SPTE_SPURIOUS; | |
2615 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2616 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2617 | return ret; |
2618 | } | |
2619 | ||
0a2b64c5 | 2620 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2621 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2622 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2623 | bool host_writable) | |
1e73f9dd MT |
2624 | { |
2625 | int was_rmapped = 0; | |
53a27b39 | 2626 | int rmap_count; |
5ce4786f | 2627 | int set_spte_ret; |
c4371c2a | 2628 | int ret = RET_PF_FIXED; |
c2a4eadf | 2629 | bool flush = false; |
1e73f9dd | 2630 | |
f7616203 XG |
2631 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2632 | *sptep, write_fault, gfn); | |
1e73f9dd | 2633 | |
a54aa15c SC |
2634 | if (unlikely(is_noslot_pfn(pfn))) { |
2635 | mark_mmio_spte(vcpu, sptep, gfn, pte_access); | |
2636 | return RET_PF_EMULATE; | |
2637 | } | |
2638 | ||
afd28fe1 | 2639 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2640 | /* |
2641 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2642 | * the parent of the now unreachable PTE. | |
2643 | */ | |
3bae0459 | 2644 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2645 | struct kvm_mmu_page *child; |
d555c333 | 2646 | u64 pte = *sptep; |
1e73f9dd | 2647 | |
e47c4aee | 2648 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2649 | drop_parent_pte(child, sptep); |
c2a4eadf | 2650 | flush = true; |
d555c333 | 2651 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2652 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2653 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2654 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2655 | flush = true; |
6bed6b9e JR |
2656 | } else |
2657 | was_rmapped = 1; | |
1e73f9dd | 2658 | } |
852e3c19 | 2659 | |
5ce4786f JS |
2660 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2661 | speculative, true, host_writable); | |
2662 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2663 | if (write_fault) |
9b8ebbdb | 2664 | ret = RET_PF_EMULATE; |
8c8560b8 | 2665 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2666 | } |
c3134ce2 | 2667 | |
c2a4eadf | 2668 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2669 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2670 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2671 | |
12703759 SC |
2672 | /* |
2673 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2674 | * are identical, and emulation is not required. | |
2675 | */ | |
2676 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2677 | WARN_ON_ONCE(!was_rmapped); | |
2678 | return RET_PF_SPURIOUS; | |
2679 | } | |
2680 | ||
d555c333 | 2681 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2682 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2683 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2684 | ++vcpu->kvm->stat.lpages; |
2685 | ||
ffb61bb3 | 2686 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2687 | if (!was_rmapped) { |
2688 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2689 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2690 | rmap_recycle(vcpu, sptep, gfn); | |
2691 | } | |
1c4f1fd6 | 2692 | } |
cb9aaa30 | 2693 | |
9b8ebbdb | 2694 | return ret; |
1c4f1fd6 AK |
2695 | } |
2696 | ||
ba049e93 | 2697 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2698 | bool no_dirty_log) |
2699 | { | |
2700 | struct kvm_memory_slot *slot; | |
957ed9ef | 2701 | |
5d163b1c | 2702 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2703 | if (!slot) |
6c8ee57b | 2704 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2705 | |
037d92dc | 2706 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2707 | } |
2708 | ||
2709 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2710 | struct kvm_mmu_page *sp, | |
2711 | u64 *start, u64 *end) | |
2712 | { | |
2713 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2714 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2715 | unsigned int access = sp->role.access; |
957ed9ef XG |
2716 | int i, ret; |
2717 | gfn_t gfn; | |
2718 | ||
2719 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2720 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2721 | if (!slot) | |
957ed9ef XG |
2722 | return -1; |
2723 | ||
d9ef13c2 | 2724 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2725 | if (ret <= 0) |
2726 | return -1; | |
2727 | ||
43fdcda9 | 2728 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2729 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2730 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2731 | put_page(pages[i]); |
2732 | } | |
957ed9ef XG |
2733 | |
2734 | return 0; | |
2735 | } | |
2736 | ||
2737 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2738 | struct kvm_mmu_page *sp, u64 *sptep) | |
2739 | { | |
2740 | u64 *spte, *start = NULL; | |
2741 | int i; | |
2742 | ||
2743 | WARN_ON(!sp->role.direct); | |
2744 | ||
2745 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2746 | spte = sp->spt + i; | |
2747 | ||
2748 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2749 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2750 | if (!start) |
2751 | continue; | |
2752 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2753 | break; | |
2754 | start = NULL; | |
2755 | } else if (!start) | |
2756 | start = spte; | |
2757 | } | |
2758 | } | |
2759 | ||
2760 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2761 | { | |
2762 | struct kvm_mmu_page *sp; | |
2763 | ||
57354682 | 2764 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2765 | |
957ed9ef | 2766 | /* |
ac8d57e5 PF |
2767 | * Without accessed bits, there's no way to distinguish between |
2768 | * actually accessed translations and prefetched, so disable pte | |
2769 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2770 | */ |
ac8d57e5 | 2771 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2772 | return; |
2773 | ||
3bae0459 | 2774 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2775 | return; |
2776 | ||
4a42d848 DS |
2777 | /* |
2778 | * If addresses are being invalidated, skip prefetching to avoid | |
2779 | * accidentally prefetching those addresses. | |
2780 | */ | |
2781 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
2782 | return; | |
2783 | ||
957ed9ef XG |
2784 | __direct_pte_prefetch(vcpu, sp, sptep); |
2785 | } | |
2786 | ||
1b6d9d9e | 2787 | static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, |
8ca6f063 | 2788 | const struct kvm_memory_slot *slot) |
db543216 | 2789 | { |
db543216 SC |
2790 | unsigned long hva; |
2791 | pte_t *pte; | |
2792 | int level; | |
2793 | ||
e851265a | 2794 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2795 | return PG_LEVEL_4K; |
db543216 | 2796 | |
293e306e SC |
2797 | /* |
2798 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2799 | * is not solely for performance, it's also necessary to avoid the | |
2800 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2801 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2802 | * page fault steps have already verified the guest isn't writing a | |
2803 | * read-only memslot. | |
2804 | */ | |
db543216 SC |
2805 | hva = __gfn_to_hva_memslot(slot, gfn); |
2806 | ||
1b6d9d9e | 2807 | pte = lookup_address_in_mm(kvm->mm, hva, &level); |
db543216 | 2808 | if (unlikely(!pte)) |
3bae0459 | 2809 | return PG_LEVEL_4K; |
db543216 SC |
2810 | |
2811 | return level; | |
2812 | } | |
2813 | ||
8ca6f063 BG |
2814 | int kvm_mmu_max_mapping_level(struct kvm *kvm, |
2815 | const struct kvm_memory_slot *slot, gfn_t gfn, | |
2816 | kvm_pfn_t pfn, int max_level) | |
1b6d9d9e SC |
2817 | { |
2818 | struct kvm_lpage_info *linfo; | |
2819 | ||
2820 | max_level = min(max_level, max_huge_page_level); | |
2821 | for ( ; max_level > PG_LEVEL_4K; max_level--) { | |
2822 | linfo = lpage_info_slot(gfn, slot, max_level); | |
2823 | if (!linfo->disallow_lpage) | |
2824 | break; | |
2825 | } | |
2826 | ||
2827 | if (max_level == PG_LEVEL_4K) | |
2828 | return PG_LEVEL_4K; | |
2829 | ||
2830 | return host_pfn_mapping_level(kvm, gfn, pfn, slot); | |
2831 | } | |
2832 | ||
bb18842e BG |
2833 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2834 | int max_level, kvm_pfn_t *pfnp, | |
2835 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2836 | { |
293e306e | 2837 | struct kvm_memory_slot *slot; |
0885904d | 2838 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2839 | kvm_pfn_t mask; |
83f06fa7 | 2840 | int level; |
17eff019 | 2841 | |
3cf06612 SC |
2842 | *req_level = PG_LEVEL_4K; |
2843 | ||
3bae0459 SC |
2844 | if (unlikely(max_level == PG_LEVEL_4K)) |
2845 | return PG_LEVEL_4K; | |
17eff019 | 2846 | |
e851265a | 2847 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2848 | return PG_LEVEL_4K; |
17eff019 | 2849 | |
293e306e SC |
2850 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2851 | if (!slot) | |
3bae0459 | 2852 | return PG_LEVEL_4K; |
293e306e | 2853 | |
1b6d9d9e | 2854 | level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level); |
3bae0459 | 2855 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2856 | return level; |
17eff019 | 2857 | |
3cf06612 SC |
2858 | *req_level = level = min(level, max_level); |
2859 | ||
2860 | /* | |
2861 | * Enforce the iTLB multihit workaround after capturing the requested | |
2862 | * level, which will be used to do precise, accurate accounting. | |
2863 | */ | |
2864 | if (huge_page_disallowed) | |
2865 | return PG_LEVEL_4K; | |
0885904d SC |
2866 | |
2867 | /* | |
17eff019 SC |
2868 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2869 | * the pmd can't be split from under us. | |
0885904d | 2870 | */ |
17eff019 SC |
2871 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2872 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2873 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2874 | |
2875 | return level; | |
0885904d SC |
2876 | } |
2877 | ||
bb18842e BG |
2878 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2879 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2880 | { |
bb18842e | 2881 | int level = *goal_levelp; |
b8e8c830 | 2882 | |
7d945312 | 2883 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2884 | is_shadow_present_pte(spte) && |
2885 | !is_large_pte(spte)) { | |
2886 | /* | |
2887 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2888 | * and __direct_map would like to create a large PTE | |
2889 | * instead: just force them to go down another level, | |
2890 | * patching back for them into pfn the next 9 bits of | |
2891 | * the address. | |
2892 | */ | |
7d945312 BG |
2893 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2894 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2895 | *pfnp |= gfn & page_mask; |
bb18842e | 2896 | (*goal_levelp)--; |
b8e8c830 PB |
2897 | } |
2898 | } | |
2899 | ||
6c2fd34f | 2900 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2901 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2902 | bool prefault, bool is_tdp) |
140754bc | 2903 | { |
6c2fd34f SC |
2904 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2905 | bool write = error_code & PFERR_WRITE_MASK; | |
2906 | bool exec = error_code & PFERR_FETCH_MASK; | |
2907 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2908 | struct kvm_shadow_walk_iterator it; |
140754bc | 2909 | struct kvm_mmu_page *sp; |
3cf06612 | 2910 | int level, req_level, ret; |
3fcf2d1b PB |
2911 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2912 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2913 | |
3cf06612 SC |
2914 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2915 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2916 | |
335e192a | 2917 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2918 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2919 | /* |
2920 | * We cannot overwrite existing page tables with an NX | |
2921 | * large page, as the leaf could be executable. | |
2922 | */ | |
dcc70651 | 2923 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
2924 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
2925 | &pfn, &level); | |
b8e8c830 | 2926 | |
3fcf2d1b PB |
2927 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2928 | if (it.level == level) | |
9f652d21 | 2929 | break; |
6aa8b732 | 2930 | |
3fcf2d1b PB |
2931 | drop_large_spte(vcpu, it.sptep); |
2932 | if (!is_shadow_present_pte(*it.sptep)) { | |
2933 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2934 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2935 | |
3fcf2d1b | 2936 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2937 | if (is_tdp && huge_page_disallowed && |
2938 | req_level >= it.level) | |
b8e8c830 | 2939 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2940 | } |
2941 | } | |
3fcf2d1b PB |
2942 | |
2943 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2944 | write, level, base_gfn, pfn, prefault, | |
2945 | map_writable); | |
12703759 SC |
2946 | if (ret == RET_PF_SPURIOUS) |
2947 | return ret; | |
2948 | ||
3fcf2d1b PB |
2949 | direct_pte_prefetch(vcpu, it.sptep); |
2950 | ++vcpu->stat.pf_fixed; | |
2951 | return ret; | |
6aa8b732 AK |
2952 | } |
2953 | ||
77db5cbd | 2954 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2955 | { |
585a8b9b | 2956 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2957 | } |
2958 | ||
ba049e93 | 2959 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2960 | { |
4d8b81ab XG |
2961 | /* |
2962 | * Do not cache the mmio info caused by writing the readonly gfn | |
2963 | * into the spte otherwise read access on readonly gfn also can | |
2964 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2965 | */ |
2966 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2967 | return RET_PF_EMULATE; |
4d8b81ab | 2968 | |
e6c1502b | 2969 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2970 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2971 | return RET_PF_RETRY; |
d7c55201 | 2972 | } |
edba23e5 | 2973 | |
2c151b25 | 2974 | return -EFAULT; |
bf998156 HY |
2975 | } |
2976 | ||
d7c55201 | 2977 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2978 | kvm_pfn_t pfn, unsigned int access, |
2979 | int *ret_val) | |
d7c55201 | 2980 | { |
d7c55201 | 2981 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2982 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2983 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2984 | return true; |
d7c55201 XG |
2985 | } |
2986 | ||
30ab5901 | 2987 | if (unlikely(is_noslot_pfn(pfn))) { |
4af77151 SC |
2988 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2989 | access & shadow_mmio_access_mask); | |
30ab5901 SC |
2990 | /* |
2991 | * If MMIO caching is disabled, emulate immediately without | |
2992 | * touching the shadow page tables as attempting to install an | |
2993 | * MMIO SPTE will just be an expensive nop. | |
2994 | */ | |
2995 | if (unlikely(!shadow_mmio_value)) { | |
2996 | *ret_val = RET_PF_EMULATE; | |
2997 | return true; | |
2998 | } | |
2999 | } | |
d7c55201 | 3000 | |
798e88b3 | 3001 | return false; |
d7c55201 XG |
3002 | } |
3003 | ||
e5552fd2 | 3004 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3005 | { |
1c118b82 XG |
3006 | /* |
3007 | * Do not fix the mmio spte with invalid generation number which | |
3008 | * need to be updated by slow page fault path. | |
3009 | */ | |
3010 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3011 | return false; | |
3012 | ||
f160c7b7 JS |
3013 | /* See if the page fault is due to an NX violation */ |
3014 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3015 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3016 | return false; | |
3017 | ||
c7ba5b48 | 3018 | /* |
f160c7b7 JS |
3019 | * #PF can be fast if: |
3020 | * 1. The shadow page table entry is not present, which could mean that | |
3021 | * the fault is potentially caused by access tracking (if enabled). | |
3022 | * 2. The shadow page table entry is present and the fault | |
3023 | * is caused by write-protect, that means we just need change the W | |
3024 | * bit of the spte which can be done out of mmu-lock. | |
3025 | * | |
3026 | * However, if access tracking is disabled we know that a non-present | |
3027 | * page must be a genuine page fault where we have to create a new SPTE. | |
3028 | * So, if access tracking is disabled, we return true only for write | |
3029 | * accesses to a present page. | |
c7ba5b48 | 3030 | */ |
c7ba5b48 | 3031 | |
f160c7b7 JS |
3032 | return shadow_acc_track_mask != 0 || |
3033 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3034 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3035 | } |
3036 | ||
97dceba2 JS |
3037 | /* |
3038 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3039 | * someone else modified the SPTE from its original value. | |
3040 | */ | |
c7ba5b48 | 3041 | static bool |
92a476cb | 3042 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3043 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3044 | { |
c7ba5b48 XG |
3045 | gfn_t gfn; |
3046 | ||
3047 | WARN_ON(!sp->role.direct); | |
3048 | ||
9b51a630 KH |
3049 | /* |
3050 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3051 | * order to eliminate unnecessary PML logging. See comments in | |
3052 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3053 | * enabled, so we do not do this. This might result in the same GPA | |
3054 | * to be logged in PML buffer again when the write really happens, and | |
3055 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3056 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3057 | * so non-PML cases won't be impacted. | |
3058 | * | |
3059 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3060 | */ | |
f160c7b7 | 3061 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3062 | return false; |
3063 | ||
d3e328f2 | 3064 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3065 | /* |
3066 | * The gfn of direct spte is stable since it is | |
3067 | * calculated by sp->gfn. | |
3068 | */ | |
3069 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3070 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3071 | } | |
c7ba5b48 XG |
3072 | |
3073 | return true; | |
3074 | } | |
3075 | ||
d3e328f2 JS |
3076 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3077 | { | |
3078 | if (fault_err_code & PFERR_FETCH_MASK) | |
3079 | return is_executable_pte(spte); | |
3080 | ||
3081 | if (fault_err_code & PFERR_WRITE_MASK) | |
3082 | return is_writable_pte(spte); | |
3083 | ||
3084 | /* Fault was on Read access */ | |
3085 | return spte & PT_PRESENT_MASK; | |
3086 | } | |
3087 | ||
c7ba5b48 | 3088 | /* |
c4371c2a | 3089 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3090 | */ |
c4371c2a SC |
3091 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3092 | u32 error_code) | |
c7ba5b48 XG |
3093 | { |
3094 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3095 | struct kvm_mmu_page *sp; |
c4371c2a | 3096 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3097 | u64 spte = 0ull; |
97dceba2 | 3098 | uint retry_count = 0; |
c7ba5b48 | 3099 | |
e5552fd2 | 3100 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3101 | return ret; |
c7ba5b48 XG |
3102 | |
3103 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3104 | |
97dceba2 | 3105 | do { |
d3e328f2 | 3106 | u64 new_spte; |
c7ba5b48 | 3107 | |
736c291c | 3108 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3109 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3110 | break; |
3111 | ||
ec89e643 SC |
3112 | if (!is_shadow_present_pte(spte)) |
3113 | break; | |
3114 | ||
57354682 | 3115 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3116 | if (!is_last_spte(spte, sp->role.level)) |
3117 | break; | |
c7ba5b48 | 3118 | |
97dceba2 | 3119 | /* |
f160c7b7 JS |
3120 | * Check whether the memory access that caused the fault would |
3121 | * still cause it if it were to be performed right now. If not, | |
3122 | * then this is a spurious fault caused by TLB lazily flushed, | |
3123 | * or some other CPU has already fixed the PTE after the | |
3124 | * current CPU took the fault. | |
97dceba2 JS |
3125 | * |
3126 | * Need not check the access of upper level table entries since | |
3127 | * they are always ACC_ALL. | |
3128 | */ | |
d3e328f2 | 3129 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3130 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3131 | break; |
3132 | } | |
f160c7b7 | 3133 | |
d3e328f2 JS |
3134 | new_spte = spte; |
3135 | ||
3136 | if (is_access_track_spte(spte)) | |
3137 | new_spte = restore_acc_track_spte(new_spte); | |
3138 | ||
3139 | /* | |
3140 | * Currently, to simplify the code, write-protection can | |
3141 | * be removed in the fast path only if the SPTE was | |
3142 | * write-protected for dirty-logging or access tracking. | |
3143 | */ | |
3144 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3145 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3146 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3147 | |
3148 | /* | |
d3e328f2 JS |
3149 | * Do not fix write-permission on the large spte. Since |
3150 | * we only dirty the first page into the dirty-bitmap in | |
3151 | * fast_pf_fix_direct_spte(), other pages are missed | |
3152 | * if its slot has dirty logging enabled. | |
3153 | * | |
3154 | * Instead, we let the slow page fault path create a | |
3155 | * normal spte to fix the access. | |
3156 | * | |
3157 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3158 | */ |
3bae0459 | 3159 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3160 | break; |
97dceba2 | 3161 | } |
c7ba5b48 | 3162 | |
f160c7b7 | 3163 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3164 | if (new_spte == spte || |
3165 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3166 | break; |
3167 | ||
3168 | /* | |
3169 | * Currently, fast page fault only works for direct mapping | |
3170 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3171 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3172 | */ |
c4371c2a SC |
3173 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3174 | new_spte)) { | |
3175 | ret = RET_PF_FIXED; | |
97dceba2 | 3176 | break; |
c4371c2a | 3177 | } |
97dceba2 JS |
3178 | |
3179 | if (++retry_count > 4) { | |
3180 | printk_once(KERN_WARNING | |
3181 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3182 | break; | |
3183 | } | |
3184 | ||
97dceba2 | 3185 | } while (true); |
c126d94f | 3186 | |
736c291c | 3187 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3188 | spte, ret); |
c7ba5b48 XG |
3189 | walk_shadow_page_lockless_end(vcpu); |
3190 | ||
c4371c2a | 3191 | return ret; |
c7ba5b48 XG |
3192 | } |
3193 | ||
74b566e6 JS |
3194 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3195 | struct list_head *invalid_list) | |
17ac10ad | 3196 | { |
4db35314 | 3197 | struct kvm_mmu_page *sp; |
17ac10ad | 3198 | |
74b566e6 | 3199 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3200 | return; |
35af577a | 3201 | |
e47c4aee | 3202 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a | 3203 | |
2bdb3d84 | 3204 | if (is_tdp_mmu_page(sp)) |
6103bc07 | 3205 | kvm_tdp_mmu_put_root(kvm, sp, false); |
76eb54e7 BG |
3206 | else if (!--sp->root_count && sp->role.invalid) |
3207 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3208 | |
74b566e6 JS |
3209 | *root_hpa = INVALID_PAGE; |
3210 | } | |
3211 | ||
08fb59d8 | 3212 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3213 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3214 | ulong roots_to_free) | |
74b566e6 | 3215 | { |
4d710de9 | 3216 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3217 | int i; |
3218 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3219 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3220 | |
b94742c9 | 3221 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3222 | |
08fb59d8 | 3223 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3224 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3225 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3226 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3227 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3228 | break; | |
3229 | ||
3230 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3231 | return; | |
3232 | } | |
35af577a | 3233 | |
531810ca | 3234 | write_lock(&kvm->mmu_lock); |
17ac10ad | 3235 | |
b94742c9 JS |
3236 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3237 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3238 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3239 | &invalid_list); |
7c390d35 | 3240 | |
08fb59d8 JS |
3241 | if (free_active_root) { |
3242 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3243 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3244 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
04d45551 | 3245 | } else if (mmu->pae_root) { |
c834e5e4 SC |
3246 | for (i = 0; i < 4; ++i) { |
3247 | if (!IS_VALID_PAE_ROOT(mmu->pae_root[i])) | |
3248 | continue; | |
3249 | ||
3250 | mmu_free_root_page(kvm, &mmu->pae_root[i], | |
3251 | &invalid_list); | |
3252 | mmu->pae_root[i] = INVALID_PAE_ROOT; | |
3253 | } | |
08fb59d8 | 3254 | } |
04d45551 | 3255 | mmu->root_hpa = INVALID_PAGE; |
be01e8e2 | 3256 | mmu->root_pgd = 0; |
17ac10ad | 3257 | } |
74b566e6 | 3258 | |
4d710de9 | 3259 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 3260 | write_unlock(&kvm->mmu_lock); |
17ac10ad | 3261 | } |
74b566e6 | 3262 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3263 | |
25b62c62 SC |
3264 | void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3265 | { | |
3266 | unsigned long roots_to_free = 0; | |
3267 | hpa_t root_hpa; | |
3268 | int i; | |
3269 | ||
3270 | /* | |
3271 | * This should not be called while L2 is active, L2 can't invalidate | |
3272 | * _only_ its own roots, e.g. INVVPID unconditionally exits. | |
3273 | */ | |
3274 | WARN_ON_ONCE(mmu->mmu_role.base.guest_mode); | |
3275 | ||
3276 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
3277 | root_hpa = mmu->prev_roots[i].hpa; | |
3278 | if (!VALID_PAGE(root_hpa)) | |
3279 | continue; | |
3280 | ||
3281 | if (!to_shadow_page(root_hpa) || | |
3282 | to_shadow_page(root_hpa)->role.guest_mode) | |
3283 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
3284 | } | |
3285 | ||
3286 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
3287 | } | |
3288 | EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots); | |
3289 | ||
3290 | ||
8986ecc0 MT |
3291 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3292 | { | |
3293 | int ret = 0; | |
3294 | ||
995decb6 | 3295 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3296 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3297 | ret = 1; |
3298 | } | |
3299 | ||
3300 | return ret; | |
3301 | } | |
3302 | ||
8123f265 SC |
3303 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3304 | u8 level, bool direct) | |
651dd37a JR |
3305 | { |
3306 | struct kvm_mmu_page *sp; | |
8123f265 | 3307 | |
8123f265 SC |
3308 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); |
3309 | ++sp->root_count; | |
3310 | ||
8123f265 SC |
3311 | return __pa(sp->spt); |
3312 | } | |
3313 | ||
3314 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3315 | { | |
b37233c9 SC |
3316 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
3317 | u8 shadow_root_level = mmu->shadow_root_level; | |
8123f265 | 3318 | hpa_t root; |
7ebaf15e | 3319 | unsigned i; |
4a38162e PB |
3320 | int r; |
3321 | ||
3322 | write_lock(&vcpu->kvm->mmu_lock); | |
3323 | r = make_mmu_pages_available(vcpu); | |
3324 | if (r < 0) | |
3325 | goto out_unlock; | |
651dd37a | 3326 | |
897218ff | 3327 | if (is_tdp_mmu_enabled(vcpu->kvm)) { |
02c00b3a | 3328 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); |
b37233c9 | 3329 | mmu->root_hpa = root; |
02c00b3a | 3330 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { |
6e6ec584 | 3331 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true); |
b37233c9 | 3332 | mmu->root_hpa = root; |
8123f265 | 3333 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { |
4a38162e PB |
3334 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3335 | r = -EIO; | |
3336 | goto out_unlock; | |
3337 | } | |
73ad1606 | 3338 | |
651dd37a | 3339 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3340 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
651dd37a | 3341 | |
8123f265 SC |
3342 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3343 | i << 30, PT32_ROOT_LEVEL, true); | |
17e368d9 SC |
3344 | mmu->pae_root[i] = root | PT_PRESENT_MASK | |
3345 | shadow_me_mask; | |
651dd37a | 3346 | } |
b37233c9 | 3347 | mmu->root_hpa = __pa(mmu->pae_root); |
73ad1606 SC |
3348 | } else { |
3349 | WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level); | |
4a38162e PB |
3350 | r = -EIO; |
3351 | goto out_unlock; | |
73ad1606 | 3352 | } |
3651c7fc | 3353 | |
be01e8e2 | 3354 | /* root_pgd is ignored for direct MMUs. */ |
b37233c9 | 3355 | mmu->root_pgd = 0; |
4a38162e PB |
3356 | out_unlock: |
3357 | write_unlock(&vcpu->kvm->mmu_lock); | |
3358 | return r; | |
651dd37a JR |
3359 | } |
3360 | ||
3361 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3362 | { |
b37233c9 | 3363 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
6e0918ae | 3364 | u64 pdptrs[4], pm_mask; |
be01e8e2 | 3365 | gfn_t root_gfn, root_pgd; |
8123f265 | 3366 | hpa_t root; |
4a38162e PB |
3367 | unsigned i; |
3368 | int r; | |
3bb65a22 | 3369 | |
b37233c9 | 3370 | root_pgd = mmu->get_guest_pgd(vcpu); |
be01e8e2 | 3371 | root_gfn = root_pgd >> PAGE_SHIFT; |
17ac10ad | 3372 | |
651dd37a JR |
3373 | if (mmu_check_root(vcpu, root_gfn)) |
3374 | return 1; | |
3375 | ||
4a38162e PB |
3376 | /* |
3377 | * On SVM, reading PDPTRs might access guest memory, which might fault | |
3378 | * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock. | |
3379 | */ | |
6e0918ae SC |
3380 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
3381 | for (i = 0; i < 4; ++i) { | |
3382 | pdptrs[i] = mmu->get_pdptr(vcpu, i); | |
3383 | if (!(pdptrs[i] & PT_PRESENT_MASK)) | |
3384 | continue; | |
3385 | ||
3386 | if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT)) | |
3387 | return 1; | |
3388 | } | |
3389 | } | |
3390 | ||
d501f747 BG |
3391 | r = alloc_all_memslots_rmaps(vcpu->kvm); |
3392 | if (r) | |
3393 | return r; | |
3394 | ||
4a38162e PB |
3395 | write_lock(&vcpu->kvm->mmu_lock); |
3396 | r = make_mmu_pages_available(vcpu); | |
3397 | if (r < 0) | |
3398 | goto out_unlock; | |
3399 | ||
651dd37a JR |
3400 | /* |
3401 | * Do we shadow a long mode page table? If so we need to | |
3402 | * write-protect the guests page table root. | |
3403 | */ | |
b37233c9 | 3404 | if (mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3405 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
b37233c9 | 3406 | mmu->shadow_root_level, false); |
b37233c9 | 3407 | mmu->root_hpa = root; |
be01e8e2 | 3408 | goto set_root_pgd; |
17ac10ad | 3409 | } |
f87f9288 | 3410 | |
4a38162e PB |
3411 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3412 | r = -EIO; | |
3413 | goto out_unlock; | |
3414 | } | |
73ad1606 | 3415 | |
651dd37a JR |
3416 | /* |
3417 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3418 | * or a PAE 3-level page table. In either case we need to be aware that |
3419 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3420 | */ |
17e368d9 | 3421 | pm_mask = PT_PRESENT_MASK | shadow_me_mask; |
748e52b9 | 3422 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3423 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3424 | ||
03ca4589 | 3425 | if (WARN_ON_ONCE(!mmu->pml4_root)) { |
4a38162e PB |
3426 | r = -EIO; |
3427 | goto out_unlock; | |
3428 | } | |
73ad1606 | 3429 | |
03ca4589 | 3430 | mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask; |
04d45551 SC |
3431 | } |
3432 | ||
17ac10ad | 3433 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3434 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
6e6ec584 | 3435 | |
b37233c9 | 3436 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
6e0918ae | 3437 | if (!(pdptrs[i] & PT_PRESENT_MASK)) { |
c834e5e4 | 3438 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
417726a3 AK |
3439 | continue; |
3440 | } | |
6e0918ae | 3441 | root_gfn = pdptrs[i] >> PAGE_SHIFT; |
5a7388c2 | 3442 | } |
8facbbff | 3443 | |
8123f265 SC |
3444 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3445 | PT32_ROOT_LEVEL, false); | |
b37233c9 | 3446 | mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3447 | } |
81407ca5 | 3448 | |
ba0a194f | 3449 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
03ca4589 | 3450 | mmu->root_hpa = __pa(mmu->pml4_root); |
ba0a194f SC |
3451 | else |
3452 | mmu->root_hpa = __pa(mmu->pae_root); | |
81407ca5 | 3453 | |
be01e8e2 | 3454 | set_root_pgd: |
b37233c9 | 3455 | mmu->root_pgd = root_pgd; |
4a38162e PB |
3456 | out_unlock: |
3457 | write_unlock(&vcpu->kvm->mmu_lock); | |
ad7dc69a | 3458 | |
8986ecc0 | 3459 | return 0; |
17ac10ad AK |
3460 | } |
3461 | ||
748e52b9 SC |
3462 | static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) |
3463 | { | |
3464 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
03ca4589 | 3465 | u64 *pml4_root, *pae_root; |
81407ca5 JR |
3466 | |
3467 | /* | |
748e52b9 SC |
3468 | * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP |
3469 | * tables are allocated and initialized at root creation as there is no | |
3470 | * equivalent level in the guest's NPT to shadow. Allocate the tables | |
3471 | * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare. | |
81407ca5 | 3472 | */ |
748e52b9 SC |
3473 | if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL || |
3474 | mmu->shadow_root_level < PT64_ROOT_4LEVEL) | |
3475 | return 0; | |
81407ca5 | 3476 | |
748e52b9 SC |
3477 | /* |
3478 | * This mess only works with 4-level paging and needs to be updated to | |
3479 | * work with 5-level paging. | |
3480 | */ | |
3481 | if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) | |
3482 | return -EIO; | |
81407ca5 | 3483 | |
03ca4589 | 3484 | if (mmu->pae_root && mmu->pml4_root) |
748e52b9 | 3485 | return 0; |
81407ca5 | 3486 | |
748e52b9 SC |
3487 | /* |
3488 | * The special roots should always be allocated in concert. Yell and | |
3489 | * bail if KVM ends up in a state where only one of the roots is valid. | |
3490 | */ | |
03ca4589 | 3491 | if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) |
748e52b9 | 3492 | return -EIO; |
81407ca5 | 3493 | |
4a98623d SC |
3494 | /* |
3495 | * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and | |
3496 | * doesn't need to be decrypted. | |
3497 | */ | |
748e52b9 SC |
3498 | pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3499 | if (!pae_root) | |
3500 | return -ENOMEM; | |
81407ca5 | 3501 | |
03ca4589 SC |
3502 | pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3503 | if (!pml4_root) { | |
748e52b9 SC |
3504 | free_page((unsigned long)pae_root); |
3505 | return -ENOMEM; | |
81407ca5 JR |
3506 | } |
3507 | ||
748e52b9 | 3508 | mmu->pae_root = pae_root; |
03ca4589 | 3509 | mmu->pml4_root = pml4_root; |
ad7dc69a | 3510 | |
8986ecc0 | 3511 | return 0; |
17ac10ad AK |
3512 | } |
3513 | ||
578e1c4d | 3514 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3515 | { |
3516 | int i; | |
3517 | struct kvm_mmu_page *sp; | |
3518 | ||
44dd3ffa | 3519 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3520 | return; |
3521 | ||
44dd3ffa | 3522 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3523 | return; |
6903074c | 3524 | |
56f17dd3 | 3525 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3526 | |
44dd3ffa VK |
3527 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3528 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3529 | sp = to_shadow_page(root); |
578e1c4d JS |
3530 | |
3531 | /* | |
3532 | * Even if another CPU was marking the SP as unsync-ed | |
3533 | * simultaneously, any guest page table changes are not | |
3534 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3535 | * flush strictly after those changes are made. We only need to | |
3536 | * ensure that the other CPU sets these flags before any actual | |
3537 | * changes to the page tables are made. The comments in | |
0337f585 SC |
3538 | * mmu_try_to_unsync_pages() describe what could go wrong if |
3539 | * this requirement isn't satisfied. | |
578e1c4d JS |
3540 | */ |
3541 | if (!smp_load_acquire(&sp->unsync) && | |
3542 | !smp_load_acquire(&sp->unsync_children)) | |
3543 | return; | |
3544 | ||
531810ca | 3545 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3546 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3547 | ||
0ba73cda | 3548 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3549 | |
0375f7fa | 3550 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3551 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3552 | return; |
3553 | } | |
578e1c4d | 3554 | |
531810ca | 3555 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3556 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3557 | ||
0ba73cda | 3558 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3559 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3560 | |
c834e5e4 | 3561 | if (IS_VALID_PAE_ROOT(root)) { |
0ba73cda | 3562 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3563 | sp = to_shadow_page(root); |
0ba73cda MT |
3564 | mmu_sync_children(vcpu, sp); |
3565 | } | |
3566 | } | |
0ba73cda | 3567 | |
578e1c4d | 3568 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3569 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3570 | } |
3571 | ||
736c291c | 3572 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3573 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3574 | { |
ab9ae313 AK |
3575 | if (exception) |
3576 | exception->error_code = 0; | |
6aa8b732 AK |
3577 | return vaddr; |
3578 | } | |
3579 | ||
736c291c | 3580 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3581 | u32 access, |
3582 | struct x86_exception *exception) | |
6539e738 | 3583 | { |
ab9ae313 AK |
3584 | if (exception) |
3585 | exception->error_code = 0; | |
54987b7a | 3586 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3587 | } |
3588 | ||
d625b155 XG |
3589 | static bool |
3590 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3591 | { | |
b5c3c1b3 | 3592 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3593 | |
b5c3c1b3 | 3594 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3595 | } |
3596 | ||
b5c3c1b3 | 3597 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3598 | { |
b5c3c1b3 | 3599 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3600 | } |
3601 | ||
ded58749 | 3602 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3603 | { |
9034e6e8 PB |
3604 | /* |
3605 | * A nested guest cannot use the MMIO cache if it is using nested | |
3606 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3607 | */ | |
3608 | if (mmu_is_nested(vcpu)) | |
3609 | return false; | |
3610 | ||
ce88decf XG |
3611 | if (direct) |
3612 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3613 | ||
3614 | return vcpu_match_mmio_gva(vcpu, addr); | |
3615 | } | |
3616 | ||
95fb5b02 BG |
3617 | /* |
3618 | * Return the level of the lowest level SPTE added to sptes. | |
3619 | * That SPTE may be non-present. | |
3620 | */ | |
39b4d43e | 3621 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level) |
ce88decf XG |
3622 | { |
3623 | struct kvm_shadow_walk_iterator iterator; | |
2aa07893 | 3624 | int leaf = -1; |
95fb5b02 | 3625 | u64 spte; |
ce88decf XG |
3626 | |
3627 | walk_shadow_page_lockless_begin(vcpu); | |
47ab8751 | 3628 | |
39b4d43e SC |
3629 | for (shadow_walk_init(&iterator, vcpu, addr), |
3630 | *root_level = iterator.level; | |
47ab8751 XG |
3631 | shadow_walk_okay(&iterator); |
3632 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3633 | leaf = iterator.level; |
47ab8751 XG |
3634 | spte = mmu_spte_get_lockless(iterator.sptep); |
3635 | ||
dde81f94 | 3636 | sptes[leaf] = spte; |
47ab8751 | 3637 | |
ce88decf XG |
3638 | if (!is_shadow_present_pte(spte)) |
3639 | break; | |
95fb5b02 BG |
3640 | } |
3641 | ||
3642 | walk_shadow_page_lockless_end(vcpu); | |
3643 | ||
3644 | return leaf; | |
3645 | } | |
3646 | ||
9aa41879 | 3647 | /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */ |
95fb5b02 BG |
3648 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) |
3649 | { | |
dde81f94 | 3650 | u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; |
95fb5b02 | 3651 | struct rsvd_bits_validate *rsvd_check; |
39b4d43e | 3652 | int root, leaf, level; |
95fb5b02 BG |
3653 | bool reserved = false; |
3654 | ||
63c0cac9 | 3655 | if (is_tdp_mmu(vcpu->arch.mmu)) |
39b4d43e | 3656 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3657 | else |
39b4d43e | 3658 | leaf = get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3659 | |
2aa07893 SC |
3660 | if (unlikely(leaf < 0)) { |
3661 | *sptep = 0ull; | |
3662 | return reserved; | |
3663 | } | |
3664 | ||
9aa41879 SC |
3665 | *sptep = sptes[leaf]; |
3666 | ||
3667 | /* | |
3668 | * Skip reserved bits checks on the terminal leaf if it's not a valid | |
3669 | * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by | |
3670 | * design, always have reserved bits set. The purpose of the checks is | |
3671 | * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs. | |
3672 | */ | |
3673 | if (!is_shadow_present_pte(sptes[leaf])) | |
3674 | leaf++; | |
95fb5b02 BG |
3675 | |
3676 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3677 | ||
9aa41879 | 3678 | for (level = root; level >= leaf; level--) |
b5c3c1b3 SC |
3679 | /* |
3680 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3681 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3682 | * adding a Jcc in the loop. | |
3683 | */ | |
dde81f94 SC |
3684 | reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) | |
3685 | __is_rsvd_bits_set(rsvd_check, sptes[level], level); | |
47ab8751 | 3686 | |
47ab8751 | 3687 | if (reserved) { |
bb4cdf3a | 3688 | pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n", |
47ab8751 | 3689 | __func__, addr); |
95fb5b02 | 3690 | for (level = root; level >= leaf; level--) |
bb4cdf3a SC |
3691 | pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx", |
3692 | sptes[level], level, | |
3693 | rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]); | |
47ab8751 | 3694 | } |
ddce6208 | 3695 | |
47ab8751 | 3696 | return reserved; |
ce88decf XG |
3697 | } |
3698 | ||
e08d26f0 | 3699 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3700 | { |
3701 | u64 spte; | |
47ab8751 | 3702 | bool reserved; |
ce88decf | 3703 | |
ded58749 | 3704 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3705 | return RET_PF_EMULATE; |
ce88decf | 3706 | |
95fb5b02 | 3707 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3708 | if (WARN_ON(reserved)) |
9b8ebbdb | 3709 | return -EINVAL; |
ce88decf XG |
3710 | |
3711 | if (is_mmio_spte(spte)) { | |
3712 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3713 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3714 | |
54bf36aa | 3715 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3716 | return RET_PF_INVALID; |
f8f55942 | 3717 | |
ce88decf XG |
3718 | if (direct) |
3719 | addr = 0; | |
4f022648 XG |
3720 | |
3721 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3722 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3723 | return RET_PF_EMULATE; |
ce88decf XG |
3724 | } |
3725 | ||
ce88decf XG |
3726 | /* |
3727 | * If the page table is zapped by other cpus, let CPU fault again on | |
3728 | * the address. | |
3729 | */ | |
9b8ebbdb | 3730 | return RET_PF_RETRY; |
ce88decf | 3731 | } |
ce88decf | 3732 | |
3d0c27ad XG |
3733 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3734 | u32 error_code, gfn_t gfn) | |
3735 | { | |
3736 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3737 | return false; | |
3738 | ||
3739 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3740 | !(error_code & PFERR_WRITE_MASK)) | |
3741 | return false; | |
3742 | ||
3743 | /* | |
3744 | * guest is writing the page which is write tracked which can | |
3745 | * not be fixed by page fault handler. | |
3746 | */ | |
3747 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3748 | return true; | |
3749 | ||
3750 | return false; | |
3751 | } | |
3752 | ||
e5691a81 XG |
3753 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3754 | { | |
3755 | struct kvm_shadow_walk_iterator iterator; | |
3756 | u64 spte; | |
3757 | ||
e5691a81 XG |
3758 | walk_shadow_page_lockless_begin(vcpu); |
3759 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3760 | clear_sp_write_flooding_count(iterator.sptep); | |
3761 | if (!is_shadow_present_pte(spte)) | |
3762 | break; | |
3763 | } | |
3764 | walk_shadow_page_lockless_end(vcpu); | |
3765 | } | |
3766 | ||
e8c22266 VK |
3767 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3768 | gfn_t gfn) | |
af585b92 GN |
3769 | { |
3770 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3771 | |
7c90705b | 3772 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3773 | arch.gfn = gfn; |
44dd3ffa | 3774 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3775 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3776 | |
9f1a8526 SC |
3777 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3778 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3779 | } |
3780 | ||
78b2c54a | 3781 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
4a42d848 DS |
3782 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva, |
3783 | bool write, bool *writable) | |
af585b92 | 3784 | { |
c36b7150 | 3785 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3786 | bool async; |
3787 | ||
e0c37868 SC |
3788 | /* |
3789 | * Retry the page fault if the gfn hit a memslot that is being deleted | |
3790 | * or moved. This ensures any existing SPTEs for the old memslot will | |
3791 | * be zapped before KVM inserts a new MMIO SPTE for the gfn. | |
3792 | */ | |
3793 | if (slot && (slot->flags & KVM_MEMSLOT_INVALID)) | |
3794 | return true; | |
3795 | ||
c36b7150 PB |
3796 | /* Don't expose private memslots to L2. */ |
3797 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3798 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3799 | *writable = false; |
3a2936de JM |
3800 | return false; |
3801 | } | |
3802 | ||
3520469d | 3803 | async = false; |
4a42d848 DS |
3804 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, |
3805 | write, writable, hva); | |
af585b92 GN |
3806 | if (!async) |
3807 | return false; /* *pfn has correct page already */ | |
3808 | ||
9bc1f09f | 3809 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3810 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3811 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3812 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3813 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3814 | return true; | |
9f1a8526 | 3815 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3816 | return true; |
3817 | } | |
3818 | ||
4a42d848 DS |
3819 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, |
3820 | write, writable, hva); | |
af585b92 GN |
3821 | return false; |
3822 | } | |
3823 | ||
0f90e1c1 SC |
3824 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3825 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3826 | { |
63c0cac9 | 3827 | bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu); |
367fd790 | 3828 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3829 | bool map_writable; |
6aa8b732 | 3830 | |
0f90e1c1 SC |
3831 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3832 | unsigned long mmu_seq; | |
3833 | kvm_pfn_t pfn; | |
4a42d848 | 3834 | hva_t hva; |
83f06fa7 | 3835 | int r; |
ce88decf | 3836 | |
3d0c27ad | 3837 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3838 | return RET_PF_EMULATE; |
ce88decf | 3839 | |
0b873fd7 | 3840 | if (!is_tdp_mmu_fault) { |
bb18842e BG |
3841 | r = fast_page_fault(vcpu, gpa, error_code); |
3842 | if (r != RET_PF_INVALID) | |
3843 | return r; | |
3844 | } | |
83291445 | 3845 | |
378f5cd6 | 3846 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3847 | if (r) |
3848 | return r; | |
714b93da | 3849 | |
367fd790 SC |
3850 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3851 | smp_rmb(); | |
3852 | ||
4a42d848 DS |
3853 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva, |
3854 | write, &map_writable)) | |
367fd790 SC |
3855 | return RET_PF_RETRY; |
3856 | ||
0f90e1c1 | 3857 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3858 | return r; |
6aa8b732 | 3859 | |
367fd790 | 3860 | r = RET_PF_RETRY; |
a2855afc | 3861 | |
0b873fd7 | 3862 | if (is_tdp_mmu_fault) |
a2855afc BG |
3863 | read_lock(&vcpu->kvm->mmu_lock); |
3864 | else | |
3865 | write_lock(&vcpu->kvm->mmu_lock); | |
3866 | ||
4a42d848 | 3867 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
367fd790 | 3868 | goto out_unlock; |
7bd7ded6 SC |
3869 | r = make_mmu_pages_available(vcpu); |
3870 | if (r) | |
367fd790 | 3871 | goto out_unlock; |
bb18842e | 3872 | |
0b873fd7 | 3873 | if (is_tdp_mmu_fault) |
bb18842e BG |
3874 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, |
3875 | pfn, prefault); | |
3876 | else | |
3877 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3878 | prefault, is_tdp); | |
0f90e1c1 | 3879 | |
367fd790 | 3880 | out_unlock: |
0b873fd7 | 3881 | if (is_tdp_mmu_fault) |
a2855afc BG |
3882 | read_unlock(&vcpu->kvm->mmu_lock); |
3883 | else | |
3884 | write_unlock(&vcpu->kvm->mmu_lock); | |
367fd790 SC |
3885 | kvm_release_pfn_clean(pfn); |
3886 | return r; | |
6aa8b732 AK |
3887 | } |
3888 | ||
0f90e1c1 SC |
3889 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3890 | u32 error_code, bool prefault) | |
3891 | { | |
3892 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3893 | ||
3894 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3895 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3896 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3897 | } |
3898 | ||
1261bfa3 | 3899 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3900 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3901 | { |
3902 | int r = 1; | |
9ce372b3 | 3903 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3904 | |
736c291c SC |
3905 | #ifndef CONFIG_X86_64 |
3906 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3907 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3908 | return -EFAULT; | |
3909 | #endif | |
3910 | ||
c595ceee | 3911 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3912 | if (!flags) { |
1261bfa3 WL |
3913 | trace_kvm_page_fault(fault_address, error_code); |
3914 | ||
d0006530 | 3915 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3916 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3917 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3918 | insn_len); | |
9ce372b3 | 3919 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3920 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3921 | local_irq_disable(); |
6bca69ad | 3922 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3923 | local_irq_enable(); |
9ce372b3 VK |
3924 | } else { |
3925 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3926 | } |
9ce372b3 | 3927 | |
1261bfa3 WL |
3928 | return r; |
3929 | } | |
3930 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3931 | ||
7a02674d SC |
3932 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3933 | bool prefault) | |
fb72d167 | 3934 | { |
cb9b88c6 | 3935 | int max_level; |
fb72d167 | 3936 | |
e662ec3e | 3937 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3938 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3939 | max_level--) { |
3940 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3941 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3942 | |
cb9b88c6 SC |
3943 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3944 | break; | |
fd136902 | 3945 | } |
852e3c19 | 3946 | |
0f90e1c1 SC |
3947 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3948 | max_level, true); | |
fb72d167 JR |
3949 | } |
3950 | ||
84a16226 | 3951 | static void nonpaging_init_context(struct kvm_mmu *context) |
6aa8b732 | 3952 | { |
6aa8b732 | 3953 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3954 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3955 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3956 | context->invlpg = NULL; |
cea0f0e7 | 3957 | context->root_level = 0; |
c5a78f2b | 3958 | context->direct_map = true; |
2d48a985 | 3959 | context->nx = false; |
6aa8b732 AK |
3960 | } |
3961 | ||
be01e8e2 | 3962 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3963 | union kvm_mmu_page_role role) |
3964 | { | |
be01e8e2 | 3965 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3966 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3967 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3968 | } |
3969 | ||
b94742c9 | 3970 | /* |
be01e8e2 | 3971 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3972 | * The current root is also inserted into the cache. |
3973 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3974 | * returned. | |
3975 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3976 | * false is returned. This root should now be freed by the caller. | |
3977 | */ | |
be01e8e2 | 3978 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3979 | union kvm_mmu_page_role new_role) |
3980 | { | |
3981 | uint i; | |
3982 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3983 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3984 | |
be01e8e2 | 3985 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3986 | root.hpa = mmu->root_hpa; |
3987 | ||
be01e8e2 | 3988 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3989 | return true; |
3990 | ||
b94742c9 JS |
3991 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3992 | swap(root, mmu->prev_roots[i]); | |
3993 | ||
be01e8e2 | 3994 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3995 | break; |
3996 | } | |
3997 | ||
3998 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3999 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
4000 | |
4001 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4002 | } | |
4003 | ||
be01e8e2 | 4004 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 4005 | union kvm_mmu_page_role new_role) |
6aa8b732 | 4006 | { |
44dd3ffa | 4007 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4008 | |
4009 | /* | |
4010 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4011 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4012 | * later if necessary. | |
4013 | */ | |
4014 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 4015 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 4016 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
4017 | |
4018 | return false; | |
6aa8b732 AK |
4019 | } |
4020 | ||
be01e8e2 | 4021 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b5129100 | 4022 | union kvm_mmu_page_role new_role) |
6aa8b732 | 4023 | { |
be01e8e2 | 4024 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
4025 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
4026 | return; | |
4027 | } | |
4028 | ||
4029 | /* | |
4030 | * It's possible that the cached previous root page is obsolete because | |
4031 | * of a change in the MMU generation number. However, changing the | |
4032 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
4033 | * free the root set here and allocate a new one. | |
4034 | */ | |
4035 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
4036 | ||
b5129100 | 4037 | if (force_flush_and_sync_on_reuse) { |
b869855b SC |
4038 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
4039 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
b5129100 | 4040 | } |
b869855b SC |
4041 | |
4042 | /* | |
4043 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
4044 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
4045 | * valid. So clear any cached MMIO info even when we don't need to sync | |
4046 | * the shadow page tables. | |
4047 | */ | |
4048 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
4049 | ||
daa5b6c1 BG |
4050 | /* |
4051 | * If this is a direct root page, it doesn't have a write flooding | |
4052 | * count. Otherwise, clear the write flooding count. | |
4053 | */ | |
4054 | if (!new_role.direct) | |
4055 | __clear_sp_write_flooding_count( | |
4056 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
4057 | } |
4058 | ||
b5129100 | 4059 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) |
0aab33e4 | 4060 | { |
b5129100 | 4061 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu)); |
0aab33e4 | 4062 | } |
be01e8e2 | 4063 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 4064 | |
5777ed34 JR |
4065 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4066 | { | |
9f8fe504 | 4067 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4068 | } |
4069 | ||
54bf36aa | 4070 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 4071 | unsigned int access, int *nr_present) |
ce88decf XG |
4072 | { |
4073 | if (unlikely(is_mmio_spte(*sptep))) { | |
4074 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4075 | mmu_spte_clear_no_track(sptep); | |
4076 | return true; | |
4077 | } | |
4078 | ||
4079 | (*nr_present)++; | |
54bf36aa | 4080 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4081 | return true; |
4082 | } | |
4083 | ||
4084 | return false; | |
4085 | } | |
4086 | ||
6bb69c9b PB |
4087 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4088 | unsigned level, unsigned gpte) | |
6fd01b71 | 4089 | { |
6bb69c9b PB |
4090 | /* |
4091 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4092 | * If it is clear, there are no large pages at this level, so clear | |
4093 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4094 | */ | |
4095 | gpte &= level - mmu->last_nonleaf_level; | |
4096 | ||
829ee279 | 4097 | /* |
3bae0459 SC |
4098 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set |
4099 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
4100 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
829ee279 | 4101 | */ |
3bae0459 | 4102 | gpte |= level - PG_LEVEL_4K - 1; |
829ee279 | 4103 | |
6bb69c9b | 4104 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4105 | } |
4106 | ||
37406aaa NHE |
4107 | #define PTTYPE_EPT 18 /* arbitrary */ |
4108 | #define PTTYPE PTTYPE_EPT | |
4109 | #include "paging_tmpl.h" | |
4110 | #undef PTTYPE | |
4111 | ||
6aa8b732 AK |
4112 | #define PTTYPE 64 |
4113 | #include "paging_tmpl.h" | |
4114 | #undef PTTYPE | |
4115 | ||
4116 | #define PTTYPE 32 | |
4117 | #include "paging_tmpl.h" | |
4118 | #undef PTTYPE | |
4119 | ||
6dc98b86 | 4120 | static void |
b705a277 | 4121 | __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check, |
5b7f575c | 4122 | u64 pa_bits_rsvd, int level, bool nx, bool gbpages, |
6fec2144 | 4123 | bool pse, bool amd) |
82725b20 | 4124 | { |
5f7dde7b | 4125 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4126 | u64 nonleaf_bit8_rsvd = 0; |
5b7f575c | 4127 | u64 high_bits_rsvd; |
82725b20 | 4128 | |
a0a64f50 | 4129 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4130 | |
6dc98b86 | 4131 | if (!gbpages) |
5f7dde7b | 4132 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 | 4133 | |
5b7f575c SC |
4134 | if (level == PT32E_ROOT_LEVEL) |
4135 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62); | |
4136 | else | |
4137 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); | |
4138 | ||
4139 | /* Note, NX doesn't exist in PDPTEs, this is handled below. */ | |
4140 | if (!nx) | |
4141 | high_bits_rsvd |= rsvd_bits(63, 63); | |
4142 | ||
a0c0feb5 PB |
4143 | /* |
4144 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4145 | * leaf entries) on AMD CPUs only. | |
4146 | */ | |
6fec2144 | 4147 | if (amd) |
a0c0feb5 PB |
4148 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4149 | ||
6dc98b86 | 4150 | switch (level) { |
82725b20 DE |
4151 | case PT32_ROOT_LEVEL: |
4152 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4153 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4154 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4155 | rsvd_check->rsvd_bits_mask[1][0] = | |
4156 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4157 | |
6dc98b86 | 4158 | if (!pse) { |
a0a64f50 | 4159 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4160 | break; |
4161 | } | |
4162 | ||
82725b20 DE |
4163 | if (is_cpuid_PSE36()) |
4164 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4165 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4166 | else |
4167 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4168 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4169 | break; |
4170 | case PT32E_ROOT_LEVEL: | |
5b7f575c SC |
4171 | rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) | |
4172 | high_bits_rsvd | | |
4173 | rsvd_bits(5, 8) | | |
4174 | rsvd_bits(1, 2); /* PDPTE */ | |
4175 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */ | |
4176 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */ | |
4177 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4178 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4179 | rsvd_check->rsvd_bits_mask[1][0] = |
4180 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4181 | break; |
855feb67 | 4182 | case PT64_ROOT_5LEVEL: |
5b7f575c SC |
4183 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | |
4184 | nonleaf_bit8_rsvd | | |
4185 | rsvd_bits(7, 7); | |
855feb67 YZ |
4186 | rsvd_check->rsvd_bits_mask[1][4] = |
4187 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4188 | fallthrough; |
2a7266a8 | 4189 | case PT64_ROOT_4LEVEL: |
5b7f575c SC |
4190 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | |
4191 | nonleaf_bit8_rsvd | | |
4192 | rsvd_bits(7, 7); | |
4193 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | | |
4194 | gbpages_bit_rsvd; | |
4195 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; | |
4196 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
a0a64f50 XG |
4197 | rsvd_check->rsvd_bits_mask[1][3] = |
4198 | rsvd_check->rsvd_bits_mask[0][3]; | |
5b7f575c SC |
4199 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | |
4200 | gbpages_bit_rsvd | | |
4201 | rsvd_bits(13, 29); | |
4202 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4203 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4204 | rsvd_check->rsvd_bits_mask[1][0] = |
4205 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4206 | break; |
4207 | } | |
4208 | } | |
4209 | ||
6dc98b86 XG |
4210 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4211 | struct kvm_mmu *context) | |
4212 | { | |
b705a277 | 4213 | __reset_rsvds_bits_mask(&context->guest_rsvd_check, |
5b7f575c SC |
4214 | vcpu->arch.reserved_gpa_bits, |
4215 | context->root_level, context->nx, | |
d6321d49 | 4216 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4e9c0d80 | 4217 | is_cr4_pse(context), |
23493d0a | 4218 | guest_cpuid_is_amd_or_hygon(vcpu)); |
6dc98b86 XG |
4219 | } |
4220 | ||
81b8eebb XG |
4221 | static void |
4222 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4223 | u64 pa_bits_rsvd, bool execonly) |
25d92081 | 4224 | { |
5b7f575c | 4225 | u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); |
951f9fd7 | 4226 | u64 bad_mt_xwr; |
25d92081 | 4227 | |
5b7f575c SC |
4228 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7); |
4229 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7); | |
4230 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6); | |
4231 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6); | |
4232 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
25d92081 YZ |
4233 | |
4234 | /* large page */ | |
855feb67 | 4235 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 | 4236 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
5b7f575c SC |
4237 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29); |
4238 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20); | |
a0a64f50 | 4239 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4240 | |
951f9fd7 PB |
4241 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4242 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4243 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4244 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4245 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4246 | if (!execonly) { | |
4247 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4248 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4249 | } |
951f9fd7 | 4250 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4251 | } |
4252 | ||
81b8eebb XG |
4253 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4254 | struct kvm_mmu *context, bool execonly) | |
4255 | { | |
4256 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
5b7f575c | 4257 | vcpu->arch.reserved_gpa_bits, execonly); |
81b8eebb XG |
4258 | } |
4259 | ||
6f8e65a6 SC |
4260 | static inline u64 reserved_hpa_bits(void) |
4261 | { | |
4262 | return rsvd_bits(shadow_phys_bits, 63); | |
4263 | } | |
4264 | ||
c258b62b XG |
4265 | /* |
4266 | * the page table on host is the shadow page table for the page | |
4267 | * table in guest or amd nested guest, its mmu features completely | |
4268 | * follow the features in guest. | |
4269 | */ | |
16be1d12 SC |
4270 | static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, |
4271 | struct kvm_mmu *context) | |
c258b62b | 4272 | { |
112022bd SC |
4273 | /* |
4274 | * KVM uses NX when TDP is disabled to handle a variety of scenarios, | |
4275 | * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and | |
4276 | * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0. | |
4277 | * The iTLB multi-hit workaround can be toggled at any time, so assume | |
4278 | * NX can be used by any non-nested shadow MMU to avoid having to reset | |
4279 | * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled. | |
4280 | */ | |
18feaad3 | 4281 | bool uses_nx = context->nx || !tdp_enabled; |
8c985b2d SC |
4282 | |
4283 | /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */ | |
4284 | bool is_amd = true; | |
4285 | /* KVM doesn't use 2-level page tables for the shadow MMU. */ | |
4286 | bool is_pse = false; | |
ea2800dd BS |
4287 | struct rsvd_bits_validate *shadow_zero_check; |
4288 | int i; | |
5f0b8199 | 4289 | |
8c985b2d SC |
4290 | WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL); |
4291 | ||
ea2800dd | 4292 | shadow_zero_check = &context->shadow_zero_check; |
b705a277 | 4293 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
5f0b8199 | 4294 | context->shadow_root_level, uses_nx, |
d6321d49 | 4295 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
8c985b2d | 4296 | is_pse, is_amd); |
ea2800dd BS |
4297 | |
4298 | if (!shadow_me_mask) | |
4299 | return; | |
4300 | ||
4301 | for (i = context->shadow_root_level; --i >= 0;) { | |
4302 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4303 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4304 | } | |
4305 | ||
c258b62b | 4306 | } |
c258b62b | 4307 | |
6fec2144 PB |
4308 | static inline bool boot_cpu_is_amd(void) |
4309 | { | |
4310 | WARN_ON_ONCE(!tdp_enabled); | |
4311 | return shadow_x_mask == 0; | |
4312 | } | |
4313 | ||
c258b62b XG |
4314 | /* |
4315 | * the direct page table on host, use as much mmu features as | |
4316 | * possible, however, kvm currently does not do execution-protection. | |
4317 | */ | |
4318 | static void | |
4319 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4320 | struct kvm_mmu *context) | |
4321 | { | |
ea2800dd BS |
4322 | struct rsvd_bits_validate *shadow_zero_check; |
4323 | int i; | |
4324 | ||
4325 | shadow_zero_check = &context->shadow_zero_check; | |
4326 | ||
6fec2144 | 4327 | if (boot_cpu_is_amd()) |
b705a277 | 4328 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
c258b62b | 4329 | context->shadow_root_level, false, |
b8291adc | 4330 | boot_cpu_has(X86_FEATURE_GBPAGES), |
8c985b2d | 4331 | false, true); |
c258b62b | 4332 | else |
ea2800dd | 4333 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
6f8e65a6 | 4334 | reserved_hpa_bits(), false); |
c258b62b | 4335 | |
ea2800dd BS |
4336 | if (!shadow_me_mask) |
4337 | return; | |
4338 | ||
4339 | for (i = context->shadow_root_level; --i >= 0;) { | |
4340 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4341 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4342 | } | |
c258b62b XG |
4343 | } |
4344 | ||
4345 | /* | |
4346 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4347 | * is the shadow page table for intel nested guest. | |
4348 | */ | |
4349 | static void | |
4350 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4351 | struct kvm_mmu *context, bool execonly) | |
4352 | { | |
4353 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
6f8e65a6 | 4354 | reserved_hpa_bits(), execonly); |
c258b62b XG |
4355 | } |
4356 | ||
09f037aa PB |
4357 | #define BYTE_MASK(access) \ |
4358 | ((1 & (access) ? 2 : 0) | \ | |
4359 | (2 & (access) ? 4 : 0) | \ | |
4360 | (3 & (access) ? 8 : 0) | \ | |
4361 | (4 & (access) ? 16 : 0) | \ | |
4362 | (5 & (access) ? 32 : 0) | \ | |
4363 | (6 & (access) ? 64 : 0) | \ | |
4364 | (7 & (access) ? 128 : 0)) | |
4365 | ||
4366 | ||
c596f147 | 4367 | static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept) |
97d64b78 | 4368 | { |
09f037aa PB |
4369 | unsigned byte; |
4370 | ||
4371 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4372 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4373 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4374 | ||
c596f147 SC |
4375 | bool cr4_smep = is_cr4_smep(mmu); |
4376 | bool cr4_smap = is_cr4_smap(mmu); | |
4377 | bool cr0_wp = is_cr0_wp(mmu); | |
97d64b78 | 4378 | |
97d64b78 | 4379 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4380 | unsigned pfec = byte << 1; |
4381 | ||
97ec8c06 | 4382 | /* |
09f037aa PB |
4383 | * Each "*f" variable has a 1 bit for each UWX value |
4384 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4385 | */ |
97d64b78 | 4386 | |
09f037aa | 4387 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4388 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4389 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4390 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4391 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4392 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4393 | /* Faults from kernel mode fetches of user pages */ |
4394 | u8 smepf = 0; | |
4395 | /* Faults from kernel mode accesses of user pages */ | |
4396 | u8 smapf = 0; | |
4397 | ||
4398 | if (!ept) { | |
4399 | /* Faults from kernel mode accesses to user pages */ | |
4400 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4401 | ||
4402 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4403 | if (!mmu->nx) | |
4404 | ff = 0; | |
4405 | ||
4406 | /* Allow supervisor writes if !cr0.wp */ | |
4407 | if (!cr0_wp) | |
4408 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4409 | ||
4410 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4411 | if (cr4_smep) | |
4412 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4413 | ||
4414 | /* | |
4415 | * SMAP:kernel-mode data accesses from user-mode | |
4416 | * mappings should fault. A fault is considered | |
4417 | * as a SMAP violation if all of the following | |
39337ad1 | 4418 | * conditions are true: |
09f037aa PB |
4419 | * - X86_CR4_SMAP is set in CR4 |
4420 | * - A user page is accessed | |
4421 | * - The access is not a fetch | |
4422 | * - Page fault in kernel mode | |
4423 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4424 | * | |
4425 | * Here, we cover the first three conditions. | |
4426 | * The fourth is computed dynamically in permission_fault(); | |
4427 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4428 | * *not* subject to SMAP restrictions. | |
4429 | */ | |
4430 | if (cr4_smap) | |
4431 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4432 | } |
09f037aa PB |
4433 | |
4434 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4435 | } |
4436 | } | |
4437 | ||
2d344105 HH |
4438 | /* |
4439 | * PKU is an additional mechanism by which the paging controls access to | |
4440 | * user-mode addresses based on the value in the PKRU register. Protection | |
4441 | * key violations are reported through a bit in the page fault error code. | |
4442 | * Unlike other bits of the error code, the PK bit is not known at the | |
4443 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4444 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4445 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4446 | * | |
4447 | * In particular the following conditions come from the error code, the | |
4448 | * page tables and the machine state: | |
4449 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4450 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4451 | * - PK is always zero if U=0 in the page tables | |
4452 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4453 | * | |
4454 | * The PKRU bitmask caches the result of these four conditions. The error | |
4455 | * code (minus the P bit) and the page table's U bit form an index into the | |
4456 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4457 | * with the two bits of the PKRU register corresponding to the protection key. | |
4458 | * For the first three conditions above the bits will be 00, thus masking | |
4459 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4460 | * only will be masked away. | |
4461 | */ | |
2e4c0661 | 4462 | static void update_pkru_bitmask(struct kvm_mmu *mmu) |
2d344105 HH |
4463 | { |
4464 | unsigned bit; | |
4465 | bool wp; | |
4466 | ||
2e4c0661 | 4467 | if (!is_cr4_pke(mmu)) { |
2d344105 HH |
4468 | mmu->pkru_mask = 0; |
4469 | return; | |
4470 | } | |
4471 | ||
2e4c0661 | 4472 | wp = is_cr0_wp(mmu); |
2d344105 HH |
4473 | |
4474 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4475 | unsigned pfec, pkey_bits; | |
4476 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4477 | ||
4478 | pfec = bit << 1; | |
4479 | ff = pfec & PFERR_FETCH_MASK; | |
4480 | uf = pfec & PFERR_USER_MASK; | |
4481 | wf = pfec & PFERR_WRITE_MASK; | |
4482 | ||
4483 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4484 | pte_user = pfec & PFERR_RSVD_MASK; | |
4485 | ||
4486 | /* | |
4487 | * Only need to check the access which is not an | |
4488 | * instruction fetch and is to a user page. | |
4489 | */ | |
4490 | check_pkey = (!ff && pte_user); | |
4491 | /* | |
4492 | * write access is controlled by PKRU if it is a | |
4493 | * user access or CR0.WP = 1. | |
4494 | */ | |
4495 | check_write = check_pkey && wf && (uf || wp); | |
4496 | ||
4497 | /* PKRU.AD stops both read and write access. */ | |
4498 | pkey_bits = !!check_pkey; | |
4499 | /* PKRU.WD stops write access. */ | |
4500 | pkey_bits |= (!!check_write) << 1; | |
4501 | ||
4502 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4503 | } | |
4504 | } | |
4505 | ||
b67a93a8 | 4506 | static void update_last_nonleaf_level(struct kvm_mmu *mmu) |
6fd01b71 | 4507 | { |
6bb69c9b PB |
4508 | unsigned root_level = mmu->root_level; |
4509 | ||
4510 | mmu->last_nonleaf_level = root_level; | |
b67a93a8 | 4511 | if (root_level == PT32_ROOT_LEVEL && is_cr4_pse(mmu)) |
6bb69c9b | 4512 | mmu->last_nonleaf_level++; |
6fd01b71 AK |
4513 | } |
4514 | ||
84a16226 | 4515 | static void paging64_init_context_common(struct kvm_mmu *context, |
d555f705 | 4516 | int root_level) |
6aa8b732 | 4517 | { |
84a16226 | 4518 | context->nx = is_efer_nx(context); |
d555f705 | 4519 | context->root_level = root_level; |
2d48a985 | 4520 | |
84a16226 | 4521 | WARN_ON_ONCE(!is_cr4_pae(context)); |
6aa8b732 | 4522 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4523 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4524 | context->sync_page = paging64_sync_page; |
a7052897 | 4525 | context->invlpg = paging64_invlpg; |
c5a78f2b | 4526 | context->direct_map = false; |
6aa8b732 AK |
4527 | } |
4528 | ||
84a16226 SC |
4529 | static void paging64_init_context(struct kvm_mmu *context, |
4530 | struct kvm_mmu_role_regs *regs) | |
17ac10ad | 4531 | { |
84a16226 SC |
4532 | int root_level = ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL : |
4533 | PT64_ROOT_4LEVEL; | |
855feb67 | 4534 | |
84a16226 | 4535 | paging64_init_context_common(context, root_level); |
17ac10ad AK |
4536 | } |
4537 | ||
84a16226 | 4538 | static void paging32_init_context(struct kvm_mmu *context) |
6aa8b732 | 4539 | { |
2d48a985 | 4540 | context->nx = false; |
4d6931c3 | 4541 | context->root_level = PT32_ROOT_LEVEL; |
6aa8b732 | 4542 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4543 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4544 | context->sync_page = paging32_sync_page; |
a7052897 | 4545 | context->invlpg = paging32_invlpg; |
c5a78f2b | 4546 | context->direct_map = false; |
6aa8b732 AK |
4547 | } |
4548 | ||
84a16226 | 4549 | static void paging32E_init_context(struct kvm_mmu *context) |
6aa8b732 | 4550 | { |
84a16226 | 4551 | paging64_init_context_common(context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4552 | } |
4553 | ||
8626c120 SC |
4554 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu, |
4555 | struct kvm_mmu_role_regs *regs) | |
a336282d VK |
4556 | { |
4557 | union kvm_mmu_extended_role ext = {0}; | |
4558 | ||
ca8d664f SC |
4559 | if (____is_cr0_pg(regs)) { |
4560 | ext.cr0_pg = 1; | |
4561 | ext.cr4_pae = ____is_cr4_pae(regs); | |
4562 | ext.cr4_smep = ____is_cr4_smep(regs); | |
4563 | ext.cr4_smap = ____is_cr4_smap(regs); | |
4564 | ext.cr4_pse = ____is_cr4_pse(regs); | |
84c679f5 SC |
4565 | |
4566 | /* PKEY and LA57 are active iff long mode is active. */ | |
4567 | ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs); | |
4568 | ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs); | |
ca8d664f | 4569 | } |
a336282d VK |
4570 | |
4571 | ext.valid = 1; | |
4572 | ||
4573 | return ext; | |
4574 | } | |
4575 | ||
7dcd5755 | 4576 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
8626c120 | 4577 | struct kvm_mmu_role_regs *regs, |
7dcd5755 VK |
4578 | bool base_only) |
4579 | { | |
4580 | union kvm_mmu_role role = {0}; | |
4581 | ||
4582 | role.base.access = ACC_ALL; | |
ca8d664f SC |
4583 | if (____is_cr0_pg(regs)) { |
4584 | role.base.efer_nx = ____is_efer_nx(regs); | |
4585 | role.base.cr0_wp = ____is_cr0_wp(regs); | |
4586 | } | |
7dcd5755 VK |
4587 | role.base.smm = is_smm(vcpu); |
4588 | role.base.guest_mode = is_guest_mode(vcpu); | |
4589 | ||
4590 | if (base_only) | |
4591 | return role; | |
4592 | ||
8626c120 | 4593 | role.ext = kvm_calc_mmu_role_ext(vcpu, regs); |
7dcd5755 VK |
4594 | |
4595 | return role; | |
4596 | } | |
4597 | ||
d468d94b SC |
4598 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4599 | { | |
4600 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4601 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4602 | return 4; |
4603 | ||
83013059 | 4604 | return max_tdp_level; |
d468d94b SC |
4605 | } |
4606 | ||
7dcd5755 | 4607 | static union kvm_mmu_role |
8626c120 SC |
4608 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4609 | struct kvm_mmu_role_regs *regs, bool base_only) | |
9fa72119 | 4610 | { |
8626c120 | 4611 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
9fa72119 | 4612 | |
7dcd5755 | 4613 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4614 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4615 | role.base.direct = true; |
47c42e6b | 4616 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4617 | |
4618 | return role; | |
4619 | } | |
4620 | ||
8a3c1a33 | 4621 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4622 | { |
8c008659 | 4623 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
8626c120 | 4624 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 | 4625 | union kvm_mmu_role new_role = |
8626c120 | 4626 | kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false); |
fb72d167 | 4627 | |
7dcd5755 VK |
4628 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4629 | return; | |
4630 | ||
4631 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4632 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4633 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4634 | context->invlpg = NULL; |
d468d94b | 4635 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4636 | context->direct_map = true; |
d8dd54e0 | 4637 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4638 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4639 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4640 | |
4641 | if (!is_paging(vcpu)) { | |
2d48a985 | 4642 | context->nx = false; |
fb72d167 JR |
4643 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4644 | context->root_level = 0; | |
4645 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4646 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4647 | context->root_level = is_la57_mode(vcpu) ? |
4648 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4649 | reset_rsvds_bits_mask(vcpu, context); |
4650 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4651 | } else if (is_pae(vcpu)) { |
2d48a985 | 4652 | context->nx = is_nx(vcpu); |
fb72d167 | 4653 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4654 | reset_rsvds_bits_mask(vcpu, context); |
4655 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4656 | } else { |
2d48a985 | 4657 | context->nx = false; |
fb72d167 | 4658 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4659 | reset_rsvds_bits_mask(vcpu, context); |
4660 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4661 | } |
4662 | ||
c596f147 | 4663 | update_permission_bitmask(context, false); |
2e4c0661 | 4664 | update_pkru_bitmask(context); |
b67a93a8 | 4665 | update_last_nonleaf_level(context); |
c258b62b | 4666 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4667 | } |
4668 | ||
7dcd5755 | 4669 | static union kvm_mmu_role |
8626c120 SC |
4670 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, |
4671 | struct kvm_mmu_role_regs *regs, bool base_only) | |
7dcd5755 | 4672 | { |
8626c120 | 4673 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
7dcd5755 | 4674 | |
8626c120 SC |
4675 | role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs); |
4676 | role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs); | |
ca8d664f | 4677 | role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs); |
9fa72119 | 4678 | |
59505b55 SC |
4679 | return role; |
4680 | } | |
4681 | ||
4682 | static union kvm_mmu_role | |
8626c120 SC |
4683 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4684 | struct kvm_mmu_role_regs *regs, bool base_only) | |
59505b55 SC |
4685 | { |
4686 | union kvm_mmu_role role = | |
8626c120 | 4687 | kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only); |
59505b55 | 4688 | |
8626c120 | 4689 | role.base.direct = !____is_cr0_pg(regs); |
59505b55 | 4690 | |
8626c120 | 4691 | if (!____is_efer_lma(regs)) |
7dcd5755 | 4692 | role.base.level = PT32E_ROOT_LEVEL; |
8626c120 | 4693 | else if (____is_cr4_la57(regs)) |
7dcd5755 | 4694 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4695 | else |
7dcd5755 | 4696 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4697 | |
4698 | return role; | |
4699 | } | |
4700 | ||
8c008659 | 4701 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
594e91a1 SC |
4702 | struct kvm_mmu_role_regs *regs, |
4703 | union kvm_mmu_role new_role) | |
9fa72119 | 4704 | { |
18db1b17 SC |
4705 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4706 | return; | |
4707 | ||
4708 | context->mmu_role.as_u64 = new_role.as_u64; | |
4709 | ||
594e91a1 | 4710 | if (!____is_cr0_pg(regs)) |
84a16226 | 4711 | nonpaging_init_context(context); |
594e91a1 | 4712 | else if (____is_efer_lma(regs)) |
84a16226 | 4713 | paging64_init_context(context, regs); |
594e91a1 | 4714 | else if (____is_cr4_pae(regs)) |
84a16226 | 4715 | paging32E_init_context(context); |
6aa8b732 | 4716 | else |
84a16226 | 4717 | paging32_init_context(context); |
a770f6f2 | 4718 | |
af098972 SC |
4719 | if (____is_cr0_pg(regs)) { |
4720 | reset_rsvds_bits_mask(vcpu, context); | |
c596f147 | 4721 | update_permission_bitmask(context, false); |
2e4c0661 | 4722 | update_pkru_bitmask(context); |
b67a93a8 | 4723 | update_last_nonleaf_level(context); |
af098972 | 4724 | } |
d555f705 SC |
4725 | context->shadow_root_level = new_role.base.level; |
4726 | ||
c258b62b | 4727 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4728 | } |
0f04a2ac | 4729 | |
594e91a1 SC |
4730 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, |
4731 | struct kvm_mmu_role_regs *regs) | |
0f04a2ac | 4732 | { |
8c008659 | 4733 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac | 4734 | union kvm_mmu_role new_role = |
8626c120 | 4735 | kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false); |
0f04a2ac | 4736 | |
18db1b17 | 4737 | shadow_mmu_init_context(vcpu, context, regs, new_role); |
0f04a2ac VK |
4738 | } |
4739 | ||
59505b55 | 4740 | static union kvm_mmu_role |
8626c120 SC |
4741 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu, |
4742 | struct kvm_mmu_role_regs *regs) | |
59505b55 SC |
4743 | { |
4744 | union kvm_mmu_role role = | |
8626c120 | 4745 | kvm_calc_shadow_root_page_role_common(vcpu, regs, false); |
59505b55 SC |
4746 | |
4747 | role.base.direct = false; | |
d468d94b | 4748 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4749 | |
4750 | return role; | |
4751 | } | |
4752 | ||
dbc4739b SC |
4753 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, |
4754 | unsigned long cr4, u64 efer, gpa_t nested_cr3) | |
0f04a2ac | 4755 | { |
8c008659 | 4756 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
594e91a1 SC |
4757 | struct kvm_mmu_role_regs regs = { |
4758 | .cr0 = cr0, | |
4759 | .cr4 = cr4, | |
4760 | .efer = efer, | |
4761 | }; | |
8626c120 SC |
4762 | union kvm_mmu_role new_role; |
4763 | ||
4764 | new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s); | |
0f04a2ac | 4765 | |
b5129100 | 4766 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base); |
a506fdd2 | 4767 | |
18db1b17 | 4768 | shadow_mmu_init_context(vcpu, context, ®s, new_role); |
a3322d5c | 4769 | |
16be1d12 SC |
4770 | /* |
4771 | * Redo the shadow bits, the reset done by shadow_mmu_init_context() | |
4772 | * (above) may use the wrong shadow_root_level. | |
4773 | */ | |
4774 | reset_shadow_zero_bits_mask(vcpu, context); | |
0f04a2ac VK |
4775 | } |
4776 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4777 | |
a336282d VK |
4778 | static union kvm_mmu_role |
4779 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4780 | bool execonly, u8 level) |
9fa72119 | 4781 | { |
552c69b1 | 4782 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4783 | |
47c42e6b SC |
4784 | /* SMM flag is inherited from root_mmu */ |
4785 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4786 | |
bb1fcc70 | 4787 | role.base.level = level; |
47c42e6b | 4788 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4789 | role.base.direct = false; |
4790 | role.base.ad_disabled = !accessed_dirty; | |
4791 | role.base.guest_mode = true; | |
4792 | role.base.access = ACC_ALL; | |
9fa72119 | 4793 | |
cd6767c3 SC |
4794 | /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */ |
4795 | role.ext.word = 0; | |
a336282d | 4796 | role.ext.execonly = execonly; |
cd6767c3 | 4797 | role.ext.valid = 1; |
9fa72119 JS |
4798 | |
4799 | return role; | |
4800 | } | |
4801 | ||
ae1e2d10 | 4802 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4803 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4804 | { |
8c008659 | 4805 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4806 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4807 | union kvm_mmu_role new_role = |
4808 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4809 | execonly, level); |
a336282d | 4810 | |
b5129100 | 4811 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base); |
a336282d | 4812 | |
a336282d VK |
4813 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4814 | return; | |
ad896af0 | 4815 | |
18db1b17 SC |
4816 | context->mmu_role.as_u64 = new_role.as_u64; |
4817 | ||
bb1fcc70 | 4818 | context->shadow_root_level = level; |
155a97a3 NHE |
4819 | |
4820 | context->nx = true; | |
ae1e2d10 | 4821 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4822 | context->page_fault = ept_page_fault; |
4823 | context->gva_to_gpa = ept_gva_to_gpa; | |
4824 | context->sync_page = ept_sync_page; | |
4825 | context->invlpg = ept_invlpg; | |
bb1fcc70 | 4826 | context->root_level = level; |
155a97a3 | 4827 | context->direct_map = false; |
3dc773e7 | 4828 | |
c596f147 | 4829 | update_permission_bitmask(context, true); |
b67a93a8 | 4830 | update_last_nonleaf_level(context); |
2e4c0661 | 4831 | update_pkru_bitmask(context); |
155a97a3 | 4832 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4833 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4834 | } |
4835 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4836 | ||
8a3c1a33 | 4837 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4838 | { |
8c008659 | 4839 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
594e91a1 | 4840 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
ad896af0 | 4841 | |
594e91a1 | 4842 | kvm_init_shadow_mmu(vcpu, ®s); |
929d1cfa | 4843 | |
d8dd54e0 | 4844 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4845 | context->get_pdptr = kvm_pdptr_read; |
4846 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4847 | } |
4848 | ||
8626c120 SC |
4849 | static union kvm_mmu_role |
4850 | kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs) | |
654430ef | 4851 | { |
8626c120 SC |
4852 | union kvm_mmu_role role; |
4853 | ||
4854 | role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false); | |
654430ef SC |
4855 | |
4856 | /* | |
4857 | * Nested MMUs are used only for walking L2's gva->gpa, they never have | |
4858 | * shadow pages of their own and so "direct" has no meaning. Set it | |
4859 | * to "true" to try to detect bogus usage of the nested MMU. | |
4860 | */ | |
4861 | role.base.direct = true; | |
4862 | ||
8626c120 | 4863 | if (!____is_cr0_pg(regs)) |
654430ef | 4864 | role.base.level = 0; |
8626c120 SC |
4865 | else if (____is_efer_lma(regs)) |
4866 | role.base.level = ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL : | |
4867 | PT64_ROOT_4LEVEL; | |
4868 | else if (____is_cr4_pae(regs)) | |
654430ef SC |
4869 | role.base.level = PT32E_ROOT_LEVEL; |
4870 | else | |
4871 | role.base.level = PT32_ROOT_LEVEL; | |
4872 | ||
4873 | return role; | |
4874 | } | |
4875 | ||
8a3c1a33 | 4876 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4877 | { |
8626c120 SC |
4878 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
4879 | union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s); | |
02f59dc9 JR |
4880 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4881 | ||
bf627a92 VK |
4882 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4883 | return; | |
4884 | ||
4885 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4886 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4887 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4888 | g_context->inject_page_fault = kvm_inject_page_fault; |
4889 | ||
5efac074 PB |
4890 | /* |
4891 | * L2 page tables are never shadowed, so there is no need to sync | |
4892 | * SPTEs. | |
4893 | */ | |
4894 | g_context->invlpg = NULL; | |
4895 | ||
02f59dc9 | 4896 | /* |
44dd3ffa | 4897 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4898 | * L1's nested page tables (e.g. EPT12). The nested translation |
4899 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4900 | * L2's page tables as the first level of translation and L1's | |
4901 | * nested page tables as the second level of translation. Basically | |
4902 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4903 | */ |
4904 | if (!is_paging(vcpu)) { | |
2d48a985 | 4905 | g_context->nx = false; |
02f59dc9 JR |
4906 | g_context->root_level = 0; |
4907 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4908 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4909 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4910 | g_context->root_level = is_la57_mode(vcpu) ? |
4911 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4912 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4913 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4914 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4915 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4916 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4917 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4918 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4919 | } else { | |
2d48a985 | 4920 | g_context->nx = false; |
02f59dc9 | 4921 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4922 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4923 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4924 | } | |
4925 | ||
c596f147 | 4926 | update_permission_bitmask(g_context, false); |
2e4c0661 | 4927 | update_pkru_bitmask(g_context); |
b67a93a8 | 4928 | update_last_nonleaf_level(g_context); |
02f59dc9 JR |
4929 | } |
4930 | ||
c9060662 | 4931 | void kvm_init_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4932 | { |
02f59dc9 | 4933 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4934 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4935 | else if (tdp_enabled) |
e0c6db3e | 4936 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4937 | else |
e0c6db3e | 4938 | init_kvm_softmmu(vcpu); |
fb72d167 | 4939 | } |
1c53da3f | 4940 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4941 | |
9fa72119 JS |
4942 | static union kvm_mmu_page_role |
4943 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4944 | { | |
8626c120 | 4945 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 VK |
4946 | union kvm_mmu_role role; |
4947 | ||
9fa72119 | 4948 | if (tdp_enabled) |
8626c120 | 4949 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true); |
9fa72119 | 4950 | else |
8626c120 | 4951 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true); |
7dcd5755 VK |
4952 | |
4953 | return role.base; | |
9fa72119 | 4954 | } |
fb72d167 | 4955 | |
49c6f875 SC |
4956 | void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu) |
4957 | { | |
4958 | /* | |
4959 | * Invalidate all MMU roles to force them to reinitialize as CPUID | |
4960 | * information is factored into reserved bit calculations. | |
4961 | */ | |
4962 | vcpu->arch.root_mmu.mmu_role.ext.valid = 0; | |
4963 | vcpu->arch.guest_mmu.mmu_role.ext.valid = 0; | |
4964 | vcpu->arch.nested_mmu.mmu_role.ext.valid = 0; | |
4965 | kvm_mmu_reset_context(vcpu); | |
63f5a190 SC |
4966 | |
4967 | /* | |
4968 | * KVM does not correctly handle changing guest CPUID after KVM_RUN, as | |
4969 | * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't | |
4970 | * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page | |
4971 | * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise | |
4972 | * sweep the problem under the rug. | |
4973 | * | |
4974 | * KVM's horrific CPUID ABI makes the problem all but impossible to | |
4975 | * solve, as correctly handling multiple vCPU models (with respect to | |
4976 | * paging and physical address properties) in a single VM would require | |
4977 | * tracking all relevant CPUID information in kvm_mmu_page_role. That | |
4978 | * is very undesirable as it would double the memory requirements for | |
4979 | * gfn_track (see struct kvm_mmu_page_role comments), and in practice | |
4980 | * no sane VMM mucks with the core vCPU model on the fly. | |
4981 | */ | |
4982 | if (vcpu->arch.last_vmentry_cpu != -1) { | |
4983 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n"); | |
4984 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n"); | |
4985 | } | |
49c6f875 SC |
4986 | } |
4987 | ||
8a3c1a33 | 4988 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4989 | { |
95f93af4 | 4990 | kvm_mmu_unload(vcpu); |
c9060662 | 4991 | kvm_init_mmu(vcpu); |
17c3ba9d | 4992 | } |
8668a3c4 | 4993 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4994 | |
4995 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4996 | { |
714b93da AK |
4997 | int r; |
4998 | ||
378f5cd6 | 4999 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
5000 | if (r) |
5001 | goto out; | |
748e52b9 | 5002 | r = mmu_alloc_special_roots(vcpu); |
17c3ba9d AK |
5003 | if (r) |
5004 | goto out; | |
4a38162e | 5005 | if (vcpu->arch.mmu->direct_map) |
6e6ec584 SC |
5006 | r = mmu_alloc_direct_roots(vcpu); |
5007 | else | |
5008 | r = mmu_alloc_shadow_roots(vcpu); | |
8986ecc0 MT |
5009 | if (r) |
5010 | goto out; | |
a91f387b SC |
5011 | |
5012 | kvm_mmu_sync_roots(vcpu); | |
5013 | ||
727a7e27 | 5014 | kvm_mmu_load_pgd(vcpu); |
b3646477 | 5015 | static_call(kvm_x86_tlb_flush_current)(vcpu); |
714b93da AK |
5016 | out: |
5017 | return r; | |
6aa8b732 | 5018 | } |
17c3ba9d AK |
5019 | |
5020 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5021 | { | |
14c07ad8 VK |
5022 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5023 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5024 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5025 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5026 | } |
6aa8b732 | 5027 | |
79539cec AK |
5028 | static bool need_remote_flush(u64 old, u64 new) |
5029 | { | |
5030 | if (!is_shadow_present_pte(old)) | |
5031 | return false; | |
5032 | if (!is_shadow_present_pte(new)) | |
5033 | return true; | |
5034 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5035 | return true; | |
53166229 GN |
5036 | old ^= shadow_nx_mask; |
5037 | new ^= shadow_nx_mask; | |
79539cec AK |
5038 | return (old & ~new & PT64_PERM_MASK) != 0; |
5039 | } | |
5040 | ||
889e5cbc | 5041 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5042 | int *bytes) |
da4a00f0 | 5043 | { |
0e0fee5c | 5044 | u64 gentry = 0; |
889e5cbc | 5045 | int r; |
72016f3a | 5046 | |
72016f3a AK |
5047 | /* |
5048 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5049 | * as the current vcpu paging mode since we update the sptes only |
5050 | * when they have the same mode. | |
72016f3a | 5051 | */ |
889e5cbc | 5052 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5053 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5054 | *gpa &= ~(gpa_t)7; |
5055 | *bytes = 8; | |
08e850c6 AK |
5056 | } |
5057 | ||
0e0fee5c JS |
5058 | if (*bytes == 4 || *bytes == 8) { |
5059 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5060 | if (r) | |
5061 | gentry = 0; | |
72016f3a AK |
5062 | } |
5063 | ||
889e5cbc XG |
5064 | return gentry; |
5065 | } | |
5066 | ||
5067 | /* | |
5068 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5069 | * or we may be forking, in which case it is better to unmap the page. | |
5070 | */ | |
a138fe75 | 5071 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5072 | { |
a30f47cb XG |
5073 | /* |
5074 | * Skip write-flooding detected for the sp whose level is 1, because | |
5075 | * it can become unsync, then the guest page is not write-protected. | |
5076 | */ | |
3bae0459 | 5077 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 5078 | return false; |
3246af0e | 5079 | |
e5691a81 XG |
5080 | atomic_inc(&sp->write_flooding_count); |
5081 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5082 | } |
5083 | ||
5084 | /* | |
5085 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5086 | * indicate a page is not used as a page table. | |
5087 | */ | |
5088 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5089 | int bytes) | |
5090 | { | |
5091 | unsigned offset, pte_size, misaligned; | |
5092 | ||
5093 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5094 | gpa, bytes, sp->role.word); | |
5095 | ||
5096 | offset = offset_in_page(gpa); | |
47c42e6b | 5097 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5098 | |
5099 | /* | |
5100 | * Sometimes, the OS only writes the last one bytes to update status | |
5101 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5102 | */ | |
5103 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5104 | return false; | |
5105 | ||
889e5cbc XG |
5106 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5107 | misaligned |= bytes < 4; | |
5108 | ||
5109 | return misaligned; | |
5110 | } | |
5111 | ||
5112 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5113 | { | |
5114 | unsigned page_offset, quadrant; | |
5115 | u64 *spte; | |
5116 | int level; | |
5117 | ||
5118 | page_offset = offset_in_page(gpa); | |
5119 | level = sp->role.level; | |
5120 | *nspte = 1; | |
47c42e6b | 5121 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5122 | page_offset <<= 1; /* 32->64 */ |
5123 | /* | |
5124 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5125 | * only 2MB. So we need to double the offset again | |
5126 | * and zap two pdes instead of one. | |
5127 | */ | |
5128 | if (level == PT32_ROOT_LEVEL) { | |
5129 | page_offset &= ~7; /* kill rounding error */ | |
5130 | page_offset <<= 1; | |
5131 | *nspte = 2; | |
5132 | } | |
5133 | quadrant = page_offset >> PAGE_SHIFT; | |
5134 | page_offset &= ~PAGE_MASK; | |
5135 | if (quadrant != sp->role.quadrant) | |
5136 | return NULL; | |
5137 | } | |
5138 | ||
5139 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5140 | return spte; | |
5141 | } | |
5142 | ||
13d268ca | 5143 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5144 | const u8 *new, int bytes, |
5145 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5146 | { |
5147 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5148 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5149 | LIST_HEAD(invalid_list); |
5150 | u64 entry, gentry, *spte; | |
5151 | int npte; | |
b8c67b7a | 5152 | bool remote_flush, local_flush; |
889e5cbc XG |
5153 | |
5154 | /* | |
5155 | * If we don't have indirect shadow pages, it means no page is | |
5156 | * write-protected, so we can exit simply. | |
5157 | */ | |
6aa7de05 | 5158 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5159 | return; |
5160 | ||
b8c67b7a | 5161 | remote_flush = local_flush = false; |
889e5cbc XG |
5162 | |
5163 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5164 | ||
889e5cbc XG |
5165 | /* |
5166 | * No need to care whether allocation memory is successful | |
d9f6e12f | 5167 | * or not since pte prefetch is skipped if it does not have |
889e5cbc XG |
5168 | * enough objects in the cache. |
5169 | */ | |
378f5cd6 | 5170 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc | 5171 | |
531810ca | 5172 | write_lock(&vcpu->kvm->mmu_lock); |
0e0fee5c JS |
5173 | |
5174 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5175 | ||
889e5cbc | 5176 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5177 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5178 | |
b67bfe0d | 5179 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5180 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5181 | detect_write_flooding(sp)) { |
b8c67b7a | 5182 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5183 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5184 | continue; |
5185 | } | |
889e5cbc XG |
5186 | |
5187 | spte = get_written_sptes(sp, gpa, &npte); | |
5188 | if (!spte) | |
5189 | continue; | |
5190 | ||
0671a8e7 | 5191 | local_flush = true; |
ac1b714e | 5192 | while (npte--) { |
79539cec | 5193 | entry = *spte; |
2de4085c | 5194 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
c5e2184d SC |
5195 | if (gentry && sp->role.level != PG_LEVEL_4K) |
5196 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
9bb4f6b1 | 5197 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5198 | remote_flush = true; |
ac1b714e | 5199 | ++spte; |
9b7a0325 | 5200 | } |
9b7a0325 | 5201 | } |
b8c67b7a | 5202 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5203 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
531810ca | 5204 | write_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5205 | } |
5206 | ||
736c291c | 5207 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5208 | void *insn, int insn_len) |
3067714c | 5209 | { |
92daa48b | 5210 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5211 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5212 | |
6948199a | 5213 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5214 | return RET_PF_RETRY; |
5215 | ||
9b8ebbdb | 5216 | r = RET_PF_INVALID; |
e9ee956e | 5217 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5218 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5219 | if (r == RET_PF_EMULATE) |
e9ee956e | 5220 | goto emulate; |
e9ee956e | 5221 | } |
3067714c | 5222 | |
9b8ebbdb | 5223 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5224 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5225 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5226 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5227 | return -EIO; | |
9b8ebbdb PB |
5228 | } |
5229 | ||
3067714c | 5230 | if (r < 0) |
e9ee956e | 5231 | return r; |
83a2ba4c SC |
5232 | if (r != RET_PF_EMULATE) |
5233 | return 1; | |
3067714c | 5234 | |
14727754 TL |
5235 | /* |
5236 | * Before emulating the instruction, check if the error code | |
5237 | * was due to a RO violation while translating the guest page. | |
5238 | * This can occur when using nested virtualization with nested | |
5239 | * paging in both guests. If true, we simply unprotect the page | |
5240 | * and resume the guest. | |
14727754 | 5241 | */ |
44dd3ffa | 5242 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5243 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5244 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5245 | return 1; |
5246 | } | |
5247 | ||
472faffa SC |
5248 | /* |
5249 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5250 | * optimistically try to just unprotect the page and let the processor | |
5251 | * re-execute the instruction that caused the page fault. Do not allow | |
5252 | * retrying MMIO emulation, as it's not only pointless but could also | |
5253 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5254 | * faulting on the non-existent MMIO address. Retrying an instruction |
5255 | * from a nested guest is also pointless and dangerous as we are only | |
5256 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5257 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5258 | */ |
736c291c | 5259 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5260 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5261 | emulate: |
736c291c | 5262 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5263 | insn_len); |
3067714c AK |
5264 | } |
5265 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5266 | ||
5efac074 PB |
5267 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5268 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5269 | { |
b94742c9 | 5270 | int i; |
7eb77e9f | 5271 | |
5efac074 PB |
5272 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5273 | if (mmu != &vcpu->arch.guest_mmu) { | |
5274 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5275 | if (is_noncanonical_address(gva, vcpu)) | |
5276 | return; | |
5277 | ||
b3646477 | 5278 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
5efac074 PB |
5279 | } |
5280 | ||
5281 | if (!mmu->invlpg) | |
faff8758 JS |
5282 | return; |
5283 | ||
5efac074 PB |
5284 | if (root_hpa == INVALID_PAGE) { |
5285 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5286 | |
5efac074 PB |
5287 | /* |
5288 | * INVLPG is required to invalidate any global mappings for the VA, | |
5289 | * irrespective of PCID. Since it would take us roughly similar amount | |
5290 | * of work to determine whether any of the prev_root mappings of the VA | |
5291 | * is marked global, or to just sync it blindly, so we might as well | |
5292 | * just always sync it. | |
5293 | * | |
5294 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5295 | * synced when switching to that cr3, so nothing needs to be done here | |
5296 | * for them. | |
5297 | */ | |
5298 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5299 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5300 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5301 | } else { | |
5302 | mmu->invlpg(vcpu, gva, root_hpa); | |
5303 | } | |
5304 | } | |
956bf353 | 5305 | |
5efac074 PB |
5306 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5307 | { | |
5308 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5309 | ++vcpu->stat.invlpg; |
5310 | } | |
5311 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5312 | ||
5efac074 | 5313 | |
eb4b248e JS |
5314 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5315 | { | |
44dd3ffa | 5316 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5317 | bool tlb_flush = false; |
b94742c9 | 5318 | uint i; |
eb4b248e JS |
5319 | |
5320 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5321 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5322 | tlb_flush = true; |
eb4b248e JS |
5323 | } |
5324 | ||
b94742c9 JS |
5325 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5326 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5327 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5328 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5329 | tlb_flush = true; | |
5330 | } | |
956bf353 | 5331 | } |
ade61e28 | 5332 | |
faff8758 | 5333 | if (tlb_flush) |
b3646477 | 5334 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
faff8758 | 5335 | |
eb4b248e JS |
5336 | ++vcpu->stat.invlpg; |
5337 | ||
5338 | /* | |
b94742c9 JS |
5339 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5340 | * synced when switching to that cr3, so nothing needs to be done here | |
5341 | * for them. | |
eb4b248e JS |
5342 | */ |
5343 | } | |
eb4b248e | 5344 | |
83013059 SC |
5345 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5346 | int tdp_huge_page_level) | |
18552672 | 5347 | { |
bde77235 | 5348 | tdp_enabled = enable_tdp; |
83013059 | 5349 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5350 | |
5351 | /* | |
1d92d2e8 | 5352 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5353 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5354 | * the kernel is not. But, KVM never creates a page size greater than | |
5355 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5356 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5357 | */ | |
5358 | if (tdp_enabled) | |
1d92d2e8 | 5359 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5360 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5361 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5362 | else |
1d92d2e8 | 5363 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5364 | } |
bde77235 | 5365 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5366 | |
5367 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
0a234f5d SC |
5368 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
5369 | struct kvm_memory_slot *slot); | |
85875a13 SC |
5370 | |
5371 | /* The caller should hold mmu-lock before calling this function. */ | |
5372 | static __always_inline bool | |
5373 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5374 | slot_level_handler fn, int start_level, int end_level, | |
1a61b7db SC |
5375 | gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield, |
5376 | bool flush) | |
85875a13 SC |
5377 | { |
5378 | struct slot_rmap_walk_iterator iterator; | |
85875a13 SC |
5379 | |
5380 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5381 | end_gfn, &iterator) { | |
5382 | if (iterator.rmap) | |
0a234f5d | 5383 | flush |= fn(kvm, iterator.rmap, memslot); |
85875a13 | 5384 | |
531810ca | 5385 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
302695a5 | 5386 | if (flush && flush_on_yield) { |
f285c633 BG |
5387 | kvm_flush_remote_tlbs_with_address(kvm, |
5388 | start_gfn, | |
5389 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5390 | flush = false; |
5391 | } | |
531810ca | 5392 | cond_resched_rwlock_write(&kvm->mmu_lock); |
85875a13 SC |
5393 | } |
5394 | } | |
5395 | ||
85875a13 SC |
5396 | return flush; |
5397 | } | |
5398 | ||
5399 | static __always_inline bool | |
5400 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5401 | slot_level_handler fn, int start_level, int end_level, | |
302695a5 | 5402 | bool flush_on_yield) |
85875a13 SC |
5403 | { |
5404 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5405 | end_level, memslot->base_gfn, | |
5406 | memslot->base_gfn + memslot->npages - 1, | |
1a61b7db | 5407 | flush_on_yield, false); |
85875a13 SC |
5408 | } |
5409 | ||
85875a13 SC |
5410 | static __always_inline bool |
5411 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
302695a5 | 5412 | slot_level_handler fn, bool flush_on_yield) |
85875a13 | 5413 | { |
3bae0459 | 5414 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
302695a5 | 5415 | PG_LEVEL_4K, flush_on_yield); |
85875a13 SC |
5416 | } |
5417 | ||
1cfff4d9 | 5418 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5419 | { |
4a98623d SC |
5420 | if (!tdp_enabled && mmu->pae_root) |
5421 | set_memory_encrypted((unsigned long)mmu->pae_root, 1); | |
1cfff4d9 | 5422 | free_page((unsigned long)mmu->pae_root); |
03ca4589 | 5423 | free_page((unsigned long)mmu->pml4_root); |
6aa8b732 AK |
5424 | } |
5425 | ||
04d28e37 | 5426 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5427 | { |
17ac10ad | 5428 | struct page *page; |
6aa8b732 AK |
5429 | int i; |
5430 | ||
04d28e37 SC |
5431 | mmu->root_hpa = INVALID_PAGE; |
5432 | mmu->root_pgd = 0; | |
5433 | mmu->translate_gpa = translate_gpa; | |
5434 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5435 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5436 | ||
17ac10ad | 5437 | /* |
b6b80c78 SC |
5438 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5439 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5440 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5441 | * x86_64. Therefore we need to allocate the PDP table in the first | |
04d45551 SC |
5442 | * 4GB of memory, which happens to fit the DMA32 zone. TDP paging |
5443 | * generally doesn't use PAE paging and can skip allocating the PDP | |
5444 | * table. The main exception, handled here, is SVM's 32-bit NPT. The | |
5445 | * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit | |
5446 | * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). | |
17ac10ad | 5447 | */ |
d468d94b | 5448 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5449 | return 0; |
5450 | ||
254272ce | 5451 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5452 | if (!page) |
d7fa6ab2 WY |
5453 | return -ENOMEM; |
5454 | ||
1cfff4d9 | 5455 | mmu->pae_root = page_address(page); |
4a98623d SC |
5456 | |
5457 | /* | |
5458 | * CR3 is only 32 bits when PAE paging is used, thus it's impossible to | |
5459 | * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so | |
5460 | * that KVM's writes and the CPU's reads get along. Note, this is | |
5461 | * only necessary when using shadow paging, as 64-bit NPT can get at | |
5462 | * the C-bit even when shadowing 32-bit NPT, and SME isn't supported | |
5463 | * by 32-bit kernels (when KVM itself uses 32-bit NPT). | |
5464 | */ | |
5465 | if (!tdp_enabled) | |
5466 | set_memory_decrypted((unsigned long)mmu->pae_root, 1); | |
5467 | else | |
5468 | WARN_ON_ONCE(shadow_me_mask); | |
5469 | ||
17ac10ad | 5470 | for (i = 0; i < 4; ++i) |
c834e5e4 | 5471 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
17ac10ad | 5472 | |
6aa8b732 | 5473 | return 0; |
6aa8b732 AK |
5474 | } |
5475 | ||
8018c27b | 5476 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5477 | { |
1cfff4d9 | 5478 | int ret; |
b94742c9 | 5479 | |
5962bfb7 | 5480 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5481 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5482 | ||
5962bfb7 | 5483 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5484 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5485 | |
96880883 SC |
5486 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5487 | ||
44dd3ffa VK |
5488 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5489 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5490 | |
14c07ad8 | 5491 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5492 | |
04d28e37 | 5493 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5494 | if (ret) |
5495 | return ret; | |
5496 | ||
04d28e37 | 5497 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5498 | if (ret) |
5499 | goto fail_allocate_root; | |
5500 | ||
5501 | return ret; | |
5502 | fail_allocate_root: | |
5503 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5504 | return ret; | |
6aa8b732 AK |
5505 | } |
5506 | ||
fbb158cb | 5507 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5508 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5509 | { | |
5510 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5511 | int nr_zapped, batch = 0; |
002c5f73 SC |
5512 | |
5513 | restart: | |
5514 | list_for_each_entry_safe_reverse(sp, node, | |
5515 | &kvm->arch.active_mmu_pages, link) { | |
5516 | /* | |
5517 | * No obsolete valid page exists before a newly created page | |
5518 | * since active_mmu_pages is a FIFO list. | |
5519 | */ | |
5520 | if (!is_obsolete_sp(kvm, sp)) | |
5521 | break; | |
5522 | ||
5523 | /* | |
f95eec9b SC |
5524 | * Invalid pages should never land back on the list of active |
5525 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5526 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5527 | */ |
f95eec9b | 5528 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5529 | continue; |
5530 | ||
4506ecf4 SC |
5531 | /* |
5532 | * No need to flush the TLB since we're only zapping shadow | |
5533 | * pages with an obsolete generation number and all vCPUS have | |
5534 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5535 | * be in active use by the guest. | |
5536 | */ | |
fbb158cb | 5537 | if (batch >= BATCH_ZAP_PAGES && |
531810ca | 5538 | cond_resched_rwlock_write(&kvm->mmu_lock)) { |
fbb158cb | 5539 | batch = 0; |
002c5f73 SC |
5540 | goto restart; |
5541 | } | |
5542 | ||
10605204 SC |
5543 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5544 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5545 | batch += nr_zapped; |
002c5f73 | 5546 | goto restart; |
fbb158cb | 5547 | } |
002c5f73 SC |
5548 | } |
5549 | ||
4506ecf4 SC |
5550 | /* |
5551 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5552 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5553 | * may reference the pages. | |
5554 | */ | |
10605204 | 5555 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5556 | } |
5557 | ||
5558 | /* | |
5559 | * Fast invalidate all shadow pages and use lock-break technique | |
5560 | * to zap obsolete pages. | |
5561 | * | |
5562 | * It's required when memslot is being deleted or VM is being | |
5563 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5564 | * not use any resource of the being-deleted slot or all slots | |
5565 | * after calling the function. | |
5566 | */ | |
5567 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5568 | { | |
ca333add SC |
5569 | lockdep_assert_held(&kvm->slots_lock); |
5570 | ||
531810ca | 5571 | write_lock(&kvm->mmu_lock); |
14a3c4f4 | 5572 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5573 | |
5574 | /* | |
5575 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5576 | * held for the entire duration of zapping obsolete pages, it's | |
5577 | * impossible for there to be multiple invalid generations associated | |
5578 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5579 | * one valid generation and (at most) one invalid generation. | |
5580 | */ | |
5581 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5582 | |
b7cccd39 BG |
5583 | /* In order to ensure all threads see this change when |
5584 | * handling the MMU reload signal, this must happen in the | |
5585 | * same critical section as kvm_reload_remote_mmus, and | |
5586 | * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages | |
5587 | * could drop the MMU lock and yield. | |
5588 | */ | |
5589 | if (is_tdp_mmu_enabled(kvm)) | |
5590 | kvm_tdp_mmu_invalidate_all_roots(kvm); | |
5591 | ||
4506ecf4 SC |
5592 | /* |
5593 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5594 | * Then all vcpus will switch to new shadow page table with the new | |
5595 | * mmu_valid_gen. | |
5596 | * | |
5597 | * Note: we need to do this under the protection of mmu_lock, | |
5598 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5599 | */ | |
5600 | kvm_reload_remote_mmus(kvm); | |
5601 | ||
002c5f73 | 5602 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 | 5603 | |
531810ca | 5604 | write_unlock(&kvm->mmu_lock); |
4c6654bd BG |
5605 | |
5606 | if (is_tdp_mmu_enabled(kvm)) { | |
5607 | read_lock(&kvm->mmu_lock); | |
5608 | kvm_tdp_mmu_zap_invalidated_roots(kvm); | |
5609 | read_unlock(&kvm->mmu_lock); | |
5610 | } | |
002c5f73 SC |
5611 | } |
5612 | ||
10605204 SC |
5613 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5614 | { | |
5615 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5616 | } | |
5617 | ||
b5f5fdca | 5618 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5619 | struct kvm_memory_slot *slot, |
5620 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5621 | { |
002c5f73 | 5622 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5623 | } |
5624 | ||
13d268ca | 5625 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5626 | { |
13d268ca | 5627 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5628 | |
d501f747 BG |
5629 | if (!kvm_mmu_init_tdp_mmu(kvm)) |
5630 | /* | |
5631 | * No smp_load/store wrappers needed here as we are in | |
5632 | * VM init and there cannot be any memslots / other threads | |
5633 | * accessing this struct kvm yet. | |
5634 | */ | |
5635 | kvm->arch.memslots_have_rmaps = true; | |
a2557408 | 5636 | |
13d268ca | 5637 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5638 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5639 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5640 | } |
5641 | ||
13d268ca | 5642 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5643 | { |
13d268ca | 5644 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5645 | |
13d268ca | 5646 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5647 | |
5648 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5649 | } |
5650 | ||
efdfe536 XG |
5651 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5652 | { | |
5653 | struct kvm_memslots *slots; | |
5654 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5655 | int i; |
1a61b7db | 5656 | bool flush = false; |
efdfe536 | 5657 | |
e2209710 BG |
5658 | if (kvm_memslots_have_rmaps(kvm)) { |
5659 | write_lock(&kvm->mmu_lock); | |
5660 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { | |
5661 | slots = __kvm_memslots(kvm, i); | |
5662 | kvm_for_each_memslot(memslot, slots) { | |
5663 | gfn_t start, end; | |
5664 | ||
5665 | start = max(gfn_start, memslot->base_gfn); | |
5666 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5667 | if (start >= end) | |
5668 | continue; | |
efdfe536 | 5669 | |
e2209710 BG |
5670 | flush = slot_handle_level_range(kvm, memslot, |
5671 | kvm_zap_rmapp, PG_LEVEL_4K, | |
5672 | KVM_MAX_HUGEPAGE_LEVEL, start, | |
5673 | end - 1, true, flush); | |
5674 | } | |
9da0e4d5 | 5675 | } |
e2209710 BG |
5676 | if (flush) |
5677 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end); | |
5678 | write_unlock(&kvm->mmu_lock); | |
efdfe536 XG |
5679 | } |
5680 | ||
897218ff | 5681 | if (is_tdp_mmu_enabled(kvm)) { |
6103bc07 BG |
5682 | flush = false; |
5683 | ||
5684 | read_lock(&kvm->mmu_lock); | |
5685 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) | |
5686 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start, | |
5687 | gfn_end, flush, true); | |
faaf05b0 | 5688 | if (flush) |
6103bc07 BG |
5689 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, |
5690 | gfn_end); | |
faaf05b0 | 5691 | |
6103bc07 BG |
5692 | read_unlock(&kvm->mmu_lock); |
5693 | } | |
efdfe536 XG |
5694 | } |
5695 | ||
018aabb5 | 5696 | static bool slot_rmap_write_protect(struct kvm *kvm, |
0a234f5d SC |
5697 | struct kvm_rmap_head *rmap_head, |
5698 | struct kvm_memory_slot *slot) | |
d77aa73c | 5699 | { |
018aabb5 | 5700 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5701 | } |
5702 | ||
1c91cad4 | 5703 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5704 | struct kvm_memory_slot *memslot, |
5705 | int start_level) | |
6aa8b732 | 5706 | { |
e2209710 | 5707 | bool flush = false; |
6aa8b732 | 5708 | |
e2209710 BG |
5709 | if (kvm_memslots_have_rmaps(kvm)) { |
5710 | write_lock(&kvm->mmu_lock); | |
5711 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, | |
5712 | start_level, KVM_MAX_HUGEPAGE_LEVEL, | |
5713 | false); | |
5714 | write_unlock(&kvm->mmu_lock); | |
5715 | } | |
198c74f4 | 5716 | |
24ae4cfa BG |
5717 | if (is_tdp_mmu_enabled(kvm)) { |
5718 | read_lock(&kvm->mmu_lock); | |
5719 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level); | |
5720 | read_unlock(&kvm->mmu_lock); | |
5721 | } | |
5722 | ||
198c74f4 XG |
5723 | /* |
5724 | * We can flush all the TLBs out of the mmu lock without TLB | |
5725 | * corruption since we just change the spte from writable to | |
5726 | * readonly so that we only need to care the case of changing | |
5727 | * spte from present to present (changing the spte from present | |
5728 | * to nonpresent will flush all the TLBs immediately), in other | |
5729 | * words, the only case we care is mmu_spte_update() where we | |
5fc3424f SC |
5730 | * have checked Host-writable | MMU-writable instead of |
5731 | * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK | |
5732 | * anymore. | |
198c74f4 | 5733 | */ |
d91ffee9 | 5734 | if (flush) |
7f42aa76 | 5735 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5736 | } |
37a7d8b0 | 5737 | |
3ea3b7fa | 5738 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
0a234f5d SC |
5739 | struct kvm_rmap_head *rmap_head, |
5740 | struct kvm_memory_slot *slot) | |
3ea3b7fa WL |
5741 | { |
5742 | u64 *sptep; | |
5743 | struct rmap_iterator iter; | |
5744 | int need_tlb_flush = 0; | |
ba049e93 | 5745 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5746 | struct kvm_mmu_page *sp; |
5747 | ||
0d536790 | 5748 | restart: |
018aabb5 | 5749 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5750 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5751 | pfn = spte_to_pfn(*sptep); |
5752 | ||
5753 | /* | |
decf6333 XG |
5754 | * We cannot do huge page mapping for indirect shadow pages, |
5755 | * which are found on the last rmap (level = 1) when not using | |
5756 | * tdp; such shadow pages are synced with the page table in | |
5757 | * the guest, and the guest page table is using 4K page size | |
5758 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5759 | */ |
a78986aa | 5760 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
9eba50f8 SC |
5761 | sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn, |
5762 | pfn, PG_LEVEL_NUM)) { | |
e7912386 | 5763 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5764 | |
5765 | if (kvm_available_flush_tlb_with_range()) | |
5766 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5767 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5768 | else | |
5769 | need_tlb_flush = 1; | |
5770 | ||
0d536790 XG |
5771 | goto restart; |
5772 | } | |
3ea3b7fa WL |
5773 | } |
5774 | ||
5775 | return need_tlb_flush; | |
5776 | } | |
5777 | ||
5778 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5779 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5780 | { |
f36f3f28 | 5781 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
9eba50f8 | 5782 | struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot; |
31c65657 | 5783 | bool flush = false; |
9eba50f8 | 5784 | |
e2209710 BG |
5785 | if (kvm_memslots_have_rmaps(kvm)) { |
5786 | write_lock(&kvm->mmu_lock); | |
5787 | flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true); | |
5788 | if (flush) | |
5789 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5790 | write_unlock(&kvm->mmu_lock); | |
5791 | } | |
2db6f772 BG |
5792 | |
5793 | if (is_tdp_mmu_enabled(kvm)) { | |
2db6f772 BG |
5794 | read_lock(&kvm->mmu_lock); |
5795 | flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush); | |
5796 | if (flush) | |
5797 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5798 | read_unlock(&kvm->mmu_lock); | |
5799 | } | |
3ea3b7fa WL |
5800 | } |
5801 | ||
b3594ffb | 5802 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
6c9dd6d2 | 5803 | const struct kvm_memory_slot *memslot) |
b3594ffb SC |
5804 | { |
5805 | /* | |
7f42aa76 | 5806 | * All current use cases for flushing the TLBs for a specific memslot |
302695a5 | 5807 | * related to dirty logging, and many do the TLB flush out of mmu_lock. |
7f42aa76 SC |
5808 | * The interaction between the various operations on memslot must be |
5809 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5810 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5811 | */ |
5812 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5813 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5814 | memslot->npages); | |
b3594ffb SC |
5815 | } |
5816 | ||
f4b4b180 KH |
5817 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5818 | struct kvm_memory_slot *memslot) | |
5819 | { | |
e2209710 | 5820 | bool flush = false; |
f4b4b180 | 5821 | |
e2209710 BG |
5822 | if (kvm_memslots_have_rmaps(kvm)) { |
5823 | write_lock(&kvm->mmu_lock); | |
5824 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, | |
5825 | false); | |
5826 | write_unlock(&kvm->mmu_lock); | |
5827 | } | |
f4b4b180 | 5828 | |
24ae4cfa BG |
5829 | if (is_tdp_mmu_enabled(kvm)) { |
5830 | read_lock(&kvm->mmu_lock); | |
5831 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); | |
5832 | read_unlock(&kvm->mmu_lock); | |
5833 | } | |
5834 | ||
f4b4b180 KH |
5835 | /* |
5836 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5837 | * function is only used for dirty logging, in which case flushing TLB | |
5838 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5839 | * dirty_bitmap. | |
5840 | */ | |
5841 | if (flush) | |
7f42aa76 | 5842 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 | 5843 | } |
f4b4b180 | 5844 | |
92f58b5c | 5845 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5846 | { |
5847 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5848 | LIST_HEAD(invalid_list); |
83cdb568 | 5849 | int ign; |
5304b8d3 | 5850 | |
531810ca | 5851 | write_lock(&kvm->mmu_lock); |
5304b8d3 | 5852 | restart: |
8a674adc | 5853 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5854 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5855 | continue; |
92f58b5c | 5856 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5857 | goto restart; |
531810ca | 5858 | if (cond_resched_rwlock_write(&kvm->mmu_lock)) |
5304b8d3 XG |
5859 | goto restart; |
5860 | } | |
5861 | ||
4771450c | 5862 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 | 5863 | |
897218ff | 5864 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5865 | kvm_tdp_mmu_zap_all(kvm); |
5866 | ||
531810ca | 5867 | write_unlock(&kvm->mmu_lock); |
5304b8d3 XG |
5868 | } |
5869 | ||
15248258 | 5870 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5871 | { |
164bf7e5 | 5872 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5873 | |
164bf7e5 | 5874 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5875 | |
f8f55942 | 5876 | /* |
e1359e2b SC |
5877 | * Generation numbers are incremented in multiples of the number of |
5878 | * address spaces in order to provide unique generations across all | |
5879 | * address spaces. Strip what is effectively the address space | |
5880 | * modifier prior to checking for a wrap of the MMIO generation so | |
5881 | * that a wrap in any address space is detected. | |
5882 | */ | |
5883 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5884 | ||
f8f55942 | 5885 | /* |
e1359e2b | 5886 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5887 | * zap all shadow pages. |
f8f55942 | 5888 | */ |
e1359e2b | 5889 | if (unlikely(gen == 0)) { |
ae0f5499 | 5890 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5891 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5892 | } |
f8f55942 XG |
5893 | } |
5894 | ||
70534a73 DC |
5895 | static unsigned long |
5896 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5897 | { |
5898 | struct kvm *kvm; | |
1495f230 | 5899 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5900 | unsigned long freed = 0; |
3ee16c81 | 5901 | |
0d9ce162 | 5902 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5903 | |
5904 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5905 | int idx; |
d98ba053 | 5906 | LIST_HEAD(invalid_list); |
3ee16c81 | 5907 | |
35f2d16b TY |
5908 | /* |
5909 | * Never scan more than sc->nr_to_scan VM instances. | |
5910 | * Will not hit this condition practically since we do not try | |
5911 | * to shrink more than one VM and it is very unlikely to see | |
5912 | * !n_used_mmu_pages so many times. | |
5913 | */ | |
5914 | if (!nr_to_scan--) | |
5915 | break; | |
19526396 GN |
5916 | /* |
5917 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5918 | * here. We may skip a VM instance errorneosly, but we do not | |
5919 | * want to shrink a VM that only started to populate its MMU | |
5920 | * anyway. | |
5921 | */ | |
10605204 SC |
5922 | if (!kvm->arch.n_used_mmu_pages && |
5923 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5924 | continue; |
19526396 | 5925 | |
f656ce01 | 5926 | idx = srcu_read_lock(&kvm->srcu); |
531810ca | 5927 | write_lock(&kvm->mmu_lock); |
3ee16c81 | 5928 | |
10605204 SC |
5929 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5930 | kvm_mmu_commit_zap_page(kvm, | |
5931 | &kvm->arch.zapped_obsolete_pages); | |
5932 | goto unlock; | |
5933 | } | |
5934 | ||
ebdb292d | 5935 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5936 | |
10605204 | 5937 | unlock: |
531810ca | 5938 | write_unlock(&kvm->mmu_lock); |
f656ce01 | 5939 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5940 | |
70534a73 DC |
5941 | /* |
5942 | * unfair on small ones | |
5943 | * per-vm shrinkers cry out | |
5944 | * sadness comes quickly | |
5945 | */ | |
19526396 GN |
5946 | list_move_tail(&kvm->vm_list, &vm_list); |
5947 | break; | |
3ee16c81 | 5948 | } |
3ee16c81 | 5949 | |
0d9ce162 | 5950 | mutex_unlock(&kvm_lock); |
70534a73 | 5951 | return freed; |
70534a73 DC |
5952 | } |
5953 | ||
5954 | static unsigned long | |
5955 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5956 | { | |
45221ab6 | 5957 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5958 | } |
5959 | ||
5960 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5961 | .count_objects = mmu_shrink_count, |
5962 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5963 | .seeks = DEFAULT_SEEKS * 10, |
5964 | }; | |
5965 | ||
2ddfd20e | 5966 | static void mmu_destroy_caches(void) |
b5a33a75 | 5967 | { |
c1bd743e TH |
5968 | kmem_cache_destroy(pte_list_desc_cache); |
5969 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5970 | } |
5971 | ||
b8e8c830 PB |
5972 | static bool get_nx_auto_mode(void) |
5973 | { | |
5974 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5975 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5976 | } | |
5977 | ||
5978 | static void __set_nx_huge_pages(bool val) | |
5979 | { | |
5980 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5981 | } | |
5982 | ||
5983 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5984 | { | |
5985 | bool old_val = nx_huge_pages; | |
5986 | bool new_val; | |
5987 | ||
5988 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5989 | if (sysfs_streq(val, "off")) | |
5990 | new_val = 0; | |
5991 | else if (sysfs_streq(val, "force")) | |
5992 | new_val = 1; | |
5993 | else if (sysfs_streq(val, "auto")) | |
5994 | new_val = get_nx_auto_mode(); | |
5995 | else if (strtobool(val, &new_val) < 0) | |
5996 | return -EINVAL; | |
5997 | ||
5998 | __set_nx_huge_pages(new_val); | |
5999 | ||
6000 | if (new_val != old_val) { | |
6001 | struct kvm *kvm; | |
b8e8c830 PB |
6002 | |
6003 | mutex_lock(&kvm_lock); | |
6004 | ||
6005 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 6006 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 6007 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 6008 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
6009 | |
6010 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
6011 | } |
6012 | mutex_unlock(&kvm_lock); | |
6013 | } | |
6014 | ||
6015 | return 0; | |
6016 | } | |
6017 | ||
b5a33a75 AK |
6018 | int kvm_mmu_module_init(void) |
6019 | { | |
ab271bd4 AB |
6020 | int ret = -ENOMEM; |
6021 | ||
b8e8c830 PB |
6022 | if (nx_huge_pages == -1) |
6023 | __set_nx_huge_pages(get_nx_auto_mode()); | |
6024 | ||
36d9594d VK |
6025 | /* |
6026 | * MMU roles use union aliasing which is, generally speaking, an | |
6027 | * undefined behavior. However, we supposedly know how compilers behave | |
6028 | * and the current status quo is unlikely to change. Guardians below are | |
6029 | * supposed to let us know if the assumption becomes false. | |
6030 | */ | |
6031 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6032 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6033 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6034 | ||
28a1f3ac | 6035 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6036 | |
53c07b18 XG |
6037 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6038 | sizeof(struct pte_list_desc), | |
46bea48a | 6039 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6040 | if (!pte_list_desc_cache) |
ab271bd4 | 6041 | goto out; |
b5a33a75 | 6042 | |
d3d25b04 AK |
6043 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6044 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6045 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6046 | if (!mmu_page_header_cache) |
ab271bd4 | 6047 | goto out; |
d3d25b04 | 6048 | |
908c7f19 | 6049 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6050 | goto out; |
45bf21a8 | 6051 | |
ab271bd4 AB |
6052 | ret = register_shrinker(&mmu_shrinker); |
6053 | if (ret) | |
6054 | goto out; | |
3ee16c81 | 6055 | |
b5a33a75 AK |
6056 | return 0; |
6057 | ||
ab271bd4 | 6058 | out: |
3ee16c81 | 6059 | mmu_destroy_caches(); |
ab271bd4 | 6060 | return ret; |
b5a33a75 AK |
6061 | } |
6062 | ||
3ad82a7e | 6063 | /* |
39337ad1 | 6064 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 6065 | */ |
bc8a3d89 | 6066 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 6067 | { |
bc8a3d89 BG |
6068 | unsigned long nr_mmu_pages; |
6069 | unsigned long nr_pages = 0; | |
bc6678a3 | 6070 | struct kvm_memslots *slots; |
be6ba0f0 | 6071 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6072 | int i; |
3ad82a7e | 6073 | |
9da0e4d5 PB |
6074 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6075 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6076 | |
9da0e4d5 PB |
6077 | kvm_for_each_memslot(memslot, slots) |
6078 | nr_pages += memslot->npages; | |
6079 | } | |
3ad82a7e ZX |
6080 | |
6081 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 6082 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6083 | |
6084 | return nr_mmu_pages; | |
6085 | } | |
6086 | ||
c42fffe3 XG |
6087 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6088 | { | |
95f93af4 | 6089 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
6090 | free_mmu_pages(&vcpu->arch.root_mmu); |
6091 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 6092 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
6093 | } |
6094 | ||
b034cf01 XG |
6095 | void kvm_mmu_module_exit(void) |
6096 | { | |
6097 | mmu_destroy_caches(); | |
6098 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6099 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6100 | mmu_audit_disable(); |
6101 | } | |
1aa9b957 JS |
6102 | |
6103 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
6104 | { | |
6105 | unsigned int old_val; | |
6106 | int err; | |
6107 | ||
6108 | old_val = nx_huge_pages_recovery_ratio; | |
6109 | err = param_set_uint(val, kp); | |
6110 | if (err) | |
6111 | return err; | |
6112 | ||
6113 | if (READ_ONCE(nx_huge_pages) && | |
6114 | !old_val && nx_huge_pages_recovery_ratio) { | |
6115 | struct kvm *kvm; | |
6116 | ||
6117 | mutex_lock(&kvm_lock); | |
6118 | ||
6119 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6120 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
6121 | ||
6122 | mutex_unlock(&kvm_lock); | |
6123 | } | |
6124 | ||
6125 | return err; | |
6126 | } | |
6127 | ||
6128 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
6129 | { | |
ade74e14 | 6130 | unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits; |
1aa9b957 JS |
6131 | int rcu_idx; |
6132 | struct kvm_mmu_page *sp; | |
6133 | unsigned int ratio; | |
6134 | LIST_HEAD(invalid_list); | |
048f4980 | 6135 | bool flush = false; |
1aa9b957 JS |
6136 | ulong to_zap; |
6137 | ||
6138 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
531810ca | 6139 | write_lock(&kvm->mmu_lock); |
1aa9b957 JS |
6140 | |
6141 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
ade74e14 | 6142 | to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0; |
7d919c7a SC |
6143 | for ( ; to_zap; --to_zap) { |
6144 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
6145 | break; | |
6146 | ||
1aa9b957 JS |
6147 | /* |
6148 | * We use a separate list instead of just using active_mmu_pages | |
6149 | * because the number of lpage_disallowed pages is expected to | |
6150 | * be relatively small compared to the total. | |
6151 | */ | |
6152 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
6153 | struct kvm_mmu_page, | |
6154 | lpage_disallowed_link); | |
6155 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
897218ff | 6156 | if (is_tdp_mmu_page(sp)) { |
315f02c6 | 6157 | flush |= kvm_tdp_mmu_zap_sp(kvm, sp); |
8d1a182e | 6158 | } else { |
29cf0f50 BG |
6159 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
6160 | WARN_ON_ONCE(sp->lpage_disallowed); | |
6161 | } | |
1aa9b957 | 6162 | |
531810ca | 6163 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
048f4980 | 6164 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
531810ca | 6165 | cond_resched_rwlock_write(&kvm->mmu_lock); |
048f4980 | 6166 | flush = false; |
1aa9b957 JS |
6167 | } |
6168 | } | |
048f4980 | 6169 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
1aa9b957 | 6170 | |
531810ca | 6171 | write_unlock(&kvm->mmu_lock); |
1aa9b957 JS |
6172 | srcu_read_unlock(&kvm->srcu, rcu_idx); |
6173 | } | |
6174 | ||
6175 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6176 | { | |
6177 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6178 | ? start_time + 60 * HZ - get_jiffies_64() | |
6179 | : MAX_SCHEDULE_TIMEOUT; | |
6180 | } | |
6181 | ||
6182 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6183 | { | |
6184 | u64 start_time; | |
6185 | long remaining_time; | |
6186 | ||
6187 | while (true) { | |
6188 | start_time = get_jiffies_64(); | |
6189 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6190 | ||
6191 | set_current_state(TASK_INTERRUPTIBLE); | |
6192 | while (!kthread_should_stop() && remaining_time > 0) { | |
6193 | schedule_timeout(remaining_time); | |
6194 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6195 | set_current_state(TASK_INTERRUPTIBLE); | |
6196 | } | |
6197 | ||
6198 | set_current_state(TASK_RUNNING); | |
6199 | ||
6200 | if (kthread_should_stop()) | |
6201 | return 0; | |
6202 | ||
6203 | kvm_recover_nx_lpages(kvm); | |
6204 | } | |
6205 | } | |
6206 | ||
6207 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6208 | { | |
6209 | int err; | |
6210 | ||
6211 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6212 | "kvm-nx-lpage-recovery", | |
6213 | &kvm->arch.nx_lpage_recovery_thread); | |
6214 | if (!err) | |
6215 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6216 | ||
6217 | return err; | |
6218 | } | |
6219 | ||
6220 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6221 | { | |
6222 | if (kvm->arch.nx_lpage_recovery_thread) | |
6223 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6224 | } |