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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
4a98623d | 51 | #include <asm/set_memory.h> |
13673a90 | 52 | #include <asm/vmx.h> |
3d0c27ad | 53 | #include <asm/kvm_page_track.h> |
1261bfa3 | 54 | #include "trace.h" |
6aa8b732 | 55 | |
fc9bf2e0 SC |
56 | #include "paging.h" |
57 | ||
b8e8c830 PB |
58 | extern bool itlb_multihit_kvm_mitigation; |
59 | ||
a9d6496d | 60 | int __read_mostly nx_huge_pages = -1; |
13fb5927 PB |
61 | #ifdef CONFIG_PREEMPT_RT |
62 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
63 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
64 | #else | |
1aa9b957 | 65 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 66 | #endif |
b8e8c830 PB |
67 | |
68 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 69 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 70 | |
d5d6c18d | 71 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
72 | .set = set_nx_huge_pages, |
73 | .get = param_get_bool, | |
74 | }; | |
75 | ||
d5d6c18d | 76 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
77 | .set = set_nx_huge_pages_recovery_ratio, |
78 | .get = param_get_uint, | |
79 | }; | |
80 | ||
b8e8c830 PB |
81 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
82 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
83 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
84 | &nx_huge_pages_recovery_ratio, 0644); | |
85 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 86 | |
71fe7013 SC |
87 | static bool __read_mostly force_flush_and_sync_on_reuse; |
88 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
89 | ||
18552672 JR |
90 | /* |
91 | * When setting this variable to true it enables Two-Dimensional-Paging | |
92 | * where the hardware walks 2 page tables: | |
93 | * 1. the guest-virtual to guest-physical | |
94 | * 2. while doing 1. it walks guest-physical to host-physical | |
95 | * If the hardware supports that we don't need to do shadow paging. | |
96 | */ | |
2f333bcb | 97 | bool tdp_enabled = false; |
18552672 | 98 | |
1d92d2e8 | 99 | static int max_huge_page_level __read_mostly; |
83013059 | 100 | static int max_tdp_level __read_mostly; |
703c335d | 101 | |
8b1fe17c XG |
102 | enum { |
103 | AUDIT_PRE_PAGE_FAULT, | |
104 | AUDIT_POST_PAGE_FAULT, | |
105 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
106 | AUDIT_POST_PTE_WRITE, |
107 | AUDIT_PRE_SYNC, | |
108 | AUDIT_POST_SYNC | |
8b1fe17c | 109 | }; |
37a7d8b0 | 110 | |
37a7d8b0 | 111 | #ifdef MMU_DEBUG |
5a9624af | 112 | bool dbg = 0; |
fa4a2c08 | 113 | module_param(dbg, bool, 0644); |
d6c69ee9 | 114 | #endif |
6aa8b732 | 115 | |
957ed9ef XG |
116 | #define PTE_PREFETCH_NUM 8 |
117 | ||
6aa8b732 AK |
118 | #define PT32_LEVEL_BITS 10 |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
6aa8b732 AK |
131 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
132 | #define PT32_DIR_BASE_ADDR_MASK \ | |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT32_LVL_ADDR_MASK(level) \ |
135 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 137 | |
90bb6fc5 AK |
138 | #include <trace/events/kvm.h> |
139 | ||
dc1cff96 | 140 | /* make pte_list_desc fit well in cache lines */ |
13236e25 | 141 | #define PTE_LIST_EXT 14 |
220f773a | 142 | |
13236e25 PX |
143 | /* |
144 | * Slight optimization of cacheline layout, by putting `more' and `spte_count' | |
145 | * at the start; then accessing it will only use one single cacheline for | |
146 | * either full (entries==PTE_LIST_EXT) case or entries<=6. | |
147 | */ | |
53c07b18 | 148 | struct pte_list_desc { |
53c07b18 | 149 | struct pte_list_desc *more; |
13236e25 PX |
150 | /* |
151 | * Stores number of entries stored in the pte_list_desc. No need to be | |
152 | * u64 but just for easier alignment. When PTE_LIST_EXT, means full. | |
153 | */ | |
154 | u64 spte_count; | |
155 | u64 *sptes[PTE_LIST_EXT]; | |
cd4a4e53 AK |
156 | }; |
157 | ||
2d11123a AK |
158 | struct kvm_shadow_walk_iterator { |
159 | u64 addr; | |
160 | hpa_t shadow_addr; | |
2d11123a | 161 | u64 *sptep; |
dd3bfd59 | 162 | int level; |
2d11123a AK |
163 | unsigned index; |
164 | }; | |
165 | ||
7eb77e9f JS |
166 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
167 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
168 | (_root), (_addr)); \ | |
169 | shadow_walk_okay(&(_walker)); \ | |
170 | shadow_walk_next(&(_walker))) | |
171 | ||
172 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
173 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
174 | shadow_walk_okay(&(_walker)); \ | |
175 | shadow_walk_next(&(_walker))) | |
176 | ||
c2a2ac2b XG |
177 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
178 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
179 | shadow_walk_okay(&(_walker)) && \ | |
180 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
181 | __shadow_walk_next(&(_walker), spte)) | |
182 | ||
53c07b18 | 183 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 184 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 185 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 186 | |
ce88decf | 187 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
188 | static union kvm_mmu_page_role |
189 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 190 | |
594e91a1 SC |
191 | struct kvm_mmu_role_regs { |
192 | const unsigned long cr0; | |
193 | const unsigned long cr4; | |
194 | const u64 efer; | |
195 | }; | |
196 | ||
335e192a PB |
197 | #define CREATE_TRACE_POINTS |
198 | #include "mmutrace.h" | |
199 | ||
594e91a1 SC |
200 | /* |
201 | * Yes, lot's of underscores. They're a hint that you probably shouldn't be | |
202 | * reading from the role_regs. Once the mmu_role is constructed, it becomes | |
203 | * the single source of truth for the MMU's state. | |
204 | */ | |
205 | #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \ | |
206 | static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\ | |
207 | { \ | |
208 | return !!(regs->reg & flag); \ | |
209 | } | |
210 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG); | |
211 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP); | |
212 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE); | |
213 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE); | |
214 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP); | |
215 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP); | |
216 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE); | |
217 | BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57); | |
218 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX); | |
219 | BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA); | |
220 | ||
60667724 SC |
221 | /* |
222 | * The MMU itself (with a valid role) is the single source of truth for the | |
223 | * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The | |
224 | * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1, | |
225 | * and the vCPU may be incorrect/irrelevant. | |
226 | */ | |
227 | #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \ | |
228 | static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \ | |
229 | { \ | |
230 | return !!(mmu->mmu_role. base_or_ext . reg##_##name); \ | |
231 | } | |
232 | BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg); | |
233 | BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp); | |
234 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse); | |
235 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae); | |
236 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep); | |
237 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap); | |
238 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke); | |
239 | BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57); | |
240 | BUILD_MMU_ROLE_ACCESSOR(base, efer, nx); | |
241 | ||
594e91a1 SC |
242 | static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu) |
243 | { | |
244 | struct kvm_mmu_role_regs regs = { | |
245 | .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS), | |
246 | .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS), | |
247 | .efer = vcpu->arch.efer, | |
248 | }; | |
249 | ||
250 | return regs; | |
251 | } | |
40ef75a7 | 252 | |
f4bd6f73 SC |
253 | static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs) |
254 | { | |
255 | if (!____is_cr0_pg(regs)) | |
256 | return 0; | |
257 | else if (____is_efer_lma(regs)) | |
258 | return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL : | |
259 | PT64_ROOT_4LEVEL; | |
260 | else if (____is_cr4_pae(regs)) | |
261 | return PT32E_ROOT_LEVEL; | |
262 | else | |
263 | return PT32_ROOT_LEVEL; | |
264 | } | |
40ef75a7 LT |
265 | |
266 | static inline bool kvm_available_flush_tlb_with_range(void) | |
267 | { | |
afaf0b2f | 268 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
269 | } |
270 | ||
271 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
272 | struct kvm_tlb_range *range) | |
273 | { | |
274 | int ret = -ENOTSUPP; | |
275 | ||
afaf0b2f | 276 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
b3646477 | 277 | ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range); |
40ef75a7 LT |
278 | |
279 | if (ret) | |
280 | kvm_flush_remote_tlbs(kvm); | |
281 | } | |
282 | ||
2f2fad08 | 283 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
284 | u64 start_gfn, u64 pages) |
285 | { | |
286 | struct kvm_tlb_range range; | |
287 | ||
288 | range.start_gfn = start_gfn; | |
289 | range.pages = pages; | |
290 | ||
291 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
292 | } | |
293 | ||
8f79b064 BG |
294 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
295 | unsigned int access) | |
296 | { | |
c236d962 | 297 | u64 spte = make_mmio_spte(vcpu, gfn, access); |
8f79b064 | 298 | |
c236d962 SC |
299 | trace_mark_mmio_spte(sptep, gfn, spte); |
300 | mmu_spte_set(sptep, spte); | |
ce88decf XG |
301 | } |
302 | ||
ce88decf XG |
303 | static gfn_t get_mmio_spte_gfn(u64 spte) |
304 | { | |
daa07cbc | 305 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 306 | |
8a967d65 | 307 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
308 | & shadow_nonpresent_or_rsvd_mask; |
309 | ||
310 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
311 | } |
312 | ||
313 | static unsigned get_mmio_spte_access(u64 spte) | |
314 | { | |
4af77151 | 315 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
316 | } |
317 | ||
54bf36aa | 318 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 319 | { |
cae7ed3c | 320 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 321 | |
cae7ed3c SC |
322 | gen = kvm_vcpu_memslots(vcpu)->generation; |
323 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
324 | return false; | |
089504c0 | 325 | |
cae7ed3c | 326 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
327 | spte_gen = get_mmio_spte_generation(spte); |
328 | ||
329 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
330 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
331 | } |
332 | ||
cd313569 MG |
333 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
334 | struct x86_exception *exception) | |
335 | { | |
ec7771ab | 336 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 337 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
338 | exception->error_code |= PFERR_RSVD_MASK; |
339 | return UNMAPPED_GVA; | |
340 | } | |
341 | ||
cd313569 MG |
342 | return gpa; |
343 | } | |
344 | ||
6aa8b732 AK |
345 | static int is_cpuid_PSE36(void) |
346 | { | |
347 | return 1; | |
348 | } | |
349 | ||
da928521 AK |
350 | static gfn_t pse36_gfn_delta(u32 gpte) |
351 | { | |
352 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
353 | ||
354 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
355 | } | |
356 | ||
603e0651 | 357 | #ifdef CONFIG_X86_64 |
d555c333 | 358 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 359 | { |
b19ee2ff | 360 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
361 | } |
362 | ||
603e0651 | 363 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 364 | { |
b19ee2ff | 365 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
366 | } |
367 | ||
368 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
369 | { | |
370 | return xchg(sptep, spte); | |
371 | } | |
c2a2ac2b XG |
372 | |
373 | static u64 __get_spte_lockless(u64 *sptep) | |
374 | { | |
6aa7de05 | 375 | return READ_ONCE(*sptep); |
c2a2ac2b | 376 | } |
a9221dd5 | 377 | #else |
603e0651 XG |
378 | union split_spte { |
379 | struct { | |
380 | u32 spte_low; | |
381 | u32 spte_high; | |
382 | }; | |
383 | u64 spte; | |
384 | }; | |
a9221dd5 | 385 | |
c2a2ac2b XG |
386 | static void count_spte_clear(u64 *sptep, u64 spte) |
387 | { | |
57354682 | 388 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
389 | |
390 | if (is_shadow_present_pte(spte)) | |
391 | return; | |
392 | ||
393 | /* Ensure the spte is completely set before we increase the count */ | |
394 | smp_wmb(); | |
395 | sp->clear_spte_count++; | |
396 | } | |
397 | ||
603e0651 XG |
398 | static void __set_spte(u64 *sptep, u64 spte) |
399 | { | |
400 | union split_spte *ssptep, sspte; | |
a9221dd5 | 401 | |
603e0651 XG |
402 | ssptep = (union split_spte *)sptep; |
403 | sspte = (union split_spte)spte; | |
404 | ||
405 | ssptep->spte_high = sspte.spte_high; | |
406 | ||
407 | /* | |
408 | * If we map the spte from nonpresent to present, We should store | |
409 | * the high bits firstly, then set present bit, so cpu can not | |
410 | * fetch this spte while we are setting the spte. | |
411 | */ | |
412 | smp_wmb(); | |
413 | ||
b19ee2ff | 414 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
415 | } |
416 | ||
603e0651 XG |
417 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
418 | { | |
419 | union split_spte *ssptep, sspte; | |
420 | ||
421 | ssptep = (union split_spte *)sptep; | |
422 | sspte = (union split_spte)spte; | |
423 | ||
b19ee2ff | 424 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
425 | |
426 | /* | |
427 | * If we map the spte from present to nonpresent, we should clear | |
428 | * present bit firstly to avoid vcpu fetch the old high bits. | |
429 | */ | |
430 | smp_wmb(); | |
431 | ||
432 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 433 | count_spte_clear(sptep, spte); |
603e0651 XG |
434 | } |
435 | ||
436 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
437 | { | |
438 | union split_spte *ssptep, sspte, orig; | |
439 | ||
440 | ssptep = (union split_spte *)sptep; | |
441 | sspte = (union split_spte)spte; | |
442 | ||
443 | /* xchg acts as a barrier before the setting of the high bits */ | |
444 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
445 | orig.spte_high = ssptep->spte_high; |
446 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 447 | count_spte_clear(sptep, spte); |
603e0651 XG |
448 | |
449 | return orig.spte; | |
450 | } | |
c2a2ac2b XG |
451 | |
452 | /* | |
453 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 454 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
455 | * |
456 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
457 | * coalesces them and we are running out of the MMU lock. Therefore | |
458 | * we need to protect against in-progress updates of the spte. | |
459 | * | |
460 | * Reading the spte while an update is in progress may get the old value | |
461 | * for the high part of the spte. The race is fine for a present->non-present | |
462 | * change (because the high part of the spte is ignored for non-present spte), | |
463 | * but for a present->present change we must reread the spte. | |
464 | * | |
465 | * All such changes are done in two steps (present->non-present and | |
466 | * non-present->present), hence it is enough to count the number of | |
467 | * present->non-present updates: if it changed while reading the spte, | |
468 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
469 | */ |
470 | static u64 __get_spte_lockless(u64 *sptep) | |
471 | { | |
57354682 | 472 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
473 | union split_spte spte, *orig = (union split_spte *)sptep; |
474 | int count; | |
475 | ||
476 | retry: | |
477 | count = sp->clear_spte_count; | |
478 | smp_rmb(); | |
479 | ||
480 | spte.spte_low = orig->spte_low; | |
481 | smp_rmb(); | |
482 | ||
483 | spte.spte_high = orig->spte_high; | |
484 | smp_rmb(); | |
485 | ||
486 | if (unlikely(spte.spte_low != orig->spte_low || | |
487 | count != sp->clear_spte_count)) | |
488 | goto retry; | |
489 | ||
490 | return spte.spte; | |
491 | } | |
603e0651 XG |
492 | #endif |
493 | ||
8672b721 XG |
494 | static bool spte_has_volatile_bits(u64 spte) |
495 | { | |
f160c7b7 JS |
496 | if (!is_shadow_present_pte(spte)) |
497 | return false; | |
498 | ||
c7ba5b48 | 499 | /* |
6a6256f9 | 500 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
501 | * out of mmu-lock, it can ensure dirty bit is not lost, |
502 | * also, it can help us to get a stable is_writable_pte() | |
503 | * to ensure tlb flush is not missed. | |
504 | */ | |
f160c7b7 JS |
505 | if (spte_can_locklessly_be_made_writable(spte) || |
506 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
507 | return true; |
508 | ||
ac8d57e5 | 509 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
510 | if ((spte & shadow_accessed_mask) == 0 || |
511 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
512 | return true; | |
513 | } | |
8672b721 | 514 | |
f160c7b7 | 515 | return false; |
8672b721 XG |
516 | } |
517 | ||
1df9f2dc XG |
518 | /* Rules for using mmu_spte_set: |
519 | * Set the sptep from nonpresent to present. | |
520 | * Note: the sptep being assigned *must* be either not present | |
521 | * or in a state where the hardware will not attempt to update | |
522 | * the spte. | |
523 | */ | |
524 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
525 | { | |
526 | WARN_ON(is_shadow_present_pte(*sptep)); | |
527 | __set_spte(sptep, new_spte); | |
528 | } | |
529 | ||
f39a058d JS |
530 | /* |
531 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
532 | * accessed/dirty status. | |
1df9f2dc | 533 | */ |
f39a058d | 534 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 535 | { |
c7ba5b48 | 536 | u64 old_spte = *sptep; |
4132779b | 537 | |
afd28fe1 | 538 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 539 | |
6e7d0354 XG |
540 | if (!is_shadow_present_pte(old_spte)) { |
541 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 542 | return old_spte; |
6e7d0354 | 543 | } |
4132779b | 544 | |
c7ba5b48 | 545 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 546 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 547 | else |
603e0651 | 548 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 549 | |
83ef6c81 JS |
550 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
551 | ||
f39a058d JS |
552 | return old_spte; |
553 | } | |
554 | ||
555 | /* Rules for using mmu_spte_update: | |
556 | * Update the state bits, it means the mapped pfn is not changed. | |
557 | * | |
558 | * Whenever we overwrite a writable spte with a read-only one we | |
559 | * should flush remote TLBs. Otherwise rmap_write_protect | |
560 | * will find a read-only spte, even though the writable spte | |
561 | * might be cached on a CPU's TLB, the return value indicates this | |
562 | * case. | |
563 | * | |
564 | * Returns true if the TLB needs to be flushed | |
565 | */ | |
566 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
567 | { | |
568 | bool flush = false; | |
569 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
570 | ||
571 | if (!is_shadow_present_pte(old_spte)) | |
572 | return false; | |
573 | ||
c7ba5b48 XG |
574 | /* |
575 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 576 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
577 | * spte_has_volatile_bits(). |
578 | */ | |
ea4114bc | 579 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 580 | !is_writable_pte(new_spte)) |
83ef6c81 | 581 | flush = true; |
4132779b | 582 | |
7e71a59b | 583 | /* |
83ef6c81 | 584 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
585 | * to guarantee consistency between TLB and page tables. |
586 | */ | |
7e71a59b | 587 | |
83ef6c81 JS |
588 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
589 | flush = true; | |
4132779b | 590 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
591 | } |
592 | ||
593 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
594 | flush = true; | |
4132779b | 595 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 596 | } |
6e7d0354 | 597 | |
83ef6c81 | 598 | return flush; |
b79b93f9 AK |
599 | } |
600 | ||
1df9f2dc XG |
601 | /* |
602 | * Rules for using mmu_spte_clear_track_bits: | |
603 | * It sets the sptep from present to nonpresent, and track the | |
604 | * state bits, it is used to clear the last level sptep. | |
7fa2a347 | 605 | * Returns the old PTE. |
1df9f2dc | 606 | */ |
7fa2a347 | 607 | static u64 mmu_spte_clear_track_bits(u64 *sptep) |
1df9f2dc | 608 | { |
ba049e93 | 609 | kvm_pfn_t pfn; |
1df9f2dc XG |
610 | u64 old_spte = *sptep; |
611 | ||
612 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 613 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 614 | else |
603e0651 | 615 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 616 | |
afd28fe1 | 617 | if (!is_shadow_present_pte(old_spte)) |
7fa2a347 | 618 | return old_spte; |
1df9f2dc XG |
619 | |
620 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
621 | |
622 | /* | |
623 | * KVM does not hold the refcount of the page used by | |
624 | * kvm mmu, before reclaiming the page, we should | |
625 | * unmap it from mmu first. | |
626 | */ | |
bf4bea8e | 627 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 628 | |
83ef6c81 | 629 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 630 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
631 | |
632 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 633 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 634 | |
7fa2a347 | 635 | return old_spte; |
1df9f2dc XG |
636 | } |
637 | ||
638 | /* | |
639 | * Rules for using mmu_spte_clear_no_track: | |
640 | * Directly clear spte without caring the state bits of sptep, | |
641 | * it is used to set the upper level spte. | |
642 | */ | |
643 | static void mmu_spte_clear_no_track(u64 *sptep) | |
644 | { | |
603e0651 | 645 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
646 | } |
647 | ||
c2a2ac2b XG |
648 | static u64 mmu_spte_get_lockless(u64 *sptep) |
649 | { | |
650 | return __get_spte_lockless(sptep); | |
651 | } | |
652 | ||
d3e328f2 JS |
653 | /* Restore an acc-track PTE back to a regular PTE */ |
654 | static u64 restore_acc_track_spte(u64 spte) | |
655 | { | |
656 | u64 new_spte = spte; | |
8a967d65 PB |
657 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
658 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 659 | |
ac8d57e5 | 660 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
661 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
662 | ||
663 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
664 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
665 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
666 | new_spte |= saved_bits; |
667 | ||
668 | return new_spte; | |
669 | } | |
670 | ||
f160c7b7 JS |
671 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
672 | static bool mmu_spte_age(u64 *sptep) | |
673 | { | |
674 | u64 spte = mmu_spte_get_lockless(sptep); | |
675 | ||
676 | if (!is_accessed_spte(spte)) | |
677 | return false; | |
678 | ||
ac8d57e5 | 679 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
680 | clear_bit((ffs(shadow_accessed_mask) - 1), |
681 | (unsigned long *)sptep); | |
682 | } else { | |
683 | /* | |
684 | * Capture the dirty status of the page, so that it doesn't get | |
685 | * lost when the SPTE is marked for access tracking. | |
686 | */ | |
687 | if (is_writable_pte(spte)) | |
688 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
689 | ||
690 | spte = mark_spte_for_access_track(spte); | |
691 | mmu_spte_update_no_track(sptep, spte); | |
692 | } | |
693 | ||
694 | return true; | |
695 | } | |
696 | ||
c2a2ac2b XG |
697 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
698 | { | |
c5c8c7c5 DM |
699 | if (is_tdp_mmu(vcpu->arch.mmu)) { |
700 | kvm_tdp_mmu_walk_lockless_begin(); | |
701 | } else { | |
702 | /* | |
703 | * Prevent page table teardown by making any free-er wait during | |
704 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
705 | */ | |
706 | local_irq_disable(); | |
36ca7e0a | 707 | |
c5c8c7c5 DM |
708 | /* |
709 | * Make sure a following spte read is not reordered ahead of the write | |
710 | * to vcpu->mode. | |
711 | */ | |
712 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); | |
713 | } | |
c2a2ac2b XG |
714 | } |
715 | ||
716 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
717 | { | |
c5c8c7c5 DM |
718 | if (is_tdp_mmu(vcpu->arch.mmu)) { |
719 | kvm_tdp_mmu_walk_lockless_end(); | |
720 | } else { | |
721 | /* | |
722 | * Make sure the write to vcpu->mode is not reordered in front of | |
723 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us | |
724 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
725 | */ | |
726 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); | |
727 | local_irq_enable(); | |
728 | } | |
c2a2ac2b XG |
729 | } |
730 | ||
378f5cd6 | 731 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 732 | { |
e2dec939 AK |
733 | int r; |
734 | ||
531281ad | 735 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
736 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
737 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 738 | if (r) |
284aa868 | 739 | return r; |
94ce87ef SC |
740 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
741 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 742 | if (r) |
171a90d7 | 743 | return r; |
378f5cd6 | 744 | if (maybe_indirect) { |
94ce87ef SC |
745 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
746 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
747 | if (r) |
748 | return r; | |
749 | } | |
94ce87ef SC |
750 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
751 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
752 | } |
753 | ||
754 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
755 | { | |
94ce87ef SC |
756 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
757 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
758 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
759 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
760 | } |
761 | ||
53c07b18 | 762 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 763 | { |
94ce87ef | 764 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
765 | } |
766 | ||
53c07b18 | 767 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 768 | { |
53c07b18 | 769 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
770 | } |
771 | ||
2032a93d LJ |
772 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
773 | { | |
774 | if (!sp->role.direct) | |
775 | return sp->gfns[index]; | |
776 | ||
777 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
778 | } | |
779 | ||
780 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
781 | { | |
e9f2a760 | 782 | if (!sp->role.direct) { |
2032a93d | 783 | sp->gfns[index] = gfn; |
e9f2a760 PB |
784 | return; |
785 | } | |
786 | ||
787 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
788 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
789 | "(expected %llx, got %llx)\n", | |
790 | sp->gfn, | |
791 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
792 | } |
793 | ||
05da4558 | 794 | /* |
d4dbf470 TY |
795 | * Return the pointer to the large page information for a given gfn, |
796 | * handling slots that are not large page aligned. | |
05da4558 | 797 | */ |
d4dbf470 | 798 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
8ca6f063 | 799 | const struct kvm_memory_slot *slot, int level) |
05da4558 MT |
800 | { |
801 | unsigned long idx; | |
802 | ||
fb03cb6f | 803 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 804 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
805 | } |
806 | ||
269e9552 | 807 | static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot *slot, |
547ffaed XG |
808 | gfn_t gfn, int count) |
809 | { | |
810 | struct kvm_lpage_info *linfo; | |
811 | int i; | |
812 | ||
3bae0459 | 813 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
814 | linfo = lpage_info_slot(gfn, slot, i); |
815 | linfo->disallow_lpage += count; | |
816 | WARN_ON(linfo->disallow_lpage < 0); | |
817 | } | |
818 | } | |
819 | ||
269e9552 | 820 | void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn) |
547ffaed XG |
821 | { |
822 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
823 | } | |
824 | ||
269e9552 | 825 | void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn) |
547ffaed XG |
826 | { |
827 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
828 | } | |
829 | ||
3ed1a478 | 830 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 831 | { |
699023e2 | 832 | struct kvm_memslots *slots; |
d25797b2 | 833 | struct kvm_memory_slot *slot; |
3ed1a478 | 834 | gfn_t gfn; |
05da4558 | 835 | |
56ca57f9 | 836 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 837 | gfn = sp->gfn; |
699023e2 PB |
838 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
839 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
840 | |
841 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 842 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
843 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
844 | KVM_PAGE_TRACK_WRITE); | |
845 | ||
547ffaed | 846 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
847 | } |
848 | ||
29cf0f50 | 849 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
850 | { |
851 | if (sp->lpage_disallowed) | |
852 | return; | |
853 | ||
854 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
855 | list_add_tail(&sp->lpage_disallowed_link, |
856 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
857 | sp->lpage_disallowed = true; |
858 | } | |
859 | ||
3ed1a478 | 860 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 861 | { |
699023e2 | 862 | struct kvm_memslots *slots; |
d25797b2 | 863 | struct kvm_memory_slot *slot; |
3ed1a478 | 864 | gfn_t gfn; |
05da4558 | 865 | |
56ca57f9 | 866 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 867 | gfn = sp->gfn; |
699023e2 PB |
868 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
869 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 870 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
871 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
872 | KVM_PAGE_TRACK_WRITE); | |
873 | ||
547ffaed | 874 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
875 | } |
876 | ||
29cf0f50 | 877 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
878 | { |
879 | --kvm->stat.nx_lpage_splits; | |
880 | sp->lpage_disallowed = false; | |
1aa9b957 | 881 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
882 | } |
883 | ||
5d163b1c XG |
884 | static struct kvm_memory_slot * |
885 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
886 | bool no_dirty_log) | |
05da4558 MT |
887 | { |
888 | struct kvm_memory_slot *slot; | |
5d163b1c | 889 | |
54bf36aa | 890 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
891 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
892 | return NULL; | |
044c59c4 | 893 | if (no_dirty_log && kvm_slot_dirty_track_enabled(slot)) |
91b0d268 | 894 | return NULL; |
5d163b1c XG |
895 | |
896 | return slot; | |
897 | } | |
898 | ||
290fc38d | 899 | /* |
018aabb5 | 900 | * About rmap_head encoding: |
cd4a4e53 | 901 | * |
018aabb5 TY |
902 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
903 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 904 | * pte_list_desc containing more mappings. |
018aabb5 TY |
905 | */ |
906 | ||
907 | /* | |
908 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 909 | */ |
53c07b18 | 910 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 911 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 912 | { |
53c07b18 | 913 | struct pte_list_desc *desc; |
13236e25 | 914 | int count = 0; |
cd4a4e53 | 915 | |
018aabb5 | 916 | if (!rmap_head->val) { |
805a0f83 | 917 | rmap_printk("%p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
918 | rmap_head->val = (unsigned long)spte; |
919 | } else if (!(rmap_head->val & 1)) { | |
805a0f83 | 920 | rmap_printk("%p %llx 1->many\n", spte, *spte); |
53c07b18 | 921 | desc = mmu_alloc_pte_list_desc(vcpu); |
018aabb5 | 922 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 923 | desc->sptes[1] = spte; |
13236e25 | 924 | desc->spte_count = 2; |
018aabb5 | 925 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 926 | ++count; |
cd4a4e53 | 927 | } else { |
805a0f83 | 928 | rmap_printk("%p %llx many->many\n", spte, *spte); |
018aabb5 | 929 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
13236e25 | 930 | while (desc->spte_count == PTE_LIST_EXT) { |
53c07b18 | 931 | count += PTE_LIST_EXT; |
c6c4f961 LR |
932 | if (!desc->more) { |
933 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
934 | desc = desc->more; | |
13236e25 | 935 | desc->spte_count = 0; |
c6c4f961 LR |
936 | break; |
937 | } | |
cd4a4e53 AK |
938 | desc = desc->more; |
939 | } | |
13236e25 PX |
940 | count += desc->spte_count; |
941 | desc->sptes[desc->spte_count++] = spte; | |
cd4a4e53 | 942 | } |
53a27b39 | 943 | return count; |
cd4a4e53 AK |
944 | } |
945 | ||
53c07b18 | 946 | static void |
018aabb5 TY |
947 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
948 | struct pte_list_desc *desc, int i, | |
949 | struct pte_list_desc *prev_desc) | |
cd4a4e53 | 950 | { |
13236e25 | 951 | int j = desc->spte_count - 1; |
cd4a4e53 | 952 | |
d555c333 AK |
953 | desc->sptes[i] = desc->sptes[j]; |
954 | desc->sptes[j] = NULL; | |
13236e25 PX |
955 | desc->spte_count--; |
956 | if (desc->spte_count) | |
cd4a4e53 AK |
957 | return; |
958 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 959 | rmap_head->val = 0; |
cd4a4e53 AK |
960 | else |
961 | if (prev_desc) | |
962 | prev_desc->more = desc->more; | |
963 | else | |
018aabb5 | 964 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 965 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
966 | } |
967 | ||
8daf3462 | 968 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 969 | { |
53c07b18 XG |
970 | struct pte_list_desc *desc; |
971 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
972 | int i; |
973 | ||
018aabb5 | 974 | if (!rmap_head->val) { |
8daf3462 | 975 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 976 | BUG(); |
018aabb5 | 977 | } else if (!(rmap_head->val & 1)) { |
805a0f83 | 978 | rmap_printk("%p 1->0\n", spte); |
018aabb5 | 979 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 980 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
981 | BUG(); |
982 | } | |
018aabb5 | 983 | rmap_head->val = 0; |
cd4a4e53 | 984 | } else { |
805a0f83 | 985 | rmap_printk("%p many->many\n", spte); |
018aabb5 | 986 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
987 | prev_desc = NULL; |
988 | while (desc) { | |
13236e25 | 989 | for (i = 0; i < desc->spte_count; ++i) { |
d555c333 | 990 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
991 | pte_list_desc_remove_entry(rmap_head, |
992 | desc, i, prev_desc); | |
cd4a4e53 AK |
993 | return; |
994 | } | |
018aabb5 | 995 | } |
cd4a4e53 AK |
996 | prev_desc = desc; |
997 | desc = desc->more; | |
998 | } | |
8daf3462 | 999 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
1000 | BUG(); |
1001 | } | |
1002 | } | |
1003 | ||
e7912386 WY |
1004 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
1005 | { | |
1006 | mmu_spte_clear_track_bits(sptep); | |
1007 | __pte_list_remove(sptep, rmap_head); | |
1008 | } | |
1009 | ||
a75b5404 PX |
1010 | /* Return true if rmap existed, false otherwise */ |
1011 | static bool pte_list_destroy(struct kvm_rmap_head *rmap_head) | |
1012 | { | |
1013 | struct pte_list_desc *desc, *next; | |
1014 | int i; | |
1015 | ||
1016 | if (!rmap_head->val) | |
1017 | return false; | |
1018 | ||
1019 | if (!(rmap_head->val & 1)) { | |
1020 | mmu_spte_clear_track_bits((u64 *)rmap_head->val); | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); | |
1025 | ||
1026 | for (; desc; desc = next) { | |
1027 | for (i = 0; i < desc->spte_count; i++) | |
1028 | mmu_spte_clear_track_bits(desc->sptes[i]); | |
1029 | next = desc->more; | |
1030 | mmu_free_pte_list_desc(desc); | |
1031 | } | |
1032 | out: | |
1033 | /* rmap_head is meaningless now, remember to reset it */ | |
1034 | rmap_head->val = 0; | |
1035 | return true; | |
1036 | } | |
1037 | ||
3bcd0662 PX |
1038 | unsigned int pte_list_count(struct kvm_rmap_head *rmap_head) |
1039 | { | |
1040 | struct pte_list_desc *desc; | |
1041 | unsigned int count = 0; | |
1042 | ||
1043 | if (!rmap_head->val) | |
1044 | return 0; | |
1045 | else if (!(rmap_head->val & 1)) | |
1046 | return 1; | |
1047 | ||
1048 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); | |
1049 | ||
1050 | while (desc) { | |
1051 | count += desc->spte_count; | |
1052 | desc = desc->more; | |
1053 | } | |
1054 | ||
1055 | return count; | |
1056 | } | |
1057 | ||
93e083d4 DM |
1058 | static struct kvm_rmap_head *gfn_to_rmap(gfn_t gfn, int level, |
1059 | const struct kvm_memory_slot *slot) | |
53c07b18 | 1060 | { |
77d11309 | 1061 | unsigned long idx; |
53c07b18 | 1062 | |
77d11309 | 1063 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 1064 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
1065 | } |
1066 | ||
f759e2b4 XG |
1067 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1068 | { | |
356ec69a | 1069 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 1070 | |
356ec69a | 1071 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 1072 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
1073 | } |
1074 | ||
53c07b18 XG |
1075 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1076 | { | |
601f8af0 | 1077 | struct kvm_memory_slot *slot; |
53c07b18 | 1078 | struct kvm_mmu_page *sp; |
018aabb5 | 1079 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1080 | |
57354682 | 1081 | sp = sptep_to_sp(spte); |
53c07b18 | 1082 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
601f8af0 | 1083 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
93e083d4 | 1084 | rmap_head = gfn_to_rmap(gfn, sp->role.level, slot); |
018aabb5 | 1085 | return pte_list_add(vcpu, spte, rmap_head); |
53c07b18 XG |
1086 | } |
1087 | ||
601f8af0 | 1088 | |
53c07b18 XG |
1089 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1090 | { | |
601f8af0 DM |
1091 | struct kvm_memslots *slots; |
1092 | struct kvm_memory_slot *slot; | |
53c07b18 XG |
1093 | struct kvm_mmu_page *sp; |
1094 | gfn_t gfn; | |
018aabb5 | 1095 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1096 | |
57354682 | 1097 | sp = sptep_to_sp(spte); |
53c07b18 | 1098 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
601f8af0 DM |
1099 | |
1100 | /* | |
1101 | * Unlike rmap_add and rmap_recycle, rmap_remove does not run in the | |
1102 | * context of a vCPU so have to determine which memslots to use based | |
1103 | * on context information in sp->role. | |
1104 | */ | |
1105 | slots = kvm_memslots_for_spte_role(kvm, sp->role); | |
1106 | ||
1107 | slot = __gfn_to_memslot(slots, gfn); | |
93e083d4 | 1108 | rmap_head = gfn_to_rmap(gfn, sp->role.level, slot); |
601f8af0 | 1109 | |
8daf3462 | 1110 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1111 | } |
1112 | ||
1e3f42f0 TY |
1113 | /* |
1114 | * Used by the following functions to iterate through the sptes linked by a | |
1115 | * rmap. All fields are private and not assumed to be used outside. | |
1116 | */ | |
1117 | struct rmap_iterator { | |
1118 | /* private fields */ | |
1119 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1120 | int pos; /* index of the sptep */ | |
1121 | }; | |
1122 | ||
1123 | /* | |
1124 | * Iteration must be started by this function. This should also be used after | |
1125 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1126 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1127 | * |
1128 | * Returns sptep if found, NULL otherwise. | |
1129 | */ | |
018aabb5 TY |
1130 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1131 | struct rmap_iterator *iter) | |
1e3f42f0 | 1132 | { |
77fbbbd2 TY |
1133 | u64 *sptep; |
1134 | ||
018aabb5 | 1135 | if (!rmap_head->val) |
1e3f42f0 TY |
1136 | return NULL; |
1137 | ||
018aabb5 | 1138 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1139 | iter->desc = NULL; |
77fbbbd2 TY |
1140 | sptep = (u64 *)rmap_head->val; |
1141 | goto out; | |
1e3f42f0 TY |
1142 | } |
1143 | ||
018aabb5 | 1144 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1145 | iter->pos = 0; |
77fbbbd2 TY |
1146 | sptep = iter->desc->sptes[iter->pos]; |
1147 | out: | |
1148 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1149 | return sptep; | |
1e3f42f0 TY |
1150 | } |
1151 | ||
1152 | /* | |
1153 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1154 | * | |
1155 | * Returns sptep if found, NULL otherwise. | |
1156 | */ | |
1157 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1158 | { | |
77fbbbd2 TY |
1159 | u64 *sptep; |
1160 | ||
1e3f42f0 TY |
1161 | if (iter->desc) { |
1162 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1163 | ++iter->pos; |
1164 | sptep = iter->desc->sptes[iter->pos]; | |
1165 | if (sptep) | |
77fbbbd2 | 1166 | goto out; |
1e3f42f0 TY |
1167 | } |
1168 | ||
1169 | iter->desc = iter->desc->more; | |
1170 | ||
1171 | if (iter->desc) { | |
1172 | iter->pos = 0; | |
1173 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1174 | sptep = iter->desc->sptes[iter->pos]; |
1175 | goto out; | |
1e3f42f0 TY |
1176 | } |
1177 | } | |
1178 | ||
1179 | return NULL; | |
77fbbbd2 TY |
1180 | out: |
1181 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1182 | return sptep; | |
1e3f42f0 TY |
1183 | } |
1184 | ||
018aabb5 TY |
1185 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1186 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1187 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1188 | |
c3707958 | 1189 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1190 | { |
7fa2a347 SC |
1191 | u64 old_spte = mmu_spte_clear_track_bits(sptep); |
1192 | ||
1193 | if (is_shadow_present_pte(old_spte)) | |
eb45fda4 | 1194 | rmap_remove(kvm, sptep); |
be38d276 AK |
1195 | } |
1196 | ||
8e22f955 XG |
1197 | |
1198 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1199 | { | |
1200 | if (is_large_pte(*sptep)) { | |
57354682 | 1201 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1202 | drop_spte(kvm, sptep); |
1203 | --kvm->stat.lpages; | |
1204 | return true; | |
1205 | } | |
1206 | ||
1207 | return false; | |
1208 | } | |
1209 | ||
1210 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1211 | { | |
c3134ce2 | 1212 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1213 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1214 | |
1215 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1216 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1217 | } | |
8e22f955 XG |
1218 | } |
1219 | ||
1220 | /* | |
49fde340 | 1221 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1222 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1223 | * |
b4619660 | 1224 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1225 | * protection: |
1226 | * - for dirty logging, the spte can be set to writable at anytime if | |
1227 | * its dirty bitmap is properly set. | |
1228 | * - for spte protection, the spte can be writable only after unsync-ing | |
1229 | * shadow page. | |
8e22f955 | 1230 | * |
c126d94f | 1231 | * Return true if tlb need be flushed. |
8e22f955 | 1232 | */ |
c4f138b4 | 1233 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1234 | { |
1235 | u64 spte = *sptep; | |
1236 | ||
49fde340 | 1237 | if (!is_writable_pte(spte) && |
ea4114bc | 1238 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1239 | return false; |
1240 | ||
805a0f83 | 1241 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
d13bc5b5 | 1242 | |
49fde340 | 1243 | if (pt_protect) |
5fc3424f | 1244 | spte &= ~shadow_mmu_writable_mask; |
d13bc5b5 | 1245 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1246 | |
c126d94f | 1247 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1248 | } |
1249 | ||
018aabb5 TY |
1250 | static bool __rmap_write_protect(struct kvm *kvm, |
1251 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1252 | bool pt_protect) |
98348e95 | 1253 | { |
1e3f42f0 TY |
1254 | u64 *sptep; |
1255 | struct rmap_iterator iter; | |
d13bc5b5 | 1256 | bool flush = false; |
374cbac0 | 1257 | |
018aabb5 | 1258 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1259 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1260 | |
d13bc5b5 | 1261 | return flush; |
a0ed4607 TY |
1262 | } |
1263 | ||
c4f138b4 | 1264 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1265 | { |
1266 | u64 spte = *sptep; | |
1267 | ||
805a0f83 | 1268 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
f4b4b180 | 1269 | |
1f4e5fc8 | 1270 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1271 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1272 | return mmu_spte_update(sptep, spte); |
1273 | } | |
1274 | ||
1f4e5fc8 | 1275 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1276 | { |
1277 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1278 | (unsigned long *)sptep); | |
1f4e5fc8 | 1279 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1280 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1281 | ||
1282 | return was_writable; | |
1283 | } | |
1284 | ||
1285 | /* | |
1286 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1287 | * - D bit on ad-enabled SPTEs, and | |
1288 | * - W bit on ad-disabled SPTEs. | |
1289 | * Returns true iff any D or W bits were cleared. | |
1290 | */ | |
0a234f5d | 1291 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
269e9552 | 1292 | const struct kvm_memory_slot *slot) |
f4b4b180 KH |
1293 | { |
1294 | u64 *sptep; | |
1295 | struct rmap_iterator iter; | |
1296 | bool flush = false; | |
1297 | ||
018aabb5 | 1298 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1299 | if (spte_ad_need_write_protect(*sptep)) |
1300 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1301 | else |
1f4e5fc8 | 1302 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1303 | |
1304 | return flush; | |
1305 | } | |
1306 | ||
5dc99b23 | 1307 | /** |
3b0f1d01 | 1308 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1309 | * @kvm: kvm instance |
1310 | * @slot: slot to protect | |
1311 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1312 | * @mask: indicates which pages we should protect | |
1313 | * | |
89212919 | 1314 | * Used when we do not need to care about huge page mappings. |
5dc99b23 | 1315 | */ |
3b0f1d01 | 1316 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1317 | struct kvm_memory_slot *slot, |
1318 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1319 | { |
018aabb5 | 1320 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1321 | |
897218ff | 1322 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1323 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1324 | slot->base_gfn + gfn_offset, mask, true); | |
e2209710 BG |
1325 | |
1326 | if (!kvm_memslots_have_rmaps(kvm)) | |
1327 | return; | |
1328 | ||
5dc99b23 | 1329 | while (mask) { |
93e083d4 DM |
1330 | rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1331 | PG_LEVEL_4K, slot); | |
018aabb5 | 1332 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1333 | |
5dc99b23 TY |
1334 | /* clear the first set bit */ |
1335 | mask &= mask - 1; | |
1336 | } | |
374cbac0 AK |
1337 | } |
1338 | ||
f4b4b180 | 1339 | /** |
ac8d57e5 PF |
1340 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1341 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1342 | * @kvm: kvm instance |
1343 | * @slot: slot to clear D-bit | |
1344 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1345 | * @mask: indicates which pages we should clear D-bit | |
1346 | * | |
1347 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1348 | */ | |
a018eba5 SC |
1349 | static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, |
1350 | struct kvm_memory_slot *slot, | |
1351 | gfn_t gfn_offset, unsigned long mask) | |
f4b4b180 | 1352 | { |
018aabb5 | 1353 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1354 | |
897218ff | 1355 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1356 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1357 | slot->base_gfn + gfn_offset, mask, false); | |
e2209710 BG |
1358 | |
1359 | if (!kvm_memslots_have_rmaps(kvm)) | |
1360 | return; | |
1361 | ||
f4b4b180 | 1362 | while (mask) { |
93e083d4 DM |
1363 | rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1364 | PG_LEVEL_4K, slot); | |
0a234f5d | 1365 | __rmap_clear_dirty(kvm, rmap_head, slot); |
f4b4b180 KH |
1366 | |
1367 | /* clear the first set bit */ | |
1368 | mask &= mask - 1; | |
1369 | } | |
1370 | } | |
f4b4b180 | 1371 | |
3b0f1d01 KH |
1372 | /** |
1373 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1374 | * PT level pages. | |
1375 | * | |
1376 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1377 | * enable dirty logging for them. | |
1378 | * | |
89212919 KZ |
1379 | * We need to care about huge page mappings: e.g. during dirty logging we may |
1380 | * have such mappings. | |
3b0f1d01 KH |
1381 | */ |
1382 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1383 | struct kvm_memory_slot *slot, | |
1384 | gfn_t gfn_offset, unsigned long mask) | |
1385 | { | |
89212919 KZ |
1386 | /* |
1387 | * Huge pages are NOT write protected when we start dirty logging in | |
1388 | * initially-all-set mode; must write protect them here so that they | |
1389 | * are split to 4K on the first write. | |
1390 | * | |
1391 | * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn | |
1392 | * of memslot has no such restriction, so the range can cross two large | |
1393 | * pages. | |
1394 | */ | |
1395 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
1396 | gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask); | |
1397 | gfn_t end = slot->base_gfn + gfn_offset + __fls(mask); | |
1398 | ||
1399 | kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M); | |
1400 | ||
1401 | /* Cross two large pages? */ | |
1402 | if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) != | |
1403 | ALIGN(end << PAGE_SHIFT, PMD_SIZE)) | |
1404 | kvm_mmu_slot_gfn_write_protect(kvm, slot, end, | |
1405 | PG_LEVEL_2M); | |
1406 | } | |
1407 | ||
1408 | /* Now handle 4K PTEs. */ | |
a018eba5 SC |
1409 | if (kvm_x86_ops.cpu_dirty_log_size) |
1410 | kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask); | |
88178fd4 KH |
1411 | else |
1412 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1413 | } |
1414 | ||
fb04a1ed PX |
1415 | int kvm_cpu_dirty_log_size(void) |
1416 | { | |
6dd03800 | 1417 | return kvm_x86_ops.cpu_dirty_log_size; |
fb04a1ed PX |
1418 | } |
1419 | ||
aeecee2e | 1420 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
3ad93562 KZ |
1421 | struct kvm_memory_slot *slot, u64 gfn, |
1422 | int min_level) | |
95d4c16c | 1423 | { |
018aabb5 | 1424 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1425 | int i; |
2f84569f | 1426 | bool write_protected = false; |
95d4c16c | 1427 | |
e2209710 BG |
1428 | if (kvm_memslots_have_rmaps(kvm)) { |
1429 | for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { | |
93e083d4 | 1430 | rmap_head = gfn_to_rmap(gfn, i, slot); |
e2209710 BG |
1431 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
1432 | } | |
5dc99b23 TY |
1433 | } |
1434 | ||
897218ff | 1435 | if (is_tdp_mmu_enabled(kvm)) |
46044f72 | 1436 | write_protected |= |
3ad93562 | 1437 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level); |
46044f72 | 1438 | |
5dc99b23 | 1439 | return write_protected; |
95d4c16c TY |
1440 | } |
1441 | ||
aeecee2e XG |
1442 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1443 | { | |
1444 | struct kvm_memory_slot *slot; | |
1445 | ||
1446 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
3ad93562 | 1447 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K); |
aeecee2e XG |
1448 | } |
1449 | ||
0a234f5d | 1450 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
269e9552 | 1451 | const struct kvm_memory_slot *slot) |
e930bffe | 1452 | { |
a75b5404 | 1453 | return pte_list_destroy(rmap_head); |
6a49f85c XG |
1454 | } |
1455 | ||
3039bcc7 SC |
1456 | static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1457 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1458 | pte_t unused) | |
6a49f85c | 1459 | { |
0a234f5d | 1460 | return kvm_zap_rmapp(kvm, rmap_head, slot); |
e930bffe AA |
1461 | } |
1462 | ||
3039bcc7 SC |
1463 | static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1464 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1465 | pte_t pte) | |
3da0dd43 | 1466 | { |
1e3f42f0 TY |
1467 | u64 *sptep; |
1468 | struct rmap_iterator iter; | |
3da0dd43 | 1469 | int need_flush = 0; |
1e3f42f0 | 1470 | u64 new_spte; |
ba049e93 | 1471 | kvm_pfn_t new_pfn; |
3da0dd43 | 1472 | |
3039bcc7 SC |
1473 | WARN_ON(pte_huge(pte)); |
1474 | new_pfn = pte_pfn(pte); | |
1e3f42f0 | 1475 | |
0d536790 | 1476 | restart: |
018aabb5 | 1477 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
805a0f83 | 1478 | rmap_printk("spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1479 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1480 | |
3da0dd43 | 1481 | need_flush = 1; |
1e3f42f0 | 1482 | |
3039bcc7 | 1483 | if (pte_write(pte)) { |
e7912386 | 1484 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1485 | goto restart; |
3da0dd43 | 1486 | } else { |
cb3eedab PB |
1487 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1488 | *sptep, new_pfn); | |
1e3f42f0 TY |
1489 | |
1490 | mmu_spte_clear_track_bits(sptep); | |
1491 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1492 | } |
1493 | } | |
1e3f42f0 | 1494 | |
3cc5ea94 LT |
1495 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1496 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1497 | return 0; | |
1498 | } | |
1499 | ||
0cf853c5 | 1500 | return need_flush; |
3da0dd43 IE |
1501 | } |
1502 | ||
6ce1f4e2 XG |
1503 | struct slot_rmap_walk_iterator { |
1504 | /* input fields. */ | |
269e9552 | 1505 | const struct kvm_memory_slot *slot; |
6ce1f4e2 XG |
1506 | gfn_t start_gfn; |
1507 | gfn_t end_gfn; | |
1508 | int start_level; | |
1509 | int end_level; | |
1510 | ||
1511 | /* output fields. */ | |
1512 | gfn_t gfn; | |
018aabb5 | 1513 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1514 | int level; |
1515 | ||
1516 | /* private field. */ | |
018aabb5 | 1517 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1518 | }; |
1519 | ||
1520 | static void | |
1521 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1522 | { | |
1523 | iterator->level = level; | |
1524 | iterator->gfn = iterator->start_gfn; | |
93e083d4 DM |
1525 | iterator->rmap = gfn_to_rmap(iterator->gfn, level, iterator->slot); |
1526 | iterator->end_rmap = gfn_to_rmap(iterator->end_gfn, level, iterator->slot); | |
6ce1f4e2 XG |
1527 | } |
1528 | ||
1529 | static void | |
1530 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
269e9552 | 1531 | const struct kvm_memory_slot *slot, int start_level, |
6ce1f4e2 XG |
1532 | int end_level, gfn_t start_gfn, gfn_t end_gfn) |
1533 | { | |
1534 | iterator->slot = slot; | |
1535 | iterator->start_level = start_level; | |
1536 | iterator->end_level = end_level; | |
1537 | iterator->start_gfn = start_gfn; | |
1538 | iterator->end_gfn = end_gfn; | |
1539 | ||
1540 | rmap_walk_init_level(iterator, iterator->start_level); | |
1541 | } | |
1542 | ||
1543 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1544 | { | |
1545 | return !!iterator->rmap; | |
1546 | } | |
1547 | ||
1548 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1549 | { | |
1550 | if (++iterator->rmap <= iterator->end_rmap) { | |
1551 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1552 | return; | |
1553 | } | |
1554 | ||
1555 | if (++iterator->level > iterator->end_level) { | |
1556 | iterator->rmap = NULL; | |
1557 | return; | |
1558 | } | |
1559 | ||
1560 | rmap_walk_init_level(iterator, iterator->level); | |
1561 | } | |
1562 | ||
1563 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1564 | _start_gfn, _end_gfn, _iter_) \ | |
1565 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1566 | _end_level_, _start_gfn, _end_gfn); \ | |
1567 | slot_rmap_walk_okay(_iter_); \ | |
1568 | slot_rmap_walk_next(_iter_)) | |
1569 | ||
3039bcc7 SC |
1570 | typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1571 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1572 | int level, pte_t pte); | |
c1b91493 | 1573 | |
3039bcc7 SC |
1574 | static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm, |
1575 | struct kvm_gfn_range *range, | |
1576 | rmap_handler_t handler) | |
e930bffe | 1577 | { |
6ce1f4e2 | 1578 | struct slot_rmap_walk_iterator iterator; |
3039bcc7 | 1579 | bool ret = false; |
e930bffe | 1580 | |
3039bcc7 SC |
1581 | for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL, |
1582 | range->start, range->end - 1, &iterator) | |
1583 | ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn, | |
1584 | iterator.level, range->pte); | |
e930bffe | 1585 | |
f395302e | 1586 | return ret; |
e930bffe AA |
1587 | } |
1588 | ||
3039bcc7 | 1589 | bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range) |
84504ef3 | 1590 | { |
e2209710 | 1591 | bool flush = false; |
063afacd | 1592 | |
e2209710 BG |
1593 | if (kvm_memslots_have_rmaps(kvm)) |
1594 | flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp); | |
063afacd | 1595 | |
897218ff | 1596 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1597 | flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush); |
063afacd | 1598 | |
3039bcc7 | 1599 | return flush; |
b3ae2096 TY |
1600 | } |
1601 | ||
3039bcc7 | 1602 | bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
3da0dd43 | 1603 | { |
e2209710 | 1604 | bool flush = false; |
1d8dd6b3 | 1605 | |
e2209710 BG |
1606 | if (kvm_memslots_have_rmaps(kvm)) |
1607 | flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp); | |
1d8dd6b3 | 1608 | |
897218ff | 1609 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1610 | flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range); |
1d8dd6b3 | 1611 | |
3039bcc7 | 1612 | return flush; |
e930bffe AA |
1613 | } |
1614 | ||
3039bcc7 SC |
1615 | static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1616 | struct kvm_memory_slot *slot, gfn_t gfn, int level, | |
1617 | pte_t unused) | |
e930bffe | 1618 | { |
1e3f42f0 | 1619 | u64 *sptep; |
3f649ab7 | 1620 | struct rmap_iterator iter; |
e930bffe AA |
1621 | int young = 0; |
1622 | ||
f160c7b7 JS |
1623 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1624 | young |= mmu_spte_age(sptep); | |
0d536790 | 1625 | |
e930bffe AA |
1626 | return young; |
1627 | } | |
1628 | ||
3039bcc7 SC |
1629 | static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1630 | struct kvm_memory_slot *slot, gfn_t gfn, | |
1631 | int level, pte_t unused) | |
8ee53820 | 1632 | { |
1e3f42f0 TY |
1633 | u64 *sptep; |
1634 | struct rmap_iterator iter; | |
8ee53820 | 1635 | |
83ef6c81 JS |
1636 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1637 | if (is_accessed_spte(*sptep)) | |
1638 | return 1; | |
83ef6c81 | 1639 | return 0; |
8ee53820 AA |
1640 | } |
1641 | ||
53a27b39 MT |
1642 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1643 | ||
852e3c19 | 1644 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1645 | { |
601f8af0 | 1646 | struct kvm_memory_slot *slot; |
018aabb5 | 1647 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1648 | struct kvm_mmu_page *sp; |
1649 | ||
57354682 | 1650 | sp = sptep_to_sp(spte); |
601f8af0 | 1651 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
93e083d4 | 1652 | rmap_head = gfn_to_rmap(gfn, sp->role.level, slot); |
53a27b39 | 1653 | |
3039bcc7 | 1654 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0)); |
c3134ce2 LT |
1655 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1656 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1657 | } |
1658 | ||
3039bcc7 | 1659 | bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
e930bffe | 1660 | { |
e2209710 | 1661 | bool young = false; |
3039bcc7 | 1662 | |
e2209710 BG |
1663 | if (kvm_memslots_have_rmaps(kvm)) |
1664 | young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp); | |
f8e14497 | 1665 | |
897218ff | 1666 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1667 | young |= kvm_tdp_mmu_age_gfn_range(kvm, range); |
f8e14497 BG |
1668 | |
1669 | return young; | |
e930bffe AA |
1670 | } |
1671 | ||
3039bcc7 | 1672 | bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range) |
8ee53820 | 1673 | { |
e2209710 | 1674 | bool young = false; |
3039bcc7 | 1675 | |
e2209710 BG |
1676 | if (kvm_memslots_have_rmaps(kvm)) |
1677 | young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp); | |
f8e14497 | 1678 | |
897218ff | 1679 | if (is_tdp_mmu_enabled(kvm)) |
3039bcc7 | 1680 | young |= kvm_tdp_mmu_test_age_gfn(kvm, range); |
f8e14497 BG |
1681 | |
1682 | return young; | |
8ee53820 AA |
1683 | } |
1684 | ||
d6c69ee9 | 1685 | #ifdef MMU_DEBUG |
47ad8e68 | 1686 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1687 | { |
139bdb2d AK |
1688 | u64 *pos; |
1689 | u64 *end; | |
1690 | ||
47ad8e68 | 1691 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1692 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1693 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1694 | pos, *pos); |
6aa8b732 | 1695 | return 0; |
139bdb2d | 1696 | } |
6aa8b732 AK |
1697 | return 1; |
1698 | } | |
d6c69ee9 | 1699 | #endif |
6aa8b732 | 1700 | |
45221ab6 DH |
1701 | /* |
1702 | * This value is the sum of all of the kvm instances's | |
1703 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1704 | * aggregate version in order to make the slab shrinker | |
1705 | * faster | |
1706 | */ | |
d5aaad6f | 1707 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr) |
45221ab6 DH |
1708 | { |
1709 | kvm->arch.n_used_mmu_pages += nr; | |
1710 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1711 | } | |
1712 | ||
834be0d8 | 1713 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1714 | { |
fa4a2c08 | 1715 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1716 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1717 | list_del(&sp->link); |
1718 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1719 | if (!sp->role.direct) |
1720 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1721 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1722 | } |
1723 | ||
cea0f0e7 AK |
1724 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1725 | { | |
114df303 | 1726 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1727 | } |
1728 | ||
714b93da | 1729 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1730 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1731 | { |
cea0f0e7 AK |
1732 | if (!parent_pte) |
1733 | return; | |
cea0f0e7 | 1734 | |
67052b35 | 1735 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1736 | } |
1737 | ||
4db35314 | 1738 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1739 | u64 *parent_pte) |
1740 | { | |
8daf3462 | 1741 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1742 | } |
1743 | ||
bcdd9a93 XG |
1744 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1745 | u64 *parent_pte) | |
1746 | { | |
1747 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1748 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1749 | } |
1750 | ||
47005792 | 1751 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1752 | { |
67052b35 | 1753 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1754 | |
94ce87ef SC |
1755 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1756 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1757 | if (!direct) |
94ce87ef | 1758 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1759 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1760 | |
1761 | /* | |
1762 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1763 | * depends on valid pages being added to the head of the list. See | |
1764 | * comments in kvm_zap_obsolete_pages(). | |
1765 | */ | |
ca333add | 1766 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1767 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1768 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1769 | return sp; | |
ad8cfbe3 MT |
1770 | } |
1771 | ||
67052b35 | 1772 | static void mark_unsync(u64 *spte); |
1047df1f | 1773 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1774 | { |
74c4e63a TY |
1775 | u64 *sptep; |
1776 | struct rmap_iterator iter; | |
1777 | ||
1778 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1779 | mark_unsync(sptep); | |
1780 | } | |
0074ff63 MT |
1781 | } |
1782 | ||
67052b35 | 1783 | static void mark_unsync(u64 *spte) |
0074ff63 | 1784 | { |
67052b35 | 1785 | struct kvm_mmu_page *sp; |
1047df1f | 1786 | unsigned int index; |
0074ff63 | 1787 | |
57354682 | 1788 | sp = sptep_to_sp(spte); |
1047df1f XG |
1789 | index = spte - sp->spt; |
1790 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1791 | return; |
1047df1f | 1792 | if (sp->unsync_children++) |
0074ff63 | 1793 | return; |
1047df1f | 1794 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1795 | } |
1796 | ||
e8bc217a | 1797 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1798 | struct kvm_mmu_page *sp) |
e8bc217a | 1799 | { |
1f50f1b3 | 1800 | return 0; |
e8bc217a MT |
1801 | } |
1802 | ||
60c8aec6 MT |
1803 | #define KVM_PAGE_ARRAY_NR 16 |
1804 | ||
1805 | struct kvm_mmu_pages { | |
1806 | struct mmu_page_and_offset { | |
1807 | struct kvm_mmu_page *sp; | |
1808 | unsigned int idx; | |
1809 | } page[KVM_PAGE_ARRAY_NR]; | |
1810 | unsigned int nr; | |
1811 | }; | |
1812 | ||
cded19f3 HE |
1813 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1814 | int idx) | |
4731d4c7 | 1815 | { |
60c8aec6 | 1816 | int i; |
4731d4c7 | 1817 | |
60c8aec6 MT |
1818 | if (sp->unsync) |
1819 | for (i=0; i < pvec->nr; i++) | |
1820 | if (pvec->page[i].sp == sp) | |
1821 | return 0; | |
1822 | ||
1823 | pvec->page[pvec->nr].sp = sp; | |
1824 | pvec->page[pvec->nr].idx = idx; | |
1825 | pvec->nr++; | |
1826 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1827 | } | |
1828 | ||
fd951457 TY |
1829 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1830 | { | |
1831 | --sp->unsync_children; | |
1832 | WARN_ON((int)sp->unsync_children < 0); | |
1833 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1834 | } | |
1835 | ||
60c8aec6 MT |
1836 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1837 | struct kvm_mmu_pages *pvec) | |
1838 | { | |
1839 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1840 | |
37178b8b | 1841 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1842 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1843 | u64 ent = sp->spt[i]; |
1844 | ||
fd951457 TY |
1845 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1846 | clear_unsync_child_bit(sp, i); | |
1847 | continue; | |
1848 | } | |
7a8f1a74 | 1849 | |
e47c4aee | 1850 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1851 | |
1852 | if (child->unsync_children) { | |
1853 | if (mmu_pages_add(pvec, child, i)) | |
1854 | return -ENOSPC; | |
1855 | ||
1856 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1857 | if (!ret) { |
1858 | clear_unsync_child_bit(sp, i); | |
1859 | continue; | |
1860 | } else if (ret > 0) { | |
7a8f1a74 | 1861 | nr_unsync_leaf += ret; |
fd951457 | 1862 | } else |
7a8f1a74 XG |
1863 | return ret; |
1864 | } else if (child->unsync) { | |
1865 | nr_unsync_leaf++; | |
1866 | if (mmu_pages_add(pvec, child, i)) | |
1867 | return -ENOSPC; | |
1868 | } else | |
fd951457 | 1869 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1870 | } |
1871 | ||
60c8aec6 MT |
1872 | return nr_unsync_leaf; |
1873 | } | |
1874 | ||
e23d3fef XG |
1875 | #define INVALID_INDEX (-1) |
1876 | ||
60c8aec6 MT |
1877 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1878 | struct kvm_mmu_pages *pvec) | |
1879 | { | |
0a47cd85 | 1880 | pvec->nr = 0; |
60c8aec6 MT |
1881 | if (!sp->unsync_children) |
1882 | return 0; | |
1883 | ||
e23d3fef | 1884 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1885 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1886 | } |
1887 | ||
4731d4c7 MT |
1888 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1889 | { | |
1890 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1891 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1892 | sp->unsync = 0; |
1893 | --kvm->stat.mmu_unsync; | |
1894 | } | |
1895 | ||
83cdb568 SC |
1896 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1897 | struct list_head *invalid_list); | |
7775834a XG |
1898 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1899 | struct list_head *invalid_list); | |
4731d4c7 | 1900 | |
ac101b7c SC |
1901 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1902 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1903 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1904 | } else |
1044b030 TY |
1905 | |
1906 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1907 | for_each_valid_sp(_kvm, _sp, \ |
1908 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1909 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1910 | |
479a1efc SC |
1911 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1912 | struct list_head *invalid_list) | |
4731d4c7 | 1913 | { |
2640b086 | 1914 | if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 1915 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1916 | return false; |
4731d4c7 MT |
1917 | } |
1918 | ||
1f50f1b3 | 1919 | return true; |
4731d4c7 MT |
1920 | } |
1921 | ||
a2113634 SC |
1922 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1923 | struct list_head *invalid_list, | |
1924 | bool remote_flush) | |
1925 | { | |
cfd32acf | 1926 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1927 | return false; |
1928 | ||
1929 | if (!list_empty(invalid_list)) | |
1930 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1931 | else | |
1932 | kvm_flush_remote_tlbs(kvm); | |
1933 | return true; | |
1934 | } | |
1935 | ||
35a70510 PB |
1936 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1937 | struct list_head *invalid_list, | |
1938 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1939 | { |
a2113634 | 1940 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1941 | return; |
d98ba053 | 1942 | |
a2113634 | 1943 | if (local_flush) |
8c8560b8 | 1944 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1945 | } |
1946 | ||
e37fa785 XG |
1947 | #ifdef CONFIG_KVM_MMU_AUDIT |
1948 | #include "mmu_audit.c" | |
1949 | #else | |
1950 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1951 | static void mmu_audit_disable(void) { } | |
1952 | #endif | |
1953 | ||
002c5f73 SC |
1954 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1955 | { | |
fac026da SC |
1956 | return sp->role.invalid || |
1957 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1958 | } |
1959 | ||
60c8aec6 | 1960 | struct mmu_page_path { |
2a7266a8 YZ |
1961 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1962 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1963 | }; |
1964 | ||
60c8aec6 | 1965 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1966 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1967 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1968 | i = mmu_pages_next(&pvec, &parents, i)) | |
1969 | ||
cded19f3 HE |
1970 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1971 | struct mmu_page_path *parents, | |
1972 | int i) | |
60c8aec6 MT |
1973 | { |
1974 | int n; | |
1975 | ||
1976 | for (n = i+1; n < pvec->nr; n++) { | |
1977 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1978 | unsigned idx = pvec->page[n].idx; |
1979 | int level = sp->role.level; | |
60c8aec6 | 1980 | |
0a47cd85 | 1981 | parents->idx[level-1] = idx; |
3bae0459 | 1982 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1983 | break; |
60c8aec6 | 1984 | |
0a47cd85 | 1985 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1986 | } |
1987 | ||
1988 | return n; | |
1989 | } | |
1990 | ||
0a47cd85 PB |
1991 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1992 | struct mmu_page_path *parents) | |
1993 | { | |
1994 | struct kvm_mmu_page *sp; | |
1995 | int level; | |
1996 | ||
1997 | if (pvec->nr == 0) | |
1998 | return 0; | |
1999 | ||
e23d3fef XG |
2000 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2001 | ||
0a47cd85 PB |
2002 | sp = pvec->page[0].sp; |
2003 | level = sp->role.level; | |
3bae0459 | 2004 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
2005 | |
2006 | parents->parent[level-2] = sp; | |
2007 | ||
2008 | /* Also set up a sentinel. Further entries in pvec are all | |
2009 | * children of sp, so this element is never overwritten. | |
2010 | */ | |
2011 | parents->parent[level-1] = NULL; | |
2012 | return mmu_pages_next(pvec, parents, 0); | |
2013 | } | |
2014 | ||
cded19f3 | 2015 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2016 | { |
60c8aec6 MT |
2017 | struct kvm_mmu_page *sp; |
2018 | unsigned int level = 0; | |
2019 | ||
2020 | do { | |
2021 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2022 | sp = parents->parent[level]; |
2023 | if (!sp) | |
2024 | return; | |
2025 | ||
e23d3fef | 2026 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2027 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2028 | level++; |
0a47cd85 | 2029 | } while (!sp->unsync_children); |
60c8aec6 | 2030 | } |
4731d4c7 | 2031 | |
60c8aec6 MT |
2032 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2033 | struct kvm_mmu_page *parent) | |
2034 | { | |
2035 | int i; | |
2036 | struct kvm_mmu_page *sp; | |
2037 | struct mmu_page_path parents; | |
2038 | struct kvm_mmu_pages pages; | |
d98ba053 | 2039 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2040 | bool flush = false; |
60c8aec6 | 2041 | |
60c8aec6 | 2042 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2043 | bool protected = false; |
b1a36821 MT |
2044 | |
2045 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2046 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2047 | |
50c9e6f3 | 2048 | if (protected) { |
b1a36821 | 2049 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2050 | flush = false; |
2051 | } | |
b1a36821 | 2052 | |
60c8aec6 | 2053 | for_each_sp(pages, sp, parents, i) { |
479a1efc | 2054 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1f50f1b3 | 2055 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2056 | mmu_pages_clear_parents(&parents); |
2057 | } | |
531810ca | 2058 | if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) { |
50c9e6f3 | 2059 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); |
531810ca | 2060 | cond_resched_rwlock_write(&vcpu->kvm->mmu_lock); |
50c9e6f3 PB |
2061 | flush = false; |
2062 | } | |
60c8aec6 | 2063 | } |
50c9e6f3 PB |
2064 | |
2065 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2066 | } |
2067 | ||
a30f47cb XG |
2068 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2069 | { | |
e5691a81 | 2070 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2071 | } |
2072 | ||
2073 | static void clear_sp_write_flooding_count(u64 *spte) | |
2074 | { | |
57354682 | 2075 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
2076 | } |
2077 | ||
cea0f0e7 AK |
2078 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2079 | gfn_t gfn, | |
2080 | gva_t gaddr, | |
2081 | unsigned level, | |
f6e2c02b | 2082 | int direct, |
0a2b64c5 | 2083 | unsigned int access) |
cea0f0e7 | 2084 | { |
fb58a9c3 | 2085 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2086 | union kvm_mmu_page_role role; |
ac101b7c | 2087 | struct hlist_head *sp_list; |
cea0f0e7 | 2088 | unsigned quadrant; |
9f1a122f | 2089 | struct kvm_mmu_page *sp; |
f3414bc7 | 2090 | int collisions = 0; |
2a74003a | 2091 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2092 | |
36d9594d | 2093 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2094 | role.level = level; |
f6e2c02b | 2095 | role.direct = direct; |
84b0c8c6 | 2096 | if (role.direct) |
47c42e6b | 2097 | role.gpte_is_8_bytes = true; |
41074d07 | 2098 | role.access = access; |
fb58a9c3 | 2099 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2100 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2101 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2102 | role.quadrant = quadrant; | |
2103 | } | |
ac101b7c SC |
2104 | |
2105 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2106 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2107 | if (sp->gfn != gfn) { |
2108 | collisions++; | |
2109 | continue; | |
2110 | } | |
2111 | ||
ddc16abb SC |
2112 | if (sp->role.word != role.word) { |
2113 | /* | |
2114 | * If the guest is creating an upper-level page, zap | |
2115 | * unsync pages for the same gfn. While it's possible | |
2116 | * the guest is using recursive page tables, in all | |
2117 | * likelihood the guest has stopped using the unsync | |
2118 | * page and is installing a completely unrelated page. | |
2119 | * Unsync pages must not be left as is, because the new | |
2120 | * upper-level page will be write-protected. | |
2121 | */ | |
2122 | if (level > PG_LEVEL_4K && sp->unsync) | |
2123 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, | |
2124 | &invalid_list); | |
7ae680eb | 2125 | continue; |
ddc16abb | 2126 | } |
4731d4c7 | 2127 | |
fb58a9c3 SC |
2128 | if (direct_mmu) |
2129 | goto trace_get_page; | |
2130 | ||
2a74003a | 2131 | if (sp->unsync) { |
07dc4f35 | 2132 | /* |
479a1efc | 2133 | * The page is good, but is stale. kvm_sync_page does |
07dc4f35 SC |
2134 | * get the latest guest state, but (unlike mmu_unsync_children) |
2135 | * it doesn't write-protect the page or mark it synchronized! | |
2136 | * This way the validity of the mapping is ensured, but the | |
2137 | * overhead of write protection is not incurred until the | |
2138 | * guest invalidates the TLB mapping. This allows multiple | |
2139 | * SPs for a single gfn to be unsync. | |
2140 | * | |
2141 | * If the sync fails, the page is zapped. If so, break | |
2142 | * in order to rebuild it. | |
2a74003a | 2143 | */ |
479a1efc | 2144 | if (!kvm_sync_page(vcpu, sp, &invalid_list)) |
2a74003a PB |
2145 | break; |
2146 | ||
2147 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2148 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2149 | } |
e02aa901 | 2150 | |
98bba238 | 2151 | if (sp->unsync_children) |
f6f6195b | 2152 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2153 | |
a30f47cb | 2154 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2155 | |
2156 | trace_get_page: | |
7ae680eb | 2157 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2158 | goto out; |
7ae680eb | 2159 | } |
47005792 | 2160 | |
dfc5aa00 | 2161 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2162 | |
2163 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2164 | ||
4db35314 AK |
2165 | sp->gfn = gfn; |
2166 | sp->role = role; | |
ac101b7c | 2167 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2168 | if (!direct) { |
56ca57f9 | 2169 | account_shadowed(vcpu->kvm, sp); |
3bae0459 | 2170 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2171 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
4731d4c7 | 2172 | } |
f691fe1d | 2173 | trace_kvm_mmu_get_page(sp, true); |
f3414bc7 | 2174 | out: |
ddc16abb SC |
2175 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
2176 | ||
f3414bc7 DM |
2177 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) |
2178 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2179 | return sp; |
cea0f0e7 AK |
2180 | } |
2181 | ||
7eb77e9f JS |
2182 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2183 | struct kvm_vcpu *vcpu, hpa_t root, | |
2184 | u64 addr) | |
2d11123a AK |
2185 | { |
2186 | iterator->addr = addr; | |
7eb77e9f | 2187 | iterator->shadow_addr = root; |
44dd3ffa | 2188 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2189 | |
2a7266a8 | 2190 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2191 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2192 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2193 | --iterator->level; |
2194 | ||
2d11123a | 2195 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2196 | /* |
2197 | * prev_root is currently only used for 64-bit hosts. So only | |
2198 | * the active root_hpa is valid here. | |
2199 | */ | |
44dd3ffa | 2200 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2201 | |
2d11123a | 2202 | iterator->shadow_addr |
44dd3ffa | 2203 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2204 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2205 | --iterator->level; | |
2206 | if (!iterator->shadow_addr) | |
2207 | iterator->level = 0; | |
2208 | } | |
2209 | } | |
2210 | ||
7eb77e9f JS |
2211 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2212 | struct kvm_vcpu *vcpu, u64 addr) | |
2213 | { | |
44dd3ffa | 2214 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2215 | addr); |
2216 | } | |
2217 | ||
2d11123a AK |
2218 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2219 | { | |
3bae0459 | 2220 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2221 | return false; |
4d88954d | 2222 | |
2d11123a AK |
2223 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2224 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2225 | return true; | |
2226 | } | |
2227 | ||
c2a2ac2b XG |
2228 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2229 | u64 spte) | |
2d11123a | 2230 | { |
c2a2ac2b | 2231 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2232 | iterator->level = 0; |
2233 | return; | |
2234 | } | |
2235 | ||
c2a2ac2b | 2236 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2237 | --iterator->level; |
2238 | } | |
2239 | ||
c2a2ac2b XG |
2240 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2241 | { | |
bb606a9b | 2242 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2243 | } |
2244 | ||
cc4674d0 BG |
2245 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2246 | struct kvm_mmu_page *sp) | |
2247 | { | |
2248 | u64 spte; | |
2249 | ||
2250 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2251 | ||
2252 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2253 | ||
1df9f2dc | 2254 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2255 | |
2256 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2257 | ||
2258 | if (sp->unsync_children || sp->unsync) | |
2259 | mark_unsync(sptep); | |
32ef26a3 AK |
2260 | } |
2261 | ||
a357bd22 AK |
2262 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2263 | unsigned direct_access) | |
2264 | { | |
2265 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2266 | struct kvm_mmu_page *child; | |
2267 | ||
2268 | /* | |
2269 | * For the direct sp, if the guest pte's dirty bit | |
2270 | * changed form clean to dirty, it will corrupt the | |
2271 | * sp's access: allow writable in the read-only sp, | |
2272 | * so we should update the spte at this point to get | |
2273 | * a new sp with the correct access. | |
2274 | */ | |
e47c4aee | 2275 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2276 | if (child->role.access == direct_access) |
2277 | return; | |
2278 | ||
bcdd9a93 | 2279 | drop_parent_pte(child, sptep); |
c3134ce2 | 2280 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2281 | } |
2282 | } | |
2283 | ||
2de4085c BG |
2284 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2285 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2286 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2287 | { |
2288 | u64 pte; | |
2289 | struct kvm_mmu_page *child; | |
2290 | ||
2291 | pte = *spte; | |
2292 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2293 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2294 | drop_spte(kvm, spte); |
505aef8f XG |
2295 | if (is_large_pte(pte)) |
2296 | --kvm->stat.lpages; | |
2297 | } else { | |
e47c4aee | 2298 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2299 | drop_parent_pte(child, spte); |
2de4085c BG |
2300 | |
2301 | /* | |
2302 | * Recursively zap nested TDP SPs, parentless SPs are | |
2303 | * unlikely to be used again in the near future. This | |
2304 | * avoids retaining a large number of stale nested SPs. | |
2305 | */ | |
2306 | if (tdp_enabled && invalid_list && | |
2307 | child->role.guest_mode && !child->parent_ptes.val) | |
2308 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2309 | invalid_list); | |
38e3b2b2 | 2310 | } |
ace569e0 | 2311 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2312 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2313 | } |
2de4085c | 2314 | return 0; |
38e3b2b2 XG |
2315 | } |
2316 | ||
2de4085c BG |
2317 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2318 | struct kvm_mmu_page *sp, | |
2319 | struct list_head *invalid_list) | |
a436036b | 2320 | { |
2de4085c | 2321 | int zapped = 0; |
697fe2e2 | 2322 | unsigned i; |
697fe2e2 | 2323 | |
38e3b2b2 | 2324 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2325 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2326 | ||
2327 | return zapped; | |
a436036b AK |
2328 | } |
2329 | ||
31aa2b44 | 2330 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2331 | { |
1e3f42f0 TY |
2332 | u64 *sptep; |
2333 | struct rmap_iterator iter; | |
a436036b | 2334 | |
018aabb5 | 2335 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2336 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2337 | } |
2338 | ||
60c8aec6 | 2339 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2340 | struct kvm_mmu_page *parent, |
2341 | struct list_head *invalid_list) | |
4731d4c7 | 2342 | { |
60c8aec6 MT |
2343 | int i, zapped = 0; |
2344 | struct mmu_page_path parents; | |
2345 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2346 | |
3bae0459 | 2347 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2348 | return 0; |
60c8aec6 | 2349 | |
60c8aec6 MT |
2350 | while (mmu_unsync_walk(parent, &pages)) { |
2351 | struct kvm_mmu_page *sp; | |
2352 | ||
2353 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2354 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2355 | mmu_pages_clear_parents(&parents); |
77662e00 | 2356 | zapped++; |
60c8aec6 | 2357 | } |
60c8aec6 MT |
2358 | } |
2359 | ||
2360 | return zapped; | |
4731d4c7 MT |
2361 | } |
2362 | ||
83cdb568 SC |
2363 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2364 | struct kvm_mmu_page *sp, | |
2365 | struct list_head *invalid_list, | |
2366 | int *nr_zapped) | |
31aa2b44 | 2367 | { |
83cdb568 | 2368 | bool list_unstable; |
f691fe1d | 2369 | |
7775834a | 2370 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2371 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2372 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2373 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2374 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2375 | |
83cdb568 SC |
2376 | /* Zapping children means active_mmu_pages has become unstable. */ |
2377 | list_unstable = *nr_zapped; | |
2378 | ||
f6e2c02b | 2379 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2380 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2381 | |
4731d4c7 MT |
2382 | if (sp->unsync) |
2383 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2384 | if (!sp->root_count) { |
54a4f023 | 2385 | /* Count self */ |
83cdb568 | 2386 | (*nr_zapped)++; |
f95eec9b SC |
2387 | |
2388 | /* | |
2389 | * Already invalid pages (previously active roots) are not on | |
2390 | * the active page list. See list_del() in the "else" case of | |
2391 | * !sp->root_count. | |
2392 | */ | |
2393 | if (sp->role.invalid) | |
2394 | list_add(&sp->link, invalid_list); | |
2395 | else | |
2396 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2397 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2398 | } else { |
f95eec9b SC |
2399 | /* |
2400 | * Remove the active root from the active page list, the root | |
2401 | * will be explicitly freed when the root_count hits zero. | |
2402 | */ | |
2403 | list_del(&sp->link); | |
05988d72 | 2404 | |
10605204 SC |
2405 | /* |
2406 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2407 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2408 | * treats invalid shadow pages as being obsolete. | |
2409 | */ | |
2410 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2411 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2412 | } |
7775834a | 2413 | |
b8e8c830 PB |
2414 | if (sp->lpage_disallowed) |
2415 | unaccount_huge_nx_page(kvm, sp); | |
2416 | ||
7775834a | 2417 | sp->role.invalid = 1; |
83cdb568 SC |
2418 | return list_unstable; |
2419 | } | |
2420 | ||
2421 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2422 | struct list_head *invalid_list) | |
2423 | { | |
2424 | int nr_zapped; | |
2425 | ||
2426 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2427 | return nr_zapped; | |
a436036b AK |
2428 | } |
2429 | ||
7775834a XG |
2430 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2431 | struct list_head *invalid_list) | |
2432 | { | |
945315b9 | 2433 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2434 | |
2435 | if (list_empty(invalid_list)) | |
2436 | return; | |
2437 | ||
c142786c | 2438 | /* |
9753f529 LT |
2439 | * We need to make sure everyone sees our modifications to |
2440 | * the page tables and see changes to vcpu->mode here. The barrier | |
2441 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2442 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2443 | * | |
2444 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2445 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2446 | */ |
2447 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2448 | |
945315b9 | 2449 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2450 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2451 | kvm_mmu_free_page(sp); |
945315b9 | 2452 | } |
7775834a XG |
2453 | } |
2454 | ||
6b82ef2c SC |
2455 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2456 | unsigned long nr_to_zap) | |
5da59607 | 2457 | { |
6b82ef2c SC |
2458 | unsigned long total_zapped = 0; |
2459 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2460 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2461 | bool unstable; |
2462 | int nr_zapped; | |
5da59607 TY |
2463 | |
2464 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2465 | return 0; |
2466 | ||
6b82ef2c | 2467 | restart: |
8fc51726 | 2468 | list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) { |
6b82ef2c SC |
2469 | /* |
2470 | * Don't zap active root pages, the page itself can't be freed | |
2471 | * and zapping it will just force vCPUs to realloc and reload. | |
2472 | */ | |
2473 | if (sp->root_count) | |
2474 | continue; | |
2475 | ||
2476 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2477 | &nr_zapped); | |
2478 | total_zapped += nr_zapped; | |
2479 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2480 | break; |
2481 | ||
6b82ef2c SC |
2482 | if (unstable) |
2483 | goto restart; | |
ba7888dd | 2484 | } |
5da59607 | 2485 | |
6b82ef2c SC |
2486 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2487 | ||
2488 | kvm->stat.mmu_recycled += total_zapped; | |
2489 | return total_zapped; | |
2490 | } | |
2491 | ||
afe8d7e6 SC |
2492 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2493 | { | |
2494 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2495 | return kvm->arch.n_max_mmu_pages - | |
2496 | kvm->arch.n_used_mmu_pages; | |
2497 | ||
2498 | return 0; | |
5da59607 TY |
2499 | } |
2500 | ||
ba7888dd SC |
2501 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2502 | { | |
6b82ef2c | 2503 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2504 | |
6b82ef2c | 2505 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2506 | return 0; |
2507 | ||
6b82ef2c | 2508 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd | 2509 | |
6e6ec584 SC |
2510 | /* |
2511 | * Note, this check is intentionally soft, it only guarantees that one | |
2512 | * page is available, while the caller may end up allocating as many as | |
2513 | * four pages, e.g. for PAE roots or for 5-level paging. Temporarily | |
2514 | * exceeding the (arbitrary by default) limit will not harm the host, | |
c4342633 | 2515 | * being too aggressive may unnecessarily kill the guest, and getting an |
6e6ec584 SC |
2516 | * exact count is far more trouble than it's worth, especially in the |
2517 | * page fault paths. | |
2518 | */ | |
ba7888dd SC |
2519 | if (!kvm_mmu_available_pages(vcpu->kvm)) |
2520 | return -ENOSPC; | |
2521 | return 0; | |
2522 | } | |
2523 | ||
82ce2c96 IE |
2524 | /* |
2525 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2526 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2527 | */ |
bc8a3d89 | 2528 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2529 | { |
531810ca | 2530 | write_lock(&kvm->mmu_lock); |
b34cb590 | 2531 | |
49d5ca26 | 2532 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2533 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2534 | goal_nr_mmu_pages); | |
82ce2c96 | 2535 | |
49d5ca26 | 2536 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2537 | } |
82ce2c96 | 2538 | |
49d5ca26 | 2539 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 | 2540 | |
531810ca | 2541 | write_unlock(&kvm->mmu_lock); |
82ce2c96 IE |
2542 | } |
2543 | ||
1cb3f3ae | 2544 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2545 | { |
4db35314 | 2546 | struct kvm_mmu_page *sp; |
d98ba053 | 2547 | LIST_HEAD(invalid_list); |
a436036b AK |
2548 | int r; |
2549 | ||
9ad17b10 | 2550 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2551 | r = 0; |
531810ca | 2552 | write_lock(&kvm->mmu_lock); |
b67bfe0d | 2553 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2554 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2555 | sp->role.word); |
2556 | r = 1; | |
f41d335a | 2557 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2558 | } |
d98ba053 | 2559 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 2560 | write_unlock(&kvm->mmu_lock); |
1cb3f3ae | 2561 | |
a436036b | 2562 | return r; |
cea0f0e7 | 2563 | } |
96ad91ae SC |
2564 | |
2565 | static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) | |
2566 | { | |
2567 | gpa_t gpa; | |
2568 | int r; | |
2569 | ||
2570 | if (vcpu->arch.mmu->direct_map) | |
2571 | return 0; | |
2572 | ||
2573 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); | |
2574 | ||
2575 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2576 | ||
2577 | return r; | |
2578 | } | |
cea0f0e7 | 2579 | |
5c520e90 | 2580 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2581 | { |
2582 | trace_kvm_mmu_unsync_page(sp); | |
2583 | ++vcpu->kvm->stat.mmu_unsync; | |
2584 | sp->unsync = 1; | |
2585 | ||
2586 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2587 | } |
2588 | ||
0337f585 SC |
2589 | /* |
2590 | * Attempt to unsync any shadow pages that can be reached by the specified gfn, | |
2591 | * KVM is creating a writable mapping for said gfn. Returns 0 if all pages | |
2592 | * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must | |
2593 | * be write-protected. | |
2594 | */ | |
2595 | int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync) | |
4731d4c7 | 2596 | { |
5c520e90 | 2597 | struct kvm_mmu_page *sp; |
ce25681d | 2598 | bool locked = false; |
4731d4c7 | 2599 | |
0337f585 SC |
2600 | /* |
2601 | * Force write-protection if the page is being tracked. Note, the page | |
2602 | * track machinery is used to write-protect upper-level shadow pages, | |
2603 | * i.e. this guards the role.level == 4K assertion below! | |
2604 | */ | |
3d0c27ad | 2605 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
0337f585 | 2606 | return -EPERM; |
9cf5cf5a | 2607 | |
0337f585 SC |
2608 | /* |
2609 | * The page is not write-tracked, mark existing shadow pages unsync | |
2610 | * unless KVM is synchronizing an unsync SP (can_unsync = false). In | |
2611 | * that case, KVM must complete emulation of the guest TLB flush before | |
2612 | * allowing shadow pages to become unsync (writable by the guest). | |
2613 | */ | |
5c520e90 | 2614 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2615 | if (!can_unsync) |
0337f585 | 2616 | return -EPERM; |
36a2e677 | 2617 | |
5c520e90 XG |
2618 | if (sp->unsync) |
2619 | continue; | |
9cf5cf5a | 2620 | |
ce25681d SC |
2621 | /* |
2622 | * TDP MMU page faults require an additional spinlock as they | |
2623 | * run with mmu_lock held for read, not write, and the unsync | |
2624 | * logic is not thread safe. Take the spinklock regardless of | |
2625 | * the MMU type to avoid extra conditionals/parameters, there's | |
2626 | * no meaningful penalty if mmu_lock is held for write. | |
2627 | */ | |
2628 | if (!locked) { | |
2629 | locked = true; | |
2630 | spin_lock(&vcpu->kvm->arch.mmu_unsync_pages_lock); | |
2631 | ||
2632 | /* | |
2633 | * Recheck after taking the spinlock, a different vCPU | |
2634 | * may have since marked the page unsync. A false | |
2635 | * positive on the unprotected check above is not | |
2636 | * possible as clearing sp->unsync _must_ hold mmu_lock | |
2637 | * for write, i.e. unsync cannot transition from 0->1 | |
2638 | * while this CPU holds mmu_lock for read (or write). | |
2639 | */ | |
2640 | if (READ_ONCE(sp->unsync)) | |
2641 | continue; | |
2642 | } | |
2643 | ||
3bae0459 | 2644 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2645 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2646 | } |
ce25681d SC |
2647 | if (locked) |
2648 | spin_unlock(&vcpu->kvm->arch.mmu_unsync_pages_lock); | |
3d0c27ad | 2649 | |
578e1c4d JS |
2650 | /* |
2651 | * We need to ensure that the marking of unsync pages is visible | |
2652 | * before the SPTE is updated to allow writes because | |
2653 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2654 | * the MMU lock and so can race with this. If the SPTE was updated | |
2655 | * before the page had been marked as unsync-ed, something like the | |
2656 | * following could happen: | |
2657 | * | |
2658 | * CPU 1 CPU 2 | |
2659 | * --------------------------------------------------------------------- | |
2660 | * 1.2 Host updates SPTE | |
2661 | * to be writable | |
2662 | * 2.1 Guest writes a GPTE for GVA X. | |
2663 | * (GPTE being in the guest page table shadowed | |
2664 | * by the SP from CPU 1.) | |
2665 | * This reads SPTE during the page table walk. | |
2666 | * Since SPTE.W is read as 1, there is no | |
2667 | * fault. | |
2668 | * | |
2669 | * 2.2 Guest issues TLB flush. | |
2670 | * That causes a VM Exit. | |
2671 | * | |
0337f585 SC |
2672 | * 2.3 Walking of unsync pages sees sp->unsync is |
2673 | * false and skips the page. | |
578e1c4d JS |
2674 | * |
2675 | * 2.4 Guest accesses GVA X. | |
2676 | * Since the mapping in the SP was not updated, | |
2677 | * so the old mapping for GVA X incorrectly | |
2678 | * gets used. | |
2679 | * 1.1 Host marks SP | |
2680 | * as unsync | |
2681 | * (sp->unsync = true) | |
2682 | * | |
2683 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2684 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2685 | * pairs with this write barrier. | |
2686 | */ | |
2687 | smp_wmb(); | |
2688 | ||
0337f585 | 2689 | return 0; |
4731d4c7 MT |
2690 | } |
2691 | ||
799a4190 BG |
2692 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2693 | unsigned int pte_access, int level, | |
2694 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2695 | bool can_unsync, bool host_writable) | |
2696 | { | |
2697 | u64 spte; | |
2698 | struct kvm_mmu_page *sp; | |
2699 | int ret; | |
2700 | ||
799a4190 BG |
2701 | sp = sptep_to_sp(sptep); |
2702 | ||
2703 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2704 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2705 | ||
2706 | if (spte & PT_WRITABLE_MASK) | |
2707 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2708 | ||
12703759 SC |
2709 | if (*sptep == spte) |
2710 | ret |= SET_SPTE_SPURIOUS; | |
2711 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2712 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2713 | return ret; |
2714 | } | |
2715 | ||
0a2b64c5 | 2716 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2717 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2718 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2719 | bool host_writable) | |
1e73f9dd MT |
2720 | { |
2721 | int was_rmapped = 0; | |
53a27b39 | 2722 | int rmap_count; |
5ce4786f | 2723 | int set_spte_ret; |
c4371c2a | 2724 | int ret = RET_PF_FIXED; |
c2a4eadf | 2725 | bool flush = false; |
1e73f9dd | 2726 | |
f7616203 XG |
2727 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2728 | *sptep, write_fault, gfn); | |
1e73f9dd | 2729 | |
a54aa15c SC |
2730 | if (unlikely(is_noslot_pfn(pfn))) { |
2731 | mark_mmio_spte(vcpu, sptep, gfn, pte_access); | |
2732 | return RET_PF_EMULATE; | |
2733 | } | |
2734 | ||
afd28fe1 | 2735 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2736 | /* |
2737 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2738 | * the parent of the now unreachable PTE. | |
2739 | */ | |
3bae0459 | 2740 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2741 | struct kvm_mmu_page *child; |
d555c333 | 2742 | u64 pte = *sptep; |
1e73f9dd | 2743 | |
e47c4aee | 2744 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2745 | drop_parent_pte(child, sptep); |
c2a4eadf | 2746 | flush = true; |
d555c333 | 2747 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2748 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2749 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2750 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2751 | flush = true; |
6bed6b9e JR |
2752 | } else |
2753 | was_rmapped = 1; | |
1e73f9dd | 2754 | } |
852e3c19 | 2755 | |
5ce4786f JS |
2756 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2757 | speculative, true, host_writable); | |
2758 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2759 | if (write_fault) |
9b8ebbdb | 2760 | ret = RET_PF_EMULATE; |
8c8560b8 | 2761 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2762 | } |
c3134ce2 | 2763 | |
c2a4eadf | 2764 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2765 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2766 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2767 | |
12703759 SC |
2768 | /* |
2769 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2770 | * are identical, and emulation is not required. | |
2771 | */ | |
2772 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2773 | WARN_ON_ONCE(!was_rmapped); | |
2774 | return RET_PF_SPURIOUS; | |
2775 | } | |
2776 | ||
d555c333 | 2777 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2778 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2779 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2780 | ++vcpu->kvm->stat.lpages; |
2781 | ||
ffb61bb3 | 2782 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2783 | if (!was_rmapped) { |
2784 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
ec1cf69c PX |
2785 | if (rmap_count > vcpu->kvm->stat.max_mmu_rmap_size) |
2786 | vcpu->kvm->stat.max_mmu_rmap_size = rmap_count; | |
ffb61bb3 XG |
2787 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
2788 | rmap_recycle(vcpu, sptep, gfn); | |
2789 | } | |
1c4f1fd6 | 2790 | } |
cb9aaa30 | 2791 | |
9b8ebbdb | 2792 | return ret; |
1c4f1fd6 AK |
2793 | } |
2794 | ||
ba049e93 | 2795 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2796 | bool no_dirty_log) |
2797 | { | |
2798 | struct kvm_memory_slot *slot; | |
957ed9ef | 2799 | |
5d163b1c | 2800 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2801 | if (!slot) |
6c8ee57b | 2802 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2803 | |
037d92dc | 2804 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2805 | } |
2806 | ||
2807 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2808 | struct kvm_mmu_page *sp, | |
2809 | u64 *start, u64 *end) | |
2810 | { | |
2811 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2812 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2813 | unsigned int access = sp->role.access; |
957ed9ef XG |
2814 | int i, ret; |
2815 | gfn_t gfn; | |
2816 | ||
2817 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2818 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2819 | if (!slot) | |
957ed9ef XG |
2820 | return -1; |
2821 | ||
d9ef13c2 | 2822 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2823 | if (ret <= 0) |
2824 | return -1; | |
2825 | ||
43fdcda9 | 2826 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2827 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2828 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2829 | put_page(pages[i]); |
2830 | } | |
957ed9ef XG |
2831 | |
2832 | return 0; | |
2833 | } | |
2834 | ||
2835 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2836 | struct kvm_mmu_page *sp, u64 *sptep) | |
2837 | { | |
2838 | u64 *spte, *start = NULL; | |
2839 | int i; | |
2840 | ||
2841 | WARN_ON(!sp->role.direct); | |
2842 | ||
2843 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2844 | spte = sp->spt + i; | |
2845 | ||
2846 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2847 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2848 | if (!start) |
2849 | continue; | |
2850 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2851 | break; | |
2852 | start = NULL; | |
2853 | } else if (!start) | |
2854 | start = spte; | |
2855 | } | |
2856 | } | |
2857 | ||
2858 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2859 | { | |
2860 | struct kvm_mmu_page *sp; | |
2861 | ||
57354682 | 2862 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2863 | |
957ed9ef | 2864 | /* |
ac8d57e5 PF |
2865 | * Without accessed bits, there's no way to distinguish between |
2866 | * actually accessed translations and prefetched, so disable pte | |
2867 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2868 | */ |
ac8d57e5 | 2869 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2870 | return; |
2871 | ||
3bae0459 | 2872 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2873 | return; |
2874 | ||
4a42d848 DS |
2875 | /* |
2876 | * If addresses are being invalidated, skip prefetching to avoid | |
2877 | * accidentally prefetching those addresses. | |
2878 | */ | |
2879 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
2880 | return; | |
2881 | ||
957ed9ef XG |
2882 | __direct_pte_prefetch(vcpu, sp, sptep); |
2883 | } | |
2884 | ||
1b6d9d9e | 2885 | static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, |
8ca6f063 | 2886 | const struct kvm_memory_slot *slot) |
db543216 | 2887 | { |
db543216 SC |
2888 | unsigned long hva; |
2889 | pte_t *pte; | |
2890 | int level; | |
2891 | ||
e851265a | 2892 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2893 | return PG_LEVEL_4K; |
db543216 | 2894 | |
293e306e SC |
2895 | /* |
2896 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2897 | * is not solely for performance, it's also necessary to avoid the | |
2898 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2899 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2900 | * page fault steps have already verified the guest isn't writing a | |
2901 | * read-only memslot. | |
2902 | */ | |
db543216 SC |
2903 | hva = __gfn_to_hva_memslot(slot, gfn); |
2904 | ||
1b6d9d9e | 2905 | pte = lookup_address_in_mm(kvm->mm, hva, &level); |
db543216 | 2906 | if (unlikely(!pte)) |
3bae0459 | 2907 | return PG_LEVEL_4K; |
db543216 SC |
2908 | |
2909 | return level; | |
2910 | } | |
2911 | ||
8ca6f063 BG |
2912 | int kvm_mmu_max_mapping_level(struct kvm *kvm, |
2913 | const struct kvm_memory_slot *slot, gfn_t gfn, | |
2914 | kvm_pfn_t pfn, int max_level) | |
1b6d9d9e SC |
2915 | { |
2916 | struct kvm_lpage_info *linfo; | |
2917 | ||
2918 | max_level = min(max_level, max_huge_page_level); | |
2919 | for ( ; max_level > PG_LEVEL_4K; max_level--) { | |
2920 | linfo = lpage_info_slot(gfn, slot, max_level); | |
2921 | if (!linfo->disallow_lpage) | |
2922 | break; | |
2923 | } | |
2924 | ||
2925 | if (max_level == PG_LEVEL_4K) | |
2926 | return PG_LEVEL_4K; | |
2927 | ||
2928 | return host_pfn_mapping_level(kvm, gfn, pfn, slot); | |
2929 | } | |
2930 | ||
bb18842e BG |
2931 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2932 | int max_level, kvm_pfn_t *pfnp, | |
2933 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2934 | { |
293e306e | 2935 | struct kvm_memory_slot *slot; |
0885904d | 2936 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2937 | kvm_pfn_t mask; |
83f06fa7 | 2938 | int level; |
17eff019 | 2939 | |
3cf06612 SC |
2940 | *req_level = PG_LEVEL_4K; |
2941 | ||
3bae0459 SC |
2942 | if (unlikely(max_level == PG_LEVEL_4K)) |
2943 | return PG_LEVEL_4K; | |
17eff019 | 2944 | |
e851265a | 2945 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2946 | return PG_LEVEL_4K; |
17eff019 | 2947 | |
293e306e SC |
2948 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2949 | if (!slot) | |
3bae0459 | 2950 | return PG_LEVEL_4K; |
293e306e | 2951 | |
1b6d9d9e | 2952 | level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level); |
3bae0459 | 2953 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2954 | return level; |
17eff019 | 2955 | |
3cf06612 SC |
2956 | *req_level = level = min(level, max_level); |
2957 | ||
2958 | /* | |
2959 | * Enforce the iTLB multihit workaround after capturing the requested | |
2960 | * level, which will be used to do precise, accurate accounting. | |
2961 | */ | |
2962 | if (huge_page_disallowed) | |
2963 | return PG_LEVEL_4K; | |
0885904d SC |
2964 | |
2965 | /* | |
17eff019 SC |
2966 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2967 | * the pmd can't be split from under us. | |
0885904d | 2968 | */ |
17eff019 SC |
2969 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2970 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2971 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2972 | |
2973 | return level; | |
0885904d SC |
2974 | } |
2975 | ||
bb18842e BG |
2976 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2977 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2978 | { |
bb18842e | 2979 | int level = *goal_levelp; |
b8e8c830 | 2980 | |
7d945312 | 2981 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2982 | is_shadow_present_pte(spte) && |
2983 | !is_large_pte(spte)) { | |
2984 | /* | |
2985 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2986 | * and __direct_map would like to create a large PTE | |
2987 | * instead: just force them to go down another level, | |
2988 | * patching back for them into pfn the next 9 bits of | |
2989 | * the address. | |
2990 | */ | |
7d945312 BG |
2991 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2992 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2993 | *pfnp |= gfn & page_mask; |
bb18842e | 2994 | (*goal_levelp)--; |
b8e8c830 PB |
2995 | } |
2996 | } | |
2997 | ||
6c2fd34f | 2998 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2999 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 3000 | bool prefault, bool is_tdp) |
140754bc | 3001 | { |
6c2fd34f SC |
3002 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
3003 | bool write = error_code & PFERR_WRITE_MASK; | |
3004 | bool exec = error_code & PFERR_FETCH_MASK; | |
3005 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 3006 | struct kvm_shadow_walk_iterator it; |
140754bc | 3007 | struct kvm_mmu_page *sp; |
3cf06612 | 3008 | int level, req_level, ret; |
3fcf2d1b PB |
3009 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3010 | gfn_t base_gfn = gfn; | |
6aa8b732 | 3011 | |
3cf06612 SC |
3012 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
3013 | huge_page_disallowed, &req_level); | |
4cd071d1 | 3014 | |
335e192a | 3015 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 3016 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
3017 | /* |
3018 | * We cannot overwrite existing page tables with an NX | |
3019 | * large page, as the leaf could be executable. | |
3020 | */ | |
dcc70651 | 3021 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
3022 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
3023 | &pfn, &level); | |
b8e8c830 | 3024 | |
3fcf2d1b PB |
3025 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
3026 | if (it.level == level) | |
9f652d21 | 3027 | break; |
6aa8b732 | 3028 | |
3fcf2d1b | 3029 | drop_large_spte(vcpu, it.sptep); |
03fffc54 SC |
3030 | if (is_shadow_present_pte(*it.sptep)) |
3031 | continue; | |
3032 | ||
3033 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
3034 | it.level - 1, true, ACC_ALL); | |
3035 | ||
3036 | link_shadow_page(vcpu, it.sptep, sp); | |
3037 | if (is_tdp && huge_page_disallowed && | |
3038 | req_level >= it.level) | |
3039 | account_huge_nx_page(vcpu->kvm, sp); | |
9f652d21 | 3040 | } |
3fcf2d1b PB |
3041 | |
3042 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
3043 | write, level, base_gfn, pfn, prefault, | |
3044 | map_writable); | |
12703759 SC |
3045 | if (ret == RET_PF_SPURIOUS) |
3046 | return ret; | |
3047 | ||
3fcf2d1b PB |
3048 | direct_pte_prefetch(vcpu, it.sptep); |
3049 | ++vcpu->stat.pf_fixed; | |
3050 | return ret; | |
6aa8b732 AK |
3051 | } |
3052 | ||
77db5cbd | 3053 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3054 | { |
585a8b9b | 3055 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
3056 | } |
3057 | ||
ba049e93 | 3058 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3059 | { |
4d8b81ab XG |
3060 | /* |
3061 | * Do not cache the mmio info caused by writing the readonly gfn | |
3062 | * into the spte otherwise read access on readonly gfn also can | |
3063 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3064 | */ |
3065 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3066 | return RET_PF_EMULATE; |
4d8b81ab | 3067 | |
e6c1502b | 3068 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3069 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3070 | return RET_PF_RETRY; |
d7c55201 | 3071 | } |
edba23e5 | 3072 | |
2c151b25 | 3073 | return -EFAULT; |
bf998156 HY |
3074 | } |
3075 | ||
d7c55201 | 3076 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
3077 | kvm_pfn_t pfn, unsigned int access, |
3078 | int *ret_val) | |
d7c55201 | 3079 | { |
d7c55201 | 3080 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3081 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3082 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3083 | return true; |
d7c55201 XG |
3084 | } |
3085 | ||
30ab5901 | 3086 | if (unlikely(is_noslot_pfn(pfn))) { |
4af77151 SC |
3087 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
3088 | access & shadow_mmio_access_mask); | |
30ab5901 SC |
3089 | /* |
3090 | * If MMIO caching is disabled, emulate immediately without | |
3091 | * touching the shadow page tables as attempting to install an | |
3092 | * MMIO SPTE will just be an expensive nop. | |
3093 | */ | |
3094 | if (unlikely(!shadow_mmio_value)) { | |
3095 | *ret_val = RET_PF_EMULATE; | |
3096 | return true; | |
3097 | } | |
3098 | } | |
d7c55201 | 3099 | |
798e88b3 | 3100 | return false; |
d7c55201 XG |
3101 | } |
3102 | ||
e5552fd2 | 3103 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3104 | { |
1c118b82 XG |
3105 | /* |
3106 | * Do not fix the mmio spte with invalid generation number which | |
3107 | * need to be updated by slow page fault path. | |
3108 | */ | |
3109 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3110 | return false; | |
3111 | ||
f160c7b7 JS |
3112 | /* See if the page fault is due to an NX violation */ |
3113 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3114 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3115 | return false; | |
3116 | ||
c7ba5b48 | 3117 | /* |
f160c7b7 JS |
3118 | * #PF can be fast if: |
3119 | * 1. The shadow page table entry is not present, which could mean that | |
3120 | * the fault is potentially caused by access tracking (if enabled). | |
3121 | * 2. The shadow page table entry is present and the fault | |
3122 | * is caused by write-protect, that means we just need change the W | |
3123 | * bit of the spte which can be done out of mmu-lock. | |
3124 | * | |
3125 | * However, if access tracking is disabled we know that a non-present | |
3126 | * page must be a genuine page fault where we have to create a new SPTE. | |
3127 | * So, if access tracking is disabled, we return true only for write | |
3128 | * accesses to a present page. | |
c7ba5b48 | 3129 | */ |
c7ba5b48 | 3130 | |
f160c7b7 JS |
3131 | return shadow_acc_track_mask != 0 || |
3132 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3133 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3134 | } |
3135 | ||
97dceba2 JS |
3136 | /* |
3137 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3138 | * someone else modified the SPTE from its original value. | |
3139 | */ | |
c7ba5b48 | 3140 | static bool |
92a476cb | 3141 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3142 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3143 | { |
c7ba5b48 XG |
3144 | gfn_t gfn; |
3145 | ||
3146 | WARN_ON(!sp->role.direct); | |
3147 | ||
9b51a630 KH |
3148 | /* |
3149 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3150 | * order to eliminate unnecessary PML logging. See comments in | |
3151 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3152 | * enabled, so we do not do this. This might result in the same GPA | |
3153 | * to be logged in PML buffer again when the write really happens, and | |
3154 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3155 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3156 | * so non-PML cases won't be impacted. | |
3157 | * | |
3158 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3159 | */ | |
f160c7b7 | 3160 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3161 | return false; |
3162 | ||
d3e328f2 | 3163 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3164 | /* |
3165 | * The gfn of direct spte is stable since it is | |
3166 | * calculated by sp->gfn. | |
3167 | */ | |
3168 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3169 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3170 | } | |
c7ba5b48 XG |
3171 | |
3172 | return true; | |
3173 | } | |
3174 | ||
d3e328f2 JS |
3175 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3176 | { | |
3177 | if (fault_err_code & PFERR_FETCH_MASK) | |
3178 | return is_executable_pte(spte); | |
3179 | ||
3180 | if (fault_err_code & PFERR_WRITE_MASK) | |
3181 | return is_writable_pte(spte); | |
3182 | ||
3183 | /* Fault was on Read access */ | |
3184 | return spte & PT_PRESENT_MASK; | |
3185 | } | |
3186 | ||
6e8eb206 DM |
3187 | /* |
3188 | * Returns the last level spte pointer of the shadow page walk for the given | |
3189 | * gpa, and sets *spte to the spte value. This spte may be non-preset. If no | |
3190 | * walk could be performed, returns NULL and *spte does not contain valid data. | |
3191 | * | |
3192 | * Contract: | |
3193 | * - Must be called between walk_shadow_page_lockless_{begin,end}. | |
3194 | * - The returned sptep must not be used after walk_shadow_page_lockless_end. | |
3195 | */ | |
3196 | static u64 *fast_pf_get_last_sptep(struct kvm_vcpu *vcpu, gpa_t gpa, u64 *spte) | |
3197 | { | |
3198 | struct kvm_shadow_walk_iterator iterator; | |
3199 | u64 old_spte; | |
3200 | u64 *sptep = NULL; | |
3201 | ||
3202 | for_each_shadow_entry_lockless(vcpu, gpa, iterator, old_spte) { | |
3203 | sptep = iterator.sptep; | |
3204 | *spte = old_spte; | |
3205 | ||
3206 | if (!is_shadow_present_pte(old_spte)) | |
3207 | break; | |
3208 | } | |
3209 | ||
3210 | return sptep; | |
3211 | } | |
3212 | ||
c7ba5b48 | 3213 | /* |
c4371c2a | 3214 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3215 | */ |
76cd325e | 3216 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code) |
c7ba5b48 | 3217 | { |
92a476cb | 3218 | struct kvm_mmu_page *sp; |
c4371c2a | 3219 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3220 | u64 spte = 0ull; |
6e8eb206 | 3221 | u64 *sptep = NULL; |
97dceba2 | 3222 | uint retry_count = 0; |
c7ba5b48 | 3223 | |
e5552fd2 | 3224 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3225 | return ret; |
c7ba5b48 XG |
3226 | |
3227 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3228 | |
97dceba2 | 3229 | do { |
d3e328f2 | 3230 | u64 new_spte; |
c7ba5b48 | 3231 | |
6e8eb206 DM |
3232 | if (is_tdp_mmu(vcpu->arch.mmu)) |
3233 | sptep = kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu, gpa, &spte); | |
3234 | else | |
3235 | sptep = fast_pf_get_last_sptep(vcpu, gpa, &spte); | |
d162f30a | 3236 | |
ec89e643 SC |
3237 | if (!is_shadow_present_pte(spte)) |
3238 | break; | |
3239 | ||
6e8eb206 | 3240 | sp = sptep_to_sp(sptep); |
97dceba2 JS |
3241 | if (!is_last_spte(spte, sp->role.level)) |
3242 | break; | |
c7ba5b48 | 3243 | |
97dceba2 | 3244 | /* |
f160c7b7 JS |
3245 | * Check whether the memory access that caused the fault would |
3246 | * still cause it if it were to be performed right now. If not, | |
3247 | * then this is a spurious fault caused by TLB lazily flushed, | |
3248 | * or some other CPU has already fixed the PTE after the | |
3249 | * current CPU took the fault. | |
97dceba2 JS |
3250 | * |
3251 | * Need not check the access of upper level table entries since | |
3252 | * they are always ACC_ALL. | |
3253 | */ | |
d3e328f2 | 3254 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3255 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3256 | break; |
3257 | } | |
f160c7b7 | 3258 | |
d3e328f2 JS |
3259 | new_spte = spte; |
3260 | ||
3261 | if (is_access_track_spte(spte)) | |
3262 | new_spte = restore_acc_track_spte(new_spte); | |
3263 | ||
3264 | /* | |
3265 | * Currently, to simplify the code, write-protection can | |
3266 | * be removed in the fast path only if the SPTE was | |
3267 | * write-protected for dirty-logging or access tracking. | |
3268 | */ | |
3269 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3270 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3271 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3272 | |
3273 | /* | |
d3e328f2 JS |
3274 | * Do not fix write-permission on the large spte. Since |
3275 | * we only dirty the first page into the dirty-bitmap in | |
3276 | * fast_pf_fix_direct_spte(), other pages are missed | |
3277 | * if its slot has dirty logging enabled. | |
3278 | * | |
3279 | * Instead, we let the slow page fault path create a | |
3280 | * normal spte to fix the access. | |
3281 | * | |
3282 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3283 | */ |
3bae0459 | 3284 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3285 | break; |
97dceba2 | 3286 | } |
c7ba5b48 | 3287 | |
f160c7b7 | 3288 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3289 | if (new_spte == spte || |
3290 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3291 | break; |
3292 | ||
3293 | /* | |
3294 | * Currently, fast page fault only works for direct mapping | |
3295 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3296 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3297 | */ |
6e8eb206 | 3298 | if (fast_pf_fix_direct_spte(vcpu, sp, sptep, spte, new_spte)) { |
c4371c2a | 3299 | ret = RET_PF_FIXED; |
97dceba2 | 3300 | break; |
c4371c2a | 3301 | } |
97dceba2 JS |
3302 | |
3303 | if (++retry_count > 4) { | |
3304 | printk_once(KERN_WARNING | |
3305 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3306 | break; | |
3307 | } | |
3308 | ||
97dceba2 | 3309 | } while (true); |
c126d94f | 3310 | |
6e8eb206 | 3311 | trace_fast_page_fault(vcpu, gpa, error_code, sptep, spte, ret); |
c7ba5b48 XG |
3312 | walk_shadow_page_lockless_end(vcpu); |
3313 | ||
c4371c2a | 3314 | return ret; |
c7ba5b48 XG |
3315 | } |
3316 | ||
74b566e6 JS |
3317 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3318 | struct list_head *invalid_list) | |
17ac10ad | 3319 | { |
4db35314 | 3320 | struct kvm_mmu_page *sp; |
17ac10ad | 3321 | |
74b566e6 | 3322 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3323 | return; |
35af577a | 3324 | |
e47c4aee | 3325 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a | 3326 | |
2bdb3d84 | 3327 | if (is_tdp_mmu_page(sp)) |
6103bc07 | 3328 | kvm_tdp_mmu_put_root(kvm, sp, false); |
76eb54e7 BG |
3329 | else if (!--sp->root_count && sp->role.invalid) |
3330 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3331 | |
74b566e6 JS |
3332 | *root_hpa = INVALID_PAGE; |
3333 | } | |
3334 | ||
08fb59d8 | 3335 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3336 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3337 | ulong roots_to_free) | |
74b566e6 | 3338 | { |
4d710de9 | 3339 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3340 | int i; |
3341 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3342 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3343 | |
b94742c9 | 3344 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3345 | |
08fb59d8 | 3346 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3347 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3348 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3349 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3350 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3351 | break; | |
3352 | ||
3353 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3354 | return; | |
3355 | } | |
35af577a | 3356 | |
531810ca | 3357 | write_lock(&kvm->mmu_lock); |
17ac10ad | 3358 | |
b94742c9 JS |
3359 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3360 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3361 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3362 | &invalid_list); |
7c390d35 | 3363 | |
08fb59d8 JS |
3364 | if (free_active_root) { |
3365 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3366 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3367 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
04d45551 | 3368 | } else if (mmu->pae_root) { |
c834e5e4 SC |
3369 | for (i = 0; i < 4; ++i) { |
3370 | if (!IS_VALID_PAE_ROOT(mmu->pae_root[i])) | |
3371 | continue; | |
3372 | ||
3373 | mmu_free_root_page(kvm, &mmu->pae_root[i], | |
3374 | &invalid_list); | |
3375 | mmu->pae_root[i] = INVALID_PAE_ROOT; | |
3376 | } | |
08fb59d8 | 3377 | } |
04d45551 | 3378 | mmu->root_hpa = INVALID_PAGE; |
be01e8e2 | 3379 | mmu->root_pgd = 0; |
17ac10ad | 3380 | } |
74b566e6 | 3381 | |
4d710de9 | 3382 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 3383 | write_unlock(&kvm->mmu_lock); |
17ac10ad | 3384 | } |
74b566e6 | 3385 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3386 | |
25b62c62 SC |
3387 | void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3388 | { | |
3389 | unsigned long roots_to_free = 0; | |
3390 | hpa_t root_hpa; | |
3391 | int i; | |
3392 | ||
3393 | /* | |
3394 | * This should not be called while L2 is active, L2 can't invalidate | |
3395 | * _only_ its own roots, e.g. INVVPID unconditionally exits. | |
3396 | */ | |
3397 | WARN_ON_ONCE(mmu->mmu_role.base.guest_mode); | |
3398 | ||
3399 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
3400 | root_hpa = mmu->prev_roots[i].hpa; | |
3401 | if (!VALID_PAGE(root_hpa)) | |
3402 | continue; | |
3403 | ||
3404 | if (!to_shadow_page(root_hpa) || | |
3405 | to_shadow_page(root_hpa)->role.guest_mode) | |
3406 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
3407 | } | |
3408 | ||
3409 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
3410 | } | |
3411 | EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots); | |
3412 | ||
3413 | ||
8986ecc0 MT |
3414 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3415 | { | |
3416 | int ret = 0; | |
3417 | ||
995decb6 | 3418 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3419 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3420 | ret = 1; |
3421 | } | |
3422 | ||
3423 | return ret; | |
3424 | } | |
3425 | ||
8123f265 SC |
3426 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3427 | u8 level, bool direct) | |
651dd37a JR |
3428 | { |
3429 | struct kvm_mmu_page *sp; | |
8123f265 | 3430 | |
8123f265 SC |
3431 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); |
3432 | ++sp->root_count; | |
3433 | ||
8123f265 SC |
3434 | return __pa(sp->spt); |
3435 | } | |
3436 | ||
3437 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3438 | { | |
b37233c9 SC |
3439 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
3440 | u8 shadow_root_level = mmu->shadow_root_level; | |
8123f265 | 3441 | hpa_t root; |
7ebaf15e | 3442 | unsigned i; |
4a38162e PB |
3443 | int r; |
3444 | ||
3445 | write_lock(&vcpu->kvm->mmu_lock); | |
3446 | r = make_mmu_pages_available(vcpu); | |
3447 | if (r < 0) | |
3448 | goto out_unlock; | |
651dd37a | 3449 | |
897218ff | 3450 | if (is_tdp_mmu_enabled(vcpu->kvm)) { |
02c00b3a | 3451 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); |
b37233c9 | 3452 | mmu->root_hpa = root; |
02c00b3a | 3453 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { |
6e6ec584 | 3454 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true); |
b37233c9 | 3455 | mmu->root_hpa = root; |
8123f265 | 3456 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { |
4a38162e PB |
3457 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3458 | r = -EIO; | |
3459 | goto out_unlock; | |
3460 | } | |
73ad1606 | 3461 | |
651dd37a | 3462 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3463 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
651dd37a | 3464 | |
8123f265 SC |
3465 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3466 | i << 30, PT32_ROOT_LEVEL, true); | |
17e368d9 SC |
3467 | mmu->pae_root[i] = root | PT_PRESENT_MASK | |
3468 | shadow_me_mask; | |
651dd37a | 3469 | } |
b37233c9 | 3470 | mmu->root_hpa = __pa(mmu->pae_root); |
73ad1606 SC |
3471 | } else { |
3472 | WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level); | |
4a38162e PB |
3473 | r = -EIO; |
3474 | goto out_unlock; | |
73ad1606 | 3475 | } |
3651c7fc | 3476 | |
be01e8e2 | 3477 | /* root_pgd is ignored for direct MMUs. */ |
b37233c9 | 3478 | mmu->root_pgd = 0; |
4a38162e PB |
3479 | out_unlock: |
3480 | write_unlock(&vcpu->kvm->mmu_lock); | |
3481 | return r; | |
651dd37a JR |
3482 | } |
3483 | ||
3484 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3485 | { |
b37233c9 | 3486 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
6e0918ae | 3487 | u64 pdptrs[4], pm_mask; |
be01e8e2 | 3488 | gfn_t root_gfn, root_pgd; |
8123f265 | 3489 | hpa_t root; |
4a38162e PB |
3490 | unsigned i; |
3491 | int r; | |
3bb65a22 | 3492 | |
b37233c9 | 3493 | root_pgd = mmu->get_guest_pgd(vcpu); |
be01e8e2 | 3494 | root_gfn = root_pgd >> PAGE_SHIFT; |
17ac10ad | 3495 | |
651dd37a JR |
3496 | if (mmu_check_root(vcpu, root_gfn)) |
3497 | return 1; | |
3498 | ||
4a38162e PB |
3499 | /* |
3500 | * On SVM, reading PDPTRs might access guest memory, which might fault | |
3501 | * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock. | |
3502 | */ | |
6e0918ae SC |
3503 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
3504 | for (i = 0; i < 4; ++i) { | |
3505 | pdptrs[i] = mmu->get_pdptr(vcpu, i); | |
3506 | if (!(pdptrs[i] & PT_PRESENT_MASK)) | |
3507 | continue; | |
3508 | ||
3509 | if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT)) | |
3510 | return 1; | |
3511 | } | |
3512 | } | |
3513 | ||
d501f747 BG |
3514 | r = alloc_all_memslots_rmaps(vcpu->kvm); |
3515 | if (r) | |
3516 | return r; | |
3517 | ||
4a38162e PB |
3518 | write_lock(&vcpu->kvm->mmu_lock); |
3519 | r = make_mmu_pages_available(vcpu); | |
3520 | if (r < 0) | |
3521 | goto out_unlock; | |
3522 | ||
651dd37a JR |
3523 | /* |
3524 | * Do we shadow a long mode page table? If so we need to | |
3525 | * write-protect the guests page table root. | |
3526 | */ | |
b37233c9 | 3527 | if (mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3528 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
b37233c9 | 3529 | mmu->shadow_root_level, false); |
b37233c9 | 3530 | mmu->root_hpa = root; |
be01e8e2 | 3531 | goto set_root_pgd; |
17ac10ad | 3532 | } |
f87f9288 | 3533 | |
4a38162e PB |
3534 | if (WARN_ON_ONCE(!mmu->pae_root)) { |
3535 | r = -EIO; | |
3536 | goto out_unlock; | |
3537 | } | |
73ad1606 | 3538 | |
651dd37a JR |
3539 | /* |
3540 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3541 | * or a PAE 3-level page table. In either case we need to be aware that |
3542 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3543 | */ |
17e368d9 | 3544 | pm_mask = PT_PRESENT_MASK | shadow_me_mask; |
748e52b9 | 3545 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3546 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3547 | ||
03ca4589 | 3548 | if (WARN_ON_ONCE(!mmu->pml4_root)) { |
4a38162e PB |
3549 | r = -EIO; |
3550 | goto out_unlock; | |
3551 | } | |
73ad1606 | 3552 | |
03ca4589 | 3553 | mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask; |
04d45551 SC |
3554 | } |
3555 | ||
17ac10ad | 3556 | for (i = 0; i < 4; ++i) { |
c834e5e4 | 3557 | WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i])); |
6e6ec584 | 3558 | |
b37233c9 | 3559 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
6e0918ae | 3560 | if (!(pdptrs[i] & PT_PRESENT_MASK)) { |
c834e5e4 | 3561 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
417726a3 AK |
3562 | continue; |
3563 | } | |
6e0918ae | 3564 | root_gfn = pdptrs[i] >> PAGE_SHIFT; |
5a7388c2 | 3565 | } |
8facbbff | 3566 | |
8123f265 SC |
3567 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3568 | PT32_ROOT_LEVEL, false); | |
b37233c9 | 3569 | mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3570 | } |
81407ca5 | 3571 | |
ba0a194f | 3572 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
03ca4589 | 3573 | mmu->root_hpa = __pa(mmu->pml4_root); |
ba0a194f SC |
3574 | else |
3575 | mmu->root_hpa = __pa(mmu->pae_root); | |
81407ca5 | 3576 | |
be01e8e2 | 3577 | set_root_pgd: |
b37233c9 | 3578 | mmu->root_pgd = root_pgd; |
4a38162e PB |
3579 | out_unlock: |
3580 | write_unlock(&vcpu->kvm->mmu_lock); | |
ad7dc69a | 3581 | |
8986ecc0 | 3582 | return 0; |
17ac10ad AK |
3583 | } |
3584 | ||
748e52b9 SC |
3585 | static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) |
3586 | { | |
3587 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
03ca4589 | 3588 | u64 *pml4_root, *pae_root; |
81407ca5 JR |
3589 | |
3590 | /* | |
748e52b9 SC |
3591 | * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP |
3592 | * tables are allocated and initialized at root creation as there is no | |
3593 | * equivalent level in the guest's NPT to shadow. Allocate the tables | |
3594 | * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare. | |
81407ca5 | 3595 | */ |
748e52b9 SC |
3596 | if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL || |
3597 | mmu->shadow_root_level < PT64_ROOT_4LEVEL) | |
3598 | return 0; | |
81407ca5 | 3599 | |
748e52b9 SC |
3600 | /* |
3601 | * This mess only works with 4-level paging and needs to be updated to | |
3602 | * work with 5-level paging. | |
3603 | */ | |
3604 | if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) | |
3605 | return -EIO; | |
81407ca5 | 3606 | |
03ca4589 | 3607 | if (mmu->pae_root && mmu->pml4_root) |
748e52b9 | 3608 | return 0; |
81407ca5 | 3609 | |
748e52b9 SC |
3610 | /* |
3611 | * The special roots should always be allocated in concert. Yell and | |
3612 | * bail if KVM ends up in a state where only one of the roots is valid. | |
3613 | */ | |
03ca4589 | 3614 | if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root)) |
748e52b9 | 3615 | return -EIO; |
81407ca5 | 3616 | |
4a98623d SC |
3617 | /* |
3618 | * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and | |
3619 | * doesn't need to be decrypted. | |
3620 | */ | |
748e52b9 SC |
3621 | pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3622 | if (!pae_root) | |
3623 | return -ENOMEM; | |
81407ca5 | 3624 | |
03ca4589 SC |
3625 | pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
3626 | if (!pml4_root) { | |
748e52b9 SC |
3627 | free_page((unsigned long)pae_root); |
3628 | return -ENOMEM; | |
81407ca5 JR |
3629 | } |
3630 | ||
748e52b9 | 3631 | mmu->pae_root = pae_root; |
03ca4589 | 3632 | mmu->pml4_root = pml4_root; |
ad7dc69a | 3633 | |
8986ecc0 | 3634 | return 0; |
17ac10ad AK |
3635 | } |
3636 | ||
578e1c4d | 3637 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3638 | { |
3639 | int i; | |
3640 | struct kvm_mmu_page *sp; | |
3641 | ||
44dd3ffa | 3642 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3643 | return; |
3644 | ||
44dd3ffa | 3645 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3646 | return; |
6903074c | 3647 | |
56f17dd3 | 3648 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3649 | |
44dd3ffa VK |
3650 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3651 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3652 | sp = to_shadow_page(root); |
578e1c4d JS |
3653 | |
3654 | /* | |
3655 | * Even if another CPU was marking the SP as unsync-ed | |
3656 | * simultaneously, any guest page table changes are not | |
3657 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3658 | * flush strictly after those changes are made. We only need to | |
3659 | * ensure that the other CPU sets these flags before any actual | |
3660 | * changes to the page tables are made. The comments in | |
0337f585 SC |
3661 | * mmu_try_to_unsync_pages() describe what could go wrong if |
3662 | * this requirement isn't satisfied. | |
578e1c4d JS |
3663 | */ |
3664 | if (!smp_load_acquire(&sp->unsync) && | |
3665 | !smp_load_acquire(&sp->unsync_children)) | |
3666 | return; | |
3667 | ||
531810ca | 3668 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3669 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3670 | ||
0ba73cda | 3671 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3672 | |
0375f7fa | 3673 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3674 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3675 | return; |
3676 | } | |
578e1c4d | 3677 | |
531810ca | 3678 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3679 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3680 | ||
0ba73cda | 3681 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3682 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3683 | |
c834e5e4 | 3684 | if (IS_VALID_PAE_ROOT(root)) { |
0ba73cda | 3685 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3686 | sp = to_shadow_page(root); |
0ba73cda MT |
3687 | mmu_sync_children(vcpu, sp); |
3688 | } | |
3689 | } | |
0ba73cda | 3690 | |
578e1c4d | 3691 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3692 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3693 | } |
3694 | ||
736c291c | 3695 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3696 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3697 | { |
ab9ae313 AK |
3698 | if (exception) |
3699 | exception->error_code = 0; | |
6aa8b732 AK |
3700 | return vaddr; |
3701 | } | |
3702 | ||
736c291c | 3703 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3704 | u32 access, |
3705 | struct x86_exception *exception) | |
6539e738 | 3706 | { |
ab9ae313 AK |
3707 | if (exception) |
3708 | exception->error_code = 0; | |
54987b7a | 3709 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3710 | } |
3711 | ||
ded58749 | 3712 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3713 | { |
9034e6e8 PB |
3714 | /* |
3715 | * A nested guest cannot use the MMIO cache if it is using nested | |
3716 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3717 | */ | |
3718 | if (mmu_is_nested(vcpu)) | |
3719 | return false; | |
3720 | ||
ce88decf XG |
3721 | if (direct) |
3722 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3723 | ||
3724 | return vcpu_match_mmio_gva(vcpu, addr); | |
3725 | } | |
3726 | ||
95fb5b02 BG |
3727 | /* |
3728 | * Return the level of the lowest level SPTE added to sptes. | |
3729 | * That SPTE may be non-present. | |
c5c8c7c5 DM |
3730 | * |
3731 | * Must be called between walk_shadow_page_lockless_{begin,end}. | |
95fb5b02 | 3732 | */ |
39b4d43e | 3733 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level) |
ce88decf XG |
3734 | { |
3735 | struct kvm_shadow_walk_iterator iterator; | |
2aa07893 | 3736 | int leaf = -1; |
95fb5b02 | 3737 | u64 spte; |
ce88decf | 3738 | |
39b4d43e SC |
3739 | for (shadow_walk_init(&iterator, vcpu, addr), |
3740 | *root_level = iterator.level; | |
47ab8751 XG |
3741 | shadow_walk_okay(&iterator); |
3742 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3743 | leaf = iterator.level; |
47ab8751 XG |
3744 | spte = mmu_spte_get_lockless(iterator.sptep); |
3745 | ||
dde81f94 | 3746 | sptes[leaf] = spte; |
47ab8751 | 3747 | |
ce88decf XG |
3748 | if (!is_shadow_present_pte(spte)) |
3749 | break; | |
95fb5b02 BG |
3750 | } |
3751 | ||
95fb5b02 BG |
3752 | return leaf; |
3753 | } | |
3754 | ||
9aa41879 | 3755 | /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */ |
95fb5b02 BG |
3756 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) |
3757 | { | |
dde81f94 | 3758 | u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; |
95fb5b02 | 3759 | struct rsvd_bits_validate *rsvd_check; |
39b4d43e | 3760 | int root, leaf, level; |
95fb5b02 BG |
3761 | bool reserved = false; |
3762 | ||
c5c8c7c5 DM |
3763 | walk_shadow_page_lockless_begin(vcpu); |
3764 | ||
63c0cac9 | 3765 | if (is_tdp_mmu(vcpu->arch.mmu)) |
39b4d43e | 3766 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3767 | else |
39b4d43e | 3768 | leaf = get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3769 | |
c5c8c7c5 DM |
3770 | walk_shadow_page_lockless_end(vcpu); |
3771 | ||
2aa07893 SC |
3772 | if (unlikely(leaf < 0)) { |
3773 | *sptep = 0ull; | |
3774 | return reserved; | |
3775 | } | |
3776 | ||
9aa41879 SC |
3777 | *sptep = sptes[leaf]; |
3778 | ||
3779 | /* | |
3780 | * Skip reserved bits checks on the terminal leaf if it's not a valid | |
3781 | * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by | |
3782 | * design, always have reserved bits set. The purpose of the checks is | |
3783 | * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs. | |
3784 | */ | |
3785 | if (!is_shadow_present_pte(sptes[leaf])) | |
3786 | leaf++; | |
95fb5b02 BG |
3787 | |
3788 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3789 | ||
9aa41879 | 3790 | for (level = root; level >= leaf; level--) |
961f8445 | 3791 | reserved |= is_rsvd_spte(rsvd_check, sptes[level], level); |
47ab8751 | 3792 | |
47ab8751 | 3793 | if (reserved) { |
bb4cdf3a | 3794 | pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n", |
47ab8751 | 3795 | __func__, addr); |
95fb5b02 | 3796 | for (level = root; level >= leaf; level--) |
bb4cdf3a SC |
3797 | pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx", |
3798 | sptes[level], level, | |
961f8445 | 3799 | get_rsvd_bits(rsvd_check, sptes[level], level)); |
47ab8751 | 3800 | } |
ddce6208 | 3801 | |
47ab8751 | 3802 | return reserved; |
ce88decf XG |
3803 | } |
3804 | ||
e08d26f0 | 3805 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3806 | { |
3807 | u64 spte; | |
47ab8751 | 3808 | bool reserved; |
ce88decf | 3809 | |
ded58749 | 3810 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3811 | return RET_PF_EMULATE; |
ce88decf | 3812 | |
95fb5b02 | 3813 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3814 | if (WARN_ON(reserved)) |
9b8ebbdb | 3815 | return -EINVAL; |
ce88decf XG |
3816 | |
3817 | if (is_mmio_spte(spte)) { | |
3818 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3819 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3820 | |
54bf36aa | 3821 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3822 | return RET_PF_INVALID; |
f8f55942 | 3823 | |
ce88decf XG |
3824 | if (direct) |
3825 | addr = 0; | |
4f022648 XG |
3826 | |
3827 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3828 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3829 | return RET_PF_EMULATE; |
ce88decf XG |
3830 | } |
3831 | ||
ce88decf XG |
3832 | /* |
3833 | * If the page table is zapped by other cpus, let CPU fault again on | |
3834 | * the address. | |
3835 | */ | |
9b8ebbdb | 3836 | return RET_PF_RETRY; |
ce88decf | 3837 | } |
ce88decf | 3838 | |
3d0c27ad XG |
3839 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3840 | u32 error_code, gfn_t gfn) | |
3841 | { | |
3842 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3843 | return false; | |
3844 | ||
3845 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3846 | !(error_code & PFERR_WRITE_MASK)) | |
3847 | return false; | |
3848 | ||
3849 | /* | |
3850 | * guest is writing the page which is write tracked which can | |
3851 | * not be fixed by page fault handler. | |
3852 | */ | |
3853 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3854 | return true; | |
3855 | ||
3856 | return false; | |
3857 | } | |
3858 | ||
e5691a81 XG |
3859 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3860 | { | |
3861 | struct kvm_shadow_walk_iterator iterator; | |
3862 | u64 spte; | |
3863 | ||
e5691a81 XG |
3864 | walk_shadow_page_lockless_begin(vcpu); |
3865 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3866 | clear_sp_write_flooding_count(iterator.sptep); | |
3867 | if (!is_shadow_present_pte(spte)) | |
3868 | break; | |
3869 | } | |
3870 | walk_shadow_page_lockless_end(vcpu); | |
3871 | } | |
3872 | ||
e8c22266 VK |
3873 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3874 | gfn_t gfn) | |
af585b92 GN |
3875 | { |
3876 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3877 | |
7c90705b | 3878 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3879 | arch.gfn = gfn; |
44dd3ffa | 3880 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3881 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3882 | |
9f1a8526 SC |
3883 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3884 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3885 | } |
3886 | ||
33a5c000 | 3887 | static bool kvm_faultin_pfn(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
4a42d848 | 3888 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva, |
8f32d5e5 | 3889 | bool write, bool *writable, int *r) |
af585b92 | 3890 | { |
c36b7150 | 3891 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3892 | bool async; |
3893 | ||
e0c37868 SC |
3894 | /* |
3895 | * Retry the page fault if the gfn hit a memslot that is being deleted | |
3896 | * or moved. This ensures any existing SPTEs for the old memslot will | |
3897 | * be zapped before KVM inserts a new MMIO SPTE for the gfn. | |
3898 | */ | |
3899 | if (slot && (slot->flags & KVM_MEMSLOT_INVALID)) | |
8f32d5e5 | 3900 | goto out_retry; |
e0c37868 | 3901 | |
c36b7150 PB |
3902 | /* Don't expose private memslots to L2. */ |
3903 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3904 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3905 | *writable = false; |
3a2936de JM |
3906 | return false; |
3907 | } | |
3908 | ||
3520469d | 3909 | async = false; |
4a42d848 DS |
3910 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, |
3911 | write, writable, hva); | |
af585b92 GN |
3912 | if (!async) |
3913 | return false; /* *pfn has correct page already */ | |
3914 | ||
9bc1f09f | 3915 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3916 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3917 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3918 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 | 3919 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
8f32d5e5 | 3920 | goto out_retry; |
9f1a8526 | 3921 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
8f32d5e5 | 3922 | goto out_retry; |
af585b92 GN |
3923 | } |
3924 | ||
4a42d848 DS |
3925 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, |
3926 | write, writable, hva); | |
8f32d5e5 ML |
3927 | |
3928 | out_retry: | |
3929 | *r = RET_PF_RETRY; | |
3930 | return true; | |
af585b92 GN |
3931 | } |
3932 | ||
0f90e1c1 SC |
3933 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3934 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3935 | { |
63c0cac9 | 3936 | bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu); |
367fd790 | 3937 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3938 | bool map_writable; |
6aa8b732 | 3939 | |
0f90e1c1 SC |
3940 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3941 | unsigned long mmu_seq; | |
3942 | kvm_pfn_t pfn; | |
4a42d848 | 3943 | hva_t hva; |
83f06fa7 | 3944 | int r; |
ce88decf | 3945 | |
3d0c27ad | 3946 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3947 | return RET_PF_EMULATE; |
ce88decf | 3948 | |
6e8eb206 DM |
3949 | r = fast_page_fault(vcpu, gpa, error_code); |
3950 | if (r != RET_PF_INVALID) | |
3951 | return r; | |
83291445 | 3952 | |
378f5cd6 | 3953 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3954 | if (r) |
3955 | return r; | |
714b93da | 3956 | |
367fd790 SC |
3957 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3958 | smp_rmb(); | |
3959 | ||
33a5c000 | 3960 | if (kvm_faultin_pfn(vcpu, prefault, gfn, gpa, &pfn, &hva, |
8f32d5e5 ML |
3961 | write, &map_writable, &r)) |
3962 | return r; | |
367fd790 | 3963 | |
0f90e1c1 | 3964 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3965 | return r; |
6aa8b732 | 3966 | |
367fd790 | 3967 | r = RET_PF_RETRY; |
a2855afc | 3968 | |
0b873fd7 | 3969 | if (is_tdp_mmu_fault) |
a2855afc BG |
3970 | read_lock(&vcpu->kvm->mmu_lock); |
3971 | else | |
3972 | write_lock(&vcpu->kvm->mmu_lock); | |
3973 | ||
4a42d848 | 3974 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
367fd790 | 3975 | goto out_unlock; |
7bd7ded6 SC |
3976 | r = make_mmu_pages_available(vcpu); |
3977 | if (r) | |
367fd790 | 3978 | goto out_unlock; |
bb18842e | 3979 | |
0b873fd7 | 3980 | if (is_tdp_mmu_fault) |
bb18842e BG |
3981 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, |
3982 | pfn, prefault); | |
3983 | else | |
3984 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3985 | prefault, is_tdp); | |
0f90e1c1 | 3986 | |
367fd790 | 3987 | out_unlock: |
0b873fd7 | 3988 | if (is_tdp_mmu_fault) |
a2855afc BG |
3989 | read_unlock(&vcpu->kvm->mmu_lock); |
3990 | else | |
3991 | write_unlock(&vcpu->kvm->mmu_lock); | |
367fd790 SC |
3992 | kvm_release_pfn_clean(pfn); |
3993 | return r; | |
6aa8b732 AK |
3994 | } |
3995 | ||
0f90e1c1 SC |
3996 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3997 | u32 error_code, bool prefault) | |
3998 | { | |
3999 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
4000 | ||
4001 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
4002 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 4003 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
4004 | } |
4005 | ||
1261bfa3 | 4006 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 4007 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
4008 | { |
4009 | int r = 1; | |
9ce372b3 | 4010 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 4011 | |
736c291c SC |
4012 | #ifndef CONFIG_X86_64 |
4013 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
4014 | if (WARN_ON_ONCE(fault_address >> 32)) | |
4015 | return -EFAULT; | |
4016 | #endif | |
4017 | ||
c595ceee | 4018 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 4019 | if (!flags) { |
1261bfa3 WL |
4020 | trace_kvm_page_fault(fault_address, error_code); |
4021 | ||
d0006530 | 4022 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
4023 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
4024 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
4025 | insn_len); | |
9ce372b3 | 4026 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 4027 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 4028 | local_irq_disable(); |
6bca69ad | 4029 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 4030 | local_irq_enable(); |
9ce372b3 VK |
4031 | } else { |
4032 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 4033 | } |
9ce372b3 | 4034 | |
1261bfa3 WL |
4035 | return r; |
4036 | } | |
4037 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
4038 | ||
7a02674d SC |
4039 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
4040 | bool prefault) | |
fb72d167 | 4041 | { |
cb9b88c6 | 4042 | int max_level; |
fb72d167 | 4043 | |
e662ec3e | 4044 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 4045 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
4046 | max_level--) { |
4047 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 4048 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 4049 | |
cb9b88c6 SC |
4050 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
4051 | break; | |
fd136902 | 4052 | } |
852e3c19 | 4053 | |
0f90e1c1 SC |
4054 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
4055 | max_level, true); | |
fb72d167 JR |
4056 | } |
4057 | ||
84a16226 | 4058 | static void nonpaging_init_context(struct kvm_mmu *context) |
6aa8b732 | 4059 | { |
6aa8b732 | 4060 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4061 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4062 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4063 | context->invlpg = NULL; |
c5a78f2b | 4064 | context->direct_map = true; |
6aa8b732 AK |
4065 | } |
4066 | ||
be01e8e2 | 4067 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
4068 | union kvm_mmu_page_role role) |
4069 | { | |
be01e8e2 | 4070 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
4071 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
4072 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
4073 | } |
4074 | ||
b94742c9 | 4075 | /* |
be01e8e2 | 4076 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
4077 | * The current root is also inserted into the cache. |
4078 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
4079 | * returned. | |
4080 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
4081 | * false is returned. This root should now be freed by the caller. | |
4082 | */ | |
be01e8e2 | 4083 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
4084 | union kvm_mmu_page_role new_role) |
4085 | { | |
4086 | uint i; | |
4087 | struct kvm_mmu_root_info root; | |
44dd3ffa | 4088 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 4089 | |
be01e8e2 | 4090 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
4091 | root.hpa = mmu->root_hpa; |
4092 | ||
be01e8e2 | 4093 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
4094 | return true; |
4095 | ||
b94742c9 JS |
4096 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
4097 | swap(root, mmu->prev_roots[i]); | |
4098 | ||
be01e8e2 | 4099 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
4100 | break; |
4101 | } | |
4102 | ||
4103 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 4104 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
4105 | |
4106 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4107 | } | |
4108 | ||
be01e8e2 | 4109 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 4110 | union kvm_mmu_page_role new_role) |
6aa8b732 | 4111 | { |
44dd3ffa | 4112 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4113 | |
4114 | /* | |
4115 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4116 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4117 | * later if necessary. | |
4118 | */ | |
4119 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 4120 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 4121 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
4122 | |
4123 | return false; | |
6aa8b732 AK |
4124 | } |
4125 | ||
be01e8e2 | 4126 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b5129100 | 4127 | union kvm_mmu_page_role new_role) |
6aa8b732 | 4128 | { |
be01e8e2 | 4129 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
4130 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
4131 | return; | |
4132 | } | |
4133 | ||
4134 | /* | |
4135 | * It's possible that the cached previous root page is obsolete because | |
4136 | * of a change in the MMU generation number. However, changing the | |
4137 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
4138 | * free the root set here and allocate a new one. | |
4139 | */ | |
4140 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
4141 | ||
b5129100 | 4142 | if (force_flush_and_sync_on_reuse) { |
b869855b SC |
4143 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
4144 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
b5129100 | 4145 | } |
b869855b SC |
4146 | |
4147 | /* | |
4148 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
4149 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
4150 | * valid. So clear any cached MMIO info even when we don't need to sync | |
4151 | * the shadow page tables. | |
4152 | */ | |
4153 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
4154 | ||
daa5b6c1 BG |
4155 | /* |
4156 | * If this is a direct root page, it doesn't have a write flooding | |
4157 | * count. Otherwise, clear the write flooding count. | |
4158 | */ | |
4159 | if (!new_role.direct) | |
4160 | __clear_sp_write_flooding_count( | |
4161 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
4162 | } |
4163 | ||
b5129100 | 4164 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) |
0aab33e4 | 4165 | { |
b5129100 | 4166 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu)); |
0aab33e4 | 4167 | } |
be01e8e2 | 4168 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 4169 | |
5777ed34 JR |
4170 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4171 | { | |
9f8fe504 | 4172 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4173 | } |
4174 | ||
54bf36aa | 4175 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 4176 | unsigned int access, int *nr_present) |
ce88decf XG |
4177 | { |
4178 | if (unlikely(is_mmio_spte(*sptep))) { | |
4179 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4180 | mmu_spte_clear_no_track(sptep); | |
4181 | return true; | |
4182 | } | |
4183 | ||
4184 | (*nr_present)++; | |
54bf36aa | 4185 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4186 | return true; |
4187 | } | |
4188 | ||
4189 | return false; | |
4190 | } | |
4191 | ||
37406aaa NHE |
4192 | #define PTTYPE_EPT 18 /* arbitrary */ |
4193 | #define PTTYPE PTTYPE_EPT | |
4194 | #include "paging_tmpl.h" | |
4195 | #undef PTTYPE | |
4196 | ||
6aa8b732 AK |
4197 | #define PTTYPE 64 |
4198 | #include "paging_tmpl.h" | |
4199 | #undef PTTYPE | |
4200 | ||
4201 | #define PTTYPE 32 | |
4202 | #include "paging_tmpl.h" | |
4203 | #undef PTTYPE | |
4204 | ||
6dc98b86 | 4205 | static void |
b705a277 | 4206 | __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check, |
5b7f575c | 4207 | u64 pa_bits_rsvd, int level, bool nx, bool gbpages, |
6fec2144 | 4208 | bool pse, bool amd) |
82725b20 | 4209 | { |
5f7dde7b | 4210 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4211 | u64 nonleaf_bit8_rsvd = 0; |
5b7f575c | 4212 | u64 high_bits_rsvd; |
82725b20 | 4213 | |
a0a64f50 | 4214 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4215 | |
6dc98b86 | 4216 | if (!gbpages) |
5f7dde7b | 4217 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 | 4218 | |
5b7f575c SC |
4219 | if (level == PT32E_ROOT_LEVEL) |
4220 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62); | |
4221 | else | |
4222 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); | |
4223 | ||
4224 | /* Note, NX doesn't exist in PDPTEs, this is handled below. */ | |
4225 | if (!nx) | |
4226 | high_bits_rsvd |= rsvd_bits(63, 63); | |
4227 | ||
a0c0feb5 PB |
4228 | /* |
4229 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4230 | * leaf entries) on AMD CPUs only. | |
4231 | */ | |
6fec2144 | 4232 | if (amd) |
a0c0feb5 PB |
4233 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4234 | ||
6dc98b86 | 4235 | switch (level) { |
82725b20 DE |
4236 | case PT32_ROOT_LEVEL: |
4237 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4238 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4239 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4240 | rsvd_check->rsvd_bits_mask[1][0] = | |
4241 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4242 | |
6dc98b86 | 4243 | if (!pse) { |
a0a64f50 | 4244 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4245 | break; |
4246 | } | |
4247 | ||
82725b20 DE |
4248 | if (is_cpuid_PSE36()) |
4249 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4250 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4251 | else |
4252 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4253 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4254 | break; |
4255 | case PT32E_ROOT_LEVEL: | |
5b7f575c SC |
4256 | rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) | |
4257 | high_bits_rsvd | | |
4258 | rsvd_bits(5, 8) | | |
4259 | rsvd_bits(1, 2); /* PDPTE */ | |
4260 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */ | |
4261 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */ | |
4262 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4263 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4264 | rsvd_check->rsvd_bits_mask[1][0] = |
4265 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4266 | break; |
855feb67 | 4267 | case PT64_ROOT_5LEVEL: |
5b7f575c SC |
4268 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | |
4269 | nonleaf_bit8_rsvd | | |
4270 | rsvd_bits(7, 7); | |
855feb67 YZ |
4271 | rsvd_check->rsvd_bits_mask[1][4] = |
4272 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4273 | fallthrough; |
2a7266a8 | 4274 | case PT64_ROOT_4LEVEL: |
5b7f575c SC |
4275 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | |
4276 | nonleaf_bit8_rsvd | | |
4277 | rsvd_bits(7, 7); | |
4278 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | | |
4279 | gbpages_bit_rsvd; | |
4280 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; | |
4281 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
a0a64f50 XG |
4282 | rsvd_check->rsvd_bits_mask[1][3] = |
4283 | rsvd_check->rsvd_bits_mask[0][3]; | |
5b7f575c SC |
4284 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | |
4285 | gbpages_bit_rsvd | | |
4286 | rsvd_bits(13, 29); | |
4287 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4288 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4289 | rsvd_check->rsvd_bits_mask[1][0] = |
4290 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4291 | break; |
4292 | } | |
4293 | } | |
4294 | ||
27de9250 SC |
4295 | static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu) |
4296 | { | |
4297 | /* | |
4298 | * If TDP is enabled, let the guest use GBPAGES if they're supported in | |
4299 | * hardware. The hardware page walker doesn't let KVM disable GBPAGES, | |
4300 | * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA | |
4301 | * walk for performance and complexity reasons. Not to mention KVM | |
4302 | * _can't_ solve the problem because GVA->GPA walks aren't visible to | |
4303 | * KVM once a TDP translation is installed. Mimic hardware behavior so | |
4304 | * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. | |
4305 | */ | |
4306 | return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : | |
4307 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); | |
4308 | } | |
4309 | ||
6dc98b86 XG |
4310 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4311 | struct kvm_mmu *context) | |
4312 | { | |
b705a277 | 4313 | __reset_rsvds_bits_mask(&context->guest_rsvd_check, |
5b7f575c | 4314 | vcpu->arch.reserved_gpa_bits, |
90599c28 | 4315 | context->root_level, is_efer_nx(context), |
27de9250 | 4316 | guest_can_use_gbpages(vcpu), |
4e9c0d80 | 4317 | is_cr4_pse(context), |
23493d0a | 4318 | guest_cpuid_is_amd_or_hygon(vcpu)); |
6dc98b86 XG |
4319 | } |
4320 | ||
81b8eebb XG |
4321 | static void |
4322 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4323 | u64 pa_bits_rsvd, bool execonly) |
25d92081 | 4324 | { |
5b7f575c | 4325 | u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); |
951f9fd7 | 4326 | u64 bad_mt_xwr; |
25d92081 | 4327 | |
5b7f575c SC |
4328 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7); |
4329 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7); | |
4330 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6); | |
4331 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6); | |
4332 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
25d92081 YZ |
4333 | |
4334 | /* large page */ | |
855feb67 | 4335 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 | 4336 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
5b7f575c SC |
4337 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29); |
4338 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20); | |
a0a64f50 | 4339 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4340 | |
951f9fd7 PB |
4341 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4342 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4343 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4344 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4345 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4346 | if (!execonly) { | |
4347 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4348 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4349 | } |
951f9fd7 | 4350 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4351 | } |
4352 | ||
81b8eebb XG |
4353 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4354 | struct kvm_mmu *context, bool execonly) | |
4355 | { | |
4356 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
5b7f575c | 4357 | vcpu->arch.reserved_gpa_bits, execonly); |
81b8eebb XG |
4358 | } |
4359 | ||
6f8e65a6 SC |
4360 | static inline u64 reserved_hpa_bits(void) |
4361 | { | |
4362 | return rsvd_bits(shadow_phys_bits, 63); | |
4363 | } | |
4364 | ||
c258b62b XG |
4365 | /* |
4366 | * the page table on host is the shadow page table for the page | |
4367 | * table in guest or amd nested guest, its mmu features completely | |
4368 | * follow the features in guest. | |
4369 | */ | |
16be1d12 SC |
4370 | static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, |
4371 | struct kvm_mmu *context) | |
c258b62b | 4372 | { |
112022bd SC |
4373 | /* |
4374 | * KVM uses NX when TDP is disabled to handle a variety of scenarios, | |
4375 | * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and | |
4376 | * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0. | |
4377 | * The iTLB multi-hit workaround can be toggled at any time, so assume | |
4378 | * NX can be used by any non-nested shadow MMU to avoid having to reset | |
4379 | * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled. | |
4380 | */ | |
90599c28 | 4381 | bool uses_nx = is_efer_nx(context) || !tdp_enabled; |
8c985b2d SC |
4382 | |
4383 | /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */ | |
4384 | bool is_amd = true; | |
4385 | /* KVM doesn't use 2-level page tables for the shadow MMU. */ | |
4386 | bool is_pse = false; | |
ea2800dd BS |
4387 | struct rsvd_bits_validate *shadow_zero_check; |
4388 | int i; | |
5f0b8199 | 4389 | |
8c985b2d SC |
4390 | WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL); |
4391 | ||
ea2800dd | 4392 | shadow_zero_check = &context->shadow_zero_check; |
b705a277 | 4393 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
5f0b8199 | 4394 | context->shadow_root_level, uses_nx, |
27de9250 | 4395 | guest_can_use_gbpages(vcpu), is_pse, is_amd); |
ea2800dd BS |
4396 | |
4397 | if (!shadow_me_mask) | |
4398 | return; | |
4399 | ||
4400 | for (i = context->shadow_root_level; --i >= 0;) { | |
4401 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4402 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4403 | } | |
4404 | ||
c258b62b | 4405 | } |
c258b62b | 4406 | |
6fec2144 PB |
4407 | static inline bool boot_cpu_is_amd(void) |
4408 | { | |
4409 | WARN_ON_ONCE(!tdp_enabled); | |
4410 | return shadow_x_mask == 0; | |
4411 | } | |
4412 | ||
c258b62b XG |
4413 | /* |
4414 | * the direct page table on host, use as much mmu features as | |
4415 | * possible, however, kvm currently does not do execution-protection. | |
4416 | */ | |
4417 | static void | |
4418 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4419 | struct kvm_mmu *context) | |
4420 | { | |
ea2800dd BS |
4421 | struct rsvd_bits_validate *shadow_zero_check; |
4422 | int i; | |
4423 | ||
4424 | shadow_zero_check = &context->shadow_zero_check; | |
4425 | ||
6fec2144 | 4426 | if (boot_cpu_is_amd()) |
b705a277 | 4427 | __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(), |
c258b62b | 4428 | context->shadow_root_level, false, |
b8291adc | 4429 | boot_cpu_has(X86_FEATURE_GBPAGES), |
8c985b2d | 4430 | false, true); |
c258b62b | 4431 | else |
ea2800dd | 4432 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
6f8e65a6 | 4433 | reserved_hpa_bits(), false); |
c258b62b | 4434 | |
ea2800dd BS |
4435 | if (!shadow_me_mask) |
4436 | return; | |
4437 | ||
4438 | for (i = context->shadow_root_level; --i >= 0;) { | |
4439 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4440 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4441 | } | |
c258b62b XG |
4442 | } |
4443 | ||
4444 | /* | |
4445 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4446 | * is the shadow page table for intel nested guest. | |
4447 | */ | |
4448 | static void | |
4449 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4450 | struct kvm_mmu *context, bool execonly) | |
4451 | { | |
4452 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
6f8e65a6 | 4453 | reserved_hpa_bits(), execonly); |
c258b62b XG |
4454 | } |
4455 | ||
09f037aa PB |
4456 | #define BYTE_MASK(access) \ |
4457 | ((1 & (access) ? 2 : 0) | \ | |
4458 | (2 & (access) ? 4 : 0) | \ | |
4459 | (3 & (access) ? 8 : 0) | \ | |
4460 | (4 & (access) ? 16 : 0) | \ | |
4461 | (5 & (access) ? 32 : 0) | \ | |
4462 | (6 & (access) ? 64 : 0) | \ | |
4463 | (7 & (access) ? 128 : 0)) | |
4464 | ||
4465 | ||
c596f147 | 4466 | static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept) |
97d64b78 | 4467 | { |
09f037aa PB |
4468 | unsigned byte; |
4469 | ||
4470 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4471 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4472 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4473 | ||
c596f147 SC |
4474 | bool cr4_smep = is_cr4_smep(mmu); |
4475 | bool cr4_smap = is_cr4_smap(mmu); | |
4476 | bool cr0_wp = is_cr0_wp(mmu); | |
90599c28 | 4477 | bool efer_nx = is_efer_nx(mmu); |
97d64b78 | 4478 | |
97d64b78 | 4479 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4480 | unsigned pfec = byte << 1; |
4481 | ||
97ec8c06 | 4482 | /* |
09f037aa PB |
4483 | * Each "*f" variable has a 1 bit for each UWX value |
4484 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4485 | */ |
97d64b78 | 4486 | |
09f037aa | 4487 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4488 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4489 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4490 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4491 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4492 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4493 | /* Faults from kernel mode fetches of user pages */ |
4494 | u8 smepf = 0; | |
4495 | /* Faults from kernel mode accesses of user pages */ | |
4496 | u8 smapf = 0; | |
4497 | ||
4498 | if (!ept) { | |
4499 | /* Faults from kernel mode accesses to user pages */ | |
4500 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4501 | ||
4502 | /* Not really needed: !nx will cause pte.nx to fault */ | |
90599c28 | 4503 | if (!efer_nx) |
09f037aa PB |
4504 | ff = 0; |
4505 | ||
4506 | /* Allow supervisor writes if !cr0.wp */ | |
4507 | if (!cr0_wp) | |
4508 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4509 | ||
4510 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4511 | if (cr4_smep) | |
4512 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4513 | ||
4514 | /* | |
4515 | * SMAP:kernel-mode data accesses from user-mode | |
4516 | * mappings should fault. A fault is considered | |
4517 | * as a SMAP violation if all of the following | |
39337ad1 | 4518 | * conditions are true: |
09f037aa PB |
4519 | * - X86_CR4_SMAP is set in CR4 |
4520 | * - A user page is accessed | |
4521 | * - The access is not a fetch | |
4522 | * - Page fault in kernel mode | |
4523 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4524 | * | |
4525 | * Here, we cover the first three conditions. | |
4526 | * The fourth is computed dynamically in permission_fault(); | |
4527 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4528 | * *not* subject to SMAP restrictions. | |
4529 | */ | |
4530 | if (cr4_smap) | |
4531 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4532 | } |
09f037aa PB |
4533 | |
4534 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4535 | } |
4536 | } | |
4537 | ||
2d344105 HH |
4538 | /* |
4539 | * PKU is an additional mechanism by which the paging controls access to | |
4540 | * user-mode addresses based on the value in the PKRU register. Protection | |
4541 | * key violations are reported through a bit in the page fault error code. | |
4542 | * Unlike other bits of the error code, the PK bit is not known at the | |
4543 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4544 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4545 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4546 | * | |
4547 | * In particular the following conditions come from the error code, the | |
4548 | * page tables and the machine state: | |
4549 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4550 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4551 | * - PK is always zero if U=0 in the page tables | |
4552 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4553 | * | |
4554 | * The PKRU bitmask caches the result of these four conditions. The error | |
4555 | * code (minus the P bit) and the page table's U bit form an index into the | |
4556 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4557 | * with the two bits of the PKRU register corresponding to the protection key. | |
4558 | * For the first three conditions above the bits will be 00, thus masking | |
4559 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4560 | * only will be masked away. | |
4561 | */ | |
2e4c0661 | 4562 | static void update_pkru_bitmask(struct kvm_mmu *mmu) |
2d344105 HH |
4563 | { |
4564 | unsigned bit; | |
4565 | bool wp; | |
4566 | ||
2e4c0661 | 4567 | if (!is_cr4_pke(mmu)) { |
2d344105 HH |
4568 | mmu->pkru_mask = 0; |
4569 | return; | |
4570 | } | |
4571 | ||
2e4c0661 | 4572 | wp = is_cr0_wp(mmu); |
2d344105 HH |
4573 | |
4574 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4575 | unsigned pfec, pkey_bits; | |
4576 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4577 | ||
4578 | pfec = bit << 1; | |
4579 | ff = pfec & PFERR_FETCH_MASK; | |
4580 | uf = pfec & PFERR_USER_MASK; | |
4581 | wf = pfec & PFERR_WRITE_MASK; | |
4582 | ||
4583 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4584 | pte_user = pfec & PFERR_RSVD_MASK; | |
4585 | ||
4586 | /* | |
4587 | * Only need to check the access which is not an | |
4588 | * instruction fetch and is to a user page. | |
4589 | */ | |
4590 | check_pkey = (!ff && pte_user); | |
4591 | /* | |
4592 | * write access is controlled by PKRU if it is a | |
4593 | * user access or CR0.WP = 1. | |
4594 | */ | |
4595 | check_write = check_pkey && wf && (uf || wp); | |
4596 | ||
4597 | /* PKRU.AD stops both read and write access. */ | |
4598 | pkey_bits = !!check_pkey; | |
4599 | /* PKRU.WD stops write access. */ | |
4600 | pkey_bits |= (!!check_write) << 1; | |
4601 | ||
4602 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4603 | } | |
4604 | } | |
4605 | ||
533f9a4b SC |
4606 | static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu, |
4607 | struct kvm_mmu *mmu) | |
6fd01b71 | 4608 | { |
533f9a4b SC |
4609 | if (!is_cr0_pg(mmu)) |
4610 | return; | |
6bb69c9b | 4611 | |
533f9a4b SC |
4612 | reset_rsvds_bits_mask(vcpu, mmu); |
4613 | update_permission_bitmask(mmu, false); | |
4614 | update_pkru_bitmask(mmu); | |
6fd01b71 AK |
4615 | } |
4616 | ||
fe660f72 | 4617 | static void paging64_init_context(struct kvm_mmu *context) |
6aa8b732 | 4618 | { |
6aa8b732 | 4619 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4620 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4621 | context->sync_page = paging64_sync_page; |
a7052897 | 4622 | context->invlpg = paging64_invlpg; |
c5a78f2b | 4623 | context->direct_map = false; |
6aa8b732 AK |
4624 | } |
4625 | ||
84a16226 | 4626 | static void paging32_init_context(struct kvm_mmu *context) |
6aa8b732 | 4627 | { |
6aa8b732 | 4628 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4629 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4630 | context->sync_page = paging32_sync_page; |
a7052897 | 4631 | context->invlpg = paging32_invlpg; |
c5a78f2b | 4632 | context->direct_map = false; |
6aa8b732 AK |
4633 | } |
4634 | ||
8626c120 SC |
4635 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu, |
4636 | struct kvm_mmu_role_regs *regs) | |
a336282d VK |
4637 | { |
4638 | union kvm_mmu_extended_role ext = {0}; | |
4639 | ||
ca8d664f SC |
4640 | if (____is_cr0_pg(regs)) { |
4641 | ext.cr0_pg = 1; | |
4642 | ext.cr4_pae = ____is_cr4_pae(regs); | |
4643 | ext.cr4_smep = ____is_cr4_smep(regs); | |
4644 | ext.cr4_smap = ____is_cr4_smap(regs); | |
4645 | ext.cr4_pse = ____is_cr4_pse(regs); | |
84c679f5 SC |
4646 | |
4647 | /* PKEY and LA57 are active iff long mode is active. */ | |
4648 | ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs); | |
4649 | ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs); | |
ca8d664f | 4650 | } |
a336282d VK |
4651 | |
4652 | ext.valid = 1; | |
4653 | ||
4654 | return ext; | |
4655 | } | |
4656 | ||
7dcd5755 | 4657 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
8626c120 | 4658 | struct kvm_mmu_role_regs *regs, |
7dcd5755 VK |
4659 | bool base_only) |
4660 | { | |
4661 | union kvm_mmu_role role = {0}; | |
4662 | ||
4663 | role.base.access = ACC_ALL; | |
ca8d664f SC |
4664 | if (____is_cr0_pg(regs)) { |
4665 | role.base.efer_nx = ____is_efer_nx(regs); | |
4666 | role.base.cr0_wp = ____is_cr0_wp(regs); | |
4667 | } | |
7dcd5755 VK |
4668 | role.base.smm = is_smm(vcpu); |
4669 | role.base.guest_mode = is_guest_mode(vcpu); | |
4670 | ||
4671 | if (base_only) | |
4672 | return role; | |
4673 | ||
8626c120 | 4674 | role.ext = kvm_calc_mmu_role_ext(vcpu, regs); |
7dcd5755 VK |
4675 | |
4676 | return role; | |
4677 | } | |
4678 | ||
d468d94b SC |
4679 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4680 | { | |
4681 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4682 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4683 | return 4; |
4684 | ||
83013059 | 4685 | return max_tdp_level; |
d468d94b SC |
4686 | } |
4687 | ||
7dcd5755 | 4688 | static union kvm_mmu_role |
8626c120 SC |
4689 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4690 | struct kvm_mmu_role_regs *regs, bool base_only) | |
9fa72119 | 4691 | { |
8626c120 | 4692 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
9fa72119 | 4693 | |
7dcd5755 | 4694 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4695 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4696 | role.base.direct = true; |
47c42e6b | 4697 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4698 | |
4699 | return role; | |
4700 | } | |
4701 | ||
8a3c1a33 | 4702 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4703 | { |
8c008659 | 4704 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
8626c120 | 4705 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 | 4706 | union kvm_mmu_role new_role = |
8626c120 | 4707 | kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false); |
fb72d167 | 4708 | |
7dcd5755 VK |
4709 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4710 | return; | |
4711 | ||
4712 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4713 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4714 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4715 | context->invlpg = NULL; |
d468d94b | 4716 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4717 | context->direct_map = true; |
d8dd54e0 | 4718 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4719 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4720 | context->inject_page_fault = kvm_inject_page_fault; |
f4bd6f73 | 4721 | context->root_level = role_regs_to_root_level(®s); |
fb72d167 | 4722 | |
36f26787 | 4723 | if (!is_cr0_pg(context)) |
fb72d167 | 4724 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
36f26787 | 4725 | else if (is_cr4_pae(context)) |
4d6931c3 | 4726 | context->gva_to_gpa = paging64_gva_to_gpa; |
f4bd6f73 | 4727 | else |
4d6931c3 | 4728 | context->gva_to_gpa = paging32_gva_to_gpa; |
fb72d167 | 4729 | |
533f9a4b | 4730 | reset_guest_paging_metadata(vcpu, context); |
c258b62b | 4731 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4732 | } |
4733 | ||
7dcd5755 | 4734 | static union kvm_mmu_role |
8626c120 SC |
4735 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, |
4736 | struct kvm_mmu_role_regs *regs, bool base_only) | |
7dcd5755 | 4737 | { |
8626c120 | 4738 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only); |
7dcd5755 | 4739 | |
8626c120 SC |
4740 | role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs); |
4741 | role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs); | |
ca8d664f | 4742 | role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs); |
9fa72119 | 4743 | |
59505b55 SC |
4744 | return role; |
4745 | } | |
4746 | ||
4747 | static union kvm_mmu_role | |
8626c120 SC |
4748 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, |
4749 | struct kvm_mmu_role_regs *regs, bool base_only) | |
59505b55 SC |
4750 | { |
4751 | union kvm_mmu_role role = | |
8626c120 | 4752 | kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only); |
59505b55 | 4753 | |
8626c120 | 4754 | role.base.direct = !____is_cr0_pg(regs); |
59505b55 | 4755 | |
8626c120 | 4756 | if (!____is_efer_lma(regs)) |
7dcd5755 | 4757 | role.base.level = PT32E_ROOT_LEVEL; |
8626c120 | 4758 | else if (____is_cr4_la57(regs)) |
7dcd5755 | 4759 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4760 | else |
7dcd5755 | 4761 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4762 | |
4763 | return role; | |
4764 | } | |
4765 | ||
8c008659 | 4766 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
594e91a1 | 4767 | struct kvm_mmu_role_regs *regs, |
8c008659 | 4768 | union kvm_mmu_role new_role) |
9fa72119 | 4769 | { |
18db1b17 SC |
4770 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4771 | return; | |
a770f6f2 | 4772 | |
7dcd5755 | 4773 | context->mmu_role.as_u64 = new_role.as_u64; |
18db1b17 | 4774 | |
36f26787 | 4775 | if (!is_cr0_pg(context)) |
84a16226 | 4776 | nonpaging_init_context(context); |
36f26787 | 4777 | else if (is_cr4_pae(context)) |
fe660f72 | 4778 | paging64_init_context(context); |
6aa8b732 | 4779 | else |
84a16226 | 4780 | paging32_init_context(context); |
f4bd6f73 | 4781 | context->root_level = role_regs_to_root_level(regs); |
a770f6f2 | 4782 | |
533f9a4b | 4783 | reset_guest_paging_metadata(vcpu, context); |
d555f705 SC |
4784 | context->shadow_root_level = new_role.base.level; |
4785 | ||
c258b62b | 4786 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4787 | } |
0f04a2ac | 4788 | |
594e91a1 SC |
4789 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, |
4790 | struct kvm_mmu_role_regs *regs) | |
0f04a2ac | 4791 | { |
8c008659 | 4792 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac | 4793 | union kvm_mmu_role new_role = |
8626c120 | 4794 | kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false); |
0f04a2ac | 4795 | |
18db1b17 | 4796 | shadow_mmu_init_context(vcpu, context, regs, new_role); |
0f04a2ac VK |
4797 | } |
4798 | ||
59505b55 | 4799 | static union kvm_mmu_role |
8626c120 SC |
4800 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu, |
4801 | struct kvm_mmu_role_regs *regs) | |
59505b55 SC |
4802 | { |
4803 | union kvm_mmu_role role = | |
8626c120 | 4804 | kvm_calc_shadow_root_page_role_common(vcpu, regs, false); |
59505b55 SC |
4805 | |
4806 | role.base.direct = false; | |
d468d94b | 4807 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4808 | |
4809 | return role; | |
4810 | } | |
4811 | ||
dbc4739b SC |
4812 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, |
4813 | unsigned long cr4, u64 efer, gpa_t nested_cr3) | |
0f04a2ac | 4814 | { |
8c008659 | 4815 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
594e91a1 SC |
4816 | struct kvm_mmu_role_regs regs = { |
4817 | .cr0 = cr0, | |
4818 | .cr4 = cr4, | |
4819 | .efer = efer, | |
4820 | }; | |
8626c120 | 4821 | union kvm_mmu_role new_role; |
0f04a2ac | 4822 | |
8626c120 | 4823 | new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s); |
a506fdd2 | 4824 | |
b5129100 | 4825 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base); |
a3322d5c | 4826 | |
18db1b17 | 4827 | shadow_mmu_init_context(vcpu, context, ®s, new_role); |
0f04a2ac VK |
4828 | } |
4829 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4830 | |
a336282d VK |
4831 | static union kvm_mmu_role |
4832 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4833 | bool execonly, u8 level) |
9fa72119 | 4834 | { |
552c69b1 | 4835 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4836 | |
47c42e6b SC |
4837 | /* SMM flag is inherited from root_mmu */ |
4838 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4839 | |
bb1fcc70 | 4840 | role.base.level = level; |
47c42e6b | 4841 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4842 | role.base.direct = false; |
4843 | role.base.ad_disabled = !accessed_dirty; | |
4844 | role.base.guest_mode = true; | |
4845 | role.base.access = ACC_ALL; | |
9fa72119 | 4846 | |
cd6767c3 SC |
4847 | /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */ |
4848 | role.ext.word = 0; | |
a336282d | 4849 | role.ext.execonly = execonly; |
cd6767c3 | 4850 | role.ext.valid = 1; |
9fa72119 JS |
4851 | |
4852 | return role; | |
4853 | } | |
4854 | ||
ae1e2d10 | 4855 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4856 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4857 | { |
8c008659 | 4858 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4859 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4860 | union kvm_mmu_role new_role = |
4861 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4862 | execonly, level); |
a336282d | 4863 | |
b5129100 | 4864 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base); |
a336282d | 4865 | |
a336282d VK |
4866 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4867 | return; | |
ad896af0 | 4868 | |
18db1b17 SC |
4869 | context->mmu_role.as_u64 = new_role.as_u64; |
4870 | ||
bb1fcc70 | 4871 | context->shadow_root_level = level; |
155a97a3 | 4872 | |
ae1e2d10 | 4873 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4874 | context->page_fault = ept_page_fault; |
4875 | context->gva_to_gpa = ept_gva_to_gpa; | |
4876 | context->sync_page = ept_sync_page; | |
4877 | context->invlpg = ept_invlpg; | |
bb1fcc70 | 4878 | context->root_level = level; |
155a97a3 | 4879 | context->direct_map = false; |
3dc773e7 | 4880 | |
c596f147 | 4881 | update_permission_bitmask(context, true); |
2e4c0661 | 4882 | update_pkru_bitmask(context); |
155a97a3 | 4883 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4884 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4885 | } |
4886 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4887 | ||
8a3c1a33 | 4888 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4889 | { |
8c008659 | 4890 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
594e91a1 | 4891 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
ad896af0 | 4892 | |
594e91a1 | 4893 | kvm_init_shadow_mmu(vcpu, ®s); |
929d1cfa | 4894 | |
d8dd54e0 | 4895 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4896 | context->get_pdptr = kvm_pdptr_read; |
4897 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4898 | } |
4899 | ||
8626c120 SC |
4900 | static union kvm_mmu_role |
4901 | kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs) | |
654430ef | 4902 | { |
8626c120 SC |
4903 | union kvm_mmu_role role; |
4904 | ||
4905 | role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false); | |
654430ef SC |
4906 | |
4907 | /* | |
4908 | * Nested MMUs are used only for walking L2's gva->gpa, they never have | |
4909 | * shadow pages of their own and so "direct" has no meaning. Set it | |
4910 | * to "true" to try to detect bogus usage of the nested MMU. | |
4911 | */ | |
4912 | role.base.direct = true; | |
f4bd6f73 | 4913 | role.base.level = role_regs_to_root_level(regs); |
654430ef SC |
4914 | return role; |
4915 | } | |
4916 | ||
8a3c1a33 | 4917 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4918 | { |
8626c120 SC |
4919 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
4920 | union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s); | |
02f59dc9 JR |
4921 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4922 | ||
bf627a92 VK |
4923 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4924 | return; | |
4925 | ||
4926 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4927 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4928 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 | 4929 | g_context->inject_page_fault = kvm_inject_page_fault; |
5472fcd4 | 4930 | g_context->root_level = new_role.base.level; |
02f59dc9 | 4931 | |
5efac074 PB |
4932 | /* |
4933 | * L2 page tables are never shadowed, so there is no need to sync | |
4934 | * SPTEs. | |
4935 | */ | |
4936 | g_context->invlpg = NULL; | |
4937 | ||
02f59dc9 | 4938 | /* |
44dd3ffa | 4939 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4940 | * L1's nested page tables (e.g. EPT12). The nested translation |
4941 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4942 | * L2's page tables as the first level of translation and L1's | |
4943 | * nested page tables as the second level of translation. Basically | |
4944 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 | 4945 | */ |
fa4b5588 | 4946 | if (!is_paging(vcpu)) |
02f59dc9 | 4947 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; |
fa4b5588 | 4948 | else if (is_long_mode(vcpu)) |
02f59dc9 | 4949 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
fa4b5588 | 4950 | else if (is_pae(vcpu)) |
02f59dc9 | 4951 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
fa4b5588 | 4952 | else |
02f59dc9 | 4953 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
02f59dc9 | 4954 | |
533f9a4b | 4955 | reset_guest_paging_metadata(vcpu, g_context); |
02f59dc9 JR |
4956 | } |
4957 | ||
c9060662 | 4958 | void kvm_init_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4959 | { |
02f59dc9 | 4960 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4961 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4962 | else if (tdp_enabled) |
e0c6db3e | 4963 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4964 | else |
e0c6db3e | 4965 | init_kvm_softmmu(vcpu); |
fb72d167 | 4966 | } |
1c53da3f | 4967 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4968 | |
9fa72119 JS |
4969 | static union kvm_mmu_page_role |
4970 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4971 | { | |
8626c120 | 4972 | struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu); |
7dcd5755 VK |
4973 | union kvm_mmu_role role; |
4974 | ||
9fa72119 | 4975 | if (tdp_enabled) |
8626c120 | 4976 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true); |
9fa72119 | 4977 | else |
8626c120 | 4978 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true); |
7dcd5755 VK |
4979 | |
4980 | return role.base; | |
9fa72119 | 4981 | } |
fb72d167 | 4982 | |
49c6f875 SC |
4983 | void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu) |
4984 | { | |
4985 | /* | |
4986 | * Invalidate all MMU roles to force them to reinitialize as CPUID | |
4987 | * information is factored into reserved bit calculations. | |
4988 | */ | |
4989 | vcpu->arch.root_mmu.mmu_role.ext.valid = 0; | |
4990 | vcpu->arch.guest_mmu.mmu_role.ext.valid = 0; | |
4991 | vcpu->arch.nested_mmu.mmu_role.ext.valid = 0; | |
4992 | kvm_mmu_reset_context(vcpu); | |
63f5a190 SC |
4993 | |
4994 | /* | |
4995 | * KVM does not correctly handle changing guest CPUID after KVM_RUN, as | |
4996 | * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't | |
4997 | * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page | |
4998 | * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise | |
4999 | * sweep the problem under the rug. | |
5000 | * | |
5001 | * KVM's horrific CPUID ABI makes the problem all but impossible to | |
5002 | * solve, as correctly handling multiple vCPU models (with respect to | |
5003 | * paging and physical address properties) in a single VM would require | |
5004 | * tracking all relevant CPUID information in kvm_mmu_page_role. That | |
5005 | * is very undesirable as it would double the memory requirements for | |
5006 | * gfn_track (see struct kvm_mmu_page_role comments), and in practice | |
5007 | * no sane VMM mucks with the core vCPU model on the fly. | |
5008 | */ | |
5009 | if (vcpu->arch.last_vmentry_cpu != -1) { | |
5010 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n"); | |
5011 | pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n"); | |
5012 | } | |
49c6f875 SC |
5013 | } |
5014 | ||
8a3c1a33 | 5015 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 5016 | { |
95f93af4 | 5017 | kvm_mmu_unload(vcpu); |
c9060662 | 5018 | kvm_init_mmu(vcpu); |
17c3ba9d | 5019 | } |
8668a3c4 | 5020 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
5021 | |
5022 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 5023 | { |
714b93da AK |
5024 | int r; |
5025 | ||
378f5cd6 | 5026 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
5027 | if (r) |
5028 | goto out; | |
748e52b9 | 5029 | r = mmu_alloc_special_roots(vcpu); |
17c3ba9d AK |
5030 | if (r) |
5031 | goto out; | |
4a38162e | 5032 | if (vcpu->arch.mmu->direct_map) |
6e6ec584 SC |
5033 | r = mmu_alloc_direct_roots(vcpu); |
5034 | else | |
5035 | r = mmu_alloc_shadow_roots(vcpu); | |
8986ecc0 MT |
5036 | if (r) |
5037 | goto out; | |
a91f387b SC |
5038 | |
5039 | kvm_mmu_sync_roots(vcpu); | |
5040 | ||
727a7e27 | 5041 | kvm_mmu_load_pgd(vcpu); |
b3646477 | 5042 | static_call(kvm_x86_tlb_flush_current)(vcpu); |
714b93da AK |
5043 | out: |
5044 | return r; | |
6aa8b732 | 5045 | } |
17c3ba9d AK |
5046 | |
5047 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5048 | { | |
14c07ad8 VK |
5049 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5050 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5051 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5052 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5053 | } |
6aa8b732 | 5054 | |
79539cec AK |
5055 | static bool need_remote_flush(u64 old, u64 new) |
5056 | { | |
5057 | if (!is_shadow_present_pte(old)) | |
5058 | return false; | |
5059 | if (!is_shadow_present_pte(new)) | |
5060 | return true; | |
5061 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5062 | return true; | |
53166229 GN |
5063 | old ^= shadow_nx_mask; |
5064 | new ^= shadow_nx_mask; | |
79539cec AK |
5065 | return (old & ~new & PT64_PERM_MASK) != 0; |
5066 | } | |
5067 | ||
889e5cbc | 5068 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5069 | int *bytes) |
da4a00f0 | 5070 | { |
0e0fee5c | 5071 | u64 gentry = 0; |
889e5cbc | 5072 | int r; |
72016f3a | 5073 | |
72016f3a AK |
5074 | /* |
5075 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5076 | * as the current vcpu paging mode since we update the sptes only |
5077 | * when they have the same mode. | |
72016f3a | 5078 | */ |
889e5cbc | 5079 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5080 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5081 | *gpa &= ~(gpa_t)7; |
5082 | *bytes = 8; | |
08e850c6 AK |
5083 | } |
5084 | ||
0e0fee5c JS |
5085 | if (*bytes == 4 || *bytes == 8) { |
5086 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5087 | if (r) | |
5088 | gentry = 0; | |
72016f3a AK |
5089 | } |
5090 | ||
889e5cbc XG |
5091 | return gentry; |
5092 | } | |
5093 | ||
5094 | /* | |
5095 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5096 | * or we may be forking, in which case it is better to unmap the page. | |
5097 | */ | |
a138fe75 | 5098 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5099 | { |
a30f47cb XG |
5100 | /* |
5101 | * Skip write-flooding detected for the sp whose level is 1, because | |
5102 | * it can become unsync, then the guest page is not write-protected. | |
5103 | */ | |
3bae0459 | 5104 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 5105 | return false; |
3246af0e | 5106 | |
e5691a81 XG |
5107 | atomic_inc(&sp->write_flooding_count); |
5108 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5109 | } |
5110 | ||
5111 | /* | |
5112 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5113 | * indicate a page is not used as a page table. | |
5114 | */ | |
5115 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5116 | int bytes) | |
5117 | { | |
5118 | unsigned offset, pte_size, misaligned; | |
5119 | ||
5120 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5121 | gpa, bytes, sp->role.word); | |
5122 | ||
5123 | offset = offset_in_page(gpa); | |
47c42e6b | 5124 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
5125 | |
5126 | /* | |
5127 | * Sometimes, the OS only writes the last one bytes to update status | |
5128 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5129 | */ | |
5130 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5131 | return false; | |
5132 | ||
889e5cbc XG |
5133 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5134 | misaligned |= bytes < 4; | |
5135 | ||
5136 | return misaligned; | |
5137 | } | |
5138 | ||
5139 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5140 | { | |
5141 | unsigned page_offset, quadrant; | |
5142 | u64 *spte; | |
5143 | int level; | |
5144 | ||
5145 | page_offset = offset_in_page(gpa); | |
5146 | level = sp->role.level; | |
5147 | *nspte = 1; | |
47c42e6b | 5148 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
5149 | page_offset <<= 1; /* 32->64 */ |
5150 | /* | |
5151 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5152 | * only 2MB. So we need to double the offset again | |
5153 | * and zap two pdes instead of one. | |
5154 | */ | |
5155 | if (level == PT32_ROOT_LEVEL) { | |
5156 | page_offset &= ~7; /* kill rounding error */ | |
5157 | page_offset <<= 1; | |
5158 | *nspte = 2; | |
5159 | } | |
5160 | quadrant = page_offset >> PAGE_SHIFT; | |
5161 | page_offset &= ~PAGE_MASK; | |
5162 | if (quadrant != sp->role.quadrant) | |
5163 | return NULL; | |
5164 | } | |
5165 | ||
5166 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5167 | return spte; | |
5168 | } | |
5169 | ||
13d268ca | 5170 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5171 | const u8 *new, int bytes, |
5172 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5173 | { |
5174 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5175 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5176 | LIST_HEAD(invalid_list); |
5177 | u64 entry, gentry, *spte; | |
5178 | int npte; | |
b8c67b7a | 5179 | bool remote_flush, local_flush; |
889e5cbc XG |
5180 | |
5181 | /* | |
5182 | * If we don't have indirect shadow pages, it means no page is | |
5183 | * write-protected, so we can exit simply. | |
5184 | */ | |
6aa7de05 | 5185 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5186 | return; |
5187 | ||
b8c67b7a | 5188 | remote_flush = local_flush = false; |
889e5cbc XG |
5189 | |
5190 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5191 | ||
889e5cbc XG |
5192 | /* |
5193 | * No need to care whether allocation memory is successful | |
d9f6e12f | 5194 | * or not since pte prefetch is skipped if it does not have |
889e5cbc XG |
5195 | * enough objects in the cache. |
5196 | */ | |
378f5cd6 | 5197 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc | 5198 | |
531810ca | 5199 | write_lock(&vcpu->kvm->mmu_lock); |
0e0fee5c JS |
5200 | |
5201 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5202 | ||
889e5cbc | 5203 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5204 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5205 | |
b67bfe0d | 5206 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5207 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5208 | detect_write_flooding(sp)) { |
b8c67b7a | 5209 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5210 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5211 | continue; |
5212 | } | |
889e5cbc XG |
5213 | |
5214 | spte = get_written_sptes(sp, gpa, &npte); | |
5215 | if (!spte) | |
5216 | continue; | |
5217 | ||
0671a8e7 | 5218 | local_flush = true; |
ac1b714e | 5219 | while (npte--) { |
79539cec | 5220 | entry = *spte; |
2de4085c | 5221 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
c5e2184d SC |
5222 | if (gentry && sp->role.level != PG_LEVEL_4K) |
5223 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
9bb4f6b1 | 5224 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5225 | remote_flush = true; |
ac1b714e | 5226 | ++spte; |
9b7a0325 | 5227 | } |
9b7a0325 | 5228 | } |
b8c67b7a | 5229 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5230 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
531810ca | 5231 | write_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5232 | } |
5233 | ||
736c291c | 5234 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5235 | void *insn, int insn_len) |
3067714c | 5236 | { |
92daa48b | 5237 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5238 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5239 | |
6948199a | 5240 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5241 | return RET_PF_RETRY; |
5242 | ||
9b8ebbdb | 5243 | r = RET_PF_INVALID; |
e9ee956e | 5244 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5245 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5246 | if (r == RET_PF_EMULATE) |
e9ee956e | 5247 | goto emulate; |
e9ee956e | 5248 | } |
3067714c | 5249 | |
9b8ebbdb | 5250 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5251 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5252 | lower_32_bits(error_code), false); | |
19025e7b | 5253 | if (KVM_BUG_ON(r == RET_PF_INVALID, vcpu->kvm)) |
7b367bc9 | 5254 | return -EIO; |
9b8ebbdb PB |
5255 | } |
5256 | ||
3067714c | 5257 | if (r < 0) |
e9ee956e | 5258 | return r; |
83a2ba4c SC |
5259 | if (r != RET_PF_EMULATE) |
5260 | return 1; | |
3067714c | 5261 | |
14727754 TL |
5262 | /* |
5263 | * Before emulating the instruction, check if the error code | |
5264 | * was due to a RO violation while translating the guest page. | |
5265 | * This can occur when using nested virtualization with nested | |
5266 | * paging in both guests. If true, we simply unprotect the page | |
5267 | * and resume the guest. | |
14727754 | 5268 | */ |
44dd3ffa | 5269 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5270 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5271 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5272 | return 1; |
5273 | } | |
5274 | ||
472faffa SC |
5275 | /* |
5276 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5277 | * optimistically try to just unprotect the page and let the processor | |
5278 | * re-execute the instruction that caused the page fault. Do not allow | |
5279 | * retrying MMIO emulation, as it's not only pointless but could also | |
5280 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5281 | * faulting on the non-existent MMIO address. Retrying an instruction |
5282 | * from a nested guest is also pointless and dangerous as we are only | |
5283 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5284 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5285 | */ |
736c291c | 5286 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5287 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5288 | emulate: |
736c291c | 5289 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5290 | insn_len); |
3067714c AK |
5291 | } |
5292 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5293 | ||
5efac074 PB |
5294 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5295 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5296 | { |
b94742c9 | 5297 | int i; |
7eb77e9f | 5298 | |
5efac074 PB |
5299 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5300 | if (mmu != &vcpu->arch.guest_mmu) { | |
5301 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5302 | if (is_noncanonical_address(gva, vcpu)) | |
5303 | return; | |
5304 | ||
b3646477 | 5305 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
5efac074 PB |
5306 | } |
5307 | ||
5308 | if (!mmu->invlpg) | |
faff8758 JS |
5309 | return; |
5310 | ||
5efac074 PB |
5311 | if (root_hpa == INVALID_PAGE) { |
5312 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5313 | |
5efac074 PB |
5314 | /* |
5315 | * INVLPG is required to invalidate any global mappings for the VA, | |
5316 | * irrespective of PCID. Since it would take us roughly similar amount | |
5317 | * of work to determine whether any of the prev_root mappings of the VA | |
5318 | * is marked global, or to just sync it blindly, so we might as well | |
5319 | * just always sync it. | |
5320 | * | |
5321 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5322 | * synced when switching to that cr3, so nothing needs to be done here | |
5323 | * for them. | |
5324 | */ | |
5325 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5326 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5327 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5328 | } else { | |
5329 | mmu->invlpg(vcpu, gva, root_hpa); | |
5330 | } | |
5331 | } | |
956bf353 | 5332 | |
5efac074 PB |
5333 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5334 | { | |
5335 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5336 | ++vcpu->stat.invlpg; |
5337 | } | |
5338 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5339 | ||
5efac074 | 5340 | |
eb4b248e JS |
5341 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5342 | { | |
44dd3ffa | 5343 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5344 | bool tlb_flush = false; |
b94742c9 | 5345 | uint i; |
eb4b248e JS |
5346 | |
5347 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5348 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5349 | tlb_flush = true; |
eb4b248e JS |
5350 | } |
5351 | ||
b94742c9 JS |
5352 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5353 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5354 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5355 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5356 | tlb_flush = true; | |
5357 | } | |
956bf353 | 5358 | } |
ade61e28 | 5359 | |
faff8758 | 5360 | if (tlb_flush) |
b3646477 | 5361 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
faff8758 | 5362 | |
eb4b248e JS |
5363 | ++vcpu->stat.invlpg; |
5364 | ||
5365 | /* | |
b94742c9 JS |
5366 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5367 | * synced when switching to that cr3, so nothing needs to be done here | |
5368 | * for them. | |
eb4b248e JS |
5369 | */ |
5370 | } | |
eb4b248e | 5371 | |
83013059 SC |
5372 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5373 | int tdp_huge_page_level) | |
18552672 | 5374 | { |
bde77235 | 5375 | tdp_enabled = enable_tdp; |
83013059 | 5376 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5377 | |
5378 | /* | |
1d92d2e8 | 5379 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5380 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5381 | * the kernel is not. But, KVM never creates a page size greater than | |
5382 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5383 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5384 | */ | |
5385 | if (tdp_enabled) | |
1d92d2e8 | 5386 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5387 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5388 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5389 | else |
1d92d2e8 | 5390 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5391 | } |
bde77235 | 5392 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5393 | |
5394 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
269e9552 HM |
5395 | typedef bool (*slot_level_handler) (struct kvm *kvm, |
5396 | struct kvm_rmap_head *rmap_head, | |
5397 | const struct kvm_memory_slot *slot); | |
85875a13 SC |
5398 | |
5399 | /* The caller should hold mmu-lock before calling this function. */ | |
5400 | static __always_inline bool | |
269e9552 | 5401 | slot_handle_level_range(struct kvm *kvm, const struct kvm_memory_slot *memslot, |
85875a13 | 5402 | slot_level_handler fn, int start_level, int end_level, |
1a61b7db SC |
5403 | gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield, |
5404 | bool flush) | |
85875a13 SC |
5405 | { |
5406 | struct slot_rmap_walk_iterator iterator; | |
85875a13 SC |
5407 | |
5408 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5409 | end_gfn, &iterator) { | |
5410 | if (iterator.rmap) | |
0a234f5d | 5411 | flush |= fn(kvm, iterator.rmap, memslot); |
85875a13 | 5412 | |
531810ca | 5413 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
302695a5 | 5414 | if (flush && flush_on_yield) { |
f285c633 BG |
5415 | kvm_flush_remote_tlbs_with_address(kvm, |
5416 | start_gfn, | |
5417 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5418 | flush = false; |
5419 | } | |
531810ca | 5420 | cond_resched_rwlock_write(&kvm->mmu_lock); |
85875a13 SC |
5421 | } |
5422 | } | |
5423 | ||
85875a13 SC |
5424 | return flush; |
5425 | } | |
5426 | ||
5427 | static __always_inline bool | |
269e9552 | 5428 | slot_handle_level(struct kvm *kvm, const struct kvm_memory_slot *memslot, |
85875a13 | 5429 | slot_level_handler fn, int start_level, int end_level, |
302695a5 | 5430 | bool flush_on_yield) |
85875a13 SC |
5431 | { |
5432 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5433 | end_level, memslot->base_gfn, | |
5434 | memslot->base_gfn + memslot->npages - 1, | |
1a61b7db | 5435 | flush_on_yield, false); |
85875a13 SC |
5436 | } |
5437 | ||
85875a13 | 5438 | static __always_inline bool |
269e9552 | 5439 | slot_handle_leaf(struct kvm *kvm, const struct kvm_memory_slot *memslot, |
302695a5 | 5440 | slot_level_handler fn, bool flush_on_yield) |
85875a13 | 5441 | { |
3bae0459 | 5442 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
302695a5 | 5443 | PG_LEVEL_4K, flush_on_yield); |
85875a13 SC |
5444 | } |
5445 | ||
1cfff4d9 | 5446 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5447 | { |
4a98623d SC |
5448 | if (!tdp_enabled && mmu->pae_root) |
5449 | set_memory_encrypted((unsigned long)mmu->pae_root, 1); | |
1cfff4d9 | 5450 | free_page((unsigned long)mmu->pae_root); |
03ca4589 | 5451 | free_page((unsigned long)mmu->pml4_root); |
6aa8b732 AK |
5452 | } |
5453 | ||
04d28e37 | 5454 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5455 | { |
17ac10ad | 5456 | struct page *page; |
6aa8b732 AK |
5457 | int i; |
5458 | ||
04d28e37 SC |
5459 | mmu->root_hpa = INVALID_PAGE; |
5460 | mmu->root_pgd = 0; | |
5461 | mmu->translate_gpa = translate_gpa; | |
5462 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5463 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5464 | ||
17ac10ad | 5465 | /* |
b6b80c78 SC |
5466 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5467 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5468 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5469 | * x86_64. Therefore we need to allocate the PDP table in the first | |
04d45551 SC |
5470 | * 4GB of memory, which happens to fit the DMA32 zone. TDP paging |
5471 | * generally doesn't use PAE paging and can skip allocating the PDP | |
5472 | * table. The main exception, handled here, is SVM's 32-bit NPT. The | |
5473 | * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit | |
5474 | * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). | |
17ac10ad | 5475 | */ |
d468d94b | 5476 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5477 | return 0; |
5478 | ||
254272ce | 5479 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5480 | if (!page) |
d7fa6ab2 WY |
5481 | return -ENOMEM; |
5482 | ||
1cfff4d9 | 5483 | mmu->pae_root = page_address(page); |
4a98623d SC |
5484 | |
5485 | /* | |
5486 | * CR3 is only 32 bits when PAE paging is used, thus it's impossible to | |
5487 | * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so | |
5488 | * that KVM's writes and the CPU's reads get along. Note, this is | |
5489 | * only necessary when using shadow paging, as 64-bit NPT can get at | |
5490 | * the C-bit even when shadowing 32-bit NPT, and SME isn't supported | |
5491 | * by 32-bit kernels (when KVM itself uses 32-bit NPT). | |
5492 | */ | |
5493 | if (!tdp_enabled) | |
5494 | set_memory_decrypted((unsigned long)mmu->pae_root, 1); | |
5495 | else | |
5496 | WARN_ON_ONCE(shadow_me_mask); | |
5497 | ||
17ac10ad | 5498 | for (i = 0; i < 4; ++i) |
c834e5e4 | 5499 | mmu->pae_root[i] = INVALID_PAE_ROOT; |
17ac10ad | 5500 | |
6aa8b732 | 5501 | return 0; |
6aa8b732 AK |
5502 | } |
5503 | ||
8018c27b | 5504 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5505 | { |
1cfff4d9 | 5506 | int ret; |
b94742c9 | 5507 | |
5962bfb7 | 5508 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5509 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5510 | ||
5962bfb7 | 5511 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5512 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5513 | |
96880883 SC |
5514 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5515 | ||
44dd3ffa VK |
5516 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5517 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5518 | |
14c07ad8 | 5519 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5520 | |
04d28e37 | 5521 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5522 | if (ret) |
5523 | return ret; | |
5524 | ||
04d28e37 | 5525 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5526 | if (ret) |
5527 | goto fail_allocate_root; | |
5528 | ||
5529 | return ret; | |
5530 | fail_allocate_root: | |
5531 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5532 | return ret; | |
6aa8b732 AK |
5533 | } |
5534 | ||
fbb158cb | 5535 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5536 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5537 | { | |
5538 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5539 | int nr_zapped, batch = 0; |
002c5f73 SC |
5540 | |
5541 | restart: | |
5542 | list_for_each_entry_safe_reverse(sp, node, | |
5543 | &kvm->arch.active_mmu_pages, link) { | |
5544 | /* | |
5545 | * No obsolete valid page exists before a newly created page | |
5546 | * since active_mmu_pages is a FIFO list. | |
5547 | */ | |
5548 | if (!is_obsolete_sp(kvm, sp)) | |
5549 | break; | |
5550 | ||
5551 | /* | |
f95eec9b SC |
5552 | * Invalid pages should never land back on the list of active |
5553 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5554 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5555 | */ |
f95eec9b | 5556 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5557 | continue; |
5558 | ||
4506ecf4 SC |
5559 | /* |
5560 | * No need to flush the TLB since we're only zapping shadow | |
5561 | * pages with an obsolete generation number and all vCPUS have | |
5562 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5563 | * be in active use by the guest. | |
5564 | */ | |
fbb158cb | 5565 | if (batch >= BATCH_ZAP_PAGES && |
531810ca | 5566 | cond_resched_rwlock_write(&kvm->mmu_lock)) { |
fbb158cb | 5567 | batch = 0; |
002c5f73 SC |
5568 | goto restart; |
5569 | } | |
5570 | ||
10605204 SC |
5571 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5572 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5573 | batch += nr_zapped; |
002c5f73 | 5574 | goto restart; |
fbb158cb | 5575 | } |
002c5f73 SC |
5576 | } |
5577 | ||
4506ecf4 SC |
5578 | /* |
5579 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5580 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5581 | * may reference the pages. | |
5582 | */ | |
10605204 | 5583 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5584 | } |
5585 | ||
5586 | /* | |
5587 | * Fast invalidate all shadow pages and use lock-break technique | |
5588 | * to zap obsolete pages. | |
5589 | * | |
5590 | * It's required when memslot is being deleted or VM is being | |
5591 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5592 | * not use any resource of the being-deleted slot or all slots | |
5593 | * after calling the function. | |
5594 | */ | |
5595 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5596 | { | |
ca333add SC |
5597 | lockdep_assert_held(&kvm->slots_lock); |
5598 | ||
531810ca | 5599 | write_lock(&kvm->mmu_lock); |
14a3c4f4 | 5600 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5601 | |
5602 | /* | |
5603 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5604 | * held for the entire duration of zapping obsolete pages, it's | |
5605 | * impossible for there to be multiple invalid generations associated | |
5606 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5607 | * one valid generation and (at most) one invalid generation. | |
5608 | */ | |
5609 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5610 | |
b7cccd39 BG |
5611 | /* In order to ensure all threads see this change when |
5612 | * handling the MMU reload signal, this must happen in the | |
5613 | * same critical section as kvm_reload_remote_mmus, and | |
5614 | * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages | |
5615 | * could drop the MMU lock and yield. | |
5616 | */ | |
5617 | if (is_tdp_mmu_enabled(kvm)) | |
5618 | kvm_tdp_mmu_invalidate_all_roots(kvm); | |
5619 | ||
4506ecf4 SC |
5620 | /* |
5621 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5622 | * Then all vcpus will switch to new shadow page table with the new | |
5623 | * mmu_valid_gen. | |
5624 | * | |
5625 | * Note: we need to do this under the protection of mmu_lock, | |
5626 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5627 | */ | |
5628 | kvm_reload_remote_mmus(kvm); | |
5629 | ||
002c5f73 | 5630 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 | 5631 | |
531810ca | 5632 | write_unlock(&kvm->mmu_lock); |
4c6654bd BG |
5633 | |
5634 | if (is_tdp_mmu_enabled(kvm)) { | |
5635 | read_lock(&kvm->mmu_lock); | |
5636 | kvm_tdp_mmu_zap_invalidated_roots(kvm); | |
5637 | read_unlock(&kvm->mmu_lock); | |
5638 | } | |
002c5f73 SC |
5639 | } |
5640 | ||
10605204 SC |
5641 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5642 | { | |
5643 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5644 | } | |
5645 | ||
b5f5fdca | 5646 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5647 | struct kvm_memory_slot *slot, |
5648 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5649 | { |
002c5f73 | 5650 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5651 | } |
5652 | ||
13d268ca | 5653 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5654 | { |
13d268ca | 5655 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5656 | |
ce25681d SC |
5657 | spin_lock_init(&kvm->arch.mmu_unsync_pages_lock); |
5658 | ||
d501f747 BG |
5659 | if (!kvm_mmu_init_tdp_mmu(kvm)) |
5660 | /* | |
5661 | * No smp_load/store wrappers needed here as we are in | |
5662 | * VM init and there cannot be any memslots / other threads | |
5663 | * accessing this struct kvm yet. | |
5664 | */ | |
5665 | kvm->arch.memslots_have_rmaps = true; | |
fe5db27d | 5666 | |
13d268ca | 5667 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5668 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5669 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5670 | } |
5671 | ||
13d268ca | 5672 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5673 | { |
13d268ca | 5674 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5675 | |
13d268ca | 5676 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5677 | |
5678 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5679 | } |
5680 | ||
88f58535 ML |
5681 | /* |
5682 | * Invalidate (zap) SPTEs that cover GFNs from gfn_start and up to gfn_end | |
5683 | * (not including it) | |
5684 | */ | |
efdfe536 XG |
5685 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5686 | { | |
5687 | struct kvm_memslots *slots; | |
5688 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5689 | int i; |
1a61b7db | 5690 | bool flush = false; |
efdfe536 | 5691 | |
5a324c24 SC |
5692 | write_lock(&kvm->mmu_lock); |
5693 | ||
edb298c6 ML |
5694 | kvm_inc_notifier_count(kvm, gfn_start, gfn_end); |
5695 | ||
e2209710 | 5696 | if (kvm_memslots_have_rmaps(kvm)) { |
e2209710 BG |
5697 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5698 | slots = __kvm_memslots(kvm, i); | |
5699 | kvm_for_each_memslot(memslot, slots) { | |
5700 | gfn_t start, end; | |
5701 | ||
5702 | start = max(gfn_start, memslot->base_gfn); | |
5703 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5704 | if (start >= end) | |
5705 | continue; | |
efdfe536 | 5706 | |
269e9552 HM |
5707 | flush = slot_handle_level_range(kvm, |
5708 | (const struct kvm_memory_slot *) memslot, | |
e2209710 BG |
5709 | kvm_zap_rmapp, PG_LEVEL_4K, |
5710 | KVM_MAX_HUGEPAGE_LEVEL, start, | |
5711 | end - 1, true, flush); | |
5712 | } | |
9da0e4d5 | 5713 | } |
e2209710 | 5714 | if (flush) |
2822da44 ML |
5715 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, |
5716 | gfn_end - gfn_start); | |
efdfe536 XG |
5717 | } |
5718 | ||
897218ff | 5719 | if (is_tdp_mmu_enabled(kvm)) { |
6103bc07 BG |
5720 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) |
5721 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start, | |
5a324c24 | 5722 | gfn_end, flush); |
2822da44 ML |
5723 | if (flush) |
5724 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, | |
5725 | gfn_end - gfn_start); | |
6103bc07 | 5726 | } |
5a324c24 SC |
5727 | |
5728 | if (flush) | |
5729 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end); | |
5730 | ||
edb298c6 ML |
5731 | kvm_dec_notifier_count(kvm, gfn_start, gfn_end); |
5732 | ||
5a324c24 | 5733 | write_unlock(&kvm->mmu_lock); |
efdfe536 XG |
5734 | } |
5735 | ||
018aabb5 | 5736 | static bool slot_rmap_write_protect(struct kvm *kvm, |
0a234f5d | 5737 | struct kvm_rmap_head *rmap_head, |
269e9552 | 5738 | const struct kvm_memory_slot *slot) |
d77aa73c | 5739 | { |
018aabb5 | 5740 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5741 | } |
5742 | ||
1c91cad4 | 5743 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
269e9552 | 5744 | const struct kvm_memory_slot *memslot, |
3c9bd400 | 5745 | int start_level) |
6aa8b732 | 5746 | { |
e2209710 | 5747 | bool flush = false; |
6aa8b732 | 5748 | |
e2209710 BG |
5749 | if (kvm_memslots_have_rmaps(kvm)) { |
5750 | write_lock(&kvm->mmu_lock); | |
5751 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, | |
5752 | start_level, KVM_MAX_HUGEPAGE_LEVEL, | |
5753 | false); | |
5754 | write_unlock(&kvm->mmu_lock); | |
5755 | } | |
198c74f4 | 5756 | |
24ae4cfa BG |
5757 | if (is_tdp_mmu_enabled(kvm)) { |
5758 | read_lock(&kvm->mmu_lock); | |
5759 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level); | |
5760 | read_unlock(&kvm->mmu_lock); | |
5761 | } | |
5762 | ||
198c74f4 XG |
5763 | /* |
5764 | * We can flush all the TLBs out of the mmu lock without TLB | |
5765 | * corruption since we just change the spte from writable to | |
5766 | * readonly so that we only need to care the case of changing | |
5767 | * spte from present to present (changing the spte from present | |
5768 | * to nonpresent will flush all the TLBs immediately), in other | |
5769 | * words, the only case we care is mmu_spte_update() where we | |
5fc3424f SC |
5770 | * have checked Host-writable | MMU-writable instead of |
5771 | * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK | |
5772 | * anymore. | |
198c74f4 | 5773 | */ |
d91ffee9 | 5774 | if (flush) |
7f42aa76 | 5775 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5776 | } |
37a7d8b0 | 5777 | |
3ea3b7fa | 5778 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
0a234f5d | 5779 | struct kvm_rmap_head *rmap_head, |
269e9552 | 5780 | const struct kvm_memory_slot *slot) |
3ea3b7fa WL |
5781 | { |
5782 | u64 *sptep; | |
5783 | struct rmap_iterator iter; | |
5784 | int need_tlb_flush = 0; | |
ba049e93 | 5785 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5786 | struct kvm_mmu_page *sp; |
5787 | ||
0d536790 | 5788 | restart: |
018aabb5 | 5789 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5790 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5791 | pfn = spte_to_pfn(*sptep); |
5792 | ||
5793 | /* | |
decf6333 XG |
5794 | * We cannot do huge page mapping for indirect shadow pages, |
5795 | * which are found on the last rmap (level = 1) when not using | |
5796 | * tdp; such shadow pages are synced with the page table in | |
5797 | * the guest, and the guest page table is using 4K page size | |
5798 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5799 | */ |
a78986aa | 5800 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
9eba50f8 SC |
5801 | sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn, |
5802 | pfn, PG_LEVEL_NUM)) { | |
e7912386 | 5803 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5804 | |
5805 | if (kvm_available_flush_tlb_with_range()) | |
5806 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5807 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5808 | else | |
5809 | need_tlb_flush = 1; | |
5810 | ||
0d536790 XG |
5811 | goto restart; |
5812 | } | |
3ea3b7fa WL |
5813 | } |
5814 | ||
5815 | return need_tlb_flush; | |
5816 | } | |
5817 | ||
5818 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
269e9552 | 5819 | const struct kvm_memory_slot *slot) |
3ea3b7fa | 5820 | { |
31c65657 | 5821 | bool flush = false; |
14881998 | 5822 | |
e2209710 BG |
5823 | if (kvm_memslots_have_rmaps(kvm)) { |
5824 | write_lock(&kvm->mmu_lock); | |
5825 | flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true); | |
5826 | if (flush) | |
5827 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5828 | write_unlock(&kvm->mmu_lock); | |
5829 | } | |
2db6f772 BG |
5830 | |
5831 | if (is_tdp_mmu_enabled(kvm)) { | |
2db6f772 BG |
5832 | read_lock(&kvm->mmu_lock); |
5833 | flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush); | |
5834 | if (flush) | |
5835 | kvm_arch_flush_remote_tlbs_memslot(kvm, slot); | |
5836 | read_unlock(&kvm->mmu_lock); | |
5837 | } | |
3ea3b7fa WL |
5838 | } |
5839 | ||
b3594ffb | 5840 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
6c9dd6d2 | 5841 | const struct kvm_memory_slot *memslot) |
b3594ffb SC |
5842 | { |
5843 | /* | |
7f42aa76 | 5844 | * All current use cases for flushing the TLBs for a specific memslot |
302695a5 | 5845 | * related to dirty logging, and many do the TLB flush out of mmu_lock. |
7f42aa76 SC |
5846 | * The interaction between the various operations on memslot must be |
5847 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5848 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5849 | */ |
5850 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5851 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5852 | memslot->npages); | |
b3594ffb SC |
5853 | } |
5854 | ||
f4b4b180 | 5855 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
269e9552 | 5856 | const struct kvm_memory_slot *memslot) |
f4b4b180 | 5857 | { |
e2209710 | 5858 | bool flush = false; |
f4b4b180 | 5859 | |
e2209710 BG |
5860 | if (kvm_memslots_have_rmaps(kvm)) { |
5861 | write_lock(&kvm->mmu_lock); | |
5862 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, | |
5863 | false); | |
5864 | write_unlock(&kvm->mmu_lock); | |
5865 | } | |
f4b4b180 | 5866 | |
24ae4cfa BG |
5867 | if (is_tdp_mmu_enabled(kvm)) { |
5868 | read_lock(&kvm->mmu_lock); | |
5869 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); | |
5870 | read_unlock(&kvm->mmu_lock); | |
5871 | } | |
5872 | ||
f4b4b180 KH |
5873 | /* |
5874 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5875 | * function is only used for dirty logging, in which case flushing TLB | |
5876 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5877 | * dirty_bitmap. | |
5878 | */ | |
5879 | if (flush) | |
7f42aa76 | 5880 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 | 5881 | } |
f4b4b180 | 5882 | |
92f58b5c | 5883 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5884 | { |
5885 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5886 | LIST_HEAD(invalid_list); |
83cdb568 | 5887 | int ign; |
5304b8d3 | 5888 | |
531810ca | 5889 | write_lock(&kvm->mmu_lock); |
5304b8d3 | 5890 | restart: |
8a674adc | 5891 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5892 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5893 | continue; |
92f58b5c | 5894 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5895 | goto restart; |
531810ca | 5896 | if (cond_resched_rwlock_write(&kvm->mmu_lock)) |
5304b8d3 XG |
5897 | goto restart; |
5898 | } | |
5899 | ||
4771450c | 5900 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 | 5901 | |
897218ff | 5902 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5903 | kvm_tdp_mmu_zap_all(kvm); |
5904 | ||
531810ca | 5905 | write_unlock(&kvm->mmu_lock); |
5304b8d3 XG |
5906 | } |
5907 | ||
15248258 | 5908 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5909 | { |
164bf7e5 | 5910 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5911 | |
164bf7e5 | 5912 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5913 | |
f8f55942 | 5914 | /* |
e1359e2b SC |
5915 | * Generation numbers are incremented in multiples of the number of |
5916 | * address spaces in order to provide unique generations across all | |
5917 | * address spaces. Strip what is effectively the address space | |
5918 | * modifier prior to checking for a wrap of the MMIO generation so | |
5919 | * that a wrap in any address space is detected. | |
5920 | */ | |
5921 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5922 | ||
f8f55942 | 5923 | /* |
e1359e2b | 5924 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5925 | * zap all shadow pages. |
f8f55942 | 5926 | */ |
e1359e2b | 5927 | if (unlikely(gen == 0)) { |
ae0f5499 | 5928 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5929 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5930 | } |
f8f55942 XG |
5931 | } |
5932 | ||
70534a73 DC |
5933 | static unsigned long |
5934 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5935 | { |
5936 | struct kvm *kvm; | |
1495f230 | 5937 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5938 | unsigned long freed = 0; |
3ee16c81 | 5939 | |
0d9ce162 | 5940 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5941 | |
5942 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5943 | int idx; |
d98ba053 | 5944 | LIST_HEAD(invalid_list); |
3ee16c81 | 5945 | |
35f2d16b TY |
5946 | /* |
5947 | * Never scan more than sc->nr_to_scan VM instances. | |
5948 | * Will not hit this condition practically since we do not try | |
5949 | * to shrink more than one VM and it is very unlikely to see | |
5950 | * !n_used_mmu_pages so many times. | |
5951 | */ | |
5952 | if (!nr_to_scan--) | |
5953 | break; | |
19526396 GN |
5954 | /* |
5955 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5956 | * here. We may skip a VM instance errorneosly, but we do not | |
5957 | * want to shrink a VM that only started to populate its MMU | |
5958 | * anyway. | |
5959 | */ | |
10605204 SC |
5960 | if (!kvm->arch.n_used_mmu_pages && |
5961 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5962 | continue; |
19526396 | 5963 | |
f656ce01 | 5964 | idx = srcu_read_lock(&kvm->srcu); |
531810ca | 5965 | write_lock(&kvm->mmu_lock); |
3ee16c81 | 5966 | |
10605204 SC |
5967 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5968 | kvm_mmu_commit_zap_page(kvm, | |
5969 | &kvm->arch.zapped_obsolete_pages); | |
5970 | goto unlock; | |
5971 | } | |
5972 | ||
ebdb292d | 5973 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5974 | |
10605204 | 5975 | unlock: |
531810ca | 5976 | write_unlock(&kvm->mmu_lock); |
f656ce01 | 5977 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5978 | |
70534a73 DC |
5979 | /* |
5980 | * unfair on small ones | |
5981 | * per-vm shrinkers cry out | |
5982 | * sadness comes quickly | |
5983 | */ | |
19526396 GN |
5984 | list_move_tail(&kvm->vm_list, &vm_list); |
5985 | break; | |
3ee16c81 | 5986 | } |
3ee16c81 | 5987 | |
0d9ce162 | 5988 | mutex_unlock(&kvm_lock); |
70534a73 | 5989 | return freed; |
70534a73 DC |
5990 | } |
5991 | ||
5992 | static unsigned long | |
5993 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5994 | { | |
45221ab6 | 5995 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5996 | } |
5997 | ||
5998 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5999 | .count_objects = mmu_shrink_count, |
6000 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
6001 | .seeks = DEFAULT_SEEKS * 10, |
6002 | }; | |
6003 | ||
2ddfd20e | 6004 | static void mmu_destroy_caches(void) |
b5a33a75 | 6005 | { |
c1bd743e TH |
6006 | kmem_cache_destroy(pte_list_desc_cache); |
6007 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
6008 | } |
6009 | ||
b8e8c830 PB |
6010 | static bool get_nx_auto_mode(void) |
6011 | { | |
6012 | /* Return true when CPU has the bug, and mitigations are ON */ | |
6013 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
6014 | } | |
6015 | ||
6016 | static void __set_nx_huge_pages(bool val) | |
6017 | { | |
6018 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
6019 | } | |
6020 | ||
6021 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
6022 | { | |
6023 | bool old_val = nx_huge_pages; | |
6024 | bool new_val; | |
6025 | ||
6026 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
6027 | if (sysfs_streq(val, "off")) | |
6028 | new_val = 0; | |
6029 | else if (sysfs_streq(val, "force")) | |
6030 | new_val = 1; | |
6031 | else if (sysfs_streq(val, "auto")) | |
6032 | new_val = get_nx_auto_mode(); | |
6033 | else if (strtobool(val, &new_val) < 0) | |
6034 | return -EINVAL; | |
6035 | ||
6036 | __set_nx_huge_pages(new_val); | |
6037 | ||
6038 | if (new_val != old_val) { | |
6039 | struct kvm *kvm; | |
b8e8c830 PB |
6040 | |
6041 | mutex_lock(&kvm_lock); | |
6042 | ||
6043 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 6044 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 6045 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 6046 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
6047 | |
6048 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
6049 | } |
6050 | mutex_unlock(&kvm_lock); | |
6051 | } | |
6052 | ||
6053 | return 0; | |
6054 | } | |
6055 | ||
b5a33a75 AK |
6056 | int kvm_mmu_module_init(void) |
6057 | { | |
ab271bd4 AB |
6058 | int ret = -ENOMEM; |
6059 | ||
b8e8c830 PB |
6060 | if (nx_huge_pages == -1) |
6061 | __set_nx_huge_pages(get_nx_auto_mode()); | |
6062 | ||
36d9594d VK |
6063 | /* |
6064 | * MMU roles use union aliasing which is, generally speaking, an | |
6065 | * undefined behavior. However, we supposedly know how compilers behave | |
6066 | * and the current status quo is unlikely to change. Guardians below are | |
6067 | * supposed to let us know if the assumption becomes false. | |
6068 | */ | |
6069 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6070 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6071 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6072 | ||
28a1f3ac | 6073 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6074 | |
53c07b18 XG |
6075 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6076 | sizeof(struct pte_list_desc), | |
46bea48a | 6077 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6078 | if (!pte_list_desc_cache) |
ab271bd4 | 6079 | goto out; |
b5a33a75 | 6080 | |
d3d25b04 AK |
6081 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6082 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6083 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6084 | if (!mmu_page_header_cache) |
ab271bd4 | 6085 | goto out; |
d3d25b04 | 6086 | |
908c7f19 | 6087 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6088 | goto out; |
45bf21a8 | 6089 | |
ab271bd4 AB |
6090 | ret = register_shrinker(&mmu_shrinker); |
6091 | if (ret) | |
6092 | goto out; | |
3ee16c81 | 6093 | |
b5a33a75 AK |
6094 | return 0; |
6095 | ||
ab271bd4 | 6096 | out: |
3ee16c81 | 6097 | mmu_destroy_caches(); |
ab271bd4 | 6098 | return ret; |
b5a33a75 AK |
6099 | } |
6100 | ||
3ad82a7e | 6101 | /* |
39337ad1 | 6102 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 6103 | */ |
bc8a3d89 | 6104 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 6105 | { |
bc8a3d89 BG |
6106 | unsigned long nr_mmu_pages; |
6107 | unsigned long nr_pages = 0; | |
bc6678a3 | 6108 | struct kvm_memslots *slots; |
be6ba0f0 | 6109 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6110 | int i; |
3ad82a7e | 6111 | |
9da0e4d5 PB |
6112 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6113 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6114 | |
9da0e4d5 PB |
6115 | kvm_for_each_memslot(memslot, slots) |
6116 | nr_pages += memslot->npages; | |
6117 | } | |
3ad82a7e ZX |
6118 | |
6119 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 6120 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6121 | |
6122 | return nr_mmu_pages; | |
6123 | } | |
6124 | ||
c42fffe3 XG |
6125 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6126 | { | |
95f93af4 | 6127 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
6128 | free_mmu_pages(&vcpu->arch.root_mmu); |
6129 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 6130 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
6131 | } |
6132 | ||
b034cf01 XG |
6133 | void kvm_mmu_module_exit(void) |
6134 | { | |
6135 | mmu_destroy_caches(); | |
6136 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6137 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6138 | mmu_audit_disable(); |
6139 | } | |
1aa9b957 JS |
6140 | |
6141 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
6142 | { | |
6143 | unsigned int old_val; | |
6144 | int err; | |
6145 | ||
6146 | old_val = nx_huge_pages_recovery_ratio; | |
6147 | err = param_set_uint(val, kp); | |
6148 | if (err) | |
6149 | return err; | |
6150 | ||
6151 | if (READ_ONCE(nx_huge_pages) && | |
6152 | !old_val && nx_huge_pages_recovery_ratio) { | |
6153 | struct kvm *kvm; | |
6154 | ||
6155 | mutex_lock(&kvm_lock); | |
6156 | ||
6157 | list_for_each_entry(kvm, &vm_list, vm_list) | |
6158 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
6159 | ||
6160 | mutex_unlock(&kvm_lock); | |
6161 | } | |
6162 | ||
6163 | return err; | |
6164 | } | |
6165 | ||
6166 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
6167 | { | |
ade74e14 | 6168 | unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits; |
1aa9b957 JS |
6169 | int rcu_idx; |
6170 | struct kvm_mmu_page *sp; | |
6171 | unsigned int ratio; | |
6172 | LIST_HEAD(invalid_list); | |
048f4980 | 6173 | bool flush = false; |
1aa9b957 JS |
6174 | ulong to_zap; |
6175 | ||
6176 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
531810ca | 6177 | write_lock(&kvm->mmu_lock); |
1aa9b957 JS |
6178 | |
6179 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
ade74e14 | 6180 | to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0; |
7d919c7a SC |
6181 | for ( ; to_zap; --to_zap) { |
6182 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
6183 | break; | |
6184 | ||
1aa9b957 JS |
6185 | /* |
6186 | * We use a separate list instead of just using active_mmu_pages | |
6187 | * because the number of lpage_disallowed pages is expected to | |
6188 | * be relatively small compared to the total. | |
6189 | */ | |
6190 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
6191 | struct kvm_mmu_page, | |
6192 | lpage_disallowed_link); | |
6193 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
897218ff | 6194 | if (is_tdp_mmu_page(sp)) { |
315f02c6 | 6195 | flush |= kvm_tdp_mmu_zap_sp(kvm, sp); |
8d1a182e | 6196 | } else { |
29cf0f50 BG |
6197 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
6198 | WARN_ON_ONCE(sp->lpage_disallowed); | |
6199 | } | |
1aa9b957 | 6200 | |
531810ca | 6201 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
048f4980 | 6202 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
531810ca | 6203 | cond_resched_rwlock_write(&kvm->mmu_lock); |
048f4980 | 6204 | flush = false; |
1aa9b957 JS |
6205 | } |
6206 | } | |
048f4980 | 6207 | kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush); |
1aa9b957 | 6208 | |
531810ca | 6209 | write_unlock(&kvm->mmu_lock); |
1aa9b957 JS |
6210 | srcu_read_unlock(&kvm->srcu, rcu_idx); |
6211 | } | |
6212 | ||
6213 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6214 | { | |
6215 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6216 | ? start_time + 60 * HZ - get_jiffies_64() | |
6217 | : MAX_SCHEDULE_TIMEOUT; | |
6218 | } | |
6219 | ||
6220 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6221 | { | |
6222 | u64 start_time; | |
6223 | long remaining_time; | |
6224 | ||
6225 | while (true) { | |
6226 | start_time = get_jiffies_64(); | |
6227 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6228 | ||
6229 | set_current_state(TASK_INTERRUPTIBLE); | |
6230 | while (!kthread_should_stop() && remaining_time > 0) { | |
6231 | schedule_timeout(remaining_time); | |
6232 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6233 | set_current_state(TASK_INTERRUPTIBLE); | |
6234 | } | |
6235 | ||
6236 | set_current_state(TASK_RUNNING); | |
6237 | ||
6238 | if (kthread_should_stop()) | |
6239 | return 0; | |
6240 | ||
6241 | kvm_recover_nx_lpages(kvm); | |
6242 | } | |
6243 | } | |
6244 | ||
6245 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6246 | { | |
6247 | int err; | |
6248 | ||
6249 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6250 | "kvm-nx-lpage-recovery", | |
6251 | &kvm->arch.nx_lpage_recovery_thread); | |
6252 | if (!err) | |
6253 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6254 | ||
6255 | return err; | |
6256 | } | |
6257 | ||
6258 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6259 | { | |
6260 | if (kvm->arch.nx_lpage_recovery_thread) | |
6261 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6262 | } |