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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
13673a90 | 51 | #include <asm/vmx.h> |
3d0c27ad | 52 | #include <asm/kvm_page_track.h> |
1261bfa3 | 53 | #include "trace.h" |
6aa8b732 | 54 | |
b8e8c830 PB |
55 | extern bool itlb_multihit_kvm_mitigation; |
56 | ||
57 | static int __read_mostly nx_huge_pages = -1; | |
13fb5927 PB |
58 | #ifdef CONFIG_PREEMPT_RT |
59 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
60 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
61 | #else | |
1aa9b957 | 62 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 63 | #endif |
b8e8c830 PB |
64 | |
65 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 66 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 67 | |
d5d6c18d | 68 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
69 | .set = set_nx_huge_pages, |
70 | .get = param_get_bool, | |
71 | }; | |
72 | ||
d5d6c18d | 73 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
74 | .set = set_nx_huge_pages_recovery_ratio, |
75 | .get = param_get_uint, | |
76 | }; | |
77 | ||
b8e8c830 PB |
78 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
79 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
80 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
81 | &nx_huge_pages_recovery_ratio, 0644); | |
82 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 83 | |
71fe7013 SC |
84 | static bool __read_mostly force_flush_and_sync_on_reuse; |
85 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
86 | ||
18552672 JR |
87 | /* |
88 | * When setting this variable to true it enables Two-Dimensional-Paging | |
89 | * where the hardware walks 2 page tables: | |
90 | * 1. the guest-virtual to guest-physical | |
91 | * 2. while doing 1. it walks guest-physical to host-physical | |
92 | * If the hardware supports that we don't need to do shadow paging. | |
93 | */ | |
2f333bcb | 94 | bool tdp_enabled = false; |
18552672 | 95 | |
1d92d2e8 | 96 | static int max_huge_page_level __read_mostly; |
83013059 | 97 | static int max_tdp_level __read_mostly; |
703c335d | 98 | |
8b1fe17c XG |
99 | enum { |
100 | AUDIT_PRE_PAGE_FAULT, | |
101 | AUDIT_POST_PAGE_FAULT, | |
102 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
103 | AUDIT_POST_PTE_WRITE, |
104 | AUDIT_PRE_SYNC, | |
105 | AUDIT_POST_SYNC | |
8b1fe17c | 106 | }; |
37a7d8b0 | 107 | |
37a7d8b0 | 108 | #ifdef MMU_DEBUG |
5a9624af | 109 | bool dbg = 0; |
fa4a2c08 | 110 | module_param(dbg, bool, 0644); |
d6c69ee9 | 111 | #endif |
6aa8b732 | 112 | |
957ed9ef XG |
113 | #define PTE_PREFETCH_NUM 8 |
114 | ||
6aa8b732 AK |
115 | #define PT32_LEVEL_BITS 10 |
116 | ||
117 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 118 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 119 | |
e04da980 JR |
120 | #define PT32_LVL_OFFSET_MASK(level) \ |
121 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
122 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
123 | |
124 | #define PT32_INDEX(address, level)\ | |
125 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
126 | ||
127 | ||
6aa8b732 AK |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
90bb6fc5 AK |
135 | #include <trace/events/kvm.h> |
136 | ||
220f773a TY |
137 | /* make pte_list_desc fit well in cache line */ |
138 | #define PTE_LIST_EXT 3 | |
139 | ||
9b8ebbdb | 140 | /* |
c4371c2a SC |
141 | * Return values of handle_mmio_page_fault, mmu.page_fault, and fast_page_fault(). |
142 | * | |
9b8ebbdb PB |
143 | * RET_PF_RETRY: let CPU fault again on the address. |
144 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
9b8ebbdb | 145 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. |
c4371c2a SC |
146 | * RET_PF_FIXED: The faulting entry has been fixed. |
147 | * RET_PF_SPURIOUS: The faulting entry was already fixed, e.g. by another vCPU. | |
9b8ebbdb PB |
148 | */ |
149 | enum { | |
150 | RET_PF_RETRY = 0, | |
c4371c2a SC |
151 | RET_PF_EMULATE, |
152 | RET_PF_INVALID, | |
153 | RET_PF_FIXED, | |
154 | RET_PF_SPURIOUS, | |
9b8ebbdb PB |
155 | }; |
156 | ||
53c07b18 XG |
157 | struct pte_list_desc { |
158 | u64 *sptes[PTE_LIST_EXT]; | |
159 | struct pte_list_desc *more; | |
cd4a4e53 AK |
160 | }; |
161 | ||
2d11123a AK |
162 | struct kvm_shadow_walk_iterator { |
163 | u64 addr; | |
164 | hpa_t shadow_addr; | |
2d11123a | 165 | u64 *sptep; |
dd3bfd59 | 166 | int level; |
2d11123a AK |
167 | unsigned index; |
168 | }; | |
169 | ||
7eb77e9f JS |
170 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
171 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
172 | (_root), (_addr)); \ | |
173 | shadow_walk_okay(&(_walker)); \ | |
174 | shadow_walk_next(&(_walker))) | |
175 | ||
176 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
177 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
178 | shadow_walk_okay(&(_walker)); \ | |
179 | shadow_walk_next(&(_walker))) | |
180 | ||
c2a2ac2b XG |
181 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
182 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
183 | shadow_walk_okay(&(_walker)) && \ | |
184 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
185 | __shadow_walk_next(&(_walker), spte)) | |
186 | ||
53c07b18 | 187 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 188 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 189 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 190 | |
ce88decf | 191 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
192 | static union kvm_mmu_page_role |
193 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 194 | |
335e192a PB |
195 | #define CREATE_TRACE_POINTS |
196 | #include "mmutrace.h" | |
197 | ||
40ef75a7 LT |
198 | |
199 | static inline bool kvm_available_flush_tlb_with_range(void) | |
200 | { | |
afaf0b2f | 201 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
202 | } |
203 | ||
204 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
205 | struct kvm_tlb_range *range) | |
206 | { | |
207 | int ret = -ENOTSUPP; | |
208 | ||
afaf0b2f SC |
209 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
210 | ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range); | |
40ef75a7 LT |
211 | |
212 | if (ret) | |
213 | kvm_flush_remote_tlbs(kvm); | |
214 | } | |
215 | ||
2f2fad08 | 216 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
217 | u64 start_gfn, u64 pages) |
218 | { | |
219 | struct kvm_tlb_range range; | |
220 | ||
221 | range.start_gfn = start_gfn; | |
222 | range.pages = pages; | |
223 | ||
224 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
225 | } | |
226 | ||
5a9624af | 227 | bool is_nx_huge_page_enabled(void) |
b8e8c830 PB |
228 | { |
229 | return READ_ONCE(nx_huge_pages); | |
230 | } | |
231 | ||
8f79b064 BG |
232 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
233 | unsigned int access) | |
234 | { | |
235 | u64 mask = make_mmio_spte(vcpu, gfn, access); | |
236 | unsigned int gen = get_mmio_spte_generation(mask); | |
237 | ||
238 | access = mask & ACC_ALL; | |
239 | ||
f8f55942 | 240 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 241 | mmu_spte_set(sptep, mask); |
ce88decf XG |
242 | } |
243 | ||
ce88decf XG |
244 | static gfn_t get_mmio_spte_gfn(u64 spte) |
245 | { | |
daa07cbc | 246 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac JS |
247 | |
248 | gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len) | |
249 | & shadow_nonpresent_or_rsvd_mask; | |
250 | ||
251 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
252 | } |
253 | ||
254 | static unsigned get_mmio_spte_access(u64 spte) | |
255 | { | |
4af77151 | 256 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
257 | } |
258 | ||
54bf36aa | 259 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 260 | kvm_pfn_t pfn, unsigned int access) |
ce88decf XG |
261 | { |
262 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 263 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
264 | return true; |
265 | } | |
266 | ||
267 | return false; | |
268 | } | |
c7addb90 | 269 | |
54bf36aa | 270 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 271 | { |
cae7ed3c | 272 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 273 | |
cae7ed3c SC |
274 | gen = kvm_vcpu_memslots(vcpu)->generation; |
275 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
276 | return false; | |
089504c0 | 277 | |
cae7ed3c | 278 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
279 | spte_gen = get_mmio_spte_generation(spte); |
280 | ||
281 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
282 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
283 | } |
284 | ||
cd313569 MG |
285 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
286 | struct x86_exception *exception) | |
287 | { | |
ec7771ab | 288 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 289 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
290 | exception->error_code |= PFERR_RSVD_MASK; |
291 | return UNMAPPED_GVA; | |
292 | } | |
293 | ||
cd313569 MG |
294 | return gpa; |
295 | } | |
296 | ||
6aa8b732 AK |
297 | static int is_cpuid_PSE36(void) |
298 | { | |
299 | return 1; | |
300 | } | |
301 | ||
73b1087e AK |
302 | static int is_nx(struct kvm_vcpu *vcpu) |
303 | { | |
f6801dff | 304 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
305 | } |
306 | ||
da928521 AK |
307 | static gfn_t pse36_gfn_delta(u32 gpte) |
308 | { | |
309 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
310 | ||
311 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
312 | } | |
313 | ||
603e0651 | 314 | #ifdef CONFIG_X86_64 |
d555c333 | 315 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 316 | { |
b19ee2ff | 317 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
318 | } |
319 | ||
603e0651 | 320 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 321 | { |
b19ee2ff | 322 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
323 | } |
324 | ||
325 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
326 | { | |
327 | return xchg(sptep, spte); | |
328 | } | |
c2a2ac2b XG |
329 | |
330 | static u64 __get_spte_lockless(u64 *sptep) | |
331 | { | |
6aa7de05 | 332 | return READ_ONCE(*sptep); |
c2a2ac2b | 333 | } |
a9221dd5 | 334 | #else |
603e0651 XG |
335 | union split_spte { |
336 | struct { | |
337 | u32 spte_low; | |
338 | u32 spte_high; | |
339 | }; | |
340 | u64 spte; | |
341 | }; | |
a9221dd5 | 342 | |
c2a2ac2b XG |
343 | static void count_spte_clear(u64 *sptep, u64 spte) |
344 | { | |
57354682 | 345 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
346 | |
347 | if (is_shadow_present_pte(spte)) | |
348 | return; | |
349 | ||
350 | /* Ensure the spte is completely set before we increase the count */ | |
351 | smp_wmb(); | |
352 | sp->clear_spte_count++; | |
353 | } | |
354 | ||
603e0651 XG |
355 | static void __set_spte(u64 *sptep, u64 spte) |
356 | { | |
357 | union split_spte *ssptep, sspte; | |
a9221dd5 | 358 | |
603e0651 XG |
359 | ssptep = (union split_spte *)sptep; |
360 | sspte = (union split_spte)spte; | |
361 | ||
362 | ssptep->spte_high = sspte.spte_high; | |
363 | ||
364 | /* | |
365 | * If we map the spte from nonpresent to present, We should store | |
366 | * the high bits firstly, then set present bit, so cpu can not | |
367 | * fetch this spte while we are setting the spte. | |
368 | */ | |
369 | smp_wmb(); | |
370 | ||
b19ee2ff | 371 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
372 | } |
373 | ||
603e0651 XG |
374 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
375 | { | |
376 | union split_spte *ssptep, sspte; | |
377 | ||
378 | ssptep = (union split_spte *)sptep; | |
379 | sspte = (union split_spte)spte; | |
380 | ||
b19ee2ff | 381 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
382 | |
383 | /* | |
384 | * If we map the spte from present to nonpresent, we should clear | |
385 | * present bit firstly to avoid vcpu fetch the old high bits. | |
386 | */ | |
387 | smp_wmb(); | |
388 | ||
389 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 390 | count_spte_clear(sptep, spte); |
603e0651 XG |
391 | } |
392 | ||
393 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
394 | { | |
395 | union split_spte *ssptep, sspte, orig; | |
396 | ||
397 | ssptep = (union split_spte *)sptep; | |
398 | sspte = (union split_spte)spte; | |
399 | ||
400 | /* xchg acts as a barrier before the setting of the high bits */ | |
401 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
402 | orig.spte_high = ssptep->spte_high; |
403 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 404 | count_spte_clear(sptep, spte); |
603e0651 XG |
405 | |
406 | return orig.spte; | |
407 | } | |
c2a2ac2b XG |
408 | |
409 | /* | |
410 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 411 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
412 | * |
413 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
414 | * coalesces them and we are running out of the MMU lock. Therefore | |
415 | * we need to protect against in-progress updates of the spte. | |
416 | * | |
417 | * Reading the spte while an update is in progress may get the old value | |
418 | * for the high part of the spte. The race is fine for a present->non-present | |
419 | * change (because the high part of the spte is ignored for non-present spte), | |
420 | * but for a present->present change we must reread the spte. | |
421 | * | |
422 | * All such changes are done in two steps (present->non-present and | |
423 | * non-present->present), hence it is enough to count the number of | |
424 | * present->non-present updates: if it changed while reading the spte, | |
425 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
426 | */ |
427 | static u64 __get_spte_lockless(u64 *sptep) | |
428 | { | |
57354682 | 429 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
430 | union split_spte spte, *orig = (union split_spte *)sptep; |
431 | int count; | |
432 | ||
433 | retry: | |
434 | count = sp->clear_spte_count; | |
435 | smp_rmb(); | |
436 | ||
437 | spte.spte_low = orig->spte_low; | |
438 | smp_rmb(); | |
439 | ||
440 | spte.spte_high = orig->spte_high; | |
441 | smp_rmb(); | |
442 | ||
443 | if (unlikely(spte.spte_low != orig->spte_low || | |
444 | count != sp->clear_spte_count)) | |
445 | goto retry; | |
446 | ||
447 | return spte.spte; | |
448 | } | |
603e0651 XG |
449 | #endif |
450 | ||
8672b721 XG |
451 | static bool spte_has_volatile_bits(u64 spte) |
452 | { | |
f160c7b7 JS |
453 | if (!is_shadow_present_pte(spte)) |
454 | return false; | |
455 | ||
c7ba5b48 | 456 | /* |
6a6256f9 | 457 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
458 | * out of mmu-lock, it can ensure dirty bit is not lost, |
459 | * also, it can help us to get a stable is_writable_pte() | |
460 | * to ensure tlb flush is not missed. | |
461 | */ | |
f160c7b7 JS |
462 | if (spte_can_locklessly_be_made_writable(spte) || |
463 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
464 | return true; |
465 | ||
ac8d57e5 | 466 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
467 | if ((spte & shadow_accessed_mask) == 0 || |
468 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
469 | return true; | |
470 | } | |
8672b721 | 471 | |
f160c7b7 | 472 | return false; |
8672b721 XG |
473 | } |
474 | ||
1df9f2dc XG |
475 | /* Rules for using mmu_spte_set: |
476 | * Set the sptep from nonpresent to present. | |
477 | * Note: the sptep being assigned *must* be either not present | |
478 | * or in a state where the hardware will not attempt to update | |
479 | * the spte. | |
480 | */ | |
481 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
482 | { | |
483 | WARN_ON(is_shadow_present_pte(*sptep)); | |
484 | __set_spte(sptep, new_spte); | |
485 | } | |
486 | ||
f39a058d JS |
487 | /* |
488 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
489 | * accessed/dirty status. | |
1df9f2dc | 490 | */ |
f39a058d | 491 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 492 | { |
c7ba5b48 | 493 | u64 old_spte = *sptep; |
4132779b | 494 | |
afd28fe1 | 495 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 496 | |
6e7d0354 XG |
497 | if (!is_shadow_present_pte(old_spte)) { |
498 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 499 | return old_spte; |
6e7d0354 | 500 | } |
4132779b | 501 | |
c7ba5b48 | 502 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 503 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 504 | else |
603e0651 | 505 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 506 | |
83ef6c81 JS |
507 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
508 | ||
f39a058d JS |
509 | return old_spte; |
510 | } | |
511 | ||
512 | /* Rules for using mmu_spte_update: | |
513 | * Update the state bits, it means the mapped pfn is not changed. | |
514 | * | |
515 | * Whenever we overwrite a writable spte with a read-only one we | |
516 | * should flush remote TLBs. Otherwise rmap_write_protect | |
517 | * will find a read-only spte, even though the writable spte | |
518 | * might be cached on a CPU's TLB, the return value indicates this | |
519 | * case. | |
520 | * | |
521 | * Returns true if the TLB needs to be flushed | |
522 | */ | |
523 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
524 | { | |
525 | bool flush = false; | |
526 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
527 | ||
528 | if (!is_shadow_present_pte(old_spte)) | |
529 | return false; | |
530 | ||
c7ba5b48 XG |
531 | /* |
532 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 533 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
534 | * spte_has_volatile_bits(). |
535 | */ | |
ea4114bc | 536 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 537 | !is_writable_pte(new_spte)) |
83ef6c81 | 538 | flush = true; |
4132779b | 539 | |
7e71a59b | 540 | /* |
83ef6c81 | 541 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
542 | * to guarantee consistency between TLB and page tables. |
543 | */ | |
7e71a59b | 544 | |
83ef6c81 JS |
545 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
546 | flush = true; | |
4132779b | 547 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
548 | } |
549 | ||
550 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
551 | flush = true; | |
4132779b | 552 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 553 | } |
6e7d0354 | 554 | |
83ef6c81 | 555 | return flush; |
b79b93f9 AK |
556 | } |
557 | ||
1df9f2dc XG |
558 | /* |
559 | * Rules for using mmu_spte_clear_track_bits: | |
560 | * It sets the sptep from present to nonpresent, and track the | |
561 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 562 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
563 | */ |
564 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
565 | { | |
ba049e93 | 566 | kvm_pfn_t pfn; |
1df9f2dc XG |
567 | u64 old_spte = *sptep; |
568 | ||
569 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 570 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 571 | else |
603e0651 | 572 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 573 | |
afd28fe1 | 574 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
575 | return 0; |
576 | ||
577 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
578 | |
579 | /* | |
580 | * KVM does not hold the refcount of the page used by | |
581 | * kvm mmu, before reclaiming the page, we should | |
582 | * unmap it from mmu first. | |
583 | */ | |
bf4bea8e | 584 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 585 | |
83ef6c81 | 586 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 587 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
588 | |
589 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 590 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 591 | |
1df9f2dc XG |
592 | return 1; |
593 | } | |
594 | ||
595 | /* | |
596 | * Rules for using mmu_spte_clear_no_track: | |
597 | * Directly clear spte without caring the state bits of sptep, | |
598 | * it is used to set the upper level spte. | |
599 | */ | |
600 | static void mmu_spte_clear_no_track(u64 *sptep) | |
601 | { | |
603e0651 | 602 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
603 | } |
604 | ||
c2a2ac2b XG |
605 | static u64 mmu_spte_get_lockless(u64 *sptep) |
606 | { | |
607 | return __get_spte_lockless(sptep); | |
608 | } | |
609 | ||
d3e328f2 JS |
610 | /* Restore an acc-track PTE back to a regular PTE */ |
611 | static u64 restore_acc_track_spte(u64 spte) | |
612 | { | |
613 | u64 new_spte = spte; | |
614 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
615 | & shadow_acc_track_saved_bits_mask; | |
616 | ||
ac8d57e5 | 617 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
618 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
619 | ||
620 | new_spte &= ~shadow_acc_track_mask; | |
621 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
622 | shadow_acc_track_saved_bits_shift); | |
623 | new_spte |= saved_bits; | |
624 | ||
625 | return new_spte; | |
626 | } | |
627 | ||
f160c7b7 JS |
628 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
629 | static bool mmu_spte_age(u64 *sptep) | |
630 | { | |
631 | u64 spte = mmu_spte_get_lockless(sptep); | |
632 | ||
633 | if (!is_accessed_spte(spte)) | |
634 | return false; | |
635 | ||
ac8d57e5 | 636 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
637 | clear_bit((ffs(shadow_accessed_mask) - 1), |
638 | (unsigned long *)sptep); | |
639 | } else { | |
640 | /* | |
641 | * Capture the dirty status of the page, so that it doesn't get | |
642 | * lost when the SPTE is marked for access tracking. | |
643 | */ | |
644 | if (is_writable_pte(spte)) | |
645 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
646 | ||
647 | spte = mark_spte_for_access_track(spte); | |
648 | mmu_spte_update_no_track(sptep, spte); | |
649 | } | |
650 | ||
651 | return true; | |
652 | } | |
653 | ||
c2a2ac2b XG |
654 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
655 | { | |
c142786c AK |
656 | /* |
657 | * Prevent page table teardown by making any free-er wait during | |
658 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
659 | */ | |
660 | local_irq_disable(); | |
36ca7e0a | 661 | |
c142786c AK |
662 | /* |
663 | * Make sure a following spte read is not reordered ahead of the write | |
664 | * to vcpu->mode. | |
665 | */ | |
36ca7e0a | 666 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
667 | } |
668 | ||
669 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
670 | { | |
c142786c AK |
671 | /* |
672 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 673 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
674 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
675 | */ | |
36ca7e0a | 676 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 677 | local_irq_enable(); |
c2a2ac2b XG |
678 | } |
679 | ||
378f5cd6 | 680 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 681 | { |
e2dec939 AK |
682 | int r; |
683 | ||
531281ad | 684 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
685 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
686 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 687 | if (r) |
284aa868 | 688 | return r; |
94ce87ef SC |
689 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
690 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 691 | if (r) |
171a90d7 | 692 | return r; |
378f5cd6 | 693 | if (maybe_indirect) { |
94ce87ef SC |
694 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
695 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
696 | if (r) |
697 | return r; | |
698 | } | |
94ce87ef SC |
699 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
700 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
701 | } |
702 | ||
703 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
704 | { | |
94ce87ef SC |
705 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
706 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
707 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
708 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
709 | } |
710 | ||
53c07b18 | 711 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 712 | { |
94ce87ef | 713 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
714 | } |
715 | ||
53c07b18 | 716 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 717 | { |
53c07b18 | 718 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
719 | } |
720 | ||
2032a93d LJ |
721 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
722 | { | |
723 | if (!sp->role.direct) | |
724 | return sp->gfns[index]; | |
725 | ||
726 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
727 | } | |
728 | ||
729 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
730 | { | |
e9f2a760 | 731 | if (!sp->role.direct) { |
2032a93d | 732 | sp->gfns[index] = gfn; |
e9f2a760 PB |
733 | return; |
734 | } | |
735 | ||
736 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
737 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
738 | "(expected %llx, got %llx)\n", | |
739 | sp->gfn, | |
740 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
741 | } |
742 | ||
05da4558 | 743 | /* |
d4dbf470 TY |
744 | * Return the pointer to the large page information for a given gfn, |
745 | * handling slots that are not large page aligned. | |
05da4558 | 746 | */ |
d4dbf470 TY |
747 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
748 | struct kvm_memory_slot *slot, | |
749 | int level) | |
05da4558 MT |
750 | { |
751 | unsigned long idx; | |
752 | ||
fb03cb6f | 753 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 754 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
755 | } |
756 | ||
547ffaed XG |
757 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
758 | gfn_t gfn, int count) | |
759 | { | |
760 | struct kvm_lpage_info *linfo; | |
761 | int i; | |
762 | ||
3bae0459 | 763 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
764 | linfo = lpage_info_slot(gfn, slot, i); |
765 | linfo->disallow_lpage += count; | |
766 | WARN_ON(linfo->disallow_lpage < 0); | |
767 | } | |
768 | } | |
769 | ||
770 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
771 | { | |
772 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
773 | } | |
774 | ||
775 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
776 | { | |
777 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
778 | } | |
779 | ||
3ed1a478 | 780 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 781 | { |
699023e2 | 782 | struct kvm_memslots *slots; |
d25797b2 | 783 | struct kvm_memory_slot *slot; |
3ed1a478 | 784 | gfn_t gfn; |
05da4558 | 785 | |
56ca57f9 | 786 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 787 | gfn = sp->gfn; |
699023e2 PB |
788 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
789 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
790 | |
791 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 792 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
793 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
794 | KVM_PAGE_TRACK_WRITE); | |
795 | ||
547ffaed | 796 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
797 | } |
798 | ||
b8e8c830 PB |
799 | static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
800 | { | |
801 | if (sp->lpage_disallowed) | |
802 | return; | |
803 | ||
804 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
805 | list_add_tail(&sp->lpage_disallowed_link, |
806 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
807 | sp->lpage_disallowed = true; |
808 | } | |
809 | ||
3ed1a478 | 810 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 811 | { |
699023e2 | 812 | struct kvm_memslots *slots; |
d25797b2 | 813 | struct kvm_memory_slot *slot; |
3ed1a478 | 814 | gfn_t gfn; |
05da4558 | 815 | |
56ca57f9 | 816 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 817 | gfn = sp->gfn; |
699023e2 PB |
818 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
819 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 820 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
821 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
822 | KVM_PAGE_TRACK_WRITE); | |
823 | ||
547ffaed | 824 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
825 | } |
826 | ||
b8e8c830 PB |
827 | static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
828 | { | |
829 | --kvm->stat.nx_lpage_splits; | |
830 | sp->lpage_disallowed = false; | |
1aa9b957 | 831 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
832 | } |
833 | ||
5d163b1c XG |
834 | static struct kvm_memory_slot * |
835 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
836 | bool no_dirty_log) | |
05da4558 MT |
837 | { |
838 | struct kvm_memory_slot *slot; | |
5d163b1c | 839 | |
54bf36aa | 840 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
841 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
842 | return NULL; | |
843 | if (no_dirty_log && slot->dirty_bitmap) | |
844 | return NULL; | |
5d163b1c XG |
845 | |
846 | return slot; | |
847 | } | |
848 | ||
290fc38d | 849 | /* |
018aabb5 | 850 | * About rmap_head encoding: |
cd4a4e53 | 851 | * |
018aabb5 TY |
852 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
853 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 854 | * pte_list_desc containing more mappings. |
018aabb5 TY |
855 | */ |
856 | ||
857 | /* | |
858 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 859 | */ |
53c07b18 | 860 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 861 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 862 | { |
53c07b18 | 863 | struct pte_list_desc *desc; |
53a27b39 | 864 | int i, count = 0; |
cd4a4e53 | 865 | |
018aabb5 | 866 | if (!rmap_head->val) { |
53c07b18 | 867 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
868 | rmap_head->val = (unsigned long)spte; |
869 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
870 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
871 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 872 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 873 | desc->sptes[1] = spte; |
018aabb5 | 874 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 875 | ++count; |
cd4a4e53 | 876 | } else { |
53c07b18 | 877 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 878 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 879 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 880 | desc = desc->more; |
53c07b18 | 881 | count += PTE_LIST_EXT; |
53a27b39 | 882 | } |
53c07b18 XG |
883 | if (desc->sptes[PTE_LIST_EXT-1]) { |
884 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
885 | desc = desc->more; |
886 | } | |
d555c333 | 887 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 888 | ++count; |
d555c333 | 889 | desc->sptes[i] = spte; |
cd4a4e53 | 890 | } |
53a27b39 | 891 | return count; |
cd4a4e53 AK |
892 | } |
893 | ||
53c07b18 | 894 | static void |
018aabb5 TY |
895 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
896 | struct pte_list_desc *desc, int i, | |
897 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
898 | { |
899 | int j; | |
900 | ||
53c07b18 | 901 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 902 | ; |
d555c333 AK |
903 | desc->sptes[i] = desc->sptes[j]; |
904 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
905 | if (j != 0) |
906 | return; | |
907 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 908 | rmap_head->val = 0; |
cd4a4e53 AK |
909 | else |
910 | if (prev_desc) | |
911 | prev_desc->more = desc->more; | |
912 | else | |
018aabb5 | 913 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 914 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
915 | } |
916 | ||
8daf3462 | 917 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 918 | { |
53c07b18 XG |
919 | struct pte_list_desc *desc; |
920 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
921 | int i; |
922 | ||
018aabb5 | 923 | if (!rmap_head->val) { |
8daf3462 | 924 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 925 | BUG(); |
018aabb5 | 926 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 927 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 928 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 929 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
930 | BUG(); |
931 | } | |
018aabb5 | 932 | rmap_head->val = 0; |
cd4a4e53 | 933 | } else { |
8daf3462 | 934 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 935 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
936 | prev_desc = NULL; |
937 | while (desc) { | |
018aabb5 | 938 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 939 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
940 | pte_list_desc_remove_entry(rmap_head, |
941 | desc, i, prev_desc); | |
cd4a4e53 AK |
942 | return; |
943 | } | |
018aabb5 | 944 | } |
cd4a4e53 AK |
945 | prev_desc = desc; |
946 | desc = desc->more; | |
947 | } | |
8daf3462 | 948 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
949 | BUG(); |
950 | } | |
951 | } | |
952 | ||
e7912386 WY |
953 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
954 | { | |
955 | mmu_spte_clear_track_bits(sptep); | |
956 | __pte_list_remove(sptep, rmap_head); | |
957 | } | |
958 | ||
018aabb5 TY |
959 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
960 | struct kvm_memory_slot *slot) | |
53c07b18 | 961 | { |
77d11309 | 962 | unsigned long idx; |
53c07b18 | 963 | |
77d11309 | 964 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 965 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
966 | } |
967 | ||
018aabb5 TY |
968 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
969 | struct kvm_mmu_page *sp) | |
9b9b1492 | 970 | { |
699023e2 | 971 | struct kvm_memslots *slots; |
9b9b1492 TY |
972 | struct kvm_memory_slot *slot; |
973 | ||
699023e2 PB |
974 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
975 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 976 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
977 | } |
978 | ||
f759e2b4 XG |
979 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
980 | { | |
356ec69a | 981 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 982 | |
356ec69a | 983 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 984 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
985 | } |
986 | ||
53c07b18 XG |
987 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
988 | { | |
989 | struct kvm_mmu_page *sp; | |
018aabb5 | 990 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 991 | |
57354682 | 992 | sp = sptep_to_sp(spte); |
53c07b18 | 993 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
994 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
995 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
996 | } |
997 | ||
53c07b18 XG |
998 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
999 | { | |
1000 | struct kvm_mmu_page *sp; | |
1001 | gfn_t gfn; | |
018aabb5 | 1002 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1003 | |
57354682 | 1004 | sp = sptep_to_sp(spte); |
53c07b18 | 1005 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 1006 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1007 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1008 | } |
1009 | ||
1e3f42f0 TY |
1010 | /* |
1011 | * Used by the following functions to iterate through the sptes linked by a | |
1012 | * rmap. All fields are private and not assumed to be used outside. | |
1013 | */ | |
1014 | struct rmap_iterator { | |
1015 | /* private fields */ | |
1016 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1017 | int pos; /* index of the sptep */ | |
1018 | }; | |
1019 | ||
1020 | /* | |
1021 | * Iteration must be started by this function. This should also be used after | |
1022 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1023 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1024 | * |
1025 | * Returns sptep if found, NULL otherwise. | |
1026 | */ | |
018aabb5 TY |
1027 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1028 | struct rmap_iterator *iter) | |
1e3f42f0 | 1029 | { |
77fbbbd2 TY |
1030 | u64 *sptep; |
1031 | ||
018aabb5 | 1032 | if (!rmap_head->val) |
1e3f42f0 TY |
1033 | return NULL; |
1034 | ||
018aabb5 | 1035 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1036 | iter->desc = NULL; |
77fbbbd2 TY |
1037 | sptep = (u64 *)rmap_head->val; |
1038 | goto out; | |
1e3f42f0 TY |
1039 | } |
1040 | ||
018aabb5 | 1041 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1042 | iter->pos = 0; |
77fbbbd2 TY |
1043 | sptep = iter->desc->sptes[iter->pos]; |
1044 | out: | |
1045 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1046 | return sptep; | |
1e3f42f0 TY |
1047 | } |
1048 | ||
1049 | /* | |
1050 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1051 | * | |
1052 | * Returns sptep if found, NULL otherwise. | |
1053 | */ | |
1054 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1055 | { | |
77fbbbd2 TY |
1056 | u64 *sptep; |
1057 | ||
1e3f42f0 TY |
1058 | if (iter->desc) { |
1059 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1060 | ++iter->pos; |
1061 | sptep = iter->desc->sptes[iter->pos]; | |
1062 | if (sptep) | |
77fbbbd2 | 1063 | goto out; |
1e3f42f0 TY |
1064 | } |
1065 | ||
1066 | iter->desc = iter->desc->more; | |
1067 | ||
1068 | if (iter->desc) { | |
1069 | iter->pos = 0; | |
1070 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1071 | sptep = iter->desc->sptes[iter->pos]; |
1072 | goto out; | |
1e3f42f0 TY |
1073 | } |
1074 | } | |
1075 | ||
1076 | return NULL; | |
77fbbbd2 TY |
1077 | out: |
1078 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1079 | return sptep; | |
1e3f42f0 TY |
1080 | } |
1081 | ||
018aabb5 TY |
1082 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1083 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1084 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1085 | |
c3707958 | 1086 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1087 | { |
1df9f2dc | 1088 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1089 | rmap_remove(kvm, sptep); |
be38d276 AK |
1090 | } |
1091 | ||
8e22f955 XG |
1092 | |
1093 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1094 | { | |
1095 | if (is_large_pte(*sptep)) { | |
57354682 | 1096 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1097 | drop_spte(kvm, sptep); |
1098 | --kvm->stat.lpages; | |
1099 | return true; | |
1100 | } | |
1101 | ||
1102 | return false; | |
1103 | } | |
1104 | ||
1105 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1106 | { | |
c3134ce2 | 1107 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1108 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1109 | |
1110 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1111 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1112 | } | |
8e22f955 XG |
1113 | } |
1114 | ||
1115 | /* | |
49fde340 | 1116 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1117 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1118 | * |
b4619660 | 1119 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1120 | * protection: |
1121 | * - for dirty logging, the spte can be set to writable at anytime if | |
1122 | * its dirty bitmap is properly set. | |
1123 | * - for spte protection, the spte can be writable only after unsync-ing | |
1124 | * shadow page. | |
8e22f955 | 1125 | * |
c126d94f | 1126 | * Return true if tlb need be flushed. |
8e22f955 | 1127 | */ |
c4f138b4 | 1128 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1129 | { |
1130 | u64 spte = *sptep; | |
1131 | ||
49fde340 | 1132 | if (!is_writable_pte(spte) && |
ea4114bc | 1133 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1134 | return false; |
1135 | ||
1136 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1137 | ||
49fde340 XG |
1138 | if (pt_protect) |
1139 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1140 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1141 | |
c126d94f | 1142 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1143 | } |
1144 | ||
018aabb5 TY |
1145 | static bool __rmap_write_protect(struct kvm *kvm, |
1146 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1147 | bool pt_protect) |
98348e95 | 1148 | { |
1e3f42f0 TY |
1149 | u64 *sptep; |
1150 | struct rmap_iterator iter; | |
d13bc5b5 | 1151 | bool flush = false; |
374cbac0 | 1152 | |
018aabb5 | 1153 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1154 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1155 | |
d13bc5b5 | 1156 | return flush; |
a0ed4607 TY |
1157 | } |
1158 | ||
c4f138b4 | 1159 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1160 | { |
1161 | u64 spte = *sptep; | |
1162 | ||
1163 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1164 | ||
1f4e5fc8 | 1165 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1166 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1167 | return mmu_spte_update(sptep, spte); |
1168 | } | |
1169 | ||
1f4e5fc8 | 1170 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1171 | { |
1172 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1173 | (unsigned long *)sptep); | |
1f4e5fc8 | 1174 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1175 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1176 | ||
1177 | return was_writable; | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1182 | * - D bit on ad-enabled SPTEs, and | |
1183 | * - W bit on ad-disabled SPTEs. | |
1184 | * Returns true iff any D or W bits were cleared. | |
1185 | */ | |
018aabb5 | 1186 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1187 | { |
1188 | u64 *sptep; | |
1189 | struct rmap_iterator iter; | |
1190 | bool flush = false; | |
1191 | ||
018aabb5 | 1192 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1193 | if (spte_ad_need_write_protect(*sptep)) |
1194 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1195 | else |
1f4e5fc8 | 1196 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1197 | |
1198 | return flush; | |
1199 | } | |
1200 | ||
c4f138b4 | 1201 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1202 | { |
1203 | u64 spte = *sptep; | |
1204 | ||
1205 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1206 | ||
1f4e5fc8 | 1207 | /* |
afaf0b2f | 1208 | * Similar to the !kvm_x86_ops.slot_disable_log_dirty case, |
1f4e5fc8 PB |
1209 | * do not bother adding back write access to pages marked |
1210 | * SPTE_AD_WRPROT_ONLY_MASK. | |
1211 | */ | |
f4b4b180 KH |
1212 | spte |= shadow_dirty_mask; |
1213 | ||
1214 | return mmu_spte_update(sptep, spte); | |
1215 | } | |
1216 | ||
018aabb5 | 1217 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1218 | { |
1219 | u64 *sptep; | |
1220 | struct rmap_iterator iter; | |
1221 | bool flush = false; | |
1222 | ||
018aabb5 | 1223 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1224 | if (spte_ad_enabled(*sptep)) |
1225 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1226 | |
1227 | return flush; | |
1228 | } | |
1229 | ||
5dc99b23 | 1230 | /** |
3b0f1d01 | 1231 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1232 | * @kvm: kvm instance |
1233 | * @slot: slot to protect | |
1234 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1235 | * @mask: indicates which pages we should protect | |
1236 | * | |
1237 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1238 | * logging we do not have any such mappings. | |
1239 | */ | |
3b0f1d01 | 1240 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1241 | struct kvm_memory_slot *slot, |
1242 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1243 | { |
018aabb5 | 1244 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1245 | |
5dc99b23 | 1246 | while (mask) { |
018aabb5 | 1247 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1248 | PG_LEVEL_4K, slot); |
018aabb5 | 1249 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1250 | |
5dc99b23 TY |
1251 | /* clear the first set bit */ |
1252 | mask &= mask - 1; | |
1253 | } | |
374cbac0 AK |
1254 | } |
1255 | ||
f4b4b180 | 1256 | /** |
ac8d57e5 PF |
1257 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1258 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1259 | * @kvm: kvm instance |
1260 | * @slot: slot to clear D-bit | |
1261 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1262 | * @mask: indicates which pages we should clear D-bit | |
1263 | * | |
1264 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1265 | */ | |
1266 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1267 | struct kvm_memory_slot *slot, | |
1268 | gfn_t gfn_offset, unsigned long mask) | |
1269 | { | |
018aabb5 | 1270 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1271 | |
1272 | while (mask) { | |
018aabb5 | 1273 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1274 | PG_LEVEL_4K, slot); |
018aabb5 | 1275 | __rmap_clear_dirty(kvm, rmap_head); |
f4b4b180 KH |
1276 | |
1277 | /* clear the first set bit */ | |
1278 | mask &= mask - 1; | |
1279 | } | |
1280 | } | |
1281 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1282 | ||
3b0f1d01 KH |
1283 | /** |
1284 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1285 | * PT level pages. | |
1286 | * | |
1287 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1288 | * enable dirty logging for them. | |
1289 | * | |
1290 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1291 | * logging we do not have any such mappings. | |
1292 | */ | |
1293 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1294 | struct kvm_memory_slot *slot, | |
1295 | gfn_t gfn_offset, unsigned long mask) | |
1296 | { | |
afaf0b2f SC |
1297 | if (kvm_x86_ops.enable_log_dirty_pt_masked) |
1298 | kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
88178fd4 KH |
1299 | mask); |
1300 | else | |
1301 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1302 | } |
1303 | ||
aeecee2e XG |
1304 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1305 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1306 | { |
018aabb5 | 1307 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1308 | int i; |
2f84569f | 1309 | bool write_protected = false; |
95d4c16c | 1310 | |
3bae0459 | 1311 | for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1312 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1313 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1314 | } |
1315 | ||
1316 | return write_protected; | |
95d4c16c TY |
1317 | } |
1318 | ||
aeecee2e XG |
1319 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1320 | { | |
1321 | struct kvm_memory_slot *slot; | |
1322 | ||
1323 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1324 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1325 | } | |
1326 | ||
018aabb5 | 1327 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1328 | { |
1e3f42f0 TY |
1329 | u64 *sptep; |
1330 | struct rmap_iterator iter; | |
6a49f85c | 1331 | bool flush = false; |
e930bffe | 1332 | |
018aabb5 | 1333 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1334 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1335 | |
e7912386 | 1336 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1337 | flush = true; |
e930bffe | 1338 | } |
1e3f42f0 | 1339 | |
6a49f85c XG |
1340 | return flush; |
1341 | } | |
1342 | ||
018aabb5 | 1343 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1344 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1345 | unsigned long data) | |
1346 | { | |
018aabb5 | 1347 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1348 | } |
1349 | ||
018aabb5 | 1350 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1351 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1352 | unsigned long data) | |
3da0dd43 | 1353 | { |
1e3f42f0 TY |
1354 | u64 *sptep; |
1355 | struct rmap_iterator iter; | |
3da0dd43 | 1356 | int need_flush = 0; |
1e3f42f0 | 1357 | u64 new_spte; |
3da0dd43 | 1358 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1359 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1360 | |
1361 | WARN_ON(pte_huge(*ptep)); | |
1362 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1363 | |
0d536790 | 1364 | restart: |
018aabb5 | 1365 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1366 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1367 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1368 | |
3da0dd43 | 1369 | need_flush = 1; |
1e3f42f0 | 1370 | |
3da0dd43 | 1371 | if (pte_write(*ptep)) { |
e7912386 | 1372 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1373 | goto restart; |
3da0dd43 | 1374 | } else { |
cb3eedab PB |
1375 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1376 | *sptep, new_pfn); | |
1e3f42f0 TY |
1377 | |
1378 | mmu_spte_clear_track_bits(sptep); | |
1379 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1380 | } |
1381 | } | |
1e3f42f0 | 1382 | |
3cc5ea94 LT |
1383 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1384 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1385 | return 0; | |
1386 | } | |
1387 | ||
0cf853c5 | 1388 | return need_flush; |
3da0dd43 IE |
1389 | } |
1390 | ||
6ce1f4e2 XG |
1391 | struct slot_rmap_walk_iterator { |
1392 | /* input fields. */ | |
1393 | struct kvm_memory_slot *slot; | |
1394 | gfn_t start_gfn; | |
1395 | gfn_t end_gfn; | |
1396 | int start_level; | |
1397 | int end_level; | |
1398 | ||
1399 | /* output fields. */ | |
1400 | gfn_t gfn; | |
018aabb5 | 1401 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1402 | int level; |
1403 | ||
1404 | /* private field. */ | |
018aabb5 | 1405 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1406 | }; |
1407 | ||
1408 | static void | |
1409 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1410 | { | |
1411 | iterator->level = level; | |
1412 | iterator->gfn = iterator->start_gfn; | |
1413 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1414 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1415 | iterator->slot); | |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1420 | struct kvm_memory_slot *slot, int start_level, | |
1421 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1422 | { | |
1423 | iterator->slot = slot; | |
1424 | iterator->start_level = start_level; | |
1425 | iterator->end_level = end_level; | |
1426 | iterator->start_gfn = start_gfn; | |
1427 | iterator->end_gfn = end_gfn; | |
1428 | ||
1429 | rmap_walk_init_level(iterator, iterator->start_level); | |
1430 | } | |
1431 | ||
1432 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1433 | { | |
1434 | return !!iterator->rmap; | |
1435 | } | |
1436 | ||
1437 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1438 | { | |
1439 | if (++iterator->rmap <= iterator->end_rmap) { | |
1440 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1441 | return; | |
1442 | } | |
1443 | ||
1444 | if (++iterator->level > iterator->end_level) { | |
1445 | iterator->rmap = NULL; | |
1446 | return; | |
1447 | } | |
1448 | ||
1449 | rmap_walk_init_level(iterator, iterator->level); | |
1450 | } | |
1451 | ||
1452 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1453 | _start_gfn, _end_gfn, _iter_) \ | |
1454 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1455 | _end_level_, _start_gfn, _end_gfn); \ | |
1456 | slot_rmap_walk_okay(_iter_); \ | |
1457 | slot_rmap_walk_next(_iter_)) | |
1458 | ||
84504ef3 TY |
1459 | static int kvm_handle_hva_range(struct kvm *kvm, |
1460 | unsigned long start, | |
1461 | unsigned long end, | |
1462 | unsigned long data, | |
1463 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1464 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1465 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1466 | gfn_t gfn, |
1467 | int level, | |
84504ef3 | 1468 | unsigned long data)) |
e930bffe | 1469 | { |
bc6678a3 | 1470 | struct kvm_memslots *slots; |
be6ba0f0 | 1471 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1472 | struct slot_rmap_walk_iterator iterator; |
1473 | int ret = 0; | |
9da0e4d5 | 1474 | int i; |
bc6678a3 | 1475 | |
9da0e4d5 PB |
1476 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1477 | slots = __kvm_memslots(kvm, i); | |
1478 | kvm_for_each_memslot(memslot, slots) { | |
1479 | unsigned long hva_start, hva_end; | |
1480 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1481 | |
9da0e4d5 PB |
1482 | hva_start = max(start, memslot->userspace_addr); |
1483 | hva_end = min(end, memslot->userspace_addr + | |
1484 | (memslot->npages << PAGE_SHIFT)); | |
1485 | if (hva_start >= hva_end) | |
1486 | continue; | |
1487 | /* | |
1488 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1489 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1490 | */ | |
1491 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1492 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1493 | ||
3bae0459 | 1494 | for_each_slot_rmap_range(memslot, PG_LEVEL_4K, |
e662ec3e | 1495 | KVM_MAX_HUGEPAGE_LEVEL, |
9da0e4d5 PB |
1496 | gfn_start, gfn_end - 1, |
1497 | &iterator) | |
1498 | ret |= handler(kvm, iterator.rmap, memslot, | |
1499 | iterator.gfn, iterator.level, data); | |
1500 | } | |
e930bffe AA |
1501 | } |
1502 | ||
f395302e | 1503 | return ret; |
e930bffe AA |
1504 | } |
1505 | ||
84504ef3 TY |
1506 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1507 | unsigned long data, | |
018aabb5 TY |
1508 | int (*handler)(struct kvm *kvm, |
1509 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1510 | struct kvm_memory_slot *slot, |
8a9522d2 | 1511 | gfn_t gfn, int level, |
84504ef3 TY |
1512 | unsigned long data)) |
1513 | { | |
1514 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1515 | } |
1516 | ||
fdfe7cbd WD |
1517 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end, |
1518 | unsigned flags) | |
b3ae2096 TY |
1519 | { |
1520 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1521 | } | |
1522 | ||
748c0e31 | 1523 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1524 | { |
0cf853c5 | 1525 | return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1526 | } |
1527 | ||
018aabb5 | 1528 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1529 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1530 | unsigned long data) | |
e930bffe | 1531 | { |
1e3f42f0 | 1532 | u64 *sptep; |
3f649ab7 | 1533 | struct rmap_iterator iter; |
e930bffe AA |
1534 | int young = 0; |
1535 | ||
f160c7b7 JS |
1536 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1537 | young |= mmu_spte_age(sptep); | |
0d536790 | 1538 | |
8a9522d2 | 1539 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1540 | return young; |
1541 | } | |
1542 | ||
018aabb5 | 1543 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1544 | struct kvm_memory_slot *slot, gfn_t gfn, |
1545 | int level, unsigned long data) | |
8ee53820 | 1546 | { |
1e3f42f0 TY |
1547 | u64 *sptep; |
1548 | struct rmap_iterator iter; | |
8ee53820 | 1549 | |
83ef6c81 JS |
1550 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1551 | if (is_accessed_spte(*sptep)) | |
1552 | return 1; | |
83ef6c81 | 1553 | return 0; |
8ee53820 AA |
1554 | } |
1555 | ||
53a27b39 MT |
1556 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1557 | ||
852e3c19 | 1558 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1559 | { |
018aabb5 | 1560 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1561 | struct kvm_mmu_page *sp; |
1562 | ||
57354682 | 1563 | sp = sptep_to_sp(spte); |
53a27b39 | 1564 | |
018aabb5 | 1565 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1566 | |
018aabb5 | 1567 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
1568 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1569 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1570 | } |
1571 | ||
57128468 | 1572 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1573 | { |
57128468 | 1574 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1575 | } |
1576 | ||
8ee53820 AA |
1577 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1578 | { | |
1579 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1580 | } | |
1581 | ||
d6c69ee9 | 1582 | #ifdef MMU_DEBUG |
47ad8e68 | 1583 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1584 | { |
139bdb2d AK |
1585 | u64 *pos; |
1586 | u64 *end; | |
1587 | ||
47ad8e68 | 1588 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1589 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1590 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1591 | pos, *pos); |
6aa8b732 | 1592 | return 0; |
139bdb2d | 1593 | } |
6aa8b732 AK |
1594 | return 1; |
1595 | } | |
d6c69ee9 | 1596 | #endif |
6aa8b732 | 1597 | |
45221ab6 DH |
1598 | /* |
1599 | * This value is the sum of all of the kvm instances's | |
1600 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1601 | * aggregate version in order to make the slab shrinker | |
1602 | * faster | |
1603 | */ | |
bc8a3d89 | 1604 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1605 | { |
1606 | kvm->arch.n_used_mmu_pages += nr; | |
1607 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1608 | } | |
1609 | ||
834be0d8 | 1610 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1611 | { |
fa4a2c08 | 1612 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1613 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1614 | list_del(&sp->link); |
1615 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1616 | if (!sp->role.direct) |
1617 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1618 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1619 | } |
1620 | ||
cea0f0e7 AK |
1621 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1622 | { | |
114df303 | 1623 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1624 | } |
1625 | ||
714b93da | 1626 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1627 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1628 | { |
cea0f0e7 AK |
1629 | if (!parent_pte) |
1630 | return; | |
cea0f0e7 | 1631 | |
67052b35 | 1632 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1633 | } |
1634 | ||
4db35314 | 1635 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1636 | u64 *parent_pte) |
1637 | { | |
8daf3462 | 1638 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1639 | } |
1640 | ||
bcdd9a93 XG |
1641 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1642 | u64 *parent_pte) | |
1643 | { | |
1644 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1645 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1646 | } |
1647 | ||
47005792 | 1648 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1649 | { |
67052b35 | 1650 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1651 | |
94ce87ef SC |
1652 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1653 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1654 | if (!direct) |
94ce87ef | 1655 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1656 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1657 | |
1658 | /* | |
1659 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1660 | * depends on valid pages being added to the head of the list. See | |
1661 | * comments in kvm_zap_obsolete_pages(). | |
1662 | */ | |
ca333add | 1663 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1664 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1665 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1666 | return sp; | |
ad8cfbe3 MT |
1667 | } |
1668 | ||
67052b35 | 1669 | static void mark_unsync(u64 *spte); |
1047df1f | 1670 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1671 | { |
74c4e63a TY |
1672 | u64 *sptep; |
1673 | struct rmap_iterator iter; | |
1674 | ||
1675 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1676 | mark_unsync(sptep); | |
1677 | } | |
0074ff63 MT |
1678 | } |
1679 | ||
67052b35 | 1680 | static void mark_unsync(u64 *spte) |
0074ff63 | 1681 | { |
67052b35 | 1682 | struct kvm_mmu_page *sp; |
1047df1f | 1683 | unsigned int index; |
0074ff63 | 1684 | |
57354682 | 1685 | sp = sptep_to_sp(spte); |
1047df1f XG |
1686 | index = spte - sp->spt; |
1687 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1688 | return; |
1047df1f | 1689 | if (sp->unsync_children++) |
0074ff63 | 1690 | return; |
1047df1f | 1691 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1692 | } |
1693 | ||
e8bc217a | 1694 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1695 | struct kvm_mmu_page *sp) |
e8bc217a | 1696 | { |
1f50f1b3 | 1697 | return 0; |
e8bc217a MT |
1698 | } |
1699 | ||
0f53b5b1 XG |
1700 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1701 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1702 | const void *pte) |
0f53b5b1 XG |
1703 | { |
1704 | WARN_ON(1); | |
1705 | } | |
1706 | ||
60c8aec6 MT |
1707 | #define KVM_PAGE_ARRAY_NR 16 |
1708 | ||
1709 | struct kvm_mmu_pages { | |
1710 | struct mmu_page_and_offset { | |
1711 | struct kvm_mmu_page *sp; | |
1712 | unsigned int idx; | |
1713 | } page[KVM_PAGE_ARRAY_NR]; | |
1714 | unsigned int nr; | |
1715 | }; | |
1716 | ||
cded19f3 HE |
1717 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1718 | int idx) | |
4731d4c7 | 1719 | { |
60c8aec6 | 1720 | int i; |
4731d4c7 | 1721 | |
60c8aec6 MT |
1722 | if (sp->unsync) |
1723 | for (i=0; i < pvec->nr; i++) | |
1724 | if (pvec->page[i].sp == sp) | |
1725 | return 0; | |
1726 | ||
1727 | pvec->page[pvec->nr].sp = sp; | |
1728 | pvec->page[pvec->nr].idx = idx; | |
1729 | pvec->nr++; | |
1730 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1731 | } | |
1732 | ||
fd951457 TY |
1733 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1734 | { | |
1735 | --sp->unsync_children; | |
1736 | WARN_ON((int)sp->unsync_children < 0); | |
1737 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1738 | } | |
1739 | ||
60c8aec6 MT |
1740 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1741 | struct kvm_mmu_pages *pvec) | |
1742 | { | |
1743 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1744 | |
37178b8b | 1745 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1746 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1747 | u64 ent = sp->spt[i]; |
1748 | ||
fd951457 TY |
1749 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1750 | clear_unsync_child_bit(sp, i); | |
1751 | continue; | |
1752 | } | |
7a8f1a74 | 1753 | |
e47c4aee | 1754 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1755 | |
1756 | if (child->unsync_children) { | |
1757 | if (mmu_pages_add(pvec, child, i)) | |
1758 | return -ENOSPC; | |
1759 | ||
1760 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1761 | if (!ret) { |
1762 | clear_unsync_child_bit(sp, i); | |
1763 | continue; | |
1764 | } else if (ret > 0) { | |
7a8f1a74 | 1765 | nr_unsync_leaf += ret; |
fd951457 | 1766 | } else |
7a8f1a74 XG |
1767 | return ret; |
1768 | } else if (child->unsync) { | |
1769 | nr_unsync_leaf++; | |
1770 | if (mmu_pages_add(pvec, child, i)) | |
1771 | return -ENOSPC; | |
1772 | } else | |
fd951457 | 1773 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1774 | } |
1775 | ||
60c8aec6 MT |
1776 | return nr_unsync_leaf; |
1777 | } | |
1778 | ||
e23d3fef XG |
1779 | #define INVALID_INDEX (-1) |
1780 | ||
60c8aec6 MT |
1781 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1782 | struct kvm_mmu_pages *pvec) | |
1783 | { | |
0a47cd85 | 1784 | pvec->nr = 0; |
60c8aec6 MT |
1785 | if (!sp->unsync_children) |
1786 | return 0; | |
1787 | ||
e23d3fef | 1788 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1789 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1790 | } |
1791 | ||
4731d4c7 MT |
1792 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1793 | { | |
1794 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1795 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1796 | sp->unsync = 0; |
1797 | --kvm->stat.mmu_unsync; | |
1798 | } | |
1799 | ||
83cdb568 SC |
1800 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1801 | struct list_head *invalid_list); | |
7775834a XG |
1802 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1803 | struct list_head *invalid_list); | |
4731d4c7 | 1804 | |
ac101b7c SC |
1805 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1806 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1807 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1808 | } else |
1044b030 TY |
1809 | |
1810 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1811 | for_each_valid_sp(_kvm, _sp, \ |
1812 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1813 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1814 | |
47c42e6b SC |
1815 | static inline bool is_ept_sp(struct kvm_mmu_page *sp) |
1816 | { | |
1817 | return sp->role.cr0_wp && sp->role.smap_andnot_wp; | |
1818 | } | |
1819 | ||
f918b443 | 1820 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
1821 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1822 | struct list_head *invalid_list) | |
4731d4c7 | 1823 | { |
47c42e6b SC |
1824 | if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) || |
1825 | vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { | |
d98ba053 | 1826 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1827 | return false; |
4731d4c7 MT |
1828 | } |
1829 | ||
1f50f1b3 | 1830 | return true; |
4731d4c7 MT |
1831 | } |
1832 | ||
a2113634 SC |
1833 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1834 | struct list_head *invalid_list, | |
1835 | bool remote_flush) | |
1836 | { | |
cfd32acf | 1837 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1838 | return false; |
1839 | ||
1840 | if (!list_empty(invalid_list)) | |
1841 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1842 | else | |
1843 | kvm_flush_remote_tlbs(kvm); | |
1844 | return true; | |
1845 | } | |
1846 | ||
35a70510 PB |
1847 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1848 | struct list_head *invalid_list, | |
1849 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1850 | { |
a2113634 | 1851 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1852 | return; |
d98ba053 | 1853 | |
a2113634 | 1854 | if (local_flush) |
8c8560b8 | 1855 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1856 | } |
1857 | ||
e37fa785 XG |
1858 | #ifdef CONFIG_KVM_MMU_AUDIT |
1859 | #include "mmu_audit.c" | |
1860 | #else | |
1861 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1862 | static void mmu_audit_disable(void) { } | |
1863 | #endif | |
1864 | ||
002c5f73 SC |
1865 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1866 | { | |
fac026da SC |
1867 | return sp->role.invalid || |
1868 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1869 | } |
1870 | ||
1f50f1b3 | 1871 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1872 | struct list_head *invalid_list) |
1d9dc7e0 | 1873 | { |
9a43c5d9 PB |
1874 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1875 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
1876 | } |
1877 | ||
9f1a122f | 1878 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
1879 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
1880 | struct list_head *invalid_list) | |
9f1a122f | 1881 | { |
9f1a122f | 1882 | struct kvm_mmu_page *s; |
2a74003a | 1883 | bool ret = false; |
9f1a122f | 1884 | |
b67bfe0d | 1885 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1886 | if (!s->unsync) |
9f1a122f XG |
1887 | continue; |
1888 | ||
3bae0459 | 1889 | WARN_ON(s->role.level != PG_LEVEL_4K); |
2a74003a | 1890 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
1891 | } |
1892 | ||
2a74003a | 1893 | return ret; |
9f1a122f XG |
1894 | } |
1895 | ||
60c8aec6 | 1896 | struct mmu_page_path { |
2a7266a8 YZ |
1897 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1898 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1899 | }; |
1900 | ||
60c8aec6 | 1901 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1902 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1903 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1904 | i = mmu_pages_next(&pvec, &parents, i)) | |
1905 | ||
cded19f3 HE |
1906 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1907 | struct mmu_page_path *parents, | |
1908 | int i) | |
60c8aec6 MT |
1909 | { |
1910 | int n; | |
1911 | ||
1912 | for (n = i+1; n < pvec->nr; n++) { | |
1913 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1914 | unsigned idx = pvec->page[n].idx; |
1915 | int level = sp->role.level; | |
60c8aec6 | 1916 | |
0a47cd85 | 1917 | parents->idx[level-1] = idx; |
3bae0459 | 1918 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1919 | break; |
60c8aec6 | 1920 | |
0a47cd85 | 1921 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1922 | } |
1923 | ||
1924 | return n; | |
1925 | } | |
1926 | ||
0a47cd85 PB |
1927 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1928 | struct mmu_page_path *parents) | |
1929 | { | |
1930 | struct kvm_mmu_page *sp; | |
1931 | int level; | |
1932 | ||
1933 | if (pvec->nr == 0) | |
1934 | return 0; | |
1935 | ||
e23d3fef XG |
1936 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1937 | ||
0a47cd85 PB |
1938 | sp = pvec->page[0].sp; |
1939 | level = sp->role.level; | |
3bae0459 | 1940 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1941 | |
1942 | parents->parent[level-2] = sp; | |
1943 | ||
1944 | /* Also set up a sentinel. Further entries in pvec are all | |
1945 | * children of sp, so this element is never overwritten. | |
1946 | */ | |
1947 | parents->parent[level-1] = NULL; | |
1948 | return mmu_pages_next(pvec, parents, 0); | |
1949 | } | |
1950 | ||
cded19f3 | 1951 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1952 | { |
60c8aec6 MT |
1953 | struct kvm_mmu_page *sp; |
1954 | unsigned int level = 0; | |
1955 | ||
1956 | do { | |
1957 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1958 | sp = parents->parent[level]; |
1959 | if (!sp) | |
1960 | return; | |
1961 | ||
e23d3fef | 1962 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1963 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1964 | level++; |
0a47cd85 | 1965 | } while (!sp->unsync_children); |
60c8aec6 | 1966 | } |
4731d4c7 | 1967 | |
60c8aec6 MT |
1968 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1969 | struct kvm_mmu_page *parent) | |
1970 | { | |
1971 | int i; | |
1972 | struct kvm_mmu_page *sp; | |
1973 | struct mmu_page_path parents; | |
1974 | struct kvm_mmu_pages pages; | |
d98ba053 | 1975 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1976 | bool flush = false; |
60c8aec6 | 1977 | |
60c8aec6 | 1978 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1979 | bool protected = false; |
b1a36821 MT |
1980 | |
1981 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1982 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1983 | |
50c9e6f3 | 1984 | if (protected) { |
b1a36821 | 1985 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
1986 | flush = false; |
1987 | } | |
b1a36821 | 1988 | |
60c8aec6 | 1989 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 1990 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1991 | mmu_pages_clear_parents(&parents); |
1992 | } | |
50c9e6f3 PB |
1993 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
1994 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
1995 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
1996 | flush = false; | |
1997 | } | |
60c8aec6 | 1998 | } |
50c9e6f3 PB |
1999 | |
2000 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2001 | } |
2002 | ||
a30f47cb XG |
2003 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2004 | { | |
e5691a81 | 2005 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2006 | } |
2007 | ||
2008 | static void clear_sp_write_flooding_count(u64 *spte) | |
2009 | { | |
57354682 | 2010 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
2011 | } |
2012 | ||
cea0f0e7 AK |
2013 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2014 | gfn_t gfn, | |
2015 | gva_t gaddr, | |
2016 | unsigned level, | |
f6e2c02b | 2017 | int direct, |
0a2b64c5 | 2018 | unsigned int access) |
cea0f0e7 | 2019 | { |
fb58a9c3 | 2020 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2021 | union kvm_mmu_page_role role; |
ac101b7c | 2022 | struct hlist_head *sp_list; |
cea0f0e7 | 2023 | unsigned quadrant; |
9f1a122f | 2024 | struct kvm_mmu_page *sp; |
9f1a122f | 2025 | bool need_sync = false; |
2a74003a | 2026 | bool flush = false; |
f3414bc7 | 2027 | int collisions = 0; |
2a74003a | 2028 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2029 | |
36d9594d | 2030 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2031 | role.level = level; |
f6e2c02b | 2032 | role.direct = direct; |
84b0c8c6 | 2033 | if (role.direct) |
47c42e6b | 2034 | role.gpte_is_8_bytes = true; |
41074d07 | 2035 | role.access = access; |
fb58a9c3 | 2036 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2037 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2038 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2039 | role.quadrant = quadrant; | |
2040 | } | |
ac101b7c SC |
2041 | |
2042 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2043 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2044 | if (sp->gfn != gfn) { |
2045 | collisions++; | |
2046 | continue; | |
2047 | } | |
2048 | ||
7ae680eb XG |
2049 | if (!need_sync && sp->unsync) |
2050 | need_sync = true; | |
4731d4c7 | 2051 | |
7ae680eb XG |
2052 | if (sp->role.word != role.word) |
2053 | continue; | |
4731d4c7 | 2054 | |
fb58a9c3 SC |
2055 | if (direct_mmu) |
2056 | goto trace_get_page; | |
2057 | ||
2a74003a PB |
2058 | if (sp->unsync) { |
2059 | /* The page is good, but __kvm_sync_page might still end | |
2060 | * up zapping it. If so, break in order to rebuild it. | |
2061 | */ | |
2062 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2063 | break; | |
2064 | ||
2065 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2066 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2067 | } |
e02aa901 | 2068 | |
98bba238 | 2069 | if (sp->unsync_children) |
f6f6195b | 2070 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2071 | |
a30f47cb | 2072 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2073 | |
2074 | trace_get_page: | |
7ae680eb | 2075 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2076 | goto out; |
7ae680eb | 2077 | } |
47005792 | 2078 | |
dfc5aa00 | 2079 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2080 | |
2081 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2082 | ||
4db35314 AK |
2083 | sp->gfn = gfn; |
2084 | sp->role = role; | |
ac101b7c | 2085 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2086 | if (!direct) { |
56ca57f9 XG |
2087 | /* |
2088 | * we should do write protection before syncing pages | |
2089 | * otherwise the content of the synced shadow page may | |
2090 | * be inconsistent with guest page table. | |
2091 | */ | |
2092 | account_shadowed(vcpu->kvm, sp); | |
3bae0459 | 2093 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2094 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2095 | |
3bae0459 | 2096 | if (level > PG_LEVEL_4K && need_sync) |
2a74003a | 2097 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2098 | } |
f691fe1d | 2099 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2100 | |
2101 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2102 | out: |
2103 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2104 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2105 | return sp; |
cea0f0e7 AK |
2106 | } |
2107 | ||
7eb77e9f JS |
2108 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2109 | struct kvm_vcpu *vcpu, hpa_t root, | |
2110 | u64 addr) | |
2d11123a AK |
2111 | { |
2112 | iterator->addr = addr; | |
7eb77e9f | 2113 | iterator->shadow_addr = root; |
44dd3ffa | 2114 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2115 | |
2a7266a8 | 2116 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2117 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2118 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2119 | --iterator->level; |
2120 | ||
2d11123a | 2121 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2122 | /* |
2123 | * prev_root is currently only used for 64-bit hosts. So only | |
2124 | * the active root_hpa is valid here. | |
2125 | */ | |
44dd3ffa | 2126 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2127 | |
2d11123a | 2128 | iterator->shadow_addr |
44dd3ffa | 2129 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2130 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2131 | --iterator->level; | |
2132 | if (!iterator->shadow_addr) | |
2133 | iterator->level = 0; | |
2134 | } | |
2135 | } | |
2136 | ||
7eb77e9f JS |
2137 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2138 | struct kvm_vcpu *vcpu, u64 addr) | |
2139 | { | |
44dd3ffa | 2140 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2141 | addr); |
2142 | } | |
2143 | ||
2d11123a AK |
2144 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2145 | { | |
3bae0459 | 2146 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2147 | return false; |
4d88954d | 2148 | |
2d11123a AK |
2149 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2150 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2151 | return true; | |
2152 | } | |
2153 | ||
c2a2ac2b XG |
2154 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2155 | u64 spte) | |
2d11123a | 2156 | { |
c2a2ac2b | 2157 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2158 | iterator->level = 0; |
2159 | return; | |
2160 | } | |
2161 | ||
c2a2ac2b | 2162 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2163 | --iterator->level; |
2164 | } | |
2165 | ||
c2a2ac2b XG |
2166 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2167 | { | |
bb606a9b | 2168 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2169 | } |
2170 | ||
cc4674d0 BG |
2171 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2172 | struct kvm_mmu_page *sp) | |
2173 | { | |
2174 | u64 spte; | |
2175 | ||
2176 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2177 | ||
2178 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2179 | ||
1df9f2dc | 2180 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2181 | |
2182 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2183 | ||
2184 | if (sp->unsync_children || sp->unsync) | |
2185 | mark_unsync(sptep); | |
32ef26a3 AK |
2186 | } |
2187 | ||
a357bd22 AK |
2188 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2189 | unsigned direct_access) | |
2190 | { | |
2191 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2192 | struct kvm_mmu_page *child; | |
2193 | ||
2194 | /* | |
2195 | * For the direct sp, if the guest pte's dirty bit | |
2196 | * changed form clean to dirty, it will corrupt the | |
2197 | * sp's access: allow writable in the read-only sp, | |
2198 | * so we should update the spte at this point to get | |
2199 | * a new sp with the correct access. | |
2200 | */ | |
e47c4aee | 2201 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2202 | if (child->role.access == direct_access) |
2203 | return; | |
2204 | ||
bcdd9a93 | 2205 | drop_parent_pte(child, sptep); |
c3134ce2 | 2206 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2207 | } |
2208 | } | |
2209 | ||
2de4085c BG |
2210 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2211 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2212 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2213 | { |
2214 | u64 pte; | |
2215 | struct kvm_mmu_page *child; | |
2216 | ||
2217 | pte = *spte; | |
2218 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2219 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2220 | drop_spte(kvm, spte); |
505aef8f XG |
2221 | if (is_large_pte(pte)) |
2222 | --kvm->stat.lpages; | |
2223 | } else { | |
e47c4aee | 2224 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2225 | drop_parent_pte(child, spte); |
2de4085c BG |
2226 | |
2227 | /* | |
2228 | * Recursively zap nested TDP SPs, parentless SPs are | |
2229 | * unlikely to be used again in the near future. This | |
2230 | * avoids retaining a large number of stale nested SPs. | |
2231 | */ | |
2232 | if (tdp_enabled && invalid_list && | |
2233 | child->role.guest_mode && !child->parent_ptes.val) | |
2234 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2235 | invalid_list); | |
38e3b2b2 | 2236 | } |
ace569e0 | 2237 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2238 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2239 | } |
2de4085c | 2240 | return 0; |
38e3b2b2 XG |
2241 | } |
2242 | ||
2de4085c BG |
2243 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2244 | struct kvm_mmu_page *sp, | |
2245 | struct list_head *invalid_list) | |
a436036b | 2246 | { |
2de4085c | 2247 | int zapped = 0; |
697fe2e2 | 2248 | unsigned i; |
697fe2e2 | 2249 | |
38e3b2b2 | 2250 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2251 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2252 | ||
2253 | return zapped; | |
a436036b AK |
2254 | } |
2255 | ||
31aa2b44 | 2256 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2257 | { |
1e3f42f0 TY |
2258 | u64 *sptep; |
2259 | struct rmap_iterator iter; | |
a436036b | 2260 | |
018aabb5 | 2261 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2262 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2263 | } |
2264 | ||
60c8aec6 | 2265 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2266 | struct kvm_mmu_page *parent, |
2267 | struct list_head *invalid_list) | |
4731d4c7 | 2268 | { |
60c8aec6 MT |
2269 | int i, zapped = 0; |
2270 | struct mmu_page_path parents; | |
2271 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2272 | |
3bae0459 | 2273 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2274 | return 0; |
60c8aec6 | 2275 | |
60c8aec6 MT |
2276 | while (mmu_unsync_walk(parent, &pages)) { |
2277 | struct kvm_mmu_page *sp; | |
2278 | ||
2279 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2280 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2281 | mmu_pages_clear_parents(&parents); |
77662e00 | 2282 | zapped++; |
60c8aec6 | 2283 | } |
60c8aec6 MT |
2284 | } |
2285 | ||
2286 | return zapped; | |
4731d4c7 MT |
2287 | } |
2288 | ||
83cdb568 SC |
2289 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2290 | struct kvm_mmu_page *sp, | |
2291 | struct list_head *invalid_list, | |
2292 | int *nr_zapped) | |
31aa2b44 | 2293 | { |
83cdb568 | 2294 | bool list_unstable; |
f691fe1d | 2295 | |
7775834a | 2296 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2297 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2298 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2299 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2300 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2301 | |
83cdb568 SC |
2302 | /* Zapping children means active_mmu_pages has become unstable. */ |
2303 | list_unstable = *nr_zapped; | |
2304 | ||
f6e2c02b | 2305 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2306 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2307 | |
4731d4c7 MT |
2308 | if (sp->unsync) |
2309 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2310 | if (!sp->root_count) { |
54a4f023 | 2311 | /* Count self */ |
83cdb568 | 2312 | (*nr_zapped)++; |
f95eec9b SC |
2313 | |
2314 | /* | |
2315 | * Already invalid pages (previously active roots) are not on | |
2316 | * the active page list. See list_del() in the "else" case of | |
2317 | * !sp->root_count. | |
2318 | */ | |
2319 | if (sp->role.invalid) | |
2320 | list_add(&sp->link, invalid_list); | |
2321 | else | |
2322 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2323 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2324 | } else { |
f95eec9b SC |
2325 | /* |
2326 | * Remove the active root from the active page list, the root | |
2327 | * will be explicitly freed when the root_count hits zero. | |
2328 | */ | |
2329 | list_del(&sp->link); | |
05988d72 | 2330 | |
10605204 SC |
2331 | /* |
2332 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2333 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2334 | * treats invalid shadow pages as being obsolete. | |
2335 | */ | |
2336 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2337 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2338 | } |
7775834a | 2339 | |
b8e8c830 PB |
2340 | if (sp->lpage_disallowed) |
2341 | unaccount_huge_nx_page(kvm, sp); | |
2342 | ||
7775834a | 2343 | sp->role.invalid = 1; |
83cdb568 SC |
2344 | return list_unstable; |
2345 | } | |
2346 | ||
2347 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2348 | struct list_head *invalid_list) | |
2349 | { | |
2350 | int nr_zapped; | |
2351 | ||
2352 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2353 | return nr_zapped; | |
a436036b AK |
2354 | } |
2355 | ||
7775834a XG |
2356 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2357 | struct list_head *invalid_list) | |
2358 | { | |
945315b9 | 2359 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2360 | |
2361 | if (list_empty(invalid_list)) | |
2362 | return; | |
2363 | ||
c142786c | 2364 | /* |
9753f529 LT |
2365 | * We need to make sure everyone sees our modifications to |
2366 | * the page tables and see changes to vcpu->mode here. The barrier | |
2367 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2368 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2369 | * | |
2370 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2371 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2372 | */ |
2373 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2374 | |
945315b9 | 2375 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2376 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2377 | kvm_mmu_free_page(sp); |
945315b9 | 2378 | } |
7775834a XG |
2379 | } |
2380 | ||
6b82ef2c SC |
2381 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2382 | unsigned long nr_to_zap) | |
5da59607 | 2383 | { |
6b82ef2c SC |
2384 | unsigned long total_zapped = 0; |
2385 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2386 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2387 | bool unstable; |
2388 | int nr_zapped; | |
5da59607 TY |
2389 | |
2390 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2391 | return 0; |
2392 | ||
6b82ef2c SC |
2393 | restart: |
2394 | list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) { | |
2395 | /* | |
2396 | * Don't zap active root pages, the page itself can't be freed | |
2397 | * and zapping it will just force vCPUs to realloc and reload. | |
2398 | */ | |
2399 | if (sp->root_count) | |
2400 | continue; | |
2401 | ||
2402 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2403 | &nr_zapped); | |
2404 | total_zapped += nr_zapped; | |
2405 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2406 | break; |
2407 | ||
6b82ef2c SC |
2408 | if (unstable) |
2409 | goto restart; | |
ba7888dd | 2410 | } |
5da59607 | 2411 | |
6b82ef2c SC |
2412 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2413 | ||
2414 | kvm->stat.mmu_recycled += total_zapped; | |
2415 | return total_zapped; | |
2416 | } | |
2417 | ||
afe8d7e6 SC |
2418 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2419 | { | |
2420 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2421 | return kvm->arch.n_max_mmu_pages - | |
2422 | kvm->arch.n_used_mmu_pages; | |
2423 | ||
2424 | return 0; | |
5da59607 TY |
2425 | } |
2426 | ||
ba7888dd SC |
2427 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2428 | { | |
6b82ef2c | 2429 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2430 | |
6b82ef2c | 2431 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2432 | return 0; |
2433 | ||
6b82ef2c | 2434 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd SC |
2435 | |
2436 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
2437 | return -ENOSPC; | |
2438 | return 0; | |
2439 | } | |
2440 | ||
82ce2c96 IE |
2441 | /* |
2442 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2443 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2444 | */ |
bc8a3d89 | 2445 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2446 | { |
b34cb590 TY |
2447 | spin_lock(&kvm->mmu_lock); |
2448 | ||
49d5ca26 | 2449 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2450 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2451 | goal_nr_mmu_pages); | |
82ce2c96 | 2452 | |
49d5ca26 | 2453 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2454 | } |
82ce2c96 | 2455 | |
49d5ca26 | 2456 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2457 | |
2458 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2459 | } |
2460 | ||
1cb3f3ae | 2461 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2462 | { |
4db35314 | 2463 | struct kvm_mmu_page *sp; |
d98ba053 | 2464 | LIST_HEAD(invalid_list); |
a436036b AK |
2465 | int r; |
2466 | ||
9ad17b10 | 2467 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2468 | r = 0; |
1cb3f3ae | 2469 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2470 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2471 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2472 | sp->role.word); |
2473 | r = 1; | |
f41d335a | 2474 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2475 | } |
d98ba053 | 2476 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2477 | spin_unlock(&kvm->mmu_lock); |
2478 | ||
a436036b | 2479 | return r; |
cea0f0e7 | 2480 | } |
1cb3f3ae | 2481 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2482 | |
5c520e90 | 2483 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2484 | { |
2485 | trace_kvm_mmu_unsync_page(sp); | |
2486 | ++vcpu->kvm->stat.mmu_unsync; | |
2487 | sp->unsync = 1; | |
2488 | ||
2489 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2490 | } |
2491 | ||
5a9624af PB |
2492 | bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2493 | bool can_unsync) | |
4731d4c7 | 2494 | { |
5c520e90 | 2495 | struct kvm_mmu_page *sp; |
4731d4c7 | 2496 | |
3d0c27ad XG |
2497 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2498 | return true; | |
9cf5cf5a | 2499 | |
5c520e90 | 2500 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2501 | if (!can_unsync) |
3d0c27ad | 2502 | return true; |
36a2e677 | 2503 | |
5c520e90 XG |
2504 | if (sp->unsync) |
2505 | continue; | |
9cf5cf5a | 2506 | |
3bae0459 | 2507 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2508 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2509 | } |
3d0c27ad | 2510 | |
578e1c4d JS |
2511 | /* |
2512 | * We need to ensure that the marking of unsync pages is visible | |
2513 | * before the SPTE is updated to allow writes because | |
2514 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2515 | * the MMU lock and so can race with this. If the SPTE was updated | |
2516 | * before the page had been marked as unsync-ed, something like the | |
2517 | * following could happen: | |
2518 | * | |
2519 | * CPU 1 CPU 2 | |
2520 | * --------------------------------------------------------------------- | |
2521 | * 1.2 Host updates SPTE | |
2522 | * to be writable | |
2523 | * 2.1 Guest writes a GPTE for GVA X. | |
2524 | * (GPTE being in the guest page table shadowed | |
2525 | * by the SP from CPU 1.) | |
2526 | * This reads SPTE during the page table walk. | |
2527 | * Since SPTE.W is read as 1, there is no | |
2528 | * fault. | |
2529 | * | |
2530 | * 2.2 Guest issues TLB flush. | |
2531 | * That causes a VM Exit. | |
2532 | * | |
2533 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2534 | * Since it is false, so it just returns. | |
2535 | * | |
2536 | * 2.4 Guest accesses GVA X. | |
2537 | * Since the mapping in the SP was not updated, | |
2538 | * so the old mapping for GVA X incorrectly | |
2539 | * gets used. | |
2540 | * 1.1 Host marks SP | |
2541 | * as unsync | |
2542 | * (sp->unsync = true) | |
2543 | * | |
2544 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2545 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2546 | * pairs with this write barrier. | |
2547 | */ | |
2548 | smp_wmb(); | |
2549 | ||
3d0c27ad | 2550 | return false; |
4731d4c7 MT |
2551 | } |
2552 | ||
799a4190 BG |
2553 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2554 | unsigned int pte_access, int level, | |
2555 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2556 | bool can_unsync, bool host_writable) | |
2557 | { | |
2558 | u64 spte; | |
2559 | struct kvm_mmu_page *sp; | |
2560 | int ret; | |
2561 | ||
2562 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) | |
2563 | return 0; | |
2564 | ||
2565 | sp = sptep_to_sp(sptep); | |
2566 | ||
2567 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2568 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2569 | ||
2570 | if (spte & PT_WRITABLE_MASK) | |
2571 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2572 | ||
12703759 SC |
2573 | if (*sptep == spte) |
2574 | ret |= SET_SPTE_SPURIOUS; | |
2575 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2576 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2577 | return ret; |
2578 | } | |
2579 | ||
0a2b64c5 | 2580 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2581 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2582 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2583 | bool host_writable) | |
1e73f9dd MT |
2584 | { |
2585 | int was_rmapped = 0; | |
53a27b39 | 2586 | int rmap_count; |
5ce4786f | 2587 | int set_spte_ret; |
c4371c2a | 2588 | int ret = RET_PF_FIXED; |
c2a4eadf | 2589 | bool flush = false; |
1e73f9dd | 2590 | |
f7616203 XG |
2591 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2592 | *sptep, write_fault, gfn); | |
1e73f9dd | 2593 | |
afd28fe1 | 2594 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2595 | /* |
2596 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2597 | * the parent of the now unreachable PTE. | |
2598 | */ | |
3bae0459 | 2599 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2600 | struct kvm_mmu_page *child; |
d555c333 | 2601 | u64 pte = *sptep; |
1e73f9dd | 2602 | |
e47c4aee | 2603 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2604 | drop_parent_pte(child, sptep); |
c2a4eadf | 2605 | flush = true; |
d555c333 | 2606 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2607 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2608 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2609 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2610 | flush = true; |
6bed6b9e JR |
2611 | } else |
2612 | was_rmapped = 1; | |
1e73f9dd | 2613 | } |
852e3c19 | 2614 | |
5ce4786f JS |
2615 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2616 | speculative, true, host_writable); | |
2617 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2618 | if (write_fault) |
9b8ebbdb | 2619 | ret = RET_PF_EMULATE; |
8c8560b8 | 2620 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2621 | } |
c3134ce2 | 2622 | |
c2a4eadf | 2623 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2624 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2625 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2626 | |
029499b4 | 2627 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 2628 | ret = RET_PF_EMULATE; |
ce88decf | 2629 | |
12703759 SC |
2630 | /* |
2631 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2632 | * are identical, and emulation is not required. | |
2633 | */ | |
2634 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2635 | WARN_ON_ONCE(!was_rmapped); | |
2636 | return RET_PF_SPURIOUS; | |
2637 | } | |
2638 | ||
d555c333 | 2639 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2640 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2641 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2642 | ++vcpu->kvm->stat.lpages; |
2643 | ||
ffb61bb3 | 2644 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2645 | if (!was_rmapped) { |
2646 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2647 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2648 | rmap_recycle(vcpu, sptep, gfn); | |
2649 | } | |
1c4f1fd6 | 2650 | } |
cb9aaa30 | 2651 | |
9b8ebbdb | 2652 | return ret; |
1c4f1fd6 AK |
2653 | } |
2654 | ||
ba049e93 | 2655 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2656 | bool no_dirty_log) |
2657 | { | |
2658 | struct kvm_memory_slot *slot; | |
957ed9ef | 2659 | |
5d163b1c | 2660 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2661 | if (!slot) |
6c8ee57b | 2662 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2663 | |
037d92dc | 2664 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2665 | } |
2666 | ||
2667 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2668 | struct kvm_mmu_page *sp, | |
2669 | u64 *start, u64 *end) | |
2670 | { | |
2671 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2672 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2673 | unsigned int access = sp->role.access; |
957ed9ef XG |
2674 | int i, ret; |
2675 | gfn_t gfn; | |
2676 | ||
2677 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2678 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2679 | if (!slot) | |
957ed9ef XG |
2680 | return -1; |
2681 | ||
d9ef13c2 | 2682 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2683 | if (ret <= 0) |
2684 | return -1; | |
2685 | ||
43fdcda9 | 2686 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2687 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2688 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2689 | put_page(pages[i]); |
2690 | } | |
957ed9ef XG |
2691 | |
2692 | return 0; | |
2693 | } | |
2694 | ||
2695 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2696 | struct kvm_mmu_page *sp, u64 *sptep) | |
2697 | { | |
2698 | u64 *spte, *start = NULL; | |
2699 | int i; | |
2700 | ||
2701 | WARN_ON(!sp->role.direct); | |
2702 | ||
2703 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2704 | spte = sp->spt + i; | |
2705 | ||
2706 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2707 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2708 | if (!start) |
2709 | continue; | |
2710 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2711 | break; | |
2712 | start = NULL; | |
2713 | } else if (!start) | |
2714 | start = spte; | |
2715 | } | |
2716 | } | |
2717 | ||
2718 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2719 | { | |
2720 | struct kvm_mmu_page *sp; | |
2721 | ||
57354682 | 2722 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2723 | |
957ed9ef | 2724 | /* |
ac8d57e5 PF |
2725 | * Without accessed bits, there's no way to distinguish between |
2726 | * actually accessed translations and prefetched, so disable pte | |
2727 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2728 | */ |
ac8d57e5 | 2729 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2730 | return; |
2731 | ||
3bae0459 | 2732 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2733 | return; |
2734 | ||
2735 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2736 | } | |
2737 | ||
db543216 | 2738 | static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn, |
293e306e | 2739 | kvm_pfn_t pfn, struct kvm_memory_slot *slot) |
db543216 | 2740 | { |
db543216 SC |
2741 | unsigned long hva; |
2742 | pte_t *pte; | |
2743 | int level; | |
2744 | ||
e851265a | 2745 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2746 | return PG_LEVEL_4K; |
db543216 | 2747 | |
293e306e SC |
2748 | /* |
2749 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2750 | * is not solely for performance, it's also necessary to avoid the | |
2751 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2752 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2753 | * page fault steps have already verified the guest isn't writing a | |
2754 | * read-only memslot. | |
2755 | */ | |
db543216 SC |
2756 | hva = __gfn_to_hva_memslot(slot, gfn); |
2757 | ||
2758 | pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level); | |
2759 | if (unlikely(!pte)) | |
3bae0459 | 2760 | return PG_LEVEL_4K; |
db543216 SC |
2761 | |
2762 | return level; | |
2763 | } | |
2764 | ||
83f06fa7 | 2765 | static int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
3cf06612 SC |
2766 | int max_level, kvm_pfn_t *pfnp, |
2767 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2768 | { |
293e306e | 2769 | struct kvm_memory_slot *slot; |
2c0629f4 | 2770 | struct kvm_lpage_info *linfo; |
0885904d | 2771 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2772 | kvm_pfn_t mask; |
83f06fa7 | 2773 | int level; |
17eff019 | 2774 | |
3cf06612 SC |
2775 | *req_level = PG_LEVEL_4K; |
2776 | ||
3bae0459 SC |
2777 | if (unlikely(max_level == PG_LEVEL_4K)) |
2778 | return PG_LEVEL_4K; | |
17eff019 | 2779 | |
e851265a | 2780 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2781 | return PG_LEVEL_4K; |
17eff019 | 2782 | |
293e306e SC |
2783 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2784 | if (!slot) | |
3bae0459 | 2785 | return PG_LEVEL_4K; |
293e306e | 2786 | |
1d92d2e8 | 2787 | max_level = min(max_level, max_huge_page_level); |
3bae0459 | 2788 | for ( ; max_level > PG_LEVEL_4K; max_level--) { |
2c0629f4 SC |
2789 | linfo = lpage_info_slot(gfn, slot, max_level); |
2790 | if (!linfo->disallow_lpage) | |
293e306e SC |
2791 | break; |
2792 | } | |
2793 | ||
3bae0459 SC |
2794 | if (max_level == PG_LEVEL_4K) |
2795 | return PG_LEVEL_4K; | |
293e306e SC |
2796 | |
2797 | level = host_pfn_mapping_level(vcpu, gfn, pfn, slot); | |
3bae0459 | 2798 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2799 | return level; |
17eff019 | 2800 | |
3cf06612 SC |
2801 | *req_level = level = min(level, max_level); |
2802 | ||
2803 | /* | |
2804 | * Enforce the iTLB multihit workaround after capturing the requested | |
2805 | * level, which will be used to do precise, accurate accounting. | |
2806 | */ | |
2807 | if (huge_page_disallowed) | |
2808 | return PG_LEVEL_4K; | |
0885904d SC |
2809 | |
2810 | /* | |
17eff019 SC |
2811 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2812 | * the pmd can't be split from under us. | |
0885904d | 2813 | */ |
17eff019 SC |
2814 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2815 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2816 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2817 | |
2818 | return level; | |
0885904d SC |
2819 | } |
2820 | ||
b8e8c830 PB |
2821 | static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it, |
2822 | gfn_t gfn, kvm_pfn_t *pfnp, int *levelp) | |
2823 | { | |
2824 | int level = *levelp; | |
2825 | u64 spte = *it.sptep; | |
2826 | ||
3bae0459 | 2827 | if (it.level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2828 | is_shadow_present_pte(spte) && |
2829 | !is_large_pte(spte)) { | |
2830 | /* | |
2831 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2832 | * and __direct_map would like to create a large PTE | |
2833 | * instead: just force them to go down another level, | |
2834 | * patching back for them into pfn the next 9 bits of | |
2835 | * the address. | |
2836 | */ | |
2837 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1); | |
2838 | *pfnp |= gfn & page_mask; | |
2839 | (*levelp)--; | |
2840 | } | |
2841 | } | |
2842 | ||
6c2fd34f | 2843 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2844 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2845 | bool prefault, bool is_tdp) |
140754bc | 2846 | { |
6c2fd34f SC |
2847 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2848 | bool write = error_code & PFERR_WRITE_MASK; | |
2849 | bool exec = error_code & PFERR_FETCH_MASK; | |
2850 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2851 | struct kvm_shadow_walk_iterator it; |
140754bc | 2852 | struct kvm_mmu_page *sp; |
3cf06612 | 2853 | int level, req_level, ret; |
3fcf2d1b PB |
2854 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2855 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2856 | |
0c7a98e3 | 2857 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
3fcf2d1b | 2858 | return RET_PF_RETRY; |
989c6b34 | 2859 | |
3cf06612 SC |
2860 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2861 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2862 | |
335e192a | 2863 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2864 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2865 | /* |
2866 | * We cannot overwrite existing page tables with an NX | |
2867 | * large page, as the leaf could be executable. | |
2868 | */ | |
dcc70651 SC |
2869 | if (nx_huge_page_workaround_enabled) |
2870 | disallowed_hugepage_adjust(it, gfn, &pfn, &level); | |
b8e8c830 | 2871 | |
3fcf2d1b PB |
2872 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2873 | if (it.level == level) | |
9f652d21 | 2874 | break; |
6aa8b732 | 2875 | |
3fcf2d1b PB |
2876 | drop_large_spte(vcpu, it.sptep); |
2877 | if (!is_shadow_present_pte(*it.sptep)) { | |
2878 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2879 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2880 | |
3fcf2d1b | 2881 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2882 | if (is_tdp && huge_page_disallowed && |
2883 | req_level >= it.level) | |
b8e8c830 | 2884 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2885 | } |
2886 | } | |
3fcf2d1b PB |
2887 | |
2888 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2889 | write, level, base_gfn, pfn, prefault, | |
2890 | map_writable); | |
12703759 SC |
2891 | if (ret == RET_PF_SPURIOUS) |
2892 | return ret; | |
2893 | ||
3fcf2d1b PB |
2894 | direct_pte_prefetch(vcpu, it.sptep); |
2895 | ++vcpu->stat.pf_fixed; | |
2896 | return ret; | |
6aa8b732 AK |
2897 | } |
2898 | ||
77db5cbd | 2899 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2900 | { |
585a8b9b | 2901 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2902 | } |
2903 | ||
ba049e93 | 2904 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2905 | { |
4d8b81ab XG |
2906 | /* |
2907 | * Do not cache the mmio info caused by writing the readonly gfn | |
2908 | * into the spte otherwise read access on readonly gfn also can | |
2909 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2910 | */ |
2911 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2912 | return RET_PF_EMULATE; |
4d8b81ab | 2913 | |
e6c1502b | 2914 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2915 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2916 | return RET_PF_RETRY; |
d7c55201 | 2917 | } |
edba23e5 | 2918 | |
2c151b25 | 2919 | return -EFAULT; |
bf998156 HY |
2920 | } |
2921 | ||
d7c55201 | 2922 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2923 | kvm_pfn_t pfn, unsigned int access, |
2924 | int *ret_val) | |
d7c55201 | 2925 | { |
d7c55201 | 2926 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2927 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2928 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2929 | return true; |
d7c55201 XG |
2930 | } |
2931 | ||
ce88decf | 2932 | if (unlikely(is_noslot_pfn(pfn))) |
4af77151 SC |
2933 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2934 | access & shadow_mmio_access_mask); | |
d7c55201 | 2935 | |
798e88b3 | 2936 | return false; |
d7c55201 XG |
2937 | } |
2938 | ||
e5552fd2 | 2939 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2940 | { |
1c118b82 XG |
2941 | /* |
2942 | * Do not fix the mmio spte with invalid generation number which | |
2943 | * need to be updated by slow page fault path. | |
2944 | */ | |
2945 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2946 | return false; | |
2947 | ||
f160c7b7 JS |
2948 | /* See if the page fault is due to an NX violation */ |
2949 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
2950 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
2951 | return false; | |
2952 | ||
c7ba5b48 | 2953 | /* |
f160c7b7 JS |
2954 | * #PF can be fast if: |
2955 | * 1. The shadow page table entry is not present, which could mean that | |
2956 | * the fault is potentially caused by access tracking (if enabled). | |
2957 | * 2. The shadow page table entry is present and the fault | |
2958 | * is caused by write-protect, that means we just need change the W | |
2959 | * bit of the spte which can be done out of mmu-lock. | |
2960 | * | |
2961 | * However, if access tracking is disabled we know that a non-present | |
2962 | * page must be a genuine page fault where we have to create a new SPTE. | |
2963 | * So, if access tracking is disabled, we return true only for write | |
2964 | * accesses to a present page. | |
c7ba5b48 | 2965 | */ |
c7ba5b48 | 2966 | |
f160c7b7 JS |
2967 | return shadow_acc_track_mask != 0 || |
2968 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
2969 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
2970 | } |
2971 | ||
97dceba2 JS |
2972 | /* |
2973 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
2974 | * someone else modified the SPTE from its original value. | |
2975 | */ | |
c7ba5b48 | 2976 | static bool |
92a476cb | 2977 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 2978 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 2979 | { |
c7ba5b48 XG |
2980 | gfn_t gfn; |
2981 | ||
2982 | WARN_ON(!sp->role.direct); | |
2983 | ||
9b51a630 KH |
2984 | /* |
2985 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
2986 | * order to eliminate unnecessary PML logging. See comments in | |
2987 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
2988 | * enabled, so we do not do this. This might result in the same GPA | |
2989 | * to be logged in PML buffer again when the write really happens, and | |
2990 | * eventually to be called by mark_page_dirty twice. But it's also no | |
2991 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
2992 | * so non-PML cases won't be impacted. | |
2993 | * | |
2994 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
2995 | */ | |
f160c7b7 | 2996 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
2997 | return false; |
2998 | ||
d3e328f2 | 2999 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3000 | /* |
3001 | * The gfn of direct spte is stable since it is | |
3002 | * calculated by sp->gfn. | |
3003 | */ | |
3004 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3005 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3006 | } | |
c7ba5b48 XG |
3007 | |
3008 | return true; | |
3009 | } | |
3010 | ||
d3e328f2 JS |
3011 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3012 | { | |
3013 | if (fault_err_code & PFERR_FETCH_MASK) | |
3014 | return is_executable_pte(spte); | |
3015 | ||
3016 | if (fault_err_code & PFERR_WRITE_MASK) | |
3017 | return is_writable_pte(spte); | |
3018 | ||
3019 | /* Fault was on Read access */ | |
3020 | return spte & PT_PRESENT_MASK; | |
3021 | } | |
3022 | ||
c7ba5b48 | 3023 | /* |
c4371c2a | 3024 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3025 | */ |
c4371c2a SC |
3026 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3027 | u32 error_code) | |
c7ba5b48 XG |
3028 | { |
3029 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3030 | struct kvm_mmu_page *sp; |
c4371c2a | 3031 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3032 | u64 spte = 0ull; |
97dceba2 | 3033 | uint retry_count = 0; |
c7ba5b48 | 3034 | |
e5552fd2 | 3035 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3036 | return ret; |
c7ba5b48 XG |
3037 | |
3038 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3039 | |
97dceba2 | 3040 | do { |
d3e328f2 | 3041 | u64 new_spte; |
c7ba5b48 | 3042 | |
736c291c | 3043 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3044 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3045 | break; |
3046 | ||
57354682 | 3047 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3048 | if (!is_last_spte(spte, sp->role.level)) |
3049 | break; | |
c7ba5b48 | 3050 | |
97dceba2 | 3051 | /* |
f160c7b7 JS |
3052 | * Check whether the memory access that caused the fault would |
3053 | * still cause it if it were to be performed right now. If not, | |
3054 | * then this is a spurious fault caused by TLB lazily flushed, | |
3055 | * or some other CPU has already fixed the PTE after the | |
3056 | * current CPU took the fault. | |
97dceba2 JS |
3057 | * |
3058 | * Need not check the access of upper level table entries since | |
3059 | * they are always ACC_ALL. | |
3060 | */ | |
d3e328f2 | 3061 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3062 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3063 | break; |
3064 | } | |
f160c7b7 | 3065 | |
d3e328f2 JS |
3066 | new_spte = spte; |
3067 | ||
3068 | if (is_access_track_spte(spte)) | |
3069 | new_spte = restore_acc_track_spte(new_spte); | |
3070 | ||
3071 | /* | |
3072 | * Currently, to simplify the code, write-protection can | |
3073 | * be removed in the fast path only if the SPTE was | |
3074 | * write-protected for dirty-logging or access tracking. | |
3075 | */ | |
3076 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3077 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3078 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3079 | |
3080 | /* | |
d3e328f2 JS |
3081 | * Do not fix write-permission on the large spte. Since |
3082 | * we only dirty the first page into the dirty-bitmap in | |
3083 | * fast_pf_fix_direct_spte(), other pages are missed | |
3084 | * if its slot has dirty logging enabled. | |
3085 | * | |
3086 | * Instead, we let the slow page fault path create a | |
3087 | * normal spte to fix the access. | |
3088 | * | |
3089 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3090 | */ |
3bae0459 | 3091 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3092 | break; |
97dceba2 | 3093 | } |
c7ba5b48 | 3094 | |
f160c7b7 | 3095 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3096 | if (new_spte == spte || |
3097 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3098 | break; |
3099 | ||
3100 | /* | |
3101 | * Currently, fast page fault only works for direct mapping | |
3102 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3103 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3104 | */ |
c4371c2a SC |
3105 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3106 | new_spte)) { | |
3107 | ret = RET_PF_FIXED; | |
97dceba2 | 3108 | break; |
c4371c2a | 3109 | } |
97dceba2 JS |
3110 | |
3111 | if (++retry_count > 4) { | |
3112 | printk_once(KERN_WARNING | |
3113 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3114 | break; | |
3115 | } | |
3116 | ||
97dceba2 | 3117 | } while (true); |
c126d94f | 3118 | |
736c291c | 3119 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3120 | spte, ret); |
c7ba5b48 XG |
3121 | walk_shadow_page_lockless_end(vcpu); |
3122 | ||
c4371c2a | 3123 | return ret; |
c7ba5b48 XG |
3124 | } |
3125 | ||
74b566e6 JS |
3126 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3127 | struct list_head *invalid_list) | |
17ac10ad | 3128 | { |
4db35314 | 3129 | struct kvm_mmu_page *sp; |
17ac10ad | 3130 | |
74b566e6 | 3131 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3132 | return; |
35af577a | 3133 | |
e47c4aee | 3134 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a BG |
3135 | |
3136 | if (kvm_mmu_put_root(kvm, sp)) { | |
3137 | if (sp->tdp_mmu_page) | |
3138 | kvm_tdp_mmu_free_root(kvm, sp); | |
3139 | else if (sp->role.invalid) | |
3140 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
3141 | } | |
17ac10ad | 3142 | |
74b566e6 JS |
3143 | *root_hpa = INVALID_PAGE; |
3144 | } | |
3145 | ||
08fb59d8 | 3146 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3147 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3148 | ulong roots_to_free) | |
74b566e6 | 3149 | { |
4d710de9 | 3150 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3151 | int i; |
3152 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3153 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3154 | |
b94742c9 | 3155 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3156 | |
08fb59d8 | 3157 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3158 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3159 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3160 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3161 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3162 | break; | |
3163 | ||
3164 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3165 | return; | |
3166 | } | |
35af577a | 3167 | |
4d710de9 | 3168 | spin_lock(&kvm->mmu_lock); |
17ac10ad | 3169 | |
b94742c9 JS |
3170 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3171 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3172 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3173 | &invalid_list); |
7c390d35 | 3174 | |
08fb59d8 JS |
3175 | if (free_active_root) { |
3176 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3177 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3178 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
08fb59d8 JS |
3179 | } else { |
3180 | for (i = 0; i < 4; ++i) | |
3181 | if (mmu->pae_root[i] != 0) | |
4d710de9 | 3182 | mmu_free_root_page(kvm, |
08fb59d8 JS |
3183 | &mmu->pae_root[i], |
3184 | &invalid_list); | |
3185 | mmu->root_hpa = INVALID_PAGE; | |
3186 | } | |
be01e8e2 | 3187 | mmu->root_pgd = 0; |
17ac10ad | 3188 | } |
74b566e6 | 3189 | |
4d710de9 SC |
3190 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3191 | spin_unlock(&kvm->mmu_lock); | |
17ac10ad | 3192 | } |
74b566e6 | 3193 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3194 | |
8986ecc0 MT |
3195 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3196 | { | |
3197 | int ret = 0; | |
3198 | ||
995decb6 | 3199 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3200 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3201 | ret = 1; |
3202 | } | |
3203 | ||
3204 | return ret; | |
3205 | } | |
3206 | ||
8123f265 SC |
3207 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3208 | u8 level, bool direct) | |
651dd37a JR |
3209 | { |
3210 | struct kvm_mmu_page *sp; | |
8123f265 SC |
3211 | |
3212 | spin_lock(&vcpu->kvm->mmu_lock); | |
3213 | ||
3214 | if (make_mmu_pages_available(vcpu)) { | |
3215 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3216 | return INVALID_PAGE; | |
3217 | } | |
3218 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); | |
3219 | ++sp->root_count; | |
3220 | ||
3221 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3222 | return __pa(sp->spt); | |
3223 | } | |
3224 | ||
3225 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3226 | { | |
3227 | u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level; | |
3228 | hpa_t root; | |
7ebaf15e | 3229 | unsigned i; |
651dd37a | 3230 | |
02c00b3a BG |
3231 | if (vcpu->kvm->arch.tdp_mmu_enabled) { |
3232 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); | |
3233 | ||
3234 | if (!VALID_PAGE(root)) | |
3235 | return -ENOSPC; | |
3236 | vcpu->arch.mmu->root_hpa = root; | |
3237 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { | |
3238 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, | |
3239 | true); | |
3240 | ||
8123f265 | 3241 | if (!VALID_PAGE(root)) |
ed52870f | 3242 | return -ENOSPC; |
8123f265 SC |
3243 | vcpu->arch.mmu->root_hpa = root; |
3244 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3245 | for (i = 0; i < 4; ++i) { |
8123f265 | 3246 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i])); |
651dd37a | 3247 | |
8123f265 SC |
3248 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3249 | i << 30, PT32_ROOT_LEVEL, true); | |
3250 | if (!VALID_PAGE(root)) | |
ed52870f | 3251 | return -ENOSPC; |
44dd3ffa | 3252 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3253 | } |
44dd3ffa | 3254 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3255 | } else |
3256 | BUG(); | |
3651c7fc | 3257 | |
be01e8e2 SC |
3258 | /* root_pgd is ignored for direct MMUs. */ |
3259 | vcpu->arch.mmu->root_pgd = 0; | |
651dd37a JR |
3260 | |
3261 | return 0; | |
3262 | } | |
3263 | ||
3264 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3265 | { |
81407ca5 | 3266 | u64 pdptr, pm_mask; |
be01e8e2 | 3267 | gfn_t root_gfn, root_pgd; |
8123f265 | 3268 | hpa_t root; |
81407ca5 | 3269 | int i; |
3bb65a22 | 3270 | |
be01e8e2 SC |
3271 | root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu); |
3272 | root_gfn = root_pgd >> PAGE_SHIFT; | |
17ac10ad | 3273 | |
651dd37a JR |
3274 | if (mmu_check_root(vcpu, root_gfn)) |
3275 | return 1; | |
3276 | ||
3277 | /* | |
3278 | * Do we shadow a long mode page table? If so we need to | |
3279 | * write-protect the guests page table root. | |
3280 | */ | |
44dd3ffa | 3281 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3282 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
651dd37a | 3283 | |
8123f265 SC |
3284 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
3285 | vcpu->arch.mmu->shadow_root_level, false); | |
3286 | if (!VALID_PAGE(root)) | |
ed52870f | 3287 | return -ENOSPC; |
44dd3ffa | 3288 | vcpu->arch.mmu->root_hpa = root; |
be01e8e2 | 3289 | goto set_root_pgd; |
17ac10ad | 3290 | } |
f87f9288 | 3291 | |
651dd37a JR |
3292 | /* |
3293 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3294 | * or a PAE 3-level page table. In either case we need to be aware that |
3295 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3296 | */ |
81407ca5 | 3297 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3298 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3299 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3300 | ||
17ac10ad | 3301 | for (i = 0; i < 4; ++i) { |
8123f265 | 3302 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i])); |
44dd3ffa VK |
3303 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3304 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3305 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3306 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3307 | continue; |
3308 | } | |
6de4f3ad | 3309 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3310 | if (mmu_check_root(vcpu, root_gfn)) |
3311 | return 1; | |
5a7388c2 | 3312 | } |
8facbbff | 3313 | |
8123f265 SC |
3314 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3315 | PT32_ROOT_LEVEL, false); | |
3316 | if (!VALID_PAGE(root)) | |
3317 | return -ENOSPC; | |
44dd3ffa | 3318 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3319 | } |
44dd3ffa | 3320 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3321 | |
3322 | /* | |
3323 | * If we shadow a 32 bit page table with a long mode page | |
3324 | * table we enter this path. | |
3325 | */ | |
44dd3ffa VK |
3326 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3327 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3328 | /* |
3329 | * The additional page necessary for this is only | |
3330 | * allocated on demand. | |
3331 | */ | |
3332 | ||
3333 | u64 *lm_root; | |
3334 | ||
254272ce | 3335 | lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
81407ca5 JR |
3336 | if (lm_root == NULL) |
3337 | return 1; | |
3338 | ||
44dd3ffa | 3339 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3340 | |
44dd3ffa | 3341 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3342 | } |
3343 | ||
44dd3ffa | 3344 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3345 | } |
3346 | ||
be01e8e2 SC |
3347 | set_root_pgd: |
3348 | vcpu->arch.mmu->root_pgd = root_pgd; | |
ad7dc69a | 3349 | |
8986ecc0 | 3350 | return 0; |
17ac10ad AK |
3351 | } |
3352 | ||
651dd37a JR |
3353 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3354 | { | |
44dd3ffa | 3355 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3356 | return mmu_alloc_direct_roots(vcpu); |
3357 | else | |
3358 | return mmu_alloc_shadow_roots(vcpu); | |
3359 | } | |
3360 | ||
578e1c4d | 3361 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3362 | { |
3363 | int i; | |
3364 | struct kvm_mmu_page *sp; | |
3365 | ||
44dd3ffa | 3366 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3367 | return; |
3368 | ||
44dd3ffa | 3369 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3370 | return; |
6903074c | 3371 | |
56f17dd3 | 3372 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3373 | |
44dd3ffa VK |
3374 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3375 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3376 | sp = to_shadow_page(root); |
578e1c4d JS |
3377 | |
3378 | /* | |
3379 | * Even if another CPU was marking the SP as unsync-ed | |
3380 | * simultaneously, any guest page table changes are not | |
3381 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3382 | * flush strictly after those changes are made. We only need to | |
3383 | * ensure that the other CPU sets these flags before any actual | |
3384 | * changes to the page tables are made. The comments in | |
3385 | * mmu_need_write_protect() describe what could go wrong if this | |
3386 | * requirement isn't satisfied. | |
3387 | */ | |
3388 | if (!smp_load_acquire(&sp->unsync) && | |
3389 | !smp_load_acquire(&sp->unsync_children)) | |
3390 | return; | |
3391 | ||
3392 | spin_lock(&vcpu->kvm->mmu_lock); | |
3393 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3394 | ||
0ba73cda | 3395 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3396 | |
0375f7fa | 3397 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3398 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3399 | return; |
3400 | } | |
578e1c4d JS |
3401 | |
3402 | spin_lock(&vcpu->kvm->mmu_lock); | |
3403 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3404 | ||
0ba73cda | 3405 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3406 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3407 | |
8986ecc0 | 3408 | if (root && VALID_PAGE(root)) { |
0ba73cda | 3409 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3410 | sp = to_shadow_page(root); |
0ba73cda MT |
3411 | mmu_sync_children(vcpu, sp); |
3412 | } | |
3413 | } | |
0ba73cda | 3414 | |
578e1c4d | 3415 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3416 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3417 | } |
bfd0a56b | 3418 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3419 | |
736c291c | 3420 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3421 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3422 | { |
ab9ae313 AK |
3423 | if (exception) |
3424 | exception->error_code = 0; | |
6aa8b732 AK |
3425 | return vaddr; |
3426 | } | |
3427 | ||
736c291c | 3428 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3429 | u32 access, |
3430 | struct x86_exception *exception) | |
6539e738 | 3431 | { |
ab9ae313 AK |
3432 | if (exception) |
3433 | exception->error_code = 0; | |
54987b7a | 3434 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3435 | } |
3436 | ||
d625b155 XG |
3437 | static bool |
3438 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3439 | { | |
b5c3c1b3 | 3440 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3441 | |
b5c3c1b3 | 3442 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3443 | } |
3444 | ||
b5c3c1b3 | 3445 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3446 | { |
b5c3c1b3 | 3447 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3448 | } |
3449 | ||
ded58749 | 3450 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3451 | { |
9034e6e8 PB |
3452 | /* |
3453 | * A nested guest cannot use the MMIO cache if it is using nested | |
3454 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3455 | */ | |
3456 | if (mmu_is_nested(vcpu)) | |
3457 | return false; | |
3458 | ||
ce88decf XG |
3459 | if (direct) |
3460 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3461 | ||
3462 | return vcpu_match_mmio_gva(vcpu, addr); | |
3463 | } | |
3464 | ||
47ab8751 XG |
3465 | /* return true if reserved bit is detected on spte. */ |
3466 | static bool | |
3467 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3468 | { |
3469 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3470 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
b5c3c1b3 | 3471 | struct rsvd_bits_validate *rsvd_check; |
47ab8751 XG |
3472 | int root, leaf; |
3473 | bool reserved = false; | |
ce88decf | 3474 | |
b5c3c1b3 | 3475 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; |
37f6a4e2 | 3476 | |
ce88decf | 3477 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3478 | |
29ecd660 PB |
3479 | for (shadow_walk_init(&iterator, vcpu, addr), |
3480 | leaf = root = iterator.level; | |
47ab8751 XG |
3481 | shadow_walk_okay(&iterator); |
3482 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3483 | spte = mmu_spte_get_lockless(iterator.sptep); |
3484 | ||
3485 | sptes[leaf - 1] = spte; | |
29ecd660 | 3486 | leaf--; |
47ab8751 | 3487 | |
ce88decf XG |
3488 | if (!is_shadow_present_pte(spte)) |
3489 | break; | |
47ab8751 | 3490 | |
b5c3c1b3 SC |
3491 | /* |
3492 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3493 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3494 | * adding a Jcc in the loop. | |
3495 | */ | |
3496 | reserved |= __is_bad_mt_xwr(rsvd_check, spte) | | |
3497 | __is_rsvd_bits_set(rsvd_check, spte, iterator.level); | |
47ab8751 XG |
3498 | } |
3499 | ||
ce88decf XG |
3500 | walk_shadow_page_lockless_end(vcpu); |
3501 | ||
47ab8751 XG |
3502 | if (reserved) { |
3503 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3504 | __func__, addr); | |
29ecd660 | 3505 | while (root > leaf) { |
47ab8751 XG |
3506 | pr_err("------ spte 0x%llx level %d.\n", |
3507 | sptes[root - 1], root); | |
3508 | root--; | |
3509 | } | |
3510 | } | |
ddce6208 | 3511 | |
47ab8751 XG |
3512 | *sptep = spte; |
3513 | return reserved; | |
ce88decf XG |
3514 | } |
3515 | ||
e08d26f0 | 3516 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3517 | { |
3518 | u64 spte; | |
47ab8751 | 3519 | bool reserved; |
ce88decf | 3520 | |
ded58749 | 3521 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3522 | return RET_PF_EMULATE; |
ce88decf | 3523 | |
47ab8751 | 3524 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3525 | if (WARN_ON(reserved)) |
9b8ebbdb | 3526 | return -EINVAL; |
ce88decf XG |
3527 | |
3528 | if (is_mmio_spte(spte)) { | |
3529 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3530 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3531 | |
54bf36aa | 3532 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3533 | return RET_PF_INVALID; |
f8f55942 | 3534 | |
ce88decf XG |
3535 | if (direct) |
3536 | addr = 0; | |
4f022648 XG |
3537 | |
3538 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3539 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3540 | return RET_PF_EMULATE; |
ce88decf XG |
3541 | } |
3542 | ||
ce88decf XG |
3543 | /* |
3544 | * If the page table is zapped by other cpus, let CPU fault again on | |
3545 | * the address. | |
3546 | */ | |
9b8ebbdb | 3547 | return RET_PF_RETRY; |
ce88decf | 3548 | } |
ce88decf | 3549 | |
3d0c27ad XG |
3550 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3551 | u32 error_code, gfn_t gfn) | |
3552 | { | |
3553 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3554 | return false; | |
3555 | ||
3556 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3557 | !(error_code & PFERR_WRITE_MASK)) | |
3558 | return false; | |
3559 | ||
3560 | /* | |
3561 | * guest is writing the page which is write tracked which can | |
3562 | * not be fixed by page fault handler. | |
3563 | */ | |
3564 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3565 | return true; | |
3566 | ||
3567 | return false; | |
3568 | } | |
3569 | ||
e5691a81 XG |
3570 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3571 | { | |
3572 | struct kvm_shadow_walk_iterator iterator; | |
3573 | u64 spte; | |
3574 | ||
e5691a81 XG |
3575 | walk_shadow_page_lockless_begin(vcpu); |
3576 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3577 | clear_sp_write_flooding_count(iterator.sptep); | |
3578 | if (!is_shadow_present_pte(spte)) | |
3579 | break; | |
3580 | } | |
3581 | walk_shadow_page_lockless_end(vcpu); | |
3582 | } | |
3583 | ||
e8c22266 VK |
3584 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3585 | gfn_t gfn) | |
af585b92 GN |
3586 | { |
3587 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3588 | |
7c90705b | 3589 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3590 | arch.gfn = gfn; |
44dd3ffa | 3591 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3592 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3593 | |
9f1a8526 SC |
3594 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3595 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3596 | } |
3597 | ||
78b2c54a | 3598 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
9f1a8526 SC |
3599 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write, |
3600 | bool *writable) | |
af585b92 | 3601 | { |
c36b7150 | 3602 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3603 | bool async; |
3604 | ||
c36b7150 PB |
3605 | /* Don't expose private memslots to L2. */ |
3606 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3607 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3608 | *writable = false; |
3a2936de JM |
3609 | return false; |
3610 | } | |
3611 | ||
3520469d PB |
3612 | async = false; |
3613 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3614 | if (!async) |
3615 | return false; /* *pfn has correct page already */ | |
3616 | ||
9bc1f09f | 3617 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3618 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3619 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3620 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3621 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3622 | return true; | |
9f1a8526 | 3623 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3624 | return true; |
3625 | } | |
3626 | ||
3520469d | 3627 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3628 | return false; |
3629 | } | |
3630 | ||
0f90e1c1 SC |
3631 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3632 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3633 | { |
367fd790 | 3634 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3635 | bool map_writable; |
6aa8b732 | 3636 | |
0f90e1c1 SC |
3637 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3638 | unsigned long mmu_seq; | |
3639 | kvm_pfn_t pfn; | |
83f06fa7 | 3640 | int r; |
ce88decf | 3641 | |
3d0c27ad | 3642 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3643 | return RET_PF_EMULATE; |
ce88decf | 3644 | |
c4371c2a SC |
3645 | r = fast_page_fault(vcpu, gpa, error_code); |
3646 | if (r != RET_PF_INVALID) | |
3647 | return r; | |
83291445 | 3648 | |
378f5cd6 | 3649 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3650 | if (r) |
3651 | return r; | |
714b93da | 3652 | |
367fd790 SC |
3653 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3654 | smp_rmb(); | |
3655 | ||
3656 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) | |
3657 | return RET_PF_RETRY; | |
3658 | ||
0f90e1c1 | 3659 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3660 | return r; |
6aa8b732 | 3661 | |
367fd790 SC |
3662 | r = RET_PF_RETRY; |
3663 | spin_lock(&vcpu->kvm->mmu_lock); | |
3664 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) | |
3665 | goto out_unlock; | |
7bd7ded6 SC |
3666 | r = make_mmu_pages_available(vcpu); |
3667 | if (r) | |
367fd790 | 3668 | goto out_unlock; |
6c2fd34f SC |
3669 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, |
3670 | prefault, is_tdp); | |
0f90e1c1 | 3671 | |
367fd790 SC |
3672 | out_unlock: |
3673 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3674 | kvm_release_pfn_clean(pfn); | |
3675 | return r; | |
6aa8b732 AK |
3676 | } |
3677 | ||
0f90e1c1 SC |
3678 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3679 | u32 error_code, bool prefault) | |
3680 | { | |
3681 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3682 | ||
3683 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3684 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3685 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3686 | } |
3687 | ||
1261bfa3 | 3688 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3689 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3690 | { |
3691 | int r = 1; | |
9ce372b3 | 3692 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3693 | |
736c291c SC |
3694 | #ifndef CONFIG_X86_64 |
3695 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3696 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3697 | return -EFAULT; | |
3698 | #endif | |
3699 | ||
c595ceee | 3700 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3701 | if (!flags) { |
1261bfa3 WL |
3702 | trace_kvm_page_fault(fault_address, error_code); |
3703 | ||
d0006530 | 3704 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3705 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3706 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3707 | insn_len); | |
9ce372b3 | 3708 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3709 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3710 | local_irq_disable(); |
6bca69ad | 3711 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3712 | local_irq_enable(); |
9ce372b3 VK |
3713 | } else { |
3714 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3715 | } |
9ce372b3 | 3716 | |
1261bfa3 WL |
3717 | return r; |
3718 | } | |
3719 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3720 | ||
7a02674d SC |
3721 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3722 | bool prefault) | |
fb72d167 | 3723 | { |
cb9b88c6 | 3724 | int max_level; |
fb72d167 | 3725 | |
e662ec3e | 3726 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3727 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3728 | max_level--) { |
3729 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3730 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3731 | |
cb9b88c6 SC |
3732 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3733 | break; | |
fd136902 | 3734 | } |
852e3c19 | 3735 | |
0f90e1c1 SC |
3736 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3737 | max_level, true); | |
fb72d167 JR |
3738 | } |
3739 | ||
8a3c1a33 PB |
3740 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3741 | struct kvm_mmu *context) | |
6aa8b732 | 3742 | { |
6aa8b732 | 3743 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3744 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3745 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3746 | context->invlpg = NULL; |
0f53b5b1 | 3747 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3748 | context->root_level = 0; |
6aa8b732 | 3749 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 3750 | context->direct_map = true; |
2d48a985 | 3751 | context->nx = false; |
6aa8b732 AK |
3752 | } |
3753 | ||
be01e8e2 | 3754 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3755 | union kvm_mmu_page_role role) |
3756 | { | |
be01e8e2 | 3757 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3758 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3759 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3760 | } |
3761 | ||
b94742c9 | 3762 | /* |
be01e8e2 | 3763 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3764 | * The current root is also inserted into the cache. |
3765 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3766 | * returned. | |
3767 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3768 | * false is returned. This root should now be freed by the caller. | |
3769 | */ | |
be01e8e2 | 3770 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3771 | union kvm_mmu_page_role new_role) |
3772 | { | |
3773 | uint i; | |
3774 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3775 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3776 | |
be01e8e2 | 3777 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3778 | root.hpa = mmu->root_hpa; |
3779 | ||
be01e8e2 | 3780 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3781 | return true; |
3782 | ||
b94742c9 JS |
3783 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3784 | swap(root, mmu->prev_roots[i]); | |
3785 | ||
be01e8e2 | 3786 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3787 | break; |
3788 | } | |
3789 | ||
3790 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3791 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
3792 | |
3793 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
3794 | } | |
3795 | ||
be01e8e2 | 3796 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 3797 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3798 | { |
44dd3ffa | 3799 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
3800 | |
3801 | /* | |
3802 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
3803 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
3804 | * later if necessary. | |
3805 | */ | |
3806 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 3807 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 3808 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
3809 | |
3810 | return false; | |
6aa8b732 AK |
3811 | } |
3812 | ||
be01e8e2 | 3813 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
ade61e28 | 3814 | union kvm_mmu_page_role new_role, |
4a632ac6 | 3815 | bool skip_tlb_flush, bool skip_mmu_sync) |
6aa8b732 | 3816 | { |
be01e8e2 | 3817 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
3818 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
3819 | return; | |
3820 | } | |
3821 | ||
3822 | /* | |
3823 | * It's possible that the cached previous root page is obsolete because | |
3824 | * of a change in the MMU generation number. However, changing the | |
3825 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
3826 | * free the root set here and allocate a new one. | |
3827 | */ | |
3828 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
3829 | ||
71fe7013 | 3830 | if (!skip_mmu_sync || force_flush_and_sync_on_reuse) |
b869855b | 3831 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
71fe7013 | 3832 | if (!skip_tlb_flush || force_flush_and_sync_on_reuse) |
b869855b | 3833 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
b869855b SC |
3834 | |
3835 | /* | |
3836 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
3837 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
3838 | * valid. So clear any cached MMIO info even when we don't need to sync | |
3839 | * the shadow page tables. | |
3840 | */ | |
3841 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
3842 | ||
e47c4aee | 3843 | __clear_sp_write_flooding_count(to_shadow_page(vcpu->arch.mmu->root_hpa)); |
6aa8b732 AK |
3844 | } |
3845 | ||
be01e8e2 | 3846 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, |
4a632ac6 | 3847 | bool skip_mmu_sync) |
0aab33e4 | 3848 | { |
be01e8e2 | 3849 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu), |
4a632ac6 | 3850 | skip_tlb_flush, skip_mmu_sync); |
0aab33e4 | 3851 | } |
be01e8e2 | 3852 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 3853 | |
5777ed34 JR |
3854 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3855 | { | |
9f8fe504 | 3856 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3857 | } |
3858 | ||
54bf36aa | 3859 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 3860 | unsigned int access, int *nr_present) |
ce88decf XG |
3861 | { |
3862 | if (unlikely(is_mmio_spte(*sptep))) { | |
3863 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3864 | mmu_spte_clear_no_track(sptep); | |
3865 | return true; | |
3866 | } | |
3867 | ||
3868 | (*nr_present)++; | |
54bf36aa | 3869 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3870 | return true; |
3871 | } | |
3872 | ||
3873 | return false; | |
3874 | } | |
3875 | ||
6bb69c9b PB |
3876 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3877 | unsigned level, unsigned gpte) | |
6fd01b71 | 3878 | { |
6bb69c9b PB |
3879 | /* |
3880 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3881 | * If it is clear, there are no large pages at this level, so clear | |
3882 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3883 | */ | |
3884 | gpte &= level - mmu->last_nonleaf_level; | |
3885 | ||
829ee279 | 3886 | /* |
3bae0459 SC |
3887 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set |
3888 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
3889 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
829ee279 | 3890 | */ |
3bae0459 | 3891 | gpte |= level - PG_LEVEL_4K - 1; |
829ee279 | 3892 | |
6bb69c9b | 3893 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
3894 | } |
3895 | ||
37406aaa NHE |
3896 | #define PTTYPE_EPT 18 /* arbitrary */ |
3897 | #define PTTYPE PTTYPE_EPT | |
3898 | #include "paging_tmpl.h" | |
3899 | #undef PTTYPE | |
3900 | ||
6aa8b732 AK |
3901 | #define PTTYPE 64 |
3902 | #include "paging_tmpl.h" | |
3903 | #undef PTTYPE | |
3904 | ||
3905 | #define PTTYPE 32 | |
3906 | #include "paging_tmpl.h" | |
3907 | #undef PTTYPE | |
3908 | ||
6dc98b86 XG |
3909 | static void |
3910 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3911 | struct rsvd_bits_validate *rsvd_check, | |
3912 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3913 | bool pse, bool amd) |
82725b20 | 3914 | { |
82725b20 | 3915 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3916 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3917 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3918 | |
a0a64f50 | 3919 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3920 | |
6dc98b86 | 3921 | if (!nx) |
82725b20 | 3922 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3923 | if (!gbpages) |
5f7dde7b | 3924 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3925 | |
3926 | /* | |
3927 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3928 | * leaf entries) on AMD CPUs only. | |
3929 | */ | |
6fec2144 | 3930 | if (amd) |
a0c0feb5 PB |
3931 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3932 | ||
6dc98b86 | 3933 | switch (level) { |
82725b20 DE |
3934 | case PT32_ROOT_LEVEL: |
3935 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3936 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3937 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3938 | rsvd_check->rsvd_bits_mask[1][0] = | |
3939 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3940 | |
6dc98b86 | 3941 | if (!pse) { |
a0a64f50 | 3942 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
3943 | break; |
3944 | } | |
3945 | ||
82725b20 DE |
3946 | if (is_cpuid_PSE36()) |
3947 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 3948 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
3949 | else |
3950 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 3951 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
3952 | break; |
3953 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 3954 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 3955 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 3956 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 3957 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3958 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 3959 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 3960 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 3961 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
3962 | rsvd_bits(maxphyaddr, 62) | |
3963 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3964 | rsvd_check->rsvd_bits_mask[1][0] = |
3965 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 3966 | break; |
855feb67 YZ |
3967 | case PT64_ROOT_5LEVEL: |
3968 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
3969 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
3970 | rsvd_bits(maxphyaddr, 51); | |
3971 | rsvd_check->rsvd_bits_mask[1][4] = | |
3972 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 3973 | fallthrough; |
2a7266a8 | 3974 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
3975 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
3976 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 3977 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 | 3978 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
5ecad245 | 3979 | gbpages_bit_rsvd | |
82725b20 | 3980 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3981 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
3982 | rsvd_bits(maxphyaddr, 51); | |
3983 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
3984 | rsvd_bits(maxphyaddr, 51); | |
3985 | rsvd_check->rsvd_bits_mask[1][3] = | |
3986 | rsvd_check->rsvd_bits_mask[0][3]; | |
3987 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 3988 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3989 | rsvd_bits(13, 29); |
a0a64f50 | 3990 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3991 | rsvd_bits(maxphyaddr, 51) | |
3992 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3993 | rsvd_check->rsvd_bits_mask[1][0] = |
3994 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3995 | break; |
3996 | } | |
3997 | } | |
3998 | ||
6dc98b86 XG |
3999 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4000 | struct kvm_mmu *context) | |
4001 | { | |
4002 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4003 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4004 | context->nx, |
4005 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
23493d0a SC |
4006 | is_pse(vcpu), |
4007 | guest_cpuid_is_amd_or_hygon(vcpu)); | |
6dc98b86 XG |
4008 | } |
4009 | ||
81b8eebb XG |
4010 | static void |
4011 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4012 | int maxphyaddr, bool execonly) | |
25d92081 | 4013 | { |
951f9fd7 | 4014 | u64 bad_mt_xwr; |
25d92081 | 4015 | |
855feb67 YZ |
4016 | rsvd_check->rsvd_bits_mask[0][4] = |
4017 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4018 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4019 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4020 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4021 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4022 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4023 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4024 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4025 | |
4026 | /* large page */ | |
855feb67 | 4027 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4028 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4029 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4030 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4031 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4032 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4033 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4034 | |
951f9fd7 PB |
4035 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4036 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4037 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4038 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4039 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4040 | if (!execonly) { | |
4041 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4042 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4043 | } |
951f9fd7 | 4044 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4045 | } |
4046 | ||
81b8eebb XG |
4047 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4048 | struct kvm_mmu *context, bool execonly) | |
4049 | { | |
4050 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4051 | cpuid_maxphyaddr(vcpu), execonly); | |
4052 | } | |
4053 | ||
c258b62b XG |
4054 | /* |
4055 | * the page table on host is the shadow page table for the page | |
4056 | * table in guest or amd nested guest, its mmu features completely | |
4057 | * follow the features in guest. | |
4058 | */ | |
4059 | void | |
4060 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4061 | { | |
36d9594d VK |
4062 | bool uses_nx = context->nx || |
4063 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4064 | struct rsvd_bits_validate *shadow_zero_check; |
4065 | int i; | |
5f0b8199 | 4066 | |
6fec2144 PB |
4067 | /* |
4068 | * Passing "true" to the last argument is okay; it adds a check | |
4069 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4070 | */ | |
ea2800dd BS |
4071 | shadow_zero_check = &context->shadow_zero_check; |
4072 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
f3ecb59d | 4073 | shadow_phys_bits, |
5f0b8199 | 4074 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4075 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4076 | is_pse(vcpu), true); | |
ea2800dd BS |
4077 | |
4078 | if (!shadow_me_mask) | |
4079 | return; | |
4080 | ||
4081 | for (i = context->shadow_root_level; --i >= 0;) { | |
4082 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4083 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4084 | } | |
4085 | ||
c258b62b XG |
4086 | } |
4087 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4088 | ||
6fec2144 PB |
4089 | static inline bool boot_cpu_is_amd(void) |
4090 | { | |
4091 | WARN_ON_ONCE(!tdp_enabled); | |
4092 | return shadow_x_mask == 0; | |
4093 | } | |
4094 | ||
c258b62b XG |
4095 | /* |
4096 | * the direct page table on host, use as much mmu features as | |
4097 | * possible, however, kvm currently does not do execution-protection. | |
4098 | */ | |
4099 | static void | |
4100 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4101 | struct kvm_mmu *context) | |
4102 | { | |
ea2800dd BS |
4103 | struct rsvd_bits_validate *shadow_zero_check; |
4104 | int i; | |
4105 | ||
4106 | shadow_zero_check = &context->shadow_zero_check; | |
4107 | ||
6fec2144 | 4108 | if (boot_cpu_is_amd()) |
ea2800dd | 4109 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
f3ecb59d | 4110 | shadow_phys_bits, |
c258b62b | 4111 | context->shadow_root_level, false, |
b8291adc BP |
4112 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4113 | true, true); | |
c258b62b | 4114 | else |
ea2800dd | 4115 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
f3ecb59d | 4116 | shadow_phys_bits, |
c258b62b XG |
4117 | false); |
4118 | ||
ea2800dd BS |
4119 | if (!shadow_me_mask) |
4120 | return; | |
4121 | ||
4122 | for (i = context->shadow_root_level; --i >= 0;) { | |
4123 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4124 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4125 | } | |
c258b62b XG |
4126 | } |
4127 | ||
4128 | /* | |
4129 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4130 | * is the shadow page table for intel nested guest. | |
4131 | */ | |
4132 | static void | |
4133 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4134 | struct kvm_mmu *context, bool execonly) | |
4135 | { | |
4136 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
f3ecb59d | 4137 | shadow_phys_bits, execonly); |
c258b62b XG |
4138 | } |
4139 | ||
09f037aa PB |
4140 | #define BYTE_MASK(access) \ |
4141 | ((1 & (access) ? 2 : 0) | \ | |
4142 | (2 & (access) ? 4 : 0) | \ | |
4143 | (3 & (access) ? 8 : 0) | \ | |
4144 | (4 & (access) ? 16 : 0) | \ | |
4145 | (5 & (access) ? 32 : 0) | \ | |
4146 | (6 & (access) ? 64 : 0) | \ | |
4147 | (7 & (access) ? 128 : 0)) | |
4148 | ||
4149 | ||
edc90b7d XG |
4150 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4151 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4152 | { |
09f037aa PB |
4153 | unsigned byte; |
4154 | ||
4155 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4156 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4157 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4158 | ||
4159 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4160 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4161 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4162 | |
97d64b78 | 4163 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4164 | unsigned pfec = byte << 1; |
4165 | ||
97ec8c06 | 4166 | /* |
09f037aa PB |
4167 | * Each "*f" variable has a 1 bit for each UWX value |
4168 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4169 | */ |
97d64b78 | 4170 | |
09f037aa | 4171 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4172 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4173 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4174 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4175 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4176 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4177 | /* Faults from kernel mode fetches of user pages */ |
4178 | u8 smepf = 0; | |
4179 | /* Faults from kernel mode accesses of user pages */ | |
4180 | u8 smapf = 0; | |
4181 | ||
4182 | if (!ept) { | |
4183 | /* Faults from kernel mode accesses to user pages */ | |
4184 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4185 | ||
4186 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4187 | if (!mmu->nx) | |
4188 | ff = 0; | |
4189 | ||
4190 | /* Allow supervisor writes if !cr0.wp */ | |
4191 | if (!cr0_wp) | |
4192 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4193 | ||
4194 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4195 | if (cr4_smep) | |
4196 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4197 | ||
4198 | /* | |
4199 | * SMAP:kernel-mode data accesses from user-mode | |
4200 | * mappings should fault. A fault is considered | |
4201 | * as a SMAP violation if all of the following | |
39337ad1 | 4202 | * conditions are true: |
09f037aa PB |
4203 | * - X86_CR4_SMAP is set in CR4 |
4204 | * - A user page is accessed | |
4205 | * - The access is not a fetch | |
4206 | * - Page fault in kernel mode | |
4207 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4208 | * | |
4209 | * Here, we cover the first three conditions. | |
4210 | * The fourth is computed dynamically in permission_fault(); | |
4211 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4212 | * *not* subject to SMAP restrictions. | |
4213 | */ | |
4214 | if (cr4_smap) | |
4215 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4216 | } |
09f037aa PB |
4217 | |
4218 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4219 | } |
4220 | } | |
4221 | ||
2d344105 HH |
4222 | /* |
4223 | * PKU is an additional mechanism by which the paging controls access to | |
4224 | * user-mode addresses based on the value in the PKRU register. Protection | |
4225 | * key violations are reported through a bit in the page fault error code. | |
4226 | * Unlike other bits of the error code, the PK bit is not known at the | |
4227 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4228 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4229 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4230 | * | |
4231 | * In particular the following conditions come from the error code, the | |
4232 | * page tables and the machine state: | |
4233 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4234 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4235 | * - PK is always zero if U=0 in the page tables | |
4236 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4237 | * | |
4238 | * The PKRU bitmask caches the result of these four conditions. The error | |
4239 | * code (minus the P bit) and the page table's U bit form an index into the | |
4240 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4241 | * with the two bits of the PKRU register corresponding to the protection key. | |
4242 | * For the first three conditions above the bits will be 00, thus masking | |
4243 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4244 | * only will be masked away. | |
4245 | */ | |
4246 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4247 | bool ept) | |
4248 | { | |
4249 | unsigned bit; | |
4250 | bool wp; | |
4251 | ||
4252 | if (ept) { | |
4253 | mmu->pkru_mask = 0; | |
4254 | return; | |
4255 | } | |
4256 | ||
4257 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4258 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4259 | mmu->pkru_mask = 0; | |
4260 | return; | |
4261 | } | |
4262 | ||
4263 | wp = is_write_protection(vcpu); | |
4264 | ||
4265 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4266 | unsigned pfec, pkey_bits; | |
4267 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4268 | ||
4269 | pfec = bit << 1; | |
4270 | ff = pfec & PFERR_FETCH_MASK; | |
4271 | uf = pfec & PFERR_USER_MASK; | |
4272 | wf = pfec & PFERR_WRITE_MASK; | |
4273 | ||
4274 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4275 | pte_user = pfec & PFERR_RSVD_MASK; | |
4276 | ||
4277 | /* | |
4278 | * Only need to check the access which is not an | |
4279 | * instruction fetch and is to a user page. | |
4280 | */ | |
4281 | check_pkey = (!ff && pte_user); | |
4282 | /* | |
4283 | * write access is controlled by PKRU if it is a | |
4284 | * user access or CR0.WP = 1. | |
4285 | */ | |
4286 | check_write = check_pkey && wf && (uf || wp); | |
4287 | ||
4288 | /* PKRU.AD stops both read and write access. */ | |
4289 | pkey_bits = !!check_pkey; | |
4290 | /* PKRU.WD stops write access. */ | |
4291 | pkey_bits |= (!!check_write) << 1; | |
4292 | ||
4293 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4294 | } | |
4295 | } | |
4296 | ||
6bb69c9b | 4297 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4298 | { |
6bb69c9b PB |
4299 | unsigned root_level = mmu->root_level; |
4300 | ||
4301 | mmu->last_nonleaf_level = root_level; | |
4302 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4303 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4304 | } |
4305 | ||
8a3c1a33 PB |
4306 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4307 | struct kvm_mmu *context, | |
4308 | int level) | |
6aa8b732 | 4309 | { |
2d48a985 | 4310 | context->nx = is_nx(vcpu); |
4d6931c3 | 4311 | context->root_level = level; |
2d48a985 | 4312 | |
4d6931c3 | 4313 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4314 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4315 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4316 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4317 | |
fa4a2c08 | 4318 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4319 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4320 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4321 | context->sync_page = paging64_sync_page; |
a7052897 | 4322 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4323 | context->update_pte = paging64_update_pte; |
17ac10ad | 4324 | context->shadow_root_level = level; |
c5a78f2b | 4325 | context->direct_map = false; |
6aa8b732 AK |
4326 | } |
4327 | ||
8a3c1a33 PB |
4328 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4329 | struct kvm_mmu *context) | |
17ac10ad | 4330 | { |
855feb67 YZ |
4331 | int root_level = is_la57_mode(vcpu) ? |
4332 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4333 | ||
4334 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4335 | } |
4336 | ||
8a3c1a33 PB |
4337 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4338 | struct kvm_mmu *context) | |
6aa8b732 | 4339 | { |
2d48a985 | 4340 | context->nx = false; |
4d6931c3 | 4341 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4342 | |
4d6931c3 | 4343 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4344 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4345 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4346 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4347 | |
6aa8b732 | 4348 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4349 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4350 | context->sync_page = paging32_sync_page; |
a7052897 | 4351 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4352 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4353 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4354 | context->direct_map = false; |
6aa8b732 AK |
4355 | } |
4356 | ||
8a3c1a33 PB |
4357 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4358 | struct kvm_mmu *context) | |
6aa8b732 | 4359 | { |
8a3c1a33 | 4360 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4361 | } |
4362 | ||
a336282d VK |
4363 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4364 | { | |
4365 | union kvm_mmu_extended_role ext = {0}; | |
4366 | ||
7dcd5755 | 4367 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4368 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4369 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4370 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4371 | ext.cr4_pse = !!is_pse(vcpu); | |
4372 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
de3ccd26 | 4373 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4374 | |
4375 | ext.valid = 1; | |
4376 | ||
4377 | return ext; | |
4378 | } | |
4379 | ||
7dcd5755 VK |
4380 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4381 | bool base_only) | |
4382 | { | |
4383 | union kvm_mmu_role role = {0}; | |
4384 | ||
4385 | role.base.access = ACC_ALL; | |
4386 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4387 | role.base.cr0_wp = is_write_protection(vcpu); |
4388 | role.base.smm = is_smm(vcpu); | |
4389 | role.base.guest_mode = is_guest_mode(vcpu); | |
4390 | ||
4391 | if (base_only) | |
4392 | return role; | |
4393 | ||
4394 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4395 | ||
4396 | return role; | |
4397 | } | |
4398 | ||
d468d94b SC |
4399 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4400 | { | |
4401 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4402 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4403 | return 4; |
4404 | ||
83013059 | 4405 | return max_tdp_level; |
d468d94b SC |
4406 | } |
4407 | ||
7dcd5755 VK |
4408 | static union kvm_mmu_role |
4409 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4410 | { |
7dcd5755 | 4411 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4412 | |
7dcd5755 | 4413 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4414 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4415 | role.base.direct = true; |
47c42e6b | 4416 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4417 | |
4418 | return role; | |
4419 | } | |
4420 | ||
8a3c1a33 | 4421 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4422 | { |
8c008659 | 4423 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
7dcd5755 VK |
4424 | union kvm_mmu_role new_role = |
4425 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4426 | |
7dcd5755 VK |
4427 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4428 | return; | |
4429 | ||
4430 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4431 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4432 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4433 | context->invlpg = NULL; |
0f53b5b1 | 4434 | context->update_pte = nonpaging_update_pte; |
d468d94b | 4435 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4436 | context->direct_map = true; |
d8dd54e0 | 4437 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4438 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4439 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4440 | |
4441 | if (!is_paging(vcpu)) { | |
2d48a985 | 4442 | context->nx = false; |
fb72d167 JR |
4443 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4444 | context->root_level = 0; | |
4445 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4446 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4447 | context->root_level = is_la57_mode(vcpu) ? |
4448 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4449 | reset_rsvds_bits_mask(vcpu, context); |
4450 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4451 | } else if (is_pae(vcpu)) { |
2d48a985 | 4452 | context->nx = is_nx(vcpu); |
fb72d167 | 4453 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4454 | reset_rsvds_bits_mask(vcpu, context); |
4455 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4456 | } else { |
2d48a985 | 4457 | context->nx = false; |
fb72d167 | 4458 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4459 | reset_rsvds_bits_mask(vcpu, context); |
4460 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4461 | } |
4462 | ||
25d92081 | 4463 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4464 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4465 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4466 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4467 | } |
4468 | ||
7dcd5755 | 4469 | static union kvm_mmu_role |
59505b55 | 4470 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only) |
7dcd5755 VK |
4471 | { |
4472 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4473 | ||
4474 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4475 | !is_write_protection(vcpu); | |
4476 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4477 | !is_write_protection(vcpu); | |
47c42e6b | 4478 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 | 4479 | |
59505b55 SC |
4480 | return role; |
4481 | } | |
4482 | ||
4483 | static union kvm_mmu_role | |
4484 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4485 | { | |
4486 | union kvm_mmu_role role = | |
4487 | kvm_calc_shadow_root_page_role_common(vcpu, base_only); | |
4488 | ||
4489 | role.base.direct = !is_paging(vcpu); | |
4490 | ||
9fa72119 | 4491 | if (!is_long_mode(vcpu)) |
7dcd5755 | 4492 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4493 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4494 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4495 | else |
7dcd5755 | 4496 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4497 | |
4498 | return role; | |
4499 | } | |
4500 | ||
8c008659 PB |
4501 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
4502 | u32 cr0, u32 cr4, u32 efer, | |
4503 | union kvm_mmu_role new_role) | |
9fa72119 | 4504 | { |
929d1cfa | 4505 | if (!(cr0 & X86_CR0_PG)) |
8a3c1a33 | 4506 | nonpaging_init_context(vcpu, context); |
929d1cfa | 4507 | else if (efer & EFER_LMA) |
8a3c1a33 | 4508 | paging64_init_context(vcpu, context); |
929d1cfa | 4509 | else if (cr4 & X86_CR4_PAE) |
8a3c1a33 | 4510 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4511 | else |
8a3c1a33 | 4512 | paging32_init_context(vcpu, context); |
a770f6f2 | 4513 | |
7dcd5755 | 4514 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4515 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4516 | } |
0f04a2ac VK |
4517 | |
4518 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer) | |
4519 | { | |
8c008659 | 4520 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac VK |
4521 | union kvm_mmu_role new_role = |
4522 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4523 | ||
4524 | if (new_role.as_u64 != context->mmu_role.as_u64) | |
8c008659 | 4525 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4526 | } |
4527 | ||
59505b55 SC |
4528 | static union kvm_mmu_role |
4529 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu) | |
4530 | { | |
4531 | union kvm_mmu_role role = | |
4532 | kvm_calc_shadow_root_page_role_common(vcpu, false); | |
4533 | ||
4534 | role.base.direct = false; | |
d468d94b | 4535 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4536 | |
4537 | return role; | |
4538 | } | |
4539 | ||
0f04a2ac VK |
4540 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer, |
4541 | gpa_t nested_cr3) | |
4542 | { | |
8c008659 | 4543 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
59505b55 | 4544 | union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu); |
0f04a2ac | 4545 | |
096586fd SC |
4546 | context->shadow_root_level = new_role.base.level; |
4547 | ||
a506fdd2 VK |
4548 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false); |
4549 | ||
0f04a2ac | 4550 | if (new_role.as_u64 != context->mmu_role.as_u64) |
8c008659 | 4551 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4552 | } |
4553 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4554 | |
a336282d VK |
4555 | static union kvm_mmu_role |
4556 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4557 | bool execonly, u8 level) |
9fa72119 | 4558 | { |
552c69b1 | 4559 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4560 | |
47c42e6b SC |
4561 | /* SMM flag is inherited from root_mmu */ |
4562 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4563 | |
bb1fcc70 | 4564 | role.base.level = level; |
47c42e6b | 4565 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4566 | role.base.direct = false; |
4567 | role.base.ad_disabled = !accessed_dirty; | |
4568 | role.base.guest_mode = true; | |
4569 | role.base.access = ACC_ALL; | |
9fa72119 | 4570 | |
47c42e6b SC |
4571 | /* |
4572 | * WP=1 and NOT_WP=1 is an impossible combination, use WP and the | |
4573 | * SMAP variation to denote shadow EPT entries. | |
4574 | */ | |
4575 | role.base.cr0_wp = true; | |
4576 | role.base.smap_andnot_wp = true; | |
4577 | ||
552c69b1 | 4578 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 4579 | role.ext.execonly = execonly; |
9fa72119 JS |
4580 | |
4581 | return role; | |
4582 | } | |
4583 | ||
ae1e2d10 | 4584 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4585 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4586 | { |
8c008659 | 4587 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4588 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4589 | union kvm_mmu_role new_role = |
4590 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4591 | execonly, level); |
a336282d | 4592 | |
be01e8e2 | 4593 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true); |
a336282d | 4594 | |
a336282d VK |
4595 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4596 | return; | |
ad896af0 | 4597 | |
bb1fcc70 | 4598 | context->shadow_root_level = level; |
155a97a3 NHE |
4599 | |
4600 | context->nx = true; | |
ae1e2d10 | 4601 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4602 | context->page_fault = ept_page_fault; |
4603 | context->gva_to_gpa = ept_gva_to_gpa; | |
4604 | context->sync_page = ept_sync_page; | |
4605 | context->invlpg = ept_invlpg; | |
4606 | context->update_pte = ept_update_pte; | |
bb1fcc70 | 4607 | context->root_level = level; |
155a97a3 | 4608 | context->direct_map = false; |
a336282d | 4609 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4610 | |
155a97a3 | 4611 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4612 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4613 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4614 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4615 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4616 | } |
4617 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4618 | ||
8a3c1a33 | 4619 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4620 | { |
8c008659 | 4621 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
ad896af0 | 4622 | |
929d1cfa PB |
4623 | kvm_init_shadow_mmu(vcpu, |
4624 | kvm_read_cr0_bits(vcpu, X86_CR0_PG), | |
4625 | kvm_read_cr4_bits(vcpu, X86_CR4_PAE), | |
4626 | vcpu->arch.efer); | |
4627 | ||
d8dd54e0 | 4628 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4629 | context->get_pdptr = kvm_pdptr_read; |
4630 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4631 | } |
4632 | ||
8a3c1a33 | 4633 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4634 | { |
bf627a92 | 4635 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
4636 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4637 | ||
bf627a92 VK |
4638 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4639 | return; | |
4640 | ||
4641 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4642 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4643 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4644 | g_context->inject_page_fault = kvm_inject_page_fault; |
4645 | ||
5efac074 PB |
4646 | /* |
4647 | * L2 page tables are never shadowed, so there is no need to sync | |
4648 | * SPTEs. | |
4649 | */ | |
4650 | g_context->invlpg = NULL; | |
4651 | ||
02f59dc9 | 4652 | /* |
44dd3ffa | 4653 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4654 | * L1's nested page tables (e.g. EPT12). The nested translation |
4655 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4656 | * L2's page tables as the first level of translation and L1's | |
4657 | * nested page tables as the second level of translation. Basically | |
4658 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4659 | */ |
4660 | if (!is_paging(vcpu)) { | |
2d48a985 | 4661 | g_context->nx = false; |
02f59dc9 JR |
4662 | g_context->root_level = 0; |
4663 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4664 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4665 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4666 | g_context->root_level = is_la57_mode(vcpu) ? |
4667 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4668 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4669 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4670 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4671 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4672 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4673 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4674 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4675 | } else { | |
2d48a985 | 4676 | g_context->nx = false; |
02f59dc9 | 4677 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4678 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4679 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4680 | } | |
4681 | ||
25d92081 | 4682 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4683 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4684 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4685 | } |
4686 | ||
1c53da3f | 4687 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 4688 | { |
1c53da3f | 4689 | if (reset_roots) { |
b94742c9 JS |
4690 | uint i; |
4691 | ||
44dd3ffa | 4692 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
4693 | |
4694 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 4695 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
4696 | } |
4697 | ||
02f59dc9 | 4698 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4699 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4700 | else if (tdp_enabled) |
e0c6db3e | 4701 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4702 | else |
e0c6db3e | 4703 | init_kvm_softmmu(vcpu); |
fb72d167 | 4704 | } |
1c53da3f | 4705 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4706 | |
9fa72119 JS |
4707 | static union kvm_mmu_page_role |
4708 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4709 | { | |
7dcd5755 VK |
4710 | union kvm_mmu_role role; |
4711 | ||
9fa72119 | 4712 | if (tdp_enabled) |
7dcd5755 | 4713 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 4714 | else |
7dcd5755 VK |
4715 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
4716 | ||
4717 | return role.base; | |
9fa72119 | 4718 | } |
fb72d167 | 4719 | |
8a3c1a33 | 4720 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4721 | { |
95f93af4 | 4722 | kvm_mmu_unload(vcpu); |
1c53da3f | 4723 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 4724 | } |
8668a3c4 | 4725 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4726 | |
4727 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4728 | { |
714b93da AK |
4729 | int r; |
4730 | ||
378f5cd6 | 4731 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
4732 | if (r) |
4733 | goto out; | |
8986ecc0 | 4734 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4735 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4736 | if (r) |
4737 | goto out; | |
727a7e27 | 4738 | kvm_mmu_load_pgd(vcpu); |
8c8560b8 | 4739 | kvm_x86_ops.tlb_flush_current(vcpu); |
714b93da AK |
4740 | out: |
4741 | return r; | |
6aa8b732 | 4742 | } |
17c3ba9d AK |
4743 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4744 | ||
4745 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4746 | { | |
14c07ad8 VK |
4747 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
4748 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
4749 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
4750 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 4751 | } |
4b16184c | 4752 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4753 | |
0028425f | 4754 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4755 | struct kvm_mmu_page *sp, u64 *spte, |
4756 | const void *new) | |
0028425f | 4757 | { |
3bae0459 | 4758 | if (sp->role.level != PG_LEVEL_4K) { |
7e4e4056 JR |
4759 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4760 | return; | |
30945387 | 4761 | } |
0028425f | 4762 | |
4cee5764 | 4763 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 4764 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
4765 | } |
4766 | ||
79539cec AK |
4767 | static bool need_remote_flush(u64 old, u64 new) |
4768 | { | |
4769 | if (!is_shadow_present_pte(old)) | |
4770 | return false; | |
4771 | if (!is_shadow_present_pte(new)) | |
4772 | return true; | |
4773 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4774 | return true; | |
53166229 GN |
4775 | old ^= shadow_nx_mask; |
4776 | new ^= shadow_nx_mask; | |
79539cec AK |
4777 | return (old & ~new & PT64_PERM_MASK) != 0; |
4778 | } | |
4779 | ||
889e5cbc | 4780 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 4781 | int *bytes) |
da4a00f0 | 4782 | { |
0e0fee5c | 4783 | u64 gentry = 0; |
889e5cbc | 4784 | int r; |
72016f3a | 4785 | |
72016f3a AK |
4786 | /* |
4787 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4788 | * as the current vcpu paging mode since we update the sptes only |
4789 | * when they have the same mode. | |
72016f3a | 4790 | */ |
889e5cbc | 4791 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4792 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4793 | *gpa &= ~(gpa_t)7; |
4794 | *bytes = 8; | |
08e850c6 AK |
4795 | } |
4796 | ||
0e0fee5c JS |
4797 | if (*bytes == 4 || *bytes == 8) { |
4798 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
4799 | if (r) | |
4800 | gentry = 0; | |
72016f3a AK |
4801 | } |
4802 | ||
889e5cbc XG |
4803 | return gentry; |
4804 | } | |
4805 | ||
4806 | /* | |
4807 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4808 | * or we may be forking, in which case it is better to unmap the page. | |
4809 | */ | |
a138fe75 | 4810 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4811 | { |
a30f47cb XG |
4812 | /* |
4813 | * Skip write-flooding detected for the sp whose level is 1, because | |
4814 | * it can become unsync, then the guest page is not write-protected. | |
4815 | */ | |
3bae0459 | 4816 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 4817 | return false; |
3246af0e | 4818 | |
e5691a81 XG |
4819 | atomic_inc(&sp->write_flooding_count); |
4820 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4821 | } |
4822 | ||
4823 | /* | |
4824 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4825 | * indicate a page is not used as a page table. | |
4826 | */ | |
4827 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4828 | int bytes) | |
4829 | { | |
4830 | unsigned offset, pte_size, misaligned; | |
4831 | ||
4832 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4833 | gpa, bytes, sp->role.word); | |
4834 | ||
4835 | offset = offset_in_page(gpa); | |
47c42e6b | 4836 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
4837 | |
4838 | /* | |
4839 | * Sometimes, the OS only writes the last one bytes to update status | |
4840 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4841 | */ | |
4842 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4843 | return false; | |
4844 | ||
889e5cbc XG |
4845 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4846 | misaligned |= bytes < 4; | |
4847 | ||
4848 | return misaligned; | |
4849 | } | |
4850 | ||
4851 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4852 | { | |
4853 | unsigned page_offset, quadrant; | |
4854 | u64 *spte; | |
4855 | int level; | |
4856 | ||
4857 | page_offset = offset_in_page(gpa); | |
4858 | level = sp->role.level; | |
4859 | *nspte = 1; | |
47c42e6b | 4860 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
4861 | page_offset <<= 1; /* 32->64 */ |
4862 | /* | |
4863 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4864 | * only 2MB. So we need to double the offset again | |
4865 | * and zap two pdes instead of one. | |
4866 | */ | |
4867 | if (level == PT32_ROOT_LEVEL) { | |
4868 | page_offset &= ~7; /* kill rounding error */ | |
4869 | page_offset <<= 1; | |
4870 | *nspte = 2; | |
4871 | } | |
4872 | quadrant = page_offset >> PAGE_SHIFT; | |
4873 | page_offset &= ~PAGE_MASK; | |
4874 | if (quadrant != sp->role.quadrant) | |
4875 | return NULL; | |
4876 | } | |
4877 | ||
4878 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4879 | return spte; | |
4880 | } | |
4881 | ||
a102a674 SC |
4882 | /* |
4883 | * Ignore various flags when determining if a SPTE can be immediately | |
4884 | * overwritten for the current MMU. | |
4885 | * - level: explicitly checked in mmu_pte_write_new_pte(), and will never | |
4886 | * match the current MMU role, as MMU's level tracks the root level. | |
4887 | * - access: updated based on the new guest PTE | |
4888 | * - quadrant: handled by get_written_sptes() | |
4889 | * - invalid: always false (loop only walks valid shadow pages) | |
4890 | */ | |
4891 | static const union kvm_mmu_page_role role_ign = { | |
4892 | .level = 0xf, | |
4893 | .access = 0x7, | |
4894 | .quadrant = 0x3, | |
4895 | .invalid = 0x1, | |
4896 | }; | |
4897 | ||
13d268ca | 4898 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4899 | const u8 *new, int bytes, |
4900 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4901 | { |
4902 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4903 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4904 | LIST_HEAD(invalid_list); |
4905 | u64 entry, gentry, *spte; | |
4906 | int npte; | |
b8c67b7a | 4907 | bool remote_flush, local_flush; |
889e5cbc XG |
4908 | |
4909 | /* | |
4910 | * If we don't have indirect shadow pages, it means no page is | |
4911 | * write-protected, so we can exit simply. | |
4912 | */ | |
6aa7de05 | 4913 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
4914 | return; |
4915 | ||
b8c67b7a | 4916 | remote_flush = local_flush = false; |
889e5cbc XG |
4917 | |
4918 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4919 | ||
889e5cbc XG |
4920 | /* |
4921 | * No need to care whether allocation memory is successful | |
4922 | * or not since pte prefetch is skiped if it does not have | |
4923 | * enough objects in the cache. | |
4924 | */ | |
378f5cd6 | 4925 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc XG |
4926 | |
4927 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
4928 | |
4929 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
4930 | ||
889e5cbc | 4931 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 4932 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4933 | |
b67bfe0d | 4934 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4935 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4936 | detect_write_flooding(sp)) { |
b8c67b7a | 4937 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4938 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4939 | continue; |
4940 | } | |
889e5cbc XG |
4941 | |
4942 | spte = get_written_sptes(sp, gpa, &npte); | |
4943 | if (!spte) | |
4944 | continue; | |
4945 | ||
0671a8e7 | 4946 | local_flush = true; |
ac1b714e | 4947 | while (npte--) { |
36d9594d VK |
4948 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
4949 | ||
79539cec | 4950 | entry = *spte; |
2de4085c | 4951 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
fa1de2bf | 4952 | if (gentry && |
a102a674 SC |
4953 | !((sp->role.word ^ base_role) & ~role_ign.word) && |
4954 | rmap_can_add(vcpu)) | |
7c562522 | 4955 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4956 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4957 | remote_flush = true; |
ac1b714e | 4958 | ++spte; |
9b7a0325 | 4959 | } |
9b7a0325 | 4960 | } |
b8c67b7a | 4961 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4962 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4963 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4964 | } |
4965 | ||
a436036b AK |
4966 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4967 | { | |
10589a46 MT |
4968 | gpa_t gpa; |
4969 | int r; | |
a436036b | 4970 | |
44dd3ffa | 4971 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
4972 | return 0; |
4973 | ||
1871c602 | 4974 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4975 | |
10589a46 | 4976 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4977 | |
10589a46 | 4978 | return r; |
a436036b | 4979 | } |
577bdc49 | 4980 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4981 | |
736c291c | 4982 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 4983 | void *insn, int insn_len) |
3067714c | 4984 | { |
92daa48b | 4985 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 4986 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 4987 | |
6948199a | 4988 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
4989 | return RET_PF_RETRY; |
4990 | ||
9b8ebbdb | 4991 | r = RET_PF_INVALID; |
e9ee956e | 4992 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 4993 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 4994 | if (r == RET_PF_EMULATE) |
e9ee956e | 4995 | goto emulate; |
e9ee956e | 4996 | } |
3067714c | 4997 | |
9b8ebbdb | 4998 | if (r == RET_PF_INVALID) { |
7a02674d SC |
4999 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5000 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5001 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5002 | return -EIO; | |
9b8ebbdb PB |
5003 | } |
5004 | ||
3067714c | 5005 | if (r < 0) |
e9ee956e | 5006 | return r; |
83a2ba4c SC |
5007 | if (r != RET_PF_EMULATE) |
5008 | return 1; | |
3067714c | 5009 | |
14727754 TL |
5010 | /* |
5011 | * Before emulating the instruction, check if the error code | |
5012 | * was due to a RO violation while translating the guest page. | |
5013 | * This can occur when using nested virtualization with nested | |
5014 | * paging in both guests. If true, we simply unprotect the page | |
5015 | * and resume the guest. | |
14727754 | 5016 | */ |
44dd3ffa | 5017 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5018 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5019 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5020 | return 1; |
5021 | } | |
5022 | ||
472faffa SC |
5023 | /* |
5024 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5025 | * optimistically try to just unprotect the page and let the processor | |
5026 | * re-execute the instruction that caused the page fault. Do not allow | |
5027 | * retrying MMIO emulation, as it's not only pointless but could also | |
5028 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5029 | * faulting on the non-existent MMIO address. Retrying an instruction |
5030 | * from a nested guest is also pointless and dangerous as we are only | |
5031 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5032 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5033 | */ |
736c291c | 5034 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5035 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5036 | emulate: |
736c291c | 5037 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5038 | insn_len); |
3067714c AK |
5039 | } |
5040 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5041 | ||
5efac074 PB |
5042 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5043 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5044 | { |
b94742c9 | 5045 | int i; |
7eb77e9f | 5046 | |
5efac074 PB |
5047 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5048 | if (mmu != &vcpu->arch.guest_mmu) { | |
5049 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5050 | if (is_noncanonical_address(gva, vcpu)) | |
5051 | return; | |
5052 | ||
5053 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); | |
5054 | } | |
5055 | ||
5056 | if (!mmu->invlpg) | |
faff8758 JS |
5057 | return; |
5058 | ||
5efac074 PB |
5059 | if (root_hpa == INVALID_PAGE) { |
5060 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5061 | |
5efac074 PB |
5062 | /* |
5063 | * INVLPG is required to invalidate any global mappings for the VA, | |
5064 | * irrespective of PCID. Since it would take us roughly similar amount | |
5065 | * of work to determine whether any of the prev_root mappings of the VA | |
5066 | * is marked global, or to just sync it blindly, so we might as well | |
5067 | * just always sync it. | |
5068 | * | |
5069 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5070 | * synced when switching to that cr3, so nothing needs to be done here | |
5071 | * for them. | |
5072 | */ | |
5073 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5074 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5075 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5076 | } else { | |
5077 | mmu->invlpg(vcpu, gva, root_hpa); | |
5078 | } | |
5079 | } | |
5080 | EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva); | |
956bf353 | 5081 | |
5efac074 PB |
5082 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5083 | { | |
5084 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5085 | ++vcpu->stat.invlpg; |
5086 | } | |
5087 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5088 | ||
5efac074 | 5089 | |
eb4b248e JS |
5090 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5091 | { | |
44dd3ffa | 5092 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5093 | bool tlb_flush = false; |
b94742c9 | 5094 | uint i; |
eb4b248e JS |
5095 | |
5096 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5097 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5098 | tlb_flush = true; |
eb4b248e JS |
5099 | } |
5100 | ||
b94742c9 JS |
5101 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5102 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5103 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5104 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5105 | tlb_flush = true; | |
5106 | } | |
956bf353 | 5107 | } |
ade61e28 | 5108 | |
faff8758 | 5109 | if (tlb_flush) |
afaf0b2f | 5110 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); |
faff8758 | 5111 | |
eb4b248e JS |
5112 | ++vcpu->stat.invlpg; |
5113 | ||
5114 | /* | |
b94742c9 JS |
5115 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5116 | * synced when switching to that cr3, so nothing needs to be done here | |
5117 | * for them. | |
eb4b248e JS |
5118 | */ |
5119 | } | |
5120 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5121 | ||
83013059 SC |
5122 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5123 | int tdp_huge_page_level) | |
18552672 | 5124 | { |
bde77235 | 5125 | tdp_enabled = enable_tdp; |
83013059 | 5126 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5127 | |
5128 | /* | |
1d92d2e8 | 5129 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5130 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5131 | * the kernel is not. But, KVM never creates a page size greater than | |
5132 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5133 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5134 | */ | |
5135 | if (tdp_enabled) | |
1d92d2e8 | 5136 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5137 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5138 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5139 | else |
1d92d2e8 | 5140 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5141 | } |
bde77235 | 5142 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5143 | |
5144 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
5145 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); | |
5146 | ||
5147 | /* The caller should hold mmu-lock before calling this function. */ | |
5148 | static __always_inline bool | |
5149 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5150 | slot_level_handler fn, int start_level, int end_level, | |
5151 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5152 | { | |
5153 | struct slot_rmap_walk_iterator iterator; | |
5154 | bool flush = false; | |
5155 | ||
5156 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5157 | end_gfn, &iterator) { | |
5158 | if (iterator.rmap) | |
5159 | flush |= fn(kvm, iterator.rmap); | |
5160 | ||
5161 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5162 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5163 | kvm_flush_remote_tlbs_with_address(kvm, |
5164 | start_gfn, | |
5165 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5166 | flush = false; |
5167 | } | |
5168 | cond_resched_lock(&kvm->mmu_lock); | |
5169 | } | |
5170 | } | |
5171 | ||
5172 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5173 | kvm_flush_remote_tlbs_with_address(kvm, start_gfn, |
5174 | end_gfn - start_gfn + 1); | |
85875a13 SC |
5175 | flush = false; |
5176 | } | |
5177 | ||
5178 | return flush; | |
5179 | } | |
5180 | ||
5181 | static __always_inline bool | |
5182 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5183 | slot_level_handler fn, int start_level, int end_level, | |
5184 | bool lock_flush_tlb) | |
5185 | { | |
5186 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5187 | end_level, memslot->base_gfn, | |
5188 | memslot->base_gfn + memslot->npages - 1, | |
5189 | lock_flush_tlb); | |
5190 | } | |
5191 | ||
5192 | static __always_inline bool | |
5193 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5194 | slot_level_handler fn, bool lock_flush_tlb) | |
5195 | { | |
3bae0459 | 5196 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
e662ec3e | 5197 | KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); |
85875a13 SC |
5198 | } |
5199 | ||
5200 | static __always_inline bool | |
5201 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5202 | slot_level_handler fn, bool lock_flush_tlb) | |
5203 | { | |
3bae0459 | 5204 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1, |
e662ec3e | 5205 | KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); |
85875a13 SC |
5206 | } |
5207 | ||
5208 | static __always_inline bool | |
5209 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5210 | slot_level_handler fn, bool lock_flush_tlb) | |
5211 | { | |
3bae0459 SC |
5212 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
5213 | PG_LEVEL_4K, lock_flush_tlb); | |
85875a13 SC |
5214 | } |
5215 | ||
1cfff4d9 | 5216 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5217 | { |
1cfff4d9 JP |
5218 | free_page((unsigned long)mmu->pae_root); |
5219 | free_page((unsigned long)mmu->lm_root); | |
6aa8b732 AK |
5220 | } |
5221 | ||
04d28e37 | 5222 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5223 | { |
17ac10ad | 5224 | struct page *page; |
6aa8b732 AK |
5225 | int i; |
5226 | ||
04d28e37 SC |
5227 | mmu->root_hpa = INVALID_PAGE; |
5228 | mmu->root_pgd = 0; | |
5229 | mmu->translate_gpa = translate_gpa; | |
5230 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5231 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5232 | ||
17ac10ad | 5233 | /* |
b6b80c78 SC |
5234 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5235 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5236 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5237 | * x86_64. Therefore we need to allocate the PDP table in the first | |
5238 | * 4GB of memory, which happens to fit the DMA32 zone. Except for | |
5239 | * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can | |
5240 | * skip allocating the PDP table. | |
17ac10ad | 5241 | */ |
d468d94b | 5242 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5243 | return 0; |
5244 | ||
254272ce | 5245 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5246 | if (!page) |
d7fa6ab2 WY |
5247 | return -ENOMEM; |
5248 | ||
1cfff4d9 | 5249 | mmu->pae_root = page_address(page); |
17ac10ad | 5250 | for (i = 0; i < 4; ++i) |
1cfff4d9 | 5251 | mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5252 | |
6aa8b732 | 5253 | return 0; |
6aa8b732 AK |
5254 | } |
5255 | ||
8018c27b | 5256 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5257 | { |
1cfff4d9 | 5258 | int ret; |
b94742c9 | 5259 | |
5962bfb7 | 5260 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5261 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5262 | ||
5962bfb7 | 5263 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5264 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5265 | |
96880883 SC |
5266 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5267 | ||
44dd3ffa VK |
5268 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5269 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5270 | |
14c07ad8 | 5271 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5272 | |
04d28e37 | 5273 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5274 | if (ret) |
5275 | return ret; | |
5276 | ||
04d28e37 | 5277 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5278 | if (ret) |
5279 | goto fail_allocate_root; | |
5280 | ||
5281 | return ret; | |
5282 | fail_allocate_root: | |
5283 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5284 | return ret; | |
6aa8b732 AK |
5285 | } |
5286 | ||
fbb158cb | 5287 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5288 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5289 | { | |
5290 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5291 | int nr_zapped, batch = 0; |
002c5f73 SC |
5292 | |
5293 | restart: | |
5294 | list_for_each_entry_safe_reverse(sp, node, | |
5295 | &kvm->arch.active_mmu_pages, link) { | |
5296 | /* | |
5297 | * No obsolete valid page exists before a newly created page | |
5298 | * since active_mmu_pages is a FIFO list. | |
5299 | */ | |
5300 | if (!is_obsolete_sp(kvm, sp)) | |
5301 | break; | |
5302 | ||
5303 | /* | |
f95eec9b SC |
5304 | * Invalid pages should never land back on the list of active |
5305 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5306 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5307 | */ |
f95eec9b | 5308 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5309 | continue; |
5310 | ||
4506ecf4 SC |
5311 | /* |
5312 | * No need to flush the TLB since we're only zapping shadow | |
5313 | * pages with an obsolete generation number and all vCPUS have | |
5314 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5315 | * be in active use by the guest. | |
5316 | */ | |
fbb158cb | 5317 | if (batch >= BATCH_ZAP_PAGES && |
4506ecf4 | 5318 | cond_resched_lock(&kvm->mmu_lock)) { |
fbb158cb | 5319 | batch = 0; |
002c5f73 SC |
5320 | goto restart; |
5321 | } | |
5322 | ||
10605204 SC |
5323 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5324 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5325 | batch += nr_zapped; |
002c5f73 | 5326 | goto restart; |
fbb158cb | 5327 | } |
002c5f73 SC |
5328 | } |
5329 | ||
4506ecf4 SC |
5330 | /* |
5331 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5332 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5333 | * may reference the pages. | |
5334 | */ | |
10605204 | 5335 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5336 | } |
5337 | ||
5338 | /* | |
5339 | * Fast invalidate all shadow pages and use lock-break technique | |
5340 | * to zap obsolete pages. | |
5341 | * | |
5342 | * It's required when memslot is being deleted or VM is being | |
5343 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5344 | * not use any resource of the being-deleted slot or all slots | |
5345 | * after calling the function. | |
5346 | */ | |
5347 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5348 | { | |
ca333add SC |
5349 | lockdep_assert_held(&kvm->slots_lock); |
5350 | ||
002c5f73 | 5351 | spin_lock(&kvm->mmu_lock); |
14a3c4f4 | 5352 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5353 | |
5354 | /* | |
5355 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5356 | * held for the entire duration of zapping obsolete pages, it's | |
5357 | * impossible for there to be multiple invalid generations associated | |
5358 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5359 | * one valid generation and (at most) one invalid generation. | |
5360 | */ | |
5361 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5362 | |
4506ecf4 SC |
5363 | /* |
5364 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5365 | * Then all vcpus will switch to new shadow page table with the new | |
5366 | * mmu_valid_gen. | |
5367 | * | |
5368 | * Note: we need to do this under the protection of mmu_lock, | |
5369 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5370 | */ | |
5371 | kvm_reload_remote_mmus(kvm); | |
5372 | ||
002c5f73 SC |
5373 | kvm_zap_obsolete_pages(kvm); |
5374 | spin_unlock(&kvm->mmu_lock); | |
5375 | } | |
5376 | ||
10605204 SC |
5377 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5378 | { | |
5379 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5380 | } | |
5381 | ||
b5f5fdca | 5382 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5383 | struct kvm_memory_slot *slot, |
5384 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5385 | { |
002c5f73 | 5386 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5387 | } |
5388 | ||
13d268ca | 5389 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5390 | { |
13d268ca | 5391 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5392 | |
fe5db27d BG |
5393 | kvm_mmu_init_tdp_mmu(kvm); |
5394 | ||
13d268ca | 5395 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5396 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5397 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5398 | } |
5399 | ||
13d268ca | 5400 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5401 | { |
13d268ca | 5402 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5403 | |
13d268ca | 5404 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5405 | |
5406 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5407 | } |
5408 | ||
efdfe536 XG |
5409 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5410 | { | |
5411 | struct kvm_memslots *slots; | |
5412 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5413 | int i; |
efdfe536 XG |
5414 | |
5415 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5416 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5417 | slots = __kvm_memslots(kvm, i); | |
5418 | kvm_for_each_memslot(memslot, slots) { | |
5419 | gfn_t start, end; | |
5420 | ||
5421 | start = max(gfn_start, memslot->base_gfn); | |
5422 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5423 | if (start >= end) | |
5424 | continue; | |
efdfe536 | 5425 | |
92da008f | 5426 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
3bae0459 | 5427 | PG_LEVEL_4K, |
e662ec3e | 5428 | KVM_MAX_HUGEPAGE_LEVEL, |
92da008f | 5429 | start, end - 1, true); |
9da0e4d5 | 5430 | } |
efdfe536 XG |
5431 | } |
5432 | ||
5433 | spin_unlock(&kvm->mmu_lock); | |
5434 | } | |
5435 | ||
018aabb5 TY |
5436 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5437 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5438 | { |
018aabb5 | 5439 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5440 | } |
5441 | ||
1c91cad4 | 5442 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5443 | struct kvm_memory_slot *memslot, |
5444 | int start_level) | |
6aa8b732 | 5445 | { |
d77aa73c | 5446 | bool flush; |
6aa8b732 | 5447 | |
9d1beefb | 5448 | spin_lock(&kvm->mmu_lock); |
3c9bd400 | 5449 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, |
e662ec3e | 5450 | start_level, KVM_MAX_HUGEPAGE_LEVEL, false); |
9d1beefb | 5451 | spin_unlock(&kvm->mmu_lock); |
198c74f4 | 5452 | |
198c74f4 XG |
5453 | /* |
5454 | * We can flush all the TLBs out of the mmu lock without TLB | |
5455 | * corruption since we just change the spte from writable to | |
5456 | * readonly so that we only need to care the case of changing | |
5457 | * spte from present to present (changing the spte from present | |
5458 | * to nonpresent will flush all the TLBs immediately), in other | |
5459 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5460 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5461 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5462 | * on PT_WRITABLE_MASK anymore. | |
5463 | */ | |
d91ffee9 | 5464 | if (flush) |
7f42aa76 | 5465 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5466 | } |
37a7d8b0 | 5467 | |
3ea3b7fa | 5468 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5469 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5470 | { |
5471 | u64 *sptep; | |
5472 | struct rmap_iterator iter; | |
5473 | int need_tlb_flush = 0; | |
ba049e93 | 5474 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5475 | struct kvm_mmu_page *sp; |
5476 | ||
0d536790 | 5477 | restart: |
018aabb5 | 5478 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5479 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5480 | pfn = spte_to_pfn(*sptep); |
5481 | ||
5482 | /* | |
decf6333 XG |
5483 | * We cannot do huge page mapping for indirect shadow pages, |
5484 | * which are found on the last rmap (level = 1) when not using | |
5485 | * tdp; such shadow pages are synced with the page table in | |
5486 | * the guest, and the guest page table is using 4K page size | |
5487 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5488 | */ |
a78986aa | 5489 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
e851265a SC |
5490 | (kvm_is_zone_device_pfn(pfn) || |
5491 | PageCompound(pfn_to_page(pfn)))) { | |
e7912386 | 5492 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5493 | |
5494 | if (kvm_available_flush_tlb_with_range()) | |
5495 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5496 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5497 | else | |
5498 | need_tlb_flush = 1; | |
5499 | ||
0d536790 XG |
5500 | goto restart; |
5501 | } | |
3ea3b7fa WL |
5502 | } |
5503 | ||
5504 | return need_tlb_flush; | |
5505 | } | |
5506 | ||
5507 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5508 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5509 | { |
f36f3f28 | 5510 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5511 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5512 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5513 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5514 | spin_unlock(&kvm->mmu_lock); |
5515 | } | |
5516 | ||
b3594ffb SC |
5517 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
5518 | struct kvm_memory_slot *memslot) | |
5519 | { | |
5520 | /* | |
7f42aa76 SC |
5521 | * All current use cases for flushing the TLBs for a specific memslot |
5522 | * are related to dirty logging, and do the TLB flush out of mmu_lock. | |
5523 | * The interaction between the various operations on memslot must be | |
5524 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5525 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5526 | */ |
5527 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5528 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5529 | memslot->npages); | |
b3594ffb SC |
5530 | } |
5531 | ||
f4b4b180 KH |
5532 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5533 | struct kvm_memory_slot *memslot) | |
5534 | { | |
d77aa73c | 5535 | bool flush; |
f4b4b180 KH |
5536 | |
5537 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5538 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5539 | spin_unlock(&kvm->mmu_lock); |
5540 | ||
f4b4b180 KH |
5541 | /* |
5542 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5543 | * function is only used for dirty logging, in which case flushing TLB | |
5544 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5545 | * dirty_bitmap. | |
5546 | */ | |
5547 | if (flush) | |
7f42aa76 | 5548 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5549 | } |
5550 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5551 | ||
5552 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5553 | struct kvm_memory_slot *memslot) | |
5554 | { | |
d77aa73c | 5555 | bool flush; |
f4b4b180 KH |
5556 | |
5557 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5558 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5559 | false); | |
f4b4b180 KH |
5560 | spin_unlock(&kvm->mmu_lock); |
5561 | ||
f4b4b180 | 5562 | if (flush) |
7f42aa76 | 5563 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5564 | } |
5565 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5566 | ||
5567 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5568 | struct kvm_memory_slot *memslot) | |
5569 | { | |
d77aa73c | 5570 | bool flush; |
f4b4b180 KH |
5571 | |
5572 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5573 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5574 | spin_unlock(&kvm->mmu_lock); |
5575 | ||
f4b4b180 | 5576 | if (flush) |
7f42aa76 | 5577 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5578 | } |
5579 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5580 | ||
92f58b5c | 5581 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5582 | { |
5583 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5584 | LIST_HEAD(invalid_list); |
83cdb568 | 5585 | int ign; |
5304b8d3 | 5586 | |
7390de1e | 5587 | spin_lock(&kvm->mmu_lock); |
5304b8d3 | 5588 | restart: |
8a674adc | 5589 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5590 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5591 | continue; |
92f58b5c | 5592 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5593 | goto restart; |
24efe61f | 5594 | if (cond_resched_lock(&kvm->mmu_lock)) |
5304b8d3 XG |
5595 | goto restart; |
5596 | } | |
5597 | ||
4771450c | 5598 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
5304b8d3 XG |
5599 | spin_unlock(&kvm->mmu_lock); |
5600 | } | |
5601 | ||
15248258 | 5602 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5603 | { |
164bf7e5 | 5604 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5605 | |
164bf7e5 | 5606 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5607 | |
f8f55942 | 5608 | /* |
e1359e2b SC |
5609 | * Generation numbers are incremented in multiples of the number of |
5610 | * address spaces in order to provide unique generations across all | |
5611 | * address spaces. Strip what is effectively the address space | |
5612 | * modifier prior to checking for a wrap of the MMIO generation so | |
5613 | * that a wrap in any address space is detected. | |
5614 | */ | |
5615 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5616 | ||
f8f55942 | 5617 | /* |
e1359e2b | 5618 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5619 | * zap all shadow pages. |
f8f55942 | 5620 | */ |
e1359e2b | 5621 | if (unlikely(gen == 0)) { |
ae0f5499 | 5622 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5623 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5624 | } |
f8f55942 XG |
5625 | } |
5626 | ||
70534a73 DC |
5627 | static unsigned long |
5628 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5629 | { |
5630 | struct kvm *kvm; | |
1495f230 | 5631 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5632 | unsigned long freed = 0; |
3ee16c81 | 5633 | |
0d9ce162 | 5634 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5635 | |
5636 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5637 | int idx; |
d98ba053 | 5638 | LIST_HEAD(invalid_list); |
3ee16c81 | 5639 | |
35f2d16b TY |
5640 | /* |
5641 | * Never scan more than sc->nr_to_scan VM instances. | |
5642 | * Will not hit this condition practically since we do not try | |
5643 | * to shrink more than one VM and it is very unlikely to see | |
5644 | * !n_used_mmu_pages so many times. | |
5645 | */ | |
5646 | if (!nr_to_scan--) | |
5647 | break; | |
19526396 GN |
5648 | /* |
5649 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5650 | * here. We may skip a VM instance errorneosly, but we do not | |
5651 | * want to shrink a VM that only started to populate its MMU | |
5652 | * anyway. | |
5653 | */ | |
10605204 SC |
5654 | if (!kvm->arch.n_used_mmu_pages && |
5655 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5656 | continue; |
19526396 | 5657 | |
f656ce01 | 5658 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5659 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5660 | |
10605204 SC |
5661 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5662 | kvm_mmu_commit_zap_page(kvm, | |
5663 | &kvm->arch.zapped_obsolete_pages); | |
5664 | goto unlock; | |
5665 | } | |
5666 | ||
ebdb292d | 5667 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5668 | |
10605204 | 5669 | unlock: |
3ee16c81 | 5670 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5671 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5672 | |
70534a73 DC |
5673 | /* |
5674 | * unfair on small ones | |
5675 | * per-vm shrinkers cry out | |
5676 | * sadness comes quickly | |
5677 | */ | |
19526396 GN |
5678 | list_move_tail(&kvm->vm_list, &vm_list); |
5679 | break; | |
3ee16c81 | 5680 | } |
3ee16c81 | 5681 | |
0d9ce162 | 5682 | mutex_unlock(&kvm_lock); |
70534a73 | 5683 | return freed; |
70534a73 DC |
5684 | } |
5685 | ||
5686 | static unsigned long | |
5687 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5688 | { | |
45221ab6 | 5689 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5690 | } |
5691 | ||
5692 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5693 | .count_objects = mmu_shrink_count, |
5694 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5695 | .seeks = DEFAULT_SEEKS * 10, |
5696 | }; | |
5697 | ||
2ddfd20e | 5698 | static void mmu_destroy_caches(void) |
b5a33a75 | 5699 | { |
c1bd743e TH |
5700 | kmem_cache_destroy(pte_list_desc_cache); |
5701 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5702 | } |
5703 | ||
7b6f8a06 KH |
5704 | static void kvm_set_mmio_spte_mask(void) |
5705 | { | |
5706 | u64 mask; | |
7b6f8a06 KH |
5707 | |
5708 | /* | |
6129ed87 SC |
5709 | * Set a reserved PA bit in MMIO SPTEs to generate page faults with |
5710 | * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT | |
5711 | * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports | |
5712 | * 52-bit physical addresses then there are no reserved PA bits in the | |
5713 | * PTEs and so the reserved PA approach must be disabled. | |
7b6f8a06 | 5714 | */ |
6129ed87 SC |
5715 | if (shadow_phys_bits < 52) |
5716 | mask = BIT_ULL(51) | PT_PRESENT_MASK; | |
5717 | else | |
5718 | mask = 0; | |
7b6f8a06 | 5719 | |
e7581cac | 5720 | kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK); |
7b6f8a06 KH |
5721 | } |
5722 | ||
b8e8c830 PB |
5723 | static bool get_nx_auto_mode(void) |
5724 | { | |
5725 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5726 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5727 | } | |
5728 | ||
5729 | static void __set_nx_huge_pages(bool val) | |
5730 | { | |
5731 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5732 | } | |
5733 | ||
5734 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5735 | { | |
5736 | bool old_val = nx_huge_pages; | |
5737 | bool new_val; | |
5738 | ||
5739 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5740 | if (sysfs_streq(val, "off")) | |
5741 | new_val = 0; | |
5742 | else if (sysfs_streq(val, "force")) | |
5743 | new_val = 1; | |
5744 | else if (sysfs_streq(val, "auto")) | |
5745 | new_val = get_nx_auto_mode(); | |
5746 | else if (strtobool(val, &new_val) < 0) | |
5747 | return -EINVAL; | |
5748 | ||
5749 | __set_nx_huge_pages(new_val); | |
5750 | ||
5751 | if (new_val != old_val) { | |
5752 | struct kvm *kvm; | |
b8e8c830 PB |
5753 | |
5754 | mutex_lock(&kvm_lock); | |
5755 | ||
5756 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 5757 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 5758 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 5759 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
5760 | |
5761 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
5762 | } |
5763 | mutex_unlock(&kvm_lock); | |
5764 | } | |
5765 | ||
5766 | return 0; | |
5767 | } | |
5768 | ||
b5a33a75 AK |
5769 | int kvm_mmu_module_init(void) |
5770 | { | |
ab271bd4 AB |
5771 | int ret = -ENOMEM; |
5772 | ||
b8e8c830 PB |
5773 | if (nx_huge_pages == -1) |
5774 | __set_nx_huge_pages(get_nx_auto_mode()); | |
5775 | ||
36d9594d VK |
5776 | /* |
5777 | * MMU roles use union aliasing which is, generally speaking, an | |
5778 | * undefined behavior. However, we supposedly know how compilers behave | |
5779 | * and the current status quo is unlikely to change. Guardians below are | |
5780 | * supposed to let us know if the assumption becomes false. | |
5781 | */ | |
5782 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
5783 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
5784 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
5785 | ||
28a1f3ac | 5786 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 5787 | |
7b6f8a06 KH |
5788 | kvm_set_mmio_spte_mask(); |
5789 | ||
53c07b18 XG |
5790 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5791 | sizeof(struct pte_list_desc), | |
46bea48a | 5792 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5793 | if (!pte_list_desc_cache) |
ab271bd4 | 5794 | goto out; |
b5a33a75 | 5795 | |
d3d25b04 AK |
5796 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5797 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5798 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5799 | if (!mmu_page_header_cache) |
ab271bd4 | 5800 | goto out; |
d3d25b04 | 5801 | |
908c7f19 | 5802 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5803 | goto out; |
45bf21a8 | 5804 | |
ab271bd4 AB |
5805 | ret = register_shrinker(&mmu_shrinker); |
5806 | if (ret) | |
5807 | goto out; | |
3ee16c81 | 5808 | |
b5a33a75 AK |
5809 | return 0; |
5810 | ||
ab271bd4 | 5811 | out: |
3ee16c81 | 5812 | mmu_destroy_caches(); |
ab271bd4 | 5813 | return ret; |
b5a33a75 AK |
5814 | } |
5815 | ||
3ad82a7e | 5816 | /* |
39337ad1 | 5817 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 5818 | */ |
bc8a3d89 | 5819 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 5820 | { |
bc8a3d89 BG |
5821 | unsigned long nr_mmu_pages; |
5822 | unsigned long nr_pages = 0; | |
bc6678a3 | 5823 | struct kvm_memslots *slots; |
be6ba0f0 | 5824 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5825 | int i; |
3ad82a7e | 5826 | |
9da0e4d5 PB |
5827 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5828 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5829 | |
9da0e4d5 PB |
5830 | kvm_for_each_memslot(memslot, slots) |
5831 | nr_pages += memslot->npages; | |
5832 | } | |
3ad82a7e ZX |
5833 | |
5834 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 5835 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5836 | |
5837 | return nr_mmu_pages; | |
5838 | } | |
5839 | ||
c42fffe3 XG |
5840 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5841 | { | |
95f93af4 | 5842 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
5843 | free_mmu_pages(&vcpu->arch.root_mmu); |
5844 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 5845 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
5846 | } |
5847 | ||
b034cf01 XG |
5848 | void kvm_mmu_module_exit(void) |
5849 | { | |
5850 | mmu_destroy_caches(); | |
5851 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5852 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5853 | mmu_audit_disable(); |
5854 | } | |
1aa9b957 JS |
5855 | |
5856 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
5857 | { | |
5858 | unsigned int old_val; | |
5859 | int err; | |
5860 | ||
5861 | old_val = nx_huge_pages_recovery_ratio; | |
5862 | err = param_set_uint(val, kp); | |
5863 | if (err) | |
5864 | return err; | |
5865 | ||
5866 | if (READ_ONCE(nx_huge_pages) && | |
5867 | !old_val && nx_huge_pages_recovery_ratio) { | |
5868 | struct kvm *kvm; | |
5869 | ||
5870 | mutex_lock(&kvm_lock); | |
5871 | ||
5872 | list_for_each_entry(kvm, &vm_list, vm_list) | |
5873 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
5874 | ||
5875 | mutex_unlock(&kvm_lock); | |
5876 | } | |
5877 | ||
5878 | return err; | |
5879 | } | |
5880 | ||
5881 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
5882 | { | |
5883 | int rcu_idx; | |
5884 | struct kvm_mmu_page *sp; | |
5885 | unsigned int ratio; | |
5886 | LIST_HEAD(invalid_list); | |
5887 | ulong to_zap; | |
5888 | ||
5889 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
5890 | spin_lock(&kvm->mmu_lock); | |
5891 | ||
5892 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
5893 | to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0; | |
7d919c7a SC |
5894 | for ( ; to_zap; --to_zap) { |
5895 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
5896 | break; | |
5897 | ||
1aa9b957 JS |
5898 | /* |
5899 | * We use a separate list instead of just using active_mmu_pages | |
5900 | * because the number of lpage_disallowed pages is expected to | |
5901 | * be relatively small compared to the total. | |
5902 | */ | |
5903 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
5904 | struct kvm_mmu_page, | |
5905 | lpage_disallowed_link); | |
5906 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
5907 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); | |
5908 | WARN_ON_ONCE(sp->lpage_disallowed); | |
5909 | ||
7d919c7a | 5910 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { |
1aa9b957 | 5911 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
7d919c7a | 5912 | cond_resched_lock(&kvm->mmu_lock); |
1aa9b957 JS |
5913 | } |
5914 | } | |
e8950569 | 5915 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1aa9b957 JS |
5916 | |
5917 | spin_unlock(&kvm->mmu_lock); | |
5918 | srcu_read_unlock(&kvm->srcu, rcu_idx); | |
5919 | } | |
5920 | ||
5921 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
5922 | { | |
5923 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
5924 | ? start_time + 60 * HZ - get_jiffies_64() | |
5925 | : MAX_SCHEDULE_TIMEOUT; | |
5926 | } | |
5927 | ||
5928 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
5929 | { | |
5930 | u64 start_time; | |
5931 | long remaining_time; | |
5932 | ||
5933 | while (true) { | |
5934 | start_time = get_jiffies_64(); | |
5935 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
5936 | ||
5937 | set_current_state(TASK_INTERRUPTIBLE); | |
5938 | while (!kthread_should_stop() && remaining_time > 0) { | |
5939 | schedule_timeout(remaining_time); | |
5940 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
5941 | set_current_state(TASK_INTERRUPTIBLE); | |
5942 | } | |
5943 | ||
5944 | set_current_state(TASK_RUNNING); | |
5945 | ||
5946 | if (kthread_should_stop()) | |
5947 | return 0; | |
5948 | ||
5949 | kvm_recover_nx_lpages(kvm); | |
5950 | } | |
5951 | } | |
5952 | ||
5953 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
5954 | { | |
5955 | int err; | |
5956 | ||
5957 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
5958 | "kvm-nx-lpage-recovery", | |
5959 | &kvm->arch.nx_lpage_recovery_thread); | |
5960 | if (!err) | |
5961 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
5962 | ||
5963 | return err; | |
5964 | } | |
5965 | ||
5966 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
5967 | { | |
5968 | if (kvm->arch.nx_lpage_recovery_thread) | |
5969 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
5970 | } |