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KVM: x86/mmu: Optimize MMU page cache lookup for fully direct MMUs
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CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
9611c187 11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
6aa8b732 16 */
e495606d 17
af585b92 18#include "irq.h"
88197e6a 19#include "ioapic.h"
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
2f728d66 23#include "kvm_emulate.h"
5f7dde7b 24#include "cpuid.h"
e495606d 25
edf88417 26#include <linux/kvm_host.h>
6aa8b732
AK
27#include <linux/types.h>
28#include <linux/string.h>
6aa8b732
AK
29#include <linux/mm.h>
30#include <linux/highmem.h>
1767e931
PG
31#include <linux/moduleparam.h>
32#include <linux/export.h>
448353ca 33#include <linux/swap.h>
05da4558 34#include <linux/hugetlb.h>
2f333bcb 35#include <linux/compiler.h>
bc6678a3 36#include <linux/srcu.h>
5a0e3ad6 37#include <linux/slab.h>
3f07c014 38#include <linux/sched/signal.h>
bf998156 39#include <linux/uaccess.h>
114df303 40#include <linux/hash.h>
f160c7b7 41#include <linux/kern_levels.h>
1aa9b957 42#include <linux/kthread.h>
6aa8b732 43
e495606d 44#include <asm/page.h>
eb243d1d 45#include <asm/memtype.h>
e495606d 46#include <asm/cmpxchg.h>
0c55671f 47#include <asm/e820/api.h>
4e542370 48#include <asm/io.h>
13673a90 49#include <asm/vmx.h>
3d0c27ad 50#include <asm/kvm_page_track.h>
1261bfa3 51#include "trace.h"
6aa8b732 52
b8e8c830
PB
53extern bool itlb_multihit_kvm_mitigation;
54
55static int __read_mostly nx_huge_pages = -1;
13fb5927
PB
56#ifdef CONFIG_PREEMPT_RT
57/* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
58static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
59#else
1aa9b957 60static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
13fb5927 61#endif
b8e8c830
PB
62
63static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
1aa9b957 64static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
b8e8c830
PB
65
66static struct kernel_param_ops nx_huge_pages_ops = {
67 .set = set_nx_huge_pages,
68 .get = param_get_bool,
69};
70
1aa9b957
JS
71static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
72 .set = set_nx_huge_pages_recovery_ratio,
73 .get = param_get_uint,
74};
75
b8e8c830
PB
76module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
77__MODULE_PARM_TYPE(nx_huge_pages, "bool");
1aa9b957
JS
78module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
79 &nx_huge_pages_recovery_ratio, 0644);
80__MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
b8e8c830 81
71fe7013
SC
82static bool __read_mostly force_flush_and_sync_on_reuse;
83module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
84
18552672
JR
85/*
86 * When setting this variable to true it enables Two-Dimensional-Paging
87 * where the hardware walks 2 page tables:
88 * 1. the guest-virtual to guest-physical
89 * 2. while doing 1. it walks guest-physical to host-physical
90 * If the hardware supports that we don't need to do shadow paging.
91 */
2f333bcb 92bool tdp_enabled = false;
18552672 93
703c335d
SC
94static int max_page_level __read_mostly;
95
8b1fe17c
XG
96enum {
97 AUDIT_PRE_PAGE_FAULT,
98 AUDIT_POST_PAGE_FAULT,
99 AUDIT_PRE_PTE_WRITE,
6903074c
XG
100 AUDIT_POST_PTE_WRITE,
101 AUDIT_PRE_SYNC,
102 AUDIT_POST_SYNC
8b1fe17c 103};
37a7d8b0 104
8b1fe17c 105#undef MMU_DEBUG
37a7d8b0
AK
106
107#ifdef MMU_DEBUG
fa4a2c08
PB
108static bool dbg = 0;
109module_param(dbg, bool, 0644);
37a7d8b0
AK
110
111#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
112#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
fa4a2c08 113#define MMU_WARN_ON(x) WARN_ON(x)
37a7d8b0 114#else
37a7d8b0
AK
115#define pgprintk(x...) do { } while (0)
116#define rmap_printk(x...) do { } while (0)
fa4a2c08 117#define MMU_WARN_ON(x) do { } while (0)
d6c69ee9 118#endif
6aa8b732 119
957ed9ef
XG
120#define PTE_PREFETCH_NUM 8
121
00763e41 122#define PT_FIRST_AVAIL_BITS_SHIFT 10
6eeb4ef0
PB
123#define PT64_SECOND_AVAIL_BITS_SHIFT 54
124
125/*
126 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
127 * Access Tracking SPTEs.
128 */
129#define SPTE_SPECIAL_MASK (3ULL << 52)
130#define SPTE_AD_ENABLED_MASK (0ULL << 52)
131#define SPTE_AD_DISABLED_MASK (1ULL << 52)
1f4e5fc8 132#define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
6eeb4ef0 133#define SPTE_MMIO_MASK (3ULL << 52)
6aa8b732 134
6aa8b732
AK
135#define PT64_LEVEL_BITS 9
136
137#define PT64_LEVEL_SHIFT(level) \
d77c26fc 138 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732 139
6aa8b732
AK
140#define PT64_INDEX(address, level)\
141 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
142
143
144#define PT32_LEVEL_BITS 10
145
146#define PT32_LEVEL_SHIFT(level) \
d77c26fc 147 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732 148
e04da980
JR
149#define PT32_LVL_OFFSET_MASK(level) \
150 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
151 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK
152
153#define PT32_INDEX(address, level)\
154 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
155
156
8acc0993
KH
157#ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
158#define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
159#else
160#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
161#endif
e04da980
JR
162#define PT64_LVL_ADDR_MASK(level) \
163 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
164 * PT64_LEVEL_BITS))) - 1))
165#define PT64_LVL_OFFSET_MASK(level) \
166 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
167 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK
168
169#define PT32_BASE_ADDR_MASK PAGE_MASK
170#define PT32_DIR_BASE_ADDR_MASK \
171 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR
172#define PT32_LVL_ADDR_MASK(level) \
173 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
174 * PT32_LEVEL_BITS))) - 1))
6aa8b732 175
53166229 176#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
d0ec49d4 177 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
6aa8b732 178
fe135d2c
AK
179#define ACC_EXEC_MASK 1
180#define ACC_WRITE_MASK PT_WRITABLE_MASK
181#define ACC_USER_MASK PT_USER_MASK
182#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
183
f160c7b7
JS
184/* The mask for the R/X bits in EPT PTEs */
185#define PT64_EPT_READABLE_MASK 0x1ull
186#define PT64_EPT_EXECUTABLE_MASK 0x4ull
187
90bb6fc5
AK
188#include <trace/events/kvm.h>
189
49fde340
XG
190#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
191#define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
1403283a 192
135f8c2b
AK
193#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
194
220f773a
TY
195/* make pte_list_desc fit well in cache line */
196#define PTE_LIST_EXT 3
197
9b8ebbdb
PB
198/*
199 * Return values of handle_mmio_page_fault and mmu.page_fault:
200 * RET_PF_RETRY: let CPU fault again on the address.
201 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
202 *
203 * For handle_mmio_page_fault only:
204 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
205 */
206enum {
207 RET_PF_RETRY = 0,
208 RET_PF_EMULATE = 1,
209 RET_PF_INVALID = 2,
210};
211
53c07b18
XG
212struct pte_list_desc {
213 u64 *sptes[PTE_LIST_EXT];
214 struct pte_list_desc *more;
cd4a4e53
AK
215};
216
2d11123a
AK
217struct kvm_shadow_walk_iterator {
218 u64 addr;
219 hpa_t shadow_addr;
2d11123a 220 u64 *sptep;
dd3bfd59 221 int level;
2d11123a
AK
222 unsigned index;
223};
224
7eb77e9f
JS
225#define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
226 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
227 (_root), (_addr)); \
228 shadow_walk_okay(&(_walker)); \
229 shadow_walk_next(&(_walker)))
230
231#define for_each_shadow_entry(_vcpu, _addr, _walker) \
2d11123a
AK
232 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
233 shadow_walk_okay(&(_walker)); \
234 shadow_walk_next(&(_walker)))
235
c2a2ac2b
XG
236#define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
237 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
238 shadow_walk_okay(&(_walker)) && \
239 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
240 __shadow_walk_next(&(_walker), spte))
241
53c07b18 242static struct kmem_cache *pte_list_desc_cache;
d3d25b04 243static struct kmem_cache *mmu_page_header_cache;
45221ab6 244static struct percpu_counter kvm_total_used_mmu_pages;
b5a33a75 245
7b52345e
SY
246static u64 __read_mostly shadow_nx_mask;
247static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
248static u64 __read_mostly shadow_user_mask;
249static u64 __read_mostly shadow_accessed_mask;
250static u64 __read_mostly shadow_dirty_mask;
dcdca5fe 251static u64 __read_mostly shadow_mmio_value;
4af77151 252static u64 __read_mostly shadow_mmio_access_mask;
ffb128c8 253static u64 __read_mostly shadow_present_mask;
d0ec49d4 254static u64 __read_mostly shadow_me_mask;
ce88decf 255
f160c7b7 256/*
6eeb4ef0
PB
257 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
258 * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
259 * pages.
f160c7b7
JS
260 */
261static u64 __read_mostly shadow_acc_track_mask;
f160c7b7
JS
262
263/*
264 * The mask/shift to use for saving the original R/X bits when marking the PTE
265 * as not-present for access tracking purposes. We do not save the W bit as the
266 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
267 * restored only when a write is attempted to the page.
268 */
269static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
270 PT64_EPT_EXECUTABLE_MASK;
271static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
272
28a1f3ac
JS
273/*
274 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
275 * to guard against L1TF attacks.
276 */
277static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
278
279/*
280 * The number of high-order 1 bits to use in the mask above.
281 */
282static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
283
daa07cbc
SC
284/*
285 * In some cases, we need to preserve the GFN of a non-present or reserved
286 * SPTE when we usurp the upper five bits of the physical address space to
287 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
288 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
289 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
290 * high and low parts. This mask covers the lower bits of the GFN.
291 */
292static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
293
f3ecb59d
KH
294/*
295 * The number of non-reserved physical address bits irrespective of features
296 * that repurpose legal bits, e.g. MKTME.
297 */
298static u8 __read_mostly shadow_phys_bits;
daa07cbc 299
ce88decf 300static void mmu_spte_set(u64 *sptep, u64 spte);
335e192a 301static bool is_executable_pte(u64 spte);
9fa72119
JS
302static union kvm_mmu_page_role
303kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
ce88decf 304
335e192a
PB
305#define CREATE_TRACE_POINTS
306#include "mmutrace.h"
307
40ef75a7
LT
308
309static inline bool kvm_available_flush_tlb_with_range(void)
310{
afaf0b2f 311 return kvm_x86_ops.tlb_remote_flush_with_range;
40ef75a7
LT
312}
313
314static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
315 struct kvm_tlb_range *range)
316{
317 int ret = -ENOTSUPP;
318
afaf0b2f
SC
319 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
320 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
40ef75a7
LT
321
322 if (ret)
323 kvm_flush_remote_tlbs(kvm);
324}
325
326static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
327 u64 start_gfn, u64 pages)
328{
329 struct kvm_tlb_range range;
330
331 range.start_gfn = start_gfn;
332 range.pages = pages;
333
334 kvm_flush_remote_tlbs_with_range(kvm, &range);
335}
336
e7581cac 337void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 access_mask)
ce88decf 338{
4af77151 339 BUG_ON((u64)(unsigned)access_mask != access_mask);
d43e2675
PB
340 WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << shadow_nonpresent_or_rsvd_mask_len));
341 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);
6eeb4ef0 342 shadow_mmio_value = mmio_value | SPTE_MMIO_MASK;
4af77151 343 shadow_mmio_access_mask = access_mask;
ce88decf
XG
344}
345EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
346
26c44a63
SC
347static bool is_mmio_spte(u64 spte)
348{
e7581cac 349 return (spte & SPTE_SPECIAL_MASK) == SPTE_MMIO_MASK;
26c44a63
SC
350}
351
ac8d57e5
PF
352static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
353{
354 return sp->role.ad_disabled;
355}
356
1f4e5fc8
PB
357static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
358{
359 /*
360 * When using the EPT page-modification log, the GPAs in the log
361 * would come from L2 rather than L1. Therefore, we need to rely
362 * on write protection to record dirty pages. This also bypasses
363 * PML, since writes now result in a vmexit.
364 */
365 return vcpu->arch.mmu == &vcpu->arch.guest_mmu;
366}
367
ac8d57e5
PF
368static inline bool spte_ad_enabled(u64 spte)
369{
26c44a63 370 MMU_WARN_ON(is_mmio_spte(spte));
1f4e5fc8
PB
371 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK;
372}
373
374static inline bool spte_ad_need_write_protect(u64 spte)
375{
376 MMU_WARN_ON(is_mmio_spte(spte));
377 return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK;
ac8d57e5
PF
378}
379
b8e8c830
PB
380static bool is_nx_huge_page_enabled(void)
381{
382 return READ_ONCE(nx_huge_pages);
383}
384
ac8d57e5
PF
385static inline u64 spte_shadow_accessed_mask(u64 spte)
386{
26c44a63 387 MMU_WARN_ON(is_mmio_spte(spte));
ac8d57e5
PF
388 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
389}
390
391static inline u64 spte_shadow_dirty_mask(u64 spte)
392{
26c44a63 393 MMU_WARN_ON(is_mmio_spte(spte));
ac8d57e5
PF
394 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
395}
396
f160c7b7
JS
397static inline bool is_access_track_spte(u64 spte)
398{
ac8d57e5 399 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
f160c7b7
JS
400}
401
f2fd125d 402/*
cae7ed3c
SC
403 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
404 * the memslots generation and is derived as follows:
ee3d1570 405 *
164bf7e5
SC
406 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
407 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
cae7ed3c 408 *
164bf7e5
SC
409 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
410 * the MMIO generation number, as doing so would require stealing a bit from
411 * the "real" generation number and thus effectively halve the maximum number
412 * of MMIO generations that can be handled before encountering a wrap (which
413 * requires a full MMU zap). The flag is instead explicitly queried when
414 * checking for MMIO spte cache hits.
f2fd125d 415 */
56871d44 416#define MMIO_SPTE_GEN_MASK GENMASK_ULL(17, 0)
f2fd125d 417
cae7ed3c
SC
418#define MMIO_SPTE_GEN_LOW_START 3
419#define MMIO_SPTE_GEN_LOW_END 11
420#define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
421 MMIO_SPTE_GEN_LOW_START)
f2fd125d 422
56871d44
PB
423#define MMIO_SPTE_GEN_HIGH_START PT64_SECOND_AVAIL_BITS_SHIFT
424#define MMIO_SPTE_GEN_HIGH_END 62
cae7ed3c
SC
425#define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
426 MMIO_SPTE_GEN_HIGH_START)
56871d44 427
5192f9b9 428static u64 generation_mmio_spte_mask(u64 gen)
f2fd125d
XG
429{
430 u64 mask;
431
cae7ed3c 432 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
56871d44 433 BUILD_BUG_ON((MMIO_SPTE_GEN_HIGH_MASK | MMIO_SPTE_GEN_LOW_MASK) & SPTE_SPECIAL_MASK);
f2fd125d 434
cae7ed3c
SC
435 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
436 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
f2fd125d
XG
437 return mask;
438}
439
5192f9b9 440static u64 get_mmio_spte_generation(u64 spte)
f2fd125d 441{
5192f9b9 442 u64 gen;
f2fd125d 443
cae7ed3c
SC
444 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
445 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
f2fd125d
XG
446 return gen;
447}
448
8f79b064 449static u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
ce88decf 450{
8f79b064 451
cae7ed3c 452 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
f8f55942 453 u64 mask = generation_mmio_spte_mask(gen);
28a1f3ac 454 u64 gpa = gfn << PAGE_SHIFT;
95b0430d 455
4af77151 456 access &= shadow_mmio_access_mask;
28a1f3ac
JS
457 mask |= shadow_mmio_value | access;
458 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
459 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
460 << shadow_nonpresent_or_rsvd_mask_len;
f2fd125d 461
8f79b064
BG
462 return mask;
463}
464
465static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
466 unsigned int access)
467{
468 u64 mask = make_mmio_spte(vcpu, gfn, access);
469 unsigned int gen = get_mmio_spte_generation(mask);
470
471 access = mask & ACC_ALL;
472
f8f55942 473 trace_mark_mmio_spte(sptep, gfn, access, gen);
f2fd125d 474 mmu_spte_set(sptep, mask);
ce88decf
XG
475}
476
ce88decf
XG
477static gfn_t get_mmio_spte_gfn(u64 spte)
478{
daa07cbc 479 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
28a1f3ac
JS
480
481 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
482 & shadow_nonpresent_or_rsvd_mask;
483
484 return gpa >> PAGE_SHIFT;
ce88decf
XG
485}
486
487static unsigned get_mmio_spte_access(u64 spte)
488{
4af77151 489 return spte & shadow_mmio_access_mask;
ce88decf
XG
490}
491
54bf36aa 492static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
0a2b64c5 493 kvm_pfn_t pfn, unsigned int access)
ce88decf
XG
494{
495 if (unlikely(is_noslot_pfn(pfn))) {
54bf36aa 496 mark_mmio_spte(vcpu, sptep, gfn, access);
ce88decf
XG
497 return true;
498 }
499
500 return false;
501}
c7addb90 502
54bf36aa 503static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
f8f55942 504{
cae7ed3c 505 u64 kvm_gen, spte_gen, gen;
089504c0 506
cae7ed3c
SC
507 gen = kvm_vcpu_memslots(vcpu)->generation;
508 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
509 return false;
089504c0 510
cae7ed3c 511 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
089504c0
XG
512 spte_gen = get_mmio_spte_generation(spte);
513
514 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
515 return likely(kvm_gen == spte_gen);
f8f55942
XG
516}
517
ce00053b
PF
518/*
519 * Sets the shadow PTE masks used by the MMU.
520 *
521 * Assumptions:
522 * - Setting either @accessed_mask or @dirty_mask requires setting both
523 * - At least one of @accessed_mask or @acc_track_mask must be set
524 */
7b52345e 525void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
f160c7b7 526 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
d0ec49d4 527 u64 acc_track_mask, u64 me_mask)
7b52345e 528{
ce00053b
PF
529 BUG_ON(!dirty_mask != !accessed_mask);
530 BUG_ON(!accessed_mask && !acc_track_mask);
6eeb4ef0 531 BUG_ON(acc_track_mask & SPTE_SPECIAL_MASK);
312b616b 532
7b52345e
SY
533 shadow_user_mask = user_mask;
534 shadow_accessed_mask = accessed_mask;
535 shadow_dirty_mask = dirty_mask;
536 shadow_nx_mask = nx_mask;
537 shadow_x_mask = x_mask;
ffb128c8 538 shadow_present_mask = p_mask;
f160c7b7 539 shadow_acc_track_mask = acc_track_mask;
d0ec49d4 540 shadow_me_mask = me_mask;
7b52345e
SY
541}
542EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
543
f3ecb59d
KH
544static u8 kvm_get_shadow_phys_bits(void)
545{
546 /*
7adacf5e
PB
547 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
548 * in CPU detection code, but the processor treats those reduced bits as
549 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
550 * the physical address bits reported by CPUID.
f3ecb59d 551 */
7adacf5e
PB
552 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
553 return cpuid_eax(0x80000008) & 0xff;
f3ecb59d 554
7adacf5e
PB
555 /*
556 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
557 * custom CPUID. Proceed with whatever the kernel found since these features
558 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
559 */
560 return boot_cpu_data.x86_phys_bits;
f3ecb59d
KH
561}
562
28a1f3ac 563static void kvm_mmu_reset_all_pte_masks(void)
f160c7b7 564{
daa07cbc
SC
565 u8 low_phys_bits;
566
f160c7b7
JS
567 shadow_user_mask = 0;
568 shadow_accessed_mask = 0;
569 shadow_dirty_mask = 0;
570 shadow_nx_mask = 0;
571 shadow_x_mask = 0;
f160c7b7
JS
572 shadow_present_mask = 0;
573 shadow_acc_track_mask = 0;
28a1f3ac 574
f3ecb59d
KH
575 shadow_phys_bits = kvm_get_shadow_phys_bits();
576
28a1f3ac
JS
577 /*
578 * If the CPU has 46 or less physical address bits, then set an
579 * appropriate mask to guard against L1TF attacks. Otherwise, it is
580 * assumed that the CPU is not vulnerable to L1TF.
61455bf2
KH
581 *
582 * Some Intel CPUs address the L1 cache using more PA bits than are
583 * reported by CPUID. Use the PA width of the L1 cache when possible
584 * to achieve more effective mitigation, e.g. if system RAM overlaps
585 * the most significant bits of legal physical address space.
28a1f3ac 586 */
61455bf2 587 shadow_nonpresent_or_rsvd_mask = 0;
d43e2675
PB
588 low_phys_bits = boot_cpu_data.x86_phys_bits;
589 if (boot_cpu_has_bug(X86_BUG_L1TF) &&
590 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >=
591 52 - shadow_nonpresent_or_rsvd_mask_len)) {
592 low_phys_bits = boot_cpu_data.x86_cache_bits
593 - shadow_nonpresent_or_rsvd_mask_len;
28a1f3ac 594 shadow_nonpresent_or_rsvd_mask =
d43e2675
PB
595 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);
596 }
61455bf2 597
daa07cbc
SC
598 shadow_nonpresent_or_rsvd_lower_gfn_mask =
599 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
f160c7b7
JS
600}
601
6aa8b732
AK
602static int is_cpuid_PSE36(void)
603{
604 return 1;
605}
606
73b1087e
AK
607static int is_nx(struct kvm_vcpu *vcpu)
608{
f6801dff 609 return vcpu->arch.efer & EFER_NX;
73b1087e
AK
610}
611
c7addb90
AK
612static int is_shadow_present_pte(u64 pte)
613{
f160c7b7 614 return (pte != 0) && !is_mmio_spte(pte);
c7addb90
AK
615}
616
05da4558
MT
617static int is_large_pte(u64 pte)
618{
619 return pte & PT_PAGE_SIZE_MASK;
620}
621
776e6633
MT
622static int is_last_spte(u64 pte, int level)
623{
3bae0459 624 if (level == PG_LEVEL_4K)
776e6633 625 return 1;
852e3c19 626 if (is_large_pte(pte))
776e6633
MT
627 return 1;
628 return 0;
629}
630
d3e328f2
JS
631static bool is_executable_pte(u64 spte)
632{
633 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
634}
635
ba049e93 636static kvm_pfn_t spte_to_pfn(u64 pte)
0b49ea86 637{
35149e21 638 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK
639}
640
da928521
AK
641static gfn_t pse36_gfn_delta(u32 gpte)
642{
643 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
644
645 return (gpte & PT32_DIR_PSE36_MASK) << shift;
646}
647
603e0651 648#ifdef CONFIG_X86_64
d555c333 649static void __set_spte(u64 *sptep, u64 spte)
e663ee64 650{
b19ee2ff 651 WRITE_ONCE(*sptep, spte);
e663ee64
AK
652}
653
603e0651 654static void __update_clear_spte_fast(u64 *sptep, u64 spte)
a9221dd5 655{
b19ee2ff 656 WRITE_ONCE(*sptep, spte);
603e0651
XG
657}
658
659static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
660{
661 return xchg(sptep, spte);
662}
c2a2ac2b
XG
663
664static u64 __get_spte_lockless(u64 *sptep)
665{
6aa7de05 666 return READ_ONCE(*sptep);
c2a2ac2b 667}
a9221dd5 668#else
603e0651
XG
669union split_spte {
670 struct {
671 u32 spte_low;
672 u32 spte_high;
673 };
674 u64 spte;
675};
a9221dd5 676
c2a2ac2b
XG
677static void count_spte_clear(u64 *sptep, u64 spte)
678{
679 struct kvm_mmu_page *sp = page_header(__pa(sptep));
680
681 if (is_shadow_present_pte(spte))
682 return;
683
684 /* Ensure the spte is completely set before we increase the count */
685 smp_wmb();
686 sp->clear_spte_count++;
687}
688
603e0651
XG
689static void __set_spte(u64 *sptep, u64 spte)
690{
691 union split_spte *ssptep, sspte;
a9221dd5 692
603e0651
XG
693 ssptep = (union split_spte *)sptep;
694 sspte = (union split_spte)spte;
695
696 ssptep->spte_high = sspte.spte_high;
697
698 /*
699 * If we map the spte from nonpresent to present, We should store
700 * the high bits firstly, then set present bit, so cpu can not
701 * fetch this spte while we are setting the spte.
702 */
703 smp_wmb();
704
b19ee2ff 705 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
a9221dd5
AK
706}
707
603e0651
XG
708static void __update_clear_spte_fast(u64 *sptep, u64 spte)
709{
710 union split_spte *ssptep, sspte;
711
712 ssptep = (union split_spte *)sptep;
713 sspte = (union split_spte)spte;
714
b19ee2ff 715 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
603e0651
XG
716
717 /*
718 * If we map the spte from present to nonpresent, we should clear
719 * present bit firstly to avoid vcpu fetch the old high bits.
720 */
721 smp_wmb();
722
723 ssptep->spte_high = sspte.spte_high;
c2a2ac2b 724 count_spte_clear(sptep, spte);
603e0651
XG
725}
726
727static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
728{
729 union split_spte *ssptep, sspte, orig;
730
731 ssptep = (union split_spte *)sptep;
732 sspte = (union split_spte)spte;
733
734 /* xchg acts as a barrier before the setting of the high bits */
735 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
41bc3186
ZJ
736 orig.spte_high = ssptep->spte_high;
737 ssptep->spte_high = sspte.spte_high;
c2a2ac2b 738 count_spte_clear(sptep, spte);
603e0651
XG
739
740 return orig.spte;
741}
c2a2ac2b
XG
742
743/*
744 * The idea using the light way get the spte on x86_32 guest is from
39656e83 745 * gup_get_pte (mm/gup.c).
accaefe0
XG
746 *
747 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
748 * coalesces them and we are running out of the MMU lock. Therefore
749 * we need to protect against in-progress updates of the spte.
750 *
751 * Reading the spte while an update is in progress may get the old value
752 * for the high part of the spte. The race is fine for a present->non-present
753 * change (because the high part of the spte is ignored for non-present spte),
754 * but for a present->present change we must reread the spte.
755 *
756 * All such changes are done in two steps (present->non-present and
757 * non-present->present), hence it is enough to count the number of
758 * present->non-present updates: if it changed while reading the spte,
759 * we might have hit the race. This is done using clear_spte_count.
c2a2ac2b
XG
760 */
761static u64 __get_spte_lockless(u64 *sptep)
762{
763 struct kvm_mmu_page *sp = page_header(__pa(sptep));
764 union split_spte spte, *orig = (union split_spte *)sptep;
765 int count;
766
767retry:
768 count = sp->clear_spte_count;
769 smp_rmb();
770
771 spte.spte_low = orig->spte_low;
772 smp_rmb();
773
774 spte.spte_high = orig->spte_high;
775 smp_rmb();
776
777 if (unlikely(spte.spte_low != orig->spte_low ||
778 count != sp->clear_spte_count))
779 goto retry;
780
781 return spte.spte;
782}
603e0651
XG
783#endif
784
ea4114bc 785static bool spte_can_locklessly_be_made_writable(u64 spte)
c7ba5b48 786{
feb3eb70
GN
787 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
788 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
c7ba5b48
XG
789}
790
8672b721
XG
791static bool spte_has_volatile_bits(u64 spte)
792{
f160c7b7
JS
793 if (!is_shadow_present_pte(spte))
794 return false;
795
c7ba5b48 796 /*
6a6256f9 797 * Always atomically update spte if it can be updated
c7ba5b48
XG
798 * out of mmu-lock, it can ensure dirty bit is not lost,
799 * also, it can help us to get a stable is_writable_pte()
800 * to ensure tlb flush is not missed.
801 */
f160c7b7
JS
802 if (spte_can_locklessly_be_made_writable(spte) ||
803 is_access_track_spte(spte))
c7ba5b48
XG
804 return true;
805
ac8d57e5 806 if (spte_ad_enabled(spte)) {
f160c7b7
JS
807 if ((spte & shadow_accessed_mask) == 0 ||
808 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
809 return true;
810 }
8672b721 811
f160c7b7 812 return false;
8672b721
XG
813}
814
83ef6c81 815static bool is_accessed_spte(u64 spte)
4132779b 816{
ac8d57e5
PF
817 u64 accessed_mask = spte_shadow_accessed_mask(spte);
818
819 return accessed_mask ? spte & accessed_mask
820 : !is_access_track_spte(spte);
4132779b
XG
821}
822
83ef6c81 823static bool is_dirty_spte(u64 spte)
7e71a59b 824{
ac8d57e5
PF
825 u64 dirty_mask = spte_shadow_dirty_mask(spte);
826
827 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
7e71a59b
KH
828}
829
1df9f2dc
XG
830/* Rules for using mmu_spte_set:
831 * Set the sptep from nonpresent to present.
832 * Note: the sptep being assigned *must* be either not present
833 * or in a state where the hardware will not attempt to update
834 * the spte.
835 */
836static void mmu_spte_set(u64 *sptep, u64 new_spte)
837{
838 WARN_ON(is_shadow_present_pte(*sptep));
839 __set_spte(sptep, new_spte);
840}
841
f39a058d
JS
842/*
843 * Update the SPTE (excluding the PFN), but do not track changes in its
844 * accessed/dirty status.
1df9f2dc 845 */
f39a058d 846static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
b79b93f9 847{
c7ba5b48 848 u64 old_spte = *sptep;
4132779b 849
afd28fe1 850 WARN_ON(!is_shadow_present_pte(new_spte));
b79b93f9 851
6e7d0354
XG
852 if (!is_shadow_present_pte(old_spte)) {
853 mmu_spte_set(sptep, new_spte);
f39a058d 854 return old_spte;
6e7d0354 855 }
4132779b 856
c7ba5b48 857 if (!spte_has_volatile_bits(old_spte))
603e0651 858 __update_clear_spte_fast(sptep, new_spte);
4132779b 859 else
603e0651 860 old_spte = __update_clear_spte_slow(sptep, new_spte);
4132779b 861
83ef6c81
JS
862 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
863
f39a058d
JS
864 return old_spte;
865}
866
867/* Rules for using mmu_spte_update:
868 * Update the state bits, it means the mapped pfn is not changed.
869 *
870 * Whenever we overwrite a writable spte with a read-only one we
871 * should flush remote TLBs. Otherwise rmap_write_protect
872 * will find a read-only spte, even though the writable spte
873 * might be cached on a CPU's TLB, the return value indicates this
874 * case.
875 *
876 * Returns true if the TLB needs to be flushed
877 */
878static bool mmu_spte_update(u64 *sptep, u64 new_spte)
879{
880 bool flush = false;
881 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
882
883 if (!is_shadow_present_pte(old_spte))
884 return false;
885
c7ba5b48
XG
886 /*
887 * For the spte updated out of mmu-lock is safe, since
6a6256f9 888 * we always atomically update it, see the comments in
c7ba5b48
XG
889 * spte_has_volatile_bits().
890 */
ea4114bc 891 if (spte_can_locklessly_be_made_writable(old_spte) &&
7f31c959 892 !is_writable_pte(new_spte))
83ef6c81 893 flush = true;
4132779b 894
7e71a59b 895 /*
83ef6c81 896 * Flush TLB when accessed/dirty states are changed in the page tables,
7e71a59b
KH
897 * to guarantee consistency between TLB and page tables.
898 */
7e71a59b 899
83ef6c81
JS
900 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
901 flush = true;
4132779b 902 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
83ef6c81
JS
903 }
904
905 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
906 flush = true;
4132779b 907 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
83ef6c81 908 }
6e7d0354 909
83ef6c81 910 return flush;
b79b93f9
AK
911}
912
1df9f2dc
XG
913/*
914 * Rules for using mmu_spte_clear_track_bits:
915 * It sets the sptep from present to nonpresent, and track the
916 * state bits, it is used to clear the last level sptep.
83ef6c81 917 * Returns non-zero if the PTE was previously valid.
1df9f2dc
XG
918 */
919static int mmu_spte_clear_track_bits(u64 *sptep)
920{
ba049e93 921 kvm_pfn_t pfn;
1df9f2dc
XG
922 u64 old_spte = *sptep;
923
924 if (!spte_has_volatile_bits(old_spte))
603e0651 925 __update_clear_spte_fast(sptep, 0ull);
1df9f2dc 926 else
603e0651 927 old_spte = __update_clear_spte_slow(sptep, 0ull);
1df9f2dc 928
afd28fe1 929 if (!is_shadow_present_pte(old_spte))
1df9f2dc
XG
930 return 0;
931
932 pfn = spte_to_pfn(old_spte);
86fde74c
XG
933
934 /*
935 * KVM does not hold the refcount of the page used by
936 * kvm mmu, before reclaiming the page, we should
937 * unmap it from mmu first.
938 */
bf4bea8e 939 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
86fde74c 940
83ef6c81 941 if (is_accessed_spte(old_spte))
1df9f2dc 942 kvm_set_pfn_accessed(pfn);
83ef6c81
JS
943
944 if (is_dirty_spte(old_spte))
1df9f2dc 945 kvm_set_pfn_dirty(pfn);
83ef6c81 946
1df9f2dc
XG
947 return 1;
948}
949
950/*
951 * Rules for using mmu_spte_clear_no_track:
952 * Directly clear spte without caring the state bits of sptep,
953 * it is used to set the upper level spte.
954 */
955static void mmu_spte_clear_no_track(u64 *sptep)
956{
603e0651 957 __update_clear_spte_fast(sptep, 0ull);
1df9f2dc
XG
958}
959
c2a2ac2b
XG
960static u64 mmu_spte_get_lockless(u64 *sptep)
961{
962 return __get_spte_lockless(sptep);
963}
964
f160c7b7
JS
965static u64 mark_spte_for_access_track(u64 spte)
966{
ac8d57e5 967 if (spte_ad_enabled(spte))
f160c7b7
JS
968 return spte & ~shadow_accessed_mask;
969
ac8d57e5 970 if (is_access_track_spte(spte))
f160c7b7
JS
971 return spte;
972
973 /*
20d65236
JS
974 * Making an Access Tracking PTE will result in removal of write access
975 * from the PTE. So, verify that we will be able to restore the write
976 * access in the fast page fault path later on.
f160c7b7
JS
977 */
978 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
979 !spte_can_locklessly_be_made_writable(spte),
980 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
981
982 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
983 shadow_acc_track_saved_bits_shift),
984 "kvm: Access Tracking saved bit locations are not zero\n");
985
986 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
987 shadow_acc_track_saved_bits_shift;
988 spte &= ~shadow_acc_track_mask;
f160c7b7
JS
989
990 return spte;
991}
992
d3e328f2
JS
993/* Restore an acc-track PTE back to a regular PTE */
994static u64 restore_acc_track_spte(u64 spte)
995{
996 u64 new_spte = spte;
997 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
998 & shadow_acc_track_saved_bits_mask;
999
ac8d57e5 1000 WARN_ON_ONCE(spte_ad_enabled(spte));
d3e328f2
JS
1001 WARN_ON_ONCE(!is_access_track_spte(spte));
1002
1003 new_spte &= ~shadow_acc_track_mask;
1004 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
1005 shadow_acc_track_saved_bits_shift);
1006 new_spte |= saved_bits;
1007
1008 return new_spte;
1009}
1010
f160c7b7
JS
1011/* Returns the Accessed status of the PTE and resets it at the same time. */
1012static bool mmu_spte_age(u64 *sptep)
1013{
1014 u64 spte = mmu_spte_get_lockless(sptep);
1015
1016 if (!is_accessed_spte(spte))
1017 return false;
1018
ac8d57e5 1019 if (spte_ad_enabled(spte)) {
f160c7b7
JS
1020 clear_bit((ffs(shadow_accessed_mask) - 1),
1021 (unsigned long *)sptep);
1022 } else {
1023 /*
1024 * Capture the dirty status of the page, so that it doesn't get
1025 * lost when the SPTE is marked for access tracking.
1026 */
1027 if (is_writable_pte(spte))
1028 kvm_set_pfn_dirty(spte_to_pfn(spte));
1029
1030 spte = mark_spte_for_access_track(spte);
1031 mmu_spte_update_no_track(sptep, spte);
1032 }
1033
1034 return true;
1035}
1036
c2a2ac2b
XG
1037static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
1038{
c142786c
AK
1039 /*
1040 * Prevent page table teardown by making any free-er wait during
1041 * kvm_flush_remote_tlbs() IPI to all active vcpus.
1042 */
1043 local_irq_disable();
36ca7e0a 1044
c142786c
AK
1045 /*
1046 * Make sure a following spte read is not reordered ahead of the write
1047 * to vcpu->mode.
1048 */
36ca7e0a 1049 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
c2a2ac2b
XG
1050}
1051
1052static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
1053{
c142786c
AK
1054 /*
1055 * Make sure the write to vcpu->mode is not reordered in front of
9a984586 1056 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
c142786c
AK
1057 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
1058 */
36ca7e0a 1059 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
c142786c 1060 local_irq_enable();
c2a2ac2b
XG
1061}
1062
e2dec939 1063static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 1064 struct kmem_cache *base_cache, int min)
714b93da
AK
1065{
1066 void *obj;
1067
1068 if (cache->nobjs >= min)
e2dec939 1069 return 0;
714b93da 1070 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
254272ce 1071 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
714b93da 1072 if (!obj)
daefb794 1073 return cache->nobjs >= min ? 0 : -ENOMEM;
714b93da
AK
1074 cache->objects[cache->nobjs++] = obj;
1075 }
e2dec939 1076 return 0;
714b93da
AK
1077}
1078
f759e2b4
XG
1079static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
1080{
1081 return cache->nobjs;
1082}
1083
e8ad9a70
XG
1084static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
1085 struct kmem_cache *cache)
714b93da
AK
1086{
1087 while (mc->nobjs)
e8ad9a70 1088 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK
1089}
1090
c1158e63 1091static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 1092 int min)
c1158e63 1093{
842f22ed 1094 void *page;
c1158e63
AK
1095
1096 if (cache->nobjs >= min)
1097 return 0;
1098 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
d97e5e61 1099 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
c1158e63 1100 if (!page)
daefb794 1101 return cache->nobjs >= min ? 0 : -ENOMEM;
842f22ed 1102 cache->objects[cache->nobjs++] = page;
c1158e63
AK
1103 }
1104 return 0;
1105}
1106
1107static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1108{
1109 while (mc->nobjs)
c4d198d5 1110 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK
1111}
1112
2e3e5882 1113static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 1114{
e2dec939
AK
1115 int r;
1116
53c07b18 1117 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
67052b35 1118 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
d3d25b04
AK
1119 if (r)
1120 goto out;
ad312c7c 1121 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK
1122 if (r)
1123 goto out;
ad312c7c 1124 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 1125 mmu_page_header_cache, 4);
e2dec939
AK
1126out:
1127 return r;
714b93da
AK
1128}
1129
1130static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1131{
53c07b18
XG
1132 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1133 pte_list_desc_cache);
ad312c7c 1134 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG
1135 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1136 mmu_page_header_cache);
714b93da
AK
1137}
1138
80feb89a 1139static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
714b93da
AK
1140{
1141 void *p;
1142
1143 BUG_ON(!mc->nobjs);
1144 p = mc->objects[--mc->nobjs];
714b93da
AK
1145 return p;
1146}
1147
53c07b18 1148static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
714b93da 1149{
80feb89a 1150 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
714b93da
AK
1151}
1152
53c07b18 1153static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
714b93da 1154{
53c07b18 1155 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
714b93da
AK
1156}
1157
2032a93d
LJ
1158static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1159{
1160 if (!sp->role.direct)
1161 return sp->gfns[index];
1162
1163 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1164}
1165
1166static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1167{
e9f2a760 1168 if (!sp->role.direct) {
2032a93d 1169 sp->gfns[index] = gfn;
e9f2a760
PB
1170 return;
1171 }
1172
1173 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
1174 pr_err_ratelimited("gfn mismatch under direct page %llx "
1175 "(expected %llx, got %llx)\n",
1176 sp->gfn,
1177 kvm_mmu_page_get_gfn(sp, index), gfn);
2032a93d
LJ
1178}
1179
05da4558 1180/*
d4dbf470
TY
1181 * Return the pointer to the large page information for a given gfn,
1182 * handling slots that are not large page aligned.
05da4558 1183 */
d4dbf470
TY
1184static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1185 struct kvm_memory_slot *slot,
1186 int level)
05da4558
MT
1187{
1188 unsigned long idx;
1189
fb03cb6f 1190 idx = gfn_to_index(gfn, slot->base_gfn, level);
db3fe4eb 1191 return &slot->arch.lpage_info[level - 2][idx];
05da4558
MT
1192}
1193
547ffaed
XG
1194static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1195 gfn_t gfn, int count)
1196{
1197 struct kvm_lpage_info *linfo;
1198 int i;
1199
3bae0459 1200 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
547ffaed
XG
1201 linfo = lpage_info_slot(gfn, slot, i);
1202 linfo->disallow_lpage += count;
1203 WARN_ON(linfo->disallow_lpage < 0);
1204 }
1205}
1206
1207void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1208{
1209 update_gfn_disallow_lpage_count(slot, gfn, 1);
1210}
1211
1212void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1213{
1214 update_gfn_disallow_lpage_count(slot, gfn, -1);
1215}
1216
3ed1a478 1217static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
05da4558 1218{
699023e2 1219 struct kvm_memslots *slots;
d25797b2 1220 struct kvm_memory_slot *slot;
3ed1a478 1221 gfn_t gfn;
05da4558 1222
56ca57f9 1223 kvm->arch.indirect_shadow_pages++;
3ed1a478 1224 gfn = sp->gfn;
699023e2
PB
1225 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1226 slot = __gfn_to_memslot(slots, gfn);
56ca57f9
XG
1227
1228 /* the non-leaf shadow pages are keeping readonly. */
3bae0459 1229 if (sp->role.level > PG_LEVEL_4K)
56ca57f9
XG
1230 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1231 KVM_PAGE_TRACK_WRITE);
1232
547ffaed 1233 kvm_mmu_gfn_disallow_lpage(slot, gfn);
05da4558
MT
1234}
1235
b8e8c830
PB
1236static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1237{
1238 if (sp->lpage_disallowed)
1239 return;
1240
1241 ++kvm->stat.nx_lpage_splits;
1aa9b957
JS
1242 list_add_tail(&sp->lpage_disallowed_link,
1243 &kvm->arch.lpage_disallowed_mmu_pages);
b8e8c830
PB
1244 sp->lpage_disallowed = true;
1245}
1246
3ed1a478 1247static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
05da4558 1248{
699023e2 1249 struct kvm_memslots *slots;
d25797b2 1250 struct kvm_memory_slot *slot;
3ed1a478 1251 gfn_t gfn;
05da4558 1252
56ca57f9 1253 kvm->arch.indirect_shadow_pages--;
3ed1a478 1254 gfn = sp->gfn;
699023e2
PB
1255 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1256 slot = __gfn_to_memslot(slots, gfn);
3bae0459 1257 if (sp->role.level > PG_LEVEL_4K)
56ca57f9
XG
1258 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1259 KVM_PAGE_TRACK_WRITE);
1260
547ffaed 1261 kvm_mmu_gfn_allow_lpage(slot, gfn);
05da4558
MT
1262}
1263
b8e8c830
PB
1264static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1265{
1266 --kvm->stat.nx_lpage_splits;
1267 sp->lpage_disallowed = false;
1aa9b957 1268 list_del(&sp->lpage_disallowed_link);
b8e8c830
PB
1269}
1270
5d163b1c
XG
1271static struct kvm_memory_slot *
1272gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1273 bool no_dirty_log)
05da4558
MT
1274{
1275 struct kvm_memory_slot *slot;
5d163b1c 1276
54bf36aa 1277 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
91b0d268
PB
1278 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1279 return NULL;
1280 if (no_dirty_log && slot->dirty_bitmap)
1281 return NULL;
5d163b1c
XG
1282
1283 return slot;
1284}
1285
290fc38d 1286/*
018aabb5 1287 * About rmap_head encoding:
cd4a4e53 1288 *
018aabb5
TY
1289 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1290 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
53c07b18 1291 * pte_list_desc containing more mappings.
018aabb5
TY
1292 */
1293
1294/*
1295 * Returns the number of pointers in the rmap chain, not counting the new one.
cd4a4e53 1296 */
53c07b18 1297static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
018aabb5 1298 struct kvm_rmap_head *rmap_head)
cd4a4e53 1299{
53c07b18 1300 struct pte_list_desc *desc;
53a27b39 1301 int i, count = 0;
cd4a4e53 1302
018aabb5 1303 if (!rmap_head->val) {
53c07b18 1304 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
018aabb5
TY
1305 rmap_head->val = (unsigned long)spte;
1306 } else if (!(rmap_head->val & 1)) {
53c07b18
XG
1307 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1308 desc = mmu_alloc_pte_list_desc(vcpu);
018aabb5 1309 desc->sptes[0] = (u64 *)rmap_head->val;
d555c333 1310 desc->sptes[1] = spte;
018aabb5 1311 rmap_head->val = (unsigned long)desc | 1;
cb16a7b3 1312 ++count;
cd4a4e53 1313 } else {
53c07b18 1314 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
018aabb5 1315 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
53c07b18 1316 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
cd4a4e53 1317 desc = desc->more;
53c07b18 1318 count += PTE_LIST_EXT;
53a27b39 1319 }
53c07b18
XG
1320 if (desc->sptes[PTE_LIST_EXT-1]) {
1321 desc->more = mmu_alloc_pte_list_desc(vcpu);
cd4a4e53
AK
1322 desc = desc->more;
1323 }
d555c333 1324 for (i = 0; desc->sptes[i]; ++i)
cb16a7b3 1325 ++count;
d555c333 1326 desc->sptes[i] = spte;
cd4a4e53 1327 }
53a27b39 1328 return count;
cd4a4e53
AK
1329}
1330
53c07b18 1331static void
018aabb5
TY
1332pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1333 struct pte_list_desc *desc, int i,
1334 struct pte_list_desc *prev_desc)
cd4a4e53
AK
1335{
1336 int j;
1337
53c07b18 1338 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 1339 ;
d555c333
AK
1340 desc->sptes[i] = desc->sptes[j];
1341 desc->sptes[j] = NULL;
cd4a4e53
AK
1342 if (j != 0)
1343 return;
1344 if (!prev_desc && !desc->more)
fe3c2b4c 1345 rmap_head->val = 0;
cd4a4e53
AK
1346 else
1347 if (prev_desc)
1348 prev_desc->more = desc->more;
1349 else
018aabb5 1350 rmap_head->val = (unsigned long)desc->more | 1;
53c07b18 1351 mmu_free_pte_list_desc(desc);
cd4a4e53
AK
1352}
1353
8daf3462 1354static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
cd4a4e53 1355{
53c07b18
XG
1356 struct pte_list_desc *desc;
1357 struct pte_list_desc *prev_desc;
cd4a4e53
AK
1358 int i;
1359
018aabb5 1360 if (!rmap_head->val) {
8daf3462 1361 pr_err("%s: %p 0->BUG\n", __func__, spte);
cd4a4e53 1362 BUG();
018aabb5 1363 } else if (!(rmap_head->val & 1)) {
8daf3462 1364 rmap_printk("%s: %p 1->0\n", __func__, spte);
018aabb5 1365 if ((u64 *)rmap_head->val != spte) {
8daf3462 1366 pr_err("%s: %p 1->BUG\n", __func__, spte);
cd4a4e53
AK
1367 BUG();
1368 }
018aabb5 1369 rmap_head->val = 0;
cd4a4e53 1370 } else {
8daf3462 1371 rmap_printk("%s: %p many->many\n", __func__, spte);
018aabb5 1372 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
cd4a4e53
AK
1373 prev_desc = NULL;
1374 while (desc) {
018aabb5 1375 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
d555c333 1376 if (desc->sptes[i] == spte) {
018aabb5
TY
1377 pte_list_desc_remove_entry(rmap_head,
1378 desc, i, prev_desc);
cd4a4e53
AK
1379 return;
1380 }
018aabb5 1381 }
cd4a4e53
AK
1382 prev_desc = desc;
1383 desc = desc->more;
1384 }
8daf3462 1385 pr_err("%s: %p many->many\n", __func__, spte);
cd4a4e53
AK
1386 BUG();
1387 }
1388}
1389
e7912386
WY
1390static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1391{
1392 mmu_spte_clear_track_bits(sptep);
1393 __pte_list_remove(sptep, rmap_head);
1394}
1395
018aabb5
TY
1396static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1397 struct kvm_memory_slot *slot)
53c07b18 1398{
77d11309 1399 unsigned long idx;
53c07b18 1400
77d11309 1401 idx = gfn_to_index(gfn, slot->base_gfn, level);
3bae0459 1402 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
53c07b18
XG
1403}
1404
018aabb5
TY
1405static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1406 struct kvm_mmu_page *sp)
9b9b1492 1407{
699023e2 1408 struct kvm_memslots *slots;
9b9b1492
TY
1409 struct kvm_memory_slot *slot;
1410
699023e2
PB
1411 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1412 slot = __gfn_to_memslot(slots, gfn);
e4cd1da9 1413 return __gfn_to_rmap(gfn, sp->role.level, slot);
9b9b1492
TY
1414}
1415
f759e2b4
XG
1416static bool rmap_can_add(struct kvm_vcpu *vcpu)
1417{
1418 struct kvm_mmu_memory_cache *cache;
1419
1420 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1421 return mmu_memory_cache_free_objects(cache);
1422}
1423
53c07b18
XG
1424static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1425{
1426 struct kvm_mmu_page *sp;
018aabb5 1427 struct kvm_rmap_head *rmap_head;
53c07b18 1428
53c07b18
XG
1429 sp = page_header(__pa(spte));
1430 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
018aabb5
TY
1431 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1432 return pte_list_add(vcpu, spte, rmap_head);
53c07b18
XG
1433}
1434
53c07b18
XG
1435static void rmap_remove(struct kvm *kvm, u64 *spte)
1436{
1437 struct kvm_mmu_page *sp;
1438 gfn_t gfn;
018aabb5 1439 struct kvm_rmap_head *rmap_head;
53c07b18
XG
1440
1441 sp = page_header(__pa(spte));
1442 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
018aabb5 1443 rmap_head = gfn_to_rmap(kvm, gfn, sp);
8daf3462 1444 __pte_list_remove(spte, rmap_head);
53c07b18
XG
1445}
1446
1e3f42f0
TY
1447/*
1448 * Used by the following functions to iterate through the sptes linked by a
1449 * rmap. All fields are private and not assumed to be used outside.
1450 */
1451struct rmap_iterator {
1452 /* private fields */
1453 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1454 int pos; /* index of the sptep */
1455};
1456
1457/*
1458 * Iteration must be started by this function. This should also be used after
1459 * removing/dropping sptes from the rmap link because in such cases the
0a03cbda 1460 * information in the iterator may not be valid.
1e3f42f0
TY
1461 *
1462 * Returns sptep if found, NULL otherwise.
1463 */
018aabb5
TY
1464static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1465 struct rmap_iterator *iter)
1e3f42f0 1466{
77fbbbd2
TY
1467 u64 *sptep;
1468
018aabb5 1469 if (!rmap_head->val)
1e3f42f0
TY
1470 return NULL;
1471
018aabb5 1472 if (!(rmap_head->val & 1)) {
1e3f42f0 1473 iter->desc = NULL;
77fbbbd2
TY
1474 sptep = (u64 *)rmap_head->val;
1475 goto out;
1e3f42f0
TY
1476 }
1477
018aabb5 1478 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1e3f42f0 1479 iter->pos = 0;
77fbbbd2
TY
1480 sptep = iter->desc->sptes[iter->pos];
1481out:
1482 BUG_ON(!is_shadow_present_pte(*sptep));
1483 return sptep;
1e3f42f0
TY
1484}
1485
1486/*
1487 * Must be used with a valid iterator: e.g. after rmap_get_first().
1488 *
1489 * Returns sptep if found, NULL otherwise.
1490 */
1491static u64 *rmap_get_next(struct rmap_iterator *iter)
1492{
77fbbbd2
TY
1493 u64 *sptep;
1494
1e3f42f0
TY
1495 if (iter->desc) {
1496 if (iter->pos < PTE_LIST_EXT - 1) {
1e3f42f0
TY
1497 ++iter->pos;
1498 sptep = iter->desc->sptes[iter->pos];
1499 if (sptep)
77fbbbd2 1500 goto out;
1e3f42f0
TY
1501 }
1502
1503 iter->desc = iter->desc->more;
1504
1505 if (iter->desc) {
1506 iter->pos = 0;
1507 /* desc->sptes[0] cannot be NULL */
77fbbbd2
TY
1508 sptep = iter->desc->sptes[iter->pos];
1509 goto out;
1e3f42f0
TY
1510 }
1511 }
1512
1513 return NULL;
77fbbbd2
TY
1514out:
1515 BUG_ON(!is_shadow_present_pte(*sptep));
1516 return sptep;
1e3f42f0
TY
1517}
1518
018aabb5
TY
1519#define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1520 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
77fbbbd2 1521 _spte_; _spte_ = rmap_get_next(_iter_))
0d536790 1522
c3707958 1523static void drop_spte(struct kvm *kvm, u64 *sptep)
e4b502ea 1524{
1df9f2dc 1525 if (mmu_spte_clear_track_bits(sptep))
eb45fda4 1526 rmap_remove(kvm, sptep);
be38d276
AK
1527}
1528
8e22f955
XG
1529
1530static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1531{
1532 if (is_large_pte(*sptep)) {
3bae0459 1533 WARN_ON(page_header(__pa(sptep))->role.level == PG_LEVEL_4K);
8e22f955
XG
1534 drop_spte(kvm, sptep);
1535 --kvm->stat.lpages;
1536 return true;
1537 }
1538
1539 return false;
1540}
1541
1542static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1543{
c3134ce2
LT
1544 if (__drop_large_spte(vcpu->kvm, sptep)) {
1545 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1546
1547 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1548 KVM_PAGES_PER_HPAGE(sp->role.level));
1549 }
8e22f955
XG
1550}
1551
1552/*
49fde340 1553 * Write-protect on the specified @sptep, @pt_protect indicates whether
c126d94f 1554 * spte write-protection is caused by protecting shadow page table.
49fde340 1555 *
b4619660 1556 * Note: write protection is difference between dirty logging and spte
49fde340
XG
1557 * protection:
1558 * - for dirty logging, the spte can be set to writable at anytime if
1559 * its dirty bitmap is properly set.
1560 * - for spte protection, the spte can be writable only after unsync-ing
1561 * shadow page.
8e22f955 1562 *
c126d94f 1563 * Return true if tlb need be flushed.
8e22f955 1564 */
c4f138b4 1565static bool spte_write_protect(u64 *sptep, bool pt_protect)
d13bc5b5
XG
1566{
1567 u64 spte = *sptep;
1568
49fde340 1569 if (!is_writable_pte(spte) &&
ea4114bc 1570 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
d13bc5b5
XG
1571 return false;
1572
1573 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1574
49fde340
XG
1575 if (pt_protect)
1576 spte &= ~SPTE_MMU_WRITEABLE;
d13bc5b5 1577 spte = spte & ~PT_WRITABLE_MASK;
49fde340 1578
c126d94f 1579 return mmu_spte_update(sptep, spte);
d13bc5b5
XG
1580}
1581
018aabb5
TY
1582static bool __rmap_write_protect(struct kvm *kvm,
1583 struct kvm_rmap_head *rmap_head,
245c3912 1584 bool pt_protect)
98348e95 1585{
1e3f42f0
TY
1586 u64 *sptep;
1587 struct rmap_iterator iter;
d13bc5b5 1588 bool flush = false;
374cbac0 1589
018aabb5 1590 for_each_rmap_spte(rmap_head, &iter, sptep)
c4f138b4 1591 flush |= spte_write_protect(sptep, pt_protect);
855149aa 1592
d13bc5b5 1593 return flush;
a0ed4607
TY
1594}
1595
c4f138b4 1596static bool spte_clear_dirty(u64 *sptep)
f4b4b180
KH
1597{
1598 u64 spte = *sptep;
1599
1600 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1601
1f4e5fc8 1602 MMU_WARN_ON(!spte_ad_enabled(spte));
f4b4b180 1603 spte &= ~shadow_dirty_mask;
f4b4b180
KH
1604 return mmu_spte_update(sptep, spte);
1605}
1606
1f4e5fc8 1607static bool spte_wrprot_for_clear_dirty(u64 *sptep)
ac8d57e5
PF
1608{
1609 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1610 (unsigned long *)sptep);
1f4e5fc8 1611 if (was_writable && !spte_ad_enabled(*sptep))
ac8d57e5
PF
1612 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1613
1614 return was_writable;
1615}
1616
1617/*
1618 * Gets the GFN ready for another round of dirty logging by clearing the
1619 * - D bit on ad-enabled SPTEs, and
1620 * - W bit on ad-disabled SPTEs.
1621 * Returns true iff any D or W bits were cleared.
1622 */
018aabb5 1623static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
f4b4b180
KH
1624{
1625 u64 *sptep;
1626 struct rmap_iterator iter;
1627 bool flush = false;
1628
018aabb5 1629 for_each_rmap_spte(rmap_head, &iter, sptep)
1f4e5fc8
PB
1630 if (spte_ad_need_write_protect(*sptep))
1631 flush |= spte_wrprot_for_clear_dirty(sptep);
ac8d57e5 1632 else
1f4e5fc8 1633 flush |= spte_clear_dirty(sptep);
f4b4b180
KH
1634
1635 return flush;
1636}
1637
c4f138b4 1638static bool spte_set_dirty(u64 *sptep)
f4b4b180
KH
1639{
1640 u64 spte = *sptep;
1641
1642 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1643
1f4e5fc8 1644 /*
afaf0b2f 1645 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1f4e5fc8
PB
1646 * do not bother adding back write access to pages marked
1647 * SPTE_AD_WRPROT_ONLY_MASK.
1648 */
f4b4b180
KH
1649 spte |= shadow_dirty_mask;
1650
1651 return mmu_spte_update(sptep, spte);
1652}
1653
018aabb5 1654static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
f4b4b180
KH
1655{
1656 u64 *sptep;
1657 struct rmap_iterator iter;
1658 bool flush = false;
1659
018aabb5 1660 for_each_rmap_spte(rmap_head, &iter, sptep)
ac8d57e5
PF
1661 if (spte_ad_enabled(*sptep))
1662 flush |= spte_set_dirty(sptep);
f4b4b180
KH
1663
1664 return flush;
1665}
1666
5dc99b23 1667/**
3b0f1d01 1668 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
5dc99b23
TY
1669 * @kvm: kvm instance
1670 * @slot: slot to protect
1671 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1672 * @mask: indicates which pages we should protect
1673 *
1674 * Used when we do not need to care about huge page mappings: e.g. during dirty
1675 * logging we do not have any such mappings.
1676 */
3b0f1d01 1677static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
5dc99b23
TY
1678 struct kvm_memory_slot *slot,
1679 gfn_t gfn_offset, unsigned long mask)
a0ed4607 1680{
018aabb5 1681 struct kvm_rmap_head *rmap_head;
a0ed4607 1682
5dc99b23 1683 while (mask) {
018aabb5 1684 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
3bae0459 1685 PG_LEVEL_4K, slot);
018aabb5 1686 __rmap_write_protect(kvm, rmap_head, false);
05da4558 1687
5dc99b23
TY
1688 /* clear the first set bit */
1689 mask &= mask - 1;
1690 }
374cbac0
AK
1691}
1692
f4b4b180 1693/**
ac8d57e5
PF
1694 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1695 * protect the page if the D-bit isn't supported.
f4b4b180
KH
1696 * @kvm: kvm instance
1697 * @slot: slot to clear D-bit
1698 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1699 * @mask: indicates which pages we should clear D-bit
1700 *
1701 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1702 */
1703void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1704 struct kvm_memory_slot *slot,
1705 gfn_t gfn_offset, unsigned long mask)
1706{
018aabb5 1707 struct kvm_rmap_head *rmap_head;
f4b4b180
KH
1708
1709 while (mask) {
018aabb5 1710 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
3bae0459 1711 PG_LEVEL_4K, slot);
018aabb5 1712 __rmap_clear_dirty(kvm, rmap_head);
f4b4b180
KH
1713
1714 /* clear the first set bit */
1715 mask &= mask - 1;
1716 }
1717}
1718EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1719
3b0f1d01
KH
1720/**
1721 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1722 * PT level pages.
1723 *
1724 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1725 * enable dirty logging for them.
1726 *
1727 * Used when we do not need to care about huge page mappings: e.g. during dirty
1728 * logging we do not have any such mappings.
1729 */
1730void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1731 struct kvm_memory_slot *slot,
1732 gfn_t gfn_offset, unsigned long mask)
1733{
afaf0b2f
SC
1734 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1735 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
88178fd4
KH
1736 mask);
1737 else
1738 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
3b0f1d01
KH
1739}
1740
aeecee2e
XG
1741bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1742 struct kvm_memory_slot *slot, u64 gfn)
95d4c16c 1743{
018aabb5 1744 struct kvm_rmap_head *rmap_head;
5dc99b23 1745 int i;
2f84569f 1746 bool write_protected = false;
95d4c16c 1747
3bae0459 1748 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
018aabb5 1749 rmap_head = __gfn_to_rmap(gfn, i, slot);
aeecee2e 1750 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
5dc99b23
TY
1751 }
1752
1753 return write_protected;
95d4c16c
TY
1754}
1755
aeecee2e
XG
1756static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1757{
1758 struct kvm_memory_slot *slot;
1759
1760 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1761 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1762}
1763
018aabb5 1764static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
e930bffe 1765{
1e3f42f0
TY
1766 u64 *sptep;
1767 struct rmap_iterator iter;
6a49f85c 1768 bool flush = false;
e930bffe 1769
018aabb5 1770 while ((sptep = rmap_get_first(rmap_head, &iter))) {
6a49f85c 1771 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1e3f42f0 1772
e7912386 1773 pte_list_remove(rmap_head, sptep);
6a49f85c 1774 flush = true;
e930bffe 1775 }
1e3f42f0 1776
6a49f85c
XG
1777 return flush;
1778}
1779
018aabb5 1780static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
6a49f85c
XG
1781 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1782 unsigned long data)
1783{
018aabb5 1784 return kvm_zap_rmapp(kvm, rmap_head);
e930bffe
AA
1785}
1786
018aabb5 1787static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
8a9522d2
ALC
1788 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1789 unsigned long data)
3da0dd43 1790{
1e3f42f0
TY
1791 u64 *sptep;
1792 struct rmap_iterator iter;
3da0dd43 1793 int need_flush = 0;
1e3f42f0 1794 u64 new_spte;
3da0dd43 1795 pte_t *ptep = (pte_t *)data;
ba049e93 1796 kvm_pfn_t new_pfn;
3da0dd43
IE
1797
1798 WARN_ON(pte_huge(*ptep));
1799 new_pfn = pte_pfn(*ptep);
1e3f42f0 1800
0d536790 1801restart:
018aabb5 1802 for_each_rmap_spte(rmap_head, &iter, sptep) {
8a9522d2 1803 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
f160c7b7 1804 sptep, *sptep, gfn, level);
1e3f42f0 1805
3da0dd43 1806 need_flush = 1;
1e3f42f0 1807
3da0dd43 1808 if (pte_write(*ptep)) {
e7912386 1809 pte_list_remove(rmap_head, sptep);
0d536790 1810 goto restart;
3da0dd43 1811 } else {
1e3f42f0 1812 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
3da0dd43
IE
1813 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1814
1815 new_spte &= ~PT_WRITABLE_MASK;
1816 new_spte &= ~SPTE_HOST_WRITEABLE;
f160c7b7
JS
1817
1818 new_spte = mark_spte_for_access_track(new_spte);
1e3f42f0
TY
1819
1820 mmu_spte_clear_track_bits(sptep);
1821 mmu_spte_set(sptep, new_spte);
3da0dd43
IE
1822 }
1823 }
1e3f42f0 1824
3cc5ea94
LT
1825 if (need_flush && kvm_available_flush_tlb_with_range()) {
1826 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1827 return 0;
1828 }
1829
0cf853c5 1830 return need_flush;
3da0dd43
IE
1831}
1832
6ce1f4e2
XG
1833struct slot_rmap_walk_iterator {
1834 /* input fields. */
1835 struct kvm_memory_slot *slot;
1836 gfn_t start_gfn;
1837 gfn_t end_gfn;
1838 int start_level;
1839 int end_level;
1840
1841 /* output fields. */
1842 gfn_t gfn;
018aabb5 1843 struct kvm_rmap_head *rmap;
6ce1f4e2
XG
1844 int level;
1845
1846 /* private field. */
018aabb5 1847 struct kvm_rmap_head *end_rmap;
6ce1f4e2
XG
1848};
1849
1850static void
1851rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1852{
1853 iterator->level = level;
1854 iterator->gfn = iterator->start_gfn;
1855 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1856 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1857 iterator->slot);
1858}
1859
1860static void
1861slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1862 struct kvm_memory_slot *slot, int start_level,
1863 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1864{
1865 iterator->slot = slot;
1866 iterator->start_level = start_level;
1867 iterator->end_level = end_level;
1868 iterator->start_gfn = start_gfn;
1869 iterator->end_gfn = end_gfn;
1870
1871 rmap_walk_init_level(iterator, iterator->start_level);
1872}
1873
1874static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1875{
1876 return !!iterator->rmap;
1877}
1878
1879static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1880{
1881 if (++iterator->rmap <= iterator->end_rmap) {
1882 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1883 return;
1884 }
1885
1886 if (++iterator->level > iterator->end_level) {
1887 iterator->rmap = NULL;
1888 return;
1889 }
1890
1891 rmap_walk_init_level(iterator, iterator->level);
1892}
1893
1894#define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1895 _start_gfn, _end_gfn, _iter_) \
1896 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1897 _end_level_, _start_gfn, _end_gfn); \
1898 slot_rmap_walk_okay(_iter_); \
1899 slot_rmap_walk_next(_iter_))
1900
84504ef3
TY
1901static int kvm_handle_hva_range(struct kvm *kvm,
1902 unsigned long start,
1903 unsigned long end,
1904 unsigned long data,
1905 int (*handler)(struct kvm *kvm,
018aabb5 1906 struct kvm_rmap_head *rmap_head,
048212d0 1907 struct kvm_memory_slot *slot,
8a9522d2
ALC
1908 gfn_t gfn,
1909 int level,
84504ef3 1910 unsigned long data))
e930bffe 1911{
bc6678a3 1912 struct kvm_memslots *slots;
be6ba0f0 1913 struct kvm_memory_slot *memslot;
6ce1f4e2
XG
1914 struct slot_rmap_walk_iterator iterator;
1915 int ret = 0;
9da0e4d5 1916 int i;
bc6678a3 1917
9da0e4d5
PB
1918 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1919 slots = __kvm_memslots(kvm, i);
1920 kvm_for_each_memslot(memslot, slots) {
1921 unsigned long hva_start, hva_end;
1922 gfn_t gfn_start, gfn_end;
e930bffe 1923
9da0e4d5
PB
1924 hva_start = max(start, memslot->userspace_addr);
1925 hva_end = min(end, memslot->userspace_addr +
1926 (memslot->npages << PAGE_SHIFT));
1927 if (hva_start >= hva_end)
1928 continue;
1929 /*
1930 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1931 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1932 */
1933 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1934 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1935
3bae0459 1936 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
e662ec3e 1937 KVM_MAX_HUGEPAGE_LEVEL,
9da0e4d5
PB
1938 gfn_start, gfn_end - 1,
1939 &iterator)
1940 ret |= handler(kvm, iterator.rmap, memslot,
1941 iterator.gfn, iterator.level, data);
1942 }
e930bffe
AA
1943 }
1944
f395302e 1945 return ret;
e930bffe
AA
1946}
1947
84504ef3
TY
1948static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1949 unsigned long data,
018aabb5
TY
1950 int (*handler)(struct kvm *kvm,
1951 struct kvm_rmap_head *rmap_head,
048212d0 1952 struct kvm_memory_slot *slot,
8a9522d2 1953 gfn_t gfn, int level,
84504ef3
TY
1954 unsigned long data))
1955{
1956 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
e930bffe
AA
1957}
1958
b3ae2096
TY
1959int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1960{
1961 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1962}
1963
748c0e31 1964int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
3da0dd43 1965{
0cf853c5 1966 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA
1967}
1968
018aabb5 1969static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
8a9522d2
ALC
1970 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1971 unsigned long data)
e930bffe 1972{
1e3f42f0 1973 u64 *sptep;
79f702a6 1974 struct rmap_iterator uninitialized_var(iter);
e930bffe
AA
1975 int young = 0;
1976
f160c7b7
JS
1977 for_each_rmap_spte(rmap_head, &iter, sptep)
1978 young |= mmu_spte_age(sptep);
0d536790 1979
8a9522d2 1980 trace_kvm_age_page(gfn, level, slot, young);
e930bffe
AA
1981 return young;
1982}
1983
018aabb5 1984static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
8a9522d2
ALC
1985 struct kvm_memory_slot *slot, gfn_t gfn,
1986 int level, unsigned long data)
8ee53820 1987{
1e3f42f0
TY
1988 u64 *sptep;
1989 struct rmap_iterator iter;
8ee53820 1990
83ef6c81
JS
1991 for_each_rmap_spte(rmap_head, &iter, sptep)
1992 if (is_accessed_spte(*sptep))
1993 return 1;
83ef6c81 1994 return 0;
8ee53820
AA
1995}
1996
53a27b39
MT
1997#define RMAP_RECYCLE_THRESHOLD 1000
1998
852e3c19 1999static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39 2000{
018aabb5 2001 struct kvm_rmap_head *rmap_head;
852e3c19
JR
2002 struct kvm_mmu_page *sp;
2003
2004 sp = page_header(__pa(spte));
53a27b39 2005
018aabb5 2006 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
53a27b39 2007
018aabb5 2008 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
c3134ce2
LT
2009 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
2010 KVM_PAGES_PER_HPAGE(sp->role.level));
53a27b39
MT
2011}
2012
57128468 2013int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
e930bffe 2014{
57128468 2015 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
e930bffe
AA
2016}
2017
8ee53820
AA
2018int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2019{
2020 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
2021}
2022
d6c69ee9 2023#ifdef MMU_DEBUG
47ad8e68 2024static int is_empty_shadow_page(u64 *spt)
6aa8b732 2025{
139bdb2d
AK
2026 u64 *pos;
2027 u64 *end;
2028
47ad8e68 2029 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 2030 if (is_shadow_present_pte(*pos)) {
b8688d51 2031 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 2032 pos, *pos);
6aa8b732 2033 return 0;
139bdb2d 2034 }
6aa8b732
AK
2035 return 1;
2036}
d6c69ee9 2037#endif
6aa8b732 2038
45221ab6
DH
2039/*
2040 * This value is the sum of all of the kvm instances's
2041 * kvm->arch.n_used_mmu_pages values. We need a global,
2042 * aggregate version in order to make the slab shrinker
2043 * faster
2044 */
bc8a3d89 2045static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
45221ab6
DH
2046{
2047 kvm->arch.n_used_mmu_pages += nr;
2048 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2049}
2050
834be0d8 2051static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
260746c0 2052{
fa4a2c08 2053 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
7775834a 2054 hlist_del(&sp->hash_link);
bd4c86ea
XG
2055 list_del(&sp->link);
2056 free_page((unsigned long)sp->spt);
834be0d8
GN
2057 if (!sp->role.direct)
2058 free_page((unsigned long)sp->gfns);
e8ad9a70 2059 kmem_cache_free(mmu_page_header_cache, sp);
260746c0
AK
2060}
2061
cea0f0e7
AK
2062static unsigned kvm_page_table_hashfn(gfn_t gfn)
2063{
114df303 2064 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
cea0f0e7
AK
2065}
2066
714b93da 2067static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 2068 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 2069{
cea0f0e7
AK
2070 if (!parent_pte)
2071 return;
cea0f0e7 2072
67052b35 2073 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
cea0f0e7
AK
2074}
2075
4db35314 2076static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK
2077 u64 *parent_pte)
2078{
8daf3462 2079 __pte_list_remove(parent_pte, &sp->parent_ptes);
cea0f0e7
AK
2080}
2081
bcdd9a93
XG
2082static void drop_parent_pte(struct kvm_mmu_page *sp,
2083 u64 *parent_pte)
2084{
2085 mmu_page_remove_parent_pte(sp, parent_pte);
1df9f2dc 2086 mmu_spte_clear_no_track(parent_pte);
bcdd9a93
XG
2087}
2088
47005792 2089static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
ad8cfbe3 2090{
67052b35 2091 struct kvm_mmu_page *sp;
7ddca7e4 2092
80feb89a
TY
2093 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2094 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
67052b35 2095 if (!direct)
80feb89a 2096 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
67052b35 2097 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
002c5f73
SC
2098
2099 /*
2100 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
2101 * depends on valid pages being added to the head of the list. See
2102 * comments in kvm_zap_obsolete_pages().
2103 */
ca333add 2104 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
67052b35 2105 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
67052b35
XG
2106 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2107 return sp;
ad8cfbe3
MT
2108}
2109
67052b35 2110static void mark_unsync(u64 *spte);
1047df1f 2111static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 2112{
74c4e63a
TY
2113 u64 *sptep;
2114 struct rmap_iterator iter;
2115
2116 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2117 mark_unsync(sptep);
2118 }
0074ff63
MT
2119}
2120
67052b35 2121static void mark_unsync(u64 *spte)
0074ff63 2122{
67052b35 2123 struct kvm_mmu_page *sp;
1047df1f 2124 unsigned int index;
0074ff63 2125
67052b35 2126 sp = page_header(__pa(spte));
1047df1f
XG
2127 index = spte - sp->spt;
2128 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
0074ff63 2129 return;
1047df1f 2130 if (sp->unsync_children++)
0074ff63 2131 return;
1047df1f 2132 kvm_mmu_mark_parents_unsync(sp);
0074ff63
MT
2133}
2134
e8bc217a 2135static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
a4a8e6f7 2136 struct kvm_mmu_page *sp)
e8bc217a 2137{
1f50f1b3 2138 return 0;
e8bc217a
MT
2139}
2140
0f53b5b1
XG
2141static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2142 struct kvm_mmu_page *sp, u64 *spte,
7c562522 2143 const void *pte)
0f53b5b1
XG
2144{
2145 WARN_ON(1);
2146}
2147
60c8aec6
MT
2148#define KVM_PAGE_ARRAY_NR 16
2149
2150struct kvm_mmu_pages {
2151 struct mmu_page_and_offset {
2152 struct kvm_mmu_page *sp;
2153 unsigned int idx;
2154 } page[KVM_PAGE_ARRAY_NR];
2155 unsigned int nr;
2156};
2157
cded19f3
HE
2158static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2159 int idx)
4731d4c7 2160{
60c8aec6 2161 int i;
4731d4c7 2162
60c8aec6
MT
2163 if (sp->unsync)
2164 for (i=0; i < pvec->nr; i++)
2165 if (pvec->page[i].sp == sp)
2166 return 0;
2167
2168 pvec->page[pvec->nr].sp = sp;
2169 pvec->page[pvec->nr].idx = idx;
2170 pvec->nr++;
2171 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2172}
2173
fd951457
TY
2174static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2175{
2176 --sp->unsync_children;
2177 WARN_ON((int)sp->unsync_children < 0);
2178 __clear_bit(idx, sp->unsync_child_bitmap);
2179}
2180
60c8aec6
MT
2181static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2182 struct kvm_mmu_pages *pvec)
2183{
2184 int i, ret, nr_unsync_leaf = 0;
4731d4c7 2185
37178b8b 2186 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
7a8f1a74 2187 struct kvm_mmu_page *child;
4731d4c7
MT
2188 u64 ent = sp->spt[i];
2189
fd951457
TY
2190 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2191 clear_unsync_child_bit(sp, i);
2192 continue;
2193 }
7a8f1a74
XG
2194
2195 child = page_header(ent & PT64_BASE_ADDR_MASK);
2196
2197 if (child->unsync_children) {
2198 if (mmu_pages_add(pvec, child, i))
2199 return -ENOSPC;
2200
2201 ret = __mmu_unsync_walk(child, pvec);
fd951457
TY
2202 if (!ret) {
2203 clear_unsync_child_bit(sp, i);
2204 continue;
2205 } else if (ret > 0) {
7a8f1a74 2206 nr_unsync_leaf += ret;
fd951457 2207 } else
7a8f1a74
XG
2208 return ret;
2209 } else if (child->unsync) {
2210 nr_unsync_leaf++;
2211 if (mmu_pages_add(pvec, child, i))
2212 return -ENOSPC;
2213 } else
fd951457 2214 clear_unsync_child_bit(sp, i);
4731d4c7
MT
2215 }
2216
60c8aec6
MT
2217 return nr_unsync_leaf;
2218}
2219
e23d3fef
XG
2220#define INVALID_INDEX (-1)
2221
60c8aec6
MT
2222static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2223 struct kvm_mmu_pages *pvec)
2224{
0a47cd85 2225 pvec->nr = 0;
60c8aec6
MT
2226 if (!sp->unsync_children)
2227 return 0;
2228
e23d3fef 2229 mmu_pages_add(pvec, sp, INVALID_INDEX);
60c8aec6 2230 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT
2231}
2232
4731d4c7
MT
2233static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2234{
2235 WARN_ON(!sp->unsync);
5e1b3ddb 2236 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT
2237 sp->unsync = 0;
2238 --kvm->stat.mmu_unsync;
2239}
2240
83cdb568
SC
2241static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2242 struct list_head *invalid_list);
7775834a
XG
2243static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2244 struct list_head *invalid_list);
4731d4c7 2245
ac101b7c
SC
2246#define for_each_valid_sp(_kvm, _sp, _list) \
2247 hlist_for_each_entry(_sp, _list, hash_link) \
fac026da 2248 if (is_obsolete_sp((_kvm), (_sp))) { \
f3414bc7 2249 } else
1044b030
TY
2250
2251#define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
ac101b7c
SC
2252 for_each_valid_sp(_kvm, _sp, \
2253 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
f3414bc7 2254 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
7ae680eb 2255
47c42e6b
SC
2256static inline bool is_ept_sp(struct kvm_mmu_page *sp)
2257{
2258 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
2259}
2260
f918b443 2261/* @sp->gfn should be write-protected at the call site */
1f50f1b3
PB
2262static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2263 struct list_head *invalid_list)
4731d4c7 2264{
47c42e6b
SC
2265 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
2266 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
d98ba053 2267 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1f50f1b3 2268 return false;
4731d4c7
MT
2269 }
2270
1f50f1b3 2271 return true;
4731d4c7
MT
2272}
2273
a2113634
SC
2274static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2275 struct list_head *invalid_list,
2276 bool remote_flush)
2277{
cfd32acf 2278 if (!remote_flush && list_empty(invalid_list))
a2113634
SC
2279 return false;
2280
2281 if (!list_empty(invalid_list))
2282 kvm_mmu_commit_zap_page(kvm, invalid_list);
2283 else
2284 kvm_flush_remote_tlbs(kvm);
2285 return true;
2286}
2287
35a70510
PB
2288static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2289 struct list_head *invalid_list,
2290 bool remote_flush, bool local_flush)
1d9dc7e0 2291{
a2113634 2292 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
35a70510 2293 return;
d98ba053 2294
a2113634 2295 if (local_flush)
8c8560b8 2296 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1d9dc7e0
XG
2297}
2298
e37fa785
XG
2299#ifdef CONFIG_KVM_MMU_AUDIT
2300#include "mmu_audit.c"
2301#else
2302static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2303static void mmu_audit_disable(void) { }
2304#endif
2305
002c5f73
SC
2306static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2307{
fac026da
SC
2308 return sp->role.invalid ||
2309 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
002c5f73
SC
2310}
2311
1f50f1b3 2312static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d98ba053 2313 struct list_head *invalid_list)
1d9dc7e0 2314{
9a43c5d9
PB
2315 kvm_unlink_unsync_page(vcpu->kvm, sp);
2316 return __kvm_sync_page(vcpu, sp, invalid_list);
1d9dc7e0
XG
2317}
2318
9f1a122f 2319/* @gfn should be write-protected at the call site */
2a74003a
PB
2320static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2321 struct list_head *invalid_list)
9f1a122f 2322{
9f1a122f 2323 struct kvm_mmu_page *s;
2a74003a 2324 bool ret = false;
9f1a122f 2325
b67bfe0d 2326 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
7ae680eb 2327 if (!s->unsync)
9f1a122f
XG
2328 continue;
2329
3bae0459 2330 WARN_ON(s->role.level != PG_LEVEL_4K);
2a74003a 2331 ret |= kvm_sync_page(vcpu, s, invalid_list);
9f1a122f
XG
2332 }
2333
2a74003a 2334 return ret;
9f1a122f
XG
2335}
2336
60c8aec6 2337struct mmu_page_path {
2a7266a8
YZ
2338 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2339 unsigned int idx[PT64_ROOT_MAX_LEVEL];
4731d4c7
MT
2340};
2341
60c8aec6 2342#define for_each_sp(pvec, sp, parents, i) \
0a47cd85 2343 for (i = mmu_pages_first(&pvec, &parents); \
60c8aec6
MT
2344 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2345 i = mmu_pages_next(&pvec, &parents, i))
2346
cded19f3
HE
2347static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2348 struct mmu_page_path *parents,
2349 int i)
60c8aec6
MT
2350{
2351 int n;
2352
2353 for (n = i+1; n < pvec->nr; n++) {
2354 struct kvm_mmu_page *sp = pvec->page[n].sp;
0a47cd85
PB
2355 unsigned idx = pvec->page[n].idx;
2356 int level = sp->role.level;
60c8aec6 2357
0a47cd85 2358 parents->idx[level-1] = idx;
3bae0459 2359 if (level == PG_LEVEL_4K)
0a47cd85 2360 break;
60c8aec6 2361
0a47cd85 2362 parents->parent[level-2] = sp;
60c8aec6
MT
2363 }
2364
2365 return n;
2366}
2367
0a47cd85
PB
2368static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2369 struct mmu_page_path *parents)
2370{
2371 struct kvm_mmu_page *sp;
2372 int level;
2373
2374 if (pvec->nr == 0)
2375 return 0;
2376
e23d3fef
XG
2377 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2378
0a47cd85
PB
2379 sp = pvec->page[0].sp;
2380 level = sp->role.level;
3bae0459 2381 WARN_ON(level == PG_LEVEL_4K);
0a47cd85
PB
2382
2383 parents->parent[level-2] = sp;
2384
2385 /* Also set up a sentinel. Further entries in pvec are all
2386 * children of sp, so this element is never overwritten.
2387 */
2388 parents->parent[level-1] = NULL;
2389 return mmu_pages_next(pvec, parents, 0);
2390}
2391
cded19f3 2392static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 2393{
60c8aec6
MT
2394 struct kvm_mmu_page *sp;
2395 unsigned int level = 0;
2396
2397 do {
2398 unsigned int idx = parents->idx[level];
60c8aec6
MT
2399 sp = parents->parent[level];
2400 if (!sp)
2401 return;
2402
e23d3fef 2403 WARN_ON(idx == INVALID_INDEX);
fd951457 2404 clear_unsync_child_bit(sp, idx);
60c8aec6 2405 level++;
0a47cd85 2406 } while (!sp->unsync_children);
60c8aec6 2407}
4731d4c7 2408
60c8aec6
MT
2409static void mmu_sync_children(struct kvm_vcpu *vcpu,
2410 struct kvm_mmu_page *parent)
2411{
2412 int i;
2413 struct kvm_mmu_page *sp;
2414 struct mmu_page_path parents;
2415 struct kvm_mmu_pages pages;
d98ba053 2416 LIST_HEAD(invalid_list);
50c9e6f3 2417 bool flush = false;
60c8aec6 2418
60c8aec6 2419 while (mmu_unsync_walk(parent, &pages)) {
2f84569f 2420 bool protected = false;
b1a36821
MT
2421
2422 for_each_sp(pages, sp, parents, i)
54bf36aa 2423 protected |= rmap_write_protect(vcpu, sp->gfn);
b1a36821 2424
50c9e6f3 2425 if (protected) {
b1a36821 2426 kvm_flush_remote_tlbs(vcpu->kvm);
50c9e6f3
PB
2427 flush = false;
2428 }
b1a36821 2429
60c8aec6 2430 for_each_sp(pages, sp, parents, i) {
1f50f1b3 2431 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
60c8aec6
MT
2432 mmu_pages_clear_parents(&parents);
2433 }
50c9e6f3
PB
2434 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2435 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2436 cond_resched_lock(&vcpu->kvm->mmu_lock);
2437 flush = false;
2438 }
60c8aec6 2439 }
50c9e6f3
PB
2440
2441 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
4731d4c7
MT
2442}
2443
a30f47cb
XG
2444static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2445{
e5691a81 2446 atomic_set(&sp->write_flooding_count, 0);
a30f47cb
XG
2447}
2448
2449static void clear_sp_write_flooding_count(u64 *spte)
2450{
2451 struct kvm_mmu_page *sp = page_header(__pa(spte));
2452
2453 __clear_sp_write_flooding_count(sp);
2454}
2455
cea0f0e7
AK
2456static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2457 gfn_t gfn,
2458 gva_t gaddr,
2459 unsigned level,
f6e2c02b 2460 int direct,
0a2b64c5 2461 unsigned int access)
cea0f0e7 2462{
fb58a9c3 2463 bool direct_mmu = vcpu->arch.mmu->direct_map;
cea0f0e7 2464 union kvm_mmu_page_role role;
ac101b7c 2465 struct hlist_head *sp_list;
cea0f0e7 2466 unsigned quadrant;
9f1a122f 2467 struct kvm_mmu_page *sp;
9f1a122f 2468 bool need_sync = false;
2a74003a 2469 bool flush = false;
f3414bc7 2470 int collisions = 0;
2a74003a 2471 LIST_HEAD(invalid_list);
cea0f0e7 2472
36d9594d 2473 role = vcpu->arch.mmu->mmu_role.base;
cea0f0e7 2474 role.level = level;
f6e2c02b 2475 role.direct = direct;
84b0c8c6 2476 if (role.direct)
47c42e6b 2477 role.gpte_is_8_bytes = true;
41074d07 2478 role.access = access;
fb58a9c3 2479 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK
2480 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2481 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2482 role.quadrant = quadrant;
2483 }
ac101b7c
SC
2484
2485 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2486 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
f3414bc7
DM
2487 if (sp->gfn != gfn) {
2488 collisions++;
2489 continue;
2490 }
2491
7ae680eb
XG
2492 if (!need_sync && sp->unsync)
2493 need_sync = true;
4731d4c7 2494
7ae680eb
XG
2495 if (sp->role.word != role.word)
2496 continue;
4731d4c7 2497
fb58a9c3
SC
2498 if (direct_mmu)
2499 goto trace_get_page;
2500
2a74003a
PB
2501 if (sp->unsync) {
2502 /* The page is good, but __kvm_sync_page might still end
2503 * up zapping it. If so, break in order to rebuild it.
2504 */
2505 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2506 break;
2507
2508 WARN_ON(!list_empty(&invalid_list));
8c8560b8 2509 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2a74003a 2510 }
e02aa901 2511
98bba238 2512 if (sp->unsync_children)
8c8560b8 2513 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
e02aa901 2514
a30f47cb 2515 __clear_sp_write_flooding_count(sp);
fb58a9c3
SC
2516
2517trace_get_page:
7ae680eb 2518 trace_kvm_mmu_get_page(sp, false);
f3414bc7 2519 goto out;
7ae680eb 2520 }
47005792 2521
dfc5aa00 2522 ++vcpu->kvm->stat.mmu_cache_miss;
47005792
TY
2523
2524 sp = kvm_mmu_alloc_page(vcpu, direct);
2525
4db35314
AK
2526 sp->gfn = gfn;
2527 sp->role = role;
ac101b7c 2528 hlist_add_head(&sp->hash_link, sp_list);
f6e2c02b 2529 if (!direct) {
56ca57f9
XG
2530 /*
2531 * we should do write protection before syncing pages
2532 * otherwise the content of the synced shadow page may
2533 * be inconsistent with guest page table.
2534 */
2535 account_shadowed(vcpu->kvm, sp);
3bae0459 2536 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
c3134ce2 2537 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
9f1a122f 2538
3bae0459 2539 if (level > PG_LEVEL_4K && need_sync)
2a74003a 2540 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
4731d4c7 2541 }
77492664 2542 clear_page(sp->spt);
f691fe1d 2543 trace_kvm_mmu_get_page(sp, true);
2a74003a
PB
2544
2545 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
f3414bc7
DM
2546out:
2547 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2548 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
4db35314 2549 return sp;
cea0f0e7
AK
2550}
2551
7eb77e9f
JS
2552static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2553 struct kvm_vcpu *vcpu, hpa_t root,
2554 u64 addr)
2d11123a
AK
2555{
2556 iterator->addr = addr;
7eb77e9f 2557 iterator->shadow_addr = root;
44dd3ffa 2558 iterator->level = vcpu->arch.mmu->shadow_root_level;
81407ca5 2559
2a7266a8 2560 if (iterator->level == PT64_ROOT_4LEVEL &&
44dd3ffa
VK
2561 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2562 !vcpu->arch.mmu->direct_map)
81407ca5
JR
2563 --iterator->level;
2564
2d11123a 2565 if (iterator->level == PT32E_ROOT_LEVEL) {
7eb77e9f
JS
2566 /*
2567 * prev_root is currently only used for 64-bit hosts. So only
2568 * the active root_hpa is valid here.
2569 */
44dd3ffa 2570 BUG_ON(root != vcpu->arch.mmu->root_hpa);
7eb77e9f 2571
2d11123a 2572 iterator->shadow_addr
44dd3ffa 2573 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2d11123a
AK
2574 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2575 --iterator->level;
2576 if (!iterator->shadow_addr)
2577 iterator->level = 0;
2578 }
2579}
2580
7eb77e9f
JS
2581static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2582 struct kvm_vcpu *vcpu, u64 addr)
2583{
44dd3ffa 2584 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
7eb77e9f
JS
2585 addr);
2586}
2587
2d11123a
AK
2588static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2589{
3bae0459 2590 if (iterator->level < PG_LEVEL_4K)
2d11123a 2591 return false;
4d88954d 2592
2d11123a
AK
2593 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2594 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2595 return true;
2596}
2597
c2a2ac2b
XG
2598static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2599 u64 spte)
2d11123a 2600{
c2a2ac2b 2601 if (is_last_spte(spte, iterator->level)) {
052331be
XG
2602 iterator->level = 0;
2603 return;
2604 }
2605
c2a2ac2b 2606 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2d11123a
AK
2607 --iterator->level;
2608}
2609
c2a2ac2b
XG
2610static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2611{
bb606a9b 2612 __shadow_walk_next(iterator, *iterator->sptep);
c2a2ac2b
XG
2613}
2614
98bba238
TY
2615static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2616 struct kvm_mmu_page *sp)
32ef26a3
AK
2617{
2618 u64 spte;
2619
ffb128c8 2620 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
7a1638ce 2621
ffb128c8 2622 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
d0ec49d4 2623 shadow_user_mask | shadow_x_mask | shadow_me_mask;
ac8d57e5
PF
2624
2625 if (sp_ad_disabled(sp))
6eeb4ef0 2626 spte |= SPTE_AD_DISABLED_MASK;
ac8d57e5
PF
2627 else
2628 spte |= shadow_accessed_mask;
24db2734 2629
1df9f2dc 2630 mmu_spte_set(sptep, spte);
98bba238
TY
2631
2632 mmu_page_add_parent_pte(vcpu, sp, sptep);
2633
2634 if (sp->unsync_children || sp->unsync)
2635 mark_unsync(sptep);
32ef26a3
AK
2636}
2637
a357bd22
AK
2638static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2639 unsigned direct_access)
2640{
2641 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2642 struct kvm_mmu_page *child;
2643
2644 /*
2645 * For the direct sp, if the guest pte's dirty bit
2646 * changed form clean to dirty, it will corrupt the
2647 * sp's access: allow writable in the read-only sp,
2648 * so we should update the spte at this point to get
2649 * a new sp with the correct access.
2650 */
2651 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2652 if (child->role.access == direct_access)
2653 return;
2654
bcdd9a93 2655 drop_parent_pte(child, sptep);
c3134ce2 2656 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
a357bd22
AK
2657 }
2658}
2659
505aef8f 2660static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
38e3b2b2
XG
2661 u64 *spte)
2662{
2663 u64 pte;
2664 struct kvm_mmu_page *child;
2665
2666 pte = *spte;
2667 if (is_shadow_present_pte(pte)) {
505aef8f 2668 if (is_last_spte(pte, sp->role.level)) {
c3707958 2669 drop_spte(kvm, spte);
505aef8f
XG
2670 if (is_large_pte(pte))
2671 --kvm->stat.lpages;
2672 } else {
38e3b2b2 2673 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 2674 drop_parent_pte(child, spte);
38e3b2b2 2675 }
505aef8f
XG
2676 return true;
2677 }
2678
2679 if (is_mmio_spte(pte))
ce88decf 2680 mmu_spte_clear_no_track(spte);
c3707958 2681
505aef8f 2682 return false;
38e3b2b2
XG
2683}
2684
90cb0529 2685static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 2686 struct kvm_mmu_page *sp)
a436036b 2687{
697fe2e2 2688 unsigned i;
697fe2e2 2689
38e3b2b2
XG
2690 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2691 mmu_page_zap_pte(kvm, sp, sp->spt + i);
a436036b
AK
2692}
2693
31aa2b44 2694static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b 2695{
1e3f42f0
TY
2696 u64 *sptep;
2697 struct rmap_iterator iter;
a436036b 2698
018aabb5 2699 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
1e3f42f0 2700 drop_parent_pte(sp, sptep);
31aa2b44
AK
2701}
2702
60c8aec6 2703static int mmu_zap_unsync_children(struct kvm *kvm,
7775834a
XG
2704 struct kvm_mmu_page *parent,
2705 struct list_head *invalid_list)
4731d4c7 2706{
60c8aec6
MT
2707 int i, zapped = 0;
2708 struct mmu_page_path parents;
2709 struct kvm_mmu_pages pages;
4731d4c7 2710
3bae0459 2711 if (parent->role.level == PG_LEVEL_4K)
4731d4c7 2712 return 0;
60c8aec6 2713
60c8aec6
MT
2714 while (mmu_unsync_walk(parent, &pages)) {
2715 struct kvm_mmu_page *sp;
2716
2717 for_each_sp(pages, sp, parents, i) {
7775834a 2718 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
60c8aec6 2719 mmu_pages_clear_parents(&parents);
77662e00 2720 zapped++;
60c8aec6 2721 }
60c8aec6
MT
2722 }
2723
2724 return zapped;
4731d4c7
MT
2725}
2726
83cdb568
SC
2727static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2728 struct kvm_mmu_page *sp,
2729 struct list_head *invalid_list,
2730 int *nr_zapped)
31aa2b44 2731{
83cdb568 2732 bool list_unstable;
f691fe1d 2733
7775834a 2734 trace_kvm_mmu_prepare_zap_page(sp);
31aa2b44 2735 ++kvm->stat.mmu_shadow_zapped;
83cdb568 2736 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
4db35314 2737 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 2738 kvm_mmu_unlink_parents(kvm, sp);
5304b8d3 2739
83cdb568
SC
2740 /* Zapping children means active_mmu_pages has become unstable. */
2741 list_unstable = *nr_zapped;
2742
f6e2c02b 2743 if (!sp->role.invalid && !sp->role.direct)
3ed1a478 2744 unaccount_shadowed(kvm, sp);
5304b8d3 2745
4731d4c7
MT
2746 if (sp->unsync)
2747 kvm_unlink_unsync_page(kvm, sp);
4db35314 2748 if (!sp->root_count) {
54a4f023 2749 /* Count self */
83cdb568 2750 (*nr_zapped)++;
7775834a 2751 list_move(&sp->link, invalid_list);
aa6bd187 2752 kvm_mod_used_mmu_pages(kvm, -1);
2e53d63a 2753 } else {
5b5c6a5a 2754 list_move(&sp->link, &kvm->arch.active_mmu_pages);
05988d72 2755
10605204
SC
2756 /*
2757 * Obsolete pages cannot be used on any vCPUs, see the comment
2758 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2759 * treats invalid shadow pages as being obsolete.
2760 */
2761 if (!is_obsolete_sp(kvm, sp))
05988d72 2762 kvm_reload_remote_mmus(kvm);
2e53d63a 2763 }
7775834a 2764
b8e8c830
PB
2765 if (sp->lpage_disallowed)
2766 unaccount_huge_nx_page(kvm, sp);
2767
7775834a 2768 sp->role.invalid = 1;
83cdb568
SC
2769 return list_unstable;
2770}
2771
2772static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2773 struct list_head *invalid_list)
2774{
2775 int nr_zapped;
2776
2777 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2778 return nr_zapped;
a436036b
AK
2779}
2780
7775834a
XG
2781static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2782 struct list_head *invalid_list)
2783{
945315b9 2784 struct kvm_mmu_page *sp, *nsp;
7775834a
XG
2785
2786 if (list_empty(invalid_list))
2787 return;
2788
c142786c 2789 /*
9753f529
LT
2790 * We need to make sure everyone sees our modifications to
2791 * the page tables and see changes to vcpu->mode here. The barrier
2792 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2793 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2794 *
2795 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2796 * guest mode and/or lockless shadow page table walks.
c142786c
AK
2797 */
2798 kvm_flush_remote_tlbs(kvm);
c2a2ac2b 2799
945315b9 2800 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
7775834a 2801 WARN_ON(!sp->role.invalid || sp->root_count);
aa6bd187 2802 kvm_mmu_free_page(sp);
945315b9 2803 }
7775834a
XG
2804}
2805
5da59607
TY
2806static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2807 struct list_head *invalid_list)
2808{
2809 struct kvm_mmu_page *sp;
2810
2811 if (list_empty(&kvm->arch.active_mmu_pages))
2812 return false;
2813
d74c0e6b
GT
2814 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2815 struct kvm_mmu_page, link);
42bcbebf 2816 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
5da59607
TY
2817}
2818
ba7888dd
SC
2819static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2820{
2821 LIST_HEAD(invalid_list);
2822
2823 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
2824 return 0;
2825
2826 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
2827 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
2828 break;
2829
2830 ++vcpu->kvm->stat.mmu_recycled;
2831 }
2832 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2833
2834 if (!kvm_mmu_available_pages(vcpu->kvm))
2835 return -ENOSPC;
2836 return 0;
2837}
2838
82ce2c96
IE
2839/*
2840 * Changing the number of mmu pages allocated to the vm
49d5ca26 2841 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
82ce2c96 2842 */
bc8a3d89 2843void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
82ce2c96 2844{
d98ba053 2845 LIST_HEAD(invalid_list);
82ce2c96 2846
b34cb590
TY
2847 spin_lock(&kvm->mmu_lock);
2848
49d5ca26 2849 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
5da59607
TY
2850 /* Need to free some mmu pages to achieve the goal. */
2851 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2852 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2853 break;
82ce2c96 2854
aa6bd187 2855 kvm_mmu_commit_zap_page(kvm, &invalid_list);
49d5ca26 2856 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
82ce2c96 2857 }
82ce2c96 2858
49d5ca26 2859 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
b34cb590
TY
2860
2861 spin_unlock(&kvm->mmu_lock);
82ce2c96
IE
2862}
2863
1cb3f3ae 2864int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b 2865{
4db35314 2866 struct kvm_mmu_page *sp;
d98ba053 2867 LIST_HEAD(invalid_list);
a436036b
AK
2868 int r;
2869
9ad17b10 2870 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
a436036b 2871 r = 0;
1cb3f3ae 2872 spin_lock(&kvm->mmu_lock);
b67bfe0d 2873 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
9ad17b10 2874 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
7ae680eb
XG
2875 sp->role.word);
2876 r = 1;
f41d335a 2877 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
7ae680eb 2878 }
d98ba053 2879 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1cb3f3ae
XG
2880 spin_unlock(&kvm->mmu_lock);
2881
a436036b 2882 return r;
cea0f0e7 2883}
1cb3f3ae 2884EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
cea0f0e7 2885
5c520e90 2886static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
9cf5cf5a
XG
2887{
2888 trace_kvm_mmu_unsync_page(sp);
2889 ++vcpu->kvm->stat.mmu_unsync;
2890 sp->unsync = 1;
2891
2892 kvm_mmu_mark_parents_unsync(sp);
9cf5cf5a
XG
2893}
2894
3d0c27ad
XG
2895static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2896 bool can_unsync)
4731d4c7 2897{
5c520e90 2898 struct kvm_mmu_page *sp;
4731d4c7 2899
3d0c27ad
XG
2900 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2901 return true;
9cf5cf5a 2902
5c520e90 2903 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
36a2e677 2904 if (!can_unsync)
3d0c27ad 2905 return true;
36a2e677 2906
5c520e90
XG
2907 if (sp->unsync)
2908 continue;
9cf5cf5a 2909
3bae0459 2910 WARN_ON(sp->role.level != PG_LEVEL_4K);
5c520e90 2911 kvm_unsync_page(vcpu, sp);
4731d4c7 2912 }
3d0c27ad 2913
578e1c4d
JS
2914 /*
2915 * We need to ensure that the marking of unsync pages is visible
2916 * before the SPTE is updated to allow writes because
2917 * kvm_mmu_sync_roots() checks the unsync flags without holding
2918 * the MMU lock and so can race with this. If the SPTE was updated
2919 * before the page had been marked as unsync-ed, something like the
2920 * following could happen:
2921 *
2922 * CPU 1 CPU 2
2923 * ---------------------------------------------------------------------
2924 * 1.2 Host updates SPTE
2925 * to be writable
2926 * 2.1 Guest writes a GPTE for GVA X.
2927 * (GPTE being in the guest page table shadowed
2928 * by the SP from CPU 1.)
2929 * This reads SPTE during the page table walk.
2930 * Since SPTE.W is read as 1, there is no
2931 * fault.
2932 *
2933 * 2.2 Guest issues TLB flush.
2934 * That causes a VM Exit.
2935 *
2936 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2937 * Since it is false, so it just returns.
2938 *
2939 * 2.4 Guest accesses GVA X.
2940 * Since the mapping in the SP was not updated,
2941 * so the old mapping for GVA X incorrectly
2942 * gets used.
2943 * 1.1 Host marks SP
2944 * as unsync
2945 * (sp->unsync = true)
2946 *
2947 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2948 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2949 * pairs with this write barrier.
2950 */
2951 smp_wmb();
2952
3d0c27ad 2953 return false;
4731d4c7
MT
2954}
2955
ba049e93 2956static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
d1fe9219
PB
2957{
2958 if (pfn_valid(pfn))
aa2e063a
HZ
2959 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2960 /*
2961 * Some reserved pages, such as those from NVDIMM
2962 * DAX devices, are not for MMIO, and can be mapped
2963 * with cached memory type for better performance.
2964 * However, the above check misconceives those pages
2965 * as MMIO, and results in KVM mapping them with UC
2966 * memory type, which would hurt the performance.
2967 * Therefore, we check the host memory type in addition
2968 * and only treat UC/UC-/WC pages as MMIO.
2969 */
2970 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
d1fe9219 2971
0c55671f
KA
2972 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
2973 pfn_to_hpa(pfn + 1) - 1,
2974 E820_TYPE_RAM);
d1fe9219
PB
2975}
2976
5ce4786f
JS
2977/* Bits which may be returned by set_spte() */
2978#define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2979#define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2980
d555c333 2981static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
0a2b64c5 2982 unsigned int pte_access, int level,
ba049e93 2983 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
9bdbba13 2984 bool can_unsync, bool host_writable)
1c4f1fd6 2985{
ffb128c8 2986 u64 spte = 0;
1e73f9dd 2987 int ret = 0;
ac8d57e5 2988 struct kvm_mmu_page *sp;
64d4d521 2989
54bf36aa 2990 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
ce88decf
XG
2991 return 0;
2992
ac8d57e5
PF
2993 sp = page_header(__pa(sptep));
2994 if (sp_ad_disabled(sp))
6eeb4ef0 2995 spte |= SPTE_AD_DISABLED_MASK;
1f4e5fc8
PB
2996 else if (kvm_vcpu_ad_need_write_protect(vcpu))
2997 spte |= SPTE_AD_WRPROT_ONLY_MASK;
ac8d57e5 2998
d95c5568
BD
2999 /*
3000 * For the EPT case, shadow_present_mask is 0 if hardware
3001 * supports exec-only page table entries. In that case,
3002 * ACC_USER_MASK and shadow_user_mask are used to represent
3003 * read access. See FNAME(gpte_access) in paging_tmpl.h.
3004 */
ffb128c8 3005 spte |= shadow_present_mask;
947da538 3006 if (!speculative)
ac8d57e5 3007 spte |= spte_shadow_accessed_mask(spte);
640d9b0d 3008
3bae0459 3009 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) &&
b8e8c830
PB
3010 is_nx_huge_page_enabled()) {
3011 pte_access &= ~ACC_EXEC_MASK;
3012 }
3013
7b52345e
SY
3014 if (pte_access & ACC_EXEC_MASK)
3015 spte |= shadow_x_mask;
3016 else
3017 spte |= shadow_nx_mask;
49fde340 3018
1c4f1fd6 3019 if (pte_access & ACC_USER_MASK)
7b52345e 3020 spte |= shadow_user_mask;
49fde340 3021
3bae0459 3022 if (level > PG_LEVEL_4K)
05da4558 3023 spte |= PT_PAGE_SIZE_MASK;
b0bc3ee2 3024 if (tdp_enabled)
afaf0b2f 3025 spte |= kvm_x86_ops.get_mt_mask(vcpu, gfn,
d1fe9219 3026 kvm_is_mmio_pfn(pfn));
1c4f1fd6 3027
9bdbba13 3028 if (host_writable)
1403283a 3029 spte |= SPTE_HOST_WRITEABLE;
f8e453b0
XG
3030 else
3031 pte_access &= ~ACC_WRITE_MASK;
1403283a 3032
daaf216c
TL
3033 if (!kvm_is_mmio_pfn(pfn))
3034 spte |= shadow_me_mask;
3035
35149e21 3036 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6 3037
c2288505 3038 if (pte_access & ACC_WRITE_MASK) {
49fde340 3039 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
1c4f1fd6 3040
ecc5589f
MT
3041 /*
3042 * Optimization: for pte sync, if spte was writable the hash
3043 * lookup is unnecessary (and expensive). Write protection
3044 * is responsibility of mmu_get_page / kvm_sync_page.
3045 * Same reasoning can be applied to dirty page accounting.
3046 */
8dae4445 3047 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT
3048 goto set_pte;
3049
4731d4c7 3050 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
9ad17b10 3051 pgprintk("%s: found shadow page for %llx, marking ro\n",
b8688d51 3052 __func__, gfn);
5ce4786f 3053 ret |= SET_SPTE_WRITE_PROTECTED_PT;
1c4f1fd6 3054 pte_access &= ~ACC_WRITE_MASK;
49fde340 3055 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
1c4f1fd6
AK
3056 }
3057 }
3058
9b51a630 3059 if (pte_access & ACC_WRITE_MASK) {
54bf36aa 3060 kvm_vcpu_mark_page_dirty(vcpu, gfn);
ac8d57e5 3061 spte |= spte_shadow_dirty_mask(spte);
9b51a630 3062 }
1c4f1fd6 3063
f160c7b7
JS
3064 if (speculative)
3065 spte = mark_spte_for_access_track(spte);
3066
38187c83 3067set_pte:
6e7d0354 3068 if (mmu_spte_update(sptep, spte))
5ce4786f 3069 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
1e73f9dd
MT
3070 return ret;
3071}
3072
0a2b64c5
BG
3073static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
3074 unsigned int pte_access, int write_fault, int level,
3075 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
3076 bool host_writable)
1e73f9dd
MT
3077{
3078 int was_rmapped = 0;
53a27b39 3079 int rmap_count;
5ce4786f 3080 int set_spte_ret;
9b8ebbdb 3081 int ret = RET_PF_RETRY;
c2a4eadf 3082 bool flush = false;
1e73f9dd 3083
f7616203
XG
3084 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3085 *sptep, write_fault, gfn);
1e73f9dd 3086
afd28fe1 3087 if (is_shadow_present_pte(*sptep)) {
1e73f9dd
MT
3088 /*
3089 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3090 * the parent of the now unreachable PTE.
3091 */
3bae0459 3092 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
1e73f9dd 3093 struct kvm_mmu_page *child;
d555c333 3094 u64 pte = *sptep;
1e73f9dd
MT
3095
3096 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 3097 drop_parent_pte(child, sptep);
c2a4eadf 3098 flush = true;
d555c333 3099 } else if (pfn != spte_to_pfn(*sptep)) {
9ad17b10 3100 pgprintk("hfn old %llx new %llx\n",
d555c333 3101 spte_to_pfn(*sptep), pfn);
c3707958 3102 drop_spte(vcpu->kvm, sptep);
c2a4eadf 3103 flush = true;
6bed6b9e
JR
3104 } else
3105 was_rmapped = 1;
1e73f9dd 3106 }
852e3c19 3107
5ce4786f
JS
3108 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3109 speculative, true, host_writable);
3110 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
1e73f9dd 3111 if (write_fault)
9b8ebbdb 3112 ret = RET_PF_EMULATE;
8c8560b8 3113 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
a378b4e6 3114 }
c3134ce2 3115
c2a4eadf 3116 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
c3134ce2
LT
3117 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3118 KVM_PAGES_PER_HPAGE(level));
1e73f9dd 3119
029499b4 3120 if (unlikely(is_mmio_spte(*sptep)))
9b8ebbdb 3121 ret = RET_PF_EMULATE;
ce88decf 3122
d555c333 3123 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
335e192a 3124 trace_kvm_mmu_set_spte(level, gfn, sptep);
d555c333 3125 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT
3126 ++vcpu->kvm->stat.lpages;
3127
ffb61bb3 3128 if (is_shadow_present_pte(*sptep)) {
ffb61bb3
XG
3129 if (!was_rmapped) {
3130 rmap_count = rmap_add(vcpu, sptep, gfn);
3131 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3132 rmap_recycle(vcpu, sptep, gfn);
3133 }
1c4f1fd6 3134 }
cb9aaa30 3135
9b8ebbdb 3136 return ret;
1c4f1fd6
AK
3137}
3138
ba049e93 3139static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
957ed9ef
XG
3140 bool no_dirty_log)
3141{
3142 struct kvm_memory_slot *slot;
957ed9ef 3143
5d163b1c 3144 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
903816fa 3145 if (!slot)
6c8ee57b 3146 return KVM_PFN_ERR_FAULT;
957ed9ef 3147
037d92dc 3148 return gfn_to_pfn_memslot_atomic(slot, gfn);
957ed9ef
XG
3149}
3150
3151static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3152 struct kvm_mmu_page *sp,
3153 u64 *start, u64 *end)
3154{
3155 struct page *pages[PTE_PREFETCH_NUM];
d9ef13c2 3156 struct kvm_memory_slot *slot;
0a2b64c5 3157 unsigned int access = sp->role.access;
957ed9ef
XG
3158 int i, ret;
3159 gfn_t gfn;
3160
3161 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
d9ef13c2
PB
3162 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3163 if (!slot)
957ed9ef
XG
3164 return -1;
3165
d9ef13c2 3166 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
957ed9ef
XG
3167 if (ret <= 0)
3168 return -1;
3169
43fdcda9 3170 for (i = 0; i < ret; i++, gfn++, start++) {
029499b4
TY
3171 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3172 page_to_pfn(pages[i]), true, true);
43fdcda9
JS
3173 put_page(pages[i]);
3174 }
957ed9ef
XG
3175
3176 return 0;
3177}
3178
3179static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3180 struct kvm_mmu_page *sp, u64 *sptep)
3181{
3182 u64 *spte, *start = NULL;
3183 int i;
3184
3185 WARN_ON(!sp->role.direct);
3186
3187 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3188 spte = sp->spt + i;
3189
3190 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
c3707958 3191 if (is_shadow_present_pte(*spte) || spte == sptep) {
957ed9ef
XG
3192 if (!start)
3193 continue;
3194 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3195 break;
3196 start = NULL;
3197 } else if (!start)
3198 start = spte;
3199 }
3200}
3201
3202static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3203{
3204 struct kvm_mmu_page *sp;
3205
ac8d57e5
PF
3206 sp = page_header(__pa(sptep));
3207
957ed9ef 3208 /*
ac8d57e5
PF
3209 * Without accessed bits, there's no way to distinguish between
3210 * actually accessed translations and prefetched, so disable pte
3211 * prefetch if accessed bits aren't available.
957ed9ef 3212 */
ac8d57e5 3213 if (sp_ad_disabled(sp))
957ed9ef
XG
3214 return;
3215
3bae0459 3216 if (sp->role.level > PG_LEVEL_4K)
957ed9ef
XG
3217 return;
3218
3219 __direct_pte_prefetch(vcpu, sp, sptep);
3220}
3221
db543216 3222static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
293e306e 3223 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
db543216 3224{
db543216
SC
3225 unsigned long hva;
3226 pte_t *pte;
3227 int level;
3228
e851265a 3229 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
3bae0459 3230 return PG_LEVEL_4K;
db543216 3231
293e306e
SC
3232 /*
3233 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
3234 * is not solely for performance, it's also necessary to avoid the
3235 * "writable" check in __gfn_to_hva_many(), which will always fail on
3236 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
3237 * page fault steps have already verified the guest isn't writing a
3238 * read-only memslot.
3239 */
db543216
SC
3240 hva = __gfn_to_hva_memslot(slot, gfn);
3241
3242 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
3243 if (unlikely(!pte))
3bae0459 3244 return PG_LEVEL_4K;
db543216
SC
3245
3246 return level;
3247}
3248
83f06fa7
SC
3249static int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
3250 int max_level, kvm_pfn_t *pfnp)
0885904d 3251{
293e306e 3252 struct kvm_memory_slot *slot;
2c0629f4 3253 struct kvm_lpage_info *linfo;
0885904d 3254 kvm_pfn_t pfn = *pfnp;
17eff019 3255 kvm_pfn_t mask;
83f06fa7 3256 int level;
17eff019 3257
3bae0459
SC
3258 if (unlikely(max_level == PG_LEVEL_4K))
3259 return PG_LEVEL_4K;
17eff019 3260
e851265a 3261 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
3bae0459 3262 return PG_LEVEL_4K;
17eff019 3263
293e306e
SC
3264 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
3265 if (!slot)
3bae0459 3266 return PG_LEVEL_4K;
293e306e 3267
703c335d 3268 max_level = min(max_level, max_page_level);
3bae0459 3269 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2c0629f4
SC
3270 linfo = lpage_info_slot(gfn, slot, max_level);
3271 if (!linfo->disallow_lpage)
293e306e
SC
3272 break;
3273 }
3274
3bae0459
SC
3275 if (max_level == PG_LEVEL_4K)
3276 return PG_LEVEL_4K;
293e306e
SC
3277
3278 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
3bae0459 3279 if (level == PG_LEVEL_4K)
83f06fa7 3280 return level;
17eff019 3281
db543216 3282 level = min(level, max_level);
0885904d
SC
3283
3284 /*
17eff019
SC
3285 * mmu_notifier_retry() was successful and mmu_lock is held, so
3286 * the pmd can't be split from under us.
0885904d 3287 */
17eff019
SC
3288 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3289 VM_BUG_ON((gfn & mask) != (pfn & mask));
3290 *pfnp = pfn & ~mask;
83f06fa7
SC
3291
3292 return level;
0885904d
SC
3293}
3294
b8e8c830
PB
3295static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it,
3296 gfn_t gfn, kvm_pfn_t *pfnp, int *levelp)
3297{
3298 int level = *levelp;
3299 u64 spte = *it.sptep;
3300
3bae0459 3301 if (it.level == level && level > PG_LEVEL_4K &&
b8e8c830
PB
3302 is_nx_huge_page_enabled() &&
3303 is_shadow_present_pte(spte) &&
3304 !is_large_pte(spte)) {
3305 /*
3306 * A small SPTE exists for this pfn, but FNAME(fetch)
3307 * and __direct_map would like to create a large PTE
3308 * instead: just force them to go down another level,
3309 * patching back for them into pfn the next 9 bits of
3310 * the address.
3311 */
3312 u64 page_mask = KVM_PAGES_PER_HPAGE(level) - KVM_PAGES_PER_HPAGE(level - 1);
3313 *pfnp |= gfn & page_mask;
3314 (*levelp)--;
3315 }
3316}
3317
3fcf2d1b 3318static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write,
83f06fa7
SC
3319 int map_writable, int max_level, kvm_pfn_t pfn,
3320 bool prefault, bool account_disallowed_nx_lpage)
140754bc 3321{
3fcf2d1b 3322 struct kvm_shadow_walk_iterator it;
140754bc 3323 struct kvm_mmu_page *sp;
83f06fa7 3324 int level, ret;
3fcf2d1b
PB
3325 gfn_t gfn = gpa >> PAGE_SHIFT;
3326 gfn_t base_gfn = gfn;
6aa8b732 3327
0c7a98e3 3328 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
3fcf2d1b 3329 return RET_PF_RETRY;
989c6b34 3330
83f06fa7 3331 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn);
4cd071d1 3332
335e192a 3333 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3fcf2d1b 3334 for_each_shadow_entry(vcpu, gpa, it) {
b8e8c830
PB
3335 /*
3336 * We cannot overwrite existing page tables with an NX
3337 * large page, as the leaf could be executable.
3338 */
3339 disallowed_hugepage_adjust(it, gfn, &pfn, &level);
3340
3fcf2d1b
PB
3341 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3342 if (it.level == level)
9f652d21 3343 break;
6aa8b732 3344
3fcf2d1b
PB
3345 drop_large_spte(vcpu, it.sptep);
3346 if (!is_shadow_present_pte(*it.sptep)) {
3347 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3348 it.level - 1, true, ACC_ALL);
c9fa0b3b 3349
3fcf2d1b 3350 link_shadow_page(vcpu, it.sptep, sp);
2cb70fd4 3351 if (account_disallowed_nx_lpage)
b8e8c830 3352 account_huge_nx_page(vcpu->kvm, sp);
9f652d21
AK
3353 }
3354 }
3fcf2d1b
PB
3355
3356 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3357 write, level, base_gfn, pfn, prefault,
3358 map_writable);
3359 direct_pte_prefetch(vcpu, it.sptep);
3360 ++vcpu->stat.pf_fixed;
3361 return ret;
6aa8b732
AK
3362}
3363
77db5cbd 3364static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
bf998156 3365{
585a8b9b 3366 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
bf998156
HY
3367}
3368
ba049e93 3369static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
bf998156 3370{
4d8b81ab
XG
3371 /*
3372 * Do not cache the mmio info caused by writing the readonly gfn
3373 * into the spte otherwise read access on readonly gfn also can
3374 * caused mmio page fault and treat it as mmio access.
4d8b81ab
XG
3375 */
3376 if (pfn == KVM_PFN_ERR_RO_FAULT)
9b8ebbdb 3377 return RET_PF_EMULATE;
4d8b81ab 3378
e6c1502b 3379 if (pfn == KVM_PFN_ERR_HWPOISON) {
54bf36aa 3380 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
9b8ebbdb 3381 return RET_PF_RETRY;
d7c55201 3382 }
edba23e5 3383
2c151b25 3384 return -EFAULT;
bf998156
HY
3385}
3386
d7c55201 3387static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
0a2b64c5
BG
3388 kvm_pfn_t pfn, unsigned int access,
3389 int *ret_val)
d7c55201 3390{
d7c55201 3391 /* The pfn is invalid, report the error! */
81c52c56 3392 if (unlikely(is_error_pfn(pfn))) {
d7c55201 3393 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
798e88b3 3394 return true;
d7c55201
XG
3395 }
3396
ce88decf 3397 if (unlikely(is_noslot_pfn(pfn)))
4af77151
SC
3398 vcpu_cache_mmio_info(vcpu, gva, gfn,
3399 access & shadow_mmio_access_mask);
d7c55201 3400
798e88b3 3401 return false;
d7c55201
XG
3402}
3403
e5552fd2 3404static bool page_fault_can_be_fast(u32 error_code)
c7ba5b48 3405{
1c118b82
XG
3406 /*
3407 * Do not fix the mmio spte with invalid generation number which
3408 * need to be updated by slow page fault path.
3409 */
3410 if (unlikely(error_code & PFERR_RSVD_MASK))
3411 return false;
3412
f160c7b7
JS
3413 /* See if the page fault is due to an NX violation */
3414 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3415 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3416 return false;
3417
c7ba5b48 3418 /*
f160c7b7
JS
3419 * #PF can be fast if:
3420 * 1. The shadow page table entry is not present, which could mean that
3421 * the fault is potentially caused by access tracking (if enabled).
3422 * 2. The shadow page table entry is present and the fault
3423 * is caused by write-protect, that means we just need change the W
3424 * bit of the spte which can be done out of mmu-lock.
3425 *
3426 * However, if access tracking is disabled we know that a non-present
3427 * page must be a genuine page fault where we have to create a new SPTE.
3428 * So, if access tracking is disabled, we return true only for write
3429 * accesses to a present page.
c7ba5b48 3430 */
c7ba5b48 3431
f160c7b7
JS
3432 return shadow_acc_track_mask != 0 ||
3433 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3434 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
c7ba5b48
XG
3435}
3436
97dceba2
JS
3437/*
3438 * Returns true if the SPTE was fixed successfully. Otherwise,
3439 * someone else modified the SPTE from its original value.
3440 */
c7ba5b48 3441static bool
92a476cb 3442fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d3e328f2 3443 u64 *sptep, u64 old_spte, u64 new_spte)
c7ba5b48 3444{
c7ba5b48
XG
3445 gfn_t gfn;
3446
3447 WARN_ON(!sp->role.direct);
3448
9b51a630
KH
3449 /*
3450 * Theoretically we could also set dirty bit (and flush TLB) here in
3451 * order to eliminate unnecessary PML logging. See comments in
3452 * set_spte. But fast_page_fault is very unlikely to happen with PML
3453 * enabled, so we do not do this. This might result in the same GPA
3454 * to be logged in PML buffer again when the write really happens, and
3455 * eventually to be called by mark_page_dirty twice. But it's also no
3456 * harm. This also avoids the TLB flush needed after setting dirty bit
3457 * so non-PML cases won't be impacted.
3458 *
3459 * Compare with set_spte where instead shadow_dirty_mask is set.
3460 */
f160c7b7 3461 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
97dceba2
JS
3462 return false;
3463
d3e328f2 3464 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
f160c7b7
JS
3465 /*
3466 * The gfn of direct spte is stable since it is
3467 * calculated by sp->gfn.
3468 */
3469 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3470 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3471 }
c7ba5b48
XG
3472
3473 return true;
3474}
3475
d3e328f2
JS
3476static bool is_access_allowed(u32 fault_err_code, u64 spte)
3477{
3478 if (fault_err_code & PFERR_FETCH_MASK)
3479 return is_executable_pte(spte);
3480
3481 if (fault_err_code & PFERR_WRITE_MASK)
3482 return is_writable_pte(spte);
3483
3484 /* Fault was on Read access */
3485 return spte & PT_PRESENT_MASK;
3486}
3487
c7ba5b48
XG
3488/*
3489 * Return value:
3490 * - true: let the vcpu to access on the same address again.
3491 * - false: let the real page fault path to fix it.
3492 */
f9fa2509 3493static bool fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
c7ba5b48
XG
3494 u32 error_code)
3495{
3496 struct kvm_shadow_walk_iterator iterator;
92a476cb 3497 struct kvm_mmu_page *sp;
97dceba2 3498 bool fault_handled = false;
c7ba5b48 3499 u64 spte = 0ull;
97dceba2 3500 uint retry_count = 0;
c7ba5b48 3501
e5552fd2 3502 if (!page_fault_can_be_fast(error_code))
c7ba5b48
XG
3503 return false;
3504
3505 walk_shadow_page_lockless_begin(vcpu);
c7ba5b48 3506
97dceba2 3507 do {
d3e328f2 3508 u64 new_spte;
c7ba5b48 3509
736c291c 3510 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
f9fa2509 3511 if (!is_shadow_present_pte(spte))
d162f30a
JS
3512 break;
3513
97dceba2
JS
3514 sp = page_header(__pa(iterator.sptep));
3515 if (!is_last_spte(spte, sp->role.level))
3516 break;
c7ba5b48 3517
97dceba2 3518 /*
f160c7b7
JS
3519 * Check whether the memory access that caused the fault would
3520 * still cause it if it were to be performed right now. If not,
3521 * then this is a spurious fault caused by TLB lazily flushed,
3522 * or some other CPU has already fixed the PTE after the
3523 * current CPU took the fault.
97dceba2
JS
3524 *
3525 * Need not check the access of upper level table entries since
3526 * they are always ACC_ALL.
3527 */
d3e328f2
JS
3528 if (is_access_allowed(error_code, spte)) {
3529 fault_handled = true;
3530 break;
3531 }
f160c7b7 3532
d3e328f2
JS
3533 new_spte = spte;
3534
3535 if (is_access_track_spte(spte))
3536 new_spte = restore_acc_track_spte(new_spte);
3537
3538 /*
3539 * Currently, to simplify the code, write-protection can
3540 * be removed in the fast path only if the SPTE was
3541 * write-protected for dirty-logging or access tracking.
3542 */
3543 if ((error_code & PFERR_WRITE_MASK) &&
e6302698 3544 spte_can_locklessly_be_made_writable(spte)) {
d3e328f2 3545 new_spte |= PT_WRITABLE_MASK;
f160c7b7
JS
3546
3547 /*
d3e328f2
JS
3548 * Do not fix write-permission on the large spte. Since
3549 * we only dirty the first page into the dirty-bitmap in
3550 * fast_pf_fix_direct_spte(), other pages are missed
3551 * if its slot has dirty logging enabled.
3552 *
3553 * Instead, we let the slow page fault path create a
3554 * normal spte to fix the access.
3555 *
3556 * See the comments in kvm_arch_commit_memory_region().
f160c7b7 3557 */
3bae0459 3558 if (sp->role.level > PG_LEVEL_4K)
f160c7b7 3559 break;
97dceba2 3560 }
c7ba5b48 3561
f160c7b7 3562 /* Verify that the fault can be handled in the fast path */
d3e328f2
JS
3563 if (new_spte == spte ||
3564 !is_access_allowed(error_code, new_spte))
97dceba2
JS
3565 break;
3566
3567 /*
3568 * Currently, fast page fault only works for direct mapping
3569 * since the gfn is not stable for indirect shadow page. See
3ecad8c2 3570 * Documentation/virt/kvm/locking.rst to get more detail.
97dceba2
JS
3571 */
3572 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
f160c7b7 3573 iterator.sptep, spte,
d3e328f2 3574 new_spte);
97dceba2
JS
3575 if (fault_handled)
3576 break;
3577
3578 if (++retry_count > 4) {
3579 printk_once(KERN_WARNING
3580 "kvm: Fast #PF retrying more than 4 times.\n");
3581 break;
3582 }
3583
97dceba2 3584 } while (true);
c126d94f 3585
736c291c 3586 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
97dceba2 3587 spte, fault_handled);
c7ba5b48
XG
3588 walk_shadow_page_lockless_end(vcpu);
3589
97dceba2 3590 return fault_handled;
c7ba5b48
XG
3591}
3592
74b566e6
JS
3593static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3594 struct list_head *invalid_list)
17ac10ad 3595{
4db35314 3596 struct kvm_mmu_page *sp;
17ac10ad 3597
74b566e6 3598 if (!VALID_PAGE(*root_hpa))
7b53aa56 3599 return;
35af577a 3600
74b566e6
JS
3601 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3602 --sp->root_count;
3603 if (!sp->root_count && sp->role.invalid)
3604 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
17ac10ad 3605
74b566e6
JS
3606 *root_hpa = INVALID_PAGE;
3607}
3608
08fb59d8 3609/* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
6a82cd1c
VK
3610void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3611 ulong roots_to_free)
74b566e6
JS
3612{
3613 int i;
3614 LIST_HEAD(invalid_list);
08fb59d8 3615 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
74b566e6 3616
b94742c9 3617 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
74b566e6 3618
08fb59d8 3619 /* Before acquiring the MMU lock, see if we need to do any real work. */
b94742c9
JS
3620 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3621 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3622 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3623 VALID_PAGE(mmu->prev_roots[i].hpa))
3624 break;
3625
3626 if (i == KVM_MMU_NUM_PREV_ROOTS)
3627 return;
3628 }
35af577a
GN
3629
3630 spin_lock(&vcpu->kvm->mmu_lock);
17ac10ad 3631
b94742c9
JS
3632 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3633 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3634 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3635 &invalid_list);
7c390d35 3636
08fb59d8
JS
3637 if (free_active_root) {
3638 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3639 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3640 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3641 &invalid_list);
3642 } else {
3643 for (i = 0; i < 4; ++i)
3644 if (mmu->pae_root[i] != 0)
3645 mmu_free_root_page(vcpu->kvm,
3646 &mmu->pae_root[i],
3647 &invalid_list);
3648 mmu->root_hpa = INVALID_PAGE;
3649 }
be01e8e2 3650 mmu->root_pgd = 0;
17ac10ad 3651 }
74b566e6 3652
d98ba053 3653 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
aaee2c94 3654 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad 3655}
74b566e6 3656EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
17ac10ad 3657
8986ecc0
MT
3658static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3659{
3660 int ret = 0;
3661
3662 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
a8eeb04a 3663 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8986ecc0
MT
3664 ret = 1;
3665 }
3666
3667 return ret;
3668}
3669
8123f265
SC
3670static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3671 u8 level, bool direct)
651dd37a
JR
3672{
3673 struct kvm_mmu_page *sp;
8123f265
SC
3674
3675 spin_lock(&vcpu->kvm->mmu_lock);
3676
3677 if (make_mmu_pages_available(vcpu)) {
3678 spin_unlock(&vcpu->kvm->mmu_lock);
3679 return INVALID_PAGE;
3680 }
3681 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3682 ++sp->root_count;
3683
3684 spin_unlock(&vcpu->kvm->mmu_lock);
3685 return __pa(sp->spt);
3686}
3687
3688static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3689{
3690 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3691 hpa_t root;
7ebaf15e 3692 unsigned i;
651dd37a 3693
8123f265
SC
3694 if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3695 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3696 if (!VALID_PAGE(root))
ed52870f 3697 return -ENOSPC;
8123f265
SC
3698 vcpu->arch.mmu->root_hpa = root;
3699 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
651dd37a 3700 for (i = 0; i < 4; ++i) {
8123f265 3701 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
651dd37a 3702
8123f265
SC
3703 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3704 i << 30, PT32_ROOT_LEVEL, true);
3705 if (!VALID_PAGE(root))
ed52870f 3706 return -ENOSPC;
44dd3ffa 3707 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
651dd37a 3708 }
44dd3ffa 3709 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
651dd37a
JR
3710 } else
3711 BUG();
3651c7fc 3712
be01e8e2
SC
3713 /* root_pgd is ignored for direct MMUs. */
3714 vcpu->arch.mmu->root_pgd = 0;
651dd37a
JR
3715
3716 return 0;
3717}
3718
3719static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
17ac10ad 3720{
81407ca5 3721 u64 pdptr, pm_mask;
be01e8e2 3722 gfn_t root_gfn, root_pgd;
8123f265 3723 hpa_t root;
81407ca5 3724 int i;
3bb65a22 3725
be01e8e2
SC
3726 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3727 root_gfn = root_pgd >> PAGE_SHIFT;
17ac10ad 3728
651dd37a
JR
3729 if (mmu_check_root(vcpu, root_gfn))
3730 return 1;
3731
3732 /*
3733 * Do we shadow a long mode page table? If so we need to
3734 * write-protect the guests page table root.
3735 */
44dd3ffa 3736 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
8123f265 3737 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
651dd37a 3738
8123f265
SC
3739 root = mmu_alloc_root(vcpu, root_gfn, 0,
3740 vcpu->arch.mmu->shadow_root_level, false);
3741 if (!VALID_PAGE(root))
ed52870f 3742 return -ENOSPC;
44dd3ffa 3743 vcpu->arch.mmu->root_hpa = root;
be01e8e2 3744 goto set_root_pgd;
17ac10ad 3745 }
f87f9288 3746
651dd37a
JR
3747 /*
3748 * We shadow a 32 bit page table. This may be a legacy 2-level
81407ca5
JR
3749 * or a PAE 3-level page table. In either case we need to be aware that
3750 * the shadow page table may be a PAE or a long mode page table.
651dd37a 3751 */
81407ca5 3752 pm_mask = PT_PRESENT_MASK;
44dd3ffa 3753 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
81407ca5
JR
3754 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3755
17ac10ad 3756 for (i = 0; i < 4; ++i) {
8123f265 3757 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
44dd3ffa
VK
3758 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3759 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
812f30b2 3760 if (!(pdptr & PT_PRESENT_MASK)) {
44dd3ffa 3761 vcpu->arch.mmu->pae_root[i] = 0;
417726a3
AK
3762 continue;
3763 }
6de4f3ad 3764 root_gfn = pdptr >> PAGE_SHIFT;
f87f9288
JR
3765 if (mmu_check_root(vcpu, root_gfn))
3766 return 1;
5a7388c2 3767 }
8facbbff 3768
8123f265
SC
3769 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3770 PT32_ROOT_LEVEL, false);
3771 if (!VALID_PAGE(root))
3772 return -ENOSPC;
44dd3ffa 3773 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
17ac10ad 3774 }
44dd3ffa 3775 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
81407ca5
JR
3776
3777 /*
3778 * If we shadow a 32 bit page table with a long mode page
3779 * table we enter this path.
3780 */
44dd3ffa
VK
3781 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3782 if (vcpu->arch.mmu->lm_root == NULL) {
81407ca5
JR
3783 /*
3784 * The additional page necessary for this is only
3785 * allocated on demand.
3786 */
3787
3788 u64 *lm_root;
3789
254272ce 3790 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
81407ca5
JR
3791 if (lm_root == NULL)
3792 return 1;
3793
44dd3ffa 3794 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
81407ca5 3795
44dd3ffa 3796 vcpu->arch.mmu->lm_root = lm_root;
81407ca5
JR
3797 }
3798
44dd3ffa 3799 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
81407ca5
JR
3800 }
3801
be01e8e2
SC
3802set_root_pgd:
3803 vcpu->arch.mmu->root_pgd = root_pgd;
ad7dc69a 3804
8986ecc0 3805 return 0;
17ac10ad
AK
3806}
3807
651dd37a
JR
3808static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3809{
44dd3ffa 3810 if (vcpu->arch.mmu->direct_map)
651dd37a
JR
3811 return mmu_alloc_direct_roots(vcpu);
3812 else
3813 return mmu_alloc_shadow_roots(vcpu);
3814}
3815
578e1c4d 3816void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
0ba73cda
MT
3817{
3818 int i;
3819 struct kvm_mmu_page *sp;
3820
44dd3ffa 3821 if (vcpu->arch.mmu->direct_map)
81407ca5
JR
3822 return;
3823
44dd3ffa 3824 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
0ba73cda 3825 return;
6903074c 3826
56f17dd3 3827 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
578e1c4d 3828
44dd3ffa
VK
3829 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3830 hpa_t root = vcpu->arch.mmu->root_hpa;
0ba73cda 3831 sp = page_header(root);
578e1c4d
JS
3832
3833 /*
3834 * Even if another CPU was marking the SP as unsync-ed
3835 * simultaneously, any guest page table changes are not
3836 * guaranteed to be visible anyway until this VCPU issues a TLB
3837 * flush strictly after those changes are made. We only need to
3838 * ensure that the other CPU sets these flags before any actual
3839 * changes to the page tables are made. The comments in
3840 * mmu_need_write_protect() describe what could go wrong if this
3841 * requirement isn't satisfied.
3842 */
3843 if (!smp_load_acquire(&sp->unsync) &&
3844 !smp_load_acquire(&sp->unsync_children))
3845 return;
3846
3847 spin_lock(&vcpu->kvm->mmu_lock);
3848 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3849
0ba73cda 3850 mmu_sync_children(vcpu, sp);
578e1c4d 3851
0375f7fa 3852 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
578e1c4d 3853 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT
3854 return;
3855 }
578e1c4d
JS
3856
3857 spin_lock(&vcpu->kvm->mmu_lock);
3858 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3859
0ba73cda 3860 for (i = 0; i < 4; ++i) {
44dd3ffa 3861 hpa_t root = vcpu->arch.mmu->pae_root[i];
0ba73cda 3862
8986ecc0 3863 if (root && VALID_PAGE(root)) {
0ba73cda
MT
3864 root &= PT64_BASE_ADDR_MASK;
3865 sp = page_header(root);
3866 mmu_sync_children(vcpu, sp);
3867 }
3868 }
0ba73cda 3869
578e1c4d 3870 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
6cffe8ca 3871 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda 3872}
bfd0a56b 3873EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
0ba73cda 3874
736c291c 3875static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
ab9ae313 3876 u32 access, struct x86_exception *exception)
6aa8b732 3877{
ab9ae313
AK
3878 if (exception)
3879 exception->error_code = 0;
6aa8b732
AK
3880 return vaddr;
3881}
3882
736c291c 3883static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
ab9ae313
AK
3884 u32 access,
3885 struct x86_exception *exception)
6539e738 3886{
ab9ae313
AK
3887 if (exception)
3888 exception->error_code = 0;
54987b7a 3889 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
6539e738
JR
3890}
3891
d625b155
XG
3892static bool
3893__is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3894{
b5c3c1b3 3895 int bit7 = (pte >> 7) & 1;
d625b155 3896
b5c3c1b3 3897 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
d625b155
XG
3898}
3899
b5c3c1b3 3900static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
d625b155 3901{
b5c3c1b3 3902 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
d625b155
XG
3903}
3904
ded58749 3905static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
ce88decf 3906{
9034e6e8
PB
3907 /*
3908 * A nested guest cannot use the MMIO cache if it is using nested
3909 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3910 */
3911 if (mmu_is_nested(vcpu))
3912 return false;
3913
ce88decf
XG
3914 if (direct)
3915 return vcpu_match_mmio_gpa(vcpu, addr);
3916
3917 return vcpu_match_mmio_gva(vcpu, addr);
3918}
3919
47ab8751
XG
3920/* return true if reserved bit is detected on spte. */
3921static bool
3922walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
ce88decf
XG
3923{
3924 struct kvm_shadow_walk_iterator iterator;
2a7266a8 3925 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
b5c3c1b3 3926 struct rsvd_bits_validate *rsvd_check;
47ab8751
XG
3927 int root, leaf;
3928 bool reserved = false;
ce88decf 3929
b5c3c1b3 3930 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
37f6a4e2 3931
ce88decf 3932 walk_shadow_page_lockless_begin(vcpu);
47ab8751 3933
29ecd660
PB
3934 for (shadow_walk_init(&iterator, vcpu, addr),
3935 leaf = root = iterator.level;
47ab8751
XG
3936 shadow_walk_okay(&iterator);
3937 __shadow_walk_next(&iterator, spte)) {
47ab8751
XG
3938 spte = mmu_spte_get_lockless(iterator.sptep);
3939
3940 sptes[leaf - 1] = spte;
29ecd660 3941 leaf--;
47ab8751 3942
ce88decf
XG
3943 if (!is_shadow_present_pte(spte))
3944 break;
47ab8751 3945
b5c3c1b3
SC
3946 /*
3947 * Use a bitwise-OR instead of a logical-OR to aggregate the
3948 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3949 * adding a Jcc in the loop.
3950 */
3951 reserved |= __is_bad_mt_xwr(rsvd_check, spte) |
3952 __is_rsvd_bits_set(rsvd_check, spte, iterator.level);
47ab8751
XG
3953 }
3954
ce88decf
XG
3955 walk_shadow_page_lockless_end(vcpu);
3956
47ab8751
XG
3957 if (reserved) {
3958 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3959 __func__, addr);
29ecd660 3960 while (root > leaf) {
47ab8751
XG
3961 pr_err("------ spte 0x%llx level %d.\n",
3962 sptes[root - 1], root);
3963 root--;
3964 }
3965 }
ddce6208 3966
47ab8751
XG
3967 *sptep = spte;
3968 return reserved;
ce88decf
XG
3969}
3970
e08d26f0 3971static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
ce88decf
XG
3972{
3973 u64 spte;
47ab8751 3974 bool reserved;
ce88decf 3975
ded58749 3976 if (mmio_info_in_cache(vcpu, addr, direct))
9b8ebbdb 3977 return RET_PF_EMULATE;
ce88decf 3978
47ab8751 3979 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
450869d6 3980 if (WARN_ON(reserved))
9b8ebbdb 3981 return -EINVAL;
ce88decf
XG
3982
3983 if (is_mmio_spte(spte)) {
3984 gfn_t gfn = get_mmio_spte_gfn(spte);
0a2b64c5 3985 unsigned int access = get_mmio_spte_access(spte);
ce88decf 3986
54bf36aa 3987 if (!check_mmio_spte(vcpu, spte))
9b8ebbdb 3988 return RET_PF_INVALID;
f8f55942 3989
ce88decf
XG
3990 if (direct)
3991 addr = 0;
4f022648
XG
3992
3993 trace_handle_mmio_page_fault(addr, gfn, access);
ce88decf 3994 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
9b8ebbdb 3995 return RET_PF_EMULATE;
ce88decf
XG
3996 }
3997
ce88decf
XG
3998 /*
3999 * If the page table is zapped by other cpus, let CPU fault again on
4000 * the address.
4001 */
9b8ebbdb 4002 return RET_PF_RETRY;
ce88decf 4003}
ce88decf 4004
3d0c27ad
XG
4005static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
4006 u32 error_code, gfn_t gfn)
4007{
4008 if (unlikely(error_code & PFERR_RSVD_MASK))
4009 return false;
4010
4011 if (!(error_code & PFERR_PRESENT_MASK) ||
4012 !(error_code & PFERR_WRITE_MASK))
4013 return false;
4014
4015 /*
4016 * guest is writing the page which is write tracked which can
4017 * not be fixed by page fault handler.
4018 */
4019 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
4020 return true;
4021
4022 return false;
4023}
4024
e5691a81
XG
4025static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
4026{
4027 struct kvm_shadow_walk_iterator iterator;
4028 u64 spte;
4029
e5691a81
XG
4030 walk_shadow_page_lockless_begin(vcpu);
4031 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4032 clear_sp_write_flooding_count(iterator.sptep);
4033 if (!is_shadow_present_pte(spte))
4034 break;
4035 }
4036 walk_shadow_page_lockless_end(vcpu);
4037}
4038
e8c22266
VK
4039static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
4040 gfn_t gfn)
af585b92
GN
4041{
4042 struct kvm_arch_async_pf arch;
fb67e14f 4043
7c90705b 4044 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
af585b92 4045 arch.gfn = gfn;
44dd3ffa 4046 arch.direct_map = vcpu->arch.mmu->direct_map;
d8dd54e0 4047 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
af585b92 4048
9f1a8526
SC
4049 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
4050 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
af585b92
GN
4051}
4052
78b2c54a 4053static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
9f1a8526
SC
4054 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
4055 bool *writable)
af585b92 4056{
c36b7150 4057 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
af585b92
GN
4058 bool async;
4059
c36b7150
PB
4060 /* Don't expose private memslots to L2. */
4061 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3a2936de 4062 *pfn = KVM_PFN_NOSLOT;
c583eed6 4063 *writable = false;
3a2936de
JM
4064 return false;
4065 }
4066
3520469d
PB
4067 async = false;
4068 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
af585b92
GN
4069 if (!async)
4070 return false; /* *pfn has correct page already */
4071
9bc1f09f 4072 if (!prefault && kvm_can_do_async_pf(vcpu)) {
9f1a8526 4073 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
af585b92 4074 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
9f1a8526 4075 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
af585b92
GN
4076 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4077 return true;
9f1a8526 4078 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
af585b92
GN
4079 return true;
4080 }
4081
3520469d 4082 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
af585b92
GN
4083 return false;
4084}
4085
0f90e1c1
SC
4086static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4087 bool prefault, int max_level, bool is_tdp)
6aa8b732 4088{
367fd790 4089 bool write = error_code & PFERR_WRITE_MASK;
367fd790
SC
4090 bool exec = error_code & PFERR_FETCH_MASK;
4091 bool lpage_disallowed = exec && is_nx_huge_page_enabled();
0f90e1c1 4092 bool map_writable;
6aa8b732 4093
0f90e1c1
SC
4094 gfn_t gfn = gpa >> PAGE_SHIFT;
4095 unsigned long mmu_seq;
4096 kvm_pfn_t pfn;
83f06fa7 4097 int r;
ce88decf 4098
3d0c27ad 4099 if (page_fault_handle_page_track(vcpu, error_code, gfn))
9b8ebbdb 4100 return RET_PF_EMULATE;
ce88decf 4101
e2dec939
AK
4102 r = mmu_topup_memory_caches(vcpu);
4103 if (r)
4104 return r;
714b93da 4105
0f90e1c1 4106 if (lpage_disallowed)
3bae0459 4107 max_level = PG_LEVEL_4K;
367fd790 4108
f9fa2509 4109 if (fast_page_fault(vcpu, gpa, error_code))
367fd790
SC
4110 return RET_PF_RETRY;
4111
4112 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4113 smp_rmb();
4114
4115 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4116 return RET_PF_RETRY;
4117
0f90e1c1 4118 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
367fd790 4119 return r;
6aa8b732 4120
367fd790
SC
4121 r = RET_PF_RETRY;
4122 spin_lock(&vcpu->kvm->mmu_lock);
4123 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4124 goto out_unlock;
4125 if (make_mmu_pages_available(vcpu) < 0)
4126 goto out_unlock;
83f06fa7 4127 r = __direct_map(vcpu, gpa, write, map_writable, max_level, pfn,
4cd071d1 4128 prefault, is_tdp && lpage_disallowed);
0f90e1c1 4129
367fd790
SC
4130out_unlock:
4131 spin_unlock(&vcpu->kvm->mmu_lock);
4132 kvm_release_pfn_clean(pfn);
4133 return r;
6aa8b732
AK
4134}
4135
0f90e1c1
SC
4136static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
4137 u32 error_code, bool prefault)
4138{
4139 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
4140
4141 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4142 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3bae0459 4143 PG_LEVEL_2M, false);
0f90e1c1
SC
4144}
4145
1261bfa3 4146int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
d0006530 4147 u64 fault_address, char *insn, int insn_len)
1261bfa3
WL
4148{
4149 int r = 1;
9ce372b3 4150 u32 flags = vcpu->arch.apf.host_apf_flags;
1261bfa3 4151
736c291c
SC
4152#ifndef CONFIG_X86_64
4153 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4154 if (WARN_ON_ONCE(fault_address >> 32))
4155 return -EFAULT;
4156#endif
4157
c595ceee 4158 vcpu->arch.l1tf_flush_l1d = true;
9ce372b3 4159 if (!flags) {
1261bfa3
WL
4160 trace_kvm_page_fault(fault_address, error_code);
4161
d0006530 4162 if (kvm_event_needs_reinjection(vcpu))
1261bfa3
WL
4163 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4164 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4165 insn_len);
9ce372b3 4166 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
68fd66f1 4167 vcpu->arch.apf.host_apf_flags = 0;
1261bfa3 4168 local_irq_disable();
6bca69ad 4169 kvm_async_pf_task_wait_schedule(fault_address);
1261bfa3 4170 local_irq_enable();
9ce372b3
VK
4171 } else {
4172 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
1261bfa3 4173 }
9ce372b3 4174
1261bfa3
WL
4175 return r;
4176}
4177EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4178
7a02674d
SC
4179int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
4180 bool prefault)
fb72d167 4181{
cb9b88c6 4182 int max_level;
fb72d167 4183
e662ec3e 4184 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3bae0459 4185 max_level > PG_LEVEL_4K;
cb9b88c6
SC
4186 max_level--) {
4187 int page_num = KVM_PAGES_PER_HPAGE(max_level);
0f90e1c1 4188 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
ce88decf 4189
cb9b88c6
SC
4190 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4191 break;
fd136902 4192 }
852e3c19 4193
0f90e1c1
SC
4194 return direct_page_fault(vcpu, gpa, error_code, prefault,
4195 max_level, true);
fb72d167
JR
4196}
4197
8a3c1a33
PB
4198static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4199 struct kvm_mmu *context)
6aa8b732 4200{
6aa8b732 4201 context->page_fault = nonpaging_page_fault;
6aa8b732 4202 context->gva_to_gpa = nonpaging_gva_to_gpa;
e8bc217a 4203 context->sync_page = nonpaging_sync_page;
5efac074 4204 context->invlpg = NULL;
0f53b5b1 4205 context->update_pte = nonpaging_update_pte;
cea0f0e7 4206 context->root_level = 0;
6aa8b732 4207 context->shadow_root_level = PT32E_ROOT_LEVEL;
c5a78f2b 4208 context->direct_map = true;
2d48a985 4209 context->nx = false;
6aa8b732
AK
4210}
4211
be01e8e2 4212static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
0be44352
SC
4213 union kvm_mmu_page_role role)
4214{
be01e8e2 4215 return (role.direct || pgd == root->pgd) &&
0be44352
SC
4216 VALID_PAGE(root->hpa) && page_header(root->hpa) &&
4217 role.word == page_header(root->hpa)->role.word;
4218}
4219
b94742c9 4220/*
be01e8e2 4221 * Find out if a previously cached root matching the new pgd/role is available.
b94742c9
JS
4222 * The current root is also inserted into the cache.
4223 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4224 * returned.
4225 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4226 * false is returned. This root should now be freed by the caller.
4227 */
be01e8e2 4228static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
b94742c9
JS
4229 union kvm_mmu_page_role new_role)
4230{
4231 uint i;
4232 struct kvm_mmu_root_info root;
44dd3ffa 4233 struct kvm_mmu *mmu = vcpu->arch.mmu;
b94742c9 4234
be01e8e2 4235 root.pgd = mmu->root_pgd;
b94742c9
JS
4236 root.hpa = mmu->root_hpa;
4237
be01e8e2 4238 if (is_root_usable(&root, new_pgd, new_role))
0be44352
SC
4239 return true;
4240
b94742c9
JS
4241 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4242 swap(root, mmu->prev_roots[i]);
4243
be01e8e2 4244 if (is_root_usable(&root, new_pgd, new_role))
b94742c9
JS
4245 break;
4246 }
4247
4248 mmu->root_hpa = root.hpa;
be01e8e2 4249 mmu->root_pgd = root.pgd;
b94742c9
JS
4250
4251 return i < KVM_MMU_NUM_PREV_ROOTS;
4252}
4253
be01e8e2 4254static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
b869855b 4255 union kvm_mmu_page_role new_role)
6aa8b732 4256{
44dd3ffa 4257 struct kvm_mmu *mmu = vcpu->arch.mmu;
7c390d35
JS
4258
4259 /*
4260 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4261 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4262 * later if necessary.
4263 */
4264 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
b869855b 4265 mmu->root_level >= PT64_ROOT_4LEVEL)
be01e8e2
SC
4266 return !mmu_check_root(vcpu, new_pgd >> PAGE_SHIFT) &&
4267 cached_root_available(vcpu, new_pgd, new_role);
7c390d35
JS
4268
4269 return false;
6aa8b732
AK
4270}
4271
be01e8e2 4272static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
ade61e28 4273 union kvm_mmu_page_role new_role,
4a632ac6 4274 bool skip_tlb_flush, bool skip_mmu_sync)
6aa8b732 4275{
be01e8e2 4276 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
b869855b
SC
4277 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4278 return;
4279 }
4280
4281 /*
4282 * It's possible that the cached previous root page is obsolete because
4283 * of a change in the MMU generation number. However, changing the
4284 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4285 * free the root set here and allocate a new one.
4286 */
4287 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4288
71fe7013 4289 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
b869855b 4290 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
71fe7013 4291 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
b869855b 4292 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
b869855b
SC
4293
4294 /*
4295 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4296 * switching to a new CR3, that GVA->GPA mapping may no longer be
4297 * valid. So clear any cached MMIO info even when we don't need to sync
4298 * the shadow page tables.
4299 */
4300 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4301
4302 __clear_sp_write_flooding_count(page_header(vcpu->arch.mmu->root_hpa));
6aa8b732
AK
4303}
4304
be01e8e2 4305void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
4a632ac6 4306 bool skip_mmu_sync)
0aab33e4 4307{
be01e8e2 4308 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
4a632ac6 4309 skip_tlb_flush, skip_mmu_sync);
0aab33e4 4310}
be01e8e2 4311EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
0aab33e4 4312
5777ed34
JR
4313static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4314{
9f8fe504 4315 return kvm_read_cr3(vcpu);
5777ed34
JR
4316}
4317
54bf36aa 4318static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
0a2b64c5 4319 unsigned int access, int *nr_present)
ce88decf
XG
4320{
4321 if (unlikely(is_mmio_spte(*sptep))) {
4322 if (gfn != get_mmio_spte_gfn(*sptep)) {
4323 mmu_spte_clear_no_track(sptep);
4324 return true;
4325 }
4326
4327 (*nr_present)++;
54bf36aa 4328 mark_mmio_spte(vcpu, sptep, gfn, access);
ce88decf
XG
4329 return true;
4330 }
4331
4332 return false;
4333}
4334
6bb69c9b
PB
4335static inline bool is_last_gpte(struct kvm_mmu *mmu,
4336 unsigned level, unsigned gpte)
6fd01b71 4337{
6bb69c9b
PB
4338 /*
4339 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4340 * If it is clear, there are no large pages at this level, so clear
4341 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4342 */
4343 gpte &= level - mmu->last_nonleaf_level;
4344
829ee279 4345 /*
3bae0459
SC
4346 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4347 * iff level <= PG_LEVEL_4K, which for our purpose means
4348 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
829ee279 4349 */
3bae0459 4350 gpte |= level - PG_LEVEL_4K - 1;
829ee279 4351
6bb69c9b 4352 return gpte & PT_PAGE_SIZE_MASK;
6fd01b71
AK
4353}
4354
37406aaa
NHE
4355#define PTTYPE_EPT 18 /* arbitrary */
4356#define PTTYPE PTTYPE_EPT
4357#include "paging_tmpl.h"
4358#undef PTTYPE
4359
6aa8b732
AK
4360#define PTTYPE 64
4361#include "paging_tmpl.h"
4362#undef PTTYPE
4363
4364#define PTTYPE 32
4365#include "paging_tmpl.h"
4366#undef PTTYPE
4367
6dc98b86
XG
4368static void
4369__reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4370 struct rsvd_bits_validate *rsvd_check,
4371 int maxphyaddr, int level, bool nx, bool gbpages,
6fec2144 4372 bool pse, bool amd)
82725b20 4373{
82725b20 4374 u64 exb_bit_rsvd = 0;
5f7dde7b 4375 u64 gbpages_bit_rsvd = 0;
a0c0feb5 4376 u64 nonleaf_bit8_rsvd = 0;
82725b20 4377
a0a64f50 4378 rsvd_check->bad_mt_xwr = 0;
25d92081 4379
6dc98b86 4380 if (!nx)
82725b20 4381 exb_bit_rsvd = rsvd_bits(63, 63);
6dc98b86 4382 if (!gbpages)
5f7dde7b 4383 gbpages_bit_rsvd = rsvd_bits(7, 7);
a0c0feb5
PB
4384
4385 /*
4386 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4387 * leaf entries) on AMD CPUs only.
4388 */
6fec2144 4389 if (amd)
a0c0feb5
PB
4390 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4391
6dc98b86 4392 switch (level) {
82725b20
DE
4393 case PT32_ROOT_LEVEL:
4394 /* no rsvd bits for 2 level 4K page table entries */
a0a64f50
XG
4395 rsvd_check->rsvd_bits_mask[0][1] = 0;
4396 rsvd_check->rsvd_bits_mask[0][0] = 0;
4397 rsvd_check->rsvd_bits_mask[1][0] =
4398 rsvd_check->rsvd_bits_mask[0][0];
f815bce8 4399
6dc98b86 4400 if (!pse) {
a0a64f50 4401 rsvd_check->rsvd_bits_mask[1][1] = 0;
f815bce8
XG
4402 break;
4403 }
4404
82725b20
DE
4405 if (is_cpuid_PSE36())
4406 /* 36bits PSE 4MB page */
a0a64f50 4407 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
82725b20
DE
4408 else
4409 /* 32 bits PSE 4MB page */
a0a64f50 4410 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE
4411 break;
4412 case PT32E_ROOT_LEVEL:
a0a64f50 4413 rsvd_check->rsvd_bits_mask[0][2] =
20c466b5 4414 rsvd_bits(maxphyaddr, 63) |
cd9ae5fe 4415 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
a0a64f50 4416 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 4417 rsvd_bits(maxphyaddr, 62); /* PDE */
a0a64f50 4418 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
82725b20 4419 rsvd_bits(maxphyaddr, 62); /* PTE */
a0a64f50 4420 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
82725b20
DE
4421 rsvd_bits(maxphyaddr, 62) |
4422 rsvd_bits(13, 20); /* large page */
a0a64f50
XG
4423 rsvd_check->rsvd_bits_mask[1][0] =
4424 rsvd_check->rsvd_bits_mask[0][0];
82725b20 4425 break;
855feb67
YZ
4426 case PT64_ROOT_5LEVEL:
4427 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4428 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4429 rsvd_bits(maxphyaddr, 51);
4430 rsvd_check->rsvd_bits_mask[1][4] =
4431 rsvd_check->rsvd_bits_mask[0][4];
b2869f28 4432 /* fall through */
2a7266a8 4433 case PT64_ROOT_4LEVEL:
a0a64f50
XG
4434 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4435 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4c26b4cd 4436 rsvd_bits(maxphyaddr, 51);
a0a64f50 4437 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
5ecad245 4438 gbpages_bit_rsvd |
82725b20 4439 rsvd_bits(maxphyaddr, 51);
a0a64f50
XG
4440 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4441 rsvd_bits(maxphyaddr, 51);
4442 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4443 rsvd_bits(maxphyaddr, 51);
4444 rsvd_check->rsvd_bits_mask[1][3] =
4445 rsvd_check->rsvd_bits_mask[0][3];
4446 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
5f7dde7b 4447 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
e04da980 4448 rsvd_bits(13, 29);
a0a64f50 4449 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY
4450 rsvd_bits(maxphyaddr, 51) |
4451 rsvd_bits(13, 20); /* large page */
a0a64f50
XG
4452 rsvd_check->rsvd_bits_mask[1][0] =
4453 rsvd_check->rsvd_bits_mask[0][0];
82725b20
DE
4454 break;
4455 }
4456}
4457
6dc98b86
XG
4458static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4459 struct kvm_mmu *context)
4460{
4461 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4462 cpuid_maxphyaddr(vcpu), context->root_level,
d6321d49
RK
4463 context->nx,
4464 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
23493d0a
SC
4465 is_pse(vcpu),
4466 guest_cpuid_is_amd_or_hygon(vcpu));
6dc98b86
XG
4467}
4468
81b8eebb
XG
4469static void
4470__reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4471 int maxphyaddr, bool execonly)
25d92081 4472{
951f9fd7 4473 u64 bad_mt_xwr;
25d92081 4474
855feb67
YZ
4475 rsvd_check->rsvd_bits_mask[0][4] =
4476 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
a0a64f50 4477 rsvd_check->rsvd_bits_mask[0][3] =
25d92081 4478 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
a0a64f50 4479 rsvd_check->rsvd_bits_mask[0][2] =
25d92081 4480 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
a0a64f50 4481 rsvd_check->rsvd_bits_mask[0][1] =
25d92081 4482 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
a0a64f50 4483 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
25d92081
YZ
4484
4485 /* large page */
855feb67 4486 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
a0a64f50
XG
4487 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4488 rsvd_check->rsvd_bits_mask[1][2] =
25d92081 4489 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
a0a64f50 4490 rsvd_check->rsvd_bits_mask[1][1] =
25d92081 4491 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
a0a64f50 4492 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
25d92081 4493
951f9fd7
PB
4494 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4495 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4496 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4497 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4498 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4499 if (!execonly) {
4500 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4501 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
25d92081 4502 }
951f9fd7 4503 rsvd_check->bad_mt_xwr = bad_mt_xwr;
25d92081
YZ
4504}
4505
81b8eebb
XG
4506static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4507 struct kvm_mmu *context, bool execonly)
4508{
4509 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4510 cpuid_maxphyaddr(vcpu), execonly);
4511}
4512
c258b62b
XG
4513/*
4514 * the page table on host is the shadow page table for the page
4515 * table in guest or amd nested guest, its mmu features completely
4516 * follow the features in guest.
4517 */
4518void
4519reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4520{
36d9594d
VK
4521 bool uses_nx = context->nx ||
4522 context->mmu_role.base.smep_andnot_wp;
ea2800dd
BS
4523 struct rsvd_bits_validate *shadow_zero_check;
4524 int i;
5f0b8199 4525
6fec2144
PB
4526 /*
4527 * Passing "true" to the last argument is okay; it adds a check
4528 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4529 */
ea2800dd
BS
4530 shadow_zero_check = &context->shadow_zero_check;
4531 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
f3ecb59d 4532 shadow_phys_bits,
5f0b8199 4533 context->shadow_root_level, uses_nx,
d6321d49
RK
4534 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4535 is_pse(vcpu), true);
ea2800dd
BS
4536
4537 if (!shadow_me_mask)
4538 return;
4539
4540 for (i = context->shadow_root_level; --i >= 0;) {
4541 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4542 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4543 }
4544
c258b62b
XG
4545}
4546EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4547
6fec2144
PB
4548static inline bool boot_cpu_is_amd(void)
4549{
4550 WARN_ON_ONCE(!tdp_enabled);
4551 return shadow_x_mask == 0;
4552}
4553
c258b62b
XG
4554/*
4555 * the direct page table on host, use as much mmu features as
4556 * possible, however, kvm currently does not do execution-protection.
4557 */
4558static void
4559reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4560 struct kvm_mmu *context)
4561{
ea2800dd
BS
4562 struct rsvd_bits_validate *shadow_zero_check;
4563 int i;
4564
4565 shadow_zero_check = &context->shadow_zero_check;
4566
6fec2144 4567 if (boot_cpu_is_amd())
ea2800dd 4568 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
f3ecb59d 4569 shadow_phys_bits,
c258b62b 4570 context->shadow_root_level, false,
b8291adc
BP
4571 boot_cpu_has(X86_FEATURE_GBPAGES),
4572 true, true);
c258b62b 4573 else
ea2800dd 4574 __reset_rsvds_bits_mask_ept(shadow_zero_check,
f3ecb59d 4575 shadow_phys_bits,
c258b62b
XG
4576 false);
4577
ea2800dd
BS
4578 if (!shadow_me_mask)
4579 return;
4580
4581 for (i = context->shadow_root_level; --i >= 0;) {
4582 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4583 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4584 }
c258b62b
XG
4585}
4586
4587/*
4588 * as the comments in reset_shadow_zero_bits_mask() except it
4589 * is the shadow page table for intel nested guest.
4590 */
4591static void
4592reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4593 struct kvm_mmu *context, bool execonly)
4594{
4595 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
f3ecb59d 4596 shadow_phys_bits, execonly);
c258b62b
XG
4597}
4598
09f037aa
PB
4599#define BYTE_MASK(access) \
4600 ((1 & (access) ? 2 : 0) | \
4601 (2 & (access) ? 4 : 0) | \
4602 (3 & (access) ? 8 : 0) | \
4603 (4 & (access) ? 16 : 0) | \
4604 (5 & (access) ? 32 : 0) | \
4605 (6 & (access) ? 64 : 0) | \
4606 (7 & (access) ? 128 : 0))
4607
4608
edc90b7d
XG
4609static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4610 struct kvm_mmu *mmu, bool ept)
97d64b78 4611{
09f037aa
PB
4612 unsigned byte;
4613
4614 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4615 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4616 const u8 u = BYTE_MASK(ACC_USER_MASK);
4617
4618 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4619 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4620 bool cr0_wp = is_write_protection(vcpu);
97d64b78 4621
97d64b78 4622 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
09f037aa
PB
4623 unsigned pfec = byte << 1;
4624
97ec8c06 4625 /*
09f037aa
PB
4626 * Each "*f" variable has a 1 bit for each UWX value
4627 * that causes a fault with the given PFEC.
97ec8c06 4628 */
97d64b78 4629
09f037aa 4630 /* Faults from writes to non-writable pages */
a6a6d3b1 4631 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
09f037aa 4632 /* Faults from user mode accesses to supervisor pages */
a6a6d3b1 4633 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
09f037aa 4634 /* Faults from fetches of non-executable pages*/
a6a6d3b1 4635 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
09f037aa
PB
4636 /* Faults from kernel mode fetches of user pages */
4637 u8 smepf = 0;
4638 /* Faults from kernel mode accesses of user pages */
4639 u8 smapf = 0;
4640
4641 if (!ept) {
4642 /* Faults from kernel mode accesses to user pages */
4643 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4644
4645 /* Not really needed: !nx will cause pte.nx to fault */
4646 if (!mmu->nx)
4647 ff = 0;
4648
4649 /* Allow supervisor writes if !cr0.wp */
4650 if (!cr0_wp)
4651 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4652
4653 /* Disallow supervisor fetches of user code if cr4.smep */
4654 if (cr4_smep)
4655 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4656
4657 /*
4658 * SMAP:kernel-mode data accesses from user-mode
4659 * mappings should fault. A fault is considered
4660 * as a SMAP violation if all of the following
39337ad1 4661 * conditions are true:
09f037aa
PB
4662 * - X86_CR4_SMAP is set in CR4
4663 * - A user page is accessed
4664 * - The access is not a fetch
4665 * - Page fault in kernel mode
4666 * - if CPL = 3 or X86_EFLAGS_AC is clear
4667 *
4668 * Here, we cover the first three conditions.
4669 * The fourth is computed dynamically in permission_fault();
4670 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4671 * *not* subject to SMAP restrictions.
4672 */
4673 if (cr4_smap)
4674 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
97d64b78 4675 }
09f037aa
PB
4676
4677 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
97d64b78
AK
4678 }
4679}
4680
2d344105
HH
4681/*
4682* PKU is an additional mechanism by which the paging controls access to
4683* user-mode addresses based on the value in the PKRU register. Protection
4684* key violations are reported through a bit in the page fault error code.
4685* Unlike other bits of the error code, the PK bit is not known at the
4686* call site of e.g. gva_to_gpa; it must be computed directly in
4687* permission_fault based on two bits of PKRU, on some machine state (CR4,
4688* CR0, EFER, CPL), and on other bits of the error code and the page tables.
4689*
4690* In particular the following conditions come from the error code, the
4691* page tables and the machine state:
4692* - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4693* - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4694* - PK is always zero if U=0 in the page tables
4695* - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4696*
4697* The PKRU bitmask caches the result of these four conditions. The error
4698* code (minus the P bit) and the page table's U bit form an index into the
4699* PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4700* with the two bits of the PKRU register corresponding to the protection key.
4701* For the first three conditions above the bits will be 00, thus masking
4702* away both AD and WD. For all reads or if the last condition holds, WD
4703* only will be masked away.
4704*/
4705static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4706 bool ept)
4707{
4708 unsigned bit;
4709 bool wp;
4710
4711 if (ept) {
4712 mmu->pkru_mask = 0;
4713 return;
4714 }
4715
4716 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4717 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4718 mmu->pkru_mask = 0;
4719 return;
4720 }
4721
4722 wp = is_write_protection(vcpu);
4723
4724 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4725 unsigned pfec, pkey_bits;
4726 bool check_pkey, check_write, ff, uf, wf, pte_user;
4727
4728 pfec = bit << 1;
4729 ff = pfec & PFERR_FETCH_MASK;
4730 uf = pfec & PFERR_USER_MASK;
4731 wf = pfec & PFERR_WRITE_MASK;
4732
4733 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4734 pte_user = pfec & PFERR_RSVD_MASK;
4735
4736 /*
4737 * Only need to check the access which is not an
4738 * instruction fetch and is to a user page.
4739 */
4740 check_pkey = (!ff && pte_user);
4741 /*
4742 * write access is controlled by PKRU if it is a
4743 * user access or CR0.WP = 1.
4744 */
4745 check_write = check_pkey && wf && (uf || wp);
4746
4747 /* PKRU.AD stops both read and write access. */
4748 pkey_bits = !!check_pkey;
4749 /* PKRU.WD stops write access. */
4750 pkey_bits |= (!!check_write) << 1;
4751
4752 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4753 }
4754}
4755
6bb69c9b 4756static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
6fd01b71 4757{
6bb69c9b
PB
4758 unsigned root_level = mmu->root_level;
4759
4760 mmu->last_nonleaf_level = root_level;
4761 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4762 mmu->last_nonleaf_level++;
6fd01b71
AK
4763}
4764
8a3c1a33
PB
4765static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4766 struct kvm_mmu *context,
4767 int level)
6aa8b732 4768{
2d48a985 4769 context->nx = is_nx(vcpu);
4d6931c3 4770 context->root_level = level;
2d48a985 4771
4d6931c3 4772 reset_rsvds_bits_mask(vcpu, context);
25d92081 4773 update_permission_bitmask(vcpu, context, false);
2d344105 4774 update_pkru_bitmask(vcpu, context, false);
6bb69c9b 4775 update_last_nonleaf_level(vcpu, context);
6aa8b732 4776
fa4a2c08 4777 MMU_WARN_ON(!is_pae(vcpu));
6aa8b732 4778 context->page_fault = paging64_page_fault;
6aa8b732 4779 context->gva_to_gpa = paging64_gva_to_gpa;
e8bc217a 4780 context->sync_page = paging64_sync_page;
a7052897 4781 context->invlpg = paging64_invlpg;
0f53b5b1 4782 context->update_pte = paging64_update_pte;
17ac10ad 4783 context->shadow_root_level = level;
c5a78f2b 4784 context->direct_map = false;
6aa8b732
AK
4785}
4786
8a3c1a33
PB
4787static void paging64_init_context(struct kvm_vcpu *vcpu,
4788 struct kvm_mmu *context)
17ac10ad 4789{
855feb67
YZ
4790 int root_level = is_la57_mode(vcpu) ?
4791 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4792
4793 paging64_init_context_common(vcpu, context, root_level);
17ac10ad
AK
4794}
4795
8a3c1a33
PB
4796static void paging32_init_context(struct kvm_vcpu *vcpu,
4797 struct kvm_mmu *context)
6aa8b732 4798{
2d48a985 4799 context->nx = false;
4d6931c3 4800 context->root_level = PT32_ROOT_LEVEL;
2d48a985 4801
4d6931c3 4802 reset_rsvds_bits_mask(vcpu, context);
25d92081 4803 update_permission_bitmask(vcpu, context, false);
2d344105 4804 update_pkru_bitmask(vcpu, context, false);
6bb69c9b 4805 update_last_nonleaf_level(vcpu, context);
6aa8b732 4806
6aa8b732 4807 context->page_fault = paging32_page_fault;
6aa8b732 4808 context->gva_to_gpa = paging32_gva_to_gpa;
e8bc217a 4809 context->sync_page = paging32_sync_page;
a7052897 4810 context->invlpg = paging32_invlpg;
0f53b5b1 4811 context->update_pte = paging32_update_pte;
6aa8b732 4812 context->shadow_root_level = PT32E_ROOT_LEVEL;
c5a78f2b 4813 context->direct_map = false;
6aa8b732
AK
4814}
4815
8a3c1a33
PB
4816static void paging32E_init_context(struct kvm_vcpu *vcpu,
4817 struct kvm_mmu *context)
6aa8b732 4818{
8a3c1a33 4819 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
6aa8b732
AK
4820}
4821
a336282d
VK
4822static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4823{
4824 union kvm_mmu_extended_role ext = {0};
4825
7dcd5755 4826 ext.cr0_pg = !!is_paging(vcpu);
0699c64a 4827 ext.cr4_pae = !!is_pae(vcpu);
a336282d
VK
4828 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4829 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4830 ext.cr4_pse = !!is_pse(vcpu);
4831 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
de3ccd26 4832 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
a336282d
VK
4833
4834 ext.valid = 1;
4835
4836 return ext;
4837}
4838
7dcd5755
VK
4839static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4840 bool base_only)
4841{
4842 union kvm_mmu_role role = {0};
4843
4844 role.base.access = ACC_ALL;
4845 role.base.nxe = !!is_nx(vcpu);
7dcd5755
VK
4846 role.base.cr0_wp = is_write_protection(vcpu);
4847 role.base.smm = is_smm(vcpu);
4848 role.base.guest_mode = is_guest_mode(vcpu);
4849
4850 if (base_only)
4851 return role;
4852
4853 role.ext = kvm_calc_mmu_role_ext(vcpu);
4854
4855 return role;
4856}
4857
4858static union kvm_mmu_role
4859kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
9fa72119 4860{
7dcd5755 4861 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
9fa72119 4862
7dcd5755 4863 role.base.ad_disabled = (shadow_accessed_mask == 0);
e93fd3b3 4864 role.base.level = vcpu->arch.tdp_level;
7dcd5755 4865 role.base.direct = true;
47c42e6b 4866 role.base.gpte_is_8_bytes = true;
9fa72119
JS
4867
4868 return role;
4869}
4870
8a3c1a33 4871static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
fb72d167 4872{
44dd3ffa 4873 struct kvm_mmu *context = vcpu->arch.mmu;
7dcd5755
VK
4874 union kvm_mmu_role new_role =
4875 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
fb72d167 4876
7dcd5755
VK
4877 if (new_role.as_u64 == context->mmu_role.as_u64)
4878 return;
4879
4880 context->mmu_role.as_u64 = new_role.as_u64;
7a02674d 4881 context->page_fault = kvm_tdp_page_fault;
e8bc217a 4882 context->sync_page = nonpaging_sync_page;
5efac074 4883 context->invlpg = NULL;
0f53b5b1 4884 context->update_pte = nonpaging_update_pte;
e93fd3b3 4885 context->shadow_root_level = vcpu->arch.tdp_level;
c5a78f2b 4886 context->direct_map = true;
d8dd54e0 4887 context->get_guest_pgd = get_cr3;
e4e517b4 4888 context->get_pdptr = kvm_pdptr_read;
cb659db8 4889 context->inject_page_fault = kvm_inject_page_fault;
fb72d167
JR
4890
4891 if (!is_paging(vcpu)) {
2d48a985 4892 context->nx = false;
fb72d167
JR
4893 context->gva_to_gpa = nonpaging_gva_to_gpa;
4894 context->root_level = 0;
4895 } else if (is_long_mode(vcpu)) {
2d48a985 4896 context->nx = is_nx(vcpu);
855feb67
YZ
4897 context->root_level = is_la57_mode(vcpu) ?
4898 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4d6931c3
DB
4899 reset_rsvds_bits_mask(vcpu, context);
4900 context->gva_to_gpa = paging64_gva_to_gpa;
fb72d167 4901 } else if (is_pae(vcpu)) {
2d48a985 4902 context->nx = is_nx(vcpu);
fb72d167 4903 context->root_level = PT32E_ROOT_LEVEL;
4d6931c3
DB
4904 reset_rsvds_bits_mask(vcpu, context);
4905 context->gva_to_gpa = paging64_gva_to_gpa;
fb72d167 4906 } else {
2d48a985 4907 context->nx = false;
fb72d167 4908 context->root_level = PT32_ROOT_LEVEL;
4d6931c3
DB
4909 reset_rsvds_bits_mask(vcpu, context);
4910 context->gva_to_gpa = paging32_gva_to_gpa;
fb72d167
JR
4911 }
4912
25d92081 4913 update_permission_bitmask(vcpu, context, false);
2d344105 4914 update_pkru_bitmask(vcpu, context, false);
6bb69c9b 4915 update_last_nonleaf_level(vcpu, context);
c258b62b 4916 reset_tdp_shadow_zero_bits_mask(vcpu, context);
fb72d167
JR
4917}
4918
7dcd5755
VK
4919static union kvm_mmu_role
4920kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4921{
4922 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4923
4924 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4925 !is_write_protection(vcpu);
4926 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4927 !is_write_protection(vcpu);
4928 role.base.direct = !is_paging(vcpu);
47c42e6b 4929 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
9fa72119
JS
4930
4931 if (!is_long_mode(vcpu))
7dcd5755 4932 role.base.level = PT32E_ROOT_LEVEL;
9fa72119 4933 else if (is_la57_mode(vcpu))
7dcd5755 4934 role.base.level = PT64_ROOT_5LEVEL;
9fa72119 4935 else
7dcd5755 4936 role.base.level = PT64_ROOT_4LEVEL;
9fa72119
JS
4937
4938 return role;
4939}
4940
929d1cfa 4941void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
9fa72119 4942{
44dd3ffa 4943 struct kvm_mmu *context = vcpu->arch.mmu;
7dcd5755
VK
4944 union kvm_mmu_role new_role =
4945 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4946
7dcd5755
VK
4947 if (new_role.as_u64 == context->mmu_role.as_u64)
4948 return;
6aa8b732 4949
929d1cfa 4950 if (!(cr0 & X86_CR0_PG))
8a3c1a33 4951 nonpaging_init_context(vcpu, context);
929d1cfa 4952 else if (efer & EFER_LMA)
8a3c1a33 4953 paging64_init_context(vcpu, context);
929d1cfa 4954 else if (cr4 & X86_CR4_PAE)
8a3c1a33 4955 paging32E_init_context(vcpu, context);
6aa8b732 4956 else
8a3c1a33 4957 paging32_init_context(vcpu, context);
a770f6f2 4958
7dcd5755 4959 context->mmu_role.as_u64 = new_role.as_u64;
c258b62b 4960 reset_shadow_zero_bits_mask(vcpu, context);
52fde8df
JR
4961}
4962EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4963
a336282d
VK
4964static union kvm_mmu_role
4965kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
bb1fcc70 4966 bool execonly, u8 level)
9fa72119 4967{
552c69b1 4968 union kvm_mmu_role role = {0};
14c07ad8 4969
47c42e6b
SC
4970 /* SMM flag is inherited from root_mmu */
4971 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
9fa72119 4972
bb1fcc70 4973 role.base.level = level;
47c42e6b 4974 role.base.gpte_is_8_bytes = true;
a336282d
VK
4975 role.base.direct = false;
4976 role.base.ad_disabled = !accessed_dirty;
4977 role.base.guest_mode = true;
4978 role.base.access = ACC_ALL;
9fa72119 4979
47c42e6b
SC
4980 /*
4981 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4982 * SMAP variation to denote shadow EPT entries.
4983 */
4984 role.base.cr0_wp = true;
4985 role.base.smap_andnot_wp = true;
4986
552c69b1 4987 role.ext = kvm_calc_mmu_role_ext(vcpu);
a336282d 4988 role.ext.execonly = execonly;
9fa72119
JS
4989
4990 return role;
4991}
4992
ae1e2d10 4993void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
50c28f21 4994 bool accessed_dirty, gpa_t new_eptp)
155a97a3 4995{
44dd3ffa 4996 struct kvm_mmu *context = vcpu->arch.mmu;
bb1fcc70 4997 u8 level = vmx_eptp_page_walk_level(new_eptp);
a336282d
VK
4998 union kvm_mmu_role new_role =
4999 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
bb1fcc70 5000 execonly, level);
a336282d 5001
be01e8e2 5002 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
a336282d 5003
a336282d
VK
5004 if (new_role.as_u64 == context->mmu_role.as_u64)
5005 return;
ad896af0 5006
bb1fcc70 5007 context->shadow_root_level = level;
155a97a3
NHE
5008
5009 context->nx = true;
ae1e2d10 5010 context->ept_ad = accessed_dirty;
155a97a3
NHE
5011 context->page_fault = ept_page_fault;
5012 context->gva_to_gpa = ept_gva_to_gpa;
5013 context->sync_page = ept_sync_page;
5014 context->invlpg = ept_invlpg;
5015 context->update_pte = ept_update_pte;
bb1fcc70 5016 context->root_level = level;
155a97a3 5017 context->direct_map = false;
a336282d 5018 context->mmu_role.as_u64 = new_role.as_u64;
3dc773e7 5019
155a97a3 5020 update_permission_bitmask(vcpu, context, true);
2d344105 5021 update_pkru_bitmask(vcpu, context, true);
fd19d3b4 5022 update_last_nonleaf_level(vcpu, context);
155a97a3 5023 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
c258b62b 5024 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
155a97a3
NHE
5025}
5026EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
5027
8a3c1a33 5028static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
52fde8df 5029{
44dd3ffa 5030 struct kvm_mmu *context = vcpu->arch.mmu;
ad896af0 5031
929d1cfa
PB
5032 kvm_init_shadow_mmu(vcpu,
5033 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
5034 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
5035 vcpu->arch.efer);
5036
d8dd54e0 5037 context->get_guest_pgd = get_cr3;
ad896af0
PB
5038 context->get_pdptr = kvm_pdptr_read;
5039 context->inject_page_fault = kvm_inject_page_fault;
6aa8b732
AK
5040}
5041
8a3c1a33 5042static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
02f59dc9 5043{
bf627a92 5044 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
02f59dc9
JR
5045 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
5046
bf627a92
VK
5047 if (new_role.as_u64 == g_context->mmu_role.as_u64)
5048 return;
5049
5050 g_context->mmu_role.as_u64 = new_role.as_u64;
d8dd54e0 5051 g_context->get_guest_pgd = get_cr3;
e4e517b4 5052 g_context->get_pdptr = kvm_pdptr_read;
02f59dc9
JR
5053 g_context->inject_page_fault = kvm_inject_page_fault;
5054
5efac074
PB
5055 /*
5056 * L2 page tables are never shadowed, so there is no need to sync
5057 * SPTEs.
5058 */
5059 g_context->invlpg = NULL;
5060
02f59dc9 5061 /*
44dd3ffa 5062 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
0af2593b
DM
5063 * L1's nested page tables (e.g. EPT12). The nested translation
5064 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5065 * L2's page tables as the first level of translation and L1's
5066 * nested page tables as the second level of translation. Basically
5067 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
02f59dc9
JR
5068 */
5069 if (!is_paging(vcpu)) {
2d48a985 5070 g_context->nx = false;
02f59dc9
JR
5071 g_context->root_level = 0;
5072 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5073 } else if (is_long_mode(vcpu)) {
2d48a985 5074 g_context->nx = is_nx(vcpu);
855feb67
YZ
5075 g_context->root_level = is_la57_mode(vcpu) ?
5076 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4d6931c3 5077 reset_rsvds_bits_mask(vcpu, g_context);
02f59dc9
JR
5078 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5079 } else if (is_pae(vcpu)) {
2d48a985 5080 g_context->nx = is_nx(vcpu);
02f59dc9 5081 g_context->root_level = PT32E_ROOT_LEVEL;
4d6931c3 5082 reset_rsvds_bits_mask(vcpu, g_context);
02f59dc9
JR
5083 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5084 } else {
2d48a985 5085 g_context->nx = false;
02f59dc9 5086 g_context->root_level = PT32_ROOT_LEVEL;
4d6931c3 5087 reset_rsvds_bits_mask(vcpu, g_context);
02f59dc9
JR
5088 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5089 }
5090
25d92081 5091 update_permission_bitmask(vcpu, g_context, false);
2d344105 5092 update_pkru_bitmask(vcpu, g_context, false);
6bb69c9b 5093 update_last_nonleaf_level(vcpu, g_context);
02f59dc9
JR
5094}
5095
1c53da3f 5096void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
fb72d167 5097{
1c53da3f 5098 if (reset_roots) {
b94742c9
JS
5099 uint i;
5100
44dd3ffa 5101 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
b94742c9
JS
5102
5103 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
44dd3ffa 5104 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
1c53da3f
JS
5105 }
5106
02f59dc9 5107 if (mmu_is_nested(vcpu))
e0c6db3e 5108 init_kvm_nested_mmu(vcpu);
02f59dc9 5109 else if (tdp_enabled)
e0c6db3e 5110 init_kvm_tdp_mmu(vcpu);
fb72d167 5111 else
e0c6db3e 5112 init_kvm_softmmu(vcpu);
fb72d167 5113}
1c53da3f 5114EXPORT_SYMBOL_GPL(kvm_init_mmu);
fb72d167 5115
9fa72119
JS
5116static union kvm_mmu_page_role
5117kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5118{
7dcd5755
VK
5119 union kvm_mmu_role role;
5120
9fa72119 5121 if (tdp_enabled)
7dcd5755 5122 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
9fa72119 5123 else
7dcd5755
VK
5124 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5125
5126 return role.base;
9fa72119 5127}
fb72d167 5128
8a3c1a33 5129void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
6aa8b732 5130{
95f93af4 5131 kvm_mmu_unload(vcpu);
1c53da3f 5132 kvm_init_mmu(vcpu, true);
17c3ba9d 5133}
8668a3c4 5134EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK
5135
5136int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 5137{
714b93da
AK
5138 int r;
5139
e2dec939 5140 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK
5141 if (r)
5142 goto out;
8986ecc0 5143 r = mmu_alloc_roots(vcpu);
e2858b4a 5144 kvm_mmu_sync_roots(vcpu);
8986ecc0
MT
5145 if (r)
5146 goto out;
727a7e27 5147 kvm_mmu_load_pgd(vcpu);
8c8560b8 5148 kvm_x86_ops.tlb_flush_current(vcpu);
714b93da
AK
5149out:
5150 return r;
6aa8b732 5151}
17c3ba9d
AK
5152EXPORT_SYMBOL_GPL(kvm_mmu_load);
5153
5154void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5155{
14c07ad8
VK
5156 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5157 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5158 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5159 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
17c3ba9d 5160}
4b16184c 5161EXPORT_SYMBOL_GPL(kvm_mmu_unload);
6aa8b732 5162
0028425f 5163static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
7c562522
XG
5164 struct kvm_mmu_page *sp, u64 *spte,
5165 const void *new)
0028425f 5166{
3bae0459 5167 if (sp->role.level != PG_LEVEL_4K) {
7e4e4056
JR
5168 ++vcpu->kvm->stat.mmu_pde_zapped;
5169 return;
30945387 5170 }
0028425f 5171
4cee5764 5172 ++vcpu->kvm->stat.mmu_pte_updated;
44dd3ffa 5173 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
0028425f
AK
5174}
5175
79539cec
AK
5176static bool need_remote_flush(u64 old, u64 new)
5177{
5178 if (!is_shadow_present_pte(old))
5179 return false;
5180 if (!is_shadow_present_pte(new))
5181 return true;
5182 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5183 return true;
53166229
GN
5184 old ^= shadow_nx_mask;
5185 new ^= shadow_nx_mask;
79539cec
AK
5186 return (old & ~new & PT64_PERM_MASK) != 0;
5187}
5188
889e5cbc 5189static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
0e0fee5c 5190 int *bytes)
da4a00f0 5191{
0e0fee5c 5192 u64 gentry = 0;
889e5cbc 5193 int r;
72016f3a 5194
72016f3a
AK
5195 /*
5196 * Assume that the pte write on a page table of the same type
49b26e26
XG
5197 * as the current vcpu paging mode since we update the sptes only
5198 * when they have the same mode.
72016f3a 5199 */
889e5cbc 5200 if (is_pae(vcpu) && *bytes == 4) {
72016f3a 5201 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
889e5cbc
XG
5202 *gpa &= ~(gpa_t)7;
5203 *bytes = 8;
08e850c6
AK
5204 }
5205
0e0fee5c
JS
5206 if (*bytes == 4 || *bytes == 8) {
5207 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5208 if (r)
5209 gentry = 0;
72016f3a
AK
5210 }
5211
889e5cbc
XG
5212 return gentry;
5213}
5214
5215/*
5216 * If we're seeing too many writes to a page, it may no longer be a page table,
5217 * or we may be forking, in which case it is better to unmap the page.
5218 */
a138fe75 5219static bool detect_write_flooding(struct kvm_mmu_page *sp)
889e5cbc 5220{
a30f47cb
XG
5221 /*
5222 * Skip write-flooding detected for the sp whose level is 1, because
5223 * it can become unsync, then the guest page is not write-protected.
5224 */
3bae0459 5225 if (sp->role.level == PG_LEVEL_4K)
a30f47cb 5226 return false;
3246af0e 5227
e5691a81
XG
5228 atomic_inc(&sp->write_flooding_count);
5229 return atomic_read(&sp->write_flooding_count) >= 3;
889e5cbc
XG
5230}
5231
5232/*
5233 * Misaligned accesses are too much trouble to fix up; also, they usually
5234 * indicate a page is not used as a page table.
5235 */
5236static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5237 int bytes)
5238{
5239 unsigned offset, pte_size, misaligned;
5240
5241 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5242 gpa, bytes, sp->role.word);
5243
5244 offset = offset_in_page(gpa);
47c42e6b 5245 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5d9ca30e
XG
5246
5247 /*
5248 * Sometimes, the OS only writes the last one bytes to update status
5249 * bits, for example, in linux, andb instruction is used in clear_bit().
5250 */
5251 if (!(offset & (pte_size - 1)) && bytes == 1)
5252 return false;
5253
889e5cbc
XG
5254 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5255 misaligned |= bytes < 4;
5256
5257 return misaligned;
5258}
5259
5260static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5261{
5262 unsigned page_offset, quadrant;
5263 u64 *spte;
5264 int level;
5265
5266 page_offset = offset_in_page(gpa);
5267 level = sp->role.level;
5268 *nspte = 1;
47c42e6b 5269 if (!sp->role.gpte_is_8_bytes) {
889e5cbc
XG
5270 page_offset <<= 1; /* 32->64 */
5271 /*
5272 * A 32-bit pde maps 4MB while the shadow pdes map
5273 * only 2MB. So we need to double the offset again
5274 * and zap two pdes instead of one.
5275 */
5276 if (level == PT32_ROOT_LEVEL) {
5277 page_offset &= ~7; /* kill rounding error */
5278 page_offset <<= 1;
5279 *nspte = 2;
5280 }
5281 quadrant = page_offset >> PAGE_SHIFT;
5282 page_offset &= ~PAGE_MASK;
5283 if (quadrant != sp->role.quadrant)
5284 return NULL;
5285 }
5286
5287 spte = &sp->spt[page_offset / sizeof(*spte)];
5288 return spte;
5289}
5290
a102a674
SC
5291/*
5292 * Ignore various flags when determining if a SPTE can be immediately
5293 * overwritten for the current MMU.
5294 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
5295 * match the current MMU role, as MMU's level tracks the root level.
5296 * - access: updated based on the new guest PTE
5297 * - quadrant: handled by get_written_sptes()
5298 * - invalid: always false (loop only walks valid shadow pages)
5299 */
5300static const union kvm_mmu_page_role role_ign = {
5301 .level = 0xf,
5302 .access = 0x7,
5303 .quadrant = 0x3,
5304 .invalid = 0x1,
5305};
5306
13d268ca 5307static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
d126363d
JS
5308 const u8 *new, int bytes,
5309 struct kvm_page_track_notifier_node *node)
889e5cbc
XG
5310{
5311 gfn_t gfn = gpa >> PAGE_SHIFT;
889e5cbc 5312 struct kvm_mmu_page *sp;
889e5cbc
XG
5313 LIST_HEAD(invalid_list);
5314 u64 entry, gentry, *spte;
5315 int npte;
b8c67b7a 5316 bool remote_flush, local_flush;
889e5cbc
XG
5317
5318 /*
5319 * If we don't have indirect shadow pages, it means no page is
5320 * write-protected, so we can exit simply.
5321 */
6aa7de05 5322 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
889e5cbc
XG
5323 return;
5324
b8c67b7a 5325 remote_flush = local_flush = false;
889e5cbc
XG
5326
5327 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5328
889e5cbc
XG
5329 /*
5330 * No need to care whether allocation memory is successful
5331 * or not since pte prefetch is skiped if it does not have
5332 * enough objects in the cache.
5333 */
5334 mmu_topup_memory_caches(vcpu);
5335
5336 spin_lock(&vcpu->kvm->mmu_lock);
0e0fee5c
JS
5337
5338 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5339
889e5cbc 5340 ++vcpu->kvm->stat.mmu_pte_write;
0375f7fa 5341 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
889e5cbc 5342
b67bfe0d 5343 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
a30f47cb 5344 if (detect_write_misaligned(sp, gpa, bytes) ||
a138fe75 5345 detect_write_flooding(sp)) {
b8c67b7a 5346 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4cee5764 5347 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK
5348 continue;
5349 }
889e5cbc
XG
5350
5351 spte = get_written_sptes(sp, gpa, &npte);
5352 if (!spte)
5353 continue;
5354
0671a8e7 5355 local_flush = true;
ac1b714e 5356 while (npte--) {
36d9594d
VK
5357 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5358
79539cec 5359 entry = *spte;
38e3b2b2 5360 mmu_page_zap_pte(vcpu->kvm, sp, spte);
fa1de2bf 5361 if (gentry &&
a102a674
SC
5362 !((sp->role.word ^ base_role) & ~role_ign.word) &&
5363 rmap_can_add(vcpu))
7c562522 5364 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
9bb4f6b1 5365 if (need_remote_flush(entry, *spte))
0671a8e7 5366 remote_flush = true;
ac1b714e 5367 ++spte;
9b7a0325 5368 }
9b7a0325 5369 }
b8c67b7a 5370 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
0375f7fa 5371 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
aaee2c94 5372 spin_unlock(&vcpu->kvm->mmu_lock);
da4a00f0
AK
5373}
5374
a436036b
AK
5375int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5376{
10589a46
MT
5377 gpa_t gpa;
5378 int r;
a436036b 5379
44dd3ffa 5380 if (vcpu->arch.mmu->direct_map)
60f24784
AK
5381 return 0;
5382
1871c602 5383 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 5384
10589a46 5385 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
1cb3f3ae 5386
10589a46 5387 return r;
a436036b 5388}
577bdc49 5389EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 5390
736c291c 5391int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
dc25e89e 5392 void *insn, int insn_len)
3067714c 5393{
92daa48b 5394 int r, emulation_type = EMULTYPE_PF;
44dd3ffa 5395 bool direct = vcpu->arch.mmu->direct_map;
3067714c 5396
6948199a 5397 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
ddce6208
SC
5398 return RET_PF_RETRY;
5399
9b8ebbdb 5400 r = RET_PF_INVALID;
e9ee956e 5401 if (unlikely(error_code & PFERR_RSVD_MASK)) {
736c291c 5402 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
472faffa 5403 if (r == RET_PF_EMULATE)
e9ee956e 5404 goto emulate;
e9ee956e 5405 }
3067714c 5406
9b8ebbdb 5407 if (r == RET_PF_INVALID) {
7a02674d
SC
5408 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5409 lower_32_bits(error_code), false);
9b8ebbdb
PB
5410 WARN_ON(r == RET_PF_INVALID);
5411 }
5412
5413 if (r == RET_PF_RETRY)
5414 return 1;
3067714c 5415 if (r < 0)
e9ee956e 5416 return r;
3067714c 5417
14727754
TL
5418 /*
5419 * Before emulating the instruction, check if the error code
5420 * was due to a RO violation while translating the guest page.
5421 * This can occur when using nested virtualization with nested
5422 * paging in both guests. If true, we simply unprotect the page
5423 * and resume the guest.
14727754 5424 */
44dd3ffa 5425 if (vcpu->arch.mmu->direct_map &&
eebed243 5426 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
736c291c 5427 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
14727754
TL
5428 return 1;
5429 }
5430
472faffa
SC
5431 /*
5432 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5433 * optimistically try to just unprotect the page and let the processor
5434 * re-execute the instruction that caused the page fault. Do not allow
5435 * retrying MMIO emulation, as it's not only pointless but could also
5436 * cause us to enter an infinite loop because the processor will keep
6c3dfeb6
SC
5437 * faulting on the non-existent MMIO address. Retrying an instruction
5438 * from a nested guest is also pointless and dangerous as we are only
5439 * explicitly shadowing L1's page tables, i.e. unprotecting something
5440 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
472faffa 5441 */
736c291c 5442 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
92daa48b 5443 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
e9ee956e 5444emulate:
00b10fe1
BS
5445 /*
5446 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5447 * This can happen if a guest gets a page-fault on data access but the HW
5448 * table walker is not able to read the instruction page (e.g instruction
5449 * page is not present in memory). In those cases we simply restart the
05d5a486 5450 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
00b10fe1 5451 */
05d5a486 5452 if (unlikely(insn && !insn_len)) {
afaf0b2f 5453 if (!kvm_x86_ops.need_emulation_on_page_fault(vcpu))
05d5a486
SB
5454 return 1;
5455 }
00b10fe1 5456
736c291c 5457 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
60fc3d02 5458 insn_len);
3067714c
AK
5459}
5460EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5461
5efac074
PB
5462void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5463 gva_t gva, hpa_t root_hpa)
a7052897 5464{
b94742c9 5465 int i;
7eb77e9f 5466
5efac074
PB
5467 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5468 if (mmu != &vcpu->arch.guest_mmu) {
5469 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5470 if (is_noncanonical_address(gva, vcpu))
5471 return;
5472
5473 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5474 }
5475
5476 if (!mmu->invlpg)
faff8758
JS
5477 return;
5478
5efac074
PB
5479 if (root_hpa == INVALID_PAGE) {
5480 mmu->invlpg(vcpu, gva, mmu->root_hpa);
956bf353 5481
5efac074
PB
5482 /*
5483 * INVLPG is required to invalidate any global mappings for the VA,
5484 * irrespective of PCID. Since it would take us roughly similar amount
5485 * of work to determine whether any of the prev_root mappings of the VA
5486 * is marked global, or to just sync it blindly, so we might as well
5487 * just always sync it.
5488 *
5489 * Mappings not reachable via the current cr3 or the prev_roots will be
5490 * synced when switching to that cr3, so nothing needs to be done here
5491 * for them.
5492 */
5493 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5494 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5495 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5496 } else {
5497 mmu->invlpg(vcpu, gva, root_hpa);
5498 }
5499}
5500EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
956bf353 5501
5efac074
PB
5502void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5503{
5504 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
a7052897
MT
5505 ++vcpu->stat.invlpg;
5506}
5507EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5508
5efac074 5509
eb4b248e
JS
5510void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5511{
44dd3ffa 5512 struct kvm_mmu *mmu = vcpu->arch.mmu;
faff8758 5513 bool tlb_flush = false;
b94742c9 5514 uint i;
eb4b248e
JS
5515
5516 if (pcid == kvm_get_active_pcid(vcpu)) {
7eb77e9f 5517 mmu->invlpg(vcpu, gva, mmu->root_hpa);
faff8758 5518 tlb_flush = true;
eb4b248e
JS
5519 }
5520
b94742c9
JS
5521 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5522 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
be01e8e2 5523 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
b94742c9
JS
5524 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5525 tlb_flush = true;
5526 }
956bf353 5527 }
ade61e28 5528
faff8758 5529 if (tlb_flush)
afaf0b2f 5530 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
faff8758 5531
eb4b248e
JS
5532 ++vcpu->stat.invlpg;
5533
5534 /*
b94742c9
JS
5535 * Mappings not reachable via the current cr3 or the prev_roots will be
5536 * synced when switching to that cr3, so nothing needs to be done here
5537 * for them.
eb4b248e
JS
5538 */
5539}
5540EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5541
703c335d 5542void kvm_configure_mmu(bool enable_tdp, int tdp_page_level)
18552672 5543{
bde77235 5544 tdp_enabled = enable_tdp;
703c335d
SC
5545
5546 /*
5547 * max_page_level reflects the capabilities of KVM's MMU irrespective
5548 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5549 * the kernel is not. But, KVM never creates a page size greater than
5550 * what is used by the kernel for any given HVA, i.e. the kernel's
5551 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5552 */
5553 if (tdp_enabled)
5554 max_page_level = tdp_page_level;
5555 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
3bae0459 5556 max_page_level = PG_LEVEL_1G;
703c335d 5557 else
3bae0459 5558 max_page_level = PG_LEVEL_2M;
18552672 5559}
bde77235 5560EXPORT_SYMBOL_GPL(kvm_configure_mmu);
85875a13
SC
5561
5562/* The return value indicates if tlb flush on all vcpus is needed. */
5563typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5564
5565/* The caller should hold mmu-lock before calling this function. */
5566static __always_inline bool
5567slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5568 slot_level_handler fn, int start_level, int end_level,
5569 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5570{
5571 struct slot_rmap_walk_iterator iterator;
5572 bool flush = false;
5573
5574 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5575 end_gfn, &iterator) {
5576 if (iterator.rmap)
5577 flush |= fn(kvm, iterator.rmap);
5578
5579 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5580 if (flush && lock_flush_tlb) {
f285c633
BG
5581 kvm_flush_remote_tlbs_with_address(kvm,
5582 start_gfn,
5583 iterator.gfn - start_gfn + 1);
85875a13
SC
5584 flush = false;
5585 }
5586 cond_resched_lock(&kvm->mmu_lock);
5587 }
5588 }
5589
5590 if (flush && lock_flush_tlb) {
f285c633
BG
5591 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5592 end_gfn - start_gfn + 1);
85875a13
SC
5593 flush = false;
5594 }
5595
5596 return flush;
5597}
5598
5599static __always_inline bool
5600slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5601 slot_level_handler fn, int start_level, int end_level,
5602 bool lock_flush_tlb)
5603{
5604 return slot_handle_level_range(kvm, memslot, fn, start_level,
5605 end_level, memslot->base_gfn,
5606 memslot->base_gfn + memslot->npages - 1,
5607 lock_flush_tlb);
5608}
5609
5610static __always_inline bool
5611slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5612 slot_level_handler fn, bool lock_flush_tlb)
5613{
3bae0459 5614 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
e662ec3e 5615 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
85875a13
SC
5616}
5617
5618static __always_inline bool
5619slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5620 slot_level_handler fn, bool lock_flush_tlb)
5621{
3bae0459 5622 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
e662ec3e 5623 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
85875a13
SC
5624}
5625
5626static __always_inline bool
5627slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5628 slot_level_handler fn, bool lock_flush_tlb)
5629{
3bae0459
SC
5630 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5631 PG_LEVEL_4K, lock_flush_tlb);
85875a13
SC
5632}
5633
1cfff4d9 5634static void free_mmu_pages(struct kvm_mmu *mmu)
6aa8b732 5635{
1cfff4d9
JP
5636 free_page((unsigned long)mmu->pae_root);
5637 free_page((unsigned long)mmu->lm_root);
6aa8b732
AK
5638}
5639
1cfff4d9 5640static int alloc_mmu_pages(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
6aa8b732 5641{
17ac10ad 5642 struct page *page;
6aa8b732
AK
5643 int i;
5644
17ac10ad 5645 /*
b6b80c78
SC
5646 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5647 * while the PDP table is a per-vCPU construct that's allocated at MMU
5648 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5649 * x86_64. Therefore we need to allocate the PDP table in the first
5650 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5651 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5652 * skip allocating the PDP table.
17ac10ad 5653 */
e93fd3b3 5654 if (tdp_enabled && vcpu->arch.tdp_level > PT32E_ROOT_LEVEL)
b6b80c78
SC
5655 return 0;
5656
254272ce 5657 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
17ac10ad 5658 if (!page)
d7fa6ab2
WY
5659 return -ENOMEM;
5660
1cfff4d9 5661 mmu->pae_root = page_address(page);
17ac10ad 5662 for (i = 0; i < 4; ++i)
1cfff4d9 5663 mmu->pae_root[i] = INVALID_PAGE;
17ac10ad 5664
6aa8b732 5665 return 0;
6aa8b732
AK
5666}
5667
8018c27b 5668int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 5669{
b94742c9 5670 uint i;
1cfff4d9 5671 int ret;
b94742c9 5672
44dd3ffa
VK
5673 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5674 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
6aa8b732 5675
44dd3ffa 5676 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
be01e8e2 5677 vcpu->arch.root_mmu.root_pgd = 0;
44dd3ffa 5678 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
b94742c9 5679 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
44dd3ffa 5680 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
6aa8b732 5681
14c07ad8 5682 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
be01e8e2 5683 vcpu->arch.guest_mmu.root_pgd = 0;
14c07ad8
VK
5684 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5685 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5686 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
2c264957 5687
14c07ad8 5688 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
1cfff4d9
JP
5689
5690 ret = alloc_mmu_pages(vcpu, &vcpu->arch.guest_mmu);
5691 if (ret)
5692 return ret;
5693
5694 ret = alloc_mmu_pages(vcpu, &vcpu->arch.root_mmu);
5695 if (ret)
5696 goto fail_allocate_root;
5697
5698 return ret;
5699 fail_allocate_root:
5700 free_mmu_pages(&vcpu->arch.guest_mmu);
5701 return ret;
6aa8b732
AK
5702}
5703
fbb158cb 5704#define BATCH_ZAP_PAGES 10
002c5f73
SC
5705static void kvm_zap_obsolete_pages(struct kvm *kvm)
5706{
5707 struct kvm_mmu_page *sp, *node;
fbb158cb 5708 int nr_zapped, batch = 0;
002c5f73
SC
5709
5710restart:
5711 list_for_each_entry_safe_reverse(sp, node,
5712 &kvm->arch.active_mmu_pages, link) {
5713 /*
5714 * No obsolete valid page exists before a newly created page
5715 * since active_mmu_pages is a FIFO list.
5716 */
5717 if (!is_obsolete_sp(kvm, sp))
5718 break;
5719
5720 /*
9a5c034c
SC
5721 * Skip invalid pages with a non-zero root count, zapping pages
5722 * with a non-zero root count will never succeed, i.e. the page
5723 * will get thrown back on active_mmu_pages and we'll get stuck
5724 * in an infinite loop.
002c5f73 5725 */
9a5c034c 5726 if (sp->role.invalid && sp->root_count)
002c5f73
SC
5727 continue;
5728
4506ecf4
SC
5729 /*
5730 * No need to flush the TLB since we're only zapping shadow
5731 * pages with an obsolete generation number and all vCPUS have
5732 * loaded a new root, i.e. the shadow pages being zapped cannot
5733 * be in active use by the guest.
5734 */
fbb158cb 5735 if (batch >= BATCH_ZAP_PAGES &&
4506ecf4 5736 cond_resched_lock(&kvm->mmu_lock)) {
fbb158cb 5737 batch = 0;
002c5f73
SC
5738 goto restart;
5739 }
5740
10605204
SC
5741 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5742 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
fbb158cb 5743 batch += nr_zapped;
002c5f73 5744 goto restart;
fbb158cb 5745 }
002c5f73
SC
5746 }
5747
4506ecf4
SC
5748 /*
5749 * Trigger a remote TLB flush before freeing the page tables to ensure
5750 * KVM is not in the middle of a lockless shadow page table walk, which
5751 * may reference the pages.
5752 */
10605204 5753 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
002c5f73
SC
5754}
5755
5756/*
5757 * Fast invalidate all shadow pages and use lock-break technique
5758 * to zap obsolete pages.
5759 *
5760 * It's required when memslot is being deleted or VM is being
5761 * destroyed, in these cases, we should ensure that KVM MMU does
5762 * not use any resource of the being-deleted slot or all slots
5763 * after calling the function.
5764 */
5765static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5766{
ca333add
SC
5767 lockdep_assert_held(&kvm->slots_lock);
5768
002c5f73 5769 spin_lock(&kvm->mmu_lock);
14a3c4f4 5770 trace_kvm_mmu_zap_all_fast(kvm);
ca333add
SC
5771
5772 /*
5773 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5774 * held for the entire duration of zapping obsolete pages, it's
5775 * impossible for there to be multiple invalid generations associated
5776 * with *valid* shadow pages at any given time, i.e. there is exactly
5777 * one valid generation and (at most) one invalid generation.
5778 */
5779 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
002c5f73 5780
4506ecf4
SC
5781 /*
5782 * Notify all vcpus to reload its shadow page table and flush TLB.
5783 * Then all vcpus will switch to new shadow page table with the new
5784 * mmu_valid_gen.
5785 *
5786 * Note: we need to do this under the protection of mmu_lock,
5787 * otherwise, vcpu would purge shadow page but miss tlb flush.
5788 */
5789 kvm_reload_remote_mmus(kvm);
5790
002c5f73
SC
5791 kvm_zap_obsolete_pages(kvm);
5792 spin_unlock(&kvm->mmu_lock);
5793}
5794
10605204
SC
5795static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5796{
5797 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5798}
5799
b5f5fdca 5800static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
d126363d
JS
5801 struct kvm_memory_slot *slot,
5802 struct kvm_page_track_notifier_node *node)
b5f5fdca 5803{
002c5f73 5804 kvm_mmu_zap_all_fast(kvm);
1bad2b2a
XG
5805}
5806
13d268ca 5807void kvm_mmu_init_vm(struct kvm *kvm)
1bad2b2a 5808{
13d268ca 5809 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
1bad2b2a 5810
13d268ca 5811 node->track_write = kvm_mmu_pte_write;
b5f5fdca 5812 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
13d268ca 5813 kvm_page_track_register_notifier(kvm, node);
1bad2b2a
XG
5814}
5815
13d268ca 5816void kvm_mmu_uninit_vm(struct kvm *kvm)
1bad2b2a 5817{
13d268ca 5818 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
1bad2b2a 5819
13d268ca 5820 kvm_page_track_unregister_notifier(kvm, node);
1bad2b2a
XG
5821}
5822
efdfe536
XG
5823void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5824{
5825 struct kvm_memslots *slots;
5826 struct kvm_memory_slot *memslot;
9da0e4d5 5827 int i;
efdfe536
XG
5828
5829 spin_lock(&kvm->mmu_lock);
9da0e4d5
PB
5830 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5831 slots = __kvm_memslots(kvm, i);
5832 kvm_for_each_memslot(memslot, slots) {
5833 gfn_t start, end;
5834
5835 start = max(gfn_start, memslot->base_gfn);
5836 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5837 if (start >= end)
5838 continue;
efdfe536 5839
92da008f 5840 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
3bae0459 5841 PG_LEVEL_4K,
e662ec3e 5842 KVM_MAX_HUGEPAGE_LEVEL,
92da008f 5843 start, end - 1, true);
9da0e4d5 5844 }
efdfe536
XG
5845 }
5846
5847 spin_unlock(&kvm->mmu_lock);
5848}
5849
018aabb5
TY
5850static bool slot_rmap_write_protect(struct kvm *kvm,
5851 struct kvm_rmap_head *rmap_head)
d77aa73c 5852{
018aabb5 5853 return __rmap_write_protect(kvm, rmap_head, false);
d77aa73c
XG
5854}
5855
1c91cad4 5856void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
3c9bd400
JZ
5857 struct kvm_memory_slot *memslot,
5858 int start_level)
6aa8b732 5859{
d77aa73c 5860 bool flush;
6aa8b732 5861
9d1beefb 5862 spin_lock(&kvm->mmu_lock);
3c9bd400 5863 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
e662ec3e 5864 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
9d1beefb 5865 spin_unlock(&kvm->mmu_lock);
198c74f4 5866
198c74f4
XG
5867 /*
5868 * We can flush all the TLBs out of the mmu lock without TLB
5869 * corruption since we just change the spte from writable to
5870 * readonly so that we only need to care the case of changing
5871 * spte from present to present (changing the spte from present
5872 * to nonpresent will flush all the TLBs immediately), in other
5873 * words, the only case we care is mmu_spte_update() where we
bdd303cb 5874 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
198c74f4
XG
5875 * instead of PT_WRITABLE_MASK, that means it does not depend
5876 * on PT_WRITABLE_MASK anymore.
5877 */
d91ffee9 5878 if (flush)
7f42aa76 5879 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
6aa8b732 5880}
37a7d8b0 5881
3ea3b7fa 5882static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
018aabb5 5883 struct kvm_rmap_head *rmap_head)
3ea3b7fa
WL
5884{
5885 u64 *sptep;
5886 struct rmap_iterator iter;
5887 int need_tlb_flush = 0;
ba049e93 5888 kvm_pfn_t pfn;
3ea3b7fa
WL
5889 struct kvm_mmu_page *sp;
5890
0d536790 5891restart:
018aabb5 5892 for_each_rmap_spte(rmap_head, &iter, sptep) {
3ea3b7fa
WL
5893 sp = page_header(__pa(sptep));
5894 pfn = spte_to_pfn(*sptep);
5895
5896 /*
decf6333
XG
5897 * We cannot do huge page mapping for indirect shadow pages,
5898 * which are found on the last rmap (level = 1) when not using
5899 * tdp; such shadow pages are synced with the page table in
5900 * the guest, and the guest page table is using 4K page size
5901 * mapping if the indirect sp has level = 1.
3ea3b7fa 5902 */
a78986aa 5903 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
e851265a
SC
5904 (kvm_is_zone_device_pfn(pfn) ||
5905 PageCompound(pfn_to_page(pfn)))) {
e7912386 5906 pte_list_remove(rmap_head, sptep);
40ef75a7
LT
5907
5908 if (kvm_available_flush_tlb_with_range())
5909 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5910 KVM_PAGES_PER_HPAGE(sp->role.level));
5911 else
5912 need_tlb_flush = 1;
5913
0d536790
XG
5914 goto restart;
5915 }
3ea3b7fa
WL
5916 }
5917
5918 return need_tlb_flush;
5919}
5920
5921void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
f36f3f28 5922 const struct kvm_memory_slot *memslot)
3ea3b7fa 5923{
f36f3f28 5924 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
3ea3b7fa 5925 spin_lock(&kvm->mmu_lock);
f36f3f28
PB
5926 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5927 kvm_mmu_zap_collapsible_spte, true);
3ea3b7fa
WL
5928 spin_unlock(&kvm->mmu_lock);
5929}
5930
b3594ffb
SC
5931void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5932 struct kvm_memory_slot *memslot)
5933{
5934 /*
7f42aa76
SC
5935 * All current use cases for flushing the TLBs for a specific memslot
5936 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5937 * The interaction between the various operations on memslot must be
5938 * serialized by slots_locks to ensure the TLB flush from one operation
5939 * is observed by any other operation on the same memslot.
b3594ffb
SC
5940 */
5941 lockdep_assert_held(&kvm->slots_lock);
cec37648
SC
5942 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5943 memslot->npages);
b3594ffb
SC
5944}
5945
f4b4b180
KH
5946void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5947 struct kvm_memory_slot *memslot)
5948{
d77aa73c 5949 bool flush;
f4b4b180
KH
5950
5951 spin_lock(&kvm->mmu_lock);
d77aa73c 5952 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
f4b4b180
KH
5953 spin_unlock(&kvm->mmu_lock);
5954
f4b4b180
KH
5955 /*
5956 * It's also safe to flush TLBs out of mmu lock here as currently this
5957 * function is only used for dirty logging, in which case flushing TLB
5958 * out of mmu lock also guarantees no dirty pages will be lost in
5959 * dirty_bitmap.
5960 */
5961 if (flush)
7f42aa76 5962 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
f4b4b180
KH
5963}
5964EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5965
5966void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5967 struct kvm_memory_slot *memslot)
5968{
d77aa73c 5969 bool flush;
f4b4b180
KH
5970
5971 spin_lock(&kvm->mmu_lock);
d77aa73c
XG
5972 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5973 false);
f4b4b180
KH
5974 spin_unlock(&kvm->mmu_lock);
5975
f4b4b180 5976 if (flush)
7f42aa76 5977 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
f4b4b180
KH
5978}
5979EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5980
5981void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5982 struct kvm_memory_slot *memslot)
5983{
d77aa73c 5984 bool flush;
f4b4b180
KH
5985
5986 spin_lock(&kvm->mmu_lock);
d77aa73c 5987 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
f4b4b180
KH
5988 spin_unlock(&kvm->mmu_lock);
5989
f4b4b180 5990 if (flush)
7f42aa76 5991 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
f4b4b180
KH
5992}
5993EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5994
92f58b5c 5995void kvm_mmu_zap_all(struct kvm *kvm)
5304b8d3
XG
5996{
5997 struct kvm_mmu_page *sp, *node;
7390de1e 5998 LIST_HEAD(invalid_list);
83cdb568 5999 int ign;
5304b8d3 6000
7390de1e 6001 spin_lock(&kvm->mmu_lock);
5304b8d3 6002restart:
8a674adc 6003 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
8ab3c471 6004 if (sp->role.invalid && sp->root_count)
4771450c 6005 continue;
92f58b5c 6006 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5304b8d3 6007 goto restart;
24efe61f 6008 if (cond_resched_lock(&kvm->mmu_lock))
5304b8d3
XG
6009 goto restart;
6010 }
6011
4771450c 6012 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5304b8d3
XG
6013 spin_unlock(&kvm->mmu_lock);
6014}
6015
15248258 6016void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
f8f55942 6017{
164bf7e5 6018 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
e1359e2b 6019
164bf7e5 6020 gen &= MMIO_SPTE_GEN_MASK;
e1359e2b 6021
f8f55942 6022 /*
e1359e2b
SC
6023 * Generation numbers are incremented in multiples of the number of
6024 * address spaces in order to provide unique generations across all
6025 * address spaces. Strip what is effectively the address space
6026 * modifier prior to checking for a wrap of the MMIO generation so
6027 * that a wrap in any address space is detected.
6028 */
6029 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
6030
f8f55942 6031 /*
e1359e2b 6032 * The very rare case: if the MMIO generation number has wrapped,
f8f55942 6033 * zap all shadow pages.
f8f55942 6034 */
e1359e2b 6035 if (unlikely(gen == 0)) {
ae0f5499 6036 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
92f58b5c 6037 kvm_mmu_zap_all_fast(kvm);
7a2e8aaf 6038 }
f8f55942
XG
6039}
6040
70534a73
DC
6041static unsigned long
6042mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
3ee16c81
IE
6043{
6044 struct kvm *kvm;
1495f230 6045 int nr_to_scan = sc->nr_to_scan;
70534a73 6046 unsigned long freed = 0;
3ee16c81 6047
0d9ce162 6048 mutex_lock(&kvm_lock);
3ee16c81
IE
6049
6050 list_for_each_entry(kvm, &vm_list, vm_list) {
3d56cbdf 6051 int idx;
d98ba053 6052 LIST_HEAD(invalid_list);
3ee16c81 6053
35f2d16b
TY
6054 /*
6055 * Never scan more than sc->nr_to_scan VM instances.
6056 * Will not hit this condition practically since we do not try
6057 * to shrink more than one VM and it is very unlikely to see
6058 * !n_used_mmu_pages so many times.
6059 */
6060 if (!nr_to_scan--)
6061 break;
19526396
GN
6062 /*
6063 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6064 * here. We may skip a VM instance errorneosly, but we do not
6065 * want to shrink a VM that only started to populate its MMU
6066 * anyway.
6067 */
10605204
SC
6068 if (!kvm->arch.n_used_mmu_pages &&
6069 !kvm_has_zapped_obsolete_pages(kvm))
19526396 6070 continue;
19526396 6071
f656ce01 6072 idx = srcu_read_lock(&kvm->srcu);
3ee16c81 6073 spin_lock(&kvm->mmu_lock);
3ee16c81 6074
10605204
SC
6075 if (kvm_has_zapped_obsolete_pages(kvm)) {
6076 kvm_mmu_commit_zap_page(kvm,
6077 &kvm->arch.zapped_obsolete_pages);
6078 goto unlock;
6079 }
6080
70534a73
DC
6081 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
6082 freed++;
d98ba053 6083 kvm_mmu_commit_zap_page(kvm, &invalid_list);
19526396 6084
10605204 6085unlock:
3ee16c81 6086 spin_unlock(&kvm->mmu_lock);
f656ce01 6087 srcu_read_unlock(&kvm->srcu, idx);
19526396 6088
70534a73
DC
6089 /*
6090 * unfair on small ones
6091 * per-vm shrinkers cry out
6092 * sadness comes quickly
6093 */
19526396
GN
6094 list_move_tail(&kvm->vm_list, &vm_list);
6095 break;
3ee16c81 6096 }
3ee16c81 6097
0d9ce162 6098 mutex_unlock(&kvm_lock);
70534a73 6099 return freed;
70534a73
DC
6100}
6101
6102static unsigned long
6103mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
6104{
45221ab6 6105 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3ee16c81
IE
6106}
6107
6108static struct shrinker mmu_shrinker = {
70534a73
DC
6109 .count_objects = mmu_shrink_count,
6110 .scan_objects = mmu_shrink_scan,
3ee16c81
IE
6111 .seeks = DEFAULT_SEEKS * 10,
6112};
6113
2ddfd20e 6114static void mmu_destroy_caches(void)
b5a33a75 6115{
c1bd743e
TH
6116 kmem_cache_destroy(pte_list_desc_cache);
6117 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
6118}
6119
7b6f8a06
KH
6120static void kvm_set_mmio_spte_mask(void)
6121{
6122 u64 mask;
7b6f8a06
KH
6123
6124 /*
6129ed87
SC
6125 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
6126 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
6127 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
6128 * 52-bit physical addresses then there are no reserved PA bits in the
6129 * PTEs and so the reserved PA approach must be disabled.
7b6f8a06 6130 */
6129ed87
SC
6131 if (shadow_phys_bits < 52)
6132 mask = BIT_ULL(51) | PT_PRESENT_MASK;
6133 else
6134 mask = 0;
7b6f8a06 6135
e7581cac 6136 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
7b6f8a06
KH
6137}
6138
b8e8c830
PB
6139static bool get_nx_auto_mode(void)
6140{
6141 /* Return true when CPU has the bug, and mitigations are ON */
6142 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
6143}
6144
6145static void __set_nx_huge_pages(bool val)
6146{
6147 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
6148}
6149
6150static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
6151{
6152 bool old_val = nx_huge_pages;
6153 bool new_val;
6154
6155 /* In "auto" mode deploy workaround only if CPU has the bug. */
6156 if (sysfs_streq(val, "off"))
6157 new_val = 0;
6158 else if (sysfs_streq(val, "force"))
6159 new_val = 1;
6160 else if (sysfs_streq(val, "auto"))
6161 new_val = get_nx_auto_mode();
6162 else if (strtobool(val, &new_val) < 0)
6163 return -EINVAL;
6164
6165 __set_nx_huge_pages(new_val);
6166
6167 if (new_val != old_val) {
6168 struct kvm *kvm;
b8e8c830
PB
6169
6170 mutex_lock(&kvm_lock);
6171
6172 list_for_each_entry(kvm, &vm_list, vm_list) {
ed69a6cb 6173 mutex_lock(&kvm->slots_lock);
b8e8c830 6174 kvm_mmu_zap_all_fast(kvm);
ed69a6cb 6175 mutex_unlock(&kvm->slots_lock);
1aa9b957
JS
6176
6177 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
b8e8c830
PB
6178 }
6179 mutex_unlock(&kvm_lock);
6180 }
6181
6182 return 0;
6183}
6184
b5a33a75
AK
6185int kvm_mmu_module_init(void)
6186{
ab271bd4
AB
6187 int ret = -ENOMEM;
6188
b8e8c830
PB
6189 if (nx_huge_pages == -1)
6190 __set_nx_huge_pages(get_nx_auto_mode());
6191
36d9594d
VK
6192 /*
6193 * MMU roles use union aliasing which is, generally speaking, an
6194 * undefined behavior. However, we supposedly know how compilers behave
6195 * and the current status quo is unlikely to change. Guardians below are
6196 * supposed to let us know if the assumption becomes false.
6197 */
6198 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6199 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6200 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6201
28a1f3ac 6202 kvm_mmu_reset_all_pte_masks();
f160c7b7 6203
7b6f8a06
KH
6204 kvm_set_mmio_spte_mask();
6205
53c07b18
XG
6206 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6207 sizeof(struct pte_list_desc),
46bea48a 6208 0, SLAB_ACCOUNT, NULL);
53c07b18 6209 if (!pte_list_desc_cache)
ab271bd4 6210 goto out;
b5a33a75 6211
d3d25b04
AK
6212 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6213 sizeof(struct kvm_mmu_page),
46bea48a 6214 0, SLAB_ACCOUNT, NULL);
d3d25b04 6215 if (!mmu_page_header_cache)
ab271bd4 6216 goto out;
d3d25b04 6217
908c7f19 6218 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
ab271bd4 6219 goto out;
45bf21a8 6220
ab271bd4
AB
6221 ret = register_shrinker(&mmu_shrinker);
6222 if (ret)
6223 goto out;
3ee16c81 6224
b5a33a75
AK
6225 return 0;
6226
ab271bd4 6227out:
3ee16c81 6228 mmu_destroy_caches();
ab271bd4 6229 return ret;
b5a33a75
AK
6230}
6231
3ad82a7e 6232/*
39337ad1 6233 * Calculate mmu pages needed for kvm.
3ad82a7e 6234 */
bc8a3d89 6235unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
3ad82a7e 6236{
bc8a3d89
BG
6237 unsigned long nr_mmu_pages;
6238 unsigned long nr_pages = 0;
bc6678a3 6239 struct kvm_memslots *slots;
be6ba0f0 6240 struct kvm_memory_slot *memslot;
9da0e4d5 6241 int i;
3ad82a7e 6242
9da0e4d5
PB
6243 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6244 slots = __kvm_memslots(kvm, i);
90d83dc3 6245
9da0e4d5
PB
6246 kvm_for_each_memslot(memslot, slots)
6247 nr_pages += memslot->npages;
6248 }
3ad82a7e
ZX
6249
6250 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
bc8a3d89 6251 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
3ad82a7e
ZX
6252
6253 return nr_mmu_pages;
6254}
6255
c42fffe3
XG
6256void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6257{
95f93af4 6258 kvm_mmu_unload(vcpu);
1cfff4d9
JP
6259 free_mmu_pages(&vcpu->arch.root_mmu);
6260 free_mmu_pages(&vcpu->arch.guest_mmu);
c42fffe3 6261 mmu_free_memory_caches(vcpu);
b034cf01
XG
6262}
6263
b034cf01
XG
6264void kvm_mmu_module_exit(void)
6265{
6266 mmu_destroy_caches();
6267 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6268 unregister_shrinker(&mmu_shrinker);
c42fffe3
XG
6269 mmu_audit_disable();
6270}
1aa9b957
JS
6271
6272static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6273{
6274 unsigned int old_val;
6275 int err;
6276
6277 old_val = nx_huge_pages_recovery_ratio;
6278 err = param_set_uint(val, kp);
6279 if (err)
6280 return err;
6281
6282 if (READ_ONCE(nx_huge_pages) &&
6283 !old_val && nx_huge_pages_recovery_ratio) {
6284 struct kvm *kvm;
6285
6286 mutex_lock(&kvm_lock);
6287
6288 list_for_each_entry(kvm, &vm_list, vm_list)
6289 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6290
6291 mutex_unlock(&kvm_lock);
6292 }
6293
6294 return err;
6295}
6296
6297static void kvm_recover_nx_lpages(struct kvm *kvm)
6298{
6299 int rcu_idx;
6300 struct kvm_mmu_page *sp;
6301 unsigned int ratio;
6302 LIST_HEAD(invalid_list);
6303 ulong to_zap;
6304
6305 rcu_idx = srcu_read_lock(&kvm->srcu);
6306 spin_lock(&kvm->mmu_lock);
6307
6308 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6309 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
6310 while (to_zap && !list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) {
6311 /*
6312 * We use a separate list instead of just using active_mmu_pages
6313 * because the number of lpage_disallowed pages is expected to
6314 * be relatively small compared to the total.
6315 */
6316 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6317 struct kvm_mmu_page,
6318 lpage_disallowed_link);
6319 WARN_ON_ONCE(!sp->lpage_disallowed);
6320 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6321 WARN_ON_ONCE(sp->lpage_disallowed);
6322
6323 if (!--to_zap || need_resched() || spin_needbreak(&kvm->mmu_lock)) {
6324 kvm_mmu_commit_zap_page(kvm, &invalid_list);
6325 if (to_zap)
6326 cond_resched_lock(&kvm->mmu_lock);
6327 }
6328 }
6329
6330 spin_unlock(&kvm->mmu_lock);
6331 srcu_read_unlock(&kvm->srcu, rcu_idx);
6332}
6333
6334static long get_nx_lpage_recovery_timeout(u64 start_time)
6335{
6336 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6337 ? start_time + 60 * HZ - get_jiffies_64()
6338 : MAX_SCHEDULE_TIMEOUT;
6339}
6340
6341static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6342{
6343 u64 start_time;
6344 long remaining_time;
6345
6346 while (true) {
6347 start_time = get_jiffies_64();
6348 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6349
6350 set_current_state(TASK_INTERRUPTIBLE);
6351 while (!kthread_should_stop() && remaining_time > 0) {
6352 schedule_timeout(remaining_time);
6353 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6354 set_current_state(TASK_INTERRUPTIBLE);
6355 }
6356
6357 set_current_state(TASK_RUNNING);
6358
6359 if (kthread_should_stop())
6360 return 0;
6361
6362 kvm_recover_nx_lpages(kvm);
6363 }
6364}
6365
6366int kvm_mmu_post_init_vm(struct kvm *kvm)
6367{
6368 int err;
6369
6370 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6371 "kvm-nx-lpage-recovery",
6372 &kvm->arch.nx_lpage_recovery_thread);
6373 if (!err)
6374 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6375
6376 return err;
6377}
6378
6379void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6380{
6381 if (kvm->arch.nx_lpage_recovery_thread)
6382 kthread_stop(kvm->arch.nx_lpage_recovery_thread);
6383}