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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 AK |
16 | */ |
17 | ||
18 | /* | |
19 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
20 | * so the code in this file is compiled twice, once per pte size. | |
21 | */ | |
22 | ||
23 | #if PTTYPE == 64 | |
24 | #define pt_element_t u64 | |
25 | #define guest_walker guest_walker64 | |
26 | #define FNAME(name) paging##64_##name | |
27 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
28 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
29 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 30 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 31 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
32 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
33 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 34 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
52 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
53 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 54 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 55 | #define CMPXCHG cmpxchg |
37406aaa NHE |
56 | #elif PTTYPE == PTTYPE_EPT |
57 | #define pt_element_t u64 | |
58 | #define guest_walker guest_walkerEPT | |
59 | #define FNAME(name) ept_##name | |
60 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
61 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
62 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
63 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
64 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
65 | #define PT_GUEST_DIRTY_SHIFT 9 |
66 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
67 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa NHE |
68 | #define CMPXCHG cmpxchg64 |
69 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
70 | #else |
71 | #error Invalid PTTYPE value | |
72 | #endif | |
73 | ||
ae1e2d10 PB |
74 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
75 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
76 | ||
e04da980 JR |
77 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
78 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 79 | |
6aa8b732 AK |
80 | /* |
81 | * The guest_walker structure emulates the behavior of the hardware page | |
82 | * table walker. | |
83 | */ | |
84 | struct guest_walker { | |
85 | int level; | |
8cbc7069 | 86 | unsigned max_level; |
cea0f0e7 | 87 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 88 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 89 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 90 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 91 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 92 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
93 | unsigned pt_access; |
94 | unsigned pte_access; | |
815af8d4 | 95 | gfn_t gfn; |
8c28d031 | 96 | struct x86_exception fault; |
6aa8b732 AK |
97 | }; |
98 | ||
e04da980 | 99 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 100 | { |
e04da980 | 101 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
102 | } |
103 | ||
86407bcb PB |
104 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
105 | unsigned gpte) | |
0ad805a0 NHE |
106 | { |
107 | unsigned mask; | |
108 | ||
61719a8f | 109 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 110 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
111 | return; |
112 | ||
0ad805a0 NHE |
113 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
114 | ||
115 | mask = (unsigned)~ACC_WRITE_MASK; | |
116 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
117 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
118 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
119 | *access &= mask; |
120 | } | |
121 | ||
0ad805a0 NHE |
122 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
123 | { | |
37406aaa | 124 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 125 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
126 | #else |
127 | return pte & 7; | |
128 | #endif | |
0ad805a0 NHE |
129 | } |
130 | ||
b5c3c1b3 SC |
131 | static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte) |
132 | { | |
133 | #if PTTYPE != PTTYPE_EPT | |
134 | return false; | |
135 | #else | |
136 | return __is_bad_mt_xwr(rsvd_check, gpte); | |
137 | #endif | |
138 | } | |
139 | ||
140 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
141 | { | |
142 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) || | |
143 | FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte); | |
144 | } | |
145 | ||
a78484c6 | 146 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
147 | pt_element_t __user *ptep_user, unsigned index, |
148 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 149 | { |
c8cfbb55 | 150 | int npages; |
b3e4e63f MT |
151 | pt_element_t ret; |
152 | pt_element_t *table; | |
153 | struct page *page; | |
154 | ||
73b0140b | 155 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
bd53cb35 FS |
156 | if (likely(npages == 1)) { |
157 | table = kmap_atomic(page); | |
158 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
159 | kunmap_atomic(table); | |
160 | ||
161 | kvm_release_page_dirty(page); | |
162 | } else { | |
163 | struct vm_area_struct *vma; | |
164 | unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK; | |
165 | unsigned long pfn; | |
166 | unsigned long paddr; | |
167 | ||
168 | down_read(¤t->mm->mmap_sem); | |
169 | vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE); | |
170 | if (!vma || !(vma->vm_flags & VM_PFNMAP)) { | |
171 | up_read(¤t->mm->mmap_sem); | |
172 | return -EFAULT; | |
173 | } | |
174 | pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff; | |
175 | paddr = pfn << PAGE_SHIFT; | |
176 | table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB); | |
177 | if (!table) { | |
178 | up_read(¤t->mm->mmap_sem); | |
179 | return -EFAULT; | |
180 | } | |
181 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
182 | memunmap(table); | |
183 | up_read(¤t->mm->mmap_sem); | |
184 | } | |
b3e4e63f MT |
185 | |
186 | return (ret != orig_pte); | |
187 | } | |
188 | ||
0ad805a0 NHE |
189 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
190 | struct kvm_mmu_page *sp, u64 *spte, | |
191 | u64 gpte) | |
192 | { | |
0ad805a0 NHE |
193 | if (!FNAME(is_present_gpte)(gpte)) |
194 | goto no_present; | |
195 | ||
61719a8f | 196 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
197 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
198 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
199 | goto no_present; |
200 | ||
b5c3c1b3 | 201 | if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
f8052a05 SC |
202 | goto no_present; |
203 | ||
0ad805a0 NHE |
204 | return false; |
205 | ||
206 | no_present: | |
207 | drop_spte(vcpu->kvm, spte); | |
208 | return true; | |
209 | } | |
210 | ||
d95c5568 BD |
211 | /* |
212 | * For PTTYPE_EPT, a page table can be executable but not readable | |
213 | * on supported processors. Therefore, set_spte does not automatically | |
214 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
215 | * to signify readability since it isn't used in the EPT case | |
216 | */ | |
42522d08 | 217 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
218 | { |
219 | unsigned access; | |
37406aaa NHE |
220 | #if PTTYPE == PTTYPE_EPT |
221 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
222 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 223 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 224 | #else |
bb9eadf0 PB |
225 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
226 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
227 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
228 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
229 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 230 | #endif |
0ad805a0 NHE |
231 | |
232 | return access; | |
233 | } | |
234 | ||
8cbc7069 AK |
235 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
236 | struct kvm_mmu *mmu, | |
237 | struct guest_walker *walker, | |
238 | int write_fault) | |
239 | { | |
240 | unsigned level, index; | |
241 | pt_element_t pte, orig_pte; | |
242 | pt_element_t __user *ptep_user; | |
243 | gfn_t table_gfn; | |
244 | int ret; | |
245 | ||
61719a8f | 246 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 247 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
248 | return 0; |
249 | ||
8cbc7069 AK |
250 | for (level = walker->max_level; level >= walker->level; --level) { |
251 | pte = orig_pte = walker->ptes[level - 1]; | |
252 | table_gfn = walker->table_gfn[level - 1]; | |
253 | ptep_user = walker->ptep_user[level - 1]; | |
254 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 255 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 256 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 257 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 258 | } |
0ad805a0 | 259 | if (level == walker->level && write_fault && |
d8089bac | 260 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 261 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
262 | #if PTTYPE == PTTYPE_EPT |
263 | if (kvm_arch_write_log_dirty(vcpu)) | |
264 | return -EINVAL; | |
265 | #endif | |
d8089bac | 266 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
267 | } |
268 | if (pte == orig_pte) | |
269 | continue; | |
270 | ||
ba6a3541 PB |
271 | /* |
272 | * If the slot is read-only, simply do not process the accessed | |
273 | * and dirty bits. This is the correct thing to do if the slot | |
274 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
275 | * are only supported if the accessed and dirty bits are already | |
276 | * set in the ROM (so that MMIO writes are never needed). | |
277 | * | |
278 | * Note that NPT does not allow this at all and faults, since | |
279 | * it always wants nested page table entries for the guest | |
280 | * page tables to be writable. And EPT works but will simply | |
281 | * overwrite the read-only memory to set the accessed and dirty | |
282 | * bits. | |
283 | */ | |
284 | if (unlikely(!walker->pte_writable[level - 1])) | |
285 | continue; | |
286 | ||
8cbc7069 AK |
287 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
288 | if (ret) | |
289 | return ret; | |
290 | ||
54bf36aa | 291 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 292 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
293 | } |
294 | return 0; | |
295 | } | |
296 | ||
be94f6b7 HH |
297 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
298 | { | |
299 | unsigned pkeys = 0; | |
300 | #if PTTYPE == 64 | |
301 | pte_t pte = {.pte = gpte}; | |
302 | ||
303 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
304 | #endif | |
305 | return pkeys; | |
306 | } | |
307 | ||
ac79c978 | 308 | /* |
736c291c | 309 | * Fetch a guest pte for a guest virtual address, or for an L2's GPA. |
ac79c978 | 310 | */ |
1e301feb JR |
311 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
312 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
736c291c | 313 | gpa_t addr, u32 access) |
6aa8b732 | 314 | { |
8cbc7069 | 315 | int ret; |
42bf3f0a | 316 | pt_element_t pte; |
b7233635 | 317 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 318 | gfn_t table_gfn; |
0780516a PB |
319 | u64 pt_access, pte_access; |
320 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 321 | unsigned nested_access; |
42bf3f0a | 322 | gpa_t pte_gpa; |
86407bcb | 323 | bool have_ad; |
134291bf | 324 | int offset; |
0780516a | 325 | u64 walk_nx_mask = 0; |
134291bf TY |
326 | const int write_fault = access & PFERR_WRITE_MASK; |
327 | const int user_fault = access & PFERR_USER_MASK; | |
328 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
329 | u16 errcode = 0; | |
13d22b6a AK |
330 | gpa_t real_gpa; |
331 | gfn_t gfn; | |
6aa8b732 | 332 | |
6fbc2770 | 333 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 334 | retry_walk: |
1e301feb JR |
335 | walker->level = mmu->root_level; |
336 | pte = mmu->get_cr3(vcpu); | |
86407bcb | 337 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 338 | |
1b0973bd | 339 | #if PTTYPE == 64 |
0780516a | 340 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 341 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 342 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 343 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 344 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 345 | goto error; |
1b0973bd AK |
346 | --walker->level; |
347 | } | |
348 | #endif | |
8cbc7069 | 349 | walker->max_level = walker->level; |
1715d0dc | 350 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 351 | |
ae1e2d10 PB |
352 | /* |
353 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
354 | * by the MOV to CR instruction are treated as reads and do not cause the | |
355 | * processor to set the dirty flag in any EPT paging-structure entry. | |
356 | */ | |
357 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
358 | ||
0780516a | 359 | pte_access = ~0; |
13d22b6a | 360 | ++walker->level; |
ac79c978 | 361 | |
13d22b6a | 362 | do { |
6e2ca7d1 TY |
363 | gfn_t real_gfn; |
364 | unsigned long host_addr; | |
365 | ||
0780516a | 366 | pt_access = pte_access; |
13d22b6a AK |
367 | --walker->level; |
368 | ||
42bf3f0a | 369 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 370 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
371 | offset = index * sizeof(pt_element_t); |
372 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
373 | |
374 | BUG_ON(walker->level < 1); | |
42bf3f0a | 375 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 376 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 377 | |
6e2ca7d1 | 378 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 379 | nested_access, |
54987b7a | 380 | &walker->fault); |
5e352519 PB |
381 | |
382 | /* | |
383 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
384 | * instruction) triggers a nested page fault. The exit | |
385 | * qualification / exit info field will incorrectly have | |
386 | * "guest page access" as the nested page fault's cause, | |
387 | * instead of "guest page structure access". To fix this, | |
388 | * the x86_exception struct should be augmented with enough | |
389 | * information to fix the exit_qualification or exit_info_1 | |
390 | * fields. | |
391 | */ | |
134291bf | 392 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 393 | return 0; |
5e352519 | 394 | |
6e2ca7d1 TY |
395 | real_gfn = gpa_to_gfn(real_gfn); |
396 | ||
54bf36aa | 397 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 398 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
399 | if (unlikely(kvm_is_error_hva(host_addr))) |
400 | goto error; | |
6e2ca7d1 TY |
401 | |
402 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
403 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
404 | goto error; | |
8cbc7069 | 405 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 406 | |
07420171 | 407 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 408 | |
0780516a PB |
409 | /* |
410 | * Inverting the NX it lets us AND it like other | |
411 | * permission bits. | |
412 | */ | |
413 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
414 | ||
0ad805a0 | 415 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 416 | goto error; |
7993ba43 | 417 | |
b5c3c1b3 | 418 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) { |
7a98205d | 419 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 420 | goto error; |
f59c1d2d | 421 | } |
82725b20 | 422 | |
7819026e | 423 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 424 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 425 | |
be94f6b7 | 426 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
427 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
428 | ||
429 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 PX |
430 | walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask); |
431 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); | |
0780516a | 432 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 433 | if (unlikely(errcode)) |
f59c1d2d AK |
434 | goto error; |
435 | ||
13d22b6a AK |
436 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
437 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
438 | ||
439 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
440 | gfn += pse36_gfn_delta(pte); | |
441 | ||
54987b7a | 442 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
443 | if (real_gpa == UNMAPPED_GVA) |
444 | return 0; | |
445 | ||
446 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
447 | ||
8ea667f2 | 448 | if (!write_fault) |
0780516a | 449 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
450 | else |
451 | /* | |
61719a8f GN |
452 | * On a write fault, fold the dirty bit into accessed_dirty. |
453 | * For modes without A/D bits support accessed_dirty will be | |
454 | * always clear. | |
908e7d79 | 455 | */ |
d8089bac GN |
456 | accessed_dirty &= pte >> |
457 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
458 | |
459 | if (unlikely(!accessed_dirty)) { | |
460 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
461 | if (unlikely(ret < 0)) | |
462 | goto error; | |
463 | else if (ret) | |
464 | goto retry_walk; | |
465 | } | |
42bf3f0a | 466 | |
fe135d2c | 467 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 468 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
469 | return 1; |
470 | ||
f59c1d2d | 471 | error: |
134291bf | 472 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
473 | if (fetch_fault && (mmu->nx || |
474 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 475 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 476 | |
134291bf TY |
477 | walker->fault.vector = PF_VECTOR; |
478 | walker->fault.error_code_valid = true; | |
479 | walker->fault.error_code = errcode; | |
25d92081 YZ |
480 | |
481 | #if PTTYPE == PTTYPE_EPT | |
482 | /* | |
483 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
484 | * misconfiguration requires to be injected. The detection is | |
485 | * done by is_rsvd_bits_set() above. | |
486 | * | |
487 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
488 | * [2:0] - Derive from the access bits. The exit_qualification might be |
489 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
490 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
491 | * [7:8] - Derived from [7:8] of real exit_qualification | |
492 | * | |
493 | * The other bits are set to 0. | |
494 | */ | |
495 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
496 | vcpu->arch.exit_qualification &= 0x180; |
497 | if (write_fault) | |
498 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
499 | if (user_fault) | |
500 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
501 | if (fetch_fault) | |
502 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 503 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
504 | } |
505 | #endif | |
6389ee94 AK |
506 | walker->fault.address = addr; |
507 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 508 | |
8c28d031 | 509 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 510 | return 0; |
6aa8b732 AK |
511 | } |
512 | ||
1e301feb | 513 | static int FNAME(walk_addr)(struct guest_walker *walker, |
736c291c | 514 | struct kvm_vcpu *vcpu, gpa_t addr, u32 access) |
1e301feb | 515 | { |
44dd3ffa | 516 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 517 | access); |
1e301feb JR |
518 | } |
519 | ||
37406aaa | 520 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
521 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
522 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 523 | u32 access) |
6539e738 JR |
524 | { |
525 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 526 | addr, access); |
6539e738 | 527 | } |
37406aaa | 528 | #endif |
6539e738 | 529 | |
bd6360cc XG |
530 | static bool |
531 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
532 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 533 | { |
41074d07 | 534 | unsigned pte_access; |
bd6360cc | 535 | gfn_t gfn; |
ba049e93 | 536 | kvm_pfn_t pfn; |
0028425f | 537 | |
0ad805a0 | 538 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 539 | return false; |
407c61c6 | 540 | |
b8688d51 | 541 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
542 | |
543 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 544 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 545 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
546 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
547 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 548 | if (is_error_pfn(pfn)) |
bd6360cc | 549 | return false; |
0f53b5b1 | 550 | |
1403283a | 551 | /* |
bd6360cc XG |
552 | * we call mmu_set_spte() with host_writable = true because |
553 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 554 | */ |
029499b4 TY |
555 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
556 | true, true); | |
bd6360cc | 557 | |
43fdcda9 | 558 | kvm_release_pfn_clean(pfn); |
bd6360cc XG |
559 | return true; |
560 | } | |
561 | ||
562 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
563 | u64 *spte, const void *pte) | |
564 | { | |
565 | pt_element_t gpte = *(const pt_element_t *)pte; | |
566 | ||
567 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
568 | } |
569 | ||
39c8c672 AK |
570 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
571 | struct guest_walker *gw, int level) | |
572 | { | |
39c8c672 | 573 | pt_element_t curr_pte; |
189be38d XG |
574 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
575 | u64 mask; | |
576 | int r, index; | |
577 | ||
578 | if (level == PT_PAGE_TABLE_LEVEL) { | |
579 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
580 | base_gpa = pte_gpa & ~mask; | |
581 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
582 | ||
54bf36aa | 583 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
584 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
585 | curr_pte = gw->prefetch_ptes[index]; | |
586 | } else | |
54bf36aa | 587 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 588 | &curr_pte, sizeof(curr_pte)); |
189be38d | 589 | |
39c8c672 AK |
590 | return r || curr_pte != gw->ptes[level - 1]; |
591 | } | |
592 | ||
189be38d XG |
593 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
594 | u64 *sptep) | |
957ed9ef XG |
595 | { |
596 | struct kvm_mmu_page *sp; | |
189be38d | 597 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 598 | u64 *spte; |
189be38d | 599 | int i; |
957ed9ef XG |
600 | |
601 | sp = page_header(__pa(sptep)); | |
602 | ||
603 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
604 | return; | |
605 | ||
606 | if (sp->role.direct) | |
607 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
608 | ||
609 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
610 | spte = sp->spt + i; |
611 | ||
612 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
613 | if (spte == sptep) |
614 | continue; | |
615 | ||
c3707958 | 616 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
617 | continue; |
618 | ||
bd6360cc | 619 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 620 | break; |
957ed9ef XG |
621 | } |
622 | } | |
623 | ||
6aa8b732 AK |
624 | /* |
625 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
626 | * If the guest tries to write a write-protected page, we need to |
627 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 628 | */ |
736c291c | 629 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, |
e7a04c99 | 630 | struct guest_walker *gw, |
83f06fa7 | 631 | int write_fault, int max_level, |
b8e8c830 PB |
632 | kvm_pfn_t pfn, bool map_writable, bool prefault, |
633 | bool lpage_disallowed) | |
6aa8b732 | 634 | { |
5991b332 | 635 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 636 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 637 | unsigned direct_access, access = gw->pt_access; |
83f06fa7 | 638 | int top_level, hlevel, ret; |
09c4453e | 639 | gfn_t base_gfn = gw->gfn; |
abb9e0b8 | 640 | |
b36c7a7c | 641 | direct_access = gw->pte_access; |
84754cd8 | 642 | |
44dd3ffa | 643 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
644 | if (top_level == PT32E_ROOT_LEVEL) |
645 | top_level = PT32_ROOT_LEVEL; | |
646 | /* | |
647 | * Verify that the top-level gpte is still there. Since the page | |
648 | * is a root page, it is either write protected (and cannot be | |
649 | * changed from now on) or it is invalid (in which case, we don't | |
650 | * really care if it changes underneath us after this point). | |
651 | */ | |
652 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
653 | goto out_gpte_changed; | |
654 | ||
0c7a98e3 | 655 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
37f6a4e2 MT |
656 | goto out_gpte_changed; |
657 | ||
24157aaf AK |
658 | for (shadow_walk_init(&it, vcpu, addr); |
659 | shadow_walk_okay(&it) && it.level > gw->level; | |
660 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
661 | gfn_t table_gfn; |
662 | ||
a30f47cb | 663 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 664 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 665 | |
5991b332 | 666 | sp = NULL; |
24157aaf AK |
667 | if (!is_shadow_present_pte(*it.sptep)) { |
668 | table_gfn = gw->table_gfn[it.level - 2]; | |
669 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 670 | false, access); |
5991b332 | 671 | } |
0b3c9333 AK |
672 | |
673 | /* | |
674 | * Verify that the gpte in the page we've just write | |
675 | * protected is still there. | |
676 | */ | |
24157aaf | 677 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 678 | goto out_gpte_changed; |
abb9e0b8 | 679 | |
5991b332 | 680 | if (sp) |
98bba238 | 681 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 682 | } |
050e6499 | 683 | |
83f06fa7 | 684 | hlevel = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn); |
4cd071d1 | 685 | |
335e192a PB |
686 | trace_kvm_mmu_spte_requested(addr, gw->level, pfn); |
687 | ||
3fcf2d1b | 688 | for (; shadow_walk_okay(&it); shadow_walk_next(&it)) { |
a30f47cb | 689 | clear_sp_write_flooding_count(it.sptep); |
b8e8c830 PB |
690 | |
691 | /* | |
692 | * We cannot overwrite existing page tables with an NX | |
693 | * large page, as the leaf could be executable. | |
694 | */ | |
09c4453e | 695 | disallowed_hugepage_adjust(it, gw->gfn, &pfn, &hlevel); |
b8e8c830 | 696 | |
09c4453e | 697 | base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
3fcf2d1b PB |
698 | if (it.level == hlevel) |
699 | break; | |
700 | ||
24157aaf | 701 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 702 | |
24157aaf | 703 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 704 | |
3fcf2d1b PB |
705 | if (!is_shadow_present_pte(*it.sptep)) { |
706 | sp = kvm_mmu_get_page(vcpu, base_gfn, addr, | |
707 | it.level - 1, true, direct_access); | |
708 | link_shadow_page(vcpu, it.sptep, sp); | |
b8e8c830 PB |
709 | if (lpage_disallowed) |
710 | account_huge_nx_page(vcpu->kvm, sp); | |
3fcf2d1b | 711 | } |
0b3c9333 AK |
712 | } |
713 | ||
9b8ebbdb | 714 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
3fcf2d1b | 715 | it.level, base_gfn, pfn, prefault, map_writable); |
189be38d | 716 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
3fcf2d1b | 717 | ++vcpu->stat.pf_fixed; |
9b8ebbdb | 718 | return ret; |
0b3c9333 AK |
719 | |
720 | out_gpte_changed: | |
9b8ebbdb | 721 | return RET_PF_RETRY; |
6aa8b732 AK |
722 | } |
723 | ||
7751babd XG |
724 | /* |
725 | * To see whether the mapped gfn can write its page table in the current | |
726 | * mapping. | |
727 | * | |
728 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
729 | * size to map the writable gfn which is used as current page table, we should | |
730 | * force kvm to use small page size to map it because new shadow page will be | |
731 | * created when kvm establishes shadow page table that stop kvm using large | |
732 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
733 | * | |
93c05d3e XG |
734 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
735 | * currently used as its page table. | |
736 | * | |
7751babd XG |
737 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
738 | * since the PDPT is always shadowed, that means, we can not use large page | |
739 | * size to map the gfn which is used as PDPT. | |
740 | */ | |
741 | static bool | |
742 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
743 | struct guest_walker *walker, int user_fault, |
744 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
745 | { |
746 | int level; | |
747 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 748 | bool self_changed = false; |
7751babd XG |
749 | |
750 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
751 | (!is_write_protection(vcpu) && !user_fault))) | |
752 | return false; | |
753 | ||
93c05d3e XG |
754 | for (level = walker->level; level <= walker->max_level; level++) { |
755 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
756 | ||
757 | self_changed |= !(gfn & mask); | |
758 | *write_fault_to_shadow_pgtable |= !gfn; | |
759 | } | |
7751babd | 760 | |
93c05d3e | 761 | return self_changed; |
7751babd XG |
762 | } |
763 | ||
6aa8b732 AK |
764 | /* |
765 | * Page fault handler. There are several causes for a page fault: | |
766 | * - there is no shadow pte for the guest pte | |
767 | * - write access through a shadow pte marked read only so that we can set | |
768 | * the dirty bit | |
769 | * - write access to a shadow pte marked read only so we can update the page | |
770 | * dirty bitmap, when userspace requests it | |
771 | * - mmio access; in this case we will never install a present shadow pte | |
772 | * - normal guest page fault due to the guest pte marked not present, not | |
773 | * writable, or not executable | |
774 | * | |
e2dec939 AK |
775 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
776 | * a negative value on error. | |
6aa8b732 | 777 | */ |
736c291c | 778 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code, |
78b2c54a | 779 | bool prefault) |
6aa8b732 AK |
780 | { |
781 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
782 | int user_fault = error_code & PFERR_USER_MASK; |
783 | struct guest_walker walker; | |
e2dec939 | 784 | int r; |
ba049e93 | 785 | kvm_pfn_t pfn; |
e930bffe | 786 | unsigned long mmu_seq; |
93c05d3e | 787 | bool map_writable, is_self_change_mapping; |
b8e8c830 PB |
788 | bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) && |
789 | is_nx_huge_page_enabled(); | |
39ca1ecb | 790 | int max_level; |
6aa8b732 | 791 | |
b8688d51 | 792 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 793 | |
e2dec939 AK |
794 | r = mmu_topup_memory_caches(vcpu); |
795 | if (r) | |
796 | return r; | |
714b93da | 797 | |
e9ee956e TY |
798 | /* |
799 | * If PFEC.RSVD is set, this is a shadow page fault. | |
800 | * The bit needs to be cleared before walking guest page tables. | |
801 | */ | |
802 | error_code &= ~PFERR_RSVD_MASK; | |
803 | ||
6aa8b732 | 804 | /* |
a8b876b1 | 805 | * Look up the guest pte for the faulting address. |
6aa8b732 | 806 | */ |
33770780 | 807 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
808 | |
809 | /* | |
810 | * The page is not mapped by the guest. Let the guest handle it. | |
811 | */ | |
7993ba43 | 812 | if (!r) { |
b8688d51 | 813 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 814 | if (!prefault) |
fb67e14f | 815 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 816 | |
9b8ebbdb | 817 | return RET_PF_RETRY; |
6aa8b732 AK |
818 | } |
819 | ||
e5691a81 XG |
820 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
821 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 822 | return RET_PF_EMULATE; |
e5691a81 | 823 | } |
3d0c27ad | 824 | |
93c05d3e XG |
825 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
826 | ||
827 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
828 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
829 | ||
cbe1e6f0 | 830 | if (lpage_disallowed || is_self_change_mapping) |
39ca1ecb | 831 | max_level = PT_PAGE_TABLE_LEVEL; |
cbe1e6f0 SC |
832 | else |
833 | max_level = walker.level; | |
834 | ||
e930bffe | 835 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 836 | smp_rmb(); |
af585b92 | 837 | |
78b2c54a | 838 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 839 | &map_writable)) |
9b8ebbdb | 840 | return RET_PF_RETRY; |
d7824fff | 841 | |
9034e6e8 | 842 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
843 | return r; |
844 | ||
c2288505 XG |
845 | /* |
846 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
847 | * we will cache the incorrect access into mmio spte. | |
848 | */ | |
849 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
850 | !is_write_protection(vcpu) && !user_fault && | |
851 | !is_noslot_pfn(pfn)) { | |
852 | walker.pte_access |= ACC_WRITE_MASK; | |
853 | walker.pte_access &= ~ACC_USER_MASK; | |
854 | ||
855 | /* | |
856 | * If we converted a user page to a kernel page, | |
857 | * so that the kernel can write to it when cr0.wp=0, | |
858 | * then we should prevent the kernel from executing it | |
859 | * if SMEP is enabled. | |
860 | */ | |
861 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
862 | walker.pte_access &= ~ACC_EXEC_MASK; | |
863 | } | |
864 | ||
43fdcda9 | 865 | r = RET_PF_RETRY; |
aaee2c94 | 866 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 867 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 868 | goto out_unlock; |
bc32ce21 | 869 | |
0375f7fa | 870 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
871 | if (make_mmu_pages_available(vcpu) < 0) |
872 | goto out_unlock; | |
83f06fa7 SC |
873 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, max_level, pfn, |
874 | map_writable, prefault, lpage_disallowed); | |
0375f7fa | 875 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
e930bffe AA |
876 | |
877 | out_unlock: | |
878 | spin_unlock(&vcpu->kvm->mmu_lock); | |
879 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 880 | return r; |
6aa8b732 AK |
881 | } |
882 | ||
505aef8f XG |
883 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
884 | { | |
885 | int offset = 0; | |
886 | ||
f71fa31f | 887 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
888 | |
889 | if (PTTYPE == 32) | |
890 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
891 | ||
892 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
893 | } | |
894 | ||
7eb77e9f | 895 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 896 | { |
a461930b | 897 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 898 | struct kvm_mmu_page *sp; |
a461930b AK |
899 | int level; |
900 | u64 *sptep; | |
901 | ||
bebb106a XG |
902 | vcpu_clear_mmio_info(vcpu, gva); |
903 | ||
f57f2ef5 XG |
904 | /* |
905 | * No need to check return value here, rmap_can_add() can | |
906 | * help us to skip pte prefetch later. | |
907 | */ | |
908 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 909 | |
7eb77e9f | 910 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
911 | WARN_ON(1); |
912 | return; | |
913 | } | |
914 | ||
f57f2ef5 | 915 | spin_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 916 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
917 | level = iterator.level; |
918 | sptep = iterator.sptep; | |
ad218f85 | 919 | |
f78978aa | 920 | sp = page_header(__pa(sptep)); |
884a0ff0 | 921 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
922 | pt_element_t gpte; |
923 | gpa_t pte_gpa; | |
924 | ||
f78978aa XG |
925 | if (!sp->unsync) |
926 | break; | |
927 | ||
505aef8f | 928 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 929 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 930 | |
505aef8f | 931 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
c3134ce2 LT |
932 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
933 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
934 | |
935 | if (!rmap_can_add(vcpu)) | |
936 | break; | |
937 | ||
54bf36aa PB |
938 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
939 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
940 | break; |
941 | ||
942 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 943 | } |
a7052897 | 944 | |
f78978aa | 945 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
946 | break; |
947 | } | |
ad218f85 | 948 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
949 | } |
950 | ||
736c291c SC |
951 | /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */ |
952 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access, | |
ab9ae313 | 953 | struct x86_exception *exception) |
6aa8b732 AK |
954 | { |
955 | struct guest_walker walker; | |
e119d117 AK |
956 | gpa_t gpa = UNMAPPED_GVA; |
957 | int r; | |
6aa8b732 | 958 | |
736c291c | 959 | r = FNAME(walk_addr)(&walker, vcpu, addr, access); |
6aa8b732 | 960 | |
e119d117 | 961 | if (r) { |
1755fbcc | 962 | gpa = gfn_to_gpa(walker.gfn); |
736c291c | 963 | gpa |= addr & ~PAGE_MASK; |
8c28d031 AK |
964 | } else if (exception) |
965 | *exception = walker.fault; | |
6aa8b732 AK |
966 | |
967 | return gpa; | |
968 | } | |
969 | ||
37406aaa | 970 | #if PTTYPE != PTTYPE_EPT |
736c291c SC |
971 | /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */ |
972 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr, | |
ab9ae313 AK |
973 | u32 access, |
974 | struct x86_exception *exception) | |
6539e738 JR |
975 | { |
976 | struct guest_walker walker; | |
977 | gpa_t gpa = UNMAPPED_GVA; | |
978 | int r; | |
979 | ||
736c291c SC |
980 | #ifndef CONFIG_X86_64 |
981 | /* A 64-bit GVA should be impossible on 32-bit KVM. */ | |
982 | WARN_ON_ONCE(vaddr >> 32); | |
983 | #endif | |
984 | ||
33770780 | 985 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
986 | |
987 | if (r) { | |
988 | gpa = gfn_to_gpa(walker.gfn); | |
989 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
990 | } else if (exception) |
991 | *exception = walker.fault; | |
6539e738 JR |
992 | |
993 | return gpa; | |
994 | } | |
37406aaa | 995 | #endif |
6539e738 | 996 | |
e8bc217a MT |
997 | /* |
998 | * Using the cached information from sp->gfns is safe because: | |
999 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
1000 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
1001 | * |
1002 | * Note: | |
1003 | * We should flush all tlbs if spte is dropped even though guest is | |
1004 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
1005 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
1006 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
1007 | * freed pages. | |
a086f6a1 | 1008 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 1009 | */ |
a4a8e6f7 | 1010 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 1011 | { |
505aef8f | 1012 | int i, nr_present = 0; |
9bdbba13 | 1013 | bool host_writable; |
51fb60d8 | 1014 | gpa_t first_pte_gpa; |
5ce4786f | 1015 | int set_spte_ret = 0; |
e8bc217a | 1016 | |
2032a93d LJ |
1017 | /* direct kvm_mmu_page can not be unsync. */ |
1018 | BUG_ON(sp->role.direct); | |
1019 | ||
505aef8f | 1020 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 1021 | |
e8bc217a MT |
1022 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
1023 | unsigned pte_access; | |
1024 | pt_element_t gpte; | |
1025 | gpa_t pte_gpa; | |
f55c3f41 | 1026 | gfn_t gfn; |
e8bc217a | 1027 | |
ce88decf | 1028 | if (!sp->spt[i]) |
e8bc217a MT |
1029 | continue; |
1030 | ||
51fb60d8 | 1031 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 1032 | |
54bf36aa PB |
1033 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
1034 | sizeof(pt_element_t))) | |
1f50f1b3 | 1035 | return 0; |
e8bc217a | 1036 | |
0ad805a0 | 1037 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
1038 | /* |
1039 | * Update spte before increasing tlbs_dirty to make | |
1040 | * sure no tlb flush is lost after spte is zapped; see | |
1041 | * the comments in kvm_flush_remote_tlbs(). | |
1042 | */ | |
1043 | smp_wmb(); | |
a086f6a1 | 1044 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1045 | continue; |
1046 | } | |
1047 | ||
ce88decf XG |
1048 | gfn = gpte_to_gfn(gpte); |
1049 | pte_access = sp->role.access; | |
42522d08 | 1050 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1051 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1052 | |
54bf36aa | 1053 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1054 | &nr_present)) |
ce88decf XG |
1055 | continue; |
1056 | ||
407c61c6 | 1057 | if (gfn != sp->gfns[i]) { |
c3707958 | 1058 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1059 | /* |
1060 | * The same as above where we are doing | |
1061 | * prefetch_invalid_gpte(). | |
1062 | */ | |
1063 | smp_wmb(); | |
a086f6a1 | 1064 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1065 | continue; |
1066 | } | |
1067 | ||
1068 | nr_present++; | |
ce88decf | 1069 | |
f8e453b0 XG |
1070 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1071 | ||
5ce4786f JS |
1072 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
1073 | pte_access, PT_PAGE_TABLE_LEVEL, | |
1074 | gfn, spte_to_pfn(sp->spt[i]), | |
1075 | true, false, host_writable); | |
e8bc217a MT |
1076 | } |
1077 | ||
5ce4786f JS |
1078 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1079 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1080 | ||
1f50f1b3 | 1081 | return nr_present; |
e8bc217a MT |
1082 | } |
1083 | ||
6aa8b732 AK |
1084 | #undef pt_element_t |
1085 | #undef guest_walker | |
1086 | #undef FNAME | |
1087 | #undef PT_BASE_ADDR_MASK | |
1088 | #undef PT_INDEX | |
e04da980 JR |
1089 | #undef PT_LVL_ADDR_MASK |
1090 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1091 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1092 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1093 | #undef gpte_to_gfn |
e04da980 | 1094 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1095 | #undef CMPXCHG |
d8089bac GN |
1096 | #undef PT_GUEST_ACCESSED_MASK |
1097 | #undef PT_GUEST_DIRTY_MASK | |
1098 | #undef PT_GUEST_DIRTY_SHIFT | |
1099 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1100 | #undef PT_HAVE_ACCESSED_DIRTY |