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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 AK |
16 | */ |
17 | ||
18 | /* | |
19 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
20 | * so the code in this file is compiled twice, once per pte size. | |
21 | */ | |
22 | ||
23 | #if PTTYPE == 64 | |
24 | #define pt_element_t u64 | |
25 | #define guest_walker guest_walker64 | |
26 | #define FNAME(name) paging##64_##name | |
27 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
28 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
29 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 30 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 31 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
32 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
33 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 34 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 | 35 | #ifdef CONFIG_X86_64 |
f6ab0107 | 36 | #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
52 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
53 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 54 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 55 | #define CMPXCHG cmpxchg |
37406aaa NHE |
56 | #elif PTTYPE == PTTYPE_EPT |
57 | #define pt_element_t u64 | |
58 | #define guest_walker guest_walkerEPT | |
59 | #define FNAME(name) ept_##name | |
60 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
61 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
62 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
63 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
64 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
65 | #define PT_GUEST_DIRTY_SHIFT 9 |
66 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
67 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa | 68 | #define CMPXCHG cmpxchg64 |
bb1fcc70 | 69 | #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL |
6aa8b732 AK |
70 | #else |
71 | #error Invalid PTTYPE value | |
72 | #endif | |
73 | ||
ae1e2d10 PB |
74 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
75 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
76 | ||
e04da980 | 77 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
3bae0459 | 78 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K) |
5fb07ddb | 79 | |
6aa8b732 AK |
80 | /* |
81 | * The guest_walker structure emulates the behavior of the hardware page | |
82 | * table walker. | |
83 | */ | |
84 | struct guest_walker { | |
85 | int level; | |
8cbc7069 | 86 | unsigned max_level; |
cea0f0e7 | 87 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 88 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 89 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 90 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 91 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 92 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
93 | unsigned pt_access; |
94 | unsigned pte_access; | |
815af8d4 | 95 | gfn_t gfn; |
8c28d031 | 96 | struct x86_exception fault; |
6aa8b732 AK |
97 | }; |
98 | ||
e04da980 | 99 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 100 | { |
e04da980 | 101 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
102 | } |
103 | ||
86407bcb PB |
104 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
105 | unsigned gpte) | |
0ad805a0 NHE |
106 | { |
107 | unsigned mask; | |
108 | ||
61719a8f | 109 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 110 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
111 | return; |
112 | ||
0ad805a0 NHE |
113 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
114 | ||
115 | mask = (unsigned)~ACC_WRITE_MASK; | |
116 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
117 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
118 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
119 | *access &= mask; |
120 | } | |
121 | ||
0ad805a0 NHE |
122 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
123 | { | |
37406aaa | 124 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 125 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
126 | #else |
127 | return pte & 7; | |
128 | #endif | |
0ad805a0 NHE |
129 | } |
130 | ||
b5c3c1b3 SC |
131 | static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte) |
132 | { | |
133 | #if PTTYPE != PTTYPE_EPT | |
134 | return false; | |
135 | #else | |
136 | return __is_bad_mt_xwr(rsvd_check, gpte); | |
137 | #endif | |
138 | } | |
139 | ||
140 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
141 | { | |
142 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) || | |
143 | FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte); | |
144 | } | |
145 | ||
a78484c6 | 146 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
147 | pt_element_t __user *ptep_user, unsigned index, |
148 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 149 | { |
c8cfbb55 | 150 | int npages; |
b3e4e63f MT |
151 | pt_element_t ret; |
152 | pt_element_t *table; | |
153 | struct page *page; | |
154 | ||
73b0140b | 155 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
bd53cb35 FS |
156 | if (likely(npages == 1)) { |
157 | table = kmap_atomic(page); | |
158 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
159 | kunmap_atomic(table); | |
160 | ||
161 | kvm_release_page_dirty(page); | |
162 | } else { | |
163 | struct vm_area_struct *vma; | |
164 | unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK; | |
165 | unsigned long pfn; | |
166 | unsigned long paddr; | |
167 | ||
89154dd5 | 168 | mmap_read_lock(current->mm); |
bd53cb35 FS |
169 | vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE); |
170 | if (!vma || !(vma->vm_flags & VM_PFNMAP)) { | |
89154dd5 | 171 | mmap_read_unlock(current->mm); |
bd53cb35 FS |
172 | return -EFAULT; |
173 | } | |
174 | pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff; | |
175 | paddr = pfn << PAGE_SHIFT; | |
176 | table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB); | |
177 | if (!table) { | |
89154dd5 | 178 | mmap_read_unlock(current->mm); |
bd53cb35 FS |
179 | return -EFAULT; |
180 | } | |
181 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
182 | memunmap(table); | |
89154dd5 | 183 | mmap_read_unlock(current->mm); |
bd53cb35 | 184 | } |
b3e4e63f MT |
185 | |
186 | return (ret != orig_pte); | |
187 | } | |
188 | ||
0ad805a0 NHE |
189 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
190 | struct kvm_mmu_page *sp, u64 *spte, | |
191 | u64 gpte) | |
192 | { | |
0ad805a0 NHE |
193 | if (!FNAME(is_present_gpte)(gpte)) |
194 | goto no_present; | |
195 | ||
61719a8f | 196 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
197 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
198 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
199 | goto no_present; |
200 | ||
3bae0459 | 201 | if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K)) |
f8052a05 SC |
202 | goto no_present; |
203 | ||
0ad805a0 NHE |
204 | return false; |
205 | ||
206 | no_present: | |
207 | drop_spte(vcpu->kvm, spte); | |
208 | return true; | |
209 | } | |
210 | ||
d95c5568 BD |
211 | /* |
212 | * For PTTYPE_EPT, a page table can be executable but not readable | |
213 | * on supported processors. Therefore, set_spte does not automatically | |
214 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
215 | * to signify readability since it isn't used in the EPT case | |
216 | */ | |
42522d08 | 217 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
218 | { |
219 | unsigned access; | |
37406aaa NHE |
220 | #if PTTYPE == PTTYPE_EPT |
221 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
222 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 223 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 224 | #else |
bb9eadf0 PB |
225 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
226 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
227 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
228 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
229 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 230 | #endif |
0ad805a0 NHE |
231 | |
232 | return access; | |
233 | } | |
234 | ||
8cbc7069 AK |
235 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
236 | struct kvm_mmu *mmu, | |
237 | struct guest_walker *walker, | |
238 | int write_fault) | |
239 | { | |
240 | unsigned level, index; | |
241 | pt_element_t pte, orig_pte; | |
242 | pt_element_t __user *ptep_user; | |
243 | gfn_t table_gfn; | |
244 | int ret; | |
245 | ||
61719a8f | 246 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 247 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
248 | return 0; |
249 | ||
8cbc7069 AK |
250 | for (level = walker->max_level; level >= walker->level; --level) { |
251 | pte = orig_pte = walker->ptes[level - 1]; | |
252 | table_gfn = walker->table_gfn[level - 1]; | |
253 | ptep_user = walker->ptep_user[level - 1]; | |
254 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 255 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 256 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 257 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 258 | } |
0ad805a0 | 259 | if (level == walker->level && write_fault && |
d8089bac | 260 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 261 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
262 | #if PTTYPE == PTTYPE_EPT |
263 | if (kvm_arch_write_log_dirty(vcpu)) | |
264 | return -EINVAL; | |
265 | #endif | |
d8089bac | 266 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
267 | } |
268 | if (pte == orig_pte) | |
269 | continue; | |
270 | ||
ba6a3541 PB |
271 | /* |
272 | * If the slot is read-only, simply do not process the accessed | |
273 | * and dirty bits. This is the correct thing to do if the slot | |
274 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
275 | * are only supported if the accessed and dirty bits are already | |
276 | * set in the ROM (so that MMIO writes are never needed). | |
277 | * | |
278 | * Note that NPT does not allow this at all and faults, since | |
279 | * it always wants nested page table entries for the guest | |
280 | * page tables to be writable. And EPT works but will simply | |
281 | * overwrite the read-only memory to set the accessed and dirty | |
282 | * bits. | |
283 | */ | |
284 | if (unlikely(!walker->pte_writable[level - 1])) | |
285 | continue; | |
286 | ||
8cbc7069 AK |
287 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
288 | if (ret) | |
289 | return ret; | |
290 | ||
54bf36aa | 291 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 292 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
293 | } |
294 | return 0; | |
295 | } | |
296 | ||
be94f6b7 HH |
297 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
298 | { | |
299 | unsigned pkeys = 0; | |
300 | #if PTTYPE == 64 | |
301 | pte_t pte = {.pte = gpte}; | |
302 | ||
303 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
304 | #endif | |
305 | return pkeys; | |
306 | } | |
307 | ||
ac79c978 | 308 | /* |
736c291c | 309 | * Fetch a guest pte for a guest virtual address, or for an L2's GPA. |
ac79c978 | 310 | */ |
1e301feb JR |
311 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
312 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
736c291c | 313 | gpa_t addr, u32 access) |
6aa8b732 | 314 | { |
8cbc7069 | 315 | int ret; |
42bf3f0a | 316 | pt_element_t pte; |
b7233635 | 317 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 318 | gfn_t table_gfn; |
0780516a PB |
319 | u64 pt_access, pte_access; |
320 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 321 | unsigned nested_access; |
42bf3f0a | 322 | gpa_t pte_gpa; |
86407bcb | 323 | bool have_ad; |
134291bf | 324 | int offset; |
0780516a | 325 | u64 walk_nx_mask = 0; |
134291bf TY |
326 | const int write_fault = access & PFERR_WRITE_MASK; |
327 | const int user_fault = access & PFERR_USER_MASK; | |
328 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
329 | u16 errcode = 0; | |
13d22b6a AK |
330 | gpa_t real_gpa; |
331 | gfn_t gfn; | |
6aa8b732 | 332 | |
6fbc2770 | 333 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 334 | retry_walk: |
1e301feb | 335 | walker->level = mmu->root_level; |
d8dd54e0 | 336 | pte = mmu->get_guest_pgd(vcpu); |
86407bcb | 337 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 338 | |
1b0973bd | 339 | #if PTTYPE == 64 |
0780516a | 340 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 341 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 342 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 343 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 344 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 345 | goto error; |
1b0973bd AK |
346 | --walker->level; |
347 | } | |
348 | #endif | |
8cbc7069 | 349 | walker->max_level = walker->level; |
1715d0dc | 350 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 351 | |
ae1e2d10 PB |
352 | /* |
353 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
354 | * by the MOV to CR instruction are treated as reads and do not cause the | |
355 | * processor to set the dirty flag in any EPT paging-structure entry. | |
356 | */ | |
357 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
358 | ||
0780516a | 359 | pte_access = ~0; |
13d22b6a | 360 | ++walker->level; |
ac79c978 | 361 | |
13d22b6a | 362 | do { |
6e2ca7d1 TY |
363 | unsigned long host_addr; |
364 | ||
0780516a | 365 | pt_access = pte_access; |
13d22b6a AK |
366 | --walker->level; |
367 | ||
42bf3f0a | 368 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 369 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
370 | offset = index * sizeof(pt_element_t); |
371 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
372 | |
373 | BUG_ON(walker->level < 1); | |
42bf3f0a | 374 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 375 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 376 | |
312d16c7 | 377 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 378 | nested_access, |
54987b7a | 379 | &walker->fault); |
5e352519 PB |
380 | |
381 | /* | |
382 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
383 | * instruction) triggers a nested page fault. The exit | |
384 | * qualification / exit info field will incorrectly have | |
385 | * "guest page access" as the nested page fault's cause, | |
386 | * instead of "guest page structure access". To fix this, | |
387 | * the x86_exception struct should be augmented with enough | |
388 | * information to fix the exit_qualification or exit_info_1 | |
389 | * fields. | |
390 | */ | |
312d16c7 | 391 | if (unlikely(real_gpa == UNMAPPED_GVA)) |
54987b7a | 392 | return 0; |
5e352519 | 393 | |
312d16c7 | 394 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa), |
ba6a3541 | 395 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
396 | if (unlikely(kvm_is_error_hva(host_addr))) |
397 | goto error; | |
6e2ca7d1 TY |
398 | |
399 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
a4814443 | 400 | if (unlikely(__get_user(pte, ptep_user))) |
134291bf | 401 | goto error; |
8cbc7069 | 402 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 403 | |
07420171 | 404 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 405 | |
0780516a PB |
406 | /* |
407 | * Inverting the NX it lets us AND it like other | |
408 | * permission bits. | |
409 | */ | |
410 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
411 | ||
0ad805a0 | 412 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 413 | goto error; |
7993ba43 | 414 | |
b5c3c1b3 | 415 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) { |
7a98205d | 416 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 417 | goto error; |
f59c1d2d | 418 | } |
82725b20 | 419 | |
7819026e | 420 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 421 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 422 | |
be94f6b7 | 423 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
424 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
425 | ||
426 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 PX |
427 | walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask); |
428 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); | |
0780516a | 429 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 430 | if (unlikely(errcode)) |
f59c1d2d AK |
431 | goto error; |
432 | ||
13d22b6a AK |
433 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
434 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
435 | ||
3bae0459 | 436 | if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36()) |
13d22b6a AK |
437 | gfn += pse36_gfn_delta(pte); |
438 | ||
54987b7a | 439 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
440 | if (real_gpa == UNMAPPED_GVA) |
441 | return 0; | |
442 | ||
443 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
444 | ||
8ea667f2 | 445 | if (!write_fault) |
0780516a | 446 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
447 | else |
448 | /* | |
61719a8f GN |
449 | * On a write fault, fold the dirty bit into accessed_dirty. |
450 | * For modes without A/D bits support accessed_dirty will be | |
451 | * always clear. | |
908e7d79 | 452 | */ |
d8089bac GN |
453 | accessed_dirty &= pte >> |
454 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
455 | |
456 | if (unlikely(!accessed_dirty)) { | |
457 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
458 | if (unlikely(ret < 0)) | |
459 | goto error; | |
460 | else if (ret) | |
461 | goto retry_walk; | |
462 | } | |
42bf3f0a | 463 | |
fe135d2c | 464 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 465 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
466 | return 1; |
467 | ||
f59c1d2d | 468 | error: |
134291bf | 469 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
470 | if (fetch_fault && (mmu->nx || |
471 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 472 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 473 | |
134291bf TY |
474 | walker->fault.vector = PF_VECTOR; |
475 | walker->fault.error_code_valid = true; | |
476 | walker->fault.error_code = errcode; | |
25d92081 YZ |
477 | |
478 | #if PTTYPE == PTTYPE_EPT | |
479 | /* | |
480 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
481 | * misconfiguration requires to be injected. The detection is | |
482 | * done by is_rsvd_bits_set() above. | |
483 | * | |
484 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
485 | * [2:0] - Derive from the access bits. The exit_qualification might be |
486 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
487 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
488 | * [7:8] - Derived from [7:8] of real exit_qualification | |
489 | * | |
490 | * The other bits are set to 0. | |
491 | */ | |
492 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
493 | vcpu->arch.exit_qualification &= 0x180; |
494 | if (write_fault) | |
495 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
496 | if (user_fault) | |
497 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
498 | if (fetch_fault) | |
499 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 500 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
501 | } |
502 | #endif | |
6389ee94 AK |
503 | walker->fault.address = addr; |
504 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 505 | |
8c28d031 | 506 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 507 | return 0; |
6aa8b732 AK |
508 | } |
509 | ||
1e301feb | 510 | static int FNAME(walk_addr)(struct guest_walker *walker, |
736c291c | 511 | struct kvm_vcpu *vcpu, gpa_t addr, u32 access) |
1e301feb | 512 | { |
44dd3ffa | 513 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 514 | access); |
1e301feb JR |
515 | } |
516 | ||
37406aaa | 517 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
518 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
519 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 520 | u32 access) |
6539e738 JR |
521 | { |
522 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 523 | addr, access); |
6539e738 | 524 | } |
37406aaa | 525 | #endif |
6539e738 | 526 | |
bd6360cc XG |
527 | static bool |
528 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
529 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 530 | { |
41074d07 | 531 | unsigned pte_access; |
bd6360cc | 532 | gfn_t gfn; |
ba049e93 | 533 | kvm_pfn_t pfn; |
0028425f | 534 | |
0ad805a0 | 535 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 536 | return false; |
407c61c6 | 537 | |
b8688d51 | 538 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
539 | |
540 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 541 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 542 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
543 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
544 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 545 | if (is_error_pfn(pfn)) |
bd6360cc | 546 | return false; |
0f53b5b1 | 547 | |
1403283a | 548 | /* |
bd6360cc XG |
549 | * we call mmu_set_spte() with host_writable = true because |
550 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 551 | */ |
3bae0459 | 552 | mmu_set_spte(vcpu, spte, pte_access, 0, PG_LEVEL_4K, gfn, pfn, |
029499b4 | 553 | true, true); |
bd6360cc | 554 | |
43fdcda9 | 555 | kvm_release_pfn_clean(pfn); |
bd6360cc XG |
556 | return true; |
557 | } | |
558 | ||
559 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
560 | u64 *spte, const void *pte) | |
561 | { | |
562 | pt_element_t gpte = *(const pt_element_t *)pte; | |
563 | ||
564 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
565 | } |
566 | ||
39c8c672 AK |
567 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
568 | struct guest_walker *gw, int level) | |
569 | { | |
39c8c672 | 570 | pt_element_t curr_pte; |
189be38d XG |
571 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
572 | u64 mask; | |
573 | int r, index; | |
574 | ||
3bae0459 | 575 | if (level == PG_LEVEL_4K) { |
189be38d XG |
576 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; |
577 | base_gpa = pte_gpa & ~mask; | |
578 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
579 | ||
54bf36aa | 580 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
581 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
582 | curr_pte = gw->prefetch_ptes[index]; | |
583 | } else | |
54bf36aa | 584 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 585 | &curr_pte, sizeof(curr_pte)); |
189be38d | 586 | |
39c8c672 AK |
587 | return r || curr_pte != gw->ptes[level - 1]; |
588 | } | |
589 | ||
189be38d XG |
590 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
591 | u64 *sptep) | |
957ed9ef XG |
592 | { |
593 | struct kvm_mmu_page *sp; | |
189be38d | 594 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 595 | u64 *spte; |
189be38d | 596 | int i; |
957ed9ef XG |
597 | |
598 | sp = page_header(__pa(sptep)); | |
599 | ||
3bae0459 | 600 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
601 | return; |
602 | ||
603 | if (sp->role.direct) | |
604 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
605 | ||
606 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
607 | spte = sp->spt + i; |
608 | ||
609 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
610 | if (spte == sptep) |
611 | continue; | |
612 | ||
c3707958 | 613 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
614 | continue; |
615 | ||
bd6360cc | 616 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 617 | break; |
957ed9ef XG |
618 | } |
619 | } | |
620 | ||
6aa8b732 AK |
621 | /* |
622 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
623 | * If the guest tries to write a write-protected page, we need to |
624 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 625 | */ |
736c291c | 626 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, |
e7a04c99 | 627 | struct guest_walker *gw, |
83f06fa7 | 628 | int write_fault, int max_level, |
b8e8c830 PB |
629 | kvm_pfn_t pfn, bool map_writable, bool prefault, |
630 | bool lpage_disallowed) | |
6aa8b732 | 631 | { |
5991b332 | 632 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 633 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 634 | unsigned direct_access, access = gw->pt_access; |
83f06fa7 | 635 | int top_level, hlevel, ret; |
09c4453e | 636 | gfn_t base_gfn = gw->gfn; |
abb9e0b8 | 637 | |
b36c7a7c | 638 | direct_access = gw->pte_access; |
84754cd8 | 639 | |
44dd3ffa | 640 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
641 | if (top_level == PT32E_ROOT_LEVEL) |
642 | top_level = PT32_ROOT_LEVEL; | |
643 | /* | |
644 | * Verify that the top-level gpte is still there. Since the page | |
645 | * is a root page, it is either write protected (and cannot be | |
646 | * changed from now on) or it is invalid (in which case, we don't | |
647 | * really care if it changes underneath us after this point). | |
648 | */ | |
649 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
650 | goto out_gpte_changed; | |
651 | ||
0c7a98e3 | 652 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
37f6a4e2 MT |
653 | goto out_gpte_changed; |
654 | ||
24157aaf AK |
655 | for (shadow_walk_init(&it, vcpu, addr); |
656 | shadow_walk_okay(&it) && it.level > gw->level; | |
657 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
658 | gfn_t table_gfn; |
659 | ||
a30f47cb | 660 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 661 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 662 | |
5991b332 | 663 | sp = NULL; |
24157aaf AK |
664 | if (!is_shadow_present_pte(*it.sptep)) { |
665 | table_gfn = gw->table_gfn[it.level - 2]; | |
666 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 667 | false, access); |
5991b332 | 668 | } |
0b3c9333 AK |
669 | |
670 | /* | |
671 | * Verify that the gpte in the page we've just write | |
672 | * protected is still there. | |
673 | */ | |
24157aaf | 674 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 675 | goto out_gpte_changed; |
abb9e0b8 | 676 | |
5991b332 | 677 | if (sp) |
98bba238 | 678 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 679 | } |
050e6499 | 680 | |
83f06fa7 | 681 | hlevel = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn); |
4cd071d1 | 682 | |
335e192a PB |
683 | trace_kvm_mmu_spte_requested(addr, gw->level, pfn); |
684 | ||
3fcf2d1b | 685 | for (; shadow_walk_okay(&it); shadow_walk_next(&it)) { |
a30f47cb | 686 | clear_sp_write_flooding_count(it.sptep); |
b8e8c830 PB |
687 | |
688 | /* | |
689 | * We cannot overwrite existing page tables with an NX | |
690 | * large page, as the leaf could be executable. | |
691 | */ | |
09c4453e | 692 | disallowed_hugepage_adjust(it, gw->gfn, &pfn, &hlevel); |
b8e8c830 | 693 | |
09c4453e | 694 | base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
3fcf2d1b PB |
695 | if (it.level == hlevel) |
696 | break; | |
697 | ||
24157aaf | 698 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 699 | |
24157aaf | 700 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 701 | |
3fcf2d1b PB |
702 | if (!is_shadow_present_pte(*it.sptep)) { |
703 | sp = kvm_mmu_get_page(vcpu, base_gfn, addr, | |
704 | it.level - 1, true, direct_access); | |
705 | link_shadow_page(vcpu, it.sptep, sp); | |
b8e8c830 PB |
706 | if (lpage_disallowed) |
707 | account_huge_nx_page(vcpu->kvm, sp); | |
3fcf2d1b | 708 | } |
0b3c9333 AK |
709 | } |
710 | ||
9b8ebbdb | 711 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
3fcf2d1b | 712 | it.level, base_gfn, pfn, prefault, map_writable); |
189be38d | 713 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
3fcf2d1b | 714 | ++vcpu->stat.pf_fixed; |
9b8ebbdb | 715 | return ret; |
0b3c9333 AK |
716 | |
717 | out_gpte_changed: | |
9b8ebbdb | 718 | return RET_PF_RETRY; |
6aa8b732 AK |
719 | } |
720 | ||
7751babd XG |
721 | /* |
722 | * To see whether the mapped gfn can write its page table in the current | |
723 | * mapping. | |
724 | * | |
725 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
726 | * size to map the writable gfn which is used as current page table, we should | |
727 | * force kvm to use small page size to map it because new shadow page will be | |
728 | * created when kvm establishes shadow page table that stop kvm using large | |
729 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
730 | * | |
93c05d3e XG |
731 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
732 | * currently used as its page table. | |
733 | * | |
7751babd XG |
734 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
735 | * since the PDPT is always shadowed, that means, we can not use large page | |
736 | * size to map the gfn which is used as PDPT. | |
737 | */ | |
738 | static bool | |
739 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
740 | struct guest_walker *walker, int user_fault, |
741 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
742 | { |
743 | int level; | |
744 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 745 | bool self_changed = false; |
7751babd XG |
746 | |
747 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
748 | (!is_write_protection(vcpu) && !user_fault))) | |
749 | return false; | |
750 | ||
93c05d3e XG |
751 | for (level = walker->level; level <= walker->max_level; level++) { |
752 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
753 | ||
754 | self_changed |= !(gfn & mask); | |
755 | *write_fault_to_shadow_pgtable |= !gfn; | |
756 | } | |
7751babd | 757 | |
93c05d3e | 758 | return self_changed; |
7751babd XG |
759 | } |
760 | ||
6aa8b732 AK |
761 | /* |
762 | * Page fault handler. There are several causes for a page fault: | |
763 | * - there is no shadow pte for the guest pte | |
764 | * - write access through a shadow pte marked read only so that we can set | |
765 | * the dirty bit | |
766 | * - write access to a shadow pte marked read only so we can update the page | |
767 | * dirty bitmap, when userspace requests it | |
768 | * - mmio access; in this case we will never install a present shadow pte | |
769 | * - normal guest page fault due to the guest pte marked not present, not | |
770 | * writable, or not executable | |
771 | * | |
e2dec939 AK |
772 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
773 | * a negative value on error. | |
6aa8b732 | 774 | */ |
736c291c | 775 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code, |
78b2c54a | 776 | bool prefault) |
6aa8b732 AK |
777 | { |
778 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
779 | int user_fault = error_code & PFERR_USER_MASK; |
780 | struct guest_walker walker; | |
e2dec939 | 781 | int r; |
ba049e93 | 782 | kvm_pfn_t pfn; |
e930bffe | 783 | unsigned long mmu_seq; |
93c05d3e | 784 | bool map_writable, is_self_change_mapping; |
b8e8c830 PB |
785 | bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) && |
786 | is_nx_huge_page_enabled(); | |
39ca1ecb | 787 | int max_level; |
6aa8b732 | 788 | |
b8688d51 | 789 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 790 | |
e2dec939 AK |
791 | r = mmu_topup_memory_caches(vcpu); |
792 | if (r) | |
793 | return r; | |
714b93da | 794 | |
e9ee956e TY |
795 | /* |
796 | * If PFEC.RSVD is set, this is a shadow page fault. | |
797 | * The bit needs to be cleared before walking guest page tables. | |
798 | */ | |
799 | error_code &= ~PFERR_RSVD_MASK; | |
800 | ||
6aa8b732 | 801 | /* |
a8b876b1 | 802 | * Look up the guest pte for the faulting address. |
6aa8b732 | 803 | */ |
33770780 | 804 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
805 | |
806 | /* | |
807 | * The page is not mapped by the guest. Let the guest handle it. | |
808 | */ | |
7993ba43 | 809 | if (!r) { |
b8688d51 | 810 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 811 | if (!prefault) |
0cd665bd | 812 | kvm_inject_emulated_page_fault(vcpu, &walker.fault); |
a30f47cb | 813 | |
9b8ebbdb | 814 | return RET_PF_RETRY; |
6aa8b732 AK |
815 | } |
816 | ||
e5691a81 XG |
817 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
818 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 819 | return RET_PF_EMULATE; |
e5691a81 | 820 | } |
3d0c27ad | 821 | |
93c05d3e XG |
822 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
823 | ||
824 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
825 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
826 | ||
cbe1e6f0 | 827 | if (lpage_disallowed || is_self_change_mapping) |
3bae0459 | 828 | max_level = PG_LEVEL_4K; |
cbe1e6f0 SC |
829 | else |
830 | max_level = walker.level; | |
831 | ||
e930bffe | 832 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 833 | smp_rmb(); |
af585b92 | 834 | |
78b2c54a | 835 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 836 | &map_writable)) |
9b8ebbdb | 837 | return RET_PF_RETRY; |
d7824fff | 838 | |
9034e6e8 | 839 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
840 | return r; |
841 | ||
c2288505 XG |
842 | /* |
843 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
844 | * we will cache the incorrect access into mmio spte. | |
845 | */ | |
846 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
847 | !is_write_protection(vcpu) && !user_fault && | |
848 | !is_noslot_pfn(pfn)) { | |
849 | walker.pte_access |= ACC_WRITE_MASK; | |
850 | walker.pte_access &= ~ACC_USER_MASK; | |
851 | ||
852 | /* | |
853 | * If we converted a user page to a kernel page, | |
854 | * so that the kernel can write to it when cr0.wp=0, | |
855 | * then we should prevent the kernel from executing it | |
856 | * if SMEP is enabled. | |
857 | */ | |
858 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
859 | walker.pte_access &= ~ACC_EXEC_MASK; | |
860 | } | |
861 | ||
43fdcda9 | 862 | r = RET_PF_RETRY; |
aaee2c94 | 863 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 864 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 865 | goto out_unlock; |
bc32ce21 | 866 | |
0375f7fa | 867 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
868 | if (make_mmu_pages_available(vcpu) < 0) |
869 | goto out_unlock; | |
83f06fa7 SC |
870 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, max_level, pfn, |
871 | map_writable, prefault, lpage_disallowed); | |
0375f7fa | 872 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
e930bffe AA |
873 | |
874 | out_unlock: | |
875 | spin_unlock(&vcpu->kvm->mmu_lock); | |
876 | kvm_release_pfn_clean(pfn); | |
43fdcda9 | 877 | return r; |
6aa8b732 AK |
878 | } |
879 | ||
505aef8f XG |
880 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
881 | { | |
882 | int offset = 0; | |
883 | ||
3bae0459 | 884 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
505aef8f XG |
885 | |
886 | if (PTTYPE == 32) | |
887 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
888 | ||
889 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
890 | } | |
891 | ||
7eb77e9f | 892 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 893 | { |
a461930b | 894 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 895 | struct kvm_mmu_page *sp; |
a461930b AK |
896 | int level; |
897 | u64 *sptep; | |
898 | ||
bebb106a XG |
899 | vcpu_clear_mmio_info(vcpu, gva); |
900 | ||
f57f2ef5 XG |
901 | /* |
902 | * No need to check return value here, rmap_can_add() can | |
903 | * help us to skip pte prefetch later. | |
904 | */ | |
905 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 906 | |
7eb77e9f | 907 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
908 | WARN_ON(1); |
909 | return; | |
910 | } | |
911 | ||
f57f2ef5 | 912 | spin_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 913 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
914 | level = iterator.level; |
915 | sptep = iterator.sptep; | |
ad218f85 | 916 | |
f78978aa | 917 | sp = page_header(__pa(sptep)); |
884a0ff0 | 918 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
919 | pt_element_t gpte; |
920 | gpa_t pte_gpa; | |
921 | ||
f78978aa XG |
922 | if (!sp->unsync) |
923 | break; | |
924 | ||
505aef8f | 925 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 926 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 927 | |
505aef8f | 928 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
c3134ce2 LT |
929 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
930 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
931 | |
932 | if (!rmap_can_add(vcpu)) | |
933 | break; | |
934 | ||
54bf36aa PB |
935 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
936 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
937 | break; |
938 | ||
939 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 940 | } |
a7052897 | 941 | |
f78978aa | 942 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
943 | break; |
944 | } | |
ad218f85 | 945 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
946 | } |
947 | ||
736c291c SC |
948 | /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */ |
949 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access, | |
ab9ae313 | 950 | struct x86_exception *exception) |
6aa8b732 AK |
951 | { |
952 | struct guest_walker walker; | |
e119d117 AK |
953 | gpa_t gpa = UNMAPPED_GVA; |
954 | int r; | |
6aa8b732 | 955 | |
736c291c | 956 | r = FNAME(walk_addr)(&walker, vcpu, addr, access); |
6aa8b732 | 957 | |
e119d117 | 958 | if (r) { |
1755fbcc | 959 | gpa = gfn_to_gpa(walker.gfn); |
736c291c | 960 | gpa |= addr & ~PAGE_MASK; |
8c28d031 AK |
961 | } else if (exception) |
962 | *exception = walker.fault; | |
6aa8b732 AK |
963 | |
964 | return gpa; | |
965 | } | |
966 | ||
37406aaa | 967 | #if PTTYPE != PTTYPE_EPT |
736c291c SC |
968 | /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */ |
969 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr, | |
ab9ae313 AK |
970 | u32 access, |
971 | struct x86_exception *exception) | |
6539e738 JR |
972 | { |
973 | struct guest_walker walker; | |
974 | gpa_t gpa = UNMAPPED_GVA; | |
975 | int r; | |
976 | ||
736c291c SC |
977 | #ifndef CONFIG_X86_64 |
978 | /* A 64-bit GVA should be impossible on 32-bit KVM. */ | |
979 | WARN_ON_ONCE(vaddr >> 32); | |
980 | #endif | |
981 | ||
33770780 | 982 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
983 | |
984 | if (r) { | |
985 | gpa = gfn_to_gpa(walker.gfn); | |
986 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
987 | } else if (exception) |
988 | *exception = walker.fault; | |
6539e738 JR |
989 | |
990 | return gpa; | |
991 | } | |
37406aaa | 992 | #endif |
6539e738 | 993 | |
e8bc217a MT |
994 | /* |
995 | * Using the cached information from sp->gfns is safe because: | |
996 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
997 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
998 | * |
999 | * Note: | |
1000 | * We should flush all tlbs if spte is dropped even though guest is | |
1001 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
1002 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
1003 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
1004 | * freed pages. | |
a086f6a1 | 1005 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 1006 | */ |
a4a8e6f7 | 1007 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 1008 | { |
505aef8f | 1009 | int i, nr_present = 0; |
9bdbba13 | 1010 | bool host_writable; |
51fb60d8 | 1011 | gpa_t first_pte_gpa; |
5ce4786f | 1012 | int set_spte_ret = 0; |
e8bc217a | 1013 | |
2032a93d LJ |
1014 | /* direct kvm_mmu_page can not be unsync. */ |
1015 | BUG_ON(sp->role.direct); | |
1016 | ||
505aef8f | 1017 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 1018 | |
e8bc217a MT |
1019 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
1020 | unsigned pte_access; | |
1021 | pt_element_t gpte; | |
1022 | gpa_t pte_gpa; | |
f55c3f41 | 1023 | gfn_t gfn; |
e8bc217a | 1024 | |
ce88decf | 1025 | if (!sp->spt[i]) |
e8bc217a MT |
1026 | continue; |
1027 | ||
51fb60d8 | 1028 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 1029 | |
54bf36aa PB |
1030 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
1031 | sizeof(pt_element_t))) | |
1f50f1b3 | 1032 | return 0; |
e8bc217a | 1033 | |
0ad805a0 | 1034 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
1035 | /* |
1036 | * Update spte before increasing tlbs_dirty to make | |
1037 | * sure no tlb flush is lost after spte is zapped; see | |
1038 | * the comments in kvm_flush_remote_tlbs(). | |
1039 | */ | |
1040 | smp_wmb(); | |
a086f6a1 | 1041 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1042 | continue; |
1043 | } | |
1044 | ||
ce88decf XG |
1045 | gfn = gpte_to_gfn(gpte); |
1046 | pte_access = sp->role.access; | |
42522d08 | 1047 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1048 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1049 | |
54bf36aa | 1050 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1051 | &nr_present)) |
ce88decf XG |
1052 | continue; |
1053 | ||
407c61c6 | 1054 | if (gfn != sp->gfns[i]) { |
c3707958 | 1055 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1056 | /* |
1057 | * The same as above where we are doing | |
1058 | * prefetch_invalid_gpte(). | |
1059 | */ | |
1060 | smp_wmb(); | |
a086f6a1 | 1061 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1062 | continue; |
1063 | } | |
1064 | ||
1065 | nr_present++; | |
ce88decf | 1066 | |
f8e453b0 XG |
1067 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1068 | ||
5ce4786f | 1069 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
3bae0459 | 1070 | pte_access, PG_LEVEL_4K, |
5ce4786f JS |
1071 | gfn, spte_to_pfn(sp->spt[i]), |
1072 | true, false, host_writable); | |
e8bc217a MT |
1073 | } |
1074 | ||
5ce4786f JS |
1075 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1076 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1077 | ||
1f50f1b3 | 1078 | return nr_present; |
e8bc217a MT |
1079 | } |
1080 | ||
6aa8b732 AK |
1081 | #undef pt_element_t |
1082 | #undef guest_walker | |
1083 | #undef FNAME | |
1084 | #undef PT_BASE_ADDR_MASK | |
1085 | #undef PT_INDEX | |
e04da980 JR |
1086 | #undef PT_LVL_ADDR_MASK |
1087 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1088 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1089 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1090 | #undef gpte_to_gfn |
e04da980 | 1091 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1092 | #undef CMPXCHG |
d8089bac GN |
1093 | #undef PT_GUEST_ACCESSED_MASK |
1094 | #undef PT_GUEST_DIRTY_MASK | |
1095 | #undef PT_GUEST_DIRTY_SHIFT | |
1096 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1097 | #undef PT_HAVE_ACCESSED_DIRTY |