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20c8ccb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 AK |
16 | */ |
17 | ||
18 | /* | |
19 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
20 | * so the code in this file is compiled twice, once per pte size. | |
21 | */ | |
22 | ||
23 | #if PTTYPE == 64 | |
24 | #define pt_element_t u64 | |
25 | #define guest_walker guest_walker64 | |
26 | #define FNAME(name) paging##64_##name | |
27 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
28 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
29 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 30 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 31 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
32 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
33 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 34 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 | 35 | #ifdef CONFIG_X86_64 |
f6ab0107 | 36 | #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
52 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
53 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 54 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 55 | #define CMPXCHG cmpxchg |
37406aaa NHE |
56 | #elif PTTYPE == PTTYPE_EPT |
57 | #define pt_element_t u64 | |
58 | #define guest_walker guest_walkerEPT | |
59 | #define FNAME(name) ept_##name | |
60 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
61 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
62 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
63 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
64 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
65 | #define PT_GUEST_DIRTY_SHIFT 9 |
66 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
67 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa | 68 | #define CMPXCHG cmpxchg64 |
bb1fcc70 | 69 | #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL |
6aa8b732 AK |
70 | #else |
71 | #error Invalid PTTYPE value | |
72 | #endif | |
73 | ||
ae1e2d10 PB |
74 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
75 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
76 | ||
e04da980 | 77 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
3bae0459 | 78 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K) |
5fb07ddb | 79 | |
6aa8b732 AK |
80 | /* |
81 | * The guest_walker structure emulates the behavior of the hardware page | |
82 | * table walker. | |
83 | */ | |
84 | struct guest_walker { | |
85 | int level; | |
8cbc7069 | 86 | unsigned max_level; |
cea0f0e7 | 87 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 88 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 89 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 90 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 91 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 92 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
b1bd5cba LJ |
93 | unsigned int pt_access[PT_MAX_FULL_LEVELS]; |
94 | unsigned int pte_access; | |
815af8d4 | 95 | gfn_t gfn; |
8c28d031 | 96 | struct x86_exception fault; |
6aa8b732 AK |
97 | }; |
98 | ||
e04da980 | 99 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 100 | { |
e04da980 | 101 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
102 | } |
103 | ||
86407bcb PB |
104 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
105 | unsigned gpte) | |
0ad805a0 NHE |
106 | { |
107 | unsigned mask; | |
108 | ||
61719a8f | 109 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 110 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
111 | return; |
112 | ||
0ad805a0 NHE |
113 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
114 | ||
115 | mask = (unsigned)~ACC_WRITE_MASK; | |
116 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
117 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
118 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
119 | *access &= mask; |
120 | } | |
121 | ||
0ad805a0 NHE |
122 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
123 | { | |
37406aaa | 124 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 125 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
126 | #else |
127 | return pte & 7; | |
128 | #endif | |
0ad805a0 NHE |
129 | } |
130 | ||
b5c3c1b3 SC |
131 | static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte) |
132 | { | |
133 | #if PTTYPE != PTTYPE_EPT | |
134 | return false; | |
135 | #else | |
136 | return __is_bad_mt_xwr(rsvd_check, gpte); | |
137 | #endif | |
138 | } | |
139 | ||
140 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
141 | { | |
142 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) || | |
143 | FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte); | |
144 | } | |
145 | ||
a78484c6 | 146 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
147 | pt_element_t __user *ptep_user, unsigned index, |
148 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 149 | { |
c8cfbb55 | 150 | int npages; |
b3e4e63f MT |
151 | pt_element_t ret; |
152 | pt_element_t *table; | |
153 | struct page *page; | |
154 | ||
73b0140b | 155 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
bd53cb35 FS |
156 | if (likely(npages == 1)) { |
157 | table = kmap_atomic(page); | |
158 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
159 | kunmap_atomic(table); | |
160 | ||
161 | kvm_release_page_dirty(page); | |
162 | } else { | |
163 | struct vm_area_struct *vma; | |
164 | unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK; | |
165 | unsigned long pfn; | |
166 | unsigned long paddr; | |
167 | ||
89154dd5 | 168 | mmap_read_lock(current->mm); |
bd53cb35 FS |
169 | vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE); |
170 | if (!vma || !(vma->vm_flags & VM_PFNMAP)) { | |
89154dd5 | 171 | mmap_read_unlock(current->mm); |
bd53cb35 FS |
172 | return -EFAULT; |
173 | } | |
174 | pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff; | |
175 | paddr = pfn << PAGE_SHIFT; | |
176 | table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB); | |
177 | if (!table) { | |
89154dd5 | 178 | mmap_read_unlock(current->mm); |
bd53cb35 FS |
179 | return -EFAULT; |
180 | } | |
181 | ret = CMPXCHG(&table[index], orig_pte, new_pte); | |
182 | memunmap(table); | |
89154dd5 | 183 | mmap_read_unlock(current->mm); |
bd53cb35 | 184 | } |
b3e4e63f MT |
185 | |
186 | return (ret != orig_pte); | |
187 | } | |
188 | ||
0ad805a0 NHE |
189 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
190 | struct kvm_mmu_page *sp, u64 *spte, | |
191 | u64 gpte) | |
192 | { | |
0ad805a0 NHE |
193 | if (!FNAME(is_present_gpte)(gpte)) |
194 | goto no_present; | |
195 | ||
61719a8f | 196 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
197 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
198 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
199 | goto no_present; |
200 | ||
3bae0459 | 201 | if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K)) |
f8052a05 SC |
202 | goto no_present; |
203 | ||
0ad805a0 NHE |
204 | return false; |
205 | ||
206 | no_present: | |
207 | drop_spte(vcpu->kvm, spte); | |
208 | return true; | |
209 | } | |
210 | ||
d95c5568 BD |
211 | /* |
212 | * For PTTYPE_EPT, a page table can be executable but not readable | |
213 | * on supported processors. Therefore, set_spte does not automatically | |
214 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
215 | * to signify readability since it isn't used in the EPT case | |
216 | */ | |
42522d08 | 217 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
218 | { |
219 | unsigned access; | |
37406aaa NHE |
220 | #if PTTYPE == PTTYPE_EPT |
221 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
222 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 223 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 224 | #else |
bb9eadf0 PB |
225 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
226 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
227 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
228 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
229 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 230 | #endif |
0ad805a0 NHE |
231 | |
232 | return access; | |
233 | } | |
234 | ||
8cbc7069 AK |
235 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
236 | struct kvm_mmu *mmu, | |
237 | struct guest_walker *walker, | |
2dbebf7a | 238 | gpa_t addr, int write_fault) |
8cbc7069 AK |
239 | { |
240 | unsigned level, index; | |
241 | pt_element_t pte, orig_pte; | |
242 | pt_element_t __user *ptep_user; | |
243 | gfn_t table_gfn; | |
244 | int ret; | |
245 | ||
61719a8f | 246 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 247 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
248 | return 0; |
249 | ||
8cbc7069 AK |
250 | for (level = walker->max_level; level >= walker->level; --level) { |
251 | pte = orig_pte = walker->ptes[level - 1]; | |
252 | table_gfn = walker->table_gfn[level - 1]; | |
253 | ptep_user = walker->ptep_user[level - 1]; | |
254 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 255 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 256 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 257 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 258 | } |
0ad805a0 | 259 | if (level == walker->level && write_fault && |
d8089bac | 260 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 261 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e | 262 | #if PTTYPE == PTTYPE_EPT |
02f5fb2e | 263 | if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr)) |
bab4165e BD |
264 | return -EINVAL; |
265 | #endif | |
d8089bac | 266 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
267 | } |
268 | if (pte == orig_pte) | |
269 | continue; | |
270 | ||
ba6a3541 PB |
271 | /* |
272 | * If the slot is read-only, simply do not process the accessed | |
273 | * and dirty bits. This is the correct thing to do if the slot | |
274 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
275 | * are only supported if the accessed and dirty bits are already | |
276 | * set in the ROM (so that MMIO writes are never needed). | |
277 | * | |
278 | * Note that NPT does not allow this at all and faults, since | |
279 | * it always wants nested page table entries for the guest | |
280 | * page tables to be writable. And EPT works but will simply | |
281 | * overwrite the read-only memory to set the accessed and dirty | |
282 | * bits. | |
283 | */ | |
284 | if (unlikely(!walker->pte_writable[level - 1])) | |
285 | continue; | |
286 | ||
8cbc7069 AK |
287 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
288 | if (ret) | |
289 | return ret; | |
290 | ||
54bf36aa | 291 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 292 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
293 | } |
294 | return 0; | |
295 | } | |
296 | ||
be94f6b7 HH |
297 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
298 | { | |
299 | unsigned pkeys = 0; | |
300 | #if PTTYPE == 64 | |
301 | pte_t pte = {.pte = gpte}; | |
302 | ||
303 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
304 | #endif | |
305 | return pkeys; | |
306 | } | |
307 | ||
7cd138db SC |
308 | static inline bool FNAME(is_last_gpte)(struct kvm_mmu *mmu, |
309 | unsigned int level, unsigned int gpte) | |
310 | { | |
311 | /* | |
312 | * For EPT and PAE paging (both variants), bit 7 is either reserved at | |
313 | * all level or indicates a huge page (ignoring CR3/EPTP). In either | |
314 | * case, bit 7 being set terminates the walk. | |
315 | */ | |
316 | #if PTTYPE == 32 | |
317 | /* | |
318 | * 32-bit paging requires special handling because bit 7 is ignored if | |
319 | * CR4.PSE=0, not reserved. Clear bit 7 in the gpte if the level is | |
320 | * greater than the last level for which bit 7 is the PAGE_SIZE bit. | |
321 | * | |
322 | * The RHS has bit 7 set iff level < (2 + PSE). If it is clear, bit 7 | |
323 | * is not reserved and does not indicate a large page at this level, | |
324 | * so clear PT_PAGE_SIZE_MASK in gpte if that is the case. | |
325 | */ | |
326 | gpte &= level - (PT32_ROOT_LEVEL + mmu->mmu_role.ext.cr4_pse); | |
327 | #endif | |
328 | /* | |
329 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set | |
330 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
331 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
332 | */ | |
333 | gpte |= level - PG_LEVEL_4K - 1; | |
334 | ||
335 | return gpte & PT_PAGE_SIZE_MASK; | |
336 | } | |
ac79c978 | 337 | /* |
736c291c | 338 | * Fetch a guest pte for a guest virtual address, or for an L2's GPA. |
ac79c978 | 339 | */ |
1e301feb JR |
340 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
341 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
736c291c | 342 | gpa_t addr, u32 access) |
6aa8b732 | 343 | { |
8cbc7069 | 344 | int ret; |
42bf3f0a | 345 | pt_element_t pte; |
3f649ab7 | 346 | pt_element_t __user *ptep_user; |
cea0f0e7 | 347 | gfn_t table_gfn; |
0780516a PB |
348 | u64 pt_access, pte_access; |
349 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 350 | unsigned nested_access; |
42bf3f0a | 351 | gpa_t pte_gpa; |
86407bcb | 352 | bool have_ad; |
134291bf | 353 | int offset; |
0780516a | 354 | u64 walk_nx_mask = 0; |
134291bf TY |
355 | const int write_fault = access & PFERR_WRITE_MASK; |
356 | const int user_fault = access & PFERR_USER_MASK; | |
357 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
358 | u16 errcode = 0; | |
13d22b6a AK |
359 | gpa_t real_gpa; |
360 | gfn_t gfn; | |
6aa8b732 | 361 | |
6fbc2770 | 362 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 363 | retry_walk: |
1e301feb | 364 | walker->level = mmu->root_level; |
d8dd54e0 | 365 | pte = mmu->get_guest_pgd(vcpu); |
86407bcb | 366 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 367 | |
1b0973bd | 368 | #if PTTYPE == 64 |
0780516a | 369 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 370 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 371 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 372 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 373 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 374 | goto error; |
1b0973bd AK |
375 | --walker->level; |
376 | } | |
377 | #endif | |
8cbc7069 | 378 | walker->max_level = walker->level; |
1715d0dc | 379 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 380 | |
ae1e2d10 PB |
381 | /* |
382 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
383 | * by the MOV to CR instruction are treated as reads and do not cause the | |
384 | * processor to set the dirty flag in any EPT paging-structure entry. | |
385 | */ | |
386 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
387 | ||
0780516a | 388 | pte_access = ~0; |
13d22b6a | 389 | ++walker->level; |
ac79c978 | 390 | |
13d22b6a | 391 | do { |
6e2ca7d1 TY |
392 | unsigned long host_addr; |
393 | ||
0780516a | 394 | pt_access = pte_access; |
13d22b6a AK |
395 | --walker->level; |
396 | ||
42bf3f0a | 397 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 398 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
399 | offset = index * sizeof(pt_element_t); |
400 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
401 | |
402 | BUG_ON(walker->level < 1); | |
42bf3f0a | 403 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 404 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 405 | |
312d16c7 | 406 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 407 | nested_access, |
54987b7a | 408 | &walker->fault); |
5e352519 PB |
409 | |
410 | /* | |
411 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
412 | * instruction) triggers a nested page fault. The exit | |
413 | * qualification / exit info field will incorrectly have | |
414 | * "guest page access" as the nested page fault's cause, | |
415 | * instead of "guest page structure access". To fix this, | |
416 | * the x86_exception struct should be augmented with enough | |
417 | * information to fix the exit_qualification or exit_info_1 | |
418 | * fields. | |
419 | */ | |
312d16c7 | 420 | if (unlikely(real_gpa == UNMAPPED_GVA)) |
54987b7a | 421 | return 0; |
5e352519 | 422 | |
312d16c7 | 423 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa), |
ba6a3541 | 424 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
425 | if (unlikely(kvm_is_error_hva(host_addr))) |
426 | goto error; | |
6e2ca7d1 TY |
427 | |
428 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
a4814443 | 429 | if (unlikely(__get_user(pte, ptep_user))) |
134291bf | 430 | goto error; |
8cbc7069 | 431 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 432 | |
07420171 | 433 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 434 | |
0780516a PB |
435 | /* |
436 | * Inverting the NX it lets us AND it like other | |
437 | * permission bits. | |
438 | */ | |
439 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
440 | ||
0ad805a0 | 441 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 442 | goto error; |
7993ba43 | 443 | |
b5c3c1b3 | 444 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) { |
7a98205d | 445 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 446 | goto error; |
f59c1d2d | 447 | } |
82725b20 | 448 | |
7819026e | 449 | walker->ptes[walker->level - 1] = pte; |
b1bd5cba LJ |
450 | |
451 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
452 | walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask); | |
7cd138db | 453 | } while (!FNAME(is_last_gpte)(mmu, walker->level, pte)); |
42bf3f0a | 454 | |
be94f6b7 | 455 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
456 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
457 | ||
458 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 | 459 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); |
0780516a | 460 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 461 | if (unlikely(errcode)) |
f59c1d2d AK |
462 | goto error; |
463 | ||
13d22b6a AK |
464 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
465 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
466 | ||
3bae0459 | 467 | if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36()) |
13d22b6a AK |
468 | gfn += pse36_gfn_delta(pte); |
469 | ||
54987b7a | 470 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
471 | if (real_gpa == UNMAPPED_GVA) |
472 | return 0; | |
473 | ||
474 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
475 | ||
8ea667f2 | 476 | if (!write_fault) |
0780516a | 477 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
478 | else |
479 | /* | |
61719a8f GN |
480 | * On a write fault, fold the dirty bit into accessed_dirty. |
481 | * For modes without A/D bits support accessed_dirty will be | |
482 | * always clear. | |
908e7d79 | 483 | */ |
d8089bac GN |
484 | accessed_dirty &= pte >> |
485 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
486 | |
487 | if (unlikely(!accessed_dirty)) { | |
2dbebf7a SC |
488 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, |
489 | addr, write_fault); | |
b514c30f AK |
490 | if (unlikely(ret < 0)) |
491 | goto error; | |
492 | else if (ret) | |
493 | goto retry_walk; | |
494 | } | |
42bf3f0a | 495 | |
fe135d2c | 496 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
b1bd5cba LJ |
497 | __func__, (u64)pte, walker->pte_access, |
498 | walker->pt_access[walker->level - 1]); | |
7993ba43 AK |
499 | return 1; |
500 | ||
f59c1d2d | 501 | error: |
134291bf | 502 | errcode |= write_fault | user_fault; |
cd628f0f | 503 | if (fetch_fault && (is_efer_nx(mmu) || is_cr4_smep(mmu))) |
134291bf | 504 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 505 | |
134291bf TY |
506 | walker->fault.vector = PF_VECTOR; |
507 | walker->fault.error_code_valid = true; | |
508 | walker->fault.error_code = errcode; | |
25d92081 YZ |
509 | |
510 | #if PTTYPE == PTTYPE_EPT | |
511 | /* | |
512 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
513 | * misconfiguration requires to be injected. The detection is | |
514 | * done by is_rsvd_bits_set() above. | |
515 | * | |
516 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
517 | * [2:0] - Derive from the access bits. The exit_qualification might be |
518 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
519 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
520 | * [7:8] - Derived from [7:8] of real exit_qualification | |
521 | * | |
522 | * The other bits are set to 0. | |
523 | */ | |
524 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
525 | vcpu->arch.exit_qualification &= 0x180; |
526 | if (write_fault) | |
527 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
528 | if (user_fault) | |
529 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
530 | if (fetch_fault) | |
531 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 532 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
533 | } |
534 | #endif | |
6389ee94 AK |
535 | walker->fault.address = addr; |
536 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
422e2e17 | 537 | walker->fault.async_page_fault = false; |
8df25a32 | 538 | |
8c28d031 | 539 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 540 | return 0; |
6aa8b732 AK |
541 | } |
542 | ||
1e301feb | 543 | static int FNAME(walk_addr)(struct guest_walker *walker, |
736c291c | 544 | struct kvm_vcpu *vcpu, gpa_t addr, u32 access) |
1e301feb | 545 | { |
44dd3ffa | 546 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 547 | access); |
1e301feb JR |
548 | } |
549 | ||
37406aaa | 550 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
551 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
552 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 553 | u32 access) |
6539e738 JR |
554 | { |
555 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 556 | addr, access); |
6539e738 | 557 | } |
37406aaa | 558 | #endif |
6539e738 | 559 | |
bd6360cc XG |
560 | static bool |
561 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
562 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 563 | { |
41074d07 | 564 | unsigned pte_access; |
bd6360cc | 565 | gfn_t gfn; |
ba049e93 | 566 | kvm_pfn_t pfn; |
0028425f | 567 | |
0ad805a0 | 568 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 569 | return false; |
407c61c6 | 570 | |
b8688d51 | 571 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
572 | |
573 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 574 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 575 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
576 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
577 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 578 | if (is_error_pfn(pfn)) |
bd6360cc | 579 | return false; |
0f53b5b1 | 580 | |
1403283a | 581 | /* |
bd6360cc XG |
582 | * we call mmu_set_spte() with host_writable = true because |
583 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 584 | */ |
e88b8093 | 585 | mmu_set_spte(vcpu, spte, pte_access, false, PG_LEVEL_4K, gfn, pfn, |
029499b4 | 586 | true, true); |
bd6360cc | 587 | |
43fdcda9 | 588 | kvm_release_pfn_clean(pfn); |
bd6360cc XG |
589 | return true; |
590 | } | |
591 | ||
592 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
593 | u64 *spte, const void *pte) | |
594 | { | |
595 | pt_element_t gpte = *(const pt_element_t *)pte; | |
596 | ||
597 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
598 | } |
599 | ||
39c8c672 AK |
600 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
601 | struct guest_walker *gw, int level) | |
602 | { | |
39c8c672 | 603 | pt_element_t curr_pte; |
189be38d XG |
604 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
605 | u64 mask; | |
606 | int r, index; | |
607 | ||
3bae0459 | 608 | if (level == PG_LEVEL_4K) { |
189be38d XG |
609 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; |
610 | base_gpa = pte_gpa & ~mask; | |
611 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
612 | ||
54bf36aa | 613 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
614 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
615 | curr_pte = gw->prefetch_ptes[index]; | |
616 | } else | |
54bf36aa | 617 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 618 | &curr_pte, sizeof(curr_pte)); |
189be38d | 619 | |
39c8c672 AK |
620 | return r || curr_pte != gw->ptes[level - 1]; |
621 | } | |
622 | ||
189be38d XG |
623 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
624 | u64 *sptep) | |
957ed9ef XG |
625 | { |
626 | struct kvm_mmu_page *sp; | |
189be38d | 627 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 628 | u64 *spte; |
189be38d | 629 | int i; |
957ed9ef | 630 | |
57354682 | 631 | sp = sptep_to_sp(sptep); |
957ed9ef | 632 | |
3bae0459 | 633 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
634 | return; |
635 | ||
4a42d848 DS |
636 | /* |
637 | * If addresses are being invalidated, skip prefetching to avoid | |
638 | * accidentally prefetching those addresses. | |
639 | */ | |
640 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
641 | return; | |
642 | ||
957ed9ef XG |
643 | if (sp->role.direct) |
644 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
645 | ||
646 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
647 | spte = sp->spt + i; |
648 | ||
649 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
650 | if (spte == sptep) |
651 | continue; | |
652 | ||
c3707958 | 653 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
654 | continue; |
655 | ||
bd6360cc | 656 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 657 | break; |
957ed9ef XG |
658 | } |
659 | } | |
660 | ||
6aa8b732 AK |
661 | /* |
662 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
663 | * If the guest tries to write a write-protected page, we need to |
664 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 665 | */ |
736c291c | 666 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, |
6c2fd34f SC |
667 | struct guest_walker *gw, u32 error_code, |
668 | int max_level, kvm_pfn_t pfn, bool map_writable, | |
669 | bool prefault) | |
6aa8b732 | 670 | { |
6c2fd34f | 671 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
e88b8093 | 672 | bool write_fault = error_code & PFERR_WRITE_MASK; |
6c2fd34f SC |
673 | bool exec = error_code & PFERR_FETCH_MASK; |
674 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
5991b332 | 675 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 676 | struct kvm_shadow_walk_iterator it; |
b1bd5cba | 677 | unsigned int direct_access, access; |
1d4a7372 | 678 | int top_level, level, req_level, ret; |
09c4453e | 679 | gfn_t base_gfn = gw->gfn; |
abb9e0b8 | 680 | |
b36c7a7c | 681 | direct_access = gw->pte_access; |
84754cd8 | 682 | |
44dd3ffa | 683 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
684 | if (top_level == PT32E_ROOT_LEVEL) |
685 | top_level = PT32_ROOT_LEVEL; | |
686 | /* | |
687 | * Verify that the top-level gpte is still there. Since the page | |
688 | * is a root page, it is either write protected (and cannot be | |
689 | * changed from now on) or it is invalid (in which case, we don't | |
690 | * really care if it changes underneath us after this point). | |
691 | */ | |
692 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
693 | goto out_gpte_changed; | |
694 | ||
0c7a98e3 | 695 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
37f6a4e2 MT |
696 | goto out_gpte_changed; |
697 | ||
24157aaf AK |
698 | for (shadow_walk_init(&it, vcpu, addr); |
699 | shadow_walk_okay(&it) && it.level > gw->level; | |
700 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
701 | gfn_t table_gfn; |
702 | ||
a30f47cb | 703 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 704 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 705 | |
5991b332 | 706 | sp = NULL; |
24157aaf AK |
707 | if (!is_shadow_present_pte(*it.sptep)) { |
708 | table_gfn = gw->table_gfn[it.level - 2]; | |
b1bd5cba | 709 | access = gw->pt_access[it.level - 2]; |
24157aaf | 710 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, |
bb11c6c9 | 711 | false, access); |
5991b332 | 712 | } |
0b3c9333 AK |
713 | |
714 | /* | |
715 | * Verify that the gpte in the page we've just write | |
716 | * protected is still there. | |
717 | */ | |
24157aaf | 718 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 719 | goto out_gpte_changed; |
abb9e0b8 | 720 | |
5991b332 | 721 | if (sp) |
98bba238 | 722 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 723 | } |
050e6499 | 724 | |
1d4a7372 SC |
725 | level = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn, |
726 | huge_page_disallowed, &req_level); | |
4cd071d1 | 727 | |
335e192a PB |
728 | trace_kvm_mmu_spte_requested(addr, gw->level, pfn); |
729 | ||
3fcf2d1b | 730 | for (; shadow_walk_okay(&it); shadow_walk_next(&it)) { |
a30f47cb | 731 | clear_sp_write_flooding_count(it.sptep); |
b8e8c830 PB |
732 | |
733 | /* | |
734 | * We cannot overwrite existing page tables with an NX | |
735 | * large page, as the leaf could be executable. | |
736 | */ | |
dcc70651 | 737 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
738 | disallowed_hugepage_adjust(*it.sptep, gw->gfn, it.level, |
739 | &pfn, &level); | |
b8e8c830 | 740 | |
09c4453e | 741 | base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
1d4a7372 | 742 | if (it.level == level) |
3fcf2d1b PB |
743 | break; |
744 | ||
24157aaf | 745 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 746 | |
24157aaf | 747 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 748 | |
3fcf2d1b PB |
749 | if (!is_shadow_present_pte(*it.sptep)) { |
750 | sp = kvm_mmu_get_page(vcpu, base_gfn, addr, | |
751 | it.level - 1, true, direct_access); | |
752 | link_shadow_page(vcpu, it.sptep, sp); | |
5bcaf3e1 | 753 | if (huge_page_disallowed && req_level >= it.level) |
b8e8c830 | 754 | account_huge_nx_page(vcpu->kvm, sp); |
3fcf2d1b | 755 | } |
0b3c9333 AK |
756 | } |
757 | ||
9b8ebbdb | 758 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
3fcf2d1b | 759 | it.level, base_gfn, pfn, prefault, map_writable); |
12703759 SC |
760 | if (ret == RET_PF_SPURIOUS) |
761 | return ret; | |
762 | ||
189be38d | 763 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
3fcf2d1b | 764 | ++vcpu->stat.pf_fixed; |
9b8ebbdb | 765 | return ret; |
0b3c9333 AK |
766 | |
767 | out_gpte_changed: | |
9b8ebbdb | 768 | return RET_PF_RETRY; |
6aa8b732 AK |
769 | } |
770 | ||
7751babd XG |
771 | /* |
772 | * To see whether the mapped gfn can write its page table in the current | |
773 | * mapping. | |
774 | * | |
775 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
776 | * size to map the writable gfn which is used as current page table, we should | |
777 | * force kvm to use small page size to map it because new shadow page will be | |
778 | * created when kvm establishes shadow page table that stop kvm using large | |
779 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
780 | * | |
93c05d3e XG |
781 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
782 | * currently used as its page table. | |
783 | * | |
7751babd XG |
784 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
785 | * since the PDPT is always shadowed, that means, we can not use large page | |
786 | * size to map the gfn which is used as PDPT. | |
787 | */ | |
788 | static bool | |
789 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
e88b8093 | 790 | struct guest_walker *walker, bool user_fault, |
93c05d3e | 791 | bool *write_fault_to_shadow_pgtable) |
7751babd XG |
792 | { |
793 | int level; | |
794 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 795 | bool self_changed = false; |
7751babd XG |
796 | |
797 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
798 | (!is_write_protection(vcpu) && !user_fault))) | |
799 | return false; | |
800 | ||
93c05d3e XG |
801 | for (level = walker->level; level <= walker->max_level; level++) { |
802 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
803 | ||
804 | self_changed |= !(gfn & mask); | |
805 | *write_fault_to_shadow_pgtable |= !gfn; | |
806 | } | |
7751babd | 807 | |
93c05d3e | 808 | return self_changed; |
7751babd XG |
809 | } |
810 | ||
6aa8b732 AK |
811 | /* |
812 | * Page fault handler. There are several causes for a page fault: | |
813 | * - there is no shadow pte for the guest pte | |
814 | * - write access through a shadow pte marked read only so that we can set | |
815 | * the dirty bit | |
816 | * - write access to a shadow pte marked read only so we can update the page | |
817 | * dirty bitmap, when userspace requests it | |
818 | * - mmio access; in this case we will never install a present shadow pte | |
819 | * - normal guest page fault due to the guest pte marked not present, not | |
820 | * writable, or not executable | |
821 | * | |
e2dec939 AK |
822 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
823 | * a negative value on error. | |
6aa8b732 | 824 | */ |
736c291c | 825 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code, |
78b2c54a | 826 | bool prefault) |
6aa8b732 | 827 | { |
e88b8093 SC |
828 | bool write_fault = error_code & PFERR_WRITE_MASK; |
829 | bool user_fault = error_code & PFERR_USER_MASK; | |
6aa8b732 | 830 | struct guest_walker walker; |
e2dec939 | 831 | int r; |
ba049e93 | 832 | kvm_pfn_t pfn; |
4a42d848 | 833 | hva_t hva; |
e930bffe | 834 | unsigned long mmu_seq; |
93c05d3e | 835 | bool map_writable, is_self_change_mapping; |
39ca1ecb | 836 | int max_level; |
6aa8b732 | 837 | |
b8688d51 | 838 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 839 | |
e9ee956e TY |
840 | /* |
841 | * If PFEC.RSVD is set, this is a shadow page fault. | |
842 | * The bit needs to be cleared before walking guest page tables. | |
843 | */ | |
844 | error_code &= ~PFERR_RSVD_MASK; | |
845 | ||
6aa8b732 | 846 | /* |
a8b876b1 | 847 | * Look up the guest pte for the faulting address. |
6aa8b732 | 848 | */ |
33770780 | 849 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
850 | |
851 | /* | |
852 | * The page is not mapped by the guest. Let the guest handle it. | |
853 | */ | |
7993ba43 | 854 | if (!r) { |
b8688d51 | 855 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 856 | if (!prefault) |
0cd665bd | 857 | kvm_inject_emulated_page_fault(vcpu, &walker.fault); |
a30f47cb | 858 | |
9b8ebbdb | 859 | return RET_PF_RETRY; |
6aa8b732 AK |
860 | } |
861 | ||
e5691a81 XG |
862 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
863 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 864 | return RET_PF_EMULATE; |
e5691a81 | 865 | } |
3d0c27ad | 866 | |
378f5cd6 | 867 | r = mmu_topup_memory_caches(vcpu, true); |
f3747a5a SC |
868 | if (r) |
869 | return r; | |
870 | ||
93c05d3e XG |
871 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
872 | ||
873 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
874 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
875 | ||
6c2fd34f | 876 | if (is_self_change_mapping) |
3bae0459 | 877 | max_level = PG_LEVEL_4K; |
cbe1e6f0 SC |
878 | else |
879 | max_level = walker.level; | |
880 | ||
e930bffe | 881 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 882 | smp_rmb(); |
af585b92 | 883 | |
4a42d848 DS |
884 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, &hva, |
885 | write_fault, &map_writable)) | |
9b8ebbdb | 886 | return RET_PF_RETRY; |
d7824fff | 887 | |
9034e6e8 | 888 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
889 | return r; |
890 | ||
c2288505 XG |
891 | /* |
892 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
893 | * we will cache the incorrect access into mmio spte. | |
894 | */ | |
895 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
896 | !is_write_protection(vcpu) && !user_fault && | |
897 | !is_noslot_pfn(pfn)) { | |
898 | walker.pte_access |= ACC_WRITE_MASK; | |
899 | walker.pte_access &= ~ACC_USER_MASK; | |
900 | ||
901 | /* | |
902 | * If we converted a user page to a kernel page, | |
903 | * so that the kernel can write to it when cr0.wp=0, | |
904 | * then we should prevent the kernel from executing it | |
905 | * if SMEP is enabled. | |
906 | */ | |
907 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
908 | walker.pte_access &= ~ACC_EXEC_MASK; | |
909 | } | |
910 | ||
43fdcda9 | 911 | r = RET_PF_RETRY; |
531810ca | 912 | write_lock(&vcpu->kvm->mmu_lock); |
4a42d848 | 913 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
e930bffe | 914 | goto out_unlock; |
bc32ce21 | 915 | |
0375f7fa | 916 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
7bd7ded6 SC |
917 | r = make_mmu_pages_available(vcpu); |
918 | if (r) | |
26eeb53c | 919 | goto out_unlock; |
6c2fd34f SC |
920 | r = FNAME(fetch)(vcpu, addr, &walker, error_code, max_level, pfn, |
921 | map_writable, prefault); | |
0375f7fa | 922 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
e930bffe AA |
923 | |
924 | out_unlock: | |
531810ca | 925 | write_unlock(&vcpu->kvm->mmu_lock); |
e930bffe | 926 | kvm_release_pfn_clean(pfn); |
43fdcda9 | 927 | return r; |
6aa8b732 AK |
928 | } |
929 | ||
505aef8f XG |
930 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
931 | { | |
932 | int offset = 0; | |
933 | ||
3bae0459 | 934 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
505aef8f XG |
935 | |
936 | if (PTTYPE == 32) | |
937 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
938 | ||
939 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
940 | } | |
941 | ||
7eb77e9f | 942 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 943 | { |
a461930b | 944 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 945 | struct kvm_mmu_page *sp; |
ace569e0 | 946 | u64 old_spte; |
a461930b AK |
947 | int level; |
948 | u64 *sptep; | |
949 | ||
bebb106a XG |
950 | vcpu_clear_mmio_info(vcpu, gva); |
951 | ||
f57f2ef5 XG |
952 | /* |
953 | * No need to check return value here, rmap_can_add() can | |
954 | * help us to skip pte prefetch later. | |
955 | */ | |
378f5cd6 | 956 | mmu_topup_memory_caches(vcpu, true); |
a7052897 | 957 | |
7eb77e9f | 958 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
959 | WARN_ON(1); |
960 | return; | |
961 | } | |
962 | ||
531810ca | 963 | write_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 964 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
965 | level = iterator.level; |
966 | sptep = iterator.sptep; | |
ad218f85 | 967 | |
57354682 | 968 | sp = sptep_to_sp(sptep); |
ace569e0 SC |
969 | old_spte = *sptep; |
970 | if (is_last_spte(old_spte, level)) { | |
f57f2ef5 XG |
971 | pt_element_t gpte; |
972 | gpa_t pte_gpa; | |
973 | ||
f78978aa XG |
974 | if (!sp->unsync) |
975 | break; | |
976 | ||
505aef8f | 977 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 978 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 979 | |
2de4085c | 980 | mmu_page_zap_pte(vcpu->kvm, sp, sptep, NULL); |
ace569e0 | 981 | if (is_shadow_present_pte(old_spte)) |
c3134ce2 LT |
982 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
983 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
984 | |
985 | if (!rmap_can_add(vcpu)) | |
986 | break; | |
987 | ||
54bf36aa PB |
988 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
989 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
990 | break; |
991 | ||
992 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 993 | } |
a7052897 | 994 | |
f78978aa | 995 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
996 | break; |
997 | } | |
531810ca | 998 | write_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
999 | } |
1000 | ||
736c291c SC |
1001 | /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */ |
1002 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access, | |
ab9ae313 | 1003 | struct x86_exception *exception) |
6aa8b732 AK |
1004 | { |
1005 | struct guest_walker walker; | |
e119d117 AK |
1006 | gpa_t gpa = UNMAPPED_GVA; |
1007 | int r; | |
6aa8b732 | 1008 | |
736c291c | 1009 | r = FNAME(walk_addr)(&walker, vcpu, addr, access); |
6aa8b732 | 1010 | |
e119d117 | 1011 | if (r) { |
1755fbcc | 1012 | gpa = gfn_to_gpa(walker.gfn); |
736c291c | 1013 | gpa |= addr & ~PAGE_MASK; |
8c28d031 AK |
1014 | } else if (exception) |
1015 | *exception = walker.fault; | |
6aa8b732 AK |
1016 | |
1017 | return gpa; | |
1018 | } | |
1019 | ||
37406aaa | 1020 | #if PTTYPE != PTTYPE_EPT |
736c291c SC |
1021 | /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */ |
1022 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr, | |
ab9ae313 AK |
1023 | u32 access, |
1024 | struct x86_exception *exception) | |
6539e738 JR |
1025 | { |
1026 | struct guest_walker walker; | |
1027 | gpa_t gpa = UNMAPPED_GVA; | |
1028 | int r; | |
1029 | ||
736c291c SC |
1030 | #ifndef CONFIG_X86_64 |
1031 | /* A 64-bit GVA should be impossible on 32-bit KVM. */ | |
1032 | WARN_ON_ONCE(vaddr >> 32); | |
1033 | #endif | |
1034 | ||
33770780 | 1035 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
1036 | |
1037 | if (r) { | |
1038 | gpa = gfn_to_gpa(walker.gfn); | |
1039 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
1040 | } else if (exception) |
1041 | *exception = walker.fault; | |
6539e738 JR |
1042 | |
1043 | return gpa; | |
1044 | } | |
37406aaa | 1045 | #endif |
6539e738 | 1046 | |
e8bc217a MT |
1047 | /* |
1048 | * Using the cached information from sp->gfns is safe because: | |
1049 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
1050 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
1051 | * |
1052 | * Note: | |
1053 | * We should flush all tlbs if spte is dropped even though guest is | |
1054 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
1055 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
1056 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
1057 | * freed pages. | |
a086f6a1 | 1058 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 1059 | */ |
a4a8e6f7 | 1060 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 1061 | { |
2640b086 | 1062 | union kvm_mmu_page_role mmu_role = vcpu->arch.mmu->mmu_role.base; |
505aef8f | 1063 | int i, nr_present = 0; |
9bdbba13 | 1064 | bool host_writable; |
51fb60d8 | 1065 | gpa_t first_pte_gpa; |
5ce4786f | 1066 | int set_spte_ret = 0; |
e8bc217a | 1067 | |
2640b086 SC |
1068 | /* |
1069 | * Ignore various flags when verifying that it's safe to sync a shadow | |
1070 | * page using the current MMU context. | |
1071 | * | |
1072 | * - level: not part of the overall MMU role and will never match as the MMU's | |
1073 | * level tracks the root level | |
1074 | * - access: updated based on the new guest PTE | |
1075 | * - quadrant: not part of the overall MMU role (similar to level) | |
1076 | */ | |
1077 | const union kvm_mmu_page_role sync_role_ign = { | |
1078 | .level = 0xf, | |
1079 | .access = 0x7, | |
1080 | .quadrant = 0x3, | |
1081 | }; | |
1082 | ||
1083 | /* | |
1084 | * Direct pages can never be unsync, and KVM should never attempt to | |
1085 | * sync a shadow page for a different MMU context, e.g. if the role | |
1086 | * differs then the memslot lookup (SMM vs. non-SMM) will be bogus, the | |
1087 | * reserved bits checks will be wrong, etc... | |
1088 | */ | |
1089 | if (WARN_ON_ONCE(sp->role.direct || | |
1090 | (sp->role.word ^ mmu_role.word) & ~sync_role_ign.word)) | |
1091 | return 0; | |
2032a93d | 1092 | |
505aef8f | 1093 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 1094 | |
e8bc217a MT |
1095 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
1096 | unsigned pte_access; | |
1097 | pt_element_t gpte; | |
1098 | gpa_t pte_gpa; | |
f55c3f41 | 1099 | gfn_t gfn; |
e8bc217a | 1100 | |
ce88decf | 1101 | if (!sp->spt[i]) |
e8bc217a MT |
1102 | continue; |
1103 | ||
51fb60d8 | 1104 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 1105 | |
54bf36aa PB |
1106 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
1107 | sizeof(pt_element_t))) | |
1f50f1b3 | 1108 | return 0; |
e8bc217a | 1109 | |
0ad805a0 | 1110 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
1111 | /* |
1112 | * Update spte before increasing tlbs_dirty to make | |
1113 | * sure no tlb flush is lost after spte is zapped; see | |
1114 | * the comments in kvm_flush_remote_tlbs(). | |
1115 | */ | |
1116 | smp_wmb(); | |
a086f6a1 | 1117 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1118 | continue; |
1119 | } | |
1120 | ||
ce88decf XG |
1121 | gfn = gpte_to_gfn(gpte); |
1122 | pte_access = sp->role.access; | |
42522d08 | 1123 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1124 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1125 | |
54bf36aa | 1126 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1127 | &nr_present)) |
ce88decf XG |
1128 | continue; |
1129 | ||
407c61c6 | 1130 | if (gfn != sp->gfns[i]) { |
c3707958 | 1131 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1132 | /* |
1133 | * The same as above where we are doing | |
1134 | * prefetch_invalid_gpte(). | |
1135 | */ | |
1136 | smp_wmb(); | |
a086f6a1 | 1137 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1138 | continue; |
1139 | } | |
1140 | ||
1141 | nr_present++; | |
ce88decf | 1142 | |
5fc3424f | 1143 | host_writable = sp->spt[i] & shadow_host_writable_mask; |
f8e453b0 | 1144 | |
5ce4786f | 1145 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
3bae0459 | 1146 | pte_access, PG_LEVEL_4K, |
5ce4786f JS |
1147 | gfn, spte_to_pfn(sp->spt[i]), |
1148 | true, false, host_writable); | |
e8bc217a MT |
1149 | } |
1150 | ||
5ce4786f JS |
1151 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1152 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1153 | ||
1f50f1b3 | 1154 | return nr_present; |
e8bc217a MT |
1155 | } |
1156 | ||
6aa8b732 AK |
1157 | #undef pt_element_t |
1158 | #undef guest_walker | |
1159 | #undef FNAME | |
1160 | #undef PT_BASE_ADDR_MASK | |
1161 | #undef PT_INDEX | |
e04da980 JR |
1162 | #undef PT_LVL_ADDR_MASK |
1163 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1164 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1165 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1166 | #undef gpte_to_gfn |
e04da980 | 1167 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1168 | #undef CMPXCHG |
d8089bac GN |
1169 | #undef PT_GUEST_ACCESSED_MASK |
1170 | #undef PT_GUEST_DIRTY_MASK | |
1171 | #undef PT_GUEST_DIRTY_SHIFT | |
1172 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1173 | #undef PT_HAVE_ACCESSED_DIRTY |