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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
200 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
201 | { | |
95b0430d TY |
202 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); |
203 | ||
ce88decf XG |
204 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
205 | ||
95b0430d | 206 | sp->mmio_cached = true; |
4f022648 | 207 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
208 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
209 | } | |
210 | ||
211 | static bool is_mmio_spte(u64 spte) | |
212 | { | |
213 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
214 | } | |
215 | ||
216 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
217 | { | |
218 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
219 | } | |
220 | ||
221 | static unsigned get_mmio_spte_access(u64 spte) | |
222 | { | |
223 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
224 | } | |
225 | ||
226 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
227 | { | |
228 | if (unlikely(is_noslot_pfn(pfn))) { | |
229 | mark_mmio_spte(sptep, gfn, access); | |
230 | return true; | |
231 | } | |
232 | ||
233 | return false; | |
234 | } | |
c7addb90 | 235 | |
82725b20 DE |
236 | static inline u64 rsvd_bits(int s, int e) |
237 | { | |
238 | return ((1ULL << (e - s + 1)) - 1) << s; | |
239 | } | |
240 | ||
7b52345e | 241 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 242 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
243 | { |
244 | shadow_user_mask = user_mask; | |
245 | shadow_accessed_mask = accessed_mask; | |
246 | shadow_dirty_mask = dirty_mask; | |
247 | shadow_nx_mask = nx_mask; | |
248 | shadow_x_mask = x_mask; | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
251 | ||
6aa8b732 AK |
252 | static int is_cpuid_PSE36(void) |
253 | { | |
254 | return 1; | |
255 | } | |
256 | ||
73b1087e AK |
257 | static int is_nx(struct kvm_vcpu *vcpu) |
258 | { | |
f6801dff | 259 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
260 | } |
261 | ||
c7addb90 AK |
262 | static int is_shadow_present_pte(u64 pte) |
263 | { | |
ce88decf | 264 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
265 | } |
266 | ||
05da4558 MT |
267 | static int is_large_pte(u64 pte) |
268 | { | |
269 | return pte & PT_PAGE_SIZE_MASK; | |
270 | } | |
271 | ||
43a3795a | 272 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 273 | { |
439e218a | 274 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
275 | } |
276 | ||
43a3795a | 277 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 278 | { |
4b1a80fa | 279 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
280 | } |
281 | ||
776e6633 MT |
282 | static int is_last_spte(u64 pte, int level) |
283 | { | |
284 | if (level == PT_PAGE_TABLE_LEVEL) | |
285 | return 1; | |
852e3c19 | 286 | if (is_large_pte(pte)) |
776e6633 MT |
287 | return 1; |
288 | return 0; | |
289 | } | |
290 | ||
35149e21 | 291 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 292 | { |
35149e21 | 293 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
294 | } |
295 | ||
da928521 AK |
296 | static gfn_t pse36_gfn_delta(u32 gpte) |
297 | { | |
298 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
299 | ||
300 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
301 | } | |
302 | ||
603e0651 | 303 | #ifdef CONFIG_X86_64 |
d555c333 | 304 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 305 | { |
603e0651 | 306 | *sptep = spte; |
e663ee64 AK |
307 | } |
308 | ||
603e0651 | 309 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 310 | { |
603e0651 XG |
311 | *sptep = spte; |
312 | } | |
313 | ||
314 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
315 | { | |
316 | return xchg(sptep, spte); | |
317 | } | |
c2a2ac2b XG |
318 | |
319 | static u64 __get_spte_lockless(u64 *sptep) | |
320 | { | |
321 | return ACCESS_ONCE(*sptep); | |
322 | } | |
ce88decf XG |
323 | |
324 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
325 | { | |
326 | /* It is valid if the spte is zapped. */ | |
327 | return spte == 0ull; | |
328 | } | |
a9221dd5 | 329 | #else |
603e0651 XG |
330 | union split_spte { |
331 | struct { | |
332 | u32 spte_low; | |
333 | u32 spte_high; | |
334 | }; | |
335 | u64 spte; | |
336 | }; | |
a9221dd5 | 337 | |
c2a2ac2b XG |
338 | static void count_spte_clear(u64 *sptep, u64 spte) |
339 | { | |
340 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
341 | ||
342 | if (is_shadow_present_pte(spte)) | |
343 | return; | |
344 | ||
345 | /* Ensure the spte is completely set before we increase the count */ | |
346 | smp_wmb(); | |
347 | sp->clear_spte_count++; | |
348 | } | |
349 | ||
603e0651 XG |
350 | static void __set_spte(u64 *sptep, u64 spte) |
351 | { | |
352 | union split_spte *ssptep, sspte; | |
a9221dd5 | 353 | |
603e0651 XG |
354 | ssptep = (union split_spte *)sptep; |
355 | sspte = (union split_spte)spte; | |
356 | ||
357 | ssptep->spte_high = sspte.spte_high; | |
358 | ||
359 | /* | |
360 | * If we map the spte from nonpresent to present, We should store | |
361 | * the high bits firstly, then set present bit, so cpu can not | |
362 | * fetch this spte while we are setting the spte. | |
363 | */ | |
364 | smp_wmb(); | |
365 | ||
366 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
367 | } |
368 | ||
603e0651 XG |
369 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
370 | { | |
371 | union split_spte *ssptep, sspte; | |
372 | ||
373 | ssptep = (union split_spte *)sptep; | |
374 | sspte = (union split_spte)spte; | |
375 | ||
376 | ssptep->spte_low = sspte.spte_low; | |
377 | ||
378 | /* | |
379 | * If we map the spte from present to nonpresent, we should clear | |
380 | * present bit firstly to avoid vcpu fetch the old high bits. | |
381 | */ | |
382 | smp_wmb(); | |
383 | ||
384 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 385 | count_spte_clear(sptep, spte); |
603e0651 XG |
386 | } |
387 | ||
388 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
389 | { | |
390 | union split_spte *ssptep, sspte, orig; | |
391 | ||
392 | ssptep = (union split_spte *)sptep; | |
393 | sspte = (union split_spte)spte; | |
394 | ||
395 | /* xchg acts as a barrier before the setting of the high bits */ | |
396 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
397 | orig.spte_high = ssptep->spte_high; |
398 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 399 | count_spte_clear(sptep, spte); |
603e0651 XG |
400 | |
401 | return orig.spte; | |
402 | } | |
c2a2ac2b XG |
403 | |
404 | /* | |
405 | * The idea using the light way get the spte on x86_32 guest is from | |
406 | * gup_get_pte(arch/x86/mm/gup.c). | |
407 | * The difference is we can not catch the spte tlb flush if we leave | |
408 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
409 | * is cleared. | |
410 | */ | |
411 | static u64 __get_spte_lockless(u64 *sptep) | |
412 | { | |
413 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
414 | union split_spte spte, *orig = (union split_spte *)sptep; | |
415 | int count; | |
416 | ||
417 | retry: | |
418 | count = sp->clear_spte_count; | |
419 | smp_rmb(); | |
420 | ||
421 | spte.spte_low = orig->spte_low; | |
422 | smp_rmb(); | |
423 | ||
424 | spte.spte_high = orig->spte_high; | |
425 | smp_rmb(); | |
426 | ||
427 | if (unlikely(spte.spte_low != orig->spte_low || | |
428 | count != sp->clear_spte_count)) | |
429 | goto retry; | |
430 | ||
431 | return spte.spte; | |
432 | } | |
ce88decf XG |
433 | |
434 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
435 | { | |
436 | union split_spte sspte = (union split_spte)spte; | |
437 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
438 | ||
439 | /* It is valid if the spte is zapped. */ | |
440 | if (spte == 0ull) | |
441 | return true; | |
442 | ||
443 | /* It is valid if the spte is being zapped. */ | |
444 | if (sspte.spte_low == 0ull && | |
445 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
446 | return true; | |
447 | ||
448 | return false; | |
449 | } | |
603e0651 XG |
450 | #endif |
451 | ||
c7ba5b48 XG |
452 | static bool spte_is_locklessly_modifiable(u64 spte) |
453 | { | |
feb3eb70 GN |
454 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
455 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
456 | } |
457 | ||
8672b721 XG |
458 | static bool spte_has_volatile_bits(u64 spte) |
459 | { | |
c7ba5b48 XG |
460 | /* |
461 | * Always atomicly update spte if it can be updated | |
462 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
463 | * also, it can help us to get a stable is_writable_pte() | |
464 | * to ensure tlb flush is not missed. | |
465 | */ | |
466 | if (spte_is_locklessly_modifiable(spte)) | |
467 | return true; | |
468 | ||
8672b721 XG |
469 | if (!shadow_accessed_mask) |
470 | return false; | |
471 | ||
472 | if (!is_shadow_present_pte(spte)) | |
473 | return false; | |
474 | ||
4132779b XG |
475 | if ((spte & shadow_accessed_mask) && |
476 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
477 | return false; |
478 | ||
479 | return true; | |
480 | } | |
481 | ||
4132779b XG |
482 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
483 | { | |
484 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
485 | } | |
486 | ||
1df9f2dc XG |
487 | /* Rules for using mmu_spte_set: |
488 | * Set the sptep from nonpresent to present. | |
489 | * Note: the sptep being assigned *must* be either not present | |
490 | * or in a state where the hardware will not attempt to update | |
491 | * the spte. | |
492 | */ | |
493 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
494 | { | |
495 | WARN_ON(is_shadow_present_pte(*sptep)); | |
496 | __set_spte(sptep, new_spte); | |
497 | } | |
498 | ||
499 | /* Rules for using mmu_spte_update: | |
500 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
501 | * |
502 | * Whenever we overwrite a writable spte with a read-only one we | |
503 | * should flush remote TLBs. Otherwise rmap_write_protect | |
504 | * will find a read-only spte, even though the writable spte | |
505 | * might be cached on a CPU's TLB, the return value indicates this | |
506 | * case. | |
1df9f2dc | 507 | */ |
6e7d0354 | 508 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 509 | { |
c7ba5b48 | 510 | u64 old_spte = *sptep; |
6e7d0354 | 511 | bool ret = false; |
4132779b XG |
512 | |
513 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 514 | |
6e7d0354 XG |
515 | if (!is_shadow_present_pte(old_spte)) { |
516 | mmu_spte_set(sptep, new_spte); | |
517 | return ret; | |
518 | } | |
4132779b | 519 | |
c7ba5b48 | 520 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 521 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 522 | else |
603e0651 | 523 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 524 | |
c7ba5b48 XG |
525 | /* |
526 | * For the spte updated out of mmu-lock is safe, since | |
527 | * we always atomicly update it, see the comments in | |
528 | * spte_has_volatile_bits(). | |
529 | */ | |
6e7d0354 XG |
530 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
531 | ret = true; | |
532 | ||
4132779b | 533 | if (!shadow_accessed_mask) |
6e7d0354 | 534 | return ret; |
4132779b XG |
535 | |
536 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
537 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
538 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
539 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
540 | |
541 | return ret; | |
b79b93f9 AK |
542 | } |
543 | ||
1df9f2dc XG |
544 | /* |
545 | * Rules for using mmu_spte_clear_track_bits: | |
546 | * It sets the sptep from present to nonpresent, and track the | |
547 | * state bits, it is used to clear the last level sptep. | |
548 | */ | |
549 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
550 | { | |
551 | pfn_t pfn; | |
552 | u64 old_spte = *sptep; | |
553 | ||
554 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 555 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 556 | else |
603e0651 | 557 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
558 | |
559 | if (!is_rmap_spte(old_spte)) | |
560 | return 0; | |
561 | ||
562 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
563 | |
564 | /* | |
565 | * KVM does not hold the refcount of the page used by | |
566 | * kvm mmu, before reclaiming the page, we should | |
567 | * unmap it from mmu first. | |
568 | */ | |
569 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
570 | ||
1df9f2dc XG |
571 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
572 | kvm_set_pfn_accessed(pfn); | |
573 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
574 | kvm_set_pfn_dirty(pfn); | |
575 | return 1; | |
576 | } | |
577 | ||
578 | /* | |
579 | * Rules for using mmu_spte_clear_no_track: | |
580 | * Directly clear spte without caring the state bits of sptep, | |
581 | * it is used to set the upper level spte. | |
582 | */ | |
583 | static void mmu_spte_clear_no_track(u64 *sptep) | |
584 | { | |
603e0651 | 585 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
586 | } |
587 | ||
c2a2ac2b XG |
588 | static u64 mmu_spte_get_lockless(u64 *sptep) |
589 | { | |
590 | return __get_spte_lockless(sptep); | |
591 | } | |
592 | ||
593 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
594 | { | |
c142786c AK |
595 | /* |
596 | * Prevent page table teardown by making any free-er wait during | |
597 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
598 | */ | |
599 | local_irq_disable(); | |
600 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
601 | /* | |
602 | * Make sure a following spte read is not reordered ahead of the write | |
603 | * to vcpu->mode. | |
604 | */ | |
605 | smp_mb(); | |
c2a2ac2b XG |
606 | } |
607 | ||
608 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
609 | { | |
c142786c AK |
610 | /* |
611 | * Make sure the write to vcpu->mode is not reordered in front of | |
612 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
613 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
614 | */ | |
615 | smp_mb(); | |
616 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
617 | local_irq_enable(); | |
c2a2ac2b XG |
618 | } |
619 | ||
e2dec939 | 620 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 621 | struct kmem_cache *base_cache, int min) |
714b93da AK |
622 | { |
623 | void *obj; | |
624 | ||
625 | if (cache->nobjs >= min) | |
e2dec939 | 626 | return 0; |
714b93da | 627 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 628 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 629 | if (!obj) |
e2dec939 | 630 | return -ENOMEM; |
714b93da AK |
631 | cache->objects[cache->nobjs++] = obj; |
632 | } | |
e2dec939 | 633 | return 0; |
714b93da AK |
634 | } |
635 | ||
f759e2b4 XG |
636 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
637 | { | |
638 | return cache->nobjs; | |
639 | } | |
640 | ||
e8ad9a70 XG |
641 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
642 | struct kmem_cache *cache) | |
714b93da AK |
643 | { |
644 | while (mc->nobjs) | |
e8ad9a70 | 645 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
646 | } |
647 | ||
c1158e63 | 648 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 649 | int min) |
c1158e63 | 650 | { |
842f22ed | 651 | void *page; |
c1158e63 AK |
652 | |
653 | if (cache->nobjs >= min) | |
654 | return 0; | |
655 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 656 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
657 | if (!page) |
658 | return -ENOMEM; | |
842f22ed | 659 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
660 | } |
661 | return 0; | |
662 | } | |
663 | ||
664 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
665 | { | |
666 | while (mc->nobjs) | |
c4d198d5 | 667 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
668 | } |
669 | ||
2e3e5882 | 670 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 671 | { |
e2dec939 AK |
672 | int r; |
673 | ||
53c07b18 | 674 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 675 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
676 | if (r) |
677 | goto out; | |
ad312c7c | 678 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
679 | if (r) |
680 | goto out; | |
ad312c7c | 681 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 682 | mmu_page_header_cache, 4); |
e2dec939 AK |
683 | out: |
684 | return r; | |
714b93da AK |
685 | } |
686 | ||
687 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
688 | { | |
53c07b18 XG |
689 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
690 | pte_list_desc_cache); | |
ad312c7c | 691 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
692 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
693 | mmu_page_header_cache); | |
714b93da AK |
694 | } |
695 | ||
80feb89a | 696 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
697 | { |
698 | void *p; | |
699 | ||
700 | BUG_ON(!mc->nobjs); | |
701 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
702 | return p; |
703 | } | |
704 | ||
53c07b18 | 705 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 706 | { |
80feb89a | 707 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
708 | } |
709 | ||
53c07b18 | 710 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 711 | { |
53c07b18 | 712 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
713 | } |
714 | ||
2032a93d LJ |
715 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
716 | { | |
717 | if (!sp->role.direct) | |
718 | return sp->gfns[index]; | |
719 | ||
720 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
721 | } | |
722 | ||
723 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
724 | { | |
725 | if (sp->role.direct) | |
726 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
727 | else | |
728 | sp->gfns[index] = gfn; | |
729 | } | |
730 | ||
05da4558 | 731 | /* |
d4dbf470 TY |
732 | * Return the pointer to the large page information for a given gfn, |
733 | * handling slots that are not large page aligned. | |
05da4558 | 734 | */ |
d4dbf470 TY |
735 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
736 | struct kvm_memory_slot *slot, | |
737 | int level) | |
05da4558 MT |
738 | { |
739 | unsigned long idx; | |
740 | ||
fb03cb6f | 741 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 742 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
743 | } |
744 | ||
745 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
746 | { | |
d25797b2 | 747 | struct kvm_memory_slot *slot; |
d4dbf470 | 748 | struct kvm_lpage_info *linfo; |
d25797b2 | 749 | int i; |
05da4558 | 750 | |
a1f4d395 | 751 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
752 | for (i = PT_DIRECTORY_LEVEL; |
753 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
754 | linfo = lpage_info_slot(gfn, slot, i); |
755 | linfo->write_count += 1; | |
d25797b2 | 756 | } |
332b207d | 757 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
758 | } |
759 | ||
760 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
761 | { | |
d25797b2 | 762 | struct kvm_memory_slot *slot; |
d4dbf470 | 763 | struct kvm_lpage_info *linfo; |
d25797b2 | 764 | int i; |
05da4558 | 765 | |
a1f4d395 | 766 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
767 | for (i = PT_DIRECTORY_LEVEL; |
768 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
769 | linfo = lpage_info_slot(gfn, slot, i); |
770 | linfo->write_count -= 1; | |
771 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 772 | } |
332b207d | 773 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
774 | } |
775 | ||
d25797b2 JR |
776 | static int has_wrprotected_page(struct kvm *kvm, |
777 | gfn_t gfn, | |
778 | int level) | |
05da4558 | 779 | { |
2843099f | 780 | struct kvm_memory_slot *slot; |
d4dbf470 | 781 | struct kvm_lpage_info *linfo; |
05da4558 | 782 | |
a1f4d395 | 783 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 784 | if (slot) { |
d4dbf470 TY |
785 | linfo = lpage_info_slot(gfn, slot, level); |
786 | return linfo->write_count; | |
05da4558 MT |
787 | } |
788 | ||
789 | return 1; | |
790 | } | |
791 | ||
d25797b2 | 792 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 793 | { |
8f0b1ab6 | 794 | unsigned long page_size; |
d25797b2 | 795 | int i, ret = 0; |
05da4558 | 796 | |
8f0b1ab6 | 797 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 798 | |
d25797b2 JR |
799 | for (i = PT_PAGE_TABLE_LEVEL; |
800 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
801 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
802 | ret = i; | |
803 | else | |
804 | break; | |
805 | } | |
806 | ||
4c2155ce | 807 | return ret; |
05da4558 MT |
808 | } |
809 | ||
5d163b1c XG |
810 | static struct kvm_memory_slot * |
811 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
812 | bool no_dirty_log) | |
05da4558 MT |
813 | { |
814 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
815 | |
816 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
817 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
818 | (no_dirty_log && slot->dirty_bitmap)) | |
819 | slot = NULL; | |
820 | ||
821 | return slot; | |
822 | } | |
823 | ||
824 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
825 | { | |
a0a8eaba | 826 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
827 | } |
828 | ||
829 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
830 | { | |
831 | int host_level, level, max_level; | |
05da4558 | 832 | |
d25797b2 JR |
833 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
834 | ||
835 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
836 | return host_level; | |
837 | ||
55dd98c3 | 838 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
839 | |
840 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
841 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
842 | break; | |
d25797b2 JR |
843 | |
844 | return level - 1; | |
05da4558 MT |
845 | } |
846 | ||
290fc38d | 847 | /* |
53c07b18 | 848 | * Pte mapping structures: |
cd4a4e53 | 849 | * |
53c07b18 | 850 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 851 | * |
53c07b18 XG |
852 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
853 | * pte_list_desc containing more mappings. | |
53a27b39 | 854 | * |
53c07b18 | 855 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
856 | * the spte was not added. |
857 | * | |
cd4a4e53 | 858 | */ |
53c07b18 XG |
859 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
860 | unsigned long *pte_list) | |
cd4a4e53 | 861 | { |
53c07b18 | 862 | struct pte_list_desc *desc; |
53a27b39 | 863 | int i, count = 0; |
cd4a4e53 | 864 | |
53c07b18 XG |
865 | if (!*pte_list) { |
866 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
867 | *pte_list = (unsigned long)spte; | |
868 | } else if (!(*pte_list & 1)) { | |
869 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
870 | desc = mmu_alloc_pte_list_desc(vcpu); | |
871 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 872 | desc->sptes[1] = spte; |
53c07b18 | 873 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 874 | ++count; |
cd4a4e53 | 875 | } else { |
53c07b18 XG |
876 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
877 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
878 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 879 | desc = desc->more; |
53c07b18 | 880 | count += PTE_LIST_EXT; |
53a27b39 | 881 | } |
53c07b18 XG |
882 | if (desc->sptes[PTE_LIST_EXT-1]) { |
883 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
884 | desc = desc->more; |
885 | } | |
d555c333 | 886 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 887 | ++count; |
d555c333 | 888 | desc->sptes[i] = spte; |
cd4a4e53 | 889 | } |
53a27b39 | 890 | return count; |
cd4a4e53 AK |
891 | } |
892 | ||
53c07b18 XG |
893 | static void |
894 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
895 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
896 | { |
897 | int j; | |
898 | ||
53c07b18 | 899 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 900 | ; |
d555c333 AK |
901 | desc->sptes[i] = desc->sptes[j]; |
902 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
903 | if (j != 0) |
904 | return; | |
905 | if (!prev_desc && !desc->more) | |
53c07b18 | 906 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
907 | else |
908 | if (prev_desc) | |
909 | prev_desc->more = desc->more; | |
910 | else | |
53c07b18 XG |
911 | *pte_list = (unsigned long)desc->more | 1; |
912 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
913 | } |
914 | ||
53c07b18 | 915 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 916 | { |
53c07b18 XG |
917 | struct pte_list_desc *desc; |
918 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
919 | int i; |
920 | ||
53c07b18 XG |
921 | if (!*pte_list) { |
922 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 923 | BUG(); |
53c07b18 XG |
924 | } else if (!(*pte_list & 1)) { |
925 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
926 | if ((u64 *)*pte_list != spte) { | |
927 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
928 | BUG(); |
929 | } | |
53c07b18 | 930 | *pte_list = 0; |
cd4a4e53 | 931 | } else { |
53c07b18 XG |
932 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
933 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
934 | prev_desc = NULL; |
935 | while (desc) { | |
53c07b18 | 936 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 937 | if (desc->sptes[i] == spte) { |
53c07b18 | 938 | pte_list_desc_remove_entry(pte_list, |
714b93da | 939 | desc, i, |
cd4a4e53 AK |
940 | prev_desc); |
941 | return; | |
942 | } | |
943 | prev_desc = desc; | |
944 | desc = desc->more; | |
945 | } | |
53c07b18 | 946 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
947 | BUG(); |
948 | } | |
949 | } | |
950 | ||
67052b35 XG |
951 | typedef void (*pte_list_walk_fn) (u64 *spte); |
952 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
953 | { | |
954 | struct pte_list_desc *desc; | |
955 | int i; | |
956 | ||
957 | if (!*pte_list) | |
958 | return; | |
959 | ||
960 | if (!(*pte_list & 1)) | |
961 | return fn((u64 *)*pte_list); | |
962 | ||
963 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
964 | while (desc) { | |
965 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
966 | fn(desc->sptes[i]); | |
967 | desc = desc->more; | |
968 | } | |
969 | } | |
970 | ||
9373e2c0 | 971 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 972 | struct kvm_memory_slot *slot) |
53c07b18 | 973 | { |
77d11309 | 974 | unsigned long idx; |
53c07b18 | 975 | |
77d11309 | 976 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 977 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
978 | } |
979 | ||
9b9b1492 TY |
980 | /* |
981 | * Take gfn and return the reverse mapping to it. | |
982 | */ | |
983 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
984 | { | |
985 | struct kvm_memory_slot *slot; | |
986 | ||
987 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 988 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
989 | } |
990 | ||
f759e2b4 XG |
991 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
992 | { | |
993 | struct kvm_mmu_memory_cache *cache; | |
994 | ||
995 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
996 | return mmu_memory_cache_free_objects(cache); | |
997 | } | |
998 | ||
53c07b18 XG |
999 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1000 | { | |
1001 | struct kvm_mmu_page *sp; | |
1002 | unsigned long *rmapp; | |
1003 | ||
53c07b18 XG |
1004 | sp = page_header(__pa(spte)); |
1005 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1006 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1007 | return pte_list_add(vcpu, spte, rmapp); | |
1008 | } | |
1009 | ||
53c07b18 XG |
1010 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1011 | { | |
1012 | struct kvm_mmu_page *sp; | |
1013 | gfn_t gfn; | |
1014 | unsigned long *rmapp; | |
1015 | ||
1016 | sp = page_header(__pa(spte)); | |
1017 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1018 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1019 | pte_list_remove(spte, rmapp); | |
1020 | } | |
1021 | ||
1e3f42f0 TY |
1022 | /* |
1023 | * Used by the following functions to iterate through the sptes linked by a | |
1024 | * rmap. All fields are private and not assumed to be used outside. | |
1025 | */ | |
1026 | struct rmap_iterator { | |
1027 | /* private fields */ | |
1028 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1029 | int pos; /* index of the sptep */ | |
1030 | }; | |
1031 | ||
1032 | /* | |
1033 | * Iteration must be started by this function. This should also be used after | |
1034 | * removing/dropping sptes from the rmap link because in such cases the | |
1035 | * information in the itererator may not be valid. | |
1036 | * | |
1037 | * Returns sptep if found, NULL otherwise. | |
1038 | */ | |
1039 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1040 | { | |
1041 | if (!rmap) | |
1042 | return NULL; | |
1043 | ||
1044 | if (!(rmap & 1)) { | |
1045 | iter->desc = NULL; | |
1046 | return (u64 *)rmap; | |
1047 | } | |
1048 | ||
1049 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1050 | iter->pos = 0; | |
1051 | return iter->desc->sptes[iter->pos]; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1056 | * | |
1057 | * Returns sptep if found, NULL otherwise. | |
1058 | */ | |
1059 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1060 | { | |
1061 | if (iter->desc) { | |
1062 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1063 | u64 *sptep; | |
1064 | ||
1065 | ++iter->pos; | |
1066 | sptep = iter->desc->sptes[iter->pos]; | |
1067 | if (sptep) | |
1068 | return sptep; | |
1069 | } | |
1070 | ||
1071 | iter->desc = iter->desc->more; | |
1072 | ||
1073 | if (iter->desc) { | |
1074 | iter->pos = 0; | |
1075 | /* desc->sptes[0] cannot be NULL */ | |
1076 | return iter->desc->sptes[iter->pos]; | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | return NULL; | |
1081 | } | |
1082 | ||
c3707958 | 1083 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1084 | { |
1df9f2dc | 1085 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1086 | rmap_remove(kvm, sptep); |
be38d276 AK |
1087 | } |
1088 | ||
8e22f955 XG |
1089 | |
1090 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1091 | { | |
1092 | if (is_large_pte(*sptep)) { | |
1093 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1094 | PT_PAGE_TABLE_LEVEL); | |
1095 | drop_spte(kvm, sptep); | |
1096 | --kvm->stat.lpages; | |
1097 | return true; | |
1098 | } | |
1099 | ||
1100 | return false; | |
1101 | } | |
1102 | ||
1103 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1104 | { | |
1105 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1106 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1107 | } | |
1108 | ||
1109 | /* | |
49fde340 | 1110 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
6b73a960 MT |
1111 | * spte writ-protection is caused by protecting shadow page table. |
1112 | * @flush indicates whether tlb need be flushed. | |
49fde340 XG |
1113 | * |
1114 | * Note: write protection is difference between drity logging and spte | |
1115 | * protection: | |
1116 | * - for dirty logging, the spte can be set to writable at anytime if | |
1117 | * its dirty bitmap is properly set. | |
1118 | * - for spte protection, the spte can be writable only after unsync-ing | |
1119 | * shadow page. | |
8e22f955 | 1120 | * |
6b73a960 | 1121 | * Return true if the spte is dropped. |
8e22f955 | 1122 | */ |
6b73a960 MT |
1123 | static bool |
1124 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1125 | { |
1126 | u64 spte = *sptep; | |
1127 | ||
49fde340 XG |
1128 | if (!is_writable_pte(spte) && |
1129 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1130 | return false; |
1131 | ||
1132 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1133 | ||
6b73a960 MT |
1134 | if (__drop_large_spte(kvm, sptep)) { |
1135 | *flush |= true; | |
1136 | return true; | |
1137 | } | |
1138 | ||
49fde340 XG |
1139 | if (pt_protect) |
1140 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1141 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1142 | |
6b73a960 MT |
1143 | *flush |= mmu_spte_update(sptep, spte); |
1144 | return false; | |
d13bc5b5 XG |
1145 | } |
1146 | ||
49fde340 | 1147 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1148 | bool pt_protect) |
98348e95 | 1149 | { |
1e3f42f0 TY |
1150 | u64 *sptep; |
1151 | struct rmap_iterator iter; | |
d13bc5b5 | 1152 | bool flush = false; |
374cbac0 | 1153 | |
1e3f42f0 TY |
1154 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1155 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
6b73a960 MT |
1156 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1157 | sptep = rmap_get_first(*rmapp, &iter); | |
1158 | continue; | |
1159 | } | |
a0ed4607 | 1160 | |
d13bc5b5 | 1161 | sptep = rmap_get_next(&iter); |
374cbac0 | 1162 | } |
855149aa | 1163 | |
d13bc5b5 | 1164 | return flush; |
a0ed4607 TY |
1165 | } |
1166 | ||
5dc99b23 TY |
1167 | /** |
1168 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1169 | * @kvm: kvm instance | |
1170 | * @slot: slot to protect | |
1171 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1172 | * @mask: indicates which pages we should protect | |
1173 | * | |
1174 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1175 | * logging we do not have any such mappings. | |
1176 | */ | |
1177 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1178 | struct kvm_memory_slot *slot, | |
1179 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1180 | { |
1181 | unsigned long *rmapp; | |
a0ed4607 | 1182 | |
5dc99b23 | 1183 | while (mask) { |
65fbe37c TY |
1184 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1185 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1186 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1187 | |
5dc99b23 TY |
1188 | /* clear the first set bit */ |
1189 | mask &= mask - 1; | |
1190 | } | |
374cbac0 AK |
1191 | } |
1192 | ||
2f84569f | 1193 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1194 | { |
1195 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1196 | unsigned long *rmapp; |
1197 | int i; | |
2f84569f | 1198 | bool write_protected = false; |
95d4c16c TY |
1199 | |
1200 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1201 | |
1202 | for (i = PT_PAGE_TABLE_LEVEL; | |
1203 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1204 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1205 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1206 | } |
1207 | ||
1208 | return write_protected; | |
95d4c16c TY |
1209 | } |
1210 | ||
8a8365c5 | 1211 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1212 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1213 | { |
1e3f42f0 TY |
1214 | u64 *sptep; |
1215 | struct rmap_iterator iter; | |
e930bffe AA |
1216 | int need_tlb_flush = 0; |
1217 | ||
1e3f42f0 TY |
1218 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1219 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1220 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1221 | ||
1222 | drop_spte(kvm, sptep); | |
e930bffe AA |
1223 | need_tlb_flush = 1; |
1224 | } | |
1e3f42f0 | 1225 | |
e930bffe AA |
1226 | return need_tlb_flush; |
1227 | } | |
1228 | ||
8a8365c5 | 1229 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1230 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1231 | { |
1e3f42f0 TY |
1232 | u64 *sptep; |
1233 | struct rmap_iterator iter; | |
3da0dd43 | 1234 | int need_flush = 0; |
1e3f42f0 | 1235 | u64 new_spte; |
3da0dd43 IE |
1236 | pte_t *ptep = (pte_t *)data; |
1237 | pfn_t new_pfn; | |
1238 | ||
1239 | WARN_ON(pte_huge(*ptep)); | |
1240 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1241 | |
1242 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1243 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1244 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1245 | ||
3da0dd43 | 1246 | need_flush = 1; |
1e3f42f0 | 1247 | |
3da0dd43 | 1248 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1249 | drop_spte(kvm, sptep); |
1250 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1251 | } else { |
1e3f42f0 | 1252 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1253 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1254 | ||
1255 | new_spte &= ~PT_WRITABLE_MASK; | |
1256 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1257 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1258 | |
1259 | mmu_spte_clear_track_bits(sptep); | |
1260 | mmu_spte_set(sptep, new_spte); | |
1261 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1262 | } |
1263 | } | |
1e3f42f0 | 1264 | |
3da0dd43 IE |
1265 | if (need_flush) |
1266 | kvm_flush_remote_tlbs(kvm); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
84504ef3 TY |
1271 | static int kvm_handle_hva_range(struct kvm *kvm, |
1272 | unsigned long start, | |
1273 | unsigned long end, | |
1274 | unsigned long data, | |
1275 | int (*handler)(struct kvm *kvm, | |
1276 | unsigned long *rmapp, | |
048212d0 | 1277 | struct kvm_memory_slot *slot, |
84504ef3 | 1278 | unsigned long data)) |
e930bffe | 1279 | { |
be6ba0f0 | 1280 | int j; |
f395302e | 1281 | int ret = 0; |
bc6678a3 | 1282 | struct kvm_memslots *slots; |
be6ba0f0 | 1283 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1284 | |
90d83dc3 | 1285 | slots = kvm_memslots(kvm); |
e930bffe | 1286 | |
be6ba0f0 | 1287 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1288 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1289 | gfn_t gfn_start, gfn_end; |
e930bffe | 1290 | |
84504ef3 TY |
1291 | hva_start = max(start, memslot->userspace_addr); |
1292 | hva_end = min(end, memslot->userspace_addr + | |
1293 | (memslot->npages << PAGE_SHIFT)); | |
1294 | if (hva_start >= hva_end) | |
1295 | continue; | |
1296 | /* | |
1297 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1298 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1299 | */ |
bcd3ef58 | 1300 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1301 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1302 | |
bcd3ef58 TY |
1303 | for (j = PT_PAGE_TABLE_LEVEL; |
1304 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1305 | unsigned long idx, idx_end; | |
1306 | unsigned long *rmapp; | |
d4dbf470 | 1307 | |
bcd3ef58 TY |
1308 | /* |
1309 | * {idx(page_j) | page_j intersects with | |
1310 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1311 | */ | |
1312 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1313 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1314 | |
bcd3ef58 | 1315 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1316 | |
bcd3ef58 TY |
1317 | for (; idx <= idx_end; ++idx) |
1318 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1319 | } |
1320 | } | |
1321 | ||
f395302e | 1322 | return ret; |
e930bffe AA |
1323 | } |
1324 | ||
84504ef3 TY |
1325 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1326 | unsigned long data, | |
1327 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1328 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1329 | unsigned long data)) |
1330 | { | |
1331 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1332 | } |
1333 | ||
1334 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1335 | { | |
3da0dd43 IE |
1336 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1337 | } | |
1338 | ||
b3ae2096 TY |
1339 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1340 | { | |
1341 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1342 | } | |
1343 | ||
3da0dd43 IE |
1344 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1345 | { | |
8a8365c5 | 1346 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1347 | } |
1348 | ||
8a8365c5 | 1349 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1350 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1351 | { |
1e3f42f0 | 1352 | u64 *sptep; |
79f702a6 | 1353 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1354 | int young = 0; |
1355 | ||
6316e1c8 | 1356 | /* |
3f6d8c8a XH |
1357 | * In case of absence of EPT Access and Dirty Bits supports, |
1358 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1359 | * an EPT mapping, and clearing it if it does. On the next access, |
1360 | * a new EPT mapping will be established. | |
1361 | * This has some overhead, but not as much as the cost of swapping | |
1362 | * out actively used pages or breaking up actively used hugepages. | |
1363 | */ | |
f395302e TY |
1364 | if (!shadow_accessed_mask) { |
1365 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1366 | goto out; | |
1367 | } | |
534e38b4 | 1368 | |
1e3f42f0 TY |
1369 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1370 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1371 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1372 | |
3f6d8c8a | 1373 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1374 | young = 1; |
3f6d8c8a XH |
1375 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1376 | (unsigned long *)sptep); | |
e930bffe | 1377 | } |
e930bffe | 1378 | } |
f395302e TY |
1379 | out: |
1380 | /* @data has hva passed to kvm_age_hva(). */ | |
1381 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1382 | return young; |
1383 | } | |
1384 | ||
8ee53820 | 1385 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1386 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1387 | { |
1e3f42f0 TY |
1388 | u64 *sptep; |
1389 | struct rmap_iterator iter; | |
8ee53820 AA |
1390 | int young = 0; |
1391 | ||
1392 | /* | |
1393 | * If there's no access bit in the secondary pte set by the | |
1394 | * hardware it's up to gup-fast/gup to set the access bit in | |
1395 | * the primary pte or in the page structure. | |
1396 | */ | |
1397 | if (!shadow_accessed_mask) | |
1398 | goto out; | |
1399 | ||
1e3f42f0 TY |
1400 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1401 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1402 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1403 | |
3f6d8c8a | 1404 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1405 | young = 1; |
1406 | break; | |
1407 | } | |
8ee53820 AA |
1408 | } |
1409 | out: | |
1410 | return young; | |
1411 | } | |
1412 | ||
53a27b39 MT |
1413 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1414 | ||
852e3c19 | 1415 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1416 | { |
1417 | unsigned long *rmapp; | |
852e3c19 JR |
1418 | struct kvm_mmu_page *sp; |
1419 | ||
1420 | sp = page_header(__pa(spte)); | |
53a27b39 | 1421 | |
852e3c19 | 1422 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1423 | |
048212d0 | 1424 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1425 | kvm_flush_remote_tlbs(vcpu->kvm); |
1426 | } | |
1427 | ||
e930bffe AA |
1428 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1429 | { | |
f395302e | 1430 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1431 | } |
1432 | ||
8ee53820 AA |
1433 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1434 | { | |
1435 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1436 | } | |
1437 | ||
d6c69ee9 | 1438 | #ifdef MMU_DEBUG |
47ad8e68 | 1439 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1440 | { |
139bdb2d AK |
1441 | u64 *pos; |
1442 | u64 *end; | |
1443 | ||
47ad8e68 | 1444 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1445 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1446 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1447 | pos, *pos); |
6aa8b732 | 1448 | return 0; |
139bdb2d | 1449 | } |
6aa8b732 AK |
1450 | return 1; |
1451 | } | |
d6c69ee9 | 1452 | #endif |
6aa8b732 | 1453 | |
45221ab6 DH |
1454 | /* |
1455 | * This value is the sum of all of the kvm instances's | |
1456 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1457 | * aggregate version in order to make the slab shrinker | |
1458 | * faster | |
1459 | */ | |
1460 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1461 | { | |
1462 | kvm->arch.n_used_mmu_pages += nr; | |
1463 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1464 | } | |
1465 | ||
834be0d8 | 1466 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1467 | { |
4db35314 | 1468 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1469 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1470 | list_del(&sp->link); |
1471 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1472 | if (!sp->role.direct) |
1473 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1474 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1475 | } |
1476 | ||
cea0f0e7 AK |
1477 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1478 | { | |
1ae0a13d | 1479 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1480 | } |
1481 | ||
714b93da | 1482 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1483 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1484 | { |
cea0f0e7 AK |
1485 | if (!parent_pte) |
1486 | return; | |
cea0f0e7 | 1487 | |
67052b35 | 1488 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1489 | } |
1490 | ||
4db35314 | 1491 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1492 | u64 *parent_pte) |
1493 | { | |
67052b35 | 1494 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1495 | } |
1496 | ||
bcdd9a93 XG |
1497 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1498 | u64 *parent_pte) | |
1499 | { | |
1500 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1501 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1502 | } |
1503 | ||
67052b35 XG |
1504 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1505 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1506 | { |
67052b35 | 1507 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1508 | |
80feb89a TY |
1509 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1510 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1511 | if (!direct) |
80feb89a | 1512 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 XG |
1513 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
1514 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
67052b35 XG |
1515 | sp->parent_ptes = 0; |
1516 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1517 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1518 | return sp; | |
ad8cfbe3 MT |
1519 | } |
1520 | ||
67052b35 | 1521 | static void mark_unsync(u64 *spte); |
1047df1f | 1522 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1523 | { |
67052b35 | 1524 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1525 | } |
1526 | ||
67052b35 | 1527 | static void mark_unsync(u64 *spte) |
0074ff63 | 1528 | { |
67052b35 | 1529 | struct kvm_mmu_page *sp; |
1047df1f | 1530 | unsigned int index; |
0074ff63 | 1531 | |
67052b35 | 1532 | sp = page_header(__pa(spte)); |
1047df1f XG |
1533 | index = spte - sp->spt; |
1534 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1535 | return; |
1047df1f | 1536 | if (sp->unsync_children++) |
0074ff63 | 1537 | return; |
1047df1f | 1538 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1539 | } |
1540 | ||
e8bc217a | 1541 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1542 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1543 | { |
1544 | return 1; | |
1545 | } | |
1546 | ||
a7052897 MT |
1547 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1548 | { | |
1549 | } | |
1550 | ||
0f53b5b1 XG |
1551 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1552 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1553 | const void *pte) |
0f53b5b1 XG |
1554 | { |
1555 | WARN_ON(1); | |
1556 | } | |
1557 | ||
60c8aec6 MT |
1558 | #define KVM_PAGE_ARRAY_NR 16 |
1559 | ||
1560 | struct kvm_mmu_pages { | |
1561 | struct mmu_page_and_offset { | |
1562 | struct kvm_mmu_page *sp; | |
1563 | unsigned int idx; | |
1564 | } page[KVM_PAGE_ARRAY_NR]; | |
1565 | unsigned int nr; | |
1566 | }; | |
1567 | ||
cded19f3 HE |
1568 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1569 | int idx) | |
4731d4c7 | 1570 | { |
60c8aec6 | 1571 | int i; |
4731d4c7 | 1572 | |
60c8aec6 MT |
1573 | if (sp->unsync) |
1574 | for (i=0; i < pvec->nr; i++) | |
1575 | if (pvec->page[i].sp == sp) | |
1576 | return 0; | |
1577 | ||
1578 | pvec->page[pvec->nr].sp = sp; | |
1579 | pvec->page[pvec->nr].idx = idx; | |
1580 | pvec->nr++; | |
1581 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1582 | } | |
1583 | ||
1584 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1585 | struct kvm_mmu_pages *pvec) | |
1586 | { | |
1587 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1588 | |
37178b8b | 1589 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1590 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1591 | u64 ent = sp->spt[i]; |
1592 | ||
7a8f1a74 XG |
1593 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1594 | goto clear_child_bitmap; | |
1595 | ||
1596 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1597 | ||
1598 | if (child->unsync_children) { | |
1599 | if (mmu_pages_add(pvec, child, i)) | |
1600 | return -ENOSPC; | |
1601 | ||
1602 | ret = __mmu_unsync_walk(child, pvec); | |
1603 | if (!ret) | |
1604 | goto clear_child_bitmap; | |
1605 | else if (ret > 0) | |
1606 | nr_unsync_leaf += ret; | |
1607 | else | |
1608 | return ret; | |
1609 | } else if (child->unsync) { | |
1610 | nr_unsync_leaf++; | |
1611 | if (mmu_pages_add(pvec, child, i)) | |
1612 | return -ENOSPC; | |
1613 | } else | |
1614 | goto clear_child_bitmap; | |
1615 | ||
1616 | continue; | |
1617 | ||
1618 | clear_child_bitmap: | |
1619 | __clear_bit(i, sp->unsync_child_bitmap); | |
1620 | sp->unsync_children--; | |
1621 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1622 | } |
1623 | ||
4731d4c7 | 1624 | |
60c8aec6 MT |
1625 | return nr_unsync_leaf; |
1626 | } | |
1627 | ||
1628 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1629 | struct kvm_mmu_pages *pvec) | |
1630 | { | |
1631 | if (!sp->unsync_children) | |
1632 | return 0; | |
1633 | ||
1634 | mmu_pages_add(pvec, sp, 0); | |
1635 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1636 | } |
1637 | ||
4731d4c7 MT |
1638 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1639 | { | |
1640 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1641 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1642 | sp->unsync = 0; |
1643 | --kvm->stat.mmu_unsync; | |
1644 | } | |
1645 | ||
7775834a XG |
1646 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1647 | struct list_head *invalid_list); | |
1648 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1649 | struct list_head *invalid_list); | |
4731d4c7 | 1650 | |
1044b030 TY |
1651 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1652 | hlist_for_each_entry(_sp, \ | |
1653 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1654 | if ((_sp)->gfn != (_gfn)) {} else | |
1655 | ||
1656 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1657 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1658 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1659 | |
f918b443 | 1660 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1661 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1662 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1663 | { |
5b7e0102 | 1664 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1665 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1666 | return 1; |
1667 | } | |
1668 | ||
f918b443 | 1669 | if (clear_unsync) |
1d9dc7e0 | 1670 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1671 | |
a4a8e6f7 | 1672 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1673 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1674 | return 1; |
1675 | } | |
1676 | ||
1677 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1678 | return 0; |
1679 | } | |
1680 | ||
1d9dc7e0 XG |
1681 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1682 | struct kvm_mmu_page *sp) | |
1683 | { | |
d98ba053 | 1684 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1685 | int ret; |
1686 | ||
d98ba053 | 1687 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1688 | if (ret) |
d98ba053 XG |
1689 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1690 | ||
1d9dc7e0 XG |
1691 | return ret; |
1692 | } | |
1693 | ||
e37fa785 XG |
1694 | #ifdef CONFIG_KVM_MMU_AUDIT |
1695 | #include "mmu_audit.c" | |
1696 | #else | |
1697 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1698 | static void mmu_audit_disable(void) { } | |
1699 | #endif | |
1700 | ||
d98ba053 XG |
1701 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1702 | struct list_head *invalid_list) | |
1d9dc7e0 | 1703 | { |
d98ba053 | 1704 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1705 | } |
1706 | ||
9f1a122f XG |
1707 | /* @gfn should be write-protected at the call site */ |
1708 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1709 | { | |
9f1a122f | 1710 | struct kvm_mmu_page *s; |
d98ba053 | 1711 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1712 | bool flush = false; |
1713 | ||
b67bfe0d | 1714 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1715 | if (!s->unsync) |
9f1a122f XG |
1716 | continue; |
1717 | ||
1718 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1719 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1720 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1721 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1722 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1723 | continue; |
1724 | } | |
9f1a122f XG |
1725 | flush = true; |
1726 | } | |
1727 | ||
d98ba053 | 1728 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1729 | if (flush) |
1730 | kvm_mmu_flush_tlb(vcpu); | |
1731 | } | |
1732 | ||
60c8aec6 MT |
1733 | struct mmu_page_path { |
1734 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1735 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1736 | }; |
1737 | ||
60c8aec6 MT |
1738 | #define for_each_sp(pvec, sp, parents, i) \ |
1739 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1740 | sp = pvec.page[i].sp; \ | |
1741 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1742 | i = mmu_pages_next(&pvec, &parents, i)) | |
1743 | ||
cded19f3 HE |
1744 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1745 | struct mmu_page_path *parents, | |
1746 | int i) | |
60c8aec6 MT |
1747 | { |
1748 | int n; | |
1749 | ||
1750 | for (n = i+1; n < pvec->nr; n++) { | |
1751 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1752 | ||
1753 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1754 | parents->idx[0] = pvec->page[n].idx; | |
1755 | return n; | |
1756 | } | |
1757 | ||
1758 | parents->parent[sp->role.level-2] = sp; | |
1759 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1760 | } | |
1761 | ||
1762 | return n; | |
1763 | } | |
1764 | ||
cded19f3 | 1765 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1766 | { |
60c8aec6 MT |
1767 | struct kvm_mmu_page *sp; |
1768 | unsigned int level = 0; | |
1769 | ||
1770 | do { | |
1771 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1772 | |
60c8aec6 MT |
1773 | sp = parents->parent[level]; |
1774 | if (!sp) | |
1775 | return; | |
1776 | ||
1777 | --sp->unsync_children; | |
1778 | WARN_ON((int)sp->unsync_children < 0); | |
1779 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1780 | level++; | |
1781 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1782 | } |
1783 | ||
60c8aec6 MT |
1784 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1785 | struct mmu_page_path *parents, | |
1786 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1787 | { |
60c8aec6 MT |
1788 | parents->parent[parent->role.level-1] = NULL; |
1789 | pvec->nr = 0; | |
1790 | } | |
4731d4c7 | 1791 | |
60c8aec6 MT |
1792 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1793 | struct kvm_mmu_page *parent) | |
1794 | { | |
1795 | int i; | |
1796 | struct kvm_mmu_page *sp; | |
1797 | struct mmu_page_path parents; | |
1798 | struct kvm_mmu_pages pages; | |
d98ba053 | 1799 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1800 | |
1801 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1802 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1803 | bool protected = false; |
b1a36821 MT |
1804 | |
1805 | for_each_sp(pages, sp, parents, i) | |
1806 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1807 | ||
1808 | if (protected) | |
1809 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1810 | ||
60c8aec6 | 1811 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1812 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1813 | mmu_pages_clear_parents(&parents); |
1814 | } | |
d98ba053 | 1815 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1816 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1817 | kvm_mmu_pages_init(parent, &parents, &pages); |
1818 | } | |
4731d4c7 MT |
1819 | } |
1820 | ||
c3707958 XG |
1821 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1822 | { | |
1823 | int i; | |
1824 | ||
1825 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1826 | sp->spt[i] = 0ull; | |
1827 | } | |
1828 | ||
a30f47cb XG |
1829 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1830 | { | |
1831 | sp->write_flooding_count = 0; | |
1832 | } | |
1833 | ||
1834 | static void clear_sp_write_flooding_count(u64 *spte) | |
1835 | { | |
1836 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1837 | ||
1838 | __clear_sp_write_flooding_count(sp); | |
1839 | } | |
1840 | ||
cea0f0e7 AK |
1841 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1842 | gfn_t gfn, | |
1843 | gva_t gaddr, | |
1844 | unsigned level, | |
f6e2c02b | 1845 | int direct, |
41074d07 | 1846 | unsigned access, |
f7d9c7b7 | 1847 | u64 *parent_pte) |
cea0f0e7 AK |
1848 | { |
1849 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1850 | unsigned quadrant; |
9f1a122f | 1851 | struct kvm_mmu_page *sp; |
9f1a122f | 1852 | bool need_sync = false; |
cea0f0e7 | 1853 | |
a770f6f2 | 1854 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1855 | role.level = level; |
f6e2c02b | 1856 | role.direct = direct; |
84b0c8c6 | 1857 | if (role.direct) |
5b7e0102 | 1858 | role.cr4_pae = 0; |
41074d07 | 1859 | role.access = access; |
c5a78f2b JR |
1860 | if (!vcpu->arch.mmu.direct_map |
1861 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1862 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1863 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1864 | role.quadrant = quadrant; | |
1865 | } | |
b67bfe0d | 1866 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7ae680eb XG |
1867 | if (!need_sync && sp->unsync) |
1868 | need_sync = true; | |
4731d4c7 | 1869 | |
7ae680eb XG |
1870 | if (sp->role.word != role.word) |
1871 | continue; | |
4731d4c7 | 1872 | |
7ae680eb XG |
1873 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1874 | break; | |
e02aa901 | 1875 | |
7ae680eb XG |
1876 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1877 | if (sp->unsync_children) { | |
a8eeb04a | 1878 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1879 | kvm_mmu_mark_parents_unsync(sp); |
1880 | } else if (sp->unsync) | |
1881 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1882 | |
a30f47cb | 1883 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1884 | trace_kvm_mmu_get_page(sp, false); |
1885 | return sp; | |
1886 | } | |
dfc5aa00 | 1887 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1888 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1889 | if (!sp) |
1890 | return sp; | |
4db35314 AK |
1891 | sp->gfn = gfn; |
1892 | sp->role = role; | |
7ae680eb XG |
1893 | hlist_add_head(&sp->hash_link, |
1894 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1895 | if (!direct) { |
b1a36821 MT |
1896 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1897 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1898 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1899 | kvm_sync_pages(vcpu, gfn); | |
1900 | ||
4731d4c7 MT |
1901 | account_shadowed(vcpu->kvm, gfn); |
1902 | } | |
c3707958 | 1903 | init_shadow_page_table(sp); |
f691fe1d | 1904 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1905 | return sp; |
cea0f0e7 AK |
1906 | } |
1907 | ||
2d11123a AK |
1908 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1909 | struct kvm_vcpu *vcpu, u64 addr) | |
1910 | { | |
1911 | iterator->addr = addr; | |
1912 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1913 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1914 | |
1915 | if (iterator->level == PT64_ROOT_LEVEL && | |
1916 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1917 | !vcpu->arch.mmu.direct_map) | |
1918 | --iterator->level; | |
1919 | ||
2d11123a AK |
1920 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1921 | iterator->shadow_addr | |
1922 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1923 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1924 | --iterator->level; | |
1925 | if (!iterator->shadow_addr) | |
1926 | iterator->level = 0; | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1931 | { | |
1932 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1933 | return false; | |
4d88954d | 1934 | |
2d11123a AK |
1935 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1936 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1937 | return true; | |
1938 | } | |
1939 | ||
c2a2ac2b XG |
1940 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1941 | u64 spte) | |
2d11123a | 1942 | { |
c2a2ac2b | 1943 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1944 | iterator->level = 0; |
1945 | return; | |
1946 | } | |
1947 | ||
c2a2ac2b | 1948 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1949 | --iterator->level; |
1950 | } | |
1951 | ||
c2a2ac2b XG |
1952 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1953 | { | |
1954 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1955 | } | |
1956 | ||
32ef26a3 AK |
1957 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1958 | { | |
1959 | u64 spte; | |
1960 | ||
24db2734 XG |
1961 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
1962 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; | |
1963 | ||
1df9f2dc | 1964 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1965 | } |
1966 | ||
a357bd22 AK |
1967 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1968 | unsigned direct_access) | |
1969 | { | |
1970 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1971 | struct kvm_mmu_page *child; | |
1972 | ||
1973 | /* | |
1974 | * For the direct sp, if the guest pte's dirty bit | |
1975 | * changed form clean to dirty, it will corrupt the | |
1976 | * sp's access: allow writable in the read-only sp, | |
1977 | * so we should update the spte at this point to get | |
1978 | * a new sp with the correct access. | |
1979 | */ | |
1980 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1981 | if (child->role.access == direct_access) | |
1982 | return; | |
1983 | ||
bcdd9a93 | 1984 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1985 | kvm_flush_remote_tlbs(vcpu->kvm); |
1986 | } | |
1987 | } | |
1988 | ||
505aef8f | 1989 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
1990 | u64 *spte) |
1991 | { | |
1992 | u64 pte; | |
1993 | struct kvm_mmu_page *child; | |
1994 | ||
1995 | pte = *spte; | |
1996 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 1997 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 1998 | drop_spte(kvm, spte); |
505aef8f XG |
1999 | if (is_large_pte(pte)) |
2000 | --kvm->stat.lpages; | |
2001 | } else { | |
38e3b2b2 | 2002 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2003 | drop_parent_pte(child, spte); |
38e3b2b2 | 2004 | } |
505aef8f XG |
2005 | return true; |
2006 | } | |
2007 | ||
2008 | if (is_mmio_spte(pte)) | |
ce88decf | 2009 | mmu_spte_clear_no_track(spte); |
c3707958 | 2010 | |
505aef8f | 2011 | return false; |
38e3b2b2 XG |
2012 | } |
2013 | ||
90cb0529 | 2014 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2015 | struct kvm_mmu_page *sp) |
a436036b | 2016 | { |
697fe2e2 | 2017 | unsigned i; |
697fe2e2 | 2018 | |
38e3b2b2 XG |
2019 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2020 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2021 | } |
2022 | ||
4db35314 | 2023 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2024 | { |
4db35314 | 2025 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2026 | } |
2027 | ||
31aa2b44 | 2028 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2029 | { |
1e3f42f0 TY |
2030 | u64 *sptep; |
2031 | struct rmap_iterator iter; | |
a436036b | 2032 | |
1e3f42f0 TY |
2033 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2034 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2035 | } |
2036 | ||
60c8aec6 | 2037 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2038 | struct kvm_mmu_page *parent, |
2039 | struct list_head *invalid_list) | |
4731d4c7 | 2040 | { |
60c8aec6 MT |
2041 | int i, zapped = 0; |
2042 | struct mmu_page_path parents; | |
2043 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2044 | |
60c8aec6 | 2045 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2046 | return 0; |
60c8aec6 MT |
2047 | |
2048 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2049 | while (mmu_unsync_walk(parent, &pages)) { | |
2050 | struct kvm_mmu_page *sp; | |
2051 | ||
2052 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2053 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2054 | mmu_pages_clear_parents(&parents); |
77662e00 | 2055 | zapped++; |
60c8aec6 | 2056 | } |
60c8aec6 MT |
2057 | kvm_mmu_pages_init(parent, &parents, &pages); |
2058 | } | |
2059 | ||
2060 | return zapped; | |
4731d4c7 MT |
2061 | } |
2062 | ||
7775834a XG |
2063 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2064 | struct list_head *invalid_list) | |
31aa2b44 | 2065 | { |
4731d4c7 | 2066 | int ret; |
f691fe1d | 2067 | |
7775834a | 2068 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2069 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2070 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2071 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2072 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 2073 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2074 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
2075 | if (sp->unsync) |
2076 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2077 | if (!sp->root_count) { |
54a4f023 GJ |
2078 | /* Count self */ |
2079 | ret++; | |
7775834a | 2080 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2081 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2082 | } else { |
5b5c6a5a | 2083 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
2084 | kvm_reload_remote_mmus(kvm); |
2085 | } | |
7775834a XG |
2086 | |
2087 | sp->role.invalid = 1; | |
4731d4c7 | 2088 | return ret; |
a436036b AK |
2089 | } |
2090 | ||
7775834a XG |
2091 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2092 | struct list_head *invalid_list) | |
2093 | { | |
945315b9 | 2094 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2095 | |
2096 | if (list_empty(invalid_list)) | |
2097 | return; | |
2098 | ||
c142786c AK |
2099 | /* |
2100 | * wmb: make sure everyone sees our modifications to the page tables | |
2101 | * rmb: make sure we see changes to vcpu->mode | |
2102 | */ | |
2103 | smp_mb(); | |
4f022648 | 2104 | |
c142786c AK |
2105 | /* |
2106 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2107 | * page table walks. | |
2108 | */ | |
2109 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2110 | |
945315b9 | 2111 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2112 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2113 | kvm_mmu_free_page(sp); |
945315b9 | 2114 | } |
7775834a XG |
2115 | } |
2116 | ||
5da59607 TY |
2117 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2118 | struct list_head *invalid_list) | |
2119 | { | |
2120 | struct kvm_mmu_page *sp; | |
2121 | ||
2122 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2123 | return false; | |
2124 | ||
2125 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2126 | struct kvm_mmu_page, link); | |
2127 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2128 | ||
2129 | return true; | |
2130 | } | |
2131 | ||
82ce2c96 IE |
2132 | /* |
2133 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2134 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2135 | */ |
49d5ca26 | 2136 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2137 | { |
d98ba053 | 2138 | LIST_HEAD(invalid_list); |
82ce2c96 | 2139 | |
b34cb590 TY |
2140 | spin_lock(&kvm->mmu_lock); |
2141 | ||
49d5ca26 | 2142 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2143 | /* Need to free some mmu pages to achieve the goal. */ |
2144 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2145 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2146 | break; | |
82ce2c96 | 2147 | |
aa6bd187 | 2148 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2149 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2150 | } |
82ce2c96 | 2151 | |
49d5ca26 | 2152 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2153 | |
2154 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2155 | } |
2156 | ||
1cb3f3ae | 2157 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2158 | { |
4db35314 | 2159 | struct kvm_mmu_page *sp; |
d98ba053 | 2160 | LIST_HEAD(invalid_list); |
a436036b AK |
2161 | int r; |
2162 | ||
9ad17b10 | 2163 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2164 | r = 0; |
1cb3f3ae | 2165 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2166 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2167 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2168 | sp->role.word); |
2169 | r = 1; | |
f41d335a | 2170 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2171 | } |
d98ba053 | 2172 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2173 | spin_unlock(&kvm->mmu_lock); |
2174 | ||
a436036b | 2175 | return r; |
cea0f0e7 | 2176 | } |
1cb3f3ae | 2177 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2178 | |
74be52e3 SY |
2179 | /* |
2180 | * The function is based on mtrr_type_lookup() in | |
2181 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2182 | */ | |
2183 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2184 | u64 start, u64 end) | |
2185 | { | |
2186 | int i; | |
2187 | u64 base, mask; | |
2188 | u8 prev_match, curr_match; | |
2189 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2190 | ||
2191 | if (!mtrr_state->enabled) | |
2192 | return 0xFF; | |
2193 | ||
2194 | /* Make end inclusive end, instead of exclusive */ | |
2195 | end--; | |
2196 | ||
2197 | /* Look in fixed ranges. Just return the type as per start */ | |
2198 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2199 | int idx; | |
2200 | ||
2201 | if (start < 0x80000) { | |
2202 | idx = 0; | |
2203 | idx += (start >> 16); | |
2204 | return mtrr_state->fixed_ranges[idx]; | |
2205 | } else if (start < 0xC0000) { | |
2206 | idx = 1 * 8; | |
2207 | idx += ((start - 0x80000) >> 14); | |
2208 | return mtrr_state->fixed_ranges[idx]; | |
2209 | } else if (start < 0x1000000) { | |
2210 | idx = 3 * 8; | |
2211 | idx += ((start - 0xC0000) >> 12); | |
2212 | return mtrr_state->fixed_ranges[idx]; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* | |
2217 | * Look in variable ranges | |
2218 | * Look of multiple ranges matching this address and pick type | |
2219 | * as per MTRR precedence | |
2220 | */ | |
2221 | if (!(mtrr_state->enabled & 2)) | |
2222 | return mtrr_state->def_type; | |
2223 | ||
2224 | prev_match = 0xFF; | |
2225 | for (i = 0; i < num_var_ranges; ++i) { | |
2226 | unsigned short start_state, end_state; | |
2227 | ||
2228 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2229 | continue; | |
2230 | ||
2231 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2232 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2233 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2234 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2235 | ||
2236 | start_state = ((start & mask) == (base & mask)); | |
2237 | end_state = ((end & mask) == (base & mask)); | |
2238 | if (start_state != end_state) | |
2239 | return 0xFE; | |
2240 | ||
2241 | if ((start & mask) != (base & mask)) | |
2242 | continue; | |
2243 | ||
2244 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2245 | if (prev_match == 0xFF) { | |
2246 | prev_match = curr_match; | |
2247 | continue; | |
2248 | } | |
2249 | ||
2250 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2251 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2252 | return MTRR_TYPE_UNCACHABLE; | |
2253 | ||
2254 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2255 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2256 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2257 | curr_match == MTRR_TYPE_WRBACK)) { | |
2258 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2259 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2260 | } | |
2261 | ||
2262 | if (prev_match != curr_match) | |
2263 | return MTRR_TYPE_UNCACHABLE; | |
2264 | } | |
2265 | ||
2266 | if (prev_match != 0xFF) | |
2267 | return prev_match; | |
2268 | ||
2269 | return mtrr_state->def_type; | |
2270 | } | |
2271 | ||
4b12f0de | 2272 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2273 | { |
2274 | u8 mtrr; | |
2275 | ||
2276 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2277 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2278 | if (mtrr == 0xfe || mtrr == 0xff) | |
2279 | mtrr = MTRR_TYPE_WRBACK; | |
2280 | return mtrr; | |
2281 | } | |
4b12f0de | 2282 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2283 | |
9cf5cf5a XG |
2284 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2285 | { | |
2286 | trace_kvm_mmu_unsync_page(sp); | |
2287 | ++vcpu->kvm->stat.mmu_unsync; | |
2288 | sp->unsync = 1; | |
2289 | ||
2290 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2291 | } |
2292 | ||
2293 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2294 | { |
4731d4c7 | 2295 | struct kvm_mmu_page *s; |
9cf5cf5a | 2296 | |
b67bfe0d | 2297 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2298 | if (s->unsync) |
4731d4c7 | 2299 | continue; |
9cf5cf5a XG |
2300 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2301 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2302 | } |
4731d4c7 MT |
2303 | } |
2304 | ||
2305 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2306 | bool can_unsync) | |
2307 | { | |
9cf5cf5a | 2308 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2309 | bool need_unsync = false; |
2310 | ||
b67bfe0d | 2311 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2312 | if (!can_unsync) |
2313 | return 1; | |
2314 | ||
9cf5cf5a | 2315 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2316 | return 1; |
9cf5cf5a | 2317 | |
9bb4f6b1 | 2318 | if (!s->unsync) |
9cf5cf5a | 2319 | need_unsync = true; |
4731d4c7 | 2320 | } |
9cf5cf5a XG |
2321 | if (need_unsync) |
2322 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2323 | return 0; |
2324 | } | |
2325 | ||
d555c333 | 2326 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2327 | unsigned pte_access, int level, |
c2d0ee46 | 2328 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2329 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2330 | { |
6e7d0354 | 2331 | u64 spte; |
1e73f9dd | 2332 | int ret = 0; |
64d4d521 | 2333 | |
ce88decf XG |
2334 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2335 | return 0; | |
2336 | ||
982c2565 | 2337 | spte = PT_PRESENT_MASK; |
947da538 | 2338 | if (!speculative) |
3201b5d9 | 2339 | spte |= shadow_accessed_mask; |
640d9b0d | 2340 | |
7b52345e SY |
2341 | if (pte_access & ACC_EXEC_MASK) |
2342 | spte |= shadow_x_mask; | |
2343 | else | |
2344 | spte |= shadow_nx_mask; | |
49fde340 | 2345 | |
1c4f1fd6 | 2346 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2347 | spte |= shadow_user_mask; |
49fde340 | 2348 | |
852e3c19 | 2349 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2350 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2351 | if (tdp_enabled) |
4b12f0de SY |
2352 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2353 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2354 | |
9bdbba13 | 2355 | if (host_writable) |
1403283a | 2356 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2357 | else |
2358 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2359 | |
35149e21 | 2360 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2361 | |
c2288505 | 2362 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2363 | |
c2193463 | 2364 | /* |
7751babd XG |
2365 | * Other vcpu creates new sp in the window between |
2366 | * mapping_level() and acquiring mmu-lock. We can | |
2367 | * allow guest to retry the access, the mapping can | |
2368 | * be fixed if guest refault. | |
c2193463 | 2369 | */ |
852e3c19 | 2370 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2371 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2372 | goto done; |
38187c83 | 2373 | |
49fde340 | 2374 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2375 | |
ecc5589f MT |
2376 | /* |
2377 | * Optimization: for pte sync, if spte was writable the hash | |
2378 | * lookup is unnecessary (and expensive). Write protection | |
2379 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2380 | * Same reasoning can be applied to dirty page accounting. | |
2381 | */ | |
8dae4445 | 2382 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2383 | goto set_pte; |
2384 | ||
4731d4c7 | 2385 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2386 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2387 | __func__, gfn); |
1e73f9dd | 2388 | ret = 1; |
1c4f1fd6 | 2389 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2390 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2391 | } |
2392 | } | |
2393 | ||
1c4f1fd6 AK |
2394 | if (pte_access & ACC_WRITE_MASK) |
2395 | mark_page_dirty(vcpu->kvm, gfn); | |
2396 | ||
38187c83 | 2397 | set_pte: |
6e7d0354 | 2398 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2399 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2400 | done: |
1e73f9dd MT |
2401 | return ret; |
2402 | } | |
2403 | ||
d555c333 | 2404 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2405 | unsigned pte_access, int write_fault, int *emulate, |
2406 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2407 | bool host_writable) | |
1e73f9dd MT |
2408 | { |
2409 | int was_rmapped = 0; | |
53a27b39 | 2410 | int rmap_count; |
1e73f9dd | 2411 | |
f7616203 XG |
2412 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2413 | *sptep, write_fault, gfn); | |
1e73f9dd | 2414 | |
d555c333 | 2415 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2416 | /* |
2417 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2418 | * the parent of the now unreachable PTE. | |
2419 | */ | |
852e3c19 JR |
2420 | if (level > PT_PAGE_TABLE_LEVEL && |
2421 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2422 | struct kvm_mmu_page *child; |
d555c333 | 2423 | u64 pte = *sptep; |
1e73f9dd MT |
2424 | |
2425 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2426 | drop_parent_pte(child, sptep); |
3be2264b | 2427 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2428 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2429 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2430 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2431 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2432 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2433 | } else |
2434 | was_rmapped = 1; | |
1e73f9dd | 2435 | } |
852e3c19 | 2436 | |
c2288505 XG |
2437 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2438 | true, host_writable)) { | |
1e73f9dd | 2439 | if (write_fault) |
b90a0e6c | 2440 | *emulate = 1; |
5304efde | 2441 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2442 | } |
1e73f9dd | 2443 | |
ce88decf XG |
2444 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2445 | *emulate = 1; | |
2446 | ||
d555c333 | 2447 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2448 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2449 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2450 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2451 | *sptep, sptep); | |
d555c333 | 2452 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2453 | ++vcpu->kvm->stat.lpages; |
2454 | ||
ffb61bb3 | 2455 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2456 | if (!was_rmapped) { |
2457 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2458 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2459 | rmap_recycle(vcpu, sptep, gfn); | |
2460 | } | |
1c4f1fd6 | 2461 | } |
cb9aaa30 | 2462 | |
f3ac1a4b | 2463 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2464 | } |
2465 | ||
6aa8b732 AK |
2466 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2467 | { | |
e676505a | 2468 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2469 | } |
2470 | ||
a052b42b XG |
2471 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2472 | { | |
2473 | int bit7; | |
2474 | ||
2475 | bit7 = (gpte >> 7) & 1; | |
2476 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2477 | } | |
2478 | ||
957ed9ef XG |
2479 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2480 | bool no_dirty_log) | |
2481 | { | |
2482 | struct kvm_memory_slot *slot; | |
957ed9ef | 2483 | |
5d163b1c | 2484 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2485 | if (!slot) |
6c8ee57b | 2486 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2487 | |
037d92dc | 2488 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2489 | } |
2490 | ||
a052b42b XG |
2491 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2492 | struct kvm_mmu_page *sp, u64 *spte, | |
2493 | u64 gpte) | |
2494 | { | |
2495 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2496 | goto no_present; | |
2497 | ||
2498 | if (!is_present_gpte(gpte)) | |
2499 | goto no_present; | |
2500 | ||
2501 | if (!(gpte & PT_ACCESSED_MASK)) | |
2502 | goto no_present; | |
2503 | ||
2504 | return false; | |
2505 | ||
2506 | no_present: | |
2507 | drop_spte(vcpu->kvm, spte); | |
2508 | return true; | |
2509 | } | |
2510 | ||
957ed9ef XG |
2511 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2512 | struct kvm_mmu_page *sp, | |
2513 | u64 *start, u64 *end) | |
2514 | { | |
2515 | struct page *pages[PTE_PREFETCH_NUM]; | |
2516 | unsigned access = sp->role.access; | |
2517 | int i, ret; | |
2518 | gfn_t gfn; | |
2519 | ||
2520 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2521 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2522 | return -1; |
2523 | ||
2524 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2525 | if (ret <= 0) | |
2526 | return -1; | |
2527 | ||
2528 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2529 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2530 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2531 | true, true); | |
957ed9ef XG |
2532 | |
2533 | return 0; | |
2534 | } | |
2535 | ||
2536 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2537 | struct kvm_mmu_page *sp, u64 *sptep) | |
2538 | { | |
2539 | u64 *spte, *start = NULL; | |
2540 | int i; | |
2541 | ||
2542 | WARN_ON(!sp->role.direct); | |
2543 | ||
2544 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2545 | spte = sp->spt + i; | |
2546 | ||
2547 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2548 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2549 | if (!start) |
2550 | continue; | |
2551 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2552 | break; | |
2553 | start = NULL; | |
2554 | } else if (!start) | |
2555 | start = spte; | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2560 | { | |
2561 | struct kvm_mmu_page *sp; | |
2562 | ||
2563 | /* | |
2564 | * Since it's no accessed bit on EPT, it's no way to | |
2565 | * distinguish between actually accessed translations | |
2566 | * and prefetched, so disable pte prefetch if EPT is | |
2567 | * enabled. | |
2568 | */ | |
2569 | if (!shadow_accessed_mask) | |
2570 | return; | |
2571 | ||
2572 | sp = page_header(__pa(sptep)); | |
2573 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2574 | return; | |
2575 | ||
2576 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2577 | } | |
2578 | ||
9f652d21 | 2579 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2580 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2581 | bool prefault) | |
140754bc | 2582 | { |
9f652d21 | 2583 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2584 | struct kvm_mmu_page *sp; |
b90a0e6c | 2585 | int emulate = 0; |
140754bc | 2586 | gfn_t pseudo_gfn; |
6aa8b732 | 2587 | |
9f652d21 | 2588 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2589 | if (iterator.level == level) { |
f7616203 | 2590 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2591 | write, &emulate, level, gfn, pfn, |
2592 | prefault, map_writable); | |
957ed9ef | 2593 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2594 | ++vcpu->stat.pf_fixed; |
2595 | break; | |
6aa8b732 AK |
2596 | } |
2597 | ||
c3707958 | 2598 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2599 | u64 base_addr = iterator.addr; |
2600 | ||
2601 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2602 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2603 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2604 | iterator.level - 1, | |
2605 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2606 | |
24db2734 | 2607 | link_shadow_page(iterator.sptep, sp); |
9f652d21 AK |
2608 | } |
2609 | } | |
b90a0e6c | 2610 | return emulate; |
6aa8b732 AK |
2611 | } |
2612 | ||
77db5cbd | 2613 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2614 | { |
77db5cbd HY |
2615 | siginfo_t info; |
2616 | ||
2617 | info.si_signo = SIGBUS; | |
2618 | info.si_errno = 0; | |
2619 | info.si_code = BUS_MCEERR_AR; | |
2620 | info.si_addr = (void __user *)address; | |
2621 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2622 | |
77db5cbd | 2623 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2624 | } |
2625 | ||
d7c55201 | 2626 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2627 | { |
4d8b81ab XG |
2628 | /* |
2629 | * Do not cache the mmio info caused by writing the readonly gfn | |
2630 | * into the spte otherwise read access on readonly gfn also can | |
2631 | * caused mmio page fault and treat it as mmio access. | |
2632 | * Return 1 to tell kvm to emulate it. | |
2633 | */ | |
2634 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2635 | return 1; | |
2636 | ||
e6c1502b | 2637 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2638 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2639 | return 0; |
d7c55201 | 2640 | } |
edba23e5 | 2641 | |
d7c55201 | 2642 | return -EFAULT; |
bf998156 HY |
2643 | } |
2644 | ||
936a5fe6 AA |
2645 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2646 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2647 | { | |
2648 | pfn_t pfn = *pfnp; | |
2649 | gfn_t gfn = *gfnp; | |
2650 | int level = *levelp; | |
2651 | ||
2652 | /* | |
2653 | * Check if it's a transparent hugepage. If this would be an | |
2654 | * hugetlbfs page, level wouldn't be set to | |
2655 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2656 | * here. | |
2657 | */ | |
81c52c56 | 2658 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2659 | level == PT_PAGE_TABLE_LEVEL && |
2660 | PageTransCompound(pfn_to_page(pfn)) && | |
2661 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2662 | unsigned long mask; | |
2663 | /* | |
2664 | * mmu_notifier_retry was successful and we hold the | |
2665 | * mmu_lock here, so the pmd can't become splitting | |
2666 | * from under us, and in turn | |
2667 | * __split_huge_page_refcount() can't run from under | |
2668 | * us and we can safely transfer the refcount from | |
2669 | * PG_tail to PG_head as we switch the pfn to tail to | |
2670 | * head. | |
2671 | */ | |
2672 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2673 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2674 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2675 | if (pfn & mask) { | |
2676 | gfn &= ~mask; | |
2677 | *gfnp = gfn; | |
2678 | kvm_release_pfn_clean(pfn); | |
2679 | pfn &= ~mask; | |
c3586667 | 2680 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2681 | *pfnp = pfn; |
2682 | } | |
2683 | } | |
2684 | } | |
2685 | ||
d7c55201 XG |
2686 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2687 | pfn_t pfn, unsigned access, int *ret_val) | |
2688 | { | |
2689 | bool ret = true; | |
2690 | ||
2691 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2692 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2693 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2694 | goto exit; | |
2695 | } | |
2696 | ||
ce88decf | 2697 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2698 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2699 | |
2700 | ret = false; | |
2701 | exit: | |
2702 | return ret; | |
2703 | } | |
2704 | ||
c7ba5b48 XG |
2705 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2706 | { | |
2707 | /* | |
2708 | * #PF can be fast only if the shadow page table is present and it | |
2709 | * is caused by write-protect, that means we just need change the | |
2710 | * W bit of the spte which can be done out of mmu-lock. | |
2711 | */ | |
2712 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2713 | !(error_code & PFERR_WRITE_MASK)) | |
2714 | return false; | |
2715 | ||
2716 | return true; | |
2717 | } | |
2718 | ||
2719 | static bool | |
2720 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2721 | { | |
2722 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2723 | gfn_t gfn; | |
2724 | ||
2725 | WARN_ON(!sp->role.direct); | |
2726 | ||
2727 | /* | |
2728 | * The gfn of direct spte is stable since it is calculated | |
2729 | * by sp->gfn. | |
2730 | */ | |
2731 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2732 | ||
2733 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2734 | mark_page_dirty(vcpu->kvm, gfn); | |
2735 | ||
2736 | return true; | |
2737 | } | |
2738 | ||
2739 | /* | |
2740 | * Return value: | |
2741 | * - true: let the vcpu to access on the same address again. | |
2742 | * - false: let the real page fault path to fix it. | |
2743 | */ | |
2744 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2745 | u32 error_code) | |
2746 | { | |
2747 | struct kvm_shadow_walk_iterator iterator; | |
2748 | bool ret = false; | |
2749 | u64 spte = 0ull; | |
2750 | ||
2751 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2752 | return false; | |
2753 | ||
2754 | walk_shadow_page_lockless_begin(vcpu); | |
2755 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2756 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2757 | break; | |
2758 | ||
2759 | /* | |
2760 | * If the mapping has been changed, let the vcpu fault on the | |
2761 | * same address again. | |
2762 | */ | |
2763 | if (!is_rmap_spte(spte)) { | |
2764 | ret = true; | |
2765 | goto exit; | |
2766 | } | |
2767 | ||
2768 | if (!is_last_spte(spte, level)) | |
2769 | goto exit; | |
2770 | ||
2771 | /* | |
2772 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2773 | * | |
2774 | * Need not check the access of upper level table entries since | |
2775 | * they are always ACC_ALL. | |
2776 | */ | |
2777 | if (is_writable_pte(spte)) { | |
2778 | ret = true; | |
2779 | goto exit; | |
2780 | } | |
2781 | ||
2782 | /* | |
2783 | * Currently, to simplify the code, only the spte write-protected | |
2784 | * by dirty-log can be fast fixed. | |
2785 | */ | |
2786 | if (!spte_is_locklessly_modifiable(spte)) | |
2787 | goto exit; | |
2788 | ||
2789 | /* | |
2790 | * Currently, fast page fault only works for direct mapping since | |
2791 | * the gfn is not stable for indirect shadow page. | |
2792 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2793 | */ | |
2794 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2795 | exit: | |
a72faf25 XG |
2796 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2797 | spte, ret); | |
c7ba5b48 XG |
2798 | walk_shadow_page_lockless_end(vcpu); |
2799 | ||
2800 | return ret; | |
2801 | } | |
2802 | ||
78b2c54a | 2803 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 2804 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2805 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2806 | |
c7ba5b48 XG |
2807 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2808 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2809 | { |
2810 | int r; | |
852e3c19 | 2811 | int level; |
936a5fe6 | 2812 | int force_pt_level; |
35149e21 | 2813 | pfn_t pfn; |
e930bffe | 2814 | unsigned long mmu_seq; |
c7ba5b48 | 2815 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2816 | |
936a5fe6 AA |
2817 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2818 | if (likely(!force_pt_level)) { | |
2819 | level = mapping_level(vcpu, gfn); | |
2820 | /* | |
2821 | * This path builds a PAE pagetable - so we can map | |
2822 | * 2mb pages at maximum. Therefore check if the level | |
2823 | * is larger than that. | |
2824 | */ | |
2825 | if (level > PT_DIRECTORY_LEVEL) | |
2826 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2827 | |
936a5fe6 AA |
2828 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2829 | } else | |
2830 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2831 | |
c7ba5b48 XG |
2832 | if (fast_page_fault(vcpu, v, level, error_code)) |
2833 | return 0; | |
2834 | ||
e930bffe | 2835 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2836 | smp_rmb(); |
060c2abe | 2837 | |
78b2c54a | 2838 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2839 | return 0; |
aaee2c94 | 2840 | |
d7c55201 XG |
2841 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2842 | return r; | |
d196e343 | 2843 | |
aaee2c94 | 2844 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2845 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2846 | goto out_unlock; |
450e0b41 | 2847 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
2848 | if (likely(!force_pt_level)) |
2849 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2850 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2851 | prefault); | |
aaee2c94 MT |
2852 | spin_unlock(&vcpu->kvm->mmu_lock); |
2853 | ||
aaee2c94 | 2854 | |
10589a46 | 2855 | return r; |
e930bffe AA |
2856 | |
2857 | out_unlock: | |
2858 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2859 | kvm_release_pfn_clean(pfn); | |
2860 | return 0; | |
10589a46 MT |
2861 | } |
2862 | ||
2863 | ||
17ac10ad AK |
2864 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2865 | { | |
2866 | int i; | |
4db35314 | 2867 | struct kvm_mmu_page *sp; |
d98ba053 | 2868 | LIST_HEAD(invalid_list); |
17ac10ad | 2869 | |
ad312c7c | 2870 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2871 | return; |
aaee2c94 | 2872 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2873 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2874 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2875 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2876 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2877 | |
4db35314 AK |
2878 | sp = page_header(root); |
2879 | --sp->root_count; | |
d98ba053 XG |
2880 | if (!sp->root_count && sp->role.invalid) { |
2881 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2882 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2883 | } | |
ad312c7c | 2884 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2885 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2886 | return; |
2887 | } | |
17ac10ad | 2888 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2889 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2890 | |
417726a3 | 2891 | if (root) { |
417726a3 | 2892 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2893 | sp = page_header(root); |
2894 | --sp->root_count; | |
2e53d63a | 2895 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2896 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2897 | &invalid_list); | |
417726a3 | 2898 | } |
ad312c7c | 2899 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2900 | } |
d98ba053 | 2901 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2902 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2903 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2904 | } |
2905 | ||
8986ecc0 MT |
2906 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2907 | { | |
2908 | int ret = 0; | |
2909 | ||
2910 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2911 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2912 | ret = 1; |
2913 | } | |
2914 | ||
2915 | return ret; | |
2916 | } | |
2917 | ||
651dd37a JR |
2918 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2919 | { | |
2920 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2921 | unsigned i; |
651dd37a JR |
2922 | |
2923 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2924 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 2925 | make_mmu_pages_available(vcpu); |
651dd37a JR |
2926 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
2927 | 1, ACC_ALL, NULL); | |
2928 | ++sp->root_count; | |
2929 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2930 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2931 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2932 | for (i = 0; i < 4; ++i) { | |
2933 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2934 | ||
2935 | ASSERT(!VALID_PAGE(root)); | |
2936 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 2937 | make_mmu_pages_available(vcpu); |
649497d1 AK |
2938 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2939 | i << 30, | |
651dd37a JR |
2940 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2941 | NULL); | |
2942 | root = __pa(sp->spt); | |
2943 | ++sp->root_count; | |
2944 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2945 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2946 | } |
6292757f | 2947 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2948 | } else |
2949 | BUG(); | |
2950 | ||
2951 | return 0; | |
2952 | } | |
2953 | ||
2954 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2955 | { |
4db35314 | 2956 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2957 | u64 pdptr, pm_mask; |
2958 | gfn_t root_gfn; | |
2959 | int i; | |
3bb65a22 | 2960 | |
5777ed34 | 2961 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2962 | |
651dd37a JR |
2963 | if (mmu_check_root(vcpu, root_gfn)) |
2964 | return 1; | |
2965 | ||
2966 | /* | |
2967 | * Do we shadow a long mode page table? If so we need to | |
2968 | * write-protect the guests page table root. | |
2969 | */ | |
2970 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2971 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2972 | |
2973 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2974 | |
8facbbff | 2975 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 2976 | make_mmu_pages_available(vcpu); |
651dd37a JR |
2977 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2978 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2979 | root = __pa(sp->spt); |
2980 | ++sp->root_count; | |
8facbbff | 2981 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2982 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2983 | return 0; |
17ac10ad | 2984 | } |
f87f9288 | 2985 | |
651dd37a JR |
2986 | /* |
2987 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2988 | * or a PAE 3-level page table. In either case we need to be aware that |
2989 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2990 | */ |
81407ca5 JR |
2991 | pm_mask = PT_PRESENT_MASK; |
2992 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2993 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2994 | ||
17ac10ad | 2995 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2996 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2997 | |
2998 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2999 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3000 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3001 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3002 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3003 | continue; |
3004 | } | |
6de4f3ad | 3005 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3006 | if (mmu_check_root(vcpu, root_gfn)) |
3007 | return 1; | |
5a7388c2 | 3008 | } |
8facbbff | 3009 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3010 | make_mmu_pages_available(vcpu); |
4db35314 | 3011 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3012 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3013 | ACC_ALL, NULL); |
4db35314 AK |
3014 | root = __pa(sp->spt); |
3015 | ++sp->root_count; | |
8facbbff AK |
3016 | spin_unlock(&vcpu->kvm->mmu_lock); |
3017 | ||
81407ca5 | 3018 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3019 | } |
6292757f | 3020 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3021 | |
3022 | /* | |
3023 | * If we shadow a 32 bit page table with a long mode page | |
3024 | * table we enter this path. | |
3025 | */ | |
3026 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3027 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3028 | /* | |
3029 | * The additional page necessary for this is only | |
3030 | * allocated on demand. | |
3031 | */ | |
3032 | ||
3033 | u64 *lm_root; | |
3034 | ||
3035 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3036 | if (lm_root == NULL) | |
3037 | return 1; | |
3038 | ||
3039 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3040 | ||
3041 | vcpu->arch.mmu.lm_root = lm_root; | |
3042 | } | |
3043 | ||
3044 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3045 | } | |
3046 | ||
8986ecc0 | 3047 | return 0; |
17ac10ad AK |
3048 | } |
3049 | ||
651dd37a JR |
3050 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3051 | { | |
3052 | if (vcpu->arch.mmu.direct_map) | |
3053 | return mmu_alloc_direct_roots(vcpu); | |
3054 | else | |
3055 | return mmu_alloc_shadow_roots(vcpu); | |
3056 | } | |
3057 | ||
0ba73cda MT |
3058 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3059 | { | |
3060 | int i; | |
3061 | struct kvm_mmu_page *sp; | |
3062 | ||
81407ca5 JR |
3063 | if (vcpu->arch.mmu.direct_map) |
3064 | return; | |
3065 | ||
0ba73cda MT |
3066 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3067 | return; | |
6903074c | 3068 | |
bebb106a | 3069 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3070 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3071 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3072 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3073 | sp = page_header(root); | |
3074 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3075 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3076 | return; |
3077 | } | |
3078 | for (i = 0; i < 4; ++i) { | |
3079 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3080 | ||
8986ecc0 | 3081 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3082 | root &= PT64_BASE_ADDR_MASK; |
3083 | sp = page_header(root); | |
3084 | mmu_sync_children(vcpu, sp); | |
3085 | } | |
3086 | } | |
0375f7fa | 3087 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3088 | } |
3089 | ||
3090 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3091 | { | |
3092 | spin_lock(&vcpu->kvm->mmu_lock); | |
3093 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3094 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3095 | } |
3096 | ||
1871c602 | 3097 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3098 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3099 | { |
ab9ae313 AK |
3100 | if (exception) |
3101 | exception->error_code = 0; | |
6aa8b732 AK |
3102 | return vaddr; |
3103 | } | |
3104 | ||
6539e738 | 3105 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3106 | u32 access, |
3107 | struct x86_exception *exception) | |
6539e738 | 3108 | { |
ab9ae313 AK |
3109 | if (exception) |
3110 | exception->error_code = 0; | |
6539e738 JR |
3111 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3112 | } | |
3113 | ||
ce88decf XG |
3114 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3115 | { | |
3116 | if (direct) | |
3117 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3118 | ||
3119 | return vcpu_match_mmio_gva(vcpu, addr); | |
3120 | } | |
3121 | ||
3122 | ||
3123 | /* | |
3124 | * On direct hosts, the last spte is only allows two states | |
3125 | * for mmio page fault: | |
3126 | * - It is the mmio spte | |
3127 | * - It is zapped or it is being zapped. | |
3128 | * | |
3129 | * This function completely checks the spte when the last spte | |
3130 | * is not the mmio spte. | |
3131 | */ | |
3132 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3133 | { | |
3134 | return __check_direct_spte_mmio_pf(spte); | |
3135 | } | |
3136 | ||
3137 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3138 | { | |
3139 | struct kvm_shadow_walk_iterator iterator; | |
3140 | u64 spte = 0ull; | |
3141 | ||
3142 | walk_shadow_page_lockless_begin(vcpu); | |
3143 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3144 | if (!is_shadow_present_pte(spte)) | |
3145 | break; | |
3146 | walk_shadow_page_lockless_end(vcpu); | |
3147 | ||
3148 | return spte; | |
3149 | } | |
3150 | ||
3151 | /* | |
3152 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
3153 | * directly, return 0 to let CPU fault again on the address, -1 is | |
3154 | * returned if bug is detected. | |
3155 | */ | |
3156 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
3157 | { | |
3158 | u64 spte; | |
3159 | ||
3160 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
3161 | return 1; | |
3162 | ||
3163 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3164 | ||
3165 | if (is_mmio_spte(spte)) { | |
3166 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3167 | unsigned access = get_mmio_spte_access(spte); | |
3168 | ||
3169 | if (direct) | |
3170 | addr = 0; | |
4f022648 XG |
3171 | |
3172 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3173 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3174 | return 1; | |
3175 | } | |
3176 | ||
3177 | /* | |
3178 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3179 | * it's a BUG if the gfn is not a mmio page. | |
3180 | */ | |
3181 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3182 | return -1; | |
3183 | ||
3184 | /* | |
3185 | * If the page table is zapped by other cpus, let CPU fault again on | |
3186 | * the address. | |
3187 | */ | |
3188 | return 0; | |
3189 | } | |
3190 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3191 | ||
3192 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3193 | u32 error_code, bool direct) | |
3194 | { | |
3195 | int ret; | |
3196 | ||
3197 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3198 | WARN_ON(ret < 0); | |
3199 | return ret; | |
3200 | } | |
3201 | ||
6aa8b732 | 3202 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3203 | u32 error_code, bool prefault) |
6aa8b732 | 3204 | { |
e833240f | 3205 | gfn_t gfn; |
e2dec939 | 3206 | int r; |
6aa8b732 | 3207 | |
b8688d51 | 3208 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3209 | |
3210 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3211 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3212 | ||
e2dec939 AK |
3213 | r = mmu_topup_memory_caches(vcpu); |
3214 | if (r) | |
3215 | return r; | |
714b93da | 3216 | |
6aa8b732 | 3217 | ASSERT(vcpu); |
ad312c7c | 3218 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3219 | |
e833240f | 3220 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3221 | |
e833240f | 3222 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3223 | error_code, gfn, prefault); |
6aa8b732 AK |
3224 | } |
3225 | ||
7e1fbeac | 3226 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3227 | { |
3228 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3229 | |
7c90705b | 3230 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3231 | arch.gfn = gfn; |
c4806acd | 3232 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3233 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3234 | |
3235 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3236 | } | |
3237 | ||
3238 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3239 | { | |
3240 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3241 | kvm_event_needs_reinjection(vcpu))) | |
3242 | return false; | |
3243 | ||
3244 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3245 | } | |
3246 | ||
78b2c54a | 3247 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3248 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3249 | { |
3250 | bool async; | |
3251 | ||
612819c3 | 3252 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3253 | |
3254 | if (!async) | |
3255 | return false; /* *pfn has correct page already */ | |
3256 | ||
78b2c54a | 3257 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3258 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3259 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3260 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3261 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3262 | return true; | |
3263 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3264 | return true; | |
3265 | } | |
3266 | ||
612819c3 | 3267 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3268 | |
3269 | return false; | |
3270 | } | |
3271 | ||
56028d08 | 3272 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3273 | bool prefault) |
fb72d167 | 3274 | { |
35149e21 | 3275 | pfn_t pfn; |
fb72d167 | 3276 | int r; |
852e3c19 | 3277 | int level; |
936a5fe6 | 3278 | int force_pt_level; |
05da4558 | 3279 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3280 | unsigned long mmu_seq; |
612819c3 MT |
3281 | int write = error_code & PFERR_WRITE_MASK; |
3282 | bool map_writable; | |
fb72d167 JR |
3283 | |
3284 | ASSERT(vcpu); | |
3285 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3286 | ||
ce88decf XG |
3287 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3288 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3289 | ||
fb72d167 JR |
3290 | r = mmu_topup_memory_caches(vcpu); |
3291 | if (r) | |
3292 | return r; | |
3293 | ||
936a5fe6 AA |
3294 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3295 | if (likely(!force_pt_level)) { | |
3296 | level = mapping_level(vcpu, gfn); | |
3297 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3298 | } else | |
3299 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3300 | |
c7ba5b48 XG |
3301 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3302 | return 0; | |
3303 | ||
e930bffe | 3304 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3305 | smp_rmb(); |
af585b92 | 3306 | |
78b2c54a | 3307 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3308 | return 0; |
3309 | ||
d7c55201 XG |
3310 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3311 | return r; | |
3312 | ||
fb72d167 | 3313 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3314 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3315 | goto out_unlock; |
450e0b41 | 3316 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3317 | if (likely(!force_pt_level)) |
3318 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3319 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3320 | level, gfn, pfn, prefault); |
fb72d167 | 3321 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3322 | |
3323 | return r; | |
e930bffe AA |
3324 | |
3325 | out_unlock: | |
3326 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3327 | kvm_release_pfn_clean(pfn); | |
3328 | return 0; | |
fb72d167 JR |
3329 | } |
3330 | ||
6aa8b732 AK |
3331 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3332 | { | |
17ac10ad | 3333 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3334 | } |
3335 | ||
52fde8df JR |
3336 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3337 | struct kvm_mmu *context) | |
6aa8b732 | 3338 | { |
6aa8b732 AK |
3339 | context->new_cr3 = nonpaging_new_cr3; |
3340 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3341 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3342 | context->free = nonpaging_free; | |
e8bc217a | 3343 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3344 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3345 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3346 | context->root_level = 0; |
6aa8b732 | 3347 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3348 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3349 | context->direct_map = true; |
2d48a985 | 3350 | context->nx = false; |
6aa8b732 AK |
3351 | return 0; |
3352 | } | |
3353 | ||
d835dfec | 3354 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3355 | { |
1165f5fe | 3356 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3357 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3358 | } |
3359 | ||
3360 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3361 | { | |
9f8fe504 | 3362 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3363 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3364 | } |
3365 | ||
5777ed34 JR |
3366 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3367 | { | |
9f8fe504 | 3368 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3369 | } |
3370 | ||
6389ee94 AK |
3371 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3372 | struct x86_exception *fault) | |
6aa8b732 | 3373 | { |
6389ee94 | 3374 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3375 | } |
3376 | ||
6aa8b732 AK |
3377 | static void paging_free(struct kvm_vcpu *vcpu) |
3378 | { | |
3379 | nonpaging_free(vcpu); | |
3380 | } | |
3381 | ||
8ea667f2 AK |
3382 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3383 | { | |
3384 | unsigned mask; | |
3385 | ||
3386 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3387 | ||
3388 | mask = (unsigned)~ACC_WRITE_MASK; | |
3389 | /* Allow write access to dirty gptes */ | |
3390 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3391 | *access &= mask; | |
3392 | } | |
3393 | ||
ce88decf XG |
3394 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3395 | int *nr_present) | |
3396 | { | |
3397 | if (unlikely(is_mmio_spte(*sptep))) { | |
3398 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3399 | mmu_spte_clear_no_track(sptep); | |
3400 | return true; | |
3401 | } | |
3402 | ||
3403 | (*nr_present)++; | |
3404 | mark_mmio_spte(sptep, gfn, access); | |
3405 | return true; | |
3406 | } | |
3407 | ||
3408 | return false; | |
3409 | } | |
3410 | ||
3d34adec AK |
3411 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3412 | { | |
3413 | unsigned access; | |
3414 | ||
3415 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3416 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3417 | ||
3418 | return access; | |
3419 | } | |
3420 | ||
6fd01b71 AK |
3421 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3422 | { | |
3423 | unsigned index; | |
3424 | ||
3425 | index = level - 1; | |
3426 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3427 | return mmu->last_pte_bitmap & (1 << index); | |
3428 | } | |
3429 | ||
6aa8b732 AK |
3430 | #define PTTYPE 64 |
3431 | #include "paging_tmpl.h" | |
3432 | #undef PTTYPE | |
3433 | ||
3434 | #define PTTYPE 32 | |
3435 | #include "paging_tmpl.h" | |
3436 | #undef PTTYPE | |
3437 | ||
52fde8df | 3438 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3439 | struct kvm_mmu *context) |
82725b20 | 3440 | { |
82725b20 DE |
3441 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3442 | u64 exb_bit_rsvd = 0; | |
3443 | ||
2d48a985 | 3444 | if (!context->nx) |
82725b20 | 3445 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3446 | switch (context->root_level) { |
82725b20 DE |
3447 | case PT32_ROOT_LEVEL: |
3448 | /* no rsvd bits for 2 level 4K page table entries */ | |
3449 | context->rsvd_bits_mask[0][1] = 0; | |
3450 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3451 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3452 | ||
3453 | if (!is_pse(vcpu)) { | |
3454 | context->rsvd_bits_mask[1][1] = 0; | |
3455 | break; | |
3456 | } | |
3457 | ||
82725b20 DE |
3458 | if (is_cpuid_PSE36()) |
3459 | /* 36bits PSE 4MB page */ | |
3460 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3461 | else | |
3462 | /* 32 bits PSE 4MB page */ | |
3463 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3464 | break; |
3465 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3466 | context->rsvd_bits_mask[0][2] = |
3467 | rsvd_bits(maxphyaddr, 63) | | |
3468 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3469 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3470 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3471 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3472 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3473 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3474 | rsvd_bits(maxphyaddr, 62) | | |
3475 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3476 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3477 | break; |
3478 | case PT64_ROOT_LEVEL: | |
3479 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3480 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3481 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3482 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3483 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3484 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3485 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3486 | rsvd_bits(maxphyaddr, 51); | |
3487 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3488 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3489 | rsvd_bits(maxphyaddr, 51) | | |
3490 | rsvd_bits(13, 29); | |
82725b20 | 3491 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3492 | rsvd_bits(maxphyaddr, 51) | |
3493 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3494 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3495 | break; |
3496 | } | |
3497 | } | |
3498 | ||
97d64b78 AK |
3499 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3500 | { | |
3501 | unsigned bit, byte, pfec; | |
3502 | u8 map; | |
3503 | bool fault, x, w, u, wf, uf, ff, smep; | |
3504 | ||
3505 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3506 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3507 | pfec = byte << 1; | |
3508 | map = 0; | |
3509 | wf = pfec & PFERR_WRITE_MASK; | |
3510 | uf = pfec & PFERR_USER_MASK; | |
3511 | ff = pfec & PFERR_FETCH_MASK; | |
3512 | for (bit = 0; bit < 8; ++bit) { | |
3513 | x = bit & ACC_EXEC_MASK; | |
3514 | w = bit & ACC_WRITE_MASK; | |
3515 | u = bit & ACC_USER_MASK; | |
3516 | ||
3517 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3518 | x |= !mmu->nx; | |
3519 | /* Allow supervisor writes if !cr0.wp */ | |
3520 | w |= !is_write_protection(vcpu) && !uf; | |
3521 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3522 | x &= !(smep && u && !uf); | |
3523 | ||
3524 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3525 | map |= fault << bit; | |
3526 | } | |
3527 | mmu->permissions[byte] = map; | |
3528 | } | |
3529 | } | |
3530 | ||
6fd01b71 AK |
3531 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3532 | { | |
3533 | u8 map; | |
3534 | unsigned level, root_level = mmu->root_level; | |
3535 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3536 | ||
3537 | if (root_level == PT32E_ROOT_LEVEL) | |
3538 | --root_level; | |
3539 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3540 | map = 1 | (1 << ps_set_index); | |
3541 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3542 | if (level <= PT_PDPE_LEVEL | |
3543 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3544 | map |= 1 << (ps_set_index | (level - 1)); | |
3545 | } | |
3546 | mmu->last_pte_bitmap = map; | |
3547 | } | |
3548 | ||
52fde8df JR |
3549 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3550 | struct kvm_mmu *context, | |
3551 | int level) | |
6aa8b732 | 3552 | { |
2d48a985 | 3553 | context->nx = is_nx(vcpu); |
4d6931c3 | 3554 | context->root_level = level; |
2d48a985 | 3555 | |
4d6931c3 | 3556 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3557 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3558 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3559 | |
3560 | ASSERT(is_pae(vcpu)); | |
3561 | context->new_cr3 = paging_new_cr3; | |
3562 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3563 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3564 | context->sync_page = paging64_sync_page; |
a7052897 | 3565 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3566 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3567 | context->free = paging_free; |
17ac10ad | 3568 | context->shadow_root_level = level; |
17c3ba9d | 3569 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3570 | context->direct_map = false; |
6aa8b732 AK |
3571 | return 0; |
3572 | } | |
3573 | ||
52fde8df JR |
3574 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3575 | struct kvm_mmu *context) | |
17ac10ad | 3576 | { |
52fde8df | 3577 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3578 | } |
3579 | ||
52fde8df JR |
3580 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3581 | struct kvm_mmu *context) | |
6aa8b732 | 3582 | { |
2d48a985 | 3583 | context->nx = false; |
4d6931c3 | 3584 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3585 | |
4d6931c3 | 3586 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3587 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3588 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3589 | |
3590 | context->new_cr3 = paging_new_cr3; | |
3591 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3592 | context->gva_to_gpa = paging32_gva_to_gpa; |
3593 | context->free = paging_free; | |
e8bc217a | 3594 | context->sync_page = paging32_sync_page; |
a7052897 | 3595 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3596 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3597 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3598 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3599 | context->direct_map = false; |
6aa8b732 AK |
3600 | return 0; |
3601 | } | |
3602 | ||
52fde8df JR |
3603 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3604 | struct kvm_mmu *context) | |
6aa8b732 | 3605 | { |
52fde8df | 3606 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3607 | } |
3608 | ||
fb72d167 JR |
3609 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3610 | { | |
14dfe855 | 3611 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3612 | |
c445f8ef | 3613 | context->base_role.word = 0; |
fb72d167 JR |
3614 | context->new_cr3 = nonpaging_new_cr3; |
3615 | context->page_fault = tdp_page_fault; | |
3616 | context->free = nonpaging_free; | |
e8bc217a | 3617 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3618 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3619 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3620 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3621 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3622 | context->direct_map = true; |
1c97f0a0 | 3623 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3624 | context->get_cr3 = get_cr3; |
e4e517b4 | 3625 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3626 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3627 | |
3628 | if (!is_paging(vcpu)) { | |
2d48a985 | 3629 | context->nx = false; |
fb72d167 JR |
3630 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3631 | context->root_level = 0; | |
3632 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3633 | context->nx = is_nx(vcpu); |
fb72d167 | 3634 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3635 | reset_rsvds_bits_mask(vcpu, context); |
3636 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3637 | } else if (is_pae(vcpu)) { |
2d48a985 | 3638 | context->nx = is_nx(vcpu); |
fb72d167 | 3639 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3640 | reset_rsvds_bits_mask(vcpu, context); |
3641 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3642 | } else { |
2d48a985 | 3643 | context->nx = false; |
fb72d167 | 3644 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3645 | reset_rsvds_bits_mask(vcpu, context); |
3646 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3647 | } |
3648 | ||
97d64b78 | 3649 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3650 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3651 | |
fb72d167 JR |
3652 | return 0; |
3653 | } | |
3654 | ||
52fde8df | 3655 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3656 | { |
a770f6f2 | 3657 | int r; |
411c588d | 3658 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3659 | ASSERT(vcpu); |
ad312c7c | 3660 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3661 | |
3662 | if (!is_paging(vcpu)) | |
52fde8df | 3663 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3664 | else if (is_long_mode(vcpu)) |
52fde8df | 3665 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3666 | else if (is_pae(vcpu)) |
52fde8df | 3667 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3668 | else |
52fde8df | 3669 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3670 | |
2c9afa52 | 3671 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3672 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3673 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3674 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3675 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3676 | |
3677 | return r; | |
3678 | } | |
3679 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3680 | ||
3681 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3682 | { | |
14dfe855 | 3683 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3684 | |
14dfe855 JR |
3685 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3686 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3687 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3688 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3689 | |
3690 | return r; | |
6aa8b732 AK |
3691 | } |
3692 | ||
02f59dc9 JR |
3693 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3694 | { | |
3695 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3696 | ||
3697 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3698 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3699 | g_context->inject_page_fault = kvm_inject_page_fault; |
3700 | ||
3701 | /* | |
3702 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3703 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3704 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3705 | * functions between mmu and nested_mmu are swapped. | |
3706 | */ | |
3707 | if (!is_paging(vcpu)) { | |
2d48a985 | 3708 | g_context->nx = false; |
02f59dc9 JR |
3709 | g_context->root_level = 0; |
3710 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3711 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3712 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3713 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3714 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3715 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3716 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3717 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3718 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3719 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3720 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3721 | } else { | |
2d48a985 | 3722 | g_context->nx = false; |
02f59dc9 | 3723 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3724 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3725 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3726 | } | |
3727 | ||
97d64b78 | 3728 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3729 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3730 | |
02f59dc9 JR |
3731 | return 0; |
3732 | } | |
3733 | ||
fb72d167 JR |
3734 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3735 | { | |
02f59dc9 JR |
3736 | if (mmu_is_nested(vcpu)) |
3737 | return init_kvm_nested_mmu(vcpu); | |
3738 | else if (tdp_enabled) | |
fb72d167 JR |
3739 | return init_kvm_tdp_mmu(vcpu); |
3740 | else | |
3741 | return init_kvm_softmmu(vcpu); | |
3742 | } | |
3743 | ||
6aa8b732 AK |
3744 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3745 | { | |
3746 | ASSERT(vcpu); | |
62ad0755 SY |
3747 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3748 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3749 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3750 | } |
3751 | ||
3752 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3753 | { |
3754 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3755 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3756 | } |
8668a3c4 | 3757 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3758 | |
3759 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3760 | { |
714b93da AK |
3761 | int r; |
3762 | ||
e2dec939 | 3763 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3764 | if (r) |
3765 | goto out; | |
8986ecc0 | 3766 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 3767 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
3768 | if (r) |
3769 | goto out; | |
3662cb1c | 3770 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3771 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3772 | out: |
3773 | return r; | |
6aa8b732 | 3774 | } |
17c3ba9d AK |
3775 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3776 | ||
3777 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3778 | { | |
3779 | mmu_free_roots(vcpu); | |
3780 | } | |
4b16184c | 3781 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3782 | |
0028425f | 3783 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3784 | struct kvm_mmu_page *sp, u64 *spte, |
3785 | const void *new) | |
0028425f | 3786 | { |
30945387 | 3787 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3788 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3789 | return; | |
30945387 | 3790 | } |
0028425f | 3791 | |
4cee5764 | 3792 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3793 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3794 | } |
3795 | ||
79539cec AK |
3796 | static bool need_remote_flush(u64 old, u64 new) |
3797 | { | |
3798 | if (!is_shadow_present_pte(old)) | |
3799 | return false; | |
3800 | if (!is_shadow_present_pte(new)) | |
3801 | return true; | |
3802 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3803 | return true; | |
3804 | old ^= PT64_NX_MASK; | |
3805 | new ^= PT64_NX_MASK; | |
3806 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3807 | } | |
3808 | ||
0671a8e7 XG |
3809 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3810 | bool remote_flush, bool local_flush) | |
79539cec | 3811 | { |
0671a8e7 XG |
3812 | if (zap_page) |
3813 | return; | |
3814 | ||
3815 | if (remote_flush) | |
79539cec | 3816 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3817 | else if (local_flush) |
79539cec AK |
3818 | kvm_mmu_flush_tlb(vcpu); |
3819 | } | |
3820 | ||
889e5cbc XG |
3821 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3822 | const u8 *new, int *bytes) | |
da4a00f0 | 3823 | { |
889e5cbc XG |
3824 | u64 gentry; |
3825 | int r; | |
72016f3a | 3826 | |
72016f3a AK |
3827 | /* |
3828 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3829 | * as the current vcpu paging mode since we update the sptes only |
3830 | * when they have the same mode. | |
72016f3a | 3831 | */ |
889e5cbc | 3832 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3833 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3834 | *gpa &= ~(gpa_t)7; |
3835 | *bytes = 8; | |
116eb3d3 | 3836 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3837 | if (r) |
3838 | gentry = 0; | |
08e850c6 AK |
3839 | new = (const u8 *)&gentry; |
3840 | } | |
3841 | ||
889e5cbc | 3842 | switch (*bytes) { |
08e850c6 AK |
3843 | case 4: |
3844 | gentry = *(const u32 *)new; | |
3845 | break; | |
3846 | case 8: | |
3847 | gentry = *(const u64 *)new; | |
3848 | break; | |
3849 | default: | |
3850 | gentry = 0; | |
3851 | break; | |
72016f3a AK |
3852 | } |
3853 | ||
889e5cbc XG |
3854 | return gentry; |
3855 | } | |
3856 | ||
3857 | /* | |
3858 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3859 | * or we may be forking, in which case it is better to unmap the page. | |
3860 | */ | |
a138fe75 | 3861 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3862 | { |
a30f47cb XG |
3863 | /* |
3864 | * Skip write-flooding detected for the sp whose level is 1, because | |
3865 | * it can become unsync, then the guest page is not write-protected. | |
3866 | */ | |
f71fa31f | 3867 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3868 | return false; |
3246af0e | 3869 | |
a30f47cb | 3870 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3871 | } |
3872 | ||
3873 | /* | |
3874 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3875 | * indicate a page is not used as a page table. | |
3876 | */ | |
3877 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3878 | int bytes) | |
3879 | { | |
3880 | unsigned offset, pte_size, misaligned; | |
3881 | ||
3882 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3883 | gpa, bytes, sp->role.word); | |
3884 | ||
3885 | offset = offset_in_page(gpa); | |
3886 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3887 | |
3888 | /* | |
3889 | * Sometimes, the OS only writes the last one bytes to update status | |
3890 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3891 | */ | |
3892 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3893 | return false; | |
3894 | ||
889e5cbc XG |
3895 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3896 | misaligned |= bytes < 4; | |
3897 | ||
3898 | return misaligned; | |
3899 | } | |
3900 | ||
3901 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3902 | { | |
3903 | unsigned page_offset, quadrant; | |
3904 | u64 *spte; | |
3905 | int level; | |
3906 | ||
3907 | page_offset = offset_in_page(gpa); | |
3908 | level = sp->role.level; | |
3909 | *nspte = 1; | |
3910 | if (!sp->role.cr4_pae) { | |
3911 | page_offset <<= 1; /* 32->64 */ | |
3912 | /* | |
3913 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3914 | * only 2MB. So we need to double the offset again | |
3915 | * and zap two pdes instead of one. | |
3916 | */ | |
3917 | if (level == PT32_ROOT_LEVEL) { | |
3918 | page_offset &= ~7; /* kill rounding error */ | |
3919 | page_offset <<= 1; | |
3920 | *nspte = 2; | |
3921 | } | |
3922 | quadrant = page_offset >> PAGE_SHIFT; | |
3923 | page_offset &= ~PAGE_MASK; | |
3924 | if (quadrant != sp->role.quadrant) | |
3925 | return NULL; | |
3926 | } | |
3927 | ||
3928 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3929 | return spte; | |
3930 | } | |
3931 | ||
3932 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3933 | const u8 *new, int bytes) | |
3934 | { | |
3935 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3936 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3937 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
3938 | LIST_HEAD(invalid_list); |
3939 | u64 entry, gentry, *spte; | |
3940 | int npte; | |
a30f47cb | 3941 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3942 | |
3943 | /* | |
3944 | * If we don't have indirect shadow pages, it means no page is | |
3945 | * write-protected, so we can exit simply. | |
3946 | */ | |
3947 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3948 | return; | |
3949 | ||
3950 | zap_page = remote_flush = local_flush = false; | |
3951 | ||
3952 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3953 | ||
3954 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3955 | ||
3956 | /* | |
3957 | * No need to care whether allocation memory is successful | |
3958 | * or not since pte prefetch is skiped if it does not have | |
3959 | * enough objects in the cache. | |
3960 | */ | |
3961 | mmu_topup_memory_caches(vcpu); | |
3962 | ||
3963 | spin_lock(&vcpu->kvm->mmu_lock); | |
3964 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 3965 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 3966 | |
fa1de2bf | 3967 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 3968 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 3969 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 3970 | detect_write_flooding(sp)) { |
0671a8e7 | 3971 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3972 | &invalid_list); |
4cee5764 | 3973 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3974 | continue; |
3975 | } | |
889e5cbc XG |
3976 | |
3977 | spte = get_written_sptes(sp, gpa, &npte); | |
3978 | if (!spte) | |
3979 | continue; | |
3980 | ||
0671a8e7 | 3981 | local_flush = true; |
ac1b714e | 3982 | while (npte--) { |
79539cec | 3983 | entry = *spte; |
38e3b2b2 | 3984 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3985 | if (gentry && |
3986 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 3987 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 3988 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 3989 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 3990 | remote_flush = true; |
ac1b714e | 3991 | ++spte; |
9b7a0325 | 3992 | } |
9b7a0325 | 3993 | } |
0671a8e7 | 3994 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3995 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 3996 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3997 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3998 | } |
3999 | ||
a436036b AK |
4000 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4001 | { | |
10589a46 MT |
4002 | gpa_t gpa; |
4003 | int r; | |
a436036b | 4004 | |
c5a78f2b | 4005 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4006 | return 0; |
4007 | ||
1871c602 | 4008 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4009 | |
10589a46 | 4010 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4011 | |
10589a46 | 4012 | return r; |
a436036b | 4013 | } |
577bdc49 | 4014 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4015 | |
81f4f76b | 4016 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4017 | { |
d98ba053 | 4018 | LIST_HEAD(invalid_list); |
103ad25a | 4019 | |
81f4f76b TY |
4020 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4021 | return; | |
4022 | ||
5da59607 TY |
4023 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4024 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4025 | break; | |
ebeace86 | 4026 | |
4cee5764 | 4027 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4028 | } |
aa6bd187 | 4029 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4030 | } |
ebeace86 | 4031 | |
1cb3f3ae XG |
4032 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4033 | { | |
4034 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4035 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4036 | ||
4037 | return vcpu_match_mmio_gva(vcpu, addr); | |
4038 | } | |
4039 | ||
dc25e89e AP |
4040 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4041 | void *insn, int insn_len) | |
3067714c | 4042 | { |
1cb3f3ae | 4043 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4044 | enum emulation_result er; |
4045 | ||
56028d08 | 4046 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4047 | if (r < 0) |
4048 | goto out; | |
4049 | ||
4050 | if (!r) { | |
4051 | r = 1; | |
4052 | goto out; | |
4053 | } | |
4054 | ||
1cb3f3ae XG |
4055 | if (is_mmio_page_fault(vcpu, cr2)) |
4056 | emulation_type = 0; | |
4057 | ||
4058 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4059 | |
4060 | switch (er) { | |
4061 | case EMULATE_DONE: | |
4062 | return 1; | |
4063 | case EMULATE_DO_MMIO: | |
4064 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4065 | /* fall through */ |
3067714c | 4066 | case EMULATE_FAIL: |
3f5d18a9 | 4067 | return 0; |
3067714c AK |
4068 | default: |
4069 | BUG(); | |
4070 | } | |
4071 | out: | |
3067714c AK |
4072 | return r; |
4073 | } | |
4074 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4075 | ||
a7052897 MT |
4076 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4077 | { | |
a7052897 | 4078 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4079 | kvm_mmu_flush_tlb(vcpu); |
4080 | ++vcpu->stat.invlpg; | |
4081 | } | |
4082 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4083 | ||
18552672 JR |
4084 | void kvm_enable_tdp(void) |
4085 | { | |
4086 | tdp_enabled = true; | |
4087 | } | |
4088 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4089 | ||
5f4cb662 JR |
4090 | void kvm_disable_tdp(void) |
4091 | { | |
4092 | tdp_enabled = false; | |
4093 | } | |
4094 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4095 | ||
6aa8b732 AK |
4096 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4097 | { | |
ad312c7c | 4098 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4099 | if (vcpu->arch.mmu.lm_root != NULL) |
4100 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4101 | } |
4102 | ||
4103 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4104 | { | |
17ac10ad | 4105 | struct page *page; |
6aa8b732 AK |
4106 | int i; |
4107 | ||
4108 | ASSERT(vcpu); | |
4109 | ||
17ac10ad AK |
4110 | /* |
4111 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4112 | * Therefore we need to allocate shadow page tables in the first | |
4113 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4114 | */ | |
4115 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4116 | if (!page) | |
d7fa6ab2 WY |
4117 | return -ENOMEM; |
4118 | ||
ad312c7c | 4119 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4120 | for (i = 0; i < 4; ++i) |
ad312c7c | 4121 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4122 | |
6aa8b732 | 4123 | return 0; |
6aa8b732 AK |
4124 | } |
4125 | ||
8018c27b | 4126 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4127 | { |
6aa8b732 | 4128 | ASSERT(vcpu); |
e459e322 XG |
4129 | |
4130 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4131 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4132 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4133 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4134 | |
8018c27b IM |
4135 | return alloc_mmu_pages(vcpu); |
4136 | } | |
6aa8b732 | 4137 | |
8018c27b IM |
4138 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4139 | { | |
4140 | ASSERT(vcpu); | |
ad312c7c | 4141 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4142 | |
8018c27b | 4143 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4144 | } |
4145 | ||
90cb0529 | 4146 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4147 | { |
b99db1d3 TY |
4148 | struct kvm_memory_slot *memslot; |
4149 | gfn_t last_gfn; | |
4150 | int i; | |
6aa8b732 | 4151 | |
b99db1d3 TY |
4152 | memslot = id_to_memslot(kvm->memslots, slot); |
4153 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4154 | |
9d1beefb TY |
4155 | spin_lock(&kvm->mmu_lock); |
4156 | ||
b99db1d3 TY |
4157 | for (i = PT_PAGE_TABLE_LEVEL; |
4158 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4159 | unsigned long *rmapp; | |
4160 | unsigned long last_index, index; | |
6aa8b732 | 4161 | |
b99db1d3 TY |
4162 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4163 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4164 | |
b99db1d3 TY |
4165 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4166 | if (*rmapp) | |
4167 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e TY |
4168 | |
4169 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4170 | kvm_flush_remote_tlbs(kvm); | |
4171 | cond_resched_lock(&kvm->mmu_lock); | |
4172 | } | |
8234b22e | 4173 | } |
6aa8b732 | 4174 | } |
b99db1d3 | 4175 | |
171d595d | 4176 | kvm_flush_remote_tlbs(kvm); |
9d1beefb | 4177 | spin_unlock(&kvm->mmu_lock); |
6aa8b732 | 4178 | } |
37a7d8b0 | 4179 | |
90cb0529 | 4180 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 4181 | { |
4db35314 | 4182 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 4183 | LIST_HEAD(invalid_list); |
e0fa826f | 4184 | |
aaee2c94 | 4185 | spin_lock(&kvm->mmu_lock); |
3246af0e | 4186 | restart: |
f05e70ac | 4187 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 4188 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
4189 | goto restart; |
4190 | ||
d98ba053 | 4191 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 4192 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
4193 | } |
4194 | ||
982b3394 TY |
4195 | void kvm_mmu_zap_mmio_sptes(struct kvm *kvm) |
4196 | { | |
4197 | struct kvm_mmu_page *sp, *node; | |
4198 | LIST_HEAD(invalid_list); | |
4199 | ||
4200 | spin_lock(&kvm->mmu_lock); | |
4201 | restart: | |
4202 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { | |
4203 | if (!sp->mmio_cached) | |
4204 | continue; | |
4205 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) | |
4206 | goto restart; | |
4207 | } | |
4208 | ||
4209 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
4210 | spin_unlock(&kvm->mmu_lock); | |
4211 | } | |
4212 | ||
1495f230 | 4213 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4214 | { |
4215 | struct kvm *kvm; | |
1495f230 | 4216 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4217 | |
4218 | if (nr_to_scan == 0) | |
4219 | goto out; | |
3ee16c81 | 4220 | |
e935b837 | 4221 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4222 | |
4223 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4224 | int idx; |
d98ba053 | 4225 | LIST_HEAD(invalid_list); |
3ee16c81 | 4226 | |
35f2d16b TY |
4227 | /* |
4228 | * Never scan more than sc->nr_to_scan VM instances. | |
4229 | * Will not hit this condition practically since we do not try | |
4230 | * to shrink more than one VM and it is very unlikely to see | |
4231 | * !n_used_mmu_pages so many times. | |
4232 | */ | |
4233 | if (!nr_to_scan--) | |
4234 | break; | |
19526396 GN |
4235 | /* |
4236 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4237 | * here. We may skip a VM instance errorneosly, but we do not | |
4238 | * want to shrink a VM that only started to populate its MMU | |
4239 | * anyway. | |
4240 | */ | |
35f2d16b | 4241 | if (!kvm->arch.n_used_mmu_pages) |
19526396 | 4242 | continue; |
19526396 | 4243 | |
f656ce01 | 4244 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4245 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4246 | |
5da59607 | 4247 | prepare_zap_oldest_mmu_page(kvm, &invalid_list); |
d98ba053 | 4248 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4249 | |
3ee16c81 | 4250 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4251 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4252 | |
4253 | list_move_tail(&kvm->vm_list, &vm_list); | |
4254 | break; | |
3ee16c81 | 4255 | } |
3ee16c81 | 4256 | |
e935b837 | 4257 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4258 | |
45221ab6 DH |
4259 | out: |
4260 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4261 | } |
4262 | ||
4263 | static struct shrinker mmu_shrinker = { | |
4264 | .shrink = mmu_shrink, | |
4265 | .seeks = DEFAULT_SEEKS * 10, | |
4266 | }; | |
4267 | ||
2ddfd20e | 4268 | static void mmu_destroy_caches(void) |
b5a33a75 | 4269 | { |
53c07b18 XG |
4270 | if (pte_list_desc_cache) |
4271 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4272 | if (mmu_page_header_cache) |
4273 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4274 | } |
4275 | ||
4276 | int kvm_mmu_module_init(void) | |
4277 | { | |
53c07b18 XG |
4278 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4279 | sizeof(struct pte_list_desc), | |
20c2df83 | 4280 | 0, 0, NULL); |
53c07b18 | 4281 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4282 | goto nomem; |
4283 | ||
d3d25b04 AK |
4284 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4285 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4286 | 0, 0, NULL); |
d3d25b04 AK |
4287 | if (!mmu_page_header_cache) |
4288 | goto nomem; | |
4289 | ||
45bf21a8 WY |
4290 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4291 | goto nomem; | |
4292 | ||
3ee16c81 IE |
4293 | register_shrinker(&mmu_shrinker); |
4294 | ||
b5a33a75 AK |
4295 | return 0; |
4296 | ||
4297 | nomem: | |
3ee16c81 | 4298 | mmu_destroy_caches(); |
b5a33a75 AK |
4299 | return -ENOMEM; |
4300 | } | |
4301 | ||
3ad82a7e ZX |
4302 | /* |
4303 | * Caculate mmu pages needed for kvm. | |
4304 | */ | |
4305 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4306 | { | |
3ad82a7e ZX |
4307 | unsigned int nr_mmu_pages; |
4308 | unsigned int nr_pages = 0; | |
bc6678a3 | 4309 | struct kvm_memslots *slots; |
be6ba0f0 | 4310 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4311 | |
90d83dc3 LJ |
4312 | slots = kvm_memslots(kvm); |
4313 | ||
be6ba0f0 XG |
4314 | kvm_for_each_memslot(memslot, slots) |
4315 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4316 | |
4317 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4318 | nr_mmu_pages = max(nr_mmu_pages, | |
4319 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4320 | ||
4321 | return nr_mmu_pages; | |
4322 | } | |
4323 | ||
94d8b056 MT |
4324 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4325 | { | |
4326 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4327 | u64 spte; |
94d8b056 MT |
4328 | int nr_sptes = 0; |
4329 | ||
c2a2ac2b XG |
4330 | walk_shadow_page_lockless_begin(vcpu); |
4331 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4332 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4333 | nr_sptes++; |
c2a2ac2b | 4334 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4335 | break; |
4336 | } | |
c2a2ac2b | 4337 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4338 | |
4339 | return nr_sptes; | |
4340 | } | |
4341 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4342 | ||
c42fffe3 XG |
4343 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4344 | { | |
4345 | ASSERT(vcpu); | |
4346 | ||
4347 | destroy_kvm_mmu(vcpu); | |
4348 | free_mmu_pages(vcpu); | |
4349 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4350 | } |
4351 | ||
b034cf01 XG |
4352 | void kvm_mmu_module_exit(void) |
4353 | { | |
4354 | mmu_destroy_caches(); | |
4355 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4356 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4357 | mmu_audit_disable(); |
4358 | } |