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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
200 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
201 | { | |
202 | access &= ACC_WRITE_MASK | ACC_USER_MASK; | |
203 | ||
4f022648 | 204 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
205 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
206 | } | |
207 | ||
208 | static bool is_mmio_spte(u64 spte) | |
209 | { | |
210 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
211 | } | |
212 | ||
213 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
214 | { | |
215 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
216 | } | |
217 | ||
218 | static unsigned get_mmio_spte_access(u64 spte) | |
219 | { | |
220 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
221 | } | |
222 | ||
223 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
224 | { | |
225 | if (unlikely(is_noslot_pfn(pfn))) { | |
226 | mark_mmio_spte(sptep, gfn, access); | |
227 | return true; | |
228 | } | |
229 | ||
230 | return false; | |
231 | } | |
c7addb90 | 232 | |
82725b20 DE |
233 | static inline u64 rsvd_bits(int s, int e) |
234 | { | |
235 | return ((1ULL << (e - s + 1)) - 1) << s; | |
236 | } | |
237 | ||
7b52345e | 238 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 239 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
240 | { |
241 | shadow_user_mask = user_mask; | |
242 | shadow_accessed_mask = accessed_mask; | |
243 | shadow_dirty_mask = dirty_mask; | |
244 | shadow_nx_mask = nx_mask; | |
245 | shadow_x_mask = x_mask; | |
246 | } | |
247 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
248 | ||
6aa8b732 AK |
249 | static int is_cpuid_PSE36(void) |
250 | { | |
251 | return 1; | |
252 | } | |
253 | ||
73b1087e AK |
254 | static int is_nx(struct kvm_vcpu *vcpu) |
255 | { | |
f6801dff | 256 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
257 | } |
258 | ||
c7addb90 AK |
259 | static int is_shadow_present_pte(u64 pte) |
260 | { | |
ce88decf | 261 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
262 | } |
263 | ||
05da4558 MT |
264 | static int is_large_pte(u64 pte) |
265 | { | |
266 | return pte & PT_PAGE_SIZE_MASK; | |
267 | } | |
268 | ||
43a3795a | 269 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 270 | { |
439e218a | 271 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
272 | } |
273 | ||
43a3795a | 274 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 275 | { |
4b1a80fa | 276 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
277 | } |
278 | ||
776e6633 MT |
279 | static int is_last_spte(u64 pte, int level) |
280 | { | |
281 | if (level == PT_PAGE_TABLE_LEVEL) | |
282 | return 1; | |
852e3c19 | 283 | if (is_large_pte(pte)) |
776e6633 MT |
284 | return 1; |
285 | return 0; | |
286 | } | |
287 | ||
35149e21 | 288 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 289 | { |
35149e21 | 290 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
291 | } |
292 | ||
da928521 AK |
293 | static gfn_t pse36_gfn_delta(u32 gpte) |
294 | { | |
295 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
296 | ||
297 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
298 | } | |
299 | ||
603e0651 | 300 | #ifdef CONFIG_X86_64 |
d555c333 | 301 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 302 | { |
603e0651 | 303 | *sptep = spte; |
e663ee64 AK |
304 | } |
305 | ||
603e0651 | 306 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 307 | { |
603e0651 XG |
308 | *sptep = spte; |
309 | } | |
310 | ||
311 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
312 | { | |
313 | return xchg(sptep, spte); | |
314 | } | |
c2a2ac2b XG |
315 | |
316 | static u64 __get_spte_lockless(u64 *sptep) | |
317 | { | |
318 | return ACCESS_ONCE(*sptep); | |
319 | } | |
ce88decf XG |
320 | |
321 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
322 | { | |
323 | /* It is valid if the spte is zapped. */ | |
324 | return spte == 0ull; | |
325 | } | |
a9221dd5 | 326 | #else |
603e0651 XG |
327 | union split_spte { |
328 | struct { | |
329 | u32 spte_low; | |
330 | u32 spte_high; | |
331 | }; | |
332 | u64 spte; | |
333 | }; | |
a9221dd5 | 334 | |
c2a2ac2b XG |
335 | static void count_spte_clear(u64 *sptep, u64 spte) |
336 | { | |
337 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
338 | ||
339 | if (is_shadow_present_pte(spte)) | |
340 | return; | |
341 | ||
342 | /* Ensure the spte is completely set before we increase the count */ | |
343 | smp_wmb(); | |
344 | sp->clear_spte_count++; | |
345 | } | |
346 | ||
603e0651 XG |
347 | static void __set_spte(u64 *sptep, u64 spte) |
348 | { | |
349 | union split_spte *ssptep, sspte; | |
a9221dd5 | 350 | |
603e0651 XG |
351 | ssptep = (union split_spte *)sptep; |
352 | sspte = (union split_spte)spte; | |
353 | ||
354 | ssptep->spte_high = sspte.spte_high; | |
355 | ||
356 | /* | |
357 | * If we map the spte from nonpresent to present, We should store | |
358 | * the high bits firstly, then set present bit, so cpu can not | |
359 | * fetch this spte while we are setting the spte. | |
360 | */ | |
361 | smp_wmb(); | |
362 | ||
363 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
364 | } |
365 | ||
603e0651 XG |
366 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
367 | { | |
368 | union split_spte *ssptep, sspte; | |
369 | ||
370 | ssptep = (union split_spte *)sptep; | |
371 | sspte = (union split_spte)spte; | |
372 | ||
373 | ssptep->spte_low = sspte.spte_low; | |
374 | ||
375 | /* | |
376 | * If we map the spte from present to nonpresent, we should clear | |
377 | * present bit firstly to avoid vcpu fetch the old high bits. | |
378 | */ | |
379 | smp_wmb(); | |
380 | ||
381 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 382 | count_spte_clear(sptep, spte); |
603e0651 XG |
383 | } |
384 | ||
385 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
386 | { | |
387 | union split_spte *ssptep, sspte, orig; | |
388 | ||
389 | ssptep = (union split_spte *)sptep; | |
390 | sspte = (union split_spte)spte; | |
391 | ||
392 | /* xchg acts as a barrier before the setting of the high bits */ | |
393 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
394 | orig.spte_high = ssptep->spte_high; |
395 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 396 | count_spte_clear(sptep, spte); |
603e0651 XG |
397 | |
398 | return orig.spte; | |
399 | } | |
c2a2ac2b XG |
400 | |
401 | /* | |
402 | * The idea using the light way get the spte on x86_32 guest is from | |
403 | * gup_get_pte(arch/x86/mm/gup.c). | |
404 | * The difference is we can not catch the spte tlb flush if we leave | |
405 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
406 | * is cleared. | |
407 | */ | |
408 | static u64 __get_spte_lockless(u64 *sptep) | |
409 | { | |
410 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
411 | union split_spte spte, *orig = (union split_spte *)sptep; | |
412 | int count; | |
413 | ||
414 | retry: | |
415 | count = sp->clear_spte_count; | |
416 | smp_rmb(); | |
417 | ||
418 | spte.spte_low = orig->spte_low; | |
419 | smp_rmb(); | |
420 | ||
421 | spte.spte_high = orig->spte_high; | |
422 | smp_rmb(); | |
423 | ||
424 | if (unlikely(spte.spte_low != orig->spte_low || | |
425 | count != sp->clear_spte_count)) | |
426 | goto retry; | |
427 | ||
428 | return spte.spte; | |
429 | } | |
ce88decf XG |
430 | |
431 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
432 | { | |
433 | union split_spte sspte = (union split_spte)spte; | |
434 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
435 | ||
436 | /* It is valid if the spte is zapped. */ | |
437 | if (spte == 0ull) | |
438 | return true; | |
439 | ||
440 | /* It is valid if the spte is being zapped. */ | |
441 | if (sspte.spte_low == 0ull && | |
442 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
443 | return true; | |
444 | ||
445 | return false; | |
446 | } | |
603e0651 XG |
447 | #endif |
448 | ||
c7ba5b48 XG |
449 | static bool spte_is_locklessly_modifiable(u64 spte) |
450 | { | |
feb3eb70 GN |
451 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
452 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
453 | } |
454 | ||
8672b721 XG |
455 | static bool spte_has_volatile_bits(u64 spte) |
456 | { | |
c7ba5b48 XG |
457 | /* |
458 | * Always atomicly update spte if it can be updated | |
459 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
460 | * also, it can help us to get a stable is_writable_pte() | |
461 | * to ensure tlb flush is not missed. | |
462 | */ | |
463 | if (spte_is_locklessly_modifiable(spte)) | |
464 | return true; | |
465 | ||
8672b721 XG |
466 | if (!shadow_accessed_mask) |
467 | return false; | |
468 | ||
469 | if (!is_shadow_present_pte(spte)) | |
470 | return false; | |
471 | ||
4132779b XG |
472 | if ((spte & shadow_accessed_mask) && |
473 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
474 | return false; |
475 | ||
476 | return true; | |
477 | } | |
478 | ||
4132779b XG |
479 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
480 | { | |
481 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
482 | } | |
483 | ||
1df9f2dc XG |
484 | /* Rules for using mmu_spte_set: |
485 | * Set the sptep from nonpresent to present. | |
486 | * Note: the sptep being assigned *must* be either not present | |
487 | * or in a state where the hardware will not attempt to update | |
488 | * the spte. | |
489 | */ | |
490 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
491 | { | |
492 | WARN_ON(is_shadow_present_pte(*sptep)); | |
493 | __set_spte(sptep, new_spte); | |
494 | } | |
495 | ||
496 | /* Rules for using mmu_spte_update: | |
497 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
498 | * |
499 | * Whenever we overwrite a writable spte with a read-only one we | |
500 | * should flush remote TLBs. Otherwise rmap_write_protect | |
501 | * will find a read-only spte, even though the writable spte | |
502 | * might be cached on a CPU's TLB, the return value indicates this | |
503 | * case. | |
1df9f2dc | 504 | */ |
6e7d0354 | 505 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 506 | { |
c7ba5b48 | 507 | u64 old_spte = *sptep; |
6e7d0354 | 508 | bool ret = false; |
4132779b XG |
509 | |
510 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 511 | |
6e7d0354 XG |
512 | if (!is_shadow_present_pte(old_spte)) { |
513 | mmu_spte_set(sptep, new_spte); | |
514 | return ret; | |
515 | } | |
4132779b | 516 | |
c7ba5b48 | 517 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 518 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 519 | else |
603e0651 | 520 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 521 | |
c7ba5b48 XG |
522 | /* |
523 | * For the spte updated out of mmu-lock is safe, since | |
524 | * we always atomicly update it, see the comments in | |
525 | * spte_has_volatile_bits(). | |
526 | */ | |
6e7d0354 XG |
527 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
528 | ret = true; | |
529 | ||
4132779b | 530 | if (!shadow_accessed_mask) |
6e7d0354 | 531 | return ret; |
4132779b XG |
532 | |
533 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
534 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
535 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
536 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
537 | |
538 | return ret; | |
b79b93f9 AK |
539 | } |
540 | ||
1df9f2dc XG |
541 | /* |
542 | * Rules for using mmu_spte_clear_track_bits: | |
543 | * It sets the sptep from present to nonpresent, and track the | |
544 | * state bits, it is used to clear the last level sptep. | |
545 | */ | |
546 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
547 | { | |
548 | pfn_t pfn; | |
549 | u64 old_spte = *sptep; | |
550 | ||
551 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 552 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 553 | else |
603e0651 | 554 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
555 | |
556 | if (!is_rmap_spte(old_spte)) | |
557 | return 0; | |
558 | ||
559 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
560 | |
561 | /* | |
562 | * KVM does not hold the refcount of the page used by | |
563 | * kvm mmu, before reclaiming the page, we should | |
564 | * unmap it from mmu first. | |
565 | */ | |
566 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
567 | ||
1df9f2dc XG |
568 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
569 | kvm_set_pfn_accessed(pfn); | |
570 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
571 | kvm_set_pfn_dirty(pfn); | |
572 | return 1; | |
573 | } | |
574 | ||
575 | /* | |
576 | * Rules for using mmu_spte_clear_no_track: | |
577 | * Directly clear spte without caring the state bits of sptep, | |
578 | * it is used to set the upper level spte. | |
579 | */ | |
580 | static void mmu_spte_clear_no_track(u64 *sptep) | |
581 | { | |
603e0651 | 582 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
583 | } |
584 | ||
c2a2ac2b XG |
585 | static u64 mmu_spte_get_lockless(u64 *sptep) |
586 | { | |
587 | return __get_spte_lockless(sptep); | |
588 | } | |
589 | ||
590 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
591 | { | |
c142786c AK |
592 | /* |
593 | * Prevent page table teardown by making any free-er wait during | |
594 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
595 | */ | |
596 | local_irq_disable(); | |
597 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
598 | /* | |
599 | * Make sure a following spte read is not reordered ahead of the write | |
600 | * to vcpu->mode. | |
601 | */ | |
602 | smp_mb(); | |
c2a2ac2b XG |
603 | } |
604 | ||
605 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
606 | { | |
c142786c AK |
607 | /* |
608 | * Make sure the write to vcpu->mode is not reordered in front of | |
609 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
610 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
611 | */ | |
612 | smp_mb(); | |
613 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
614 | local_irq_enable(); | |
c2a2ac2b XG |
615 | } |
616 | ||
e2dec939 | 617 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 618 | struct kmem_cache *base_cache, int min) |
714b93da AK |
619 | { |
620 | void *obj; | |
621 | ||
622 | if (cache->nobjs >= min) | |
e2dec939 | 623 | return 0; |
714b93da | 624 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 625 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 626 | if (!obj) |
e2dec939 | 627 | return -ENOMEM; |
714b93da AK |
628 | cache->objects[cache->nobjs++] = obj; |
629 | } | |
e2dec939 | 630 | return 0; |
714b93da AK |
631 | } |
632 | ||
f759e2b4 XG |
633 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
634 | { | |
635 | return cache->nobjs; | |
636 | } | |
637 | ||
e8ad9a70 XG |
638 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
639 | struct kmem_cache *cache) | |
714b93da AK |
640 | { |
641 | while (mc->nobjs) | |
e8ad9a70 | 642 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
643 | } |
644 | ||
c1158e63 | 645 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 646 | int min) |
c1158e63 | 647 | { |
842f22ed | 648 | void *page; |
c1158e63 AK |
649 | |
650 | if (cache->nobjs >= min) | |
651 | return 0; | |
652 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 653 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
654 | if (!page) |
655 | return -ENOMEM; | |
842f22ed | 656 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
657 | } |
658 | return 0; | |
659 | } | |
660 | ||
661 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
662 | { | |
663 | while (mc->nobjs) | |
c4d198d5 | 664 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
665 | } |
666 | ||
2e3e5882 | 667 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 668 | { |
e2dec939 AK |
669 | int r; |
670 | ||
53c07b18 | 671 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 672 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
673 | if (r) |
674 | goto out; | |
ad312c7c | 675 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
676 | if (r) |
677 | goto out; | |
ad312c7c | 678 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 679 | mmu_page_header_cache, 4); |
e2dec939 AK |
680 | out: |
681 | return r; | |
714b93da AK |
682 | } |
683 | ||
684 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
685 | { | |
53c07b18 XG |
686 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
687 | pte_list_desc_cache); | |
ad312c7c | 688 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
689 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
690 | mmu_page_header_cache); | |
714b93da AK |
691 | } |
692 | ||
80feb89a | 693 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
694 | { |
695 | void *p; | |
696 | ||
697 | BUG_ON(!mc->nobjs); | |
698 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
699 | return p; |
700 | } | |
701 | ||
53c07b18 | 702 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 703 | { |
80feb89a | 704 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
705 | } |
706 | ||
53c07b18 | 707 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 708 | { |
53c07b18 | 709 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
710 | } |
711 | ||
2032a93d LJ |
712 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
713 | { | |
714 | if (!sp->role.direct) | |
715 | return sp->gfns[index]; | |
716 | ||
717 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
718 | } | |
719 | ||
720 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
721 | { | |
722 | if (sp->role.direct) | |
723 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
724 | else | |
725 | sp->gfns[index] = gfn; | |
726 | } | |
727 | ||
05da4558 | 728 | /* |
d4dbf470 TY |
729 | * Return the pointer to the large page information for a given gfn, |
730 | * handling slots that are not large page aligned. | |
05da4558 | 731 | */ |
d4dbf470 TY |
732 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
733 | struct kvm_memory_slot *slot, | |
734 | int level) | |
05da4558 MT |
735 | { |
736 | unsigned long idx; | |
737 | ||
fb03cb6f | 738 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 739 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
740 | } |
741 | ||
742 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
743 | { | |
d25797b2 | 744 | struct kvm_memory_slot *slot; |
d4dbf470 | 745 | struct kvm_lpage_info *linfo; |
d25797b2 | 746 | int i; |
05da4558 | 747 | |
a1f4d395 | 748 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
749 | for (i = PT_DIRECTORY_LEVEL; |
750 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
751 | linfo = lpage_info_slot(gfn, slot, i); |
752 | linfo->write_count += 1; | |
d25797b2 | 753 | } |
332b207d | 754 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
755 | } |
756 | ||
757 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
758 | { | |
d25797b2 | 759 | struct kvm_memory_slot *slot; |
d4dbf470 | 760 | struct kvm_lpage_info *linfo; |
d25797b2 | 761 | int i; |
05da4558 | 762 | |
a1f4d395 | 763 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
764 | for (i = PT_DIRECTORY_LEVEL; |
765 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
766 | linfo = lpage_info_slot(gfn, slot, i); |
767 | linfo->write_count -= 1; | |
768 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 769 | } |
332b207d | 770 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
771 | } |
772 | ||
d25797b2 JR |
773 | static int has_wrprotected_page(struct kvm *kvm, |
774 | gfn_t gfn, | |
775 | int level) | |
05da4558 | 776 | { |
2843099f | 777 | struct kvm_memory_slot *slot; |
d4dbf470 | 778 | struct kvm_lpage_info *linfo; |
05da4558 | 779 | |
a1f4d395 | 780 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 781 | if (slot) { |
d4dbf470 TY |
782 | linfo = lpage_info_slot(gfn, slot, level); |
783 | return linfo->write_count; | |
05da4558 MT |
784 | } |
785 | ||
786 | return 1; | |
787 | } | |
788 | ||
d25797b2 | 789 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 790 | { |
8f0b1ab6 | 791 | unsigned long page_size; |
d25797b2 | 792 | int i, ret = 0; |
05da4558 | 793 | |
8f0b1ab6 | 794 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 795 | |
d25797b2 JR |
796 | for (i = PT_PAGE_TABLE_LEVEL; |
797 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
798 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
799 | ret = i; | |
800 | else | |
801 | break; | |
802 | } | |
803 | ||
4c2155ce | 804 | return ret; |
05da4558 MT |
805 | } |
806 | ||
5d163b1c XG |
807 | static struct kvm_memory_slot * |
808 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
809 | bool no_dirty_log) | |
05da4558 MT |
810 | { |
811 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
812 | |
813 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
814 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
815 | (no_dirty_log && slot->dirty_bitmap)) | |
816 | slot = NULL; | |
817 | ||
818 | return slot; | |
819 | } | |
820 | ||
821 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
822 | { | |
a0a8eaba | 823 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
824 | } |
825 | ||
826 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
827 | { | |
828 | int host_level, level, max_level; | |
05da4558 | 829 | |
d25797b2 JR |
830 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
831 | ||
832 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
833 | return host_level; | |
834 | ||
55dd98c3 | 835 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
836 | |
837 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
838 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
839 | break; | |
d25797b2 JR |
840 | |
841 | return level - 1; | |
05da4558 MT |
842 | } |
843 | ||
290fc38d | 844 | /* |
53c07b18 | 845 | * Pte mapping structures: |
cd4a4e53 | 846 | * |
53c07b18 | 847 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 848 | * |
53c07b18 XG |
849 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
850 | * pte_list_desc containing more mappings. | |
53a27b39 | 851 | * |
53c07b18 | 852 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
853 | * the spte was not added. |
854 | * | |
cd4a4e53 | 855 | */ |
53c07b18 XG |
856 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
857 | unsigned long *pte_list) | |
cd4a4e53 | 858 | { |
53c07b18 | 859 | struct pte_list_desc *desc; |
53a27b39 | 860 | int i, count = 0; |
cd4a4e53 | 861 | |
53c07b18 XG |
862 | if (!*pte_list) { |
863 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
864 | *pte_list = (unsigned long)spte; | |
865 | } else if (!(*pte_list & 1)) { | |
866 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
867 | desc = mmu_alloc_pte_list_desc(vcpu); | |
868 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 869 | desc->sptes[1] = spte; |
53c07b18 | 870 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 871 | ++count; |
cd4a4e53 | 872 | } else { |
53c07b18 XG |
873 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
874 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
875 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 876 | desc = desc->more; |
53c07b18 | 877 | count += PTE_LIST_EXT; |
53a27b39 | 878 | } |
53c07b18 XG |
879 | if (desc->sptes[PTE_LIST_EXT-1]) { |
880 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
881 | desc = desc->more; |
882 | } | |
d555c333 | 883 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 884 | ++count; |
d555c333 | 885 | desc->sptes[i] = spte; |
cd4a4e53 | 886 | } |
53a27b39 | 887 | return count; |
cd4a4e53 AK |
888 | } |
889 | ||
53c07b18 XG |
890 | static void |
891 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
892 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
893 | { |
894 | int j; | |
895 | ||
53c07b18 | 896 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 897 | ; |
d555c333 AK |
898 | desc->sptes[i] = desc->sptes[j]; |
899 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
900 | if (j != 0) |
901 | return; | |
902 | if (!prev_desc && !desc->more) | |
53c07b18 | 903 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
904 | else |
905 | if (prev_desc) | |
906 | prev_desc->more = desc->more; | |
907 | else | |
53c07b18 XG |
908 | *pte_list = (unsigned long)desc->more | 1; |
909 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
910 | } |
911 | ||
53c07b18 | 912 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 913 | { |
53c07b18 XG |
914 | struct pte_list_desc *desc; |
915 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
916 | int i; |
917 | ||
53c07b18 XG |
918 | if (!*pte_list) { |
919 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 920 | BUG(); |
53c07b18 XG |
921 | } else if (!(*pte_list & 1)) { |
922 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
923 | if ((u64 *)*pte_list != spte) { | |
924 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
925 | BUG(); |
926 | } | |
53c07b18 | 927 | *pte_list = 0; |
cd4a4e53 | 928 | } else { |
53c07b18 XG |
929 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
930 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
931 | prev_desc = NULL; |
932 | while (desc) { | |
53c07b18 | 933 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 934 | if (desc->sptes[i] == spte) { |
53c07b18 | 935 | pte_list_desc_remove_entry(pte_list, |
714b93da | 936 | desc, i, |
cd4a4e53 AK |
937 | prev_desc); |
938 | return; | |
939 | } | |
940 | prev_desc = desc; | |
941 | desc = desc->more; | |
942 | } | |
53c07b18 | 943 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
944 | BUG(); |
945 | } | |
946 | } | |
947 | ||
67052b35 XG |
948 | typedef void (*pte_list_walk_fn) (u64 *spte); |
949 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
950 | { | |
951 | struct pte_list_desc *desc; | |
952 | int i; | |
953 | ||
954 | if (!*pte_list) | |
955 | return; | |
956 | ||
957 | if (!(*pte_list & 1)) | |
958 | return fn((u64 *)*pte_list); | |
959 | ||
960 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
961 | while (desc) { | |
962 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
963 | fn(desc->sptes[i]); | |
964 | desc = desc->more; | |
965 | } | |
966 | } | |
967 | ||
9373e2c0 | 968 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 969 | struct kvm_memory_slot *slot) |
53c07b18 | 970 | { |
77d11309 | 971 | unsigned long idx; |
53c07b18 | 972 | |
77d11309 | 973 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 974 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
975 | } |
976 | ||
9b9b1492 TY |
977 | /* |
978 | * Take gfn and return the reverse mapping to it. | |
979 | */ | |
980 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
981 | { | |
982 | struct kvm_memory_slot *slot; | |
983 | ||
984 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 985 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
986 | } |
987 | ||
f759e2b4 XG |
988 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
989 | { | |
990 | struct kvm_mmu_memory_cache *cache; | |
991 | ||
992 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
993 | return mmu_memory_cache_free_objects(cache); | |
994 | } | |
995 | ||
53c07b18 XG |
996 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
997 | { | |
998 | struct kvm_mmu_page *sp; | |
999 | unsigned long *rmapp; | |
1000 | ||
53c07b18 XG |
1001 | sp = page_header(__pa(spte)); |
1002 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1003 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1004 | return pte_list_add(vcpu, spte, rmapp); | |
1005 | } | |
1006 | ||
53c07b18 XG |
1007 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1008 | { | |
1009 | struct kvm_mmu_page *sp; | |
1010 | gfn_t gfn; | |
1011 | unsigned long *rmapp; | |
1012 | ||
1013 | sp = page_header(__pa(spte)); | |
1014 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1015 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1016 | pte_list_remove(spte, rmapp); | |
1017 | } | |
1018 | ||
1e3f42f0 TY |
1019 | /* |
1020 | * Used by the following functions to iterate through the sptes linked by a | |
1021 | * rmap. All fields are private and not assumed to be used outside. | |
1022 | */ | |
1023 | struct rmap_iterator { | |
1024 | /* private fields */ | |
1025 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1026 | int pos; /* index of the sptep */ | |
1027 | }; | |
1028 | ||
1029 | /* | |
1030 | * Iteration must be started by this function. This should also be used after | |
1031 | * removing/dropping sptes from the rmap link because in such cases the | |
1032 | * information in the itererator may not be valid. | |
1033 | * | |
1034 | * Returns sptep if found, NULL otherwise. | |
1035 | */ | |
1036 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1037 | { | |
1038 | if (!rmap) | |
1039 | return NULL; | |
1040 | ||
1041 | if (!(rmap & 1)) { | |
1042 | iter->desc = NULL; | |
1043 | return (u64 *)rmap; | |
1044 | } | |
1045 | ||
1046 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1047 | iter->pos = 0; | |
1048 | return iter->desc->sptes[iter->pos]; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1053 | * | |
1054 | * Returns sptep if found, NULL otherwise. | |
1055 | */ | |
1056 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1057 | { | |
1058 | if (iter->desc) { | |
1059 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1060 | u64 *sptep; | |
1061 | ||
1062 | ++iter->pos; | |
1063 | sptep = iter->desc->sptes[iter->pos]; | |
1064 | if (sptep) | |
1065 | return sptep; | |
1066 | } | |
1067 | ||
1068 | iter->desc = iter->desc->more; | |
1069 | ||
1070 | if (iter->desc) { | |
1071 | iter->pos = 0; | |
1072 | /* desc->sptes[0] cannot be NULL */ | |
1073 | return iter->desc->sptes[iter->pos]; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | return NULL; | |
1078 | } | |
1079 | ||
c3707958 | 1080 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1081 | { |
1df9f2dc | 1082 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1083 | rmap_remove(kvm, sptep); |
be38d276 AK |
1084 | } |
1085 | ||
8e22f955 XG |
1086 | |
1087 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1088 | { | |
1089 | if (is_large_pte(*sptep)) { | |
1090 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1091 | PT_PAGE_TABLE_LEVEL); | |
1092 | drop_spte(kvm, sptep); | |
1093 | --kvm->stat.lpages; | |
1094 | return true; | |
1095 | } | |
1096 | ||
1097 | return false; | |
1098 | } | |
1099 | ||
1100 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1101 | { | |
1102 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1103 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1104 | } | |
1105 | ||
1106 | /* | |
49fde340 | 1107 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
6b73a960 MT |
1108 | * spte writ-protection is caused by protecting shadow page table. |
1109 | * @flush indicates whether tlb need be flushed. | |
49fde340 XG |
1110 | * |
1111 | * Note: write protection is difference between drity logging and spte | |
1112 | * protection: | |
1113 | * - for dirty logging, the spte can be set to writable at anytime if | |
1114 | * its dirty bitmap is properly set. | |
1115 | * - for spte protection, the spte can be writable only after unsync-ing | |
1116 | * shadow page. | |
8e22f955 | 1117 | * |
6b73a960 | 1118 | * Return true if the spte is dropped. |
8e22f955 | 1119 | */ |
6b73a960 MT |
1120 | static bool |
1121 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1122 | { |
1123 | u64 spte = *sptep; | |
1124 | ||
49fde340 XG |
1125 | if (!is_writable_pte(spte) && |
1126 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1127 | return false; |
1128 | ||
1129 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1130 | ||
6b73a960 MT |
1131 | if (__drop_large_spte(kvm, sptep)) { |
1132 | *flush |= true; | |
1133 | return true; | |
1134 | } | |
1135 | ||
49fde340 XG |
1136 | if (pt_protect) |
1137 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1138 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1139 | |
6b73a960 MT |
1140 | *flush |= mmu_spte_update(sptep, spte); |
1141 | return false; | |
d13bc5b5 XG |
1142 | } |
1143 | ||
49fde340 | 1144 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1145 | bool pt_protect) |
98348e95 | 1146 | { |
1e3f42f0 TY |
1147 | u64 *sptep; |
1148 | struct rmap_iterator iter; | |
d13bc5b5 | 1149 | bool flush = false; |
374cbac0 | 1150 | |
1e3f42f0 TY |
1151 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1152 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
6b73a960 MT |
1153 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1154 | sptep = rmap_get_first(*rmapp, &iter); | |
1155 | continue; | |
1156 | } | |
a0ed4607 | 1157 | |
d13bc5b5 | 1158 | sptep = rmap_get_next(&iter); |
374cbac0 | 1159 | } |
855149aa | 1160 | |
d13bc5b5 | 1161 | return flush; |
a0ed4607 TY |
1162 | } |
1163 | ||
5dc99b23 TY |
1164 | /** |
1165 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1166 | * @kvm: kvm instance | |
1167 | * @slot: slot to protect | |
1168 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1169 | * @mask: indicates which pages we should protect | |
1170 | * | |
1171 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1172 | * logging we do not have any such mappings. | |
1173 | */ | |
1174 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1175 | struct kvm_memory_slot *slot, | |
1176 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1177 | { |
1178 | unsigned long *rmapp; | |
a0ed4607 | 1179 | |
5dc99b23 | 1180 | while (mask) { |
65fbe37c TY |
1181 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1182 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1183 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1184 | |
5dc99b23 TY |
1185 | /* clear the first set bit */ |
1186 | mask &= mask - 1; | |
1187 | } | |
374cbac0 AK |
1188 | } |
1189 | ||
2f84569f | 1190 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1191 | { |
1192 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1193 | unsigned long *rmapp; |
1194 | int i; | |
2f84569f | 1195 | bool write_protected = false; |
95d4c16c TY |
1196 | |
1197 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1198 | |
1199 | for (i = PT_PAGE_TABLE_LEVEL; | |
1200 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1201 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1202 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1203 | } |
1204 | ||
1205 | return write_protected; | |
95d4c16c TY |
1206 | } |
1207 | ||
8a8365c5 | 1208 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1209 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1210 | { |
1e3f42f0 TY |
1211 | u64 *sptep; |
1212 | struct rmap_iterator iter; | |
e930bffe AA |
1213 | int need_tlb_flush = 0; |
1214 | ||
1e3f42f0 TY |
1215 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1216 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1217 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1218 | ||
1219 | drop_spte(kvm, sptep); | |
e930bffe AA |
1220 | need_tlb_flush = 1; |
1221 | } | |
1e3f42f0 | 1222 | |
e930bffe AA |
1223 | return need_tlb_flush; |
1224 | } | |
1225 | ||
8a8365c5 | 1226 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1227 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1228 | { |
1e3f42f0 TY |
1229 | u64 *sptep; |
1230 | struct rmap_iterator iter; | |
3da0dd43 | 1231 | int need_flush = 0; |
1e3f42f0 | 1232 | u64 new_spte; |
3da0dd43 IE |
1233 | pte_t *ptep = (pte_t *)data; |
1234 | pfn_t new_pfn; | |
1235 | ||
1236 | WARN_ON(pte_huge(*ptep)); | |
1237 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1238 | |
1239 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1240 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1241 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1242 | ||
3da0dd43 | 1243 | need_flush = 1; |
1e3f42f0 | 1244 | |
3da0dd43 | 1245 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1246 | drop_spte(kvm, sptep); |
1247 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1248 | } else { |
1e3f42f0 | 1249 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1250 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1251 | ||
1252 | new_spte &= ~PT_WRITABLE_MASK; | |
1253 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1254 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1255 | |
1256 | mmu_spte_clear_track_bits(sptep); | |
1257 | mmu_spte_set(sptep, new_spte); | |
1258 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1259 | } |
1260 | } | |
1e3f42f0 | 1261 | |
3da0dd43 IE |
1262 | if (need_flush) |
1263 | kvm_flush_remote_tlbs(kvm); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
84504ef3 TY |
1268 | static int kvm_handle_hva_range(struct kvm *kvm, |
1269 | unsigned long start, | |
1270 | unsigned long end, | |
1271 | unsigned long data, | |
1272 | int (*handler)(struct kvm *kvm, | |
1273 | unsigned long *rmapp, | |
048212d0 | 1274 | struct kvm_memory_slot *slot, |
84504ef3 | 1275 | unsigned long data)) |
e930bffe | 1276 | { |
be6ba0f0 | 1277 | int j; |
f395302e | 1278 | int ret = 0; |
bc6678a3 | 1279 | struct kvm_memslots *slots; |
be6ba0f0 | 1280 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1281 | |
90d83dc3 | 1282 | slots = kvm_memslots(kvm); |
e930bffe | 1283 | |
be6ba0f0 | 1284 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1285 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1286 | gfn_t gfn_start, gfn_end; |
e930bffe | 1287 | |
84504ef3 TY |
1288 | hva_start = max(start, memslot->userspace_addr); |
1289 | hva_end = min(end, memslot->userspace_addr + | |
1290 | (memslot->npages << PAGE_SHIFT)); | |
1291 | if (hva_start >= hva_end) | |
1292 | continue; | |
1293 | /* | |
1294 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1295 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1296 | */ |
bcd3ef58 | 1297 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1298 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1299 | |
bcd3ef58 TY |
1300 | for (j = PT_PAGE_TABLE_LEVEL; |
1301 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1302 | unsigned long idx, idx_end; | |
1303 | unsigned long *rmapp; | |
d4dbf470 | 1304 | |
bcd3ef58 TY |
1305 | /* |
1306 | * {idx(page_j) | page_j intersects with | |
1307 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1308 | */ | |
1309 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1310 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1311 | |
bcd3ef58 | 1312 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1313 | |
bcd3ef58 TY |
1314 | for (; idx <= idx_end; ++idx) |
1315 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1316 | } |
1317 | } | |
1318 | ||
f395302e | 1319 | return ret; |
e930bffe AA |
1320 | } |
1321 | ||
84504ef3 TY |
1322 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1323 | unsigned long data, | |
1324 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1325 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1326 | unsigned long data)) |
1327 | { | |
1328 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1329 | } |
1330 | ||
1331 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1332 | { | |
3da0dd43 IE |
1333 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1334 | } | |
1335 | ||
b3ae2096 TY |
1336 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1337 | { | |
1338 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1339 | } | |
1340 | ||
3da0dd43 IE |
1341 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1342 | { | |
8a8365c5 | 1343 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1344 | } |
1345 | ||
8a8365c5 | 1346 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1347 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1348 | { |
1e3f42f0 | 1349 | u64 *sptep; |
79f702a6 | 1350 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1351 | int young = 0; |
1352 | ||
6316e1c8 | 1353 | /* |
3f6d8c8a XH |
1354 | * In case of absence of EPT Access and Dirty Bits supports, |
1355 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1356 | * an EPT mapping, and clearing it if it does. On the next access, |
1357 | * a new EPT mapping will be established. | |
1358 | * This has some overhead, but not as much as the cost of swapping | |
1359 | * out actively used pages or breaking up actively used hugepages. | |
1360 | */ | |
f395302e TY |
1361 | if (!shadow_accessed_mask) { |
1362 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1363 | goto out; | |
1364 | } | |
534e38b4 | 1365 | |
1e3f42f0 TY |
1366 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1367 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1368 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1369 | |
3f6d8c8a | 1370 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1371 | young = 1; |
3f6d8c8a XH |
1372 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1373 | (unsigned long *)sptep); | |
e930bffe | 1374 | } |
e930bffe | 1375 | } |
f395302e TY |
1376 | out: |
1377 | /* @data has hva passed to kvm_age_hva(). */ | |
1378 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1379 | return young; |
1380 | } | |
1381 | ||
8ee53820 | 1382 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1383 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1384 | { |
1e3f42f0 TY |
1385 | u64 *sptep; |
1386 | struct rmap_iterator iter; | |
8ee53820 AA |
1387 | int young = 0; |
1388 | ||
1389 | /* | |
1390 | * If there's no access bit in the secondary pte set by the | |
1391 | * hardware it's up to gup-fast/gup to set the access bit in | |
1392 | * the primary pte or in the page structure. | |
1393 | */ | |
1394 | if (!shadow_accessed_mask) | |
1395 | goto out; | |
1396 | ||
1e3f42f0 TY |
1397 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1398 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1399 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1400 | |
3f6d8c8a | 1401 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1402 | young = 1; |
1403 | break; | |
1404 | } | |
8ee53820 AA |
1405 | } |
1406 | out: | |
1407 | return young; | |
1408 | } | |
1409 | ||
53a27b39 MT |
1410 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1411 | ||
852e3c19 | 1412 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1413 | { |
1414 | unsigned long *rmapp; | |
852e3c19 JR |
1415 | struct kvm_mmu_page *sp; |
1416 | ||
1417 | sp = page_header(__pa(spte)); | |
53a27b39 | 1418 | |
852e3c19 | 1419 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1420 | |
048212d0 | 1421 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1422 | kvm_flush_remote_tlbs(vcpu->kvm); |
1423 | } | |
1424 | ||
e930bffe AA |
1425 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1426 | { | |
f395302e | 1427 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1428 | } |
1429 | ||
8ee53820 AA |
1430 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1431 | { | |
1432 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1433 | } | |
1434 | ||
d6c69ee9 | 1435 | #ifdef MMU_DEBUG |
47ad8e68 | 1436 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1437 | { |
139bdb2d AK |
1438 | u64 *pos; |
1439 | u64 *end; | |
1440 | ||
47ad8e68 | 1441 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1442 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1443 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1444 | pos, *pos); |
6aa8b732 | 1445 | return 0; |
139bdb2d | 1446 | } |
6aa8b732 AK |
1447 | return 1; |
1448 | } | |
d6c69ee9 | 1449 | #endif |
6aa8b732 | 1450 | |
45221ab6 DH |
1451 | /* |
1452 | * This value is the sum of all of the kvm instances's | |
1453 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1454 | * aggregate version in order to make the slab shrinker | |
1455 | * faster | |
1456 | */ | |
1457 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1458 | { | |
1459 | kvm->arch.n_used_mmu_pages += nr; | |
1460 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1461 | } | |
1462 | ||
834be0d8 | 1463 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1464 | { |
4db35314 | 1465 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1466 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1467 | list_del(&sp->link); |
1468 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1469 | if (!sp->role.direct) |
1470 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1471 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1472 | } |
1473 | ||
cea0f0e7 AK |
1474 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1475 | { | |
1ae0a13d | 1476 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1477 | } |
1478 | ||
714b93da | 1479 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1480 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1481 | { |
cea0f0e7 AK |
1482 | if (!parent_pte) |
1483 | return; | |
cea0f0e7 | 1484 | |
67052b35 | 1485 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1486 | } |
1487 | ||
4db35314 | 1488 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1489 | u64 *parent_pte) |
1490 | { | |
67052b35 | 1491 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1492 | } |
1493 | ||
bcdd9a93 XG |
1494 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1495 | u64 *parent_pte) | |
1496 | { | |
1497 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1498 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1499 | } |
1500 | ||
67052b35 XG |
1501 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1502 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1503 | { |
67052b35 | 1504 | struct kvm_mmu_page *sp; |
80feb89a TY |
1505 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1506 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1507 | if (!direct) |
80feb89a | 1508 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 XG |
1509 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
1510 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
67052b35 XG |
1511 | sp->parent_ptes = 0; |
1512 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1513 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1514 | return sp; | |
ad8cfbe3 MT |
1515 | } |
1516 | ||
67052b35 | 1517 | static void mark_unsync(u64 *spte); |
1047df1f | 1518 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1519 | { |
67052b35 | 1520 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1521 | } |
1522 | ||
67052b35 | 1523 | static void mark_unsync(u64 *spte) |
0074ff63 | 1524 | { |
67052b35 | 1525 | struct kvm_mmu_page *sp; |
1047df1f | 1526 | unsigned int index; |
0074ff63 | 1527 | |
67052b35 | 1528 | sp = page_header(__pa(spte)); |
1047df1f XG |
1529 | index = spte - sp->spt; |
1530 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1531 | return; |
1047df1f | 1532 | if (sp->unsync_children++) |
0074ff63 | 1533 | return; |
1047df1f | 1534 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1535 | } |
1536 | ||
e8bc217a | 1537 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1538 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1539 | { |
1540 | return 1; | |
1541 | } | |
1542 | ||
a7052897 MT |
1543 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1544 | { | |
1545 | } | |
1546 | ||
0f53b5b1 XG |
1547 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1548 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1549 | const void *pte) |
0f53b5b1 XG |
1550 | { |
1551 | WARN_ON(1); | |
1552 | } | |
1553 | ||
60c8aec6 MT |
1554 | #define KVM_PAGE_ARRAY_NR 16 |
1555 | ||
1556 | struct kvm_mmu_pages { | |
1557 | struct mmu_page_and_offset { | |
1558 | struct kvm_mmu_page *sp; | |
1559 | unsigned int idx; | |
1560 | } page[KVM_PAGE_ARRAY_NR]; | |
1561 | unsigned int nr; | |
1562 | }; | |
1563 | ||
cded19f3 HE |
1564 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1565 | int idx) | |
4731d4c7 | 1566 | { |
60c8aec6 | 1567 | int i; |
4731d4c7 | 1568 | |
60c8aec6 MT |
1569 | if (sp->unsync) |
1570 | for (i=0; i < pvec->nr; i++) | |
1571 | if (pvec->page[i].sp == sp) | |
1572 | return 0; | |
1573 | ||
1574 | pvec->page[pvec->nr].sp = sp; | |
1575 | pvec->page[pvec->nr].idx = idx; | |
1576 | pvec->nr++; | |
1577 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1578 | } | |
1579 | ||
1580 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1581 | struct kvm_mmu_pages *pvec) | |
1582 | { | |
1583 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1584 | |
37178b8b | 1585 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1586 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1587 | u64 ent = sp->spt[i]; |
1588 | ||
7a8f1a74 XG |
1589 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1590 | goto clear_child_bitmap; | |
1591 | ||
1592 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1593 | ||
1594 | if (child->unsync_children) { | |
1595 | if (mmu_pages_add(pvec, child, i)) | |
1596 | return -ENOSPC; | |
1597 | ||
1598 | ret = __mmu_unsync_walk(child, pvec); | |
1599 | if (!ret) | |
1600 | goto clear_child_bitmap; | |
1601 | else if (ret > 0) | |
1602 | nr_unsync_leaf += ret; | |
1603 | else | |
1604 | return ret; | |
1605 | } else if (child->unsync) { | |
1606 | nr_unsync_leaf++; | |
1607 | if (mmu_pages_add(pvec, child, i)) | |
1608 | return -ENOSPC; | |
1609 | } else | |
1610 | goto clear_child_bitmap; | |
1611 | ||
1612 | continue; | |
1613 | ||
1614 | clear_child_bitmap: | |
1615 | __clear_bit(i, sp->unsync_child_bitmap); | |
1616 | sp->unsync_children--; | |
1617 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1618 | } |
1619 | ||
4731d4c7 | 1620 | |
60c8aec6 MT |
1621 | return nr_unsync_leaf; |
1622 | } | |
1623 | ||
1624 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1625 | struct kvm_mmu_pages *pvec) | |
1626 | { | |
1627 | if (!sp->unsync_children) | |
1628 | return 0; | |
1629 | ||
1630 | mmu_pages_add(pvec, sp, 0); | |
1631 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1632 | } |
1633 | ||
4731d4c7 MT |
1634 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1635 | { | |
1636 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1637 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1638 | sp->unsync = 0; |
1639 | --kvm->stat.mmu_unsync; | |
1640 | } | |
1641 | ||
7775834a XG |
1642 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1643 | struct list_head *invalid_list); | |
1644 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1645 | struct list_head *invalid_list); | |
4731d4c7 | 1646 | |
1044b030 TY |
1647 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1648 | hlist_for_each_entry(_sp, \ | |
1649 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1650 | if ((_sp)->gfn != (_gfn)) {} else | |
1651 | ||
1652 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1653 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1654 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1655 | |
f918b443 | 1656 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1657 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1658 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1659 | { |
5b7e0102 | 1660 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1661 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1662 | return 1; |
1663 | } | |
1664 | ||
f918b443 | 1665 | if (clear_unsync) |
1d9dc7e0 | 1666 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1667 | |
a4a8e6f7 | 1668 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1669 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1670 | return 1; |
1671 | } | |
1672 | ||
1673 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1674 | return 0; |
1675 | } | |
1676 | ||
1d9dc7e0 XG |
1677 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1678 | struct kvm_mmu_page *sp) | |
1679 | { | |
d98ba053 | 1680 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1681 | int ret; |
1682 | ||
d98ba053 | 1683 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1684 | if (ret) |
d98ba053 XG |
1685 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1686 | ||
1d9dc7e0 XG |
1687 | return ret; |
1688 | } | |
1689 | ||
e37fa785 XG |
1690 | #ifdef CONFIG_KVM_MMU_AUDIT |
1691 | #include "mmu_audit.c" | |
1692 | #else | |
1693 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1694 | static void mmu_audit_disable(void) { } | |
1695 | #endif | |
1696 | ||
d98ba053 XG |
1697 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1698 | struct list_head *invalid_list) | |
1d9dc7e0 | 1699 | { |
d98ba053 | 1700 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1701 | } |
1702 | ||
9f1a122f XG |
1703 | /* @gfn should be write-protected at the call site */ |
1704 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1705 | { | |
9f1a122f | 1706 | struct kvm_mmu_page *s; |
d98ba053 | 1707 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1708 | bool flush = false; |
1709 | ||
b67bfe0d | 1710 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1711 | if (!s->unsync) |
9f1a122f XG |
1712 | continue; |
1713 | ||
1714 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1715 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1716 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1717 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1718 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1719 | continue; |
1720 | } | |
9f1a122f XG |
1721 | flush = true; |
1722 | } | |
1723 | ||
d98ba053 | 1724 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1725 | if (flush) |
1726 | kvm_mmu_flush_tlb(vcpu); | |
1727 | } | |
1728 | ||
60c8aec6 MT |
1729 | struct mmu_page_path { |
1730 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1731 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1732 | }; |
1733 | ||
60c8aec6 MT |
1734 | #define for_each_sp(pvec, sp, parents, i) \ |
1735 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1736 | sp = pvec.page[i].sp; \ | |
1737 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1738 | i = mmu_pages_next(&pvec, &parents, i)) | |
1739 | ||
cded19f3 HE |
1740 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1741 | struct mmu_page_path *parents, | |
1742 | int i) | |
60c8aec6 MT |
1743 | { |
1744 | int n; | |
1745 | ||
1746 | for (n = i+1; n < pvec->nr; n++) { | |
1747 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1748 | ||
1749 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1750 | parents->idx[0] = pvec->page[n].idx; | |
1751 | return n; | |
1752 | } | |
1753 | ||
1754 | parents->parent[sp->role.level-2] = sp; | |
1755 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1756 | } | |
1757 | ||
1758 | return n; | |
1759 | } | |
1760 | ||
cded19f3 | 1761 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1762 | { |
60c8aec6 MT |
1763 | struct kvm_mmu_page *sp; |
1764 | unsigned int level = 0; | |
1765 | ||
1766 | do { | |
1767 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1768 | |
60c8aec6 MT |
1769 | sp = parents->parent[level]; |
1770 | if (!sp) | |
1771 | return; | |
1772 | ||
1773 | --sp->unsync_children; | |
1774 | WARN_ON((int)sp->unsync_children < 0); | |
1775 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1776 | level++; | |
1777 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1778 | } |
1779 | ||
60c8aec6 MT |
1780 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1781 | struct mmu_page_path *parents, | |
1782 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1783 | { |
60c8aec6 MT |
1784 | parents->parent[parent->role.level-1] = NULL; |
1785 | pvec->nr = 0; | |
1786 | } | |
4731d4c7 | 1787 | |
60c8aec6 MT |
1788 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1789 | struct kvm_mmu_page *parent) | |
1790 | { | |
1791 | int i; | |
1792 | struct kvm_mmu_page *sp; | |
1793 | struct mmu_page_path parents; | |
1794 | struct kvm_mmu_pages pages; | |
d98ba053 | 1795 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1796 | |
1797 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1798 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1799 | bool protected = false; |
b1a36821 MT |
1800 | |
1801 | for_each_sp(pages, sp, parents, i) | |
1802 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1803 | ||
1804 | if (protected) | |
1805 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1806 | ||
60c8aec6 | 1807 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1808 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1809 | mmu_pages_clear_parents(&parents); |
1810 | } | |
d98ba053 | 1811 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1812 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1813 | kvm_mmu_pages_init(parent, &parents, &pages); |
1814 | } | |
4731d4c7 MT |
1815 | } |
1816 | ||
c3707958 XG |
1817 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1818 | { | |
1819 | int i; | |
1820 | ||
1821 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1822 | sp->spt[i] = 0ull; | |
1823 | } | |
1824 | ||
a30f47cb XG |
1825 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1826 | { | |
1827 | sp->write_flooding_count = 0; | |
1828 | } | |
1829 | ||
1830 | static void clear_sp_write_flooding_count(u64 *spte) | |
1831 | { | |
1832 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1833 | ||
1834 | __clear_sp_write_flooding_count(sp); | |
1835 | } | |
1836 | ||
cea0f0e7 AK |
1837 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1838 | gfn_t gfn, | |
1839 | gva_t gaddr, | |
1840 | unsigned level, | |
f6e2c02b | 1841 | int direct, |
41074d07 | 1842 | unsigned access, |
f7d9c7b7 | 1843 | u64 *parent_pte) |
cea0f0e7 AK |
1844 | { |
1845 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1846 | unsigned quadrant; |
9f1a122f | 1847 | struct kvm_mmu_page *sp; |
9f1a122f | 1848 | bool need_sync = false; |
cea0f0e7 | 1849 | |
a770f6f2 | 1850 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1851 | role.level = level; |
f6e2c02b | 1852 | role.direct = direct; |
84b0c8c6 | 1853 | if (role.direct) |
5b7e0102 | 1854 | role.cr4_pae = 0; |
41074d07 | 1855 | role.access = access; |
c5a78f2b JR |
1856 | if (!vcpu->arch.mmu.direct_map |
1857 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1858 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1859 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1860 | role.quadrant = quadrant; | |
1861 | } | |
b67bfe0d | 1862 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7ae680eb XG |
1863 | if (!need_sync && sp->unsync) |
1864 | need_sync = true; | |
4731d4c7 | 1865 | |
7ae680eb XG |
1866 | if (sp->role.word != role.word) |
1867 | continue; | |
4731d4c7 | 1868 | |
7ae680eb XG |
1869 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1870 | break; | |
e02aa901 | 1871 | |
7ae680eb XG |
1872 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1873 | if (sp->unsync_children) { | |
a8eeb04a | 1874 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1875 | kvm_mmu_mark_parents_unsync(sp); |
1876 | } else if (sp->unsync) | |
1877 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1878 | |
a30f47cb | 1879 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1880 | trace_kvm_mmu_get_page(sp, false); |
1881 | return sp; | |
1882 | } | |
dfc5aa00 | 1883 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1884 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1885 | if (!sp) |
1886 | return sp; | |
4db35314 AK |
1887 | sp->gfn = gfn; |
1888 | sp->role = role; | |
7ae680eb XG |
1889 | hlist_add_head(&sp->hash_link, |
1890 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1891 | if (!direct) { |
b1a36821 MT |
1892 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1893 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1894 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1895 | kvm_sync_pages(vcpu, gfn); | |
1896 | ||
4731d4c7 MT |
1897 | account_shadowed(vcpu->kvm, gfn); |
1898 | } | |
c3707958 | 1899 | init_shadow_page_table(sp); |
f691fe1d | 1900 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1901 | return sp; |
cea0f0e7 AK |
1902 | } |
1903 | ||
2d11123a AK |
1904 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1905 | struct kvm_vcpu *vcpu, u64 addr) | |
1906 | { | |
1907 | iterator->addr = addr; | |
1908 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1909 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1910 | |
1911 | if (iterator->level == PT64_ROOT_LEVEL && | |
1912 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1913 | !vcpu->arch.mmu.direct_map) | |
1914 | --iterator->level; | |
1915 | ||
2d11123a AK |
1916 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1917 | iterator->shadow_addr | |
1918 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1919 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1920 | --iterator->level; | |
1921 | if (!iterator->shadow_addr) | |
1922 | iterator->level = 0; | |
1923 | } | |
1924 | } | |
1925 | ||
1926 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1927 | { | |
1928 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1929 | return false; | |
4d88954d | 1930 | |
2d11123a AK |
1931 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1932 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1933 | return true; | |
1934 | } | |
1935 | ||
c2a2ac2b XG |
1936 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1937 | u64 spte) | |
2d11123a | 1938 | { |
c2a2ac2b | 1939 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1940 | iterator->level = 0; |
1941 | return; | |
1942 | } | |
1943 | ||
c2a2ac2b | 1944 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1945 | --iterator->level; |
1946 | } | |
1947 | ||
c2a2ac2b XG |
1948 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1949 | { | |
1950 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1951 | } | |
1952 | ||
32ef26a3 AK |
1953 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1954 | { | |
1955 | u64 spte; | |
1956 | ||
24db2734 XG |
1957 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
1958 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; | |
1959 | ||
1df9f2dc | 1960 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1961 | } |
1962 | ||
a357bd22 AK |
1963 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1964 | unsigned direct_access) | |
1965 | { | |
1966 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1967 | struct kvm_mmu_page *child; | |
1968 | ||
1969 | /* | |
1970 | * For the direct sp, if the guest pte's dirty bit | |
1971 | * changed form clean to dirty, it will corrupt the | |
1972 | * sp's access: allow writable in the read-only sp, | |
1973 | * so we should update the spte at this point to get | |
1974 | * a new sp with the correct access. | |
1975 | */ | |
1976 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1977 | if (child->role.access == direct_access) | |
1978 | return; | |
1979 | ||
bcdd9a93 | 1980 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1981 | kvm_flush_remote_tlbs(vcpu->kvm); |
1982 | } | |
1983 | } | |
1984 | ||
505aef8f | 1985 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
1986 | u64 *spte) |
1987 | { | |
1988 | u64 pte; | |
1989 | struct kvm_mmu_page *child; | |
1990 | ||
1991 | pte = *spte; | |
1992 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 1993 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 1994 | drop_spte(kvm, spte); |
505aef8f XG |
1995 | if (is_large_pte(pte)) |
1996 | --kvm->stat.lpages; | |
1997 | } else { | |
38e3b2b2 | 1998 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 1999 | drop_parent_pte(child, spte); |
38e3b2b2 | 2000 | } |
505aef8f XG |
2001 | return true; |
2002 | } | |
2003 | ||
2004 | if (is_mmio_spte(pte)) | |
ce88decf | 2005 | mmu_spte_clear_no_track(spte); |
c3707958 | 2006 | |
505aef8f | 2007 | return false; |
38e3b2b2 XG |
2008 | } |
2009 | ||
90cb0529 | 2010 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2011 | struct kvm_mmu_page *sp) |
a436036b | 2012 | { |
697fe2e2 | 2013 | unsigned i; |
697fe2e2 | 2014 | |
38e3b2b2 XG |
2015 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2016 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2017 | } |
2018 | ||
4db35314 | 2019 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2020 | { |
4db35314 | 2021 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2022 | } |
2023 | ||
31aa2b44 | 2024 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2025 | { |
1e3f42f0 TY |
2026 | u64 *sptep; |
2027 | struct rmap_iterator iter; | |
a436036b | 2028 | |
1e3f42f0 TY |
2029 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2030 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2031 | } |
2032 | ||
60c8aec6 | 2033 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2034 | struct kvm_mmu_page *parent, |
2035 | struct list_head *invalid_list) | |
4731d4c7 | 2036 | { |
60c8aec6 MT |
2037 | int i, zapped = 0; |
2038 | struct mmu_page_path parents; | |
2039 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2040 | |
60c8aec6 | 2041 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2042 | return 0; |
60c8aec6 MT |
2043 | |
2044 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2045 | while (mmu_unsync_walk(parent, &pages)) { | |
2046 | struct kvm_mmu_page *sp; | |
2047 | ||
2048 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2049 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2050 | mmu_pages_clear_parents(&parents); |
77662e00 | 2051 | zapped++; |
60c8aec6 | 2052 | } |
60c8aec6 MT |
2053 | kvm_mmu_pages_init(parent, &parents, &pages); |
2054 | } | |
2055 | ||
2056 | return zapped; | |
4731d4c7 MT |
2057 | } |
2058 | ||
7775834a XG |
2059 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2060 | struct list_head *invalid_list) | |
31aa2b44 | 2061 | { |
4731d4c7 | 2062 | int ret; |
f691fe1d | 2063 | |
7775834a | 2064 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2065 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2066 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2067 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2068 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 2069 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2070 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
2071 | if (sp->unsync) |
2072 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2073 | if (!sp->root_count) { |
54a4f023 GJ |
2074 | /* Count self */ |
2075 | ret++; | |
7775834a | 2076 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2077 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2078 | } else { |
5b5c6a5a | 2079 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
2080 | kvm_reload_remote_mmus(kvm); |
2081 | } | |
7775834a XG |
2082 | |
2083 | sp->role.invalid = 1; | |
4731d4c7 | 2084 | return ret; |
a436036b AK |
2085 | } |
2086 | ||
7775834a XG |
2087 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2088 | struct list_head *invalid_list) | |
2089 | { | |
2090 | struct kvm_mmu_page *sp; | |
2091 | ||
2092 | if (list_empty(invalid_list)) | |
2093 | return; | |
2094 | ||
c142786c AK |
2095 | /* |
2096 | * wmb: make sure everyone sees our modifications to the page tables | |
2097 | * rmb: make sure we see changes to vcpu->mode | |
2098 | */ | |
2099 | smp_mb(); | |
4f022648 | 2100 | |
c142786c AK |
2101 | /* |
2102 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2103 | * page table walks. | |
2104 | */ | |
2105 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2106 | |
7775834a XG |
2107 | do { |
2108 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
2109 | WARN_ON(!sp->role.invalid || sp->root_count); | |
aa6bd187 | 2110 | kvm_mmu_free_page(sp); |
7775834a | 2111 | } while (!list_empty(invalid_list)); |
7775834a XG |
2112 | } |
2113 | ||
82ce2c96 IE |
2114 | /* |
2115 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2116 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2117 | */ |
49d5ca26 | 2118 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2119 | { |
d98ba053 | 2120 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
2121 | /* |
2122 | * If we set the number of mmu pages to be smaller be than the | |
2123 | * number of actived pages , we must to free some mmu pages before we | |
2124 | * change the value | |
2125 | */ | |
2126 | ||
b34cb590 TY |
2127 | spin_lock(&kvm->mmu_lock); |
2128 | ||
49d5ca26 DH |
2129 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
2130 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 2131 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
2132 | struct kvm_mmu_page *page; |
2133 | ||
f05e70ac | 2134 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 2135 | struct kvm_mmu_page, link); |
80b63faf | 2136 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 2137 | } |
aa6bd187 | 2138 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2139 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2140 | } |
82ce2c96 | 2141 | |
49d5ca26 | 2142 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2143 | |
2144 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2145 | } |
2146 | ||
1cb3f3ae | 2147 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2148 | { |
4db35314 | 2149 | struct kvm_mmu_page *sp; |
d98ba053 | 2150 | LIST_HEAD(invalid_list); |
a436036b AK |
2151 | int r; |
2152 | ||
9ad17b10 | 2153 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2154 | r = 0; |
1cb3f3ae | 2155 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2156 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2157 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2158 | sp->role.word); |
2159 | r = 1; | |
f41d335a | 2160 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2161 | } |
d98ba053 | 2162 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2163 | spin_unlock(&kvm->mmu_lock); |
2164 | ||
a436036b | 2165 | return r; |
cea0f0e7 | 2166 | } |
1cb3f3ae | 2167 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2168 | |
74be52e3 SY |
2169 | /* |
2170 | * The function is based on mtrr_type_lookup() in | |
2171 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2172 | */ | |
2173 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2174 | u64 start, u64 end) | |
2175 | { | |
2176 | int i; | |
2177 | u64 base, mask; | |
2178 | u8 prev_match, curr_match; | |
2179 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2180 | ||
2181 | if (!mtrr_state->enabled) | |
2182 | return 0xFF; | |
2183 | ||
2184 | /* Make end inclusive end, instead of exclusive */ | |
2185 | end--; | |
2186 | ||
2187 | /* Look in fixed ranges. Just return the type as per start */ | |
2188 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2189 | int idx; | |
2190 | ||
2191 | if (start < 0x80000) { | |
2192 | idx = 0; | |
2193 | idx += (start >> 16); | |
2194 | return mtrr_state->fixed_ranges[idx]; | |
2195 | } else if (start < 0xC0000) { | |
2196 | idx = 1 * 8; | |
2197 | idx += ((start - 0x80000) >> 14); | |
2198 | return mtrr_state->fixed_ranges[idx]; | |
2199 | } else if (start < 0x1000000) { | |
2200 | idx = 3 * 8; | |
2201 | idx += ((start - 0xC0000) >> 12); | |
2202 | return mtrr_state->fixed_ranges[idx]; | |
2203 | } | |
2204 | } | |
2205 | ||
2206 | /* | |
2207 | * Look in variable ranges | |
2208 | * Look of multiple ranges matching this address and pick type | |
2209 | * as per MTRR precedence | |
2210 | */ | |
2211 | if (!(mtrr_state->enabled & 2)) | |
2212 | return mtrr_state->def_type; | |
2213 | ||
2214 | prev_match = 0xFF; | |
2215 | for (i = 0; i < num_var_ranges; ++i) { | |
2216 | unsigned short start_state, end_state; | |
2217 | ||
2218 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2219 | continue; | |
2220 | ||
2221 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2222 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2223 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2224 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2225 | ||
2226 | start_state = ((start & mask) == (base & mask)); | |
2227 | end_state = ((end & mask) == (base & mask)); | |
2228 | if (start_state != end_state) | |
2229 | return 0xFE; | |
2230 | ||
2231 | if ((start & mask) != (base & mask)) | |
2232 | continue; | |
2233 | ||
2234 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2235 | if (prev_match == 0xFF) { | |
2236 | prev_match = curr_match; | |
2237 | continue; | |
2238 | } | |
2239 | ||
2240 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2241 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2242 | return MTRR_TYPE_UNCACHABLE; | |
2243 | ||
2244 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2245 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2246 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2247 | curr_match == MTRR_TYPE_WRBACK)) { | |
2248 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2249 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2250 | } | |
2251 | ||
2252 | if (prev_match != curr_match) | |
2253 | return MTRR_TYPE_UNCACHABLE; | |
2254 | } | |
2255 | ||
2256 | if (prev_match != 0xFF) | |
2257 | return prev_match; | |
2258 | ||
2259 | return mtrr_state->def_type; | |
2260 | } | |
2261 | ||
4b12f0de | 2262 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2263 | { |
2264 | u8 mtrr; | |
2265 | ||
2266 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2267 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2268 | if (mtrr == 0xfe || mtrr == 0xff) | |
2269 | mtrr = MTRR_TYPE_WRBACK; | |
2270 | return mtrr; | |
2271 | } | |
4b12f0de | 2272 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2273 | |
9cf5cf5a XG |
2274 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2275 | { | |
2276 | trace_kvm_mmu_unsync_page(sp); | |
2277 | ++vcpu->kvm->stat.mmu_unsync; | |
2278 | sp->unsync = 1; | |
2279 | ||
2280 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2281 | } |
2282 | ||
2283 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2284 | { |
4731d4c7 | 2285 | struct kvm_mmu_page *s; |
9cf5cf5a | 2286 | |
b67bfe0d | 2287 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2288 | if (s->unsync) |
4731d4c7 | 2289 | continue; |
9cf5cf5a XG |
2290 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2291 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2292 | } |
4731d4c7 MT |
2293 | } |
2294 | ||
2295 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2296 | bool can_unsync) | |
2297 | { | |
9cf5cf5a | 2298 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2299 | bool need_unsync = false; |
2300 | ||
b67bfe0d | 2301 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2302 | if (!can_unsync) |
2303 | return 1; | |
2304 | ||
9cf5cf5a | 2305 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2306 | return 1; |
9cf5cf5a | 2307 | |
9bb4f6b1 | 2308 | if (!s->unsync) |
9cf5cf5a | 2309 | need_unsync = true; |
4731d4c7 | 2310 | } |
9cf5cf5a XG |
2311 | if (need_unsync) |
2312 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2313 | return 0; |
2314 | } | |
2315 | ||
d555c333 | 2316 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2317 | unsigned pte_access, int level, |
c2d0ee46 | 2318 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2319 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2320 | { |
6e7d0354 | 2321 | u64 spte; |
1e73f9dd | 2322 | int ret = 0; |
64d4d521 | 2323 | |
ce88decf XG |
2324 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2325 | return 0; | |
2326 | ||
982c2565 | 2327 | spte = PT_PRESENT_MASK; |
947da538 | 2328 | if (!speculative) |
3201b5d9 | 2329 | spte |= shadow_accessed_mask; |
640d9b0d | 2330 | |
7b52345e SY |
2331 | if (pte_access & ACC_EXEC_MASK) |
2332 | spte |= shadow_x_mask; | |
2333 | else | |
2334 | spte |= shadow_nx_mask; | |
49fde340 | 2335 | |
1c4f1fd6 | 2336 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2337 | spte |= shadow_user_mask; |
49fde340 | 2338 | |
852e3c19 | 2339 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2340 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2341 | if (tdp_enabled) |
4b12f0de SY |
2342 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2343 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2344 | |
9bdbba13 | 2345 | if (host_writable) |
1403283a | 2346 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2347 | else |
2348 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2349 | |
35149e21 | 2350 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2351 | |
c2288505 | 2352 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2353 | |
c2193463 | 2354 | /* |
7751babd XG |
2355 | * Other vcpu creates new sp in the window between |
2356 | * mapping_level() and acquiring mmu-lock. We can | |
2357 | * allow guest to retry the access, the mapping can | |
2358 | * be fixed if guest refault. | |
c2193463 | 2359 | */ |
852e3c19 | 2360 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2361 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2362 | goto done; |
38187c83 | 2363 | |
49fde340 | 2364 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2365 | |
ecc5589f MT |
2366 | /* |
2367 | * Optimization: for pte sync, if spte was writable the hash | |
2368 | * lookup is unnecessary (and expensive). Write protection | |
2369 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2370 | * Same reasoning can be applied to dirty page accounting. | |
2371 | */ | |
8dae4445 | 2372 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2373 | goto set_pte; |
2374 | ||
4731d4c7 | 2375 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2376 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2377 | __func__, gfn); |
1e73f9dd | 2378 | ret = 1; |
1c4f1fd6 | 2379 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2380 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2381 | } |
2382 | } | |
2383 | ||
1c4f1fd6 AK |
2384 | if (pte_access & ACC_WRITE_MASK) |
2385 | mark_page_dirty(vcpu->kvm, gfn); | |
2386 | ||
38187c83 | 2387 | set_pte: |
6e7d0354 | 2388 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2389 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2390 | done: |
1e73f9dd MT |
2391 | return ret; |
2392 | } | |
2393 | ||
d555c333 | 2394 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2395 | unsigned pte_access, int write_fault, int *emulate, |
2396 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2397 | bool host_writable) | |
1e73f9dd MT |
2398 | { |
2399 | int was_rmapped = 0; | |
53a27b39 | 2400 | int rmap_count; |
1e73f9dd | 2401 | |
f7616203 XG |
2402 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2403 | *sptep, write_fault, gfn); | |
1e73f9dd | 2404 | |
d555c333 | 2405 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2406 | /* |
2407 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2408 | * the parent of the now unreachable PTE. | |
2409 | */ | |
852e3c19 JR |
2410 | if (level > PT_PAGE_TABLE_LEVEL && |
2411 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2412 | struct kvm_mmu_page *child; |
d555c333 | 2413 | u64 pte = *sptep; |
1e73f9dd MT |
2414 | |
2415 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2416 | drop_parent_pte(child, sptep); |
3be2264b | 2417 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2418 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2419 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2420 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2421 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2422 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2423 | } else |
2424 | was_rmapped = 1; | |
1e73f9dd | 2425 | } |
852e3c19 | 2426 | |
c2288505 XG |
2427 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2428 | true, host_writable)) { | |
1e73f9dd | 2429 | if (write_fault) |
b90a0e6c | 2430 | *emulate = 1; |
5304efde | 2431 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2432 | } |
1e73f9dd | 2433 | |
ce88decf XG |
2434 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2435 | *emulate = 1; | |
2436 | ||
d555c333 | 2437 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2438 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2439 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2440 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2441 | *sptep, sptep); | |
d555c333 | 2442 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2443 | ++vcpu->kvm->stat.lpages; |
2444 | ||
ffb61bb3 | 2445 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2446 | if (!was_rmapped) { |
2447 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2448 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2449 | rmap_recycle(vcpu, sptep, gfn); | |
2450 | } | |
1c4f1fd6 | 2451 | } |
cb9aaa30 | 2452 | |
f3ac1a4b | 2453 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2454 | } |
2455 | ||
6aa8b732 AK |
2456 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2457 | { | |
e676505a | 2458 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2459 | } |
2460 | ||
a052b42b XG |
2461 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2462 | { | |
2463 | int bit7; | |
2464 | ||
2465 | bit7 = (gpte >> 7) & 1; | |
2466 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2467 | } | |
2468 | ||
957ed9ef XG |
2469 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2470 | bool no_dirty_log) | |
2471 | { | |
2472 | struct kvm_memory_slot *slot; | |
957ed9ef | 2473 | |
5d163b1c | 2474 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2475 | if (!slot) |
6c8ee57b | 2476 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2477 | |
037d92dc | 2478 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2479 | } |
2480 | ||
a052b42b XG |
2481 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2482 | struct kvm_mmu_page *sp, u64 *spte, | |
2483 | u64 gpte) | |
2484 | { | |
2485 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2486 | goto no_present; | |
2487 | ||
2488 | if (!is_present_gpte(gpte)) | |
2489 | goto no_present; | |
2490 | ||
2491 | if (!(gpte & PT_ACCESSED_MASK)) | |
2492 | goto no_present; | |
2493 | ||
2494 | return false; | |
2495 | ||
2496 | no_present: | |
2497 | drop_spte(vcpu->kvm, spte); | |
2498 | return true; | |
2499 | } | |
2500 | ||
957ed9ef XG |
2501 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2502 | struct kvm_mmu_page *sp, | |
2503 | u64 *start, u64 *end) | |
2504 | { | |
2505 | struct page *pages[PTE_PREFETCH_NUM]; | |
2506 | unsigned access = sp->role.access; | |
2507 | int i, ret; | |
2508 | gfn_t gfn; | |
2509 | ||
2510 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2511 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2512 | return -1; |
2513 | ||
2514 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2515 | if (ret <= 0) | |
2516 | return -1; | |
2517 | ||
2518 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2519 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2520 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2521 | true, true); | |
957ed9ef XG |
2522 | |
2523 | return 0; | |
2524 | } | |
2525 | ||
2526 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2527 | struct kvm_mmu_page *sp, u64 *sptep) | |
2528 | { | |
2529 | u64 *spte, *start = NULL; | |
2530 | int i; | |
2531 | ||
2532 | WARN_ON(!sp->role.direct); | |
2533 | ||
2534 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2535 | spte = sp->spt + i; | |
2536 | ||
2537 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2538 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2539 | if (!start) |
2540 | continue; | |
2541 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2542 | break; | |
2543 | start = NULL; | |
2544 | } else if (!start) | |
2545 | start = spte; | |
2546 | } | |
2547 | } | |
2548 | ||
2549 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2550 | { | |
2551 | struct kvm_mmu_page *sp; | |
2552 | ||
2553 | /* | |
2554 | * Since it's no accessed bit on EPT, it's no way to | |
2555 | * distinguish between actually accessed translations | |
2556 | * and prefetched, so disable pte prefetch if EPT is | |
2557 | * enabled. | |
2558 | */ | |
2559 | if (!shadow_accessed_mask) | |
2560 | return; | |
2561 | ||
2562 | sp = page_header(__pa(sptep)); | |
2563 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2564 | return; | |
2565 | ||
2566 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2567 | } | |
2568 | ||
9f652d21 | 2569 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2570 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2571 | bool prefault) | |
140754bc | 2572 | { |
9f652d21 | 2573 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2574 | struct kvm_mmu_page *sp; |
b90a0e6c | 2575 | int emulate = 0; |
140754bc | 2576 | gfn_t pseudo_gfn; |
6aa8b732 | 2577 | |
9f652d21 | 2578 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2579 | if (iterator.level == level) { |
f7616203 | 2580 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2581 | write, &emulate, level, gfn, pfn, |
2582 | prefault, map_writable); | |
957ed9ef | 2583 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2584 | ++vcpu->stat.pf_fixed; |
2585 | break; | |
6aa8b732 AK |
2586 | } |
2587 | ||
c3707958 | 2588 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2589 | u64 base_addr = iterator.addr; |
2590 | ||
2591 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2592 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2593 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2594 | iterator.level - 1, | |
2595 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2596 | |
24db2734 | 2597 | link_shadow_page(iterator.sptep, sp); |
9f652d21 AK |
2598 | } |
2599 | } | |
b90a0e6c | 2600 | return emulate; |
6aa8b732 AK |
2601 | } |
2602 | ||
77db5cbd | 2603 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2604 | { |
77db5cbd HY |
2605 | siginfo_t info; |
2606 | ||
2607 | info.si_signo = SIGBUS; | |
2608 | info.si_errno = 0; | |
2609 | info.si_code = BUS_MCEERR_AR; | |
2610 | info.si_addr = (void __user *)address; | |
2611 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2612 | |
77db5cbd | 2613 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2614 | } |
2615 | ||
d7c55201 | 2616 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2617 | { |
4d8b81ab XG |
2618 | /* |
2619 | * Do not cache the mmio info caused by writing the readonly gfn | |
2620 | * into the spte otherwise read access on readonly gfn also can | |
2621 | * caused mmio page fault and treat it as mmio access. | |
2622 | * Return 1 to tell kvm to emulate it. | |
2623 | */ | |
2624 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2625 | return 1; | |
2626 | ||
e6c1502b | 2627 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2628 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2629 | return 0; |
d7c55201 | 2630 | } |
edba23e5 | 2631 | |
d7c55201 | 2632 | return -EFAULT; |
bf998156 HY |
2633 | } |
2634 | ||
936a5fe6 AA |
2635 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2636 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2637 | { | |
2638 | pfn_t pfn = *pfnp; | |
2639 | gfn_t gfn = *gfnp; | |
2640 | int level = *levelp; | |
2641 | ||
2642 | /* | |
2643 | * Check if it's a transparent hugepage. If this would be an | |
2644 | * hugetlbfs page, level wouldn't be set to | |
2645 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2646 | * here. | |
2647 | */ | |
81c52c56 | 2648 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2649 | level == PT_PAGE_TABLE_LEVEL && |
2650 | PageTransCompound(pfn_to_page(pfn)) && | |
2651 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2652 | unsigned long mask; | |
2653 | /* | |
2654 | * mmu_notifier_retry was successful and we hold the | |
2655 | * mmu_lock here, so the pmd can't become splitting | |
2656 | * from under us, and in turn | |
2657 | * __split_huge_page_refcount() can't run from under | |
2658 | * us and we can safely transfer the refcount from | |
2659 | * PG_tail to PG_head as we switch the pfn to tail to | |
2660 | * head. | |
2661 | */ | |
2662 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2663 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2664 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2665 | if (pfn & mask) { | |
2666 | gfn &= ~mask; | |
2667 | *gfnp = gfn; | |
2668 | kvm_release_pfn_clean(pfn); | |
2669 | pfn &= ~mask; | |
c3586667 | 2670 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2671 | *pfnp = pfn; |
2672 | } | |
2673 | } | |
2674 | } | |
2675 | ||
d7c55201 XG |
2676 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2677 | pfn_t pfn, unsigned access, int *ret_val) | |
2678 | { | |
2679 | bool ret = true; | |
2680 | ||
2681 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2682 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2683 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2684 | goto exit; | |
2685 | } | |
2686 | ||
ce88decf | 2687 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2688 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2689 | |
2690 | ret = false; | |
2691 | exit: | |
2692 | return ret; | |
2693 | } | |
2694 | ||
c7ba5b48 XG |
2695 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2696 | { | |
2697 | /* | |
2698 | * #PF can be fast only if the shadow page table is present and it | |
2699 | * is caused by write-protect, that means we just need change the | |
2700 | * W bit of the spte which can be done out of mmu-lock. | |
2701 | */ | |
2702 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2703 | !(error_code & PFERR_WRITE_MASK)) | |
2704 | return false; | |
2705 | ||
2706 | return true; | |
2707 | } | |
2708 | ||
2709 | static bool | |
2710 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2711 | { | |
2712 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2713 | gfn_t gfn; | |
2714 | ||
2715 | WARN_ON(!sp->role.direct); | |
2716 | ||
2717 | /* | |
2718 | * The gfn of direct spte is stable since it is calculated | |
2719 | * by sp->gfn. | |
2720 | */ | |
2721 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2722 | ||
2723 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2724 | mark_page_dirty(vcpu->kvm, gfn); | |
2725 | ||
2726 | return true; | |
2727 | } | |
2728 | ||
2729 | /* | |
2730 | * Return value: | |
2731 | * - true: let the vcpu to access on the same address again. | |
2732 | * - false: let the real page fault path to fix it. | |
2733 | */ | |
2734 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2735 | u32 error_code) | |
2736 | { | |
2737 | struct kvm_shadow_walk_iterator iterator; | |
2738 | bool ret = false; | |
2739 | u64 spte = 0ull; | |
2740 | ||
2741 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2742 | return false; | |
2743 | ||
2744 | walk_shadow_page_lockless_begin(vcpu); | |
2745 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2746 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2747 | break; | |
2748 | ||
2749 | /* | |
2750 | * If the mapping has been changed, let the vcpu fault on the | |
2751 | * same address again. | |
2752 | */ | |
2753 | if (!is_rmap_spte(spte)) { | |
2754 | ret = true; | |
2755 | goto exit; | |
2756 | } | |
2757 | ||
2758 | if (!is_last_spte(spte, level)) | |
2759 | goto exit; | |
2760 | ||
2761 | /* | |
2762 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2763 | * | |
2764 | * Need not check the access of upper level table entries since | |
2765 | * they are always ACC_ALL. | |
2766 | */ | |
2767 | if (is_writable_pte(spte)) { | |
2768 | ret = true; | |
2769 | goto exit; | |
2770 | } | |
2771 | ||
2772 | /* | |
2773 | * Currently, to simplify the code, only the spte write-protected | |
2774 | * by dirty-log can be fast fixed. | |
2775 | */ | |
2776 | if (!spte_is_locklessly_modifiable(spte)) | |
2777 | goto exit; | |
2778 | ||
2779 | /* | |
2780 | * Currently, fast page fault only works for direct mapping since | |
2781 | * the gfn is not stable for indirect shadow page. | |
2782 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2783 | */ | |
2784 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2785 | exit: | |
a72faf25 XG |
2786 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2787 | spte, ret); | |
c7ba5b48 XG |
2788 | walk_shadow_page_lockless_end(vcpu); |
2789 | ||
2790 | return ret; | |
2791 | } | |
2792 | ||
78b2c54a | 2793 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2794 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2795 | ||
c7ba5b48 XG |
2796 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2797 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2798 | { |
2799 | int r; | |
852e3c19 | 2800 | int level; |
936a5fe6 | 2801 | int force_pt_level; |
35149e21 | 2802 | pfn_t pfn; |
e930bffe | 2803 | unsigned long mmu_seq; |
c7ba5b48 | 2804 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2805 | |
936a5fe6 AA |
2806 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2807 | if (likely(!force_pt_level)) { | |
2808 | level = mapping_level(vcpu, gfn); | |
2809 | /* | |
2810 | * This path builds a PAE pagetable - so we can map | |
2811 | * 2mb pages at maximum. Therefore check if the level | |
2812 | * is larger than that. | |
2813 | */ | |
2814 | if (level > PT_DIRECTORY_LEVEL) | |
2815 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2816 | |
936a5fe6 AA |
2817 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2818 | } else | |
2819 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2820 | |
c7ba5b48 XG |
2821 | if (fast_page_fault(vcpu, v, level, error_code)) |
2822 | return 0; | |
2823 | ||
e930bffe | 2824 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2825 | smp_rmb(); |
060c2abe | 2826 | |
78b2c54a | 2827 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2828 | return 0; |
aaee2c94 | 2829 | |
d7c55201 XG |
2830 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2831 | return r; | |
d196e343 | 2832 | |
aaee2c94 | 2833 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2834 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2835 | goto out_unlock; |
eb787d10 | 2836 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2837 | if (likely(!force_pt_level)) |
2838 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2839 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2840 | prefault); | |
aaee2c94 MT |
2841 | spin_unlock(&vcpu->kvm->mmu_lock); |
2842 | ||
aaee2c94 | 2843 | |
10589a46 | 2844 | return r; |
e930bffe AA |
2845 | |
2846 | out_unlock: | |
2847 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2848 | kvm_release_pfn_clean(pfn); | |
2849 | return 0; | |
10589a46 MT |
2850 | } |
2851 | ||
2852 | ||
17ac10ad AK |
2853 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2854 | { | |
2855 | int i; | |
4db35314 | 2856 | struct kvm_mmu_page *sp; |
d98ba053 | 2857 | LIST_HEAD(invalid_list); |
17ac10ad | 2858 | |
ad312c7c | 2859 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2860 | return; |
aaee2c94 | 2861 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2862 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2863 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2864 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2865 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2866 | |
4db35314 AK |
2867 | sp = page_header(root); |
2868 | --sp->root_count; | |
d98ba053 XG |
2869 | if (!sp->root_count && sp->role.invalid) { |
2870 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2871 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2872 | } | |
ad312c7c | 2873 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2874 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2875 | return; |
2876 | } | |
17ac10ad | 2877 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2878 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2879 | |
417726a3 | 2880 | if (root) { |
417726a3 | 2881 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2882 | sp = page_header(root); |
2883 | --sp->root_count; | |
2e53d63a | 2884 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2885 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2886 | &invalid_list); | |
417726a3 | 2887 | } |
ad312c7c | 2888 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2889 | } |
d98ba053 | 2890 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2891 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2892 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2893 | } |
2894 | ||
8986ecc0 MT |
2895 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2896 | { | |
2897 | int ret = 0; | |
2898 | ||
2899 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2900 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2901 | ret = 1; |
2902 | } | |
2903 | ||
2904 | return ret; | |
2905 | } | |
2906 | ||
651dd37a JR |
2907 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2908 | { | |
2909 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2910 | unsigned i; |
651dd37a JR |
2911 | |
2912 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2913 | spin_lock(&vcpu->kvm->mmu_lock); | |
2914 | kvm_mmu_free_some_pages(vcpu); | |
2915 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2916 | 1, ACC_ALL, NULL); | |
2917 | ++sp->root_count; | |
2918 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2919 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2920 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2921 | for (i = 0; i < 4; ++i) { | |
2922 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2923 | ||
2924 | ASSERT(!VALID_PAGE(root)); | |
2925 | spin_lock(&vcpu->kvm->mmu_lock); | |
2926 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2927 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2928 | i << 30, | |
651dd37a JR |
2929 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2930 | NULL); | |
2931 | root = __pa(sp->spt); | |
2932 | ++sp->root_count; | |
2933 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2934 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2935 | } |
6292757f | 2936 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2937 | } else |
2938 | BUG(); | |
2939 | ||
2940 | return 0; | |
2941 | } | |
2942 | ||
2943 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2944 | { |
4db35314 | 2945 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2946 | u64 pdptr, pm_mask; |
2947 | gfn_t root_gfn; | |
2948 | int i; | |
3bb65a22 | 2949 | |
5777ed34 | 2950 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2951 | |
651dd37a JR |
2952 | if (mmu_check_root(vcpu, root_gfn)) |
2953 | return 1; | |
2954 | ||
2955 | /* | |
2956 | * Do we shadow a long mode page table? If so we need to | |
2957 | * write-protect the guests page table root. | |
2958 | */ | |
2959 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2960 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2961 | |
2962 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2963 | |
8facbbff | 2964 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2965 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2966 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2967 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2968 | root = __pa(sp->spt); |
2969 | ++sp->root_count; | |
8facbbff | 2970 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2971 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2972 | return 0; |
17ac10ad | 2973 | } |
f87f9288 | 2974 | |
651dd37a JR |
2975 | /* |
2976 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2977 | * or a PAE 3-level page table. In either case we need to be aware that |
2978 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2979 | */ |
81407ca5 JR |
2980 | pm_mask = PT_PRESENT_MASK; |
2981 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2982 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2983 | ||
17ac10ad | 2984 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2985 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2986 | |
2987 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2988 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 2989 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 2990 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2991 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2992 | continue; |
2993 | } | |
6de4f3ad | 2994 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2995 | if (mmu_check_root(vcpu, root_gfn)) |
2996 | return 1; | |
5a7388c2 | 2997 | } |
8facbbff | 2998 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2999 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 3000 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3001 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3002 | ACC_ALL, NULL); |
4db35314 AK |
3003 | root = __pa(sp->spt); |
3004 | ++sp->root_count; | |
8facbbff AK |
3005 | spin_unlock(&vcpu->kvm->mmu_lock); |
3006 | ||
81407ca5 | 3007 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3008 | } |
6292757f | 3009 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3010 | |
3011 | /* | |
3012 | * If we shadow a 32 bit page table with a long mode page | |
3013 | * table we enter this path. | |
3014 | */ | |
3015 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3016 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3017 | /* | |
3018 | * The additional page necessary for this is only | |
3019 | * allocated on demand. | |
3020 | */ | |
3021 | ||
3022 | u64 *lm_root; | |
3023 | ||
3024 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3025 | if (lm_root == NULL) | |
3026 | return 1; | |
3027 | ||
3028 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3029 | ||
3030 | vcpu->arch.mmu.lm_root = lm_root; | |
3031 | } | |
3032 | ||
3033 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3034 | } | |
3035 | ||
8986ecc0 | 3036 | return 0; |
17ac10ad AK |
3037 | } |
3038 | ||
651dd37a JR |
3039 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3040 | { | |
3041 | if (vcpu->arch.mmu.direct_map) | |
3042 | return mmu_alloc_direct_roots(vcpu); | |
3043 | else | |
3044 | return mmu_alloc_shadow_roots(vcpu); | |
3045 | } | |
3046 | ||
0ba73cda MT |
3047 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3048 | { | |
3049 | int i; | |
3050 | struct kvm_mmu_page *sp; | |
3051 | ||
81407ca5 JR |
3052 | if (vcpu->arch.mmu.direct_map) |
3053 | return; | |
3054 | ||
0ba73cda MT |
3055 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3056 | return; | |
6903074c | 3057 | |
bebb106a | 3058 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3059 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3060 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3061 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3062 | sp = page_header(root); | |
3063 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3064 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3065 | return; |
3066 | } | |
3067 | for (i = 0; i < 4; ++i) { | |
3068 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3069 | ||
8986ecc0 | 3070 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3071 | root &= PT64_BASE_ADDR_MASK; |
3072 | sp = page_header(root); | |
3073 | mmu_sync_children(vcpu, sp); | |
3074 | } | |
3075 | } | |
0375f7fa | 3076 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3077 | } |
3078 | ||
3079 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3080 | { | |
3081 | spin_lock(&vcpu->kvm->mmu_lock); | |
3082 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3083 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3084 | } |
3085 | ||
1871c602 | 3086 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3087 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3088 | { |
ab9ae313 AK |
3089 | if (exception) |
3090 | exception->error_code = 0; | |
6aa8b732 AK |
3091 | return vaddr; |
3092 | } | |
3093 | ||
6539e738 | 3094 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3095 | u32 access, |
3096 | struct x86_exception *exception) | |
6539e738 | 3097 | { |
ab9ae313 AK |
3098 | if (exception) |
3099 | exception->error_code = 0; | |
6539e738 JR |
3100 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3101 | } | |
3102 | ||
ce88decf XG |
3103 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3104 | { | |
3105 | if (direct) | |
3106 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3107 | ||
3108 | return vcpu_match_mmio_gva(vcpu, addr); | |
3109 | } | |
3110 | ||
3111 | ||
3112 | /* | |
3113 | * On direct hosts, the last spte is only allows two states | |
3114 | * for mmio page fault: | |
3115 | * - It is the mmio spte | |
3116 | * - It is zapped or it is being zapped. | |
3117 | * | |
3118 | * This function completely checks the spte when the last spte | |
3119 | * is not the mmio spte. | |
3120 | */ | |
3121 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3122 | { | |
3123 | return __check_direct_spte_mmio_pf(spte); | |
3124 | } | |
3125 | ||
3126 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3127 | { | |
3128 | struct kvm_shadow_walk_iterator iterator; | |
3129 | u64 spte = 0ull; | |
3130 | ||
3131 | walk_shadow_page_lockless_begin(vcpu); | |
3132 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3133 | if (!is_shadow_present_pte(spte)) | |
3134 | break; | |
3135 | walk_shadow_page_lockless_end(vcpu); | |
3136 | ||
3137 | return spte; | |
3138 | } | |
3139 | ||
3140 | /* | |
3141 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
3142 | * directly, return 0 to let CPU fault again on the address, -1 is | |
3143 | * returned if bug is detected. | |
3144 | */ | |
3145 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
3146 | { | |
3147 | u64 spte; | |
3148 | ||
3149 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
3150 | return 1; | |
3151 | ||
3152 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3153 | ||
3154 | if (is_mmio_spte(spte)) { | |
3155 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3156 | unsigned access = get_mmio_spte_access(spte); | |
3157 | ||
3158 | if (direct) | |
3159 | addr = 0; | |
4f022648 XG |
3160 | |
3161 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3162 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3163 | return 1; | |
3164 | } | |
3165 | ||
3166 | /* | |
3167 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3168 | * it's a BUG if the gfn is not a mmio page. | |
3169 | */ | |
3170 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3171 | return -1; | |
3172 | ||
3173 | /* | |
3174 | * If the page table is zapped by other cpus, let CPU fault again on | |
3175 | * the address. | |
3176 | */ | |
3177 | return 0; | |
3178 | } | |
3179 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3180 | ||
3181 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3182 | u32 error_code, bool direct) | |
3183 | { | |
3184 | int ret; | |
3185 | ||
3186 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3187 | WARN_ON(ret < 0); | |
3188 | return ret; | |
3189 | } | |
3190 | ||
6aa8b732 | 3191 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3192 | u32 error_code, bool prefault) |
6aa8b732 | 3193 | { |
e833240f | 3194 | gfn_t gfn; |
e2dec939 | 3195 | int r; |
6aa8b732 | 3196 | |
b8688d51 | 3197 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3198 | |
3199 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3200 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3201 | ||
e2dec939 AK |
3202 | r = mmu_topup_memory_caches(vcpu); |
3203 | if (r) | |
3204 | return r; | |
714b93da | 3205 | |
6aa8b732 | 3206 | ASSERT(vcpu); |
ad312c7c | 3207 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3208 | |
e833240f | 3209 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3210 | |
e833240f | 3211 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3212 | error_code, gfn, prefault); |
6aa8b732 AK |
3213 | } |
3214 | ||
7e1fbeac | 3215 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3216 | { |
3217 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3218 | |
7c90705b | 3219 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3220 | arch.gfn = gfn; |
c4806acd | 3221 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3222 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3223 | |
3224 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3225 | } | |
3226 | ||
3227 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3228 | { | |
3229 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3230 | kvm_event_needs_reinjection(vcpu))) | |
3231 | return false; | |
3232 | ||
3233 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3234 | } | |
3235 | ||
78b2c54a | 3236 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3237 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3238 | { |
3239 | bool async; | |
3240 | ||
612819c3 | 3241 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3242 | |
3243 | if (!async) | |
3244 | return false; /* *pfn has correct page already */ | |
3245 | ||
78b2c54a | 3246 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3247 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3248 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3249 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3250 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3251 | return true; | |
3252 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3253 | return true; | |
3254 | } | |
3255 | ||
612819c3 | 3256 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3257 | |
3258 | return false; | |
3259 | } | |
3260 | ||
56028d08 | 3261 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3262 | bool prefault) |
fb72d167 | 3263 | { |
35149e21 | 3264 | pfn_t pfn; |
fb72d167 | 3265 | int r; |
852e3c19 | 3266 | int level; |
936a5fe6 | 3267 | int force_pt_level; |
05da4558 | 3268 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3269 | unsigned long mmu_seq; |
612819c3 MT |
3270 | int write = error_code & PFERR_WRITE_MASK; |
3271 | bool map_writable; | |
fb72d167 JR |
3272 | |
3273 | ASSERT(vcpu); | |
3274 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3275 | ||
ce88decf XG |
3276 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3277 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3278 | ||
fb72d167 JR |
3279 | r = mmu_topup_memory_caches(vcpu); |
3280 | if (r) | |
3281 | return r; | |
3282 | ||
936a5fe6 AA |
3283 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3284 | if (likely(!force_pt_level)) { | |
3285 | level = mapping_level(vcpu, gfn); | |
3286 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3287 | } else | |
3288 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3289 | |
c7ba5b48 XG |
3290 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3291 | return 0; | |
3292 | ||
e930bffe | 3293 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3294 | smp_rmb(); |
af585b92 | 3295 | |
78b2c54a | 3296 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3297 | return 0; |
3298 | ||
d7c55201 XG |
3299 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3300 | return r; | |
3301 | ||
fb72d167 | 3302 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3303 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3304 | goto out_unlock; |
fb72d167 | 3305 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
3306 | if (likely(!force_pt_level)) |
3307 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3308 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3309 | level, gfn, pfn, prefault); |
fb72d167 | 3310 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3311 | |
3312 | return r; | |
e930bffe AA |
3313 | |
3314 | out_unlock: | |
3315 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3316 | kvm_release_pfn_clean(pfn); | |
3317 | return 0; | |
fb72d167 JR |
3318 | } |
3319 | ||
6aa8b732 AK |
3320 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3321 | { | |
17ac10ad | 3322 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3323 | } |
3324 | ||
52fde8df JR |
3325 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3326 | struct kvm_mmu *context) | |
6aa8b732 | 3327 | { |
6aa8b732 AK |
3328 | context->new_cr3 = nonpaging_new_cr3; |
3329 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3330 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3331 | context->free = nonpaging_free; | |
e8bc217a | 3332 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3333 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3334 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3335 | context->root_level = 0; |
6aa8b732 | 3336 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3337 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3338 | context->direct_map = true; |
2d48a985 | 3339 | context->nx = false; |
6aa8b732 AK |
3340 | return 0; |
3341 | } | |
3342 | ||
d835dfec | 3343 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3344 | { |
1165f5fe | 3345 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3346 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3347 | } |
3348 | ||
3349 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3350 | { | |
9f8fe504 | 3351 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3352 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3353 | } |
3354 | ||
5777ed34 JR |
3355 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3356 | { | |
9f8fe504 | 3357 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3358 | } |
3359 | ||
6389ee94 AK |
3360 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3361 | struct x86_exception *fault) | |
6aa8b732 | 3362 | { |
6389ee94 | 3363 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3364 | } |
3365 | ||
6aa8b732 AK |
3366 | static void paging_free(struct kvm_vcpu *vcpu) |
3367 | { | |
3368 | nonpaging_free(vcpu); | |
3369 | } | |
3370 | ||
8ea667f2 AK |
3371 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3372 | { | |
3373 | unsigned mask; | |
3374 | ||
3375 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3376 | ||
3377 | mask = (unsigned)~ACC_WRITE_MASK; | |
3378 | /* Allow write access to dirty gptes */ | |
3379 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3380 | *access &= mask; | |
3381 | } | |
3382 | ||
ce88decf XG |
3383 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3384 | int *nr_present) | |
3385 | { | |
3386 | if (unlikely(is_mmio_spte(*sptep))) { | |
3387 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3388 | mmu_spte_clear_no_track(sptep); | |
3389 | return true; | |
3390 | } | |
3391 | ||
3392 | (*nr_present)++; | |
3393 | mark_mmio_spte(sptep, gfn, access); | |
3394 | return true; | |
3395 | } | |
3396 | ||
3397 | return false; | |
3398 | } | |
3399 | ||
3d34adec AK |
3400 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3401 | { | |
3402 | unsigned access; | |
3403 | ||
3404 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3405 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3406 | ||
3407 | return access; | |
3408 | } | |
3409 | ||
6fd01b71 AK |
3410 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3411 | { | |
3412 | unsigned index; | |
3413 | ||
3414 | index = level - 1; | |
3415 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3416 | return mmu->last_pte_bitmap & (1 << index); | |
3417 | } | |
3418 | ||
6aa8b732 AK |
3419 | #define PTTYPE 64 |
3420 | #include "paging_tmpl.h" | |
3421 | #undef PTTYPE | |
3422 | ||
3423 | #define PTTYPE 32 | |
3424 | #include "paging_tmpl.h" | |
3425 | #undef PTTYPE | |
3426 | ||
52fde8df | 3427 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3428 | struct kvm_mmu *context) |
82725b20 | 3429 | { |
82725b20 DE |
3430 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3431 | u64 exb_bit_rsvd = 0; | |
3432 | ||
2d48a985 | 3433 | if (!context->nx) |
82725b20 | 3434 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3435 | switch (context->root_level) { |
82725b20 DE |
3436 | case PT32_ROOT_LEVEL: |
3437 | /* no rsvd bits for 2 level 4K page table entries */ | |
3438 | context->rsvd_bits_mask[0][1] = 0; | |
3439 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3440 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3441 | ||
3442 | if (!is_pse(vcpu)) { | |
3443 | context->rsvd_bits_mask[1][1] = 0; | |
3444 | break; | |
3445 | } | |
3446 | ||
82725b20 DE |
3447 | if (is_cpuid_PSE36()) |
3448 | /* 36bits PSE 4MB page */ | |
3449 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3450 | else | |
3451 | /* 32 bits PSE 4MB page */ | |
3452 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3453 | break; |
3454 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3455 | context->rsvd_bits_mask[0][2] = |
3456 | rsvd_bits(maxphyaddr, 63) | | |
3457 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3458 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3459 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3460 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3461 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3462 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3463 | rsvd_bits(maxphyaddr, 62) | | |
3464 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3465 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3466 | break; |
3467 | case PT64_ROOT_LEVEL: | |
3468 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3469 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3470 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3471 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3472 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3473 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3474 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3475 | rsvd_bits(maxphyaddr, 51); | |
3476 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3477 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3478 | rsvd_bits(maxphyaddr, 51) | | |
3479 | rsvd_bits(13, 29); | |
82725b20 | 3480 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3481 | rsvd_bits(maxphyaddr, 51) | |
3482 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3483 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3484 | break; |
3485 | } | |
3486 | } | |
3487 | ||
97d64b78 AK |
3488 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3489 | { | |
3490 | unsigned bit, byte, pfec; | |
3491 | u8 map; | |
3492 | bool fault, x, w, u, wf, uf, ff, smep; | |
3493 | ||
3494 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3495 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3496 | pfec = byte << 1; | |
3497 | map = 0; | |
3498 | wf = pfec & PFERR_WRITE_MASK; | |
3499 | uf = pfec & PFERR_USER_MASK; | |
3500 | ff = pfec & PFERR_FETCH_MASK; | |
3501 | for (bit = 0; bit < 8; ++bit) { | |
3502 | x = bit & ACC_EXEC_MASK; | |
3503 | w = bit & ACC_WRITE_MASK; | |
3504 | u = bit & ACC_USER_MASK; | |
3505 | ||
3506 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3507 | x |= !mmu->nx; | |
3508 | /* Allow supervisor writes if !cr0.wp */ | |
3509 | w |= !is_write_protection(vcpu) && !uf; | |
3510 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3511 | x &= !(smep && u && !uf); | |
3512 | ||
3513 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3514 | map |= fault << bit; | |
3515 | } | |
3516 | mmu->permissions[byte] = map; | |
3517 | } | |
3518 | } | |
3519 | ||
6fd01b71 AK |
3520 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3521 | { | |
3522 | u8 map; | |
3523 | unsigned level, root_level = mmu->root_level; | |
3524 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3525 | ||
3526 | if (root_level == PT32E_ROOT_LEVEL) | |
3527 | --root_level; | |
3528 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3529 | map = 1 | (1 << ps_set_index); | |
3530 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3531 | if (level <= PT_PDPE_LEVEL | |
3532 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3533 | map |= 1 << (ps_set_index | (level - 1)); | |
3534 | } | |
3535 | mmu->last_pte_bitmap = map; | |
3536 | } | |
3537 | ||
52fde8df JR |
3538 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3539 | struct kvm_mmu *context, | |
3540 | int level) | |
6aa8b732 | 3541 | { |
2d48a985 | 3542 | context->nx = is_nx(vcpu); |
4d6931c3 | 3543 | context->root_level = level; |
2d48a985 | 3544 | |
4d6931c3 | 3545 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3546 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3547 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3548 | |
3549 | ASSERT(is_pae(vcpu)); | |
3550 | context->new_cr3 = paging_new_cr3; | |
3551 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3552 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3553 | context->sync_page = paging64_sync_page; |
a7052897 | 3554 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3555 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3556 | context->free = paging_free; |
17ac10ad | 3557 | context->shadow_root_level = level; |
17c3ba9d | 3558 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3559 | context->direct_map = false; |
6aa8b732 AK |
3560 | return 0; |
3561 | } | |
3562 | ||
52fde8df JR |
3563 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3564 | struct kvm_mmu *context) | |
17ac10ad | 3565 | { |
52fde8df | 3566 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3567 | } |
3568 | ||
52fde8df JR |
3569 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3570 | struct kvm_mmu *context) | |
6aa8b732 | 3571 | { |
2d48a985 | 3572 | context->nx = false; |
4d6931c3 | 3573 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3574 | |
4d6931c3 | 3575 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3576 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3577 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3578 | |
3579 | context->new_cr3 = paging_new_cr3; | |
3580 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3581 | context->gva_to_gpa = paging32_gva_to_gpa; |
3582 | context->free = paging_free; | |
e8bc217a | 3583 | context->sync_page = paging32_sync_page; |
a7052897 | 3584 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3585 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3586 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3587 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3588 | context->direct_map = false; |
6aa8b732 AK |
3589 | return 0; |
3590 | } | |
3591 | ||
52fde8df JR |
3592 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3593 | struct kvm_mmu *context) | |
6aa8b732 | 3594 | { |
52fde8df | 3595 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3596 | } |
3597 | ||
fb72d167 JR |
3598 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3599 | { | |
14dfe855 | 3600 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3601 | |
c445f8ef | 3602 | context->base_role.word = 0; |
fb72d167 JR |
3603 | context->new_cr3 = nonpaging_new_cr3; |
3604 | context->page_fault = tdp_page_fault; | |
3605 | context->free = nonpaging_free; | |
e8bc217a | 3606 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3607 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3608 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3609 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3610 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3611 | context->direct_map = true; |
1c97f0a0 | 3612 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3613 | context->get_cr3 = get_cr3; |
e4e517b4 | 3614 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3615 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3616 | |
3617 | if (!is_paging(vcpu)) { | |
2d48a985 | 3618 | context->nx = false; |
fb72d167 JR |
3619 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3620 | context->root_level = 0; | |
3621 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3622 | context->nx = is_nx(vcpu); |
fb72d167 | 3623 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3624 | reset_rsvds_bits_mask(vcpu, context); |
3625 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3626 | } else if (is_pae(vcpu)) { |
2d48a985 | 3627 | context->nx = is_nx(vcpu); |
fb72d167 | 3628 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3629 | reset_rsvds_bits_mask(vcpu, context); |
3630 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3631 | } else { |
2d48a985 | 3632 | context->nx = false; |
fb72d167 | 3633 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3634 | reset_rsvds_bits_mask(vcpu, context); |
3635 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3636 | } |
3637 | ||
97d64b78 | 3638 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3639 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3640 | |
fb72d167 JR |
3641 | return 0; |
3642 | } | |
3643 | ||
52fde8df | 3644 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3645 | { |
a770f6f2 | 3646 | int r; |
411c588d | 3647 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3648 | ASSERT(vcpu); |
ad312c7c | 3649 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3650 | |
3651 | if (!is_paging(vcpu)) | |
52fde8df | 3652 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3653 | else if (is_long_mode(vcpu)) |
52fde8df | 3654 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3655 | else if (is_pae(vcpu)) |
52fde8df | 3656 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3657 | else |
52fde8df | 3658 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3659 | |
2c9afa52 | 3660 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3661 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3662 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3663 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3664 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3665 | |
3666 | return r; | |
3667 | } | |
3668 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3669 | ||
3670 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3671 | { | |
14dfe855 | 3672 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3673 | |
14dfe855 JR |
3674 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3675 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3676 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3677 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3678 | |
3679 | return r; | |
6aa8b732 AK |
3680 | } |
3681 | ||
02f59dc9 JR |
3682 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3683 | { | |
3684 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3685 | ||
3686 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3687 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3688 | g_context->inject_page_fault = kvm_inject_page_fault; |
3689 | ||
3690 | /* | |
3691 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3692 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3693 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3694 | * functions between mmu and nested_mmu are swapped. | |
3695 | */ | |
3696 | if (!is_paging(vcpu)) { | |
2d48a985 | 3697 | g_context->nx = false; |
02f59dc9 JR |
3698 | g_context->root_level = 0; |
3699 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3700 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3701 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3702 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3703 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3704 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3705 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3706 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3707 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3708 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3709 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3710 | } else { | |
2d48a985 | 3711 | g_context->nx = false; |
02f59dc9 | 3712 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3713 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3714 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3715 | } | |
3716 | ||
97d64b78 | 3717 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3718 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3719 | |
02f59dc9 JR |
3720 | return 0; |
3721 | } | |
3722 | ||
fb72d167 JR |
3723 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3724 | { | |
02f59dc9 JR |
3725 | if (mmu_is_nested(vcpu)) |
3726 | return init_kvm_nested_mmu(vcpu); | |
3727 | else if (tdp_enabled) | |
fb72d167 JR |
3728 | return init_kvm_tdp_mmu(vcpu); |
3729 | else | |
3730 | return init_kvm_softmmu(vcpu); | |
3731 | } | |
3732 | ||
6aa8b732 AK |
3733 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3734 | { | |
3735 | ASSERT(vcpu); | |
62ad0755 SY |
3736 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3737 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3738 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3739 | } |
3740 | ||
3741 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3742 | { |
3743 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3744 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3745 | } |
8668a3c4 | 3746 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3747 | |
3748 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3749 | { |
714b93da AK |
3750 | int r; |
3751 | ||
e2dec939 | 3752 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3753 | if (r) |
3754 | goto out; | |
8986ecc0 | 3755 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3756 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3757 | mmu_sync_roots(vcpu); |
aaee2c94 | 3758 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3759 | if (r) |
3760 | goto out; | |
3662cb1c | 3761 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3762 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3763 | out: |
3764 | return r; | |
6aa8b732 | 3765 | } |
17c3ba9d AK |
3766 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3767 | ||
3768 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3769 | { | |
3770 | mmu_free_roots(vcpu); | |
3771 | } | |
4b16184c | 3772 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3773 | |
0028425f | 3774 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3775 | struct kvm_mmu_page *sp, u64 *spte, |
3776 | const void *new) | |
0028425f | 3777 | { |
30945387 | 3778 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3779 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3780 | return; | |
30945387 | 3781 | } |
0028425f | 3782 | |
4cee5764 | 3783 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3784 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3785 | } |
3786 | ||
79539cec AK |
3787 | static bool need_remote_flush(u64 old, u64 new) |
3788 | { | |
3789 | if (!is_shadow_present_pte(old)) | |
3790 | return false; | |
3791 | if (!is_shadow_present_pte(new)) | |
3792 | return true; | |
3793 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3794 | return true; | |
3795 | old ^= PT64_NX_MASK; | |
3796 | new ^= PT64_NX_MASK; | |
3797 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3798 | } | |
3799 | ||
0671a8e7 XG |
3800 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3801 | bool remote_flush, bool local_flush) | |
79539cec | 3802 | { |
0671a8e7 XG |
3803 | if (zap_page) |
3804 | return; | |
3805 | ||
3806 | if (remote_flush) | |
79539cec | 3807 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3808 | else if (local_flush) |
79539cec AK |
3809 | kvm_mmu_flush_tlb(vcpu); |
3810 | } | |
3811 | ||
889e5cbc XG |
3812 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3813 | const u8 *new, int *bytes) | |
da4a00f0 | 3814 | { |
889e5cbc XG |
3815 | u64 gentry; |
3816 | int r; | |
72016f3a | 3817 | |
72016f3a AK |
3818 | /* |
3819 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3820 | * as the current vcpu paging mode since we update the sptes only |
3821 | * when they have the same mode. | |
72016f3a | 3822 | */ |
889e5cbc | 3823 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3824 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3825 | *gpa &= ~(gpa_t)7; |
3826 | *bytes = 8; | |
116eb3d3 | 3827 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3828 | if (r) |
3829 | gentry = 0; | |
08e850c6 AK |
3830 | new = (const u8 *)&gentry; |
3831 | } | |
3832 | ||
889e5cbc | 3833 | switch (*bytes) { |
08e850c6 AK |
3834 | case 4: |
3835 | gentry = *(const u32 *)new; | |
3836 | break; | |
3837 | case 8: | |
3838 | gentry = *(const u64 *)new; | |
3839 | break; | |
3840 | default: | |
3841 | gentry = 0; | |
3842 | break; | |
72016f3a AK |
3843 | } |
3844 | ||
889e5cbc XG |
3845 | return gentry; |
3846 | } | |
3847 | ||
3848 | /* | |
3849 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3850 | * or we may be forking, in which case it is better to unmap the page. | |
3851 | */ | |
a138fe75 | 3852 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3853 | { |
a30f47cb XG |
3854 | /* |
3855 | * Skip write-flooding detected for the sp whose level is 1, because | |
3856 | * it can become unsync, then the guest page is not write-protected. | |
3857 | */ | |
f71fa31f | 3858 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3859 | return false; |
3246af0e | 3860 | |
a30f47cb | 3861 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3862 | } |
3863 | ||
3864 | /* | |
3865 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3866 | * indicate a page is not used as a page table. | |
3867 | */ | |
3868 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3869 | int bytes) | |
3870 | { | |
3871 | unsigned offset, pte_size, misaligned; | |
3872 | ||
3873 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3874 | gpa, bytes, sp->role.word); | |
3875 | ||
3876 | offset = offset_in_page(gpa); | |
3877 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3878 | |
3879 | /* | |
3880 | * Sometimes, the OS only writes the last one bytes to update status | |
3881 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3882 | */ | |
3883 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3884 | return false; | |
3885 | ||
889e5cbc XG |
3886 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3887 | misaligned |= bytes < 4; | |
3888 | ||
3889 | return misaligned; | |
3890 | } | |
3891 | ||
3892 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3893 | { | |
3894 | unsigned page_offset, quadrant; | |
3895 | u64 *spte; | |
3896 | int level; | |
3897 | ||
3898 | page_offset = offset_in_page(gpa); | |
3899 | level = sp->role.level; | |
3900 | *nspte = 1; | |
3901 | if (!sp->role.cr4_pae) { | |
3902 | page_offset <<= 1; /* 32->64 */ | |
3903 | /* | |
3904 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3905 | * only 2MB. So we need to double the offset again | |
3906 | * and zap two pdes instead of one. | |
3907 | */ | |
3908 | if (level == PT32_ROOT_LEVEL) { | |
3909 | page_offset &= ~7; /* kill rounding error */ | |
3910 | page_offset <<= 1; | |
3911 | *nspte = 2; | |
3912 | } | |
3913 | quadrant = page_offset >> PAGE_SHIFT; | |
3914 | page_offset &= ~PAGE_MASK; | |
3915 | if (quadrant != sp->role.quadrant) | |
3916 | return NULL; | |
3917 | } | |
3918 | ||
3919 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3920 | return spte; | |
3921 | } | |
3922 | ||
3923 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3924 | const u8 *new, int bytes) | |
3925 | { | |
3926 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3927 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3928 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
3929 | LIST_HEAD(invalid_list); |
3930 | u64 entry, gentry, *spte; | |
3931 | int npte; | |
a30f47cb | 3932 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3933 | |
3934 | /* | |
3935 | * If we don't have indirect shadow pages, it means no page is | |
3936 | * write-protected, so we can exit simply. | |
3937 | */ | |
3938 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3939 | return; | |
3940 | ||
3941 | zap_page = remote_flush = local_flush = false; | |
3942 | ||
3943 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3944 | ||
3945 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3946 | ||
3947 | /* | |
3948 | * No need to care whether allocation memory is successful | |
3949 | * or not since pte prefetch is skiped if it does not have | |
3950 | * enough objects in the cache. | |
3951 | */ | |
3952 | mmu_topup_memory_caches(vcpu); | |
3953 | ||
3954 | spin_lock(&vcpu->kvm->mmu_lock); | |
3955 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 3956 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 3957 | |
fa1de2bf | 3958 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 3959 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 3960 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 3961 | detect_write_flooding(sp)) { |
0671a8e7 | 3962 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3963 | &invalid_list); |
4cee5764 | 3964 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3965 | continue; |
3966 | } | |
889e5cbc XG |
3967 | |
3968 | spte = get_written_sptes(sp, gpa, &npte); | |
3969 | if (!spte) | |
3970 | continue; | |
3971 | ||
0671a8e7 | 3972 | local_flush = true; |
ac1b714e | 3973 | while (npte--) { |
79539cec | 3974 | entry = *spte; |
38e3b2b2 | 3975 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3976 | if (gentry && |
3977 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 3978 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 3979 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 3980 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 3981 | remote_flush = true; |
ac1b714e | 3982 | ++spte; |
9b7a0325 | 3983 | } |
9b7a0325 | 3984 | } |
0671a8e7 | 3985 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3986 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 3987 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3988 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3989 | } |
3990 | ||
a436036b AK |
3991 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3992 | { | |
10589a46 MT |
3993 | gpa_t gpa; |
3994 | int r; | |
a436036b | 3995 | |
c5a78f2b | 3996 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3997 | return 0; |
3998 | ||
1871c602 | 3999 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4000 | |
10589a46 | 4001 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4002 | |
10589a46 | 4003 | return r; |
a436036b | 4004 | } |
577bdc49 | 4005 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4006 | |
22d95b12 | 4007 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 4008 | { |
d98ba053 | 4009 | LIST_HEAD(invalid_list); |
103ad25a | 4010 | |
e0df7b9f | 4011 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 4012 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 4013 | struct kvm_mmu_page *sp; |
ebeace86 | 4014 | |
f05e70ac | 4015 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 4016 | struct kvm_mmu_page, link); |
e0df7b9f | 4017 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4018 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4019 | } |
aa6bd187 | 4020 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4021 | } |
ebeace86 | 4022 | |
1cb3f3ae XG |
4023 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4024 | { | |
4025 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4026 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4027 | ||
4028 | return vcpu_match_mmio_gva(vcpu, addr); | |
4029 | } | |
4030 | ||
dc25e89e AP |
4031 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4032 | void *insn, int insn_len) | |
3067714c | 4033 | { |
1cb3f3ae | 4034 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4035 | enum emulation_result er; |
4036 | ||
56028d08 | 4037 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4038 | if (r < 0) |
4039 | goto out; | |
4040 | ||
4041 | if (!r) { | |
4042 | r = 1; | |
4043 | goto out; | |
4044 | } | |
4045 | ||
1cb3f3ae XG |
4046 | if (is_mmio_page_fault(vcpu, cr2)) |
4047 | emulation_type = 0; | |
4048 | ||
4049 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4050 | |
4051 | switch (er) { | |
4052 | case EMULATE_DONE: | |
4053 | return 1; | |
4054 | case EMULATE_DO_MMIO: | |
4055 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4056 | /* fall through */ |
3067714c | 4057 | case EMULATE_FAIL: |
3f5d18a9 | 4058 | return 0; |
3067714c AK |
4059 | default: |
4060 | BUG(); | |
4061 | } | |
4062 | out: | |
3067714c AK |
4063 | return r; |
4064 | } | |
4065 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4066 | ||
a7052897 MT |
4067 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4068 | { | |
a7052897 | 4069 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4070 | kvm_mmu_flush_tlb(vcpu); |
4071 | ++vcpu->stat.invlpg; | |
4072 | } | |
4073 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4074 | ||
18552672 JR |
4075 | void kvm_enable_tdp(void) |
4076 | { | |
4077 | tdp_enabled = true; | |
4078 | } | |
4079 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4080 | ||
5f4cb662 JR |
4081 | void kvm_disable_tdp(void) |
4082 | { | |
4083 | tdp_enabled = false; | |
4084 | } | |
4085 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4086 | ||
6aa8b732 AK |
4087 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4088 | { | |
ad312c7c | 4089 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4090 | if (vcpu->arch.mmu.lm_root != NULL) |
4091 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4092 | } |
4093 | ||
4094 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4095 | { | |
17ac10ad | 4096 | struct page *page; |
6aa8b732 AK |
4097 | int i; |
4098 | ||
4099 | ASSERT(vcpu); | |
4100 | ||
17ac10ad AK |
4101 | /* |
4102 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4103 | * Therefore we need to allocate shadow page tables in the first | |
4104 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4105 | */ | |
4106 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4107 | if (!page) | |
d7fa6ab2 WY |
4108 | return -ENOMEM; |
4109 | ||
ad312c7c | 4110 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4111 | for (i = 0; i < 4; ++i) |
ad312c7c | 4112 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4113 | |
6aa8b732 | 4114 | return 0; |
6aa8b732 AK |
4115 | } |
4116 | ||
8018c27b | 4117 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4118 | { |
6aa8b732 | 4119 | ASSERT(vcpu); |
e459e322 XG |
4120 | |
4121 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4122 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4123 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4124 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4125 | |
8018c27b IM |
4126 | return alloc_mmu_pages(vcpu); |
4127 | } | |
6aa8b732 | 4128 | |
8018c27b IM |
4129 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4130 | { | |
4131 | ASSERT(vcpu); | |
ad312c7c | 4132 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4133 | |
8018c27b | 4134 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4135 | } |
4136 | ||
90cb0529 | 4137 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4138 | { |
b99db1d3 TY |
4139 | struct kvm_memory_slot *memslot; |
4140 | gfn_t last_gfn; | |
4141 | int i; | |
6aa8b732 | 4142 | |
b99db1d3 TY |
4143 | memslot = id_to_memslot(kvm->memslots, slot); |
4144 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4145 | |
9d1beefb TY |
4146 | spin_lock(&kvm->mmu_lock); |
4147 | ||
b99db1d3 TY |
4148 | for (i = PT_PAGE_TABLE_LEVEL; |
4149 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4150 | unsigned long *rmapp; | |
4151 | unsigned long last_index, index; | |
6aa8b732 | 4152 | |
b99db1d3 TY |
4153 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4154 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4155 | |
b99db1d3 TY |
4156 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4157 | if (*rmapp) | |
4158 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e TY |
4159 | |
4160 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4161 | kvm_flush_remote_tlbs(kvm); | |
4162 | cond_resched_lock(&kvm->mmu_lock); | |
4163 | } | |
8234b22e | 4164 | } |
6aa8b732 | 4165 | } |
b99db1d3 | 4166 | |
171d595d | 4167 | kvm_flush_remote_tlbs(kvm); |
9d1beefb | 4168 | spin_unlock(&kvm->mmu_lock); |
6aa8b732 | 4169 | } |
37a7d8b0 | 4170 | |
90cb0529 | 4171 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 4172 | { |
4db35314 | 4173 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 4174 | LIST_HEAD(invalid_list); |
e0fa826f | 4175 | |
aaee2c94 | 4176 | spin_lock(&kvm->mmu_lock); |
3246af0e | 4177 | restart: |
f05e70ac | 4178 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 4179 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
4180 | goto restart; |
4181 | ||
d98ba053 | 4182 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 4183 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
4184 | } |
4185 | ||
3d56cbdf JK |
4186 | static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
4187 | struct list_head *invalid_list) | |
3ee16c81 IE |
4188 | { |
4189 | struct kvm_mmu_page *page; | |
4190 | ||
85b70591 XG |
4191 | if (list_empty(&kvm->arch.active_mmu_pages)) |
4192 | return; | |
4193 | ||
3ee16c81 IE |
4194 | page = container_of(kvm->arch.active_mmu_pages.prev, |
4195 | struct kvm_mmu_page, link); | |
3d56cbdf | 4196 | kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
4197 | } |
4198 | ||
1495f230 | 4199 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4200 | { |
4201 | struct kvm *kvm; | |
1495f230 | 4202 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4203 | |
4204 | if (nr_to_scan == 0) | |
4205 | goto out; | |
3ee16c81 | 4206 | |
e935b837 | 4207 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4208 | |
4209 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4210 | int idx; |
d98ba053 | 4211 | LIST_HEAD(invalid_list); |
3ee16c81 | 4212 | |
35f2d16b TY |
4213 | /* |
4214 | * Never scan more than sc->nr_to_scan VM instances. | |
4215 | * Will not hit this condition practically since we do not try | |
4216 | * to shrink more than one VM and it is very unlikely to see | |
4217 | * !n_used_mmu_pages so many times. | |
4218 | */ | |
4219 | if (!nr_to_scan--) | |
4220 | break; | |
19526396 GN |
4221 | /* |
4222 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4223 | * here. We may skip a VM instance errorneosly, but we do not | |
4224 | * want to shrink a VM that only started to populate its MMU | |
4225 | * anyway. | |
4226 | */ | |
35f2d16b | 4227 | if (!kvm->arch.n_used_mmu_pages) |
19526396 | 4228 | continue; |
19526396 | 4229 | |
f656ce01 | 4230 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4231 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4232 | |
19526396 | 4233 | kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list); |
d98ba053 | 4234 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4235 | |
3ee16c81 | 4236 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4237 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4238 | |
4239 | list_move_tail(&kvm->vm_list, &vm_list); | |
4240 | break; | |
3ee16c81 | 4241 | } |
3ee16c81 | 4242 | |
e935b837 | 4243 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4244 | |
45221ab6 DH |
4245 | out: |
4246 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4247 | } |
4248 | ||
4249 | static struct shrinker mmu_shrinker = { | |
4250 | .shrink = mmu_shrink, | |
4251 | .seeks = DEFAULT_SEEKS * 10, | |
4252 | }; | |
4253 | ||
2ddfd20e | 4254 | static void mmu_destroy_caches(void) |
b5a33a75 | 4255 | { |
53c07b18 XG |
4256 | if (pte_list_desc_cache) |
4257 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4258 | if (mmu_page_header_cache) |
4259 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4260 | } |
4261 | ||
4262 | int kvm_mmu_module_init(void) | |
4263 | { | |
53c07b18 XG |
4264 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4265 | sizeof(struct pte_list_desc), | |
20c2df83 | 4266 | 0, 0, NULL); |
53c07b18 | 4267 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4268 | goto nomem; |
4269 | ||
d3d25b04 AK |
4270 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4271 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4272 | 0, 0, NULL); |
d3d25b04 AK |
4273 | if (!mmu_page_header_cache) |
4274 | goto nomem; | |
4275 | ||
45bf21a8 WY |
4276 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4277 | goto nomem; | |
4278 | ||
3ee16c81 IE |
4279 | register_shrinker(&mmu_shrinker); |
4280 | ||
b5a33a75 AK |
4281 | return 0; |
4282 | ||
4283 | nomem: | |
3ee16c81 | 4284 | mmu_destroy_caches(); |
b5a33a75 AK |
4285 | return -ENOMEM; |
4286 | } | |
4287 | ||
3ad82a7e ZX |
4288 | /* |
4289 | * Caculate mmu pages needed for kvm. | |
4290 | */ | |
4291 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4292 | { | |
3ad82a7e ZX |
4293 | unsigned int nr_mmu_pages; |
4294 | unsigned int nr_pages = 0; | |
bc6678a3 | 4295 | struct kvm_memslots *slots; |
be6ba0f0 | 4296 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4297 | |
90d83dc3 LJ |
4298 | slots = kvm_memslots(kvm); |
4299 | ||
be6ba0f0 XG |
4300 | kvm_for_each_memslot(memslot, slots) |
4301 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4302 | |
4303 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4304 | nr_mmu_pages = max(nr_mmu_pages, | |
4305 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4306 | ||
4307 | return nr_mmu_pages; | |
4308 | } | |
4309 | ||
94d8b056 MT |
4310 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4311 | { | |
4312 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4313 | u64 spte; |
94d8b056 MT |
4314 | int nr_sptes = 0; |
4315 | ||
c2a2ac2b XG |
4316 | walk_shadow_page_lockless_begin(vcpu); |
4317 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4318 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4319 | nr_sptes++; |
c2a2ac2b | 4320 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4321 | break; |
4322 | } | |
c2a2ac2b | 4323 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4324 | |
4325 | return nr_sptes; | |
4326 | } | |
4327 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4328 | ||
c42fffe3 XG |
4329 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4330 | { | |
4331 | ASSERT(vcpu); | |
4332 | ||
4333 | destroy_kvm_mmu(vcpu); | |
4334 | free_mmu_pages(vcpu); | |
4335 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4336 | } |
4337 | ||
b034cf01 XG |
4338 | void kvm_mmu_module_exit(void) |
4339 | { | |
4340 | mmu_destroy_caches(); | |
4341 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4342 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4343 | mmu_audit_disable(); |
4344 | } |