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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d | 44 | #include <asm/page.h> |
aa2e063a | 45 | #include <asm/pat.h> |
e495606d | 46 | #include <asm/cmpxchg.h> |
4e542370 | 47 | #include <asm/io.h> |
13673a90 | 48 | #include <asm/vmx.h> |
3d0c27ad | 49 | #include <asm/kvm_page_track.h> |
1261bfa3 | 50 | #include "trace.h" |
6aa8b732 | 51 | |
18552672 JR |
52 | /* |
53 | * When setting this variable to true it enables Two-Dimensional-Paging | |
54 | * where the hardware walks 2 page tables: | |
55 | * 1. the guest-virtual to guest-physical | |
56 | * 2. while doing 1. it walks guest-physical to host-physical | |
57 | * If the hardware supports that we don't need to do shadow paging. | |
58 | */ | |
2f333bcb | 59 | bool tdp_enabled = false; |
18552672 | 60 | |
8b1fe17c XG |
61 | enum { |
62 | AUDIT_PRE_PAGE_FAULT, | |
63 | AUDIT_POST_PAGE_FAULT, | |
64 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
65 | AUDIT_POST_PTE_WRITE, |
66 | AUDIT_PRE_SYNC, | |
67 | AUDIT_POST_SYNC | |
8b1fe17c | 68 | }; |
37a7d8b0 | 69 | |
8b1fe17c | 70 | #undef MMU_DEBUG |
37a7d8b0 AK |
71 | |
72 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
73 | static bool dbg = 0; |
74 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
75 | |
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 78 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 79 | #else |
37a7d8b0 AK |
80 | #define pgprintk(x...) do { } while (0) |
81 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 82 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 83 | #endif |
6aa8b732 | 84 | |
957ed9ef XG |
85 | #define PTE_PREFETCH_NUM 8 |
86 | ||
00763e41 | 87 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
88 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
89 | ||
6aa8b732 AK |
90 | #define PT64_LEVEL_BITS 9 |
91 | ||
92 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 93 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 94 | |
6aa8b732 AK |
95 | #define PT64_INDEX(address, level)\ |
96 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
97 | ||
98 | ||
99 | #define PT32_LEVEL_BITS 10 | |
100 | ||
101 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 102 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 103 | |
e04da980 JR |
104 | #define PT32_LVL_OFFSET_MASK(level) \ |
105 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
106 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
107 | |
108 | #define PT32_INDEX(address, level)\ | |
109 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
110 | ||
111 | ||
d0ec49d4 | 112 | #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))) |
6aa8b732 AK |
113 | #define PT64_DIR_BASE_ADDR_MASK \ |
114 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
115 | #define PT64_LVL_ADDR_MASK(level) \ |
116 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
117 | * PT64_LEVEL_BITS))) - 1)) | |
118 | #define PT64_LVL_OFFSET_MASK(level) \ | |
119 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
120 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
121 | |
122 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
123 | #define PT32_DIR_BASE_ADDR_MASK \ | |
124 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT32_LVL_ADDR_MASK(level) \ |
126 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 128 | |
53166229 | 129 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 130 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 131 | |
fe135d2c AK |
132 | #define ACC_EXEC_MASK 1 |
133 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
134 | #define ACC_USER_MASK PT_USER_MASK | |
135 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
136 | ||
f160c7b7 JS |
137 | /* The mask for the R/X bits in EPT PTEs */ |
138 | #define PT64_EPT_READABLE_MASK 0x1ull | |
139 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
140 | ||
90bb6fc5 AK |
141 | #include <trace/events/kvm.h> |
142 | ||
07420171 AK |
143 | #define CREATE_TRACE_POINTS |
144 | #include "mmutrace.h" | |
145 | ||
49fde340 XG |
146 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
147 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 148 | |
135f8c2b AK |
149 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
150 | ||
220f773a TY |
151 | /* make pte_list_desc fit well in cache line */ |
152 | #define PTE_LIST_EXT 3 | |
153 | ||
9b8ebbdb PB |
154 | /* |
155 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
156 | * RET_PF_RETRY: let CPU fault again on the address. | |
157 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
158 | * | |
159 | * For handle_mmio_page_fault only: | |
160 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
161 | */ | |
162 | enum { | |
163 | RET_PF_RETRY = 0, | |
164 | RET_PF_EMULATE = 1, | |
165 | RET_PF_INVALID = 2, | |
166 | }; | |
167 | ||
53c07b18 XG |
168 | struct pte_list_desc { |
169 | u64 *sptes[PTE_LIST_EXT]; | |
170 | struct pte_list_desc *more; | |
cd4a4e53 AK |
171 | }; |
172 | ||
2d11123a AK |
173 | struct kvm_shadow_walk_iterator { |
174 | u64 addr; | |
175 | hpa_t shadow_addr; | |
2d11123a | 176 | u64 *sptep; |
dd3bfd59 | 177 | int level; |
2d11123a AK |
178 | unsigned index; |
179 | }; | |
180 | ||
9fa72119 JS |
181 | static const union kvm_mmu_page_role mmu_base_role_mask = { |
182 | .cr0_wp = 1, | |
183 | .cr4_pae = 1, | |
184 | .nxe = 1, | |
185 | .smep_andnot_wp = 1, | |
186 | .smap_andnot_wp = 1, | |
187 | .smm = 1, | |
188 | .guest_mode = 1, | |
189 | .ad_disabled = 1, | |
190 | }; | |
191 | ||
2d11123a AK |
192 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ |
193 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
194 | shadow_walk_okay(&(_walker)); \ | |
195 | shadow_walk_next(&(_walker))) | |
196 | ||
c2a2ac2b XG |
197 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
198 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
199 | shadow_walk_okay(&(_walker)) && \ | |
200 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
201 | __shadow_walk_next(&(_walker), spte)) | |
202 | ||
53c07b18 | 203 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 204 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 205 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 206 | |
7b52345e SY |
207 | static u64 __read_mostly shadow_nx_mask; |
208 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
209 | static u64 __read_mostly shadow_user_mask; | |
210 | static u64 __read_mostly shadow_accessed_mask; | |
211 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 212 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 213 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 214 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 215 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 216 | |
f160c7b7 | 217 | /* |
ac8d57e5 PF |
218 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
219 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
220 | * tracking. | |
f160c7b7 JS |
221 | */ |
222 | static u64 __read_mostly shadow_acc_track_mask; | |
223 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
224 | ||
225 | /* | |
226 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
227 | * as not-present for access tracking purposes. We do not save the W bit as the | |
228 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
229 | * restored only when a write is attempted to the page. | |
230 | */ | |
231 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
232 | PT64_EPT_EXECUTABLE_MASK; | |
233 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
234 | ||
ce88decf | 235 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
236 | static union kvm_mmu_page_role |
237 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 238 | |
dcdca5fe | 239 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 240 | { |
dcdca5fe PF |
241 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
242 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 243 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
244 | } |
245 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
246 | ||
ac8d57e5 PF |
247 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
248 | { | |
249 | return sp->role.ad_disabled; | |
250 | } | |
251 | ||
252 | static inline bool spte_ad_enabled(u64 spte) | |
253 | { | |
254 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
255 | return !(spte & shadow_acc_track_value); | |
256 | } | |
257 | ||
258 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
259 | { | |
260 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
261 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
262 | } | |
263 | ||
264 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
265 | { | |
266 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
267 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
268 | } | |
269 | ||
f160c7b7 JS |
270 | static inline bool is_access_track_spte(u64 spte) |
271 | { | |
ac8d57e5 | 272 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
273 | } |
274 | ||
f2fd125d | 275 | /* |
ee3d1570 DM |
276 | * the low bit of the generation number is always presumed to be zero. |
277 | * This disables mmio caching during memslot updates. The concept is | |
278 | * similar to a seqcount but instead of retrying the access we just punt | |
279 | * and ignore the cache. | |
280 | * | |
281 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
282 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 283 | */ |
ee3d1570 | 284 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
285 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
286 | ||
ee3d1570 DM |
287 | #define MMIO_GEN_SHIFT 20 |
288 | #define MMIO_GEN_LOW_SHIFT 10 | |
289 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 290 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
291 | |
292 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
293 | { | |
294 | u64 mask; | |
295 | ||
842bb26a | 296 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
297 | |
298 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
299 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
300 | return mask; | |
301 | } | |
302 | ||
303 | static unsigned int get_mmio_spte_generation(u64 spte) | |
304 | { | |
305 | unsigned int gen; | |
306 | ||
307 | spte &= ~shadow_mmio_mask; | |
308 | ||
309 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
310 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
311 | return gen; | |
312 | } | |
313 | ||
54bf36aa | 314 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 315 | { |
54bf36aa | 316 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
317 | } |
318 | ||
54bf36aa | 319 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 320 | unsigned access) |
ce88decf | 321 | { |
54bf36aa | 322 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 323 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 324 | |
ce88decf | 325 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
dcdca5fe | 326 | mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT; |
f2fd125d | 327 | |
f8f55942 | 328 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 329 | mmu_spte_set(sptep, mask); |
ce88decf XG |
330 | } |
331 | ||
332 | static bool is_mmio_spte(u64 spte) | |
333 | { | |
dcdca5fe | 334 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
335 | } |
336 | ||
337 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
338 | { | |
842bb26a | 339 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 340 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
341 | } |
342 | ||
343 | static unsigned get_mmio_spte_access(u64 spte) | |
344 | { | |
842bb26a | 345 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 346 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
347 | } |
348 | ||
54bf36aa | 349 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 350 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
351 | { |
352 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 353 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
354 | return true; |
355 | } | |
356 | ||
357 | return false; | |
358 | } | |
c7addb90 | 359 | |
54bf36aa | 360 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 361 | { |
089504c0 XG |
362 | unsigned int kvm_gen, spte_gen; |
363 | ||
54bf36aa | 364 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
365 | spte_gen = get_mmio_spte_generation(spte); |
366 | ||
367 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
368 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
369 | } |
370 | ||
ce00053b PF |
371 | /* |
372 | * Sets the shadow PTE masks used by the MMU. | |
373 | * | |
374 | * Assumptions: | |
375 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
376 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
377 | */ | |
7b52345e | 378 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 379 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 380 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 381 | { |
ce00053b PF |
382 | BUG_ON(!dirty_mask != !accessed_mask); |
383 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 384 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 385 | |
7b52345e SY |
386 | shadow_user_mask = user_mask; |
387 | shadow_accessed_mask = accessed_mask; | |
388 | shadow_dirty_mask = dirty_mask; | |
389 | shadow_nx_mask = nx_mask; | |
390 | shadow_x_mask = x_mask; | |
ffb128c8 | 391 | shadow_present_mask = p_mask; |
f160c7b7 | 392 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 393 | shadow_me_mask = me_mask; |
7b52345e SY |
394 | } |
395 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
396 | ||
858ac87f | 397 | static void kvm_mmu_clear_all_pte_masks(void) |
f160c7b7 JS |
398 | { |
399 | shadow_user_mask = 0; | |
400 | shadow_accessed_mask = 0; | |
401 | shadow_dirty_mask = 0; | |
402 | shadow_nx_mask = 0; | |
403 | shadow_x_mask = 0; | |
404 | shadow_mmio_mask = 0; | |
405 | shadow_present_mask = 0; | |
406 | shadow_acc_track_mask = 0; | |
407 | } | |
408 | ||
6aa8b732 AK |
409 | static int is_cpuid_PSE36(void) |
410 | { | |
411 | return 1; | |
412 | } | |
413 | ||
73b1087e AK |
414 | static int is_nx(struct kvm_vcpu *vcpu) |
415 | { | |
f6801dff | 416 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
417 | } |
418 | ||
c7addb90 AK |
419 | static int is_shadow_present_pte(u64 pte) |
420 | { | |
f160c7b7 | 421 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
422 | } |
423 | ||
05da4558 MT |
424 | static int is_large_pte(u64 pte) |
425 | { | |
426 | return pte & PT_PAGE_SIZE_MASK; | |
427 | } | |
428 | ||
776e6633 MT |
429 | static int is_last_spte(u64 pte, int level) |
430 | { | |
431 | if (level == PT_PAGE_TABLE_LEVEL) | |
432 | return 1; | |
852e3c19 | 433 | if (is_large_pte(pte)) |
776e6633 MT |
434 | return 1; |
435 | return 0; | |
436 | } | |
437 | ||
d3e328f2 JS |
438 | static bool is_executable_pte(u64 spte) |
439 | { | |
440 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
441 | } | |
442 | ||
ba049e93 | 443 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 444 | { |
35149e21 | 445 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
446 | } |
447 | ||
da928521 AK |
448 | static gfn_t pse36_gfn_delta(u32 gpte) |
449 | { | |
450 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
451 | ||
452 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
453 | } | |
454 | ||
603e0651 | 455 | #ifdef CONFIG_X86_64 |
d555c333 | 456 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 457 | { |
b19ee2ff | 458 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
459 | } |
460 | ||
603e0651 | 461 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 462 | { |
b19ee2ff | 463 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
464 | } |
465 | ||
466 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
467 | { | |
468 | return xchg(sptep, spte); | |
469 | } | |
c2a2ac2b XG |
470 | |
471 | static u64 __get_spte_lockless(u64 *sptep) | |
472 | { | |
6aa7de05 | 473 | return READ_ONCE(*sptep); |
c2a2ac2b | 474 | } |
a9221dd5 | 475 | #else |
603e0651 XG |
476 | union split_spte { |
477 | struct { | |
478 | u32 spte_low; | |
479 | u32 spte_high; | |
480 | }; | |
481 | u64 spte; | |
482 | }; | |
a9221dd5 | 483 | |
c2a2ac2b XG |
484 | static void count_spte_clear(u64 *sptep, u64 spte) |
485 | { | |
486 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
487 | ||
488 | if (is_shadow_present_pte(spte)) | |
489 | return; | |
490 | ||
491 | /* Ensure the spte is completely set before we increase the count */ | |
492 | smp_wmb(); | |
493 | sp->clear_spte_count++; | |
494 | } | |
495 | ||
603e0651 XG |
496 | static void __set_spte(u64 *sptep, u64 spte) |
497 | { | |
498 | union split_spte *ssptep, sspte; | |
a9221dd5 | 499 | |
603e0651 XG |
500 | ssptep = (union split_spte *)sptep; |
501 | sspte = (union split_spte)spte; | |
502 | ||
503 | ssptep->spte_high = sspte.spte_high; | |
504 | ||
505 | /* | |
506 | * If we map the spte from nonpresent to present, We should store | |
507 | * the high bits firstly, then set present bit, so cpu can not | |
508 | * fetch this spte while we are setting the spte. | |
509 | */ | |
510 | smp_wmb(); | |
511 | ||
b19ee2ff | 512 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
513 | } |
514 | ||
603e0651 XG |
515 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
516 | { | |
517 | union split_spte *ssptep, sspte; | |
518 | ||
519 | ssptep = (union split_spte *)sptep; | |
520 | sspte = (union split_spte)spte; | |
521 | ||
b19ee2ff | 522 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
523 | |
524 | /* | |
525 | * If we map the spte from present to nonpresent, we should clear | |
526 | * present bit firstly to avoid vcpu fetch the old high bits. | |
527 | */ | |
528 | smp_wmb(); | |
529 | ||
530 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 531 | count_spte_clear(sptep, spte); |
603e0651 XG |
532 | } |
533 | ||
534 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
535 | { | |
536 | union split_spte *ssptep, sspte, orig; | |
537 | ||
538 | ssptep = (union split_spte *)sptep; | |
539 | sspte = (union split_spte)spte; | |
540 | ||
541 | /* xchg acts as a barrier before the setting of the high bits */ | |
542 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
543 | orig.spte_high = ssptep->spte_high; |
544 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 545 | count_spte_clear(sptep, spte); |
603e0651 XG |
546 | |
547 | return orig.spte; | |
548 | } | |
c2a2ac2b XG |
549 | |
550 | /* | |
551 | * The idea using the light way get the spte on x86_32 guest is from | |
552 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
553 | * |
554 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
555 | * coalesces them and we are running out of the MMU lock. Therefore | |
556 | * we need to protect against in-progress updates of the spte. | |
557 | * | |
558 | * Reading the spte while an update is in progress may get the old value | |
559 | * for the high part of the spte. The race is fine for a present->non-present | |
560 | * change (because the high part of the spte is ignored for non-present spte), | |
561 | * but for a present->present change we must reread the spte. | |
562 | * | |
563 | * All such changes are done in two steps (present->non-present and | |
564 | * non-present->present), hence it is enough to count the number of | |
565 | * present->non-present updates: if it changed while reading the spte, | |
566 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
567 | */ |
568 | static u64 __get_spte_lockless(u64 *sptep) | |
569 | { | |
570 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
571 | union split_spte spte, *orig = (union split_spte *)sptep; | |
572 | int count; | |
573 | ||
574 | retry: | |
575 | count = sp->clear_spte_count; | |
576 | smp_rmb(); | |
577 | ||
578 | spte.spte_low = orig->spte_low; | |
579 | smp_rmb(); | |
580 | ||
581 | spte.spte_high = orig->spte_high; | |
582 | smp_rmb(); | |
583 | ||
584 | if (unlikely(spte.spte_low != orig->spte_low || | |
585 | count != sp->clear_spte_count)) | |
586 | goto retry; | |
587 | ||
588 | return spte.spte; | |
589 | } | |
603e0651 XG |
590 | #endif |
591 | ||
ea4114bc | 592 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 593 | { |
feb3eb70 GN |
594 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
595 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
596 | } |
597 | ||
8672b721 XG |
598 | static bool spte_has_volatile_bits(u64 spte) |
599 | { | |
f160c7b7 JS |
600 | if (!is_shadow_present_pte(spte)) |
601 | return false; | |
602 | ||
c7ba5b48 | 603 | /* |
6a6256f9 | 604 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
605 | * out of mmu-lock, it can ensure dirty bit is not lost, |
606 | * also, it can help us to get a stable is_writable_pte() | |
607 | * to ensure tlb flush is not missed. | |
608 | */ | |
f160c7b7 JS |
609 | if (spte_can_locklessly_be_made_writable(spte) || |
610 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
611 | return true; |
612 | ||
ac8d57e5 | 613 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
614 | if ((spte & shadow_accessed_mask) == 0 || |
615 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
616 | return true; | |
617 | } | |
8672b721 | 618 | |
f160c7b7 | 619 | return false; |
8672b721 XG |
620 | } |
621 | ||
83ef6c81 | 622 | static bool is_accessed_spte(u64 spte) |
4132779b | 623 | { |
ac8d57e5 PF |
624 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
625 | ||
626 | return accessed_mask ? spte & accessed_mask | |
627 | : !is_access_track_spte(spte); | |
4132779b XG |
628 | } |
629 | ||
83ef6c81 | 630 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 631 | { |
ac8d57e5 PF |
632 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
633 | ||
634 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
635 | } |
636 | ||
1df9f2dc XG |
637 | /* Rules for using mmu_spte_set: |
638 | * Set the sptep from nonpresent to present. | |
639 | * Note: the sptep being assigned *must* be either not present | |
640 | * or in a state where the hardware will not attempt to update | |
641 | * the spte. | |
642 | */ | |
643 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
644 | { | |
645 | WARN_ON(is_shadow_present_pte(*sptep)); | |
646 | __set_spte(sptep, new_spte); | |
647 | } | |
648 | ||
f39a058d JS |
649 | /* |
650 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
651 | * accessed/dirty status. | |
1df9f2dc | 652 | */ |
f39a058d | 653 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 654 | { |
c7ba5b48 | 655 | u64 old_spte = *sptep; |
4132779b | 656 | |
afd28fe1 | 657 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 658 | |
6e7d0354 XG |
659 | if (!is_shadow_present_pte(old_spte)) { |
660 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 661 | return old_spte; |
6e7d0354 | 662 | } |
4132779b | 663 | |
c7ba5b48 | 664 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 665 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 666 | else |
603e0651 | 667 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 668 | |
83ef6c81 JS |
669 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
670 | ||
f39a058d JS |
671 | return old_spte; |
672 | } | |
673 | ||
674 | /* Rules for using mmu_spte_update: | |
675 | * Update the state bits, it means the mapped pfn is not changed. | |
676 | * | |
677 | * Whenever we overwrite a writable spte with a read-only one we | |
678 | * should flush remote TLBs. Otherwise rmap_write_protect | |
679 | * will find a read-only spte, even though the writable spte | |
680 | * might be cached on a CPU's TLB, the return value indicates this | |
681 | * case. | |
682 | * | |
683 | * Returns true if the TLB needs to be flushed | |
684 | */ | |
685 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
686 | { | |
687 | bool flush = false; | |
688 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
689 | ||
690 | if (!is_shadow_present_pte(old_spte)) | |
691 | return false; | |
692 | ||
c7ba5b48 XG |
693 | /* |
694 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 695 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
696 | * spte_has_volatile_bits(). |
697 | */ | |
ea4114bc | 698 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 699 | !is_writable_pte(new_spte)) |
83ef6c81 | 700 | flush = true; |
4132779b | 701 | |
7e71a59b | 702 | /* |
83ef6c81 | 703 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
704 | * to guarantee consistency between TLB and page tables. |
705 | */ | |
7e71a59b | 706 | |
83ef6c81 JS |
707 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
708 | flush = true; | |
4132779b | 709 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
710 | } |
711 | ||
712 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
713 | flush = true; | |
4132779b | 714 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 715 | } |
6e7d0354 | 716 | |
83ef6c81 | 717 | return flush; |
b79b93f9 AK |
718 | } |
719 | ||
1df9f2dc XG |
720 | /* |
721 | * Rules for using mmu_spte_clear_track_bits: | |
722 | * It sets the sptep from present to nonpresent, and track the | |
723 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 724 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
725 | */ |
726 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
727 | { | |
ba049e93 | 728 | kvm_pfn_t pfn; |
1df9f2dc XG |
729 | u64 old_spte = *sptep; |
730 | ||
731 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 732 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 733 | else |
603e0651 | 734 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 735 | |
afd28fe1 | 736 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
737 | return 0; |
738 | ||
739 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
740 | |
741 | /* | |
742 | * KVM does not hold the refcount of the page used by | |
743 | * kvm mmu, before reclaiming the page, we should | |
744 | * unmap it from mmu first. | |
745 | */ | |
bf4bea8e | 746 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 747 | |
83ef6c81 | 748 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 749 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
750 | |
751 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 752 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 753 | |
1df9f2dc XG |
754 | return 1; |
755 | } | |
756 | ||
757 | /* | |
758 | * Rules for using mmu_spte_clear_no_track: | |
759 | * Directly clear spte without caring the state bits of sptep, | |
760 | * it is used to set the upper level spte. | |
761 | */ | |
762 | static void mmu_spte_clear_no_track(u64 *sptep) | |
763 | { | |
603e0651 | 764 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
765 | } |
766 | ||
c2a2ac2b XG |
767 | static u64 mmu_spte_get_lockless(u64 *sptep) |
768 | { | |
769 | return __get_spte_lockless(sptep); | |
770 | } | |
771 | ||
f160c7b7 JS |
772 | static u64 mark_spte_for_access_track(u64 spte) |
773 | { | |
ac8d57e5 | 774 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
775 | return spte & ~shadow_accessed_mask; |
776 | ||
ac8d57e5 | 777 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
778 | return spte; |
779 | ||
780 | /* | |
20d65236 JS |
781 | * Making an Access Tracking PTE will result in removal of write access |
782 | * from the PTE. So, verify that we will be able to restore the write | |
783 | * access in the fast page fault path later on. | |
f160c7b7 JS |
784 | */ |
785 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
786 | !spte_can_locklessly_be_made_writable(spte), | |
787 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
788 | ||
789 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
790 | shadow_acc_track_saved_bits_shift), | |
791 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
792 | ||
793 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
794 | shadow_acc_track_saved_bits_shift; | |
795 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
796 | |
797 | return spte; | |
798 | } | |
799 | ||
d3e328f2 JS |
800 | /* Restore an acc-track PTE back to a regular PTE */ |
801 | static u64 restore_acc_track_spte(u64 spte) | |
802 | { | |
803 | u64 new_spte = spte; | |
804 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
805 | & shadow_acc_track_saved_bits_mask; | |
806 | ||
ac8d57e5 | 807 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
808 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
809 | ||
810 | new_spte &= ~shadow_acc_track_mask; | |
811 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
812 | shadow_acc_track_saved_bits_shift); | |
813 | new_spte |= saved_bits; | |
814 | ||
815 | return new_spte; | |
816 | } | |
817 | ||
f160c7b7 JS |
818 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
819 | static bool mmu_spte_age(u64 *sptep) | |
820 | { | |
821 | u64 spte = mmu_spte_get_lockless(sptep); | |
822 | ||
823 | if (!is_accessed_spte(spte)) | |
824 | return false; | |
825 | ||
ac8d57e5 | 826 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
827 | clear_bit((ffs(shadow_accessed_mask) - 1), |
828 | (unsigned long *)sptep); | |
829 | } else { | |
830 | /* | |
831 | * Capture the dirty status of the page, so that it doesn't get | |
832 | * lost when the SPTE is marked for access tracking. | |
833 | */ | |
834 | if (is_writable_pte(spte)) | |
835 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
836 | ||
837 | spte = mark_spte_for_access_track(spte); | |
838 | mmu_spte_update_no_track(sptep, spte); | |
839 | } | |
840 | ||
841 | return true; | |
842 | } | |
843 | ||
c2a2ac2b XG |
844 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
845 | { | |
c142786c AK |
846 | /* |
847 | * Prevent page table teardown by making any free-er wait during | |
848 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
849 | */ | |
850 | local_irq_disable(); | |
36ca7e0a | 851 | |
c142786c AK |
852 | /* |
853 | * Make sure a following spte read is not reordered ahead of the write | |
854 | * to vcpu->mode. | |
855 | */ | |
36ca7e0a | 856 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
857 | } |
858 | ||
859 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
860 | { | |
c142786c AK |
861 | /* |
862 | * Make sure the write to vcpu->mode is not reordered in front of | |
863 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
864 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
865 | */ | |
36ca7e0a | 866 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 867 | local_irq_enable(); |
c2a2ac2b XG |
868 | } |
869 | ||
e2dec939 | 870 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 871 | struct kmem_cache *base_cache, int min) |
714b93da AK |
872 | { |
873 | void *obj; | |
874 | ||
875 | if (cache->nobjs >= min) | |
e2dec939 | 876 | return 0; |
714b93da | 877 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 878 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 879 | if (!obj) |
e2dec939 | 880 | return -ENOMEM; |
714b93da AK |
881 | cache->objects[cache->nobjs++] = obj; |
882 | } | |
e2dec939 | 883 | return 0; |
714b93da AK |
884 | } |
885 | ||
f759e2b4 XG |
886 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
887 | { | |
888 | return cache->nobjs; | |
889 | } | |
890 | ||
e8ad9a70 XG |
891 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
892 | struct kmem_cache *cache) | |
714b93da AK |
893 | { |
894 | while (mc->nobjs) | |
e8ad9a70 | 895 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
896 | } |
897 | ||
c1158e63 | 898 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 899 | int min) |
c1158e63 | 900 | { |
842f22ed | 901 | void *page; |
c1158e63 AK |
902 | |
903 | if (cache->nobjs >= min) | |
904 | return 0; | |
905 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 906 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
907 | if (!page) |
908 | return -ENOMEM; | |
842f22ed | 909 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
910 | } |
911 | return 0; | |
912 | } | |
913 | ||
914 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
915 | { | |
916 | while (mc->nobjs) | |
c4d198d5 | 917 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
918 | } |
919 | ||
2e3e5882 | 920 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 921 | { |
e2dec939 AK |
922 | int r; |
923 | ||
53c07b18 | 924 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 925 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
926 | if (r) |
927 | goto out; | |
ad312c7c | 928 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
929 | if (r) |
930 | goto out; | |
ad312c7c | 931 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 932 | mmu_page_header_cache, 4); |
e2dec939 AK |
933 | out: |
934 | return r; | |
714b93da AK |
935 | } |
936 | ||
937 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
938 | { | |
53c07b18 XG |
939 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
940 | pte_list_desc_cache); | |
ad312c7c | 941 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
942 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
943 | mmu_page_header_cache); | |
714b93da AK |
944 | } |
945 | ||
80feb89a | 946 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
947 | { |
948 | void *p; | |
949 | ||
950 | BUG_ON(!mc->nobjs); | |
951 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
952 | return p; |
953 | } | |
954 | ||
53c07b18 | 955 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 956 | { |
80feb89a | 957 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
958 | } |
959 | ||
53c07b18 | 960 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 961 | { |
53c07b18 | 962 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
963 | } |
964 | ||
2032a93d LJ |
965 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
966 | { | |
967 | if (!sp->role.direct) | |
968 | return sp->gfns[index]; | |
969 | ||
970 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
971 | } | |
972 | ||
973 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
974 | { | |
975 | if (sp->role.direct) | |
976 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
977 | else | |
978 | sp->gfns[index] = gfn; | |
979 | } | |
980 | ||
05da4558 | 981 | /* |
d4dbf470 TY |
982 | * Return the pointer to the large page information for a given gfn, |
983 | * handling slots that are not large page aligned. | |
05da4558 | 984 | */ |
d4dbf470 TY |
985 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
986 | struct kvm_memory_slot *slot, | |
987 | int level) | |
05da4558 MT |
988 | { |
989 | unsigned long idx; | |
990 | ||
fb03cb6f | 991 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 992 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
993 | } |
994 | ||
547ffaed XG |
995 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
996 | gfn_t gfn, int count) | |
997 | { | |
998 | struct kvm_lpage_info *linfo; | |
999 | int i; | |
1000 | ||
1001 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
1002 | linfo = lpage_info_slot(gfn, slot, i); | |
1003 | linfo->disallow_lpage += count; | |
1004 | WARN_ON(linfo->disallow_lpage < 0); | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1009 | { | |
1010 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
1011 | } | |
1012 | ||
1013 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1014 | { | |
1015 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1016 | } | |
1017 | ||
3ed1a478 | 1018 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1019 | { |
699023e2 | 1020 | struct kvm_memslots *slots; |
d25797b2 | 1021 | struct kvm_memory_slot *slot; |
3ed1a478 | 1022 | gfn_t gfn; |
05da4558 | 1023 | |
56ca57f9 | 1024 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1025 | gfn = sp->gfn; |
699023e2 PB |
1026 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1027 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1028 | |
1029 | /* the non-leaf shadow pages are keeping readonly. */ | |
1030 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1031 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1032 | KVM_PAGE_TRACK_WRITE); | |
1033 | ||
547ffaed | 1034 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1035 | } |
1036 | ||
3ed1a478 | 1037 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1038 | { |
699023e2 | 1039 | struct kvm_memslots *slots; |
d25797b2 | 1040 | struct kvm_memory_slot *slot; |
3ed1a478 | 1041 | gfn_t gfn; |
05da4558 | 1042 | |
56ca57f9 | 1043 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1044 | gfn = sp->gfn; |
699023e2 PB |
1045 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1046 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1047 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1048 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1049 | KVM_PAGE_TRACK_WRITE); | |
1050 | ||
547ffaed | 1051 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1052 | } |
1053 | ||
92f94f1e XG |
1054 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1055 | struct kvm_memory_slot *slot) | |
05da4558 | 1056 | { |
d4dbf470 | 1057 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1058 | |
1059 | if (slot) { | |
d4dbf470 | 1060 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1061 | return !!linfo->disallow_lpage; |
05da4558 MT |
1062 | } |
1063 | ||
92f94f1e | 1064 | return true; |
05da4558 MT |
1065 | } |
1066 | ||
92f94f1e XG |
1067 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1068 | int level) | |
5225fdf8 TY |
1069 | { |
1070 | struct kvm_memory_slot *slot; | |
1071 | ||
1072 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1073 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1074 | } |
1075 | ||
d25797b2 | 1076 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1077 | { |
8f0b1ab6 | 1078 | unsigned long page_size; |
d25797b2 | 1079 | int i, ret = 0; |
05da4558 | 1080 | |
8f0b1ab6 | 1081 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1082 | |
8a3d08f1 | 1083 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1084 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1085 | ret = i; | |
1086 | else | |
1087 | break; | |
1088 | } | |
1089 | ||
4c2155ce | 1090 | return ret; |
05da4558 MT |
1091 | } |
1092 | ||
d8aacf5d TY |
1093 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1094 | bool no_dirty_log) | |
1095 | { | |
1096 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1097 | return false; | |
1098 | if (no_dirty_log && slot->dirty_bitmap) | |
1099 | return false; | |
1100 | ||
1101 | return true; | |
1102 | } | |
1103 | ||
5d163b1c XG |
1104 | static struct kvm_memory_slot * |
1105 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1106 | bool no_dirty_log) | |
05da4558 MT |
1107 | { |
1108 | struct kvm_memory_slot *slot; | |
5d163b1c | 1109 | |
54bf36aa | 1110 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1111 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1112 | slot = NULL; |
1113 | ||
1114 | return slot; | |
1115 | } | |
1116 | ||
fd136902 TY |
1117 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1118 | bool *force_pt_level) | |
936a5fe6 AA |
1119 | { |
1120 | int host_level, level, max_level; | |
d8aacf5d TY |
1121 | struct kvm_memory_slot *slot; |
1122 | ||
8c85ac1c TY |
1123 | if (unlikely(*force_pt_level)) |
1124 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1125 | |
8c85ac1c TY |
1126 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1127 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1128 | if (unlikely(*force_pt_level)) |
1129 | return PT_PAGE_TABLE_LEVEL; | |
1130 | ||
d25797b2 JR |
1131 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1132 | ||
1133 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1134 | return host_level; | |
1135 | ||
55dd98c3 | 1136 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1137 | |
1138 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1139 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1140 | break; |
d25797b2 JR |
1141 | |
1142 | return level - 1; | |
05da4558 MT |
1143 | } |
1144 | ||
290fc38d | 1145 | /* |
018aabb5 | 1146 | * About rmap_head encoding: |
cd4a4e53 | 1147 | * |
018aabb5 TY |
1148 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1149 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1150 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1151 | */ |
1152 | ||
1153 | /* | |
1154 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1155 | */ |
53c07b18 | 1156 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1157 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1158 | { |
53c07b18 | 1159 | struct pte_list_desc *desc; |
53a27b39 | 1160 | int i, count = 0; |
cd4a4e53 | 1161 | |
018aabb5 | 1162 | if (!rmap_head->val) { |
53c07b18 | 1163 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1164 | rmap_head->val = (unsigned long)spte; |
1165 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1166 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1167 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1168 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1169 | desc->sptes[1] = spte; |
018aabb5 | 1170 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1171 | ++count; |
cd4a4e53 | 1172 | } else { |
53c07b18 | 1173 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1174 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1175 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1176 | desc = desc->more; |
53c07b18 | 1177 | count += PTE_LIST_EXT; |
53a27b39 | 1178 | } |
53c07b18 XG |
1179 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1180 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1181 | desc = desc->more; |
1182 | } | |
d555c333 | 1183 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1184 | ++count; |
d555c333 | 1185 | desc->sptes[i] = spte; |
cd4a4e53 | 1186 | } |
53a27b39 | 1187 | return count; |
cd4a4e53 AK |
1188 | } |
1189 | ||
53c07b18 | 1190 | static void |
018aabb5 TY |
1191 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1192 | struct pte_list_desc *desc, int i, | |
1193 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1194 | { |
1195 | int j; | |
1196 | ||
53c07b18 | 1197 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1198 | ; |
d555c333 AK |
1199 | desc->sptes[i] = desc->sptes[j]; |
1200 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1201 | if (j != 0) |
1202 | return; | |
1203 | if (!prev_desc && !desc->more) | |
018aabb5 | 1204 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1205 | else |
1206 | if (prev_desc) | |
1207 | prev_desc->more = desc->more; | |
1208 | else | |
018aabb5 | 1209 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1210 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1211 | } |
1212 | ||
018aabb5 | 1213 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1214 | { |
53c07b18 XG |
1215 | struct pte_list_desc *desc; |
1216 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1217 | int i; |
1218 | ||
018aabb5 | 1219 | if (!rmap_head->val) { |
53c07b18 | 1220 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1221 | BUG(); |
018aabb5 | 1222 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1223 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1224 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1225 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1226 | BUG(); |
1227 | } | |
018aabb5 | 1228 | rmap_head->val = 0; |
cd4a4e53 | 1229 | } else { |
53c07b18 | 1230 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1231 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1232 | prev_desc = NULL; |
1233 | while (desc) { | |
018aabb5 | 1234 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1235 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1236 | pte_list_desc_remove_entry(rmap_head, |
1237 | desc, i, prev_desc); | |
cd4a4e53 AK |
1238 | return; |
1239 | } | |
018aabb5 | 1240 | } |
cd4a4e53 AK |
1241 | prev_desc = desc; |
1242 | desc = desc->more; | |
1243 | } | |
53c07b18 | 1244 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1245 | BUG(); |
1246 | } | |
1247 | } | |
1248 | ||
018aabb5 TY |
1249 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1250 | struct kvm_memory_slot *slot) | |
53c07b18 | 1251 | { |
77d11309 | 1252 | unsigned long idx; |
53c07b18 | 1253 | |
77d11309 | 1254 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1255 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1256 | } |
1257 | ||
018aabb5 TY |
1258 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1259 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1260 | { |
699023e2 | 1261 | struct kvm_memslots *slots; |
9b9b1492 TY |
1262 | struct kvm_memory_slot *slot; |
1263 | ||
699023e2 PB |
1264 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1265 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1266 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1267 | } |
1268 | ||
f759e2b4 XG |
1269 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1270 | { | |
1271 | struct kvm_mmu_memory_cache *cache; | |
1272 | ||
1273 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1274 | return mmu_memory_cache_free_objects(cache); | |
1275 | } | |
1276 | ||
53c07b18 XG |
1277 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1278 | { | |
1279 | struct kvm_mmu_page *sp; | |
018aabb5 | 1280 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1281 | |
53c07b18 XG |
1282 | sp = page_header(__pa(spte)); |
1283 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1284 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1285 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1286 | } |
1287 | ||
53c07b18 XG |
1288 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1289 | { | |
1290 | struct kvm_mmu_page *sp; | |
1291 | gfn_t gfn; | |
018aabb5 | 1292 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1293 | |
1294 | sp = page_header(__pa(spte)); | |
1295 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1296 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1297 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1298 | } |
1299 | ||
1e3f42f0 TY |
1300 | /* |
1301 | * Used by the following functions to iterate through the sptes linked by a | |
1302 | * rmap. All fields are private and not assumed to be used outside. | |
1303 | */ | |
1304 | struct rmap_iterator { | |
1305 | /* private fields */ | |
1306 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1307 | int pos; /* index of the sptep */ | |
1308 | }; | |
1309 | ||
1310 | /* | |
1311 | * Iteration must be started by this function. This should also be used after | |
1312 | * removing/dropping sptes from the rmap link because in such cases the | |
1313 | * information in the itererator may not be valid. | |
1314 | * | |
1315 | * Returns sptep if found, NULL otherwise. | |
1316 | */ | |
018aabb5 TY |
1317 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1318 | struct rmap_iterator *iter) | |
1e3f42f0 | 1319 | { |
77fbbbd2 TY |
1320 | u64 *sptep; |
1321 | ||
018aabb5 | 1322 | if (!rmap_head->val) |
1e3f42f0 TY |
1323 | return NULL; |
1324 | ||
018aabb5 | 1325 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1326 | iter->desc = NULL; |
77fbbbd2 TY |
1327 | sptep = (u64 *)rmap_head->val; |
1328 | goto out; | |
1e3f42f0 TY |
1329 | } |
1330 | ||
018aabb5 | 1331 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1332 | iter->pos = 0; |
77fbbbd2 TY |
1333 | sptep = iter->desc->sptes[iter->pos]; |
1334 | out: | |
1335 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1336 | return sptep; | |
1e3f42f0 TY |
1337 | } |
1338 | ||
1339 | /* | |
1340 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1341 | * | |
1342 | * Returns sptep if found, NULL otherwise. | |
1343 | */ | |
1344 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1345 | { | |
77fbbbd2 TY |
1346 | u64 *sptep; |
1347 | ||
1e3f42f0 TY |
1348 | if (iter->desc) { |
1349 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1350 | ++iter->pos; |
1351 | sptep = iter->desc->sptes[iter->pos]; | |
1352 | if (sptep) | |
77fbbbd2 | 1353 | goto out; |
1e3f42f0 TY |
1354 | } |
1355 | ||
1356 | iter->desc = iter->desc->more; | |
1357 | ||
1358 | if (iter->desc) { | |
1359 | iter->pos = 0; | |
1360 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1361 | sptep = iter->desc->sptes[iter->pos]; |
1362 | goto out; | |
1e3f42f0 TY |
1363 | } |
1364 | } | |
1365 | ||
1366 | return NULL; | |
77fbbbd2 TY |
1367 | out: |
1368 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1369 | return sptep; | |
1e3f42f0 TY |
1370 | } |
1371 | ||
018aabb5 TY |
1372 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1373 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1374 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1375 | |
c3707958 | 1376 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1377 | { |
1df9f2dc | 1378 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1379 | rmap_remove(kvm, sptep); |
be38d276 AK |
1380 | } |
1381 | ||
8e22f955 XG |
1382 | |
1383 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1384 | { | |
1385 | if (is_large_pte(*sptep)) { | |
1386 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1387 | PT_PAGE_TABLE_LEVEL); | |
1388 | drop_spte(kvm, sptep); | |
1389 | --kvm->stat.lpages; | |
1390 | return true; | |
1391 | } | |
1392 | ||
1393 | return false; | |
1394 | } | |
1395 | ||
1396 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1397 | { | |
1398 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1399 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1400 | } | |
1401 | ||
1402 | /* | |
49fde340 | 1403 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1404 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1405 | * |
b4619660 | 1406 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1407 | * protection: |
1408 | * - for dirty logging, the spte can be set to writable at anytime if | |
1409 | * its dirty bitmap is properly set. | |
1410 | * - for spte protection, the spte can be writable only after unsync-ing | |
1411 | * shadow page. | |
8e22f955 | 1412 | * |
c126d94f | 1413 | * Return true if tlb need be flushed. |
8e22f955 | 1414 | */ |
c4f138b4 | 1415 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1416 | { |
1417 | u64 spte = *sptep; | |
1418 | ||
49fde340 | 1419 | if (!is_writable_pte(spte) && |
ea4114bc | 1420 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1421 | return false; |
1422 | ||
1423 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1424 | ||
49fde340 XG |
1425 | if (pt_protect) |
1426 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1427 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1428 | |
c126d94f | 1429 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1430 | } |
1431 | ||
018aabb5 TY |
1432 | static bool __rmap_write_protect(struct kvm *kvm, |
1433 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1434 | bool pt_protect) |
98348e95 | 1435 | { |
1e3f42f0 TY |
1436 | u64 *sptep; |
1437 | struct rmap_iterator iter; | |
d13bc5b5 | 1438 | bool flush = false; |
374cbac0 | 1439 | |
018aabb5 | 1440 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1441 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1442 | |
d13bc5b5 | 1443 | return flush; |
a0ed4607 TY |
1444 | } |
1445 | ||
c4f138b4 | 1446 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1447 | { |
1448 | u64 spte = *sptep; | |
1449 | ||
1450 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1451 | ||
1452 | spte &= ~shadow_dirty_mask; | |
1453 | ||
1454 | return mmu_spte_update(sptep, spte); | |
1455 | } | |
1456 | ||
ac8d57e5 PF |
1457 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1458 | { | |
1459 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1460 | (unsigned long *)sptep); | |
1461 | if (was_writable) | |
1462 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1463 | ||
1464 | return was_writable; | |
1465 | } | |
1466 | ||
1467 | /* | |
1468 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1469 | * - D bit on ad-enabled SPTEs, and | |
1470 | * - W bit on ad-disabled SPTEs. | |
1471 | * Returns true iff any D or W bits were cleared. | |
1472 | */ | |
018aabb5 | 1473 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1474 | { |
1475 | u64 *sptep; | |
1476 | struct rmap_iterator iter; | |
1477 | bool flush = false; | |
1478 | ||
018aabb5 | 1479 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1480 | if (spte_ad_enabled(*sptep)) |
1481 | flush |= spte_clear_dirty(sptep); | |
1482 | else | |
1483 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1484 | |
1485 | return flush; | |
1486 | } | |
1487 | ||
c4f138b4 | 1488 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1489 | { |
1490 | u64 spte = *sptep; | |
1491 | ||
1492 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1493 | ||
1494 | spte |= shadow_dirty_mask; | |
1495 | ||
1496 | return mmu_spte_update(sptep, spte); | |
1497 | } | |
1498 | ||
018aabb5 | 1499 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1500 | { |
1501 | u64 *sptep; | |
1502 | struct rmap_iterator iter; | |
1503 | bool flush = false; | |
1504 | ||
018aabb5 | 1505 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1506 | if (spte_ad_enabled(*sptep)) |
1507 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1508 | |
1509 | return flush; | |
1510 | } | |
1511 | ||
5dc99b23 | 1512 | /** |
3b0f1d01 | 1513 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1514 | * @kvm: kvm instance |
1515 | * @slot: slot to protect | |
1516 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1517 | * @mask: indicates which pages we should protect | |
1518 | * | |
1519 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1520 | * logging we do not have any such mappings. | |
1521 | */ | |
3b0f1d01 | 1522 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1523 | struct kvm_memory_slot *slot, |
1524 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1525 | { |
018aabb5 | 1526 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1527 | |
5dc99b23 | 1528 | while (mask) { |
018aabb5 TY |
1529 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1530 | PT_PAGE_TABLE_LEVEL, slot); | |
1531 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1532 | |
5dc99b23 TY |
1533 | /* clear the first set bit */ |
1534 | mask &= mask - 1; | |
1535 | } | |
374cbac0 AK |
1536 | } |
1537 | ||
f4b4b180 | 1538 | /** |
ac8d57e5 PF |
1539 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1540 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1541 | * @kvm: kvm instance |
1542 | * @slot: slot to clear D-bit | |
1543 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1544 | * @mask: indicates which pages we should clear D-bit | |
1545 | * | |
1546 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1547 | */ | |
1548 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1549 | struct kvm_memory_slot *slot, | |
1550 | gfn_t gfn_offset, unsigned long mask) | |
1551 | { | |
018aabb5 | 1552 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1553 | |
1554 | while (mask) { | |
018aabb5 TY |
1555 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1556 | PT_PAGE_TABLE_LEVEL, slot); | |
1557 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1558 | |
1559 | /* clear the first set bit */ | |
1560 | mask &= mask - 1; | |
1561 | } | |
1562 | } | |
1563 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1564 | ||
3b0f1d01 KH |
1565 | /** |
1566 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1567 | * PT level pages. | |
1568 | * | |
1569 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1570 | * enable dirty logging for them. | |
1571 | * | |
1572 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1573 | * logging we do not have any such mappings. | |
1574 | */ | |
1575 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1576 | struct kvm_memory_slot *slot, | |
1577 | gfn_t gfn_offset, unsigned long mask) | |
1578 | { | |
88178fd4 KH |
1579 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1580 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1581 | mask); | |
1582 | else | |
1583 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1584 | } |
1585 | ||
bab4165e BD |
1586 | /** |
1587 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1588 | * @vcpu: Guest mode vcpu | |
1589 | * | |
1590 | * Emulate arch specific page modification logging for the | |
1591 | * nested hypervisor | |
1592 | */ | |
1593 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1594 | { | |
1595 | if (kvm_x86_ops->write_log_dirty) | |
1596 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
aeecee2e XG |
1601 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1602 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1603 | { |
018aabb5 | 1604 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1605 | int i; |
2f84569f | 1606 | bool write_protected = false; |
95d4c16c | 1607 | |
8a3d08f1 | 1608 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1609 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1610 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1611 | } |
1612 | ||
1613 | return write_protected; | |
95d4c16c TY |
1614 | } |
1615 | ||
aeecee2e XG |
1616 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1617 | { | |
1618 | struct kvm_memory_slot *slot; | |
1619 | ||
1620 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1621 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1622 | } | |
1623 | ||
018aabb5 | 1624 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1625 | { |
1e3f42f0 TY |
1626 | u64 *sptep; |
1627 | struct rmap_iterator iter; | |
6a49f85c | 1628 | bool flush = false; |
e930bffe | 1629 | |
018aabb5 | 1630 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1631 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1632 | |
1633 | drop_spte(kvm, sptep); | |
6a49f85c | 1634 | flush = true; |
e930bffe | 1635 | } |
1e3f42f0 | 1636 | |
6a49f85c XG |
1637 | return flush; |
1638 | } | |
1639 | ||
018aabb5 | 1640 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1641 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1642 | unsigned long data) | |
1643 | { | |
018aabb5 | 1644 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1645 | } |
1646 | ||
018aabb5 | 1647 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1648 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1649 | unsigned long data) | |
3da0dd43 | 1650 | { |
1e3f42f0 TY |
1651 | u64 *sptep; |
1652 | struct rmap_iterator iter; | |
3da0dd43 | 1653 | int need_flush = 0; |
1e3f42f0 | 1654 | u64 new_spte; |
3da0dd43 | 1655 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1656 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1657 | |
1658 | WARN_ON(pte_huge(*ptep)); | |
1659 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1660 | |
0d536790 | 1661 | restart: |
018aabb5 | 1662 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1663 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1664 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1665 | |
3da0dd43 | 1666 | need_flush = 1; |
1e3f42f0 | 1667 | |
3da0dd43 | 1668 | if (pte_write(*ptep)) { |
1e3f42f0 | 1669 | drop_spte(kvm, sptep); |
0d536790 | 1670 | goto restart; |
3da0dd43 | 1671 | } else { |
1e3f42f0 | 1672 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1673 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1674 | ||
1675 | new_spte &= ~PT_WRITABLE_MASK; | |
1676 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1677 | |
1678 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1679 | |
1680 | mmu_spte_clear_track_bits(sptep); | |
1681 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1682 | } |
1683 | } | |
1e3f42f0 | 1684 | |
3da0dd43 IE |
1685 | if (need_flush) |
1686 | kvm_flush_remote_tlbs(kvm); | |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
6ce1f4e2 XG |
1691 | struct slot_rmap_walk_iterator { |
1692 | /* input fields. */ | |
1693 | struct kvm_memory_slot *slot; | |
1694 | gfn_t start_gfn; | |
1695 | gfn_t end_gfn; | |
1696 | int start_level; | |
1697 | int end_level; | |
1698 | ||
1699 | /* output fields. */ | |
1700 | gfn_t gfn; | |
018aabb5 | 1701 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1702 | int level; |
1703 | ||
1704 | /* private field. */ | |
018aabb5 | 1705 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1706 | }; |
1707 | ||
1708 | static void | |
1709 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1710 | { | |
1711 | iterator->level = level; | |
1712 | iterator->gfn = iterator->start_gfn; | |
1713 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1714 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1715 | iterator->slot); | |
1716 | } | |
1717 | ||
1718 | static void | |
1719 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1720 | struct kvm_memory_slot *slot, int start_level, | |
1721 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1722 | { | |
1723 | iterator->slot = slot; | |
1724 | iterator->start_level = start_level; | |
1725 | iterator->end_level = end_level; | |
1726 | iterator->start_gfn = start_gfn; | |
1727 | iterator->end_gfn = end_gfn; | |
1728 | ||
1729 | rmap_walk_init_level(iterator, iterator->start_level); | |
1730 | } | |
1731 | ||
1732 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1733 | { | |
1734 | return !!iterator->rmap; | |
1735 | } | |
1736 | ||
1737 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1738 | { | |
1739 | if (++iterator->rmap <= iterator->end_rmap) { | |
1740 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1741 | return; | |
1742 | } | |
1743 | ||
1744 | if (++iterator->level > iterator->end_level) { | |
1745 | iterator->rmap = NULL; | |
1746 | return; | |
1747 | } | |
1748 | ||
1749 | rmap_walk_init_level(iterator, iterator->level); | |
1750 | } | |
1751 | ||
1752 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1753 | _start_gfn, _end_gfn, _iter_) \ | |
1754 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1755 | _end_level_, _start_gfn, _end_gfn); \ | |
1756 | slot_rmap_walk_okay(_iter_); \ | |
1757 | slot_rmap_walk_next(_iter_)) | |
1758 | ||
84504ef3 TY |
1759 | static int kvm_handle_hva_range(struct kvm *kvm, |
1760 | unsigned long start, | |
1761 | unsigned long end, | |
1762 | unsigned long data, | |
1763 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1764 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1765 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1766 | gfn_t gfn, |
1767 | int level, | |
84504ef3 | 1768 | unsigned long data)) |
e930bffe | 1769 | { |
bc6678a3 | 1770 | struct kvm_memslots *slots; |
be6ba0f0 | 1771 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1772 | struct slot_rmap_walk_iterator iterator; |
1773 | int ret = 0; | |
9da0e4d5 | 1774 | int i; |
bc6678a3 | 1775 | |
9da0e4d5 PB |
1776 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1777 | slots = __kvm_memslots(kvm, i); | |
1778 | kvm_for_each_memslot(memslot, slots) { | |
1779 | unsigned long hva_start, hva_end; | |
1780 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1781 | |
9da0e4d5 PB |
1782 | hva_start = max(start, memslot->userspace_addr); |
1783 | hva_end = min(end, memslot->userspace_addr + | |
1784 | (memslot->npages << PAGE_SHIFT)); | |
1785 | if (hva_start >= hva_end) | |
1786 | continue; | |
1787 | /* | |
1788 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1789 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1790 | */ | |
1791 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1792 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1793 | ||
1794 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1795 | PT_MAX_HUGEPAGE_LEVEL, | |
1796 | gfn_start, gfn_end - 1, | |
1797 | &iterator) | |
1798 | ret |= handler(kvm, iterator.rmap, memslot, | |
1799 | iterator.gfn, iterator.level, data); | |
1800 | } | |
e930bffe AA |
1801 | } |
1802 | ||
f395302e | 1803 | return ret; |
e930bffe AA |
1804 | } |
1805 | ||
84504ef3 TY |
1806 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1807 | unsigned long data, | |
018aabb5 TY |
1808 | int (*handler)(struct kvm *kvm, |
1809 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1810 | struct kvm_memory_slot *slot, |
8a9522d2 | 1811 | gfn_t gfn, int level, |
84504ef3 TY |
1812 | unsigned long data)) |
1813 | { | |
1814 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1815 | } |
1816 | ||
1817 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1818 | { | |
3da0dd43 IE |
1819 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1820 | } | |
1821 | ||
b3ae2096 TY |
1822 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1823 | { | |
1824 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1825 | } | |
1826 | ||
3da0dd43 IE |
1827 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1828 | { | |
8a8365c5 | 1829 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1830 | } |
1831 | ||
018aabb5 | 1832 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1833 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1834 | unsigned long data) | |
e930bffe | 1835 | { |
1e3f42f0 | 1836 | u64 *sptep; |
79f702a6 | 1837 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1838 | int young = 0; |
1839 | ||
f160c7b7 JS |
1840 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1841 | young |= mmu_spte_age(sptep); | |
0d536790 | 1842 | |
8a9522d2 | 1843 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1844 | return young; |
1845 | } | |
1846 | ||
018aabb5 | 1847 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1848 | struct kvm_memory_slot *slot, gfn_t gfn, |
1849 | int level, unsigned long data) | |
8ee53820 | 1850 | { |
1e3f42f0 TY |
1851 | u64 *sptep; |
1852 | struct rmap_iterator iter; | |
8ee53820 | 1853 | |
83ef6c81 JS |
1854 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1855 | if (is_accessed_spte(*sptep)) | |
1856 | return 1; | |
83ef6c81 | 1857 | return 0; |
8ee53820 AA |
1858 | } |
1859 | ||
53a27b39 MT |
1860 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1861 | ||
852e3c19 | 1862 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1863 | { |
018aabb5 | 1864 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1865 | struct kvm_mmu_page *sp; |
1866 | ||
1867 | sp = page_header(__pa(spte)); | |
53a27b39 | 1868 | |
018aabb5 | 1869 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1870 | |
018aabb5 | 1871 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1872 | kvm_flush_remote_tlbs(vcpu->kvm); |
1873 | } | |
1874 | ||
57128468 | 1875 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1876 | { |
57128468 | 1877 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1878 | } |
1879 | ||
8ee53820 AA |
1880 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1881 | { | |
1882 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1883 | } | |
1884 | ||
d6c69ee9 | 1885 | #ifdef MMU_DEBUG |
47ad8e68 | 1886 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1887 | { |
139bdb2d AK |
1888 | u64 *pos; |
1889 | u64 *end; | |
1890 | ||
47ad8e68 | 1891 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1892 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1893 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1894 | pos, *pos); |
6aa8b732 | 1895 | return 0; |
139bdb2d | 1896 | } |
6aa8b732 AK |
1897 | return 1; |
1898 | } | |
d6c69ee9 | 1899 | #endif |
6aa8b732 | 1900 | |
45221ab6 DH |
1901 | /* |
1902 | * This value is the sum of all of the kvm instances's | |
1903 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1904 | * aggregate version in order to make the slab shrinker | |
1905 | * faster | |
1906 | */ | |
1907 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1908 | { | |
1909 | kvm->arch.n_used_mmu_pages += nr; | |
1910 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1911 | } | |
1912 | ||
834be0d8 | 1913 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1914 | { |
fa4a2c08 | 1915 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1916 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1917 | list_del(&sp->link); |
1918 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1919 | if (!sp->role.direct) |
1920 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1921 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1922 | } |
1923 | ||
cea0f0e7 AK |
1924 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1925 | { | |
114df303 | 1926 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1927 | } |
1928 | ||
714b93da | 1929 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1930 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1931 | { |
cea0f0e7 AK |
1932 | if (!parent_pte) |
1933 | return; | |
cea0f0e7 | 1934 | |
67052b35 | 1935 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1936 | } |
1937 | ||
4db35314 | 1938 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1939 | u64 *parent_pte) |
1940 | { | |
67052b35 | 1941 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1942 | } |
1943 | ||
bcdd9a93 XG |
1944 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1945 | u64 *parent_pte) | |
1946 | { | |
1947 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1948 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1949 | } |
1950 | ||
47005792 | 1951 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1952 | { |
67052b35 | 1953 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1954 | |
80feb89a TY |
1955 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1956 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1957 | if (!direct) |
80feb89a | 1958 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1959 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1960 | |
1961 | /* | |
1962 | * The active_mmu_pages list is the FIFO list, do not move the | |
1963 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1964 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1965 | */ | |
67052b35 | 1966 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1967 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1968 | return sp; | |
ad8cfbe3 MT |
1969 | } |
1970 | ||
67052b35 | 1971 | static void mark_unsync(u64 *spte); |
1047df1f | 1972 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1973 | { |
74c4e63a TY |
1974 | u64 *sptep; |
1975 | struct rmap_iterator iter; | |
1976 | ||
1977 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1978 | mark_unsync(sptep); | |
1979 | } | |
0074ff63 MT |
1980 | } |
1981 | ||
67052b35 | 1982 | static void mark_unsync(u64 *spte) |
0074ff63 | 1983 | { |
67052b35 | 1984 | struct kvm_mmu_page *sp; |
1047df1f | 1985 | unsigned int index; |
0074ff63 | 1986 | |
67052b35 | 1987 | sp = page_header(__pa(spte)); |
1047df1f XG |
1988 | index = spte - sp->spt; |
1989 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1990 | return; |
1047df1f | 1991 | if (sp->unsync_children++) |
0074ff63 | 1992 | return; |
1047df1f | 1993 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1994 | } |
1995 | ||
e8bc217a | 1996 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1997 | struct kvm_mmu_page *sp) |
e8bc217a | 1998 | { |
1f50f1b3 | 1999 | return 0; |
e8bc217a MT |
2000 | } |
2001 | ||
a7052897 MT |
2002 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2003 | { | |
2004 | } | |
2005 | ||
0f53b5b1 XG |
2006 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
2007 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 2008 | const void *pte) |
0f53b5b1 XG |
2009 | { |
2010 | WARN_ON(1); | |
2011 | } | |
2012 | ||
60c8aec6 MT |
2013 | #define KVM_PAGE_ARRAY_NR 16 |
2014 | ||
2015 | struct kvm_mmu_pages { | |
2016 | struct mmu_page_and_offset { | |
2017 | struct kvm_mmu_page *sp; | |
2018 | unsigned int idx; | |
2019 | } page[KVM_PAGE_ARRAY_NR]; | |
2020 | unsigned int nr; | |
2021 | }; | |
2022 | ||
cded19f3 HE |
2023 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2024 | int idx) | |
4731d4c7 | 2025 | { |
60c8aec6 | 2026 | int i; |
4731d4c7 | 2027 | |
60c8aec6 MT |
2028 | if (sp->unsync) |
2029 | for (i=0; i < pvec->nr; i++) | |
2030 | if (pvec->page[i].sp == sp) | |
2031 | return 0; | |
2032 | ||
2033 | pvec->page[pvec->nr].sp = sp; | |
2034 | pvec->page[pvec->nr].idx = idx; | |
2035 | pvec->nr++; | |
2036 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2037 | } | |
2038 | ||
fd951457 TY |
2039 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2040 | { | |
2041 | --sp->unsync_children; | |
2042 | WARN_ON((int)sp->unsync_children < 0); | |
2043 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2044 | } | |
2045 | ||
60c8aec6 MT |
2046 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2047 | struct kvm_mmu_pages *pvec) | |
2048 | { | |
2049 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2050 | |
37178b8b | 2051 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2052 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2053 | u64 ent = sp->spt[i]; |
2054 | ||
fd951457 TY |
2055 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2056 | clear_unsync_child_bit(sp, i); | |
2057 | continue; | |
2058 | } | |
7a8f1a74 XG |
2059 | |
2060 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2061 | ||
2062 | if (child->unsync_children) { | |
2063 | if (mmu_pages_add(pvec, child, i)) | |
2064 | return -ENOSPC; | |
2065 | ||
2066 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2067 | if (!ret) { |
2068 | clear_unsync_child_bit(sp, i); | |
2069 | continue; | |
2070 | } else if (ret > 0) { | |
7a8f1a74 | 2071 | nr_unsync_leaf += ret; |
fd951457 | 2072 | } else |
7a8f1a74 XG |
2073 | return ret; |
2074 | } else if (child->unsync) { | |
2075 | nr_unsync_leaf++; | |
2076 | if (mmu_pages_add(pvec, child, i)) | |
2077 | return -ENOSPC; | |
2078 | } else | |
fd951457 | 2079 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2080 | } |
2081 | ||
60c8aec6 MT |
2082 | return nr_unsync_leaf; |
2083 | } | |
2084 | ||
e23d3fef XG |
2085 | #define INVALID_INDEX (-1) |
2086 | ||
60c8aec6 MT |
2087 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2088 | struct kvm_mmu_pages *pvec) | |
2089 | { | |
0a47cd85 | 2090 | pvec->nr = 0; |
60c8aec6 MT |
2091 | if (!sp->unsync_children) |
2092 | return 0; | |
2093 | ||
e23d3fef | 2094 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2095 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2096 | } |
2097 | ||
4731d4c7 MT |
2098 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2099 | { | |
2100 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2101 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2102 | sp->unsync = 0; |
2103 | --kvm->stat.mmu_unsync; | |
2104 | } | |
2105 | ||
7775834a XG |
2106 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2107 | struct list_head *invalid_list); | |
2108 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2109 | struct list_head *invalid_list); | |
4731d4c7 | 2110 | |
f34d251d XG |
2111 | /* |
2112 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2113 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2114 | * since it has been deleted from active_mmu_pages but still can be found | |
2115 | * at hast list. | |
2116 | * | |
f3414bc7 | 2117 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2118 | */ |
f3414bc7 | 2119 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2120 | hlist_for_each_entry(_sp, \ |
2121 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2122 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2123 | } else | |
1044b030 TY |
2124 | |
2125 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2126 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2127 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2128 | |
f918b443 | 2129 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2130 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2131 | struct list_head *invalid_list) | |
4731d4c7 | 2132 | { |
5b7e0102 | 2133 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 2134 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2135 | return false; |
4731d4c7 MT |
2136 | } |
2137 | ||
1f50f1b3 | 2138 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 2139 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2140 | return false; |
4731d4c7 MT |
2141 | } |
2142 | ||
1f50f1b3 | 2143 | return true; |
4731d4c7 MT |
2144 | } |
2145 | ||
35a70510 PB |
2146 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2147 | struct list_head *invalid_list, | |
2148 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2149 | { |
35a70510 PB |
2150 | if (!list_empty(invalid_list)) { |
2151 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2152 | return; | |
2153 | } | |
d98ba053 | 2154 | |
35a70510 PB |
2155 | if (remote_flush) |
2156 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2157 | else if (local_flush) | |
2158 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2159 | } |
2160 | ||
e37fa785 XG |
2161 | #ifdef CONFIG_KVM_MMU_AUDIT |
2162 | #include "mmu_audit.c" | |
2163 | #else | |
2164 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2165 | static void mmu_audit_disable(void) { } | |
2166 | #endif | |
2167 | ||
46971a2f XG |
2168 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2169 | { | |
2170 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2171 | } | |
2172 | ||
1f50f1b3 | 2173 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2174 | struct list_head *invalid_list) |
1d9dc7e0 | 2175 | { |
9a43c5d9 PB |
2176 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2177 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2178 | } |
2179 | ||
9f1a122f | 2180 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2181 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2182 | struct list_head *invalid_list) | |
9f1a122f | 2183 | { |
9f1a122f | 2184 | struct kvm_mmu_page *s; |
2a74003a | 2185 | bool ret = false; |
9f1a122f | 2186 | |
b67bfe0d | 2187 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2188 | if (!s->unsync) |
9f1a122f XG |
2189 | continue; |
2190 | ||
2191 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2192 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2193 | } |
2194 | ||
2a74003a | 2195 | return ret; |
9f1a122f XG |
2196 | } |
2197 | ||
60c8aec6 | 2198 | struct mmu_page_path { |
2a7266a8 YZ |
2199 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2200 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2201 | }; |
2202 | ||
60c8aec6 | 2203 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2204 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2205 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2206 | i = mmu_pages_next(&pvec, &parents, i)) | |
2207 | ||
cded19f3 HE |
2208 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2209 | struct mmu_page_path *parents, | |
2210 | int i) | |
60c8aec6 MT |
2211 | { |
2212 | int n; | |
2213 | ||
2214 | for (n = i+1; n < pvec->nr; n++) { | |
2215 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2216 | unsigned idx = pvec->page[n].idx; |
2217 | int level = sp->role.level; | |
60c8aec6 | 2218 | |
0a47cd85 PB |
2219 | parents->idx[level-1] = idx; |
2220 | if (level == PT_PAGE_TABLE_LEVEL) | |
2221 | break; | |
60c8aec6 | 2222 | |
0a47cd85 | 2223 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2224 | } |
2225 | ||
2226 | return n; | |
2227 | } | |
2228 | ||
0a47cd85 PB |
2229 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2230 | struct mmu_page_path *parents) | |
2231 | { | |
2232 | struct kvm_mmu_page *sp; | |
2233 | int level; | |
2234 | ||
2235 | if (pvec->nr == 0) | |
2236 | return 0; | |
2237 | ||
e23d3fef XG |
2238 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2239 | ||
0a47cd85 PB |
2240 | sp = pvec->page[0].sp; |
2241 | level = sp->role.level; | |
2242 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2243 | ||
2244 | parents->parent[level-2] = sp; | |
2245 | ||
2246 | /* Also set up a sentinel. Further entries in pvec are all | |
2247 | * children of sp, so this element is never overwritten. | |
2248 | */ | |
2249 | parents->parent[level-1] = NULL; | |
2250 | return mmu_pages_next(pvec, parents, 0); | |
2251 | } | |
2252 | ||
cded19f3 | 2253 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2254 | { |
60c8aec6 MT |
2255 | struct kvm_mmu_page *sp; |
2256 | unsigned int level = 0; | |
2257 | ||
2258 | do { | |
2259 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2260 | sp = parents->parent[level]; |
2261 | if (!sp) | |
2262 | return; | |
2263 | ||
e23d3fef | 2264 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2265 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2266 | level++; |
0a47cd85 | 2267 | } while (!sp->unsync_children); |
60c8aec6 | 2268 | } |
4731d4c7 | 2269 | |
60c8aec6 MT |
2270 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2271 | struct kvm_mmu_page *parent) | |
2272 | { | |
2273 | int i; | |
2274 | struct kvm_mmu_page *sp; | |
2275 | struct mmu_page_path parents; | |
2276 | struct kvm_mmu_pages pages; | |
d98ba053 | 2277 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2278 | bool flush = false; |
60c8aec6 | 2279 | |
60c8aec6 | 2280 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2281 | bool protected = false; |
b1a36821 MT |
2282 | |
2283 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2284 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2285 | |
50c9e6f3 | 2286 | if (protected) { |
b1a36821 | 2287 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2288 | flush = false; |
2289 | } | |
b1a36821 | 2290 | |
60c8aec6 | 2291 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2292 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2293 | mmu_pages_clear_parents(&parents); |
2294 | } | |
50c9e6f3 PB |
2295 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2296 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2297 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2298 | flush = false; | |
2299 | } | |
60c8aec6 | 2300 | } |
50c9e6f3 PB |
2301 | |
2302 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2303 | } |
2304 | ||
a30f47cb XG |
2305 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2306 | { | |
e5691a81 | 2307 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2308 | } |
2309 | ||
2310 | static void clear_sp_write_flooding_count(u64 *spte) | |
2311 | { | |
2312 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2313 | ||
2314 | __clear_sp_write_flooding_count(sp); | |
2315 | } | |
2316 | ||
cea0f0e7 AK |
2317 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2318 | gfn_t gfn, | |
2319 | gva_t gaddr, | |
2320 | unsigned level, | |
f6e2c02b | 2321 | int direct, |
bb11c6c9 | 2322 | unsigned access) |
cea0f0e7 AK |
2323 | { |
2324 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2325 | unsigned quadrant; |
9f1a122f | 2326 | struct kvm_mmu_page *sp; |
9f1a122f | 2327 | bool need_sync = false; |
2a74003a | 2328 | bool flush = false; |
f3414bc7 | 2329 | int collisions = 0; |
2a74003a | 2330 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2331 | |
a770f6f2 | 2332 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2333 | role.level = level; |
f6e2c02b | 2334 | role.direct = direct; |
84b0c8c6 | 2335 | if (role.direct) |
5b7e0102 | 2336 | role.cr4_pae = 0; |
41074d07 | 2337 | role.access = access; |
c5a78f2b JR |
2338 | if (!vcpu->arch.mmu.direct_map |
2339 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2340 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2341 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2342 | role.quadrant = quadrant; | |
2343 | } | |
f3414bc7 DM |
2344 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2345 | if (sp->gfn != gfn) { | |
2346 | collisions++; | |
2347 | continue; | |
2348 | } | |
2349 | ||
7ae680eb XG |
2350 | if (!need_sync && sp->unsync) |
2351 | need_sync = true; | |
4731d4c7 | 2352 | |
7ae680eb XG |
2353 | if (sp->role.word != role.word) |
2354 | continue; | |
4731d4c7 | 2355 | |
2a74003a PB |
2356 | if (sp->unsync) { |
2357 | /* The page is good, but __kvm_sync_page might still end | |
2358 | * up zapping it. If so, break in order to rebuild it. | |
2359 | */ | |
2360 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2361 | break; | |
2362 | ||
2363 | WARN_ON(!list_empty(&invalid_list)); | |
2364 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2365 | } | |
e02aa901 | 2366 | |
98bba238 | 2367 | if (sp->unsync_children) |
a8eeb04a | 2368 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2369 | |
a30f47cb | 2370 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2371 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2372 | goto out; |
7ae680eb | 2373 | } |
47005792 | 2374 | |
dfc5aa00 | 2375 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2376 | |
2377 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2378 | ||
4db35314 AK |
2379 | sp->gfn = gfn; |
2380 | sp->role = role; | |
7ae680eb XG |
2381 | hlist_add_head(&sp->hash_link, |
2382 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2383 | if (!direct) { |
56ca57f9 XG |
2384 | /* |
2385 | * we should do write protection before syncing pages | |
2386 | * otherwise the content of the synced shadow page may | |
2387 | * be inconsistent with guest page table. | |
2388 | */ | |
2389 | account_shadowed(vcpu->kvm, sp); | |
2390 | if (level == PT_PAGE_TABLE_LEVEL && | |
2391 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2392 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2393 | |
9f1a122f | 2394 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2395 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2396 | } |
5304b8d3 | 2397 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2398 | clear_page(sp->spt); |
f691fe1d | 2399 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2400 | |
2401 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2402 | out: |
2403 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2404 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2405 | return sp; |
cea0f0e7 AK |
2406 | } |
2407 | ||
2d11123a AK |
2408 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2409 | struct kvm_vcpu *vcpu, u64 addr) | |
2410 | { | |
2411 | iterator->addr = addr; | |
2412 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2413 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 | 2414 | |
2a7266a8 YZ |
2415 | if (iterator->level == PT64_ROOT_4LEVEL && |
2416 | vcpu->arch.mmu.root_level < PT64_ROOT_4LEVEL && | |
81407ca5 JR |
2417 | !vcpu->arch.mmu.direct_map) |
2418 | --iterator->level; | |
2419 | ||
2d11123a AK |
2420 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2421 | iterator->shadow_addr | |
2422 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2423 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2424 | --iterator->level; | |
2425 | if (!iterator->shadow_addr) | |
2426 | iterator->level = 0; | |
2427 | } | |
2428 | } | |
2429 | ||
2430 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2431 | { | |
2432 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2433 | return false; | |
4d88954d | 2434 | |
2d11123a AK |
2435 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2436 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2437 | return true; | |
2438 | } | |
2439 | ||
c2a2ac2b XG |
2440 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2441 | u64 spte) | |
2d11123a | 2442 | { |
c2a2ac2b | 2443 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2444 | iterator->level = 0; |
2445 | return; | |
2446 | } | |
2447 | ||
c2a2ac2b | 2448 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2449 | --iterator->level; |
2450 | } | |
2451 | ||
c2a2ac2b XG |
2452 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2453 | { | |
bb606a9b | 2454 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2455 | } |
2456 | ||
98bba238 TY |
2457 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2458 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2459 | { |
2460 | u64 spte; | |
2461 | ||
ffb128c8 | 2462 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2463 | |
ffb128c8 | 2464 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2465 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2466 | |
2467 | if (sp_ad_disabled(sp)) | |
2468 | spte |= shadow_acc_track_value; | |
2469 | else | |
2470 | spte |= shadow_accessed_mask; | |
24db2734 | 2471 | |
1df9f2dc | 2472 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2473 | |
2474 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2475 | ||
2476 | if (sp->unsync_children || sp->unsync) | |
2477 | mark_unsync(sptep); | |
32ef26a3 AK |
2478 | } |
2479 | ||
a357bd22 AK |
2480 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2481 | unsigned direct_access) | |
2482 | { | |
2483 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2484 | struct kvm_mmu_page *child; | |
2485 | ||
2486 | /* | |
2487 | * For the direct sp, if the guest pte's dirty bit | |
2488 | * changed form clean to dirty, it will corrupt the | |
2489 | * sp's access: allow writable in the read-only sp, | |
2490 | * so we should update the spte at this point to get | |
2491 | * a new sp with the correct access. | |
2492 | */ | |
2493 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2494 | if (child->role.access == direct_access) | |
2495 | return; | |
2496 | ||
bcdd9a93 | 2497 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2498 | kvm_flush_remote_tlbs(vcpu->kvm); |
2499 | } | |
2500 | } | |
2501 | ||
505aef8f | 2502 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2503 | u64 *spte) |
2504 | { | |
2505 | u64 pte; | |
2506 | struct kvm_mmu_page *child; | |
2507 | ||
2508 | pte = *spte; | |
2509 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2510 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2511 | drop_spte(kvm, spte); |
505aef8f XG |
2512 | if (is_large_pte(pte)) |
2513 | --kvm->stat.lpages; | |
2514 | } else { | |
38e3b2b2 | 2515 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2516 | drop_parent_pte(child, spte); |
38e3b2b2 | 2517 | } |
505aef8f XG |
2518 | return true; |
2519 | } | |
2520 | ||
2521 | if (is_mmio_spte(pte)) | |
ce88decf | 2522 | mmu_spte_clear_no_track(spte); |
c3707958 | 2523 | |
505aef8f | 2524 | return false; |
38e3b2b2 XG |
2525 | } |
2526 | ||
90cb0529 | 2527 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2528 | struct kvm_mmu_page *sp) |
a436036b | 2529 | { |
697fe2e2 | 2530 | unsigned i; |
697fe2e2 | 2531 | |
38e3b2b2 XG |
2532 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2533 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2534 | } |
2535 | ||
31aa2b44 | 2536 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2537 | { |
1e3f42f0 TY |
2538 | u64 *sptep; |
2539 | struct rmap_iterator iter; | |
a436036b | 2540 | |
018aabb5 | 2541 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2542 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2543 | } |
2544 | ||
60c8aec6 | 2545 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2546 | struct kvm_mmu_page *parent, |
2547 | struct list_head *invalid_list) | |
4731d4c7 | 2548 | { |
60c8aec6 MT |
2549 | int i, zapped = 0; |
2550 | struct mmu_page_path parents; | |
2551 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2552 | |
60c8aec6 | 2553 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2554 | return 0; |
60c8aec6 | 2555 | |
60c8aec6 MT |
2556 | while (mmu_unsync_walk(parent, &pages)) { |
2557 | struct kvm_mmu_page *sp; | |
2558 | ||
2559 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2560 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2561 | mmu_pages_clear_parents(&parents); |
77662e00 | 2562 | zapped++; |
60c8aec6 | 2563 | } |
60c8aec6 MT |
2564 | } |
2565 | ||
2566 | return zapped; | |
4731d4c7 MT |
2567 | } |
2568 | ||
7775834a XG |
2569 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2570 | struct list_head *invalid_list) | |
31aa2b44 | 2571 | { |
4731d4c7 | 2572 | int ret; |
f691fe1d | 2573 | |
7775834a | 2574 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2575 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2576 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2577 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2578 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2579 | |
f6e2c02b | 2580 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2581 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2582 | |
4731d4c7 MT |
2583 | if (sp->unsync) |
2584 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2585 | if (!sp->root_count) { |
54a4f023 GJ |
2586 | /* Count self */ |
2587 | ret++; | |
7775834a | 2588 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2589 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2590 | } else { |
5b5c6a5a | 2591 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2592 | |
2593 | /* | |
2594 | * The obsolete pages can not be used on any vcpus. | |
2595 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2596 | */ | |
2597 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2598 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2599 | } |
7775834a XG |
2600 | |
2601 | sp->role.invalid = 1; | |
4731d4c7 | 2602 | return ret; |
a436036b AK |
2603 | } |
2604 | ||
7775834a XG |
2605 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2606 | struct list_head *invalid_list) | |
2607 | { | |
945315b9 | 2608 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2609 | |
2610 | if (list_empty(invalid_list)) | |
2611 | return; | |
2612 | ||
c142786c | 2613 | /* |
9753f529 LT |
2614 | * We need to make sure everyone sees our modifications to |
2615 | * the page tables and see changes to vcpu->mode here. The barrier | |
2616 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2617 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2618 | * | |
2619 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2620 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2621 | */ |
2622 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2623 | |
945315b9 | 2624 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2625 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2626 | kvm_mmu_free_page(sp); |
945315b9 | 2627 | } |
7775834a XG |
2628 | } |
2629 | ||
5da59607 TY |
2630 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2631 | struct list_head *invalid_list) | |
2632 | { | |
2633 | struct kvm_mmu_page *sp; | |
2634 | ||
2635 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2636 | return false; | |
2637 | ||
d74c0e6b GT |
2638 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2639 | struct kvm_mmu_page, link); | |
42bcbebf | 2640 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2641 | } |
2642 | ||
82ce2c96 IE |
2643 | /* |
2644 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2645 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2646 | */ |
49d5ca26 | 2647 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2648 | { |
d98ba053 | 2649 | LIST_HEAD(invalid_list); |
82ce2c96 | 2650 | |
b34cb590 TY |
2651 | spin_lock(&kvm->mmu_lock); |
2652 | ||
49d5ca26 | 2653 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2654 | /* Need to free some mmu pages to achieve the goal. */ |
2655 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2656 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2657 | break; | |
82ce2c96 | 2658 | |
aa6bd187 | 2659 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2660 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2661 | } |
82ce2c96 | 2662 | |
49d5ca26 | 2663 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2664 | |
2665 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2666 | } |
2667 | ||
1cb3f3ae | 2668 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2669 | { |
4db35314 | 2670 | struct kvm_mmu_page *sp; |
d98ba053 | 2671 | LIST_HEAD(invalid_list); |
a436036b AK |
2672 | int r; |
2673 | ||
9ad17b10 | 2674 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2675 | r = 0; |
1cb3f3ae | 2676 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2677 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2678 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2679 | sp->role.word); |
2680 | r = 1; | |
f41d335a | 2681 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2682 | } |
d98ba053 | 2683 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2684 | spin_unlock(&kvm->mmu_lock); |
2685 | ||
a436036b | 2686 | return r; |
cea0f0e7 | 2687 | } |
1cb3f3ae | 2688 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2689 | |
5c520e90 | 2690 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2691 | { |
2692 | trace_kvm_mmu_unsync_page(sp); | |
2693 | ++vcpu->kvm->stat.mmu_unsync; | |
2694 | sp->unsync = 1; | |
2695 | ||
2696 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2697 | } |
2698 | ||
3d0c27ad XG |
2699 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2700 | bool can_unsync) | |
4731d4c7 | 2701 | { |
5c520e90 | 2702 | struct kvm_mmu_page *sp; |
4731d4c7 | 2703 | |
3d0c27ad XG |
2704 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2705 | return true; | |
9cf5cf5a | 2706 | |
5c520e90 | 2707 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2708 | if (!can_unsync) |
3d0c27ad | 2709 | return true; |
36a2e677 | 2710 | |
5c520e90 XG |
2711 | if (sp->unsync) |
2712 | continue; | |
9cf5cf5a | 2713 | |
5c520e90 XG |
2714 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2715 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2716 | } |
3d0c27ad | 2717 | |
578e1c4d JS |
2718 | /* |
2719 | * We need to ensure that the marking of unsync pages is visible | |
2720 | * before the SPTE is updated to allow writes because | |
2721 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2722 | * the MMU lock and so can race with this. If the SPTE was updated | |
2723 | * before the page had been marked as unsync-ed, something like the | |
2724 | * following could happen: | |
2725 | * | |
2726 | * CPU 1 CPU 2 | |
2727 | * --------------------------------------------------------------------- | |
2728 | * 1.2 Host updates SPTE | |
2729 | * to be writable | |
2730 | * 2.1 Guest writes a GPTE for GVA X. | |
2731 | * (GPTE being in the guest page table shadowed | |
2732 | * by the SP from CPU 1.) | |
2733 | * This reads SPTE during the page table walk. | |
2734 | * Since SPTE.W is read as 1, there is no | |
2735 | * fault. | |
2736 | * | |
2737 | * 2.2 Guest issues TLB flush. | |
2738 | * That causes a VM Exit. | |
2739 | * | |
2740 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2741 | * Since it is false, so it just returns. | |
2742 | * | |
2743 | * 2.4 Guest accesses GVA X. | |
2744 | * Since the mapping in the SP was not updated, | |
2745 | * so the old mapping for GVA X incorrectly | |
2746 | * gets used. | |
2747 | * 1.1 Host marks SP | |
2748 | * as unsync | |
2749 | * (sp->unsync = true) | |
2750 | * | |
2751 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2752 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2753 | * pairs with this write barrier. | |
2754 | */ | |
2755 | smp_wmb(); | |
2756 | ||
3d0c27ad | 2757 | return false; |
4731d4c7 MT |
2758 | } |
2759 | ||
ba049e93 | 2760 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2761 | { |
2762 | if (pfn_valid(pfn)) | |
aa2e063a HZ |
2763 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && |
2764 | /* | |
2765 | * Some reserved pages, such as those from NVDIMM | |
2766 | * DAX devices, are not for MMIO, and can be mapped | |
2767 | * with cached memory type for better performance. | |
2768 | * However, the above check misconceives those pages | |
2769 | * as MMIO, and results in KVM mapping them with UC | |
2770 | * memory type, which would hurt the performance. | |
2771 | * Therefore, we check the host memory type in addition | |
2772 | * and only treat UC/UC-/WC pages as MMIO. | |
2773 | */ | |
2774 | (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); | |
d1fe9219 PB |
2775 | |
2776 | return true; | |
2777 | } | |
2778 | ||
5ce4786f JS |
2779 | /* Bits which may be returned by set_spte() */ |
2780 | #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) | |
2781 | #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) | |
2782 | ||
d555c333 | 2783 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2784 | unsigned pte_access, int level, |
ba049e93 | 2785 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2786 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2787 | { |
ffb128c8 | 2788 | u64 spte = 0; |
1e73f9dd | 2789 | int ret = 0; |
ac8d57e5 | 2790 | struct kvm_mmu_page *sp; |
64d4d521 | 2791 | |
54bf36aa | 2792 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2793 | return 0; |
2794 | ||
ac8d57e5 PF |
2795 | sp = page_header(__pa(sptep)); |
2796 | if (sp_ad_disabled(sp)) | |
2797 | spte |= shadow_acc_track_value; | |
2798 | ||
d95c5568 BD |
2799 | /* |
2800 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2801 | * supports exec-only page table entries. In that case, | |
2802 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2803 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2804 | */ | |
ffb128c8 | 2805 | spte |= shadow_present_mask; |
947da538 | 2806 | if (!speculative) |
ac8d57e5 | 2807 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2808 | |
7b52345e SY |
2809 | if (pte_access & ACC_EXEC_MASK) |
2810 | spte |= shadow_x_mask; | |
2811 | else | |
2812 | spte |= shadow_nx_mask; | |
49fde340 | 2813 | |
1c4f1fd6 | 2814 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2815 | spte |= shadow_user_mask; |
49fde340 | 2816 | |
852e3c19 | 2817 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2818 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2819 | if (tdp_enabled) |
4b12f0de | 2820 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2821 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2822 | |
9bdbba13 | 2823 | if (host_writable) |
1403283a | 2824 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2825 | else |
2826 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2827 | |
daaf216c TL |
2828 | if (!kvm_is_mmio_pfn(pfn)) |
2829 | spte |= shadow_me_mask; | |
2830 | ||
35149e21 | 2831 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2832 | |
c2288505 | 2833 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2834 | |
c2193463 | 2835 | /* |
7751babd XG |
2836 | * Other vcpu creates new sp in the window between |
2837 | * mapping_level() and acquiring mmu-lock. We can | |
2838 | * allow guest to retry the access, the mapping can | |
2839 | * be fixed if guest refault. | |
c2193463 | 2840 | */ |
852e3c19 | 2841 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2842 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2843 | goto done; |
38187c83 | 2844 | |
49fde340 | 2845 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2846 | |
ecc5589f MT |
2847 | /* |
2848 | * Optimization: for pte sync, if spte was writable the hash | |
2849 | * lookup is unnecessary (and expensive). Write protection | |
2850 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2851 | * Same reasoning can be applied to dirty page accounting. | |
2852 | */ | |
8dae4445 | 2853 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2854 | goto set_pte; |
2855 | ||
4731d4c7 | 2856 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2857 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2858 | __func__, gfn); |
5ce4786f | 2859 | ret |= SET_SPTE_WRITE_PROTECTED_PT; |
1c4f1fd6 | 2860 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2861 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2862 | } |
2863 | } | |
2864 | ||
9b51a630 | 2865 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2866 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2867 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2868 | } |
1c4f1fd6 | 2869 | |
f160c7b7 JS |
2870 | if (speculative) |
2871 | spte = mark_spte_for_access_track(spte); | |
2872 | ||
38187c83 | 2873 | set_pte: |
6e7d0354 | 2874 | if (mmu_spte_update(sptep, spte)) |
5ce4786f | 2875 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
be38d276 | 2876 | done: |
1e73f9dd MT |
2877 | return ret; |
2878 | } | |
2879 | ||
9b8ebbdb PB |
2880 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
2881 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, | |
2882 | bool speculative, bool host_writable) | |
1e73f9dd MT |
2883 | { |
2884 | int was_rmapped = 0; | |
53a27b39 | 2885 | int rmap_count; |
5ce4786f | 2886 | int set_spte_ret; |
9b8ebbdb | 2887 | int ret = RET_PF_RETRY; |
1e73f9dd | 2888 | |
f7616203 XG |
2889 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2890 | *sptep, write_fault, gfn); | |
1e73f9dd | 2891 | |
afd28fe1 | 2892 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2893 | /* |
2894 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2895 | * the parent of the now unreachable PTE. | |
2896 | */ | |
852e3c19 JR |
2897 | if (level > PT_PAGE_TABLE_LEVEL && |
2898 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2899 | struct kvm_mmu_page *child; |
d555c333 | 2900 | u64 pte = *sptep; |
1e73f9dd MT |
2901 | |
2902 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2903 | drop_parent_pte(child, sptep); |
3be2264b | 2904 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2905 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2906 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2907 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2908 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2909 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2910 | } else |
2911 | was_rmapped = 1; | |
1e73f9dd | 2912 | } |
852e3c19 | 2913 | |
5ce4786f JS |
2914 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2915 | speculative, true, host_writable); | |
2916 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2917 | if (write_fault) |
9b8ebbdb | 2918 | ret = RET_PF_EMULATE; |
77c3913b | 2919 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2920 | } |
5ce4786f JS |
2921 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
2922 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1e73f9dd | 2923 | |
029499b4 | 2924 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 2925 | ret = RET_PF_EMULATE; |
ce88decf | 2926 | |
d555c333 | 2927 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2928 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2929 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 2930 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 2931 | *sptep, sptep); |
d555c333 | 2932 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2933 | ++vcpu->kvm->stat.lpages; |
2934 | ||
ffb61bb3 | 2935 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2936 | if (!was_rmapped) { |
2937 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2938 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2939 | rmap_recycle(vcpu, sptep, gfn); | |
2940 | } | |
1c4f1fd6 | 2941 | } |
cb9aaa30 | 2942 | |
f3ac1a4b | 2943 | kvm_release_pfn_clean(pfn); |
029499b4 | 2944 | |
9b8ebbdb | 2945 | return ret; |
1c4f1fd6 AK |
2946 | } |
2947 | ||
ba049e93 | 2948 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2949 | bool no_dirty_log) |
2950 | { | |
2951 | struct kvm_memory_slot *slot; | |
957ed9ef | 2952 | |
5d163b1c | 2953 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2954 | if (!slot) |
6c8ee57b | 2955 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2956 | |
037d92dc | 2957 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2958 | } |
2959 | ||
2960 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2961 | struct kvm_mmu_page *sp, | |
2962 | u64 *start, u64 *end) | |
2963 | { | |
2964 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2965 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2966 | unsigned access = sp->role.access; |
2967 | int i, ret; | |
2968 | gfn_t gfn; | |
2969 | ||
2970 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2971 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2972 | if (!slot) | |
957ed9ef XG |
2973 | return -1; |
2974 | ||
d9ef13c2 | 2975 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2976 | if (ret <= 0) |
2977 | return -1; | |
2978 | ||
2979 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2980 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2981 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2982 | |
2983 | return 0; | |
2984 | } | |
2985 | ||
2986 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2987 | struct kvm_mmu_page *sp, u64 *sptep) | |
2988 | { | |
2989 | u64 *spte, *start = NULL; | |
2990 | int i; | |
2991 | ||
2992 | WARN_ON(!sp->role.direct); | |
2993 | ||
2994 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2995 | spte = sp->spt + i; | |
2996 | ||
2997 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2998 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2999 | if (!start) |
3000 | continue; | |
3001 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
3002 | break; | |
3003 | start = NULL; | |
3004 | } else if (!start) | |
3005 | start = spte; | |
3006 | } | |
3007 | } | |
3008 | ||
3009 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
3010 | { | |
3011 | struct kvm_mmu_page *sp; | |
3012 | ||
ac8d57e5 PF |
3013 | sp = page_header(__pa(sptep)); |
3014 | ||
957ed9ef | 3015 | /* |
ac8d57e5 PF |
3016 | * Without accessed bits, there's no way to distinguish between |
3017 | * actually accessed translations and prefetched, so disable pte | |
3018 | * prefetch if accessed bits aren't available. | |
957ed9ef | 3019 | */ |
ac8d57e5 | 3020 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
3021 | return; |
3022 | ||
957ed9ef XG |
3023 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
3024 | return; | |
3025 | ||
3026 | __direct_pte_prefetch(vcpu, sp, sptep); | |
3027 | } | |
3028 | ||
7ee0e5b2 | 3029 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 3030 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 3031 | { |
9f652d21 | 3032 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 3033 | struct kvm_mmu_page *sp; |
b90a0e6c | 3034 | int emulate = 0; |
140754bc | 3035 | gfn_t pseudo_gfn; |
6aa8b732 | 3036 | |
989c6b34 MT |
3037 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3038 | return 0; | |
3039 | ||
9f652d21 | 3040 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 3041 | if (iterator.level == level) { |
029499b4 TY |
3042 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
3043 | write, level, gfn, pfn, prefault, | |
3044 | map_writable); | |
957ed9ef | 3045 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
3046 | ++vcpu->stat.pf_fixed; |
3047 | break; | |
6aa8b732 AK |
3048 | } |
3049 | ||
404381c5 | 3050 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 3051 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
3052 | u64 base_addr = iterator.addr; |
3053 | ||
3054 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
3055 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 3056 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 3057 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 3058 | |
98bba238 | 3059 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
3060 | } |
3061 | } | |
b90a0e6c | 3062 | return emulate; |
6aa8b732 AK |
3063 | } |
3064 | ||
77db5cbd | 3065 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3066 | { |
77db5cbd HY |
3067 | siginfo_t info; |
3068 | ||
3eb0f519 | 3069 | clear_siginfo(&info); |
77db5cbd HY |
3070 | info.si_signo = SIGBUS; |
3071 | info.si_errno = 0; | |
3072 | info.si_code = BUS_MCEERR_AR; | |
3073 | info.si_addr = (void __user *)address; | |
3074 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 3075 | |
77db5cbd | 3076 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
3077 | } |
3078 | ||
ba049e93 | 3079 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3080 | { |
4d8b81ab XG |
3081 | /* |
3082 | * Do not cache the mmio info caused by writing the readonly gfn | |
3083 | * into the spte otherwise read access on readonly gfn also can | |
3084 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3085 | */ |
3086 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3087 | return RET_PF_EMULATE; |
4d8b81ab | 3088 | |
e6c1502b | 3089 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3090 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3091 | return RET_PF_RETRY; |
d7c55201 | 3092 | } |
edba23e5 | 3093 | |
2c151b25 | 3094 | return -EFAULT; |
bf998156 HY |
3095 | } |
3096 | ||
936a5fe6 | 3097 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3098 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3099 | int *levelp) | |
936a5fe6 | 3100 | { |
ba049e93 | 3101 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3102 | gfn_t gfn = *gfnp; |
3103 | int level = *levelp; | |
3104 | ||
3105 | /* | |
3106 | * Check if it's a transparent hugepage. If this would be an | |
3107 | * hugetlbfs page, level wouldn't be set to | |
3108 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3109 | * here. | |
3110 | */ | |
bf4bea8e | 3111 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3112 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3113 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3114 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3115 | unsigned long mask; |
3116 | /* | |
3117 | * mmu_notifier_retry was successful and we hold the | |
3118 | * mmu_lock here, so the pmd can't become splitting | |
3119 | * from under us, and in turn | |
3120 | * __split_huge_page_refcount() can't run from under | |
3121 | * us and we can safely transfer the refcount from | |
3122 | * PG_tail to PG_head as we switch the pfn to tail to | |
3123 | * head. | |
3124 | */ | |
3125 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3126 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3127 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3128 | if (pfn & mask) { | |
3129 | gfn &= ~mask; | |
3130 | *gfnp = gfn; | |
3131 | kvm_release_pfn_clean(pfn); | |
3132 | pfn &= ~mask; | |
c3586667 | 3133 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3134 | *pfnp = pfn; |
3135 | } | |
3136 | } | |
3137 | } | |
3138 | ||
d7c55201 | 3139 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3140 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3141 | { |
d7c55201 | 3142 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3143 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3144 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3145 | return true; |
d7c55201 XG |
3146 | } |
3147 | ||
ce88decf | 3148 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3149 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3150 | |
798e88b3 | 3151 | return false; |
d7c55201 XG |
3152 | } |
3153 | ||
e5552fd2 | 3154 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3155 | { |
1c118b82 XG |
3156 | /* |
3157 | * Do not fix the mmio spte with invalid generation number which | |
3158 | * need to be updated by slow page fault path. | |
3159 | */ | |
3160 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3161 | return false; | |
3162 | ||
f160c7b7 JS |
3163 | /* See if the page fault is due to an NX violation */ |
3164 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3165 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3166 | return false; | |
3167 | ||
c7ba5b48 | 3168 | /* |
f160c7b7 JS |
3169 | * #PF can be fast if: |
3170 | * 1. The shadow page table entry is not present, which could mean that | |
3171 | * the fault is potentially caused by access tracking (if enabled). | |
3172 | * 2. The shadow page table entry is present and the fault | |
3173 | * is caused by write-protect, that means we just need change the W | |
3174 | * bit of the spte which can be done out of mmu-lock. | |
3175 | * | |
3176 | * However, if access tracking is disabled we know that a non-present | |
3177 | * page must be a genuine page fault where we have to create a new SPTE. | |
3178 | * So, if access tracking is disabled, we return true only for write | |
3179 | * accesses to a present page. | |
c7ba5b48 | 3180 | */ |
c7ba5b48 | 3181 | |
f160c7b7 JS |
3182 | return shadow_acc_track_mask != 0 || |
3183 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3184 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3185 | } |
3186 | ||
97dceba2 JS |
3187 | /* |
3188 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3189 | * someone else modified the SPTE from its original value. | |
3190 | */ | |
c7ba5b48 | 3191 | static bool |
92a476cb | 3192 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3193 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3194 | { |
c7ba5b48 XG |
3195 | gfn_t gfn; |
3196 | ||
3197 | WARN_ON(!sp->role.direct); | |
3198 | ||
9b51a630 KH |
3199 | /* |
3200 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3201 | * order to eliminate unnecessary PML logging. See comments in | |
3202 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3203 | * enabled, so we do not do this. This might result in the same GPA | |
3204 | * to be logged in PML buffer again when the write really happens, and | |
3205 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3206 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3207 | * so non-PML cases won't be impacted. | |
3208 | * | |
3209 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3210 | */ | |
f160c7b7 | 3211 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3212 | return false; |
3213 | ||
d3e328f2 | 3214 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3215 | /* |
3216 | * The gfn of direct spte is stable since it is | |
3217 | * calculated by sp->gfn. | |
3218 | */ | |
3219 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3220 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3221 | } | |
c7ba5b48 XG |
3222 | |
3223 | return true; | |
3224 | } | |
3225 | ||
d3e328f2 JS |
3226 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3227 | { | |
3228 | if (fault_err_code & PFERR_FETCH_MASK) | |
3229 | return is_executable_pte(spte); | |
3230 | ||
3231 | if (fault_err_code & PFERR_WRITE_MASK) | |
3232 | return is_writable_pte(spte); | |
3233 | ||
3234 | /* Fault was on Read access */ | |
3235 | return spte & PT_PRESENT_MASK; | |
3236 | } | |
3237 | ||
c7ba5b48 XG |
3238 | /* |
3239 | * Return value: | |
3240 | * - true: let the vcpu to access on the same address again. | |
3241 | * - false: let the real page fault path to fix it. | |
3242 | */ | |
3243 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3244 | u32 error_code) | |
3245 | { | |
3246 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3247 | struct kvm_mmu_page *sp; |
97dceba2 | 3248 | bool fault_handled = false; |
c7ba5b48 | 3249 | u64 spte = 0ull; |
97dceba2 | 3250 | uint retry_count = 0; |
c7ba5b48 | 3251 | |
37f6a4e2 MT |
3252 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3253 | return false; | |
3254 | ||
e5552fd2 | 3255 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3256 | return false; |
3257 | ||
3258 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3259 | |
97dceba2 | 3260 | do { |
d3e328f2 | 3261 | u64 new_spte; |
c7ba5b48 | 3262 | |
d162f30a JS |
3263 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3264 | if (!is_shadow_present_pte(spte) || | |
3265 | iterator.level < level) | |
3266 | break; | |
3267 | ||
97dceba2 JS |
3268 | sp = page_header(__pa(iterator.sptep)); |
3269 | if (!is_last_spte(spte, sp->role.level)) | |
3270 | break; | |
c7ba5b48 | 3271 | |
97dceba2 | 3272 | /* |
f160c7b7 JS |
3273 | * Check whether the memory access that caused the fault would |
3274 | * still cause it if it were to be performed right now. If not, | |
3275 | * then this is a spurious fault caused by TLB lazily flushed, | |
3276 | * or some other CPU has already fixed the PTE after the | |
3277 | * current CPU took the fault. | |
97dceba2 JS |
3278 | * |
3279 | * Need not check the access of upper level table entries since | |
3280 | * they are always ACC_ALL. | |
3281 | */ | |
d3e328f2 JS |
3282 | if (is_access_allowed(error_code, spte)) { |
3283 | fault_handled = true; | |
3284 | break; | |
3285 | } | |
f160c7b7 | 3286 | |
d3e328f2 JS |
3287 | new_spte = spte; |
3288 | ||
3289 | if (is_access_track_spte(spte)) | |
3290 | new_spte = restore_acc_track_spte(new_spte); | |
3291 | ||
3292 | /* | |
3293 | * Currently, to simplify the code, write-protection can | |
3294 | * be removed in the fast path only if the SPTE was | |
3295 | * write-protected for dirty-logging or access tracking. | |
3296 | */ | |
3297 | if ((error_code & PFERR_WRITE_MASK) && | |
3298 | spte_can_locklessly_be_made_writable(spte)) | |
3299 | { | |
3300 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3301 | |
3302 | /* | |
d3e328f2 JS |
3303 | * Do not fix write-permission on the large spte. Since |
3304 | * we only dirty the first page into the dirty-bitmap in | |
3305 | * fast_pf_fix_direct_spte(), other pages are missed | |
3306 | * if its slot has dirty logging enabled. | |
3307 | * | |
3308 | * Instead, we let the slow page fault path create a | |
3309 | * normal spte to fix the access. | |
3310 | * | |
3311 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3312 | */ |
d3e328f2 | 3313 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3314 | break; |
97dceba2 | 3315 | } |
c7ba5b48 | 3316 | |
f160c7b7 | 3317 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3318 | if (new_spte == spte || |
3319 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3320 | break; |
3321 | ||
3322 | /* | |
3323 | * Currently, fast page fault only works for direct mapping | |
3324 | * since the gfn is not stable for indirect shadow page. See | |
3325 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3326 | */ | |
3327 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3328 | iterator.sptep, spte, |
d3e328f2 | 3329 | new_spte); |
97dceba2 JS |
3330 | if (fault_handled) |
3331 | break; | |
3332 | ||
3333 | if (++retry_count > 4) { | |
3334 | printk_once(KERN_WARNING | |
3335 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3336 | break; | |
3337 | } | |
3338 | ||
97dceba2 | 3339 | } while (true); |
c126d94f | 3340 | |
a72faf25 | 3341 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3342 | spte, fault_handled); |
c7ba5b48 XG |
3343 | walk_shadow_page_lockless_end(vcpu); |
3344 | ||
97dceba2 | 3345 | return fault_handled; |
c7ba5b48 XG |
3346 | } |
3347 | ||
78b2c54a | 3348 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3349 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3350 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3351 | |
c7ba5b48 XG |
3352 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3353 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3354 | { |
3355 | int r; | |
852e3c19 | 3356 | int level; |
fd136902 | 3357 | bool force_pt_level = false; |
ba049e93 | 3358 | kvm_pfn_t pfn; |
e930bffe | 3359 | unsigned long mmu_seq; |
c7ba5b48 | 3360 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3361 | |
fd136902 | 3362 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3363 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3364 | /* |
3365 | * This path builds a PAE pagetable - so we can map | |
3366 | * 2mb pages at maximum. Therefore check if the level | |
3367 | * is larger than that. | |
3368 | */ | |
3369 | if (level > PT_DIRECTORY_LEVEL) | |
3370 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3371 | |
936a5fe6 | 3372 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3373 | } |
05da4558 | 3374 | |
c7ba5b48 | 3375 | if (fast_page_fault(vcpu, v, level, error_code)) |
9b8ebbdb | 3376 | return RET_PF_RETRY; |
c7ba5b48 | 3377 | |
e930bffe | 3378 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3379 | smp_rmb(); |
060c2abe | 3380 | |
78b2c54a | 3381 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
9b8ebbdb | 3382 | return RET_PF_RETRY; |
aaee2c94 | 3383 | |
d7c55201 XG |
3384 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3385 | return r; | |
d196e343 | 3386 | |
aaee2c94 | 3387 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3388 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3389 | goto out_unlock; |
26eeb53c WL |
3390 | if (make_mmu_pages_available(vcpu) < 0) |
3391 | goto out_unlock; | |
936a5fe6 AA |
3392 | if (likely(!force_pt_level)) |
3393 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3394 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3395 | spin_unlock(&vcpu->kvm->mmu_lock); |
3396 | ||
10589a46 | 3397 | return r; |
e930bffe AA |
3398 | |
3399 | out_unlock: | |
3400 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3401 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 3402 | return RET_PF_RETRY; |
10589a46 MT |
3403 | } |
3404 | ||
74b566e6 JS |
3405 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3406 | struct list_head *invalid_list) | |
17ac10ad | 3407 | { |
4db35314 | 3408 | struct kvm_mmu_page *sp; |
17ac10ad | 3409 | |
74b566e6 | 3410 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3411 | return; |
35af577a | 3412 | |
74b566e6 JS |
3413 | sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK); |
3414 | --sp->root_count; | |
3415 | if (!sp->root_count && sp->role.invalid) | |
3416 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3417 | |
74b566e6 JS |
3418 | *root_hpa = INVALID_PAGE; |
3419 | } | |
3420 | ||
7c390d35 | 3421 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, bool free_prev_root) |
74b566e6 JS |
3422 | { |
3423 | int i; | |
3424 | LIST_HEAD(invalid_list); | |
3425 | struct kvm_mmu *mmu = &vcpu->arch.mmu; | |
3426 | ||
7c390d35 JS |
3427 | if (!VALID_PAGE(mmu->root_hpa) && |
3428 | (!VALID_PAGE(mmu->prev_root.hpa) || !free_prev_root)) | |
17ac10ad | 3429 | return; |
35af577a GN |
3430 | |
3431 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3432 | |
7c390d35 JS |
3433 | if (free_prev_root) |
3434 | mmu_free_root_page(vcpu->kvm, &mmu->prev_root.hpa, | |
3435 | &invalid_list); | |
3436 | ||
74b566e6 JS |
3437 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && |
3438 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
3439 | mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, &invalid_list); | |
3440 | } else { | |
3441 | for (i = 0; i < 4; ++i) | |
3442 | if (mmu->pae_root[i] != 0) | |
3443 | mmu_free_root_page(vcpu->kvm, &mmu->pae_root[i], | |
3444 | &invalid_list); | |
3445 | mmu->root_hpa = INVALID_PAGE; | |
17ac10ad | 3446 | } |
74b566e6 | 3447 | |
d98ba053 | 3448 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3449 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad | 3450 | } |
74b566e6 | 3451 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3452 | |
8986ecc0 MT |
3453 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3454 | { | |
3455 | int ret = 0; | |
3456 | ||
3457 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3458 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3459 | ret = 1; |
3460 | } | |
3461 | ||
3462 | return ret; | |
3463 | } | |
3464 | ||
651dd37a JR |
3465 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3466 | { | |
3467 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3468 | unsigned i; |
651dd37a | 3469 | |
855feb67 | 3470 | if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3471 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3472 | if(make_mmu_pages_available(vcpu) < 0) { |
3473 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3474 | return -ENOSPC; |
26eeb53c | 3475 | } |
855feb67 YZ |
3476 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
3477 | vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL); | |
651dd37a JR |
3478 | ++sp->root_count; |
3479 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3480 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3481 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3482 | for (i = 0; i < 4; ++i) { | |
3483 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3484 | ||
fa4a2c08 | 3485 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3486 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3487 | if (make_mmu_pages_available(vcpu) < 0) { |
3488 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3489 | return -ENOSPC; |
26eeb53c | 3490 | } |
649497d1 | 3491 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3492 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3493 | root = __pa(sp->spt); |
3494 | ++sp->root_count; | |
3495 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3496 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3497 | } |
6292757f | 3498 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3499 | } else |
3500 | BUG(); | |
3501 | ||
3502 | return 0; | |
3503 | } | |
3504 | ||
3505 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3506 | { |
4db35314 | 3507 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3508 | u64 pdptr, pm_mask; |
3509 | gfn_t root_gfn; | |
3510 | int i; | |
3bb65a22 | 3511 | |
5777ed34 | 3512 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3513 | |
651dd37a JR |
3514 | if (mmu_check_root(vcpu, root_gfn)) |
3515 | return 1; | |
3516 | ||
3517 | /* | |
3518 | * Do we shadow a long mode page table? If so we need to | |
3519 | * write-protect the guests page table root. | |
3520 | */ | |
855feb67 | 3521 | if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) { |
ad312c7c | 3522 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3523 | |
fa4a2c08 | 3524 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3525 | |
8facbbff | 3526 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3527 | if (make_mmu_pages_available(vcpu) < 0) { |
3528 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3529 | return -ENOSPC; |
26eeb53c | 3530 | } |
855feb67 YZ |
3531 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
3532 | vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL); | |
4db35314 AK |
3533 | root = __pa(sp->spt); |
3534 | ++sp->root_count; | |
8facbbff | 3535 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3536 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3537 | return 0; |
17ac10ad | 3538 | } |
f87f9288 | 3539 | |
651dd37a JR |
3540 | /* |
3541 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3542 | * or a PAE 3-level page table. In either case we need to be aware that |
3543 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3544 | */ |
81407ca5 | 3545 | pm_mask = PT_PRESENT_MASK; |
2a7266a8 | 3546 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3547 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3548 | ||
17ac10ad | 3549 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3550 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3551 | |
fa4a2c08 | 3552 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3553 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3554 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
812f30b2 | 3555 | if (!(pdptr & PT_PRESENT_MASK)) { |
ad312c7c | 3556 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3557 | continue; |
3558 | } | |
6de4f3ad | 3559 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3560 | if (mmu_check_root(vcpu, root_gfn)) |
3561 | return 1; | |
5a7388c2 | 3562 | } |
8facbbff | 3563 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3564 | if (make_mmu_pages_available(vcpu) < 0) { |
3565 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3566 | return -ENOSPC; |
26eeb53c | 3567 | } |
bb11c6c9 TY |
3568 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3569 | 0, ACC_ALL); | |
4db35314 AK |
3570 | root = __pa(sp->spt); |
3571 | ++sp->root_count; | |
8facbbff AK |
3572 | spin_unlock(&vcpu->kvm->mmu_lock); |
3573 | ||
81407ca5 | 3574 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3575 | } |
6292757f | 3576 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3577 | |
3578 | /* | |
3579 | * If we shadow a 32 bit page table with a long mode page | |
3580 | * table we enter this path. | |
3581 | */ | |
2a7266a8 | 3582 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3583 | if (vcpu->arch.mmu.lm_root == NULL) { |
3584 | /* | |
3585 | * The additional page necessary for this is only | |
3586 | * allocated on demand. | |
3587 | */ | |
3588 | ||
3589 | u64 *lm_root; | |
3590 | ||
3591 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3592 | if (lm_root == NULL) | |
3593 | return 1; | |
3594 | ||
3595 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3596 | ||
3597 | vcpu->arch.mmu.lm_root = lm_root; | |
3598 | } | |
3599 | ||
3600 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3601 | } | |
3602 | ||
8986ecc0 | 3603 | return 0; |
17ac10ad AK |
3604 | } |
3605 | ||
651dd37a JR |
3606 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3607 | { | |
3608 | if (vcpu->arch.mmu.direct_map) | |
3609 | return mmu_alloc_direct_roots(vcpu); | |
3610 | else | |
3611 | return mmu_alloc_shadow_roots(vcpu); | |
3612 | } | |
3613 | ||
578e1c4d | 3614 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3615 | { |
3616 | int i; | |
3617 | struct kvm_mmu_page *sp; | |
3618 | ||
81407ca5 JR |
3619 | if (vcpu->arch.mmu.direct_map) |
3620 | return; | |
3621 | ||
0ba73cda MT |
3622 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3623 | return; | |
6903074c | 3624 | |
56f17dd3 | 3625 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3626 | |
855feb67 | 3627 | if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) { |
0ba73cda | 3628 | hpa_t root = vcpu->arch.mmu.root_hpa; |
578e1c4d | 3629 | |
0ba73cda | 3630 | sp = page_header(root); |
578e1c4d JS |
3631 | |
3632 | /* | |
3633 | * Even if another CPU was marking the SP as unsync-ed | |
3634 | * simultaneously, any guest page table changes are not | |
3635 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3636 | * flush strictly after those changes are made. We only need to | |
3637 | * ensure that the other CPU sets these flags before any actual | |
3638 | * changes to the page tables are made. The comments in | |
3639 | * mmu_need_write_protect() describe what could go wrong if this | |
3640 | * requirement isn't satisfied. | |
3641 | */ | |
3642 | if (!smp_load_acquire(&sp->unsync) && | |
3643 | !smp_load_acquire(&sp->unsync_children)) | |
3644 | return; | |
3645 | ||
3646 | spin_lock(&vcpu->kvm->mmu_lock); | |
3647 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3648 | ||
0ba73cda | 3649 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3650 | |
0375f7fa | 3651 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3652 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3653 | return; |
3654 | } | |
578e1c4d JS |
3655 | |
3656 | spin_lock(&vcpu->kvm->mmu_lock); | |
3657 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3658 | ||
0ba73cda MT |
3659 | for (i = 0; i < 4; ++i) { |
3660 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3661 | ||
8986ecc0 | 3662 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3663 | root &= PT64_BASE_ADDR_MASK; |
3664 | sp = page_header(root); | |
3665 | mmu_sync_children(vcpu, sp); | |
3666 | } | |
3667 | } | |
0ba73cda | 3668 | |
578e1c4d | 3669 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3670 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3671 | } |
bfd0a56b | 3672 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3673 | |
1871c602 | 3674 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3675 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3676 | { |
ab9ae313 AK |
3677 | if (exception) |
3678 | exception->error_code = 0; | |
6aa8b732 AK |
3679 | return vaddr; |
3680 | } | |
3681 | ||
6539e738 | 3682 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3683 | u32 access, |
3684 | struct x86_exception *exception) | |
6539e738 | 3685 | { |
ab9ae313 AK |
3686 | if (exception) |
3687 | exception->error_code = 0; | |
54987b7a | 3688 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3689 | } |
3690 | ||
d625b155 XG |
3691 | static bool |
3692 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3693 | { | |
3694 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3695 | ||
3696 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3697 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3698 | } | |
3699 | ||
3700 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3701 | { | |
3702 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3703 | } | |
3704 | ||
3705 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3706 | { | |
3707 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3708 | } | |
3709 | ||
ded58749 | 3710 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3711 | { |
9034e6e8 PB |
3712 | /* |
3713 | * A nested guest cannot use the MMIO cache if it is using nested | |
3714 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3715 | */ | |
3716 | if (mmu_is_nested(vcpu)) | |
3717 | return false; | |
3718 | ||
ce88decf XG |
3719 | if (direct) |
3720 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3721 | ||
3722 | return vcpu_match_mmio_gva(vcpu, addr); | |
3723 | } | |
3724 | ||
47ab8751 XG |
3725 | /* return true if reserved bit is detected on spte. */ |
3726 | static bool | |
3727 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3728 | { |
3729 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3730 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
47ab8751 XG |
3731 | int root, leaf; |
3732 | bool reserved = false; | |
ce88decf | 3733 | |
37f6a4e2 | 3734 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3735 | goto exit; |
37f6a4e2 | 3736 | |
ce88decf | 3737 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3738 | |
29ecd660 PB |
3739 | for (shadow_walk_init(&iterator, vcpu, addr), |
3740 | leaf = root = iterator.level; | |
47ab8751 XG |
3741 | shadow_walk_okay(&iterator); |
3742 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3743 | spte = mmu_spte_get_lockless(iterator.sptep); |
3744 | ||
3745 | sptes[leaf - 1] = spte; | |
29ecd660 | 3746 | leaf--; |
47ab8751 | 3747 | |
ce88decf XG |
3748 | if (!is_shadow_present_pte(spte)) |
3749 | break; | |
47ab8751 XG |
3750 | |
3751 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3752 | iterator.level); |
47ab8751 XG |
3753 | } |
3754 | ||
ce88decf XG |
3755 | walk_shadow_page_lockless_end(vcpu); |
3756 | ||
47ab8751 XG |
3757 | if (reserved) { |
3758 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3759 | __func__, addr); | |
29ecd660 | 3760 | while (root > leaf) { |
47ab8751 XG |
3761 | pr_err("------ spte 0x%llx level %d.\n", |
3762 | sptes[root - 1], root); | |
3763 | root--; | |
3764 | } | |
3765 | } | |
3766 | exit: | |
3767 | *sptep = spte; | |
3768 | return reserved; | |
ce88decf XG |
3769 | } |
3770 | ||
e08d26f0 | 3771 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3772 | { |
3773 | u64 spte; | |
47ab8751 | 3774 | bool reserved; |
ce88decf | 3775 | |
ded58749 | 3776 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3777 | return RET_PF_EMULATE; |
ce88decf | 3778 | |
47ab8751 | 3779 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3780 | if (WARN_ON(reserved)) |
9b8ebbdb | 3781 | return -EINVAL; |
ce88decf XG |
3782 | |
3783 | if (is_mmio_spte(spte)) { | |
3784 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3785 | unsigned access = get_mmio_spte_access(spte); | |
3786 | ||
54bf36aa | 3787 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3788 | return RET_PF_INVALID; |
f8f55942 | 3789 | |
ce88decf XG |
3790 | if (direct) |
3791 | addr = 0; | |
4f022648 XG |
3792 | |
3793 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3794 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3795 | return RET_PF_EMULATE; |
ce88decf XG |
3796 | } |
3797 | ||
ce88decf XG |
3798 | /* |
3799 | * If the page table is zapped by other cpus, let CPU fault again on | |
3800 | * the address. | |
3801 | */ | |
9b8ebbdb | 3802 | return RET_PF_RETRY; |
ce88decf | 3803 | } |
ce88decf | 3804 | |
3d0c27ad XG |
3805 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3806 | u32 error_code, gfn_t gfn) | |
3807 | { | |
3808 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3809 | return false; | |
3810 | ||
3811 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3812 | !(error_code & PFERR_WRITE_MASK)) | |
3813 | return false; | |
3814 | ||
3815 | /* | |
3816 | * guest is writing the page which is write tracked which can | |
3817 | * not be fixed by page fault handler. | |
3818 | */ | |
3819 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3820 | return true; | |
3821 | ||
3822 | return false; | |
3823 | } | |
3824 | ||
e5691a81 XG |
3825 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3826 | { | |
3827 | struct kvm_shadow_walk_iterator iterator; | |
3828 | u64 spte; | |
3829 | ||
3830 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3831 | return; | |
3832 | ||
3833 | walk_shadow_page_lockless_begin(vcpu); | |
3834 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3835 | clear_sp_write_flooding_count(iterator.sptep); | |
3836 | if (!is_shadow_present_pte(spte)) | |
3837 | break; | |
3838 | } | |
3839 | walk_shadow_page_lockless_end(vcpu); | |
3840 | } | |
3841 | ||
6aa8b732 | 3842 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3843 | u32 error_code, bool prefault) |
6aa8b732 | 3844 | { |
3d0c27ad | 3845 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3846 | int r; |
6aa8b732 | 3847 | |
b8688d51 | 3848 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3849 | |
3d0c27ad | 3850 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3851 | return RET_PF_EMULATE; |
ce88decf | 3852 | |
e2dec939 AK |
3853 | r = mmu_topup_memory_caches(vcpu); |
3854 | if (r) | |
3855 | return r; | |
714b93da | 3856 | |
fa4a2c08 | 3857 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3858 | |
6aa8b732 | 3859 | |
e833240f | 3860 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3861 | error_code, gfn, prefault); |
6aa8b732 AK |
3862 | } |
3863 | ||
7e1fbeac | 3864 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3865 | { |
3866 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3867 | |
7c90705b | 3868 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3869 | arch.gfn = gfn; |
c4806acd | 3870 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3871 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3872 | |
54bf36aa | 3873 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3874 | } |
3875 | ||
9bc1f09f | 3876 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3877 | { |
35754c98 | 3878 | if (unlikely(!lapic_in_kernel(vcpu) || |
2a266f23 HZ |
3879 | kvm_event_needs_reinjection(vcpu) || |
3880 | vcpu->arch.exception.pending)) | |
af585b92 GN |
3881 | return false; |
3882 | ||
52a5c155 | 3883 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) |
9bc1f09f WL |
3884 | return false; |
3885 | ||
af585b92 GN |
3886 | return kvm_x86_ops->interrupt_allowed(vcpu); |
3887 | } | |
3888 | ||
78b2c54a | 3889 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3890 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3891 | { |
3520469d | 3892 | struct kvm_memory_slot *slot; |
af585b92 GN |
3893 | bool async; |
3894 | ||
3a2936de JM |
3895 | /* |
3896 | * Don't expose private memslots to L2. | |
3897 | */ | |
3898 | if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
3899 | *pfn = KVM_PFN_NOSLOT; | |
3900 | return false; | |
3901 | } | |
3902 | ||
54bf36aa | 3903 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3904 | async = false; |
3905 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3906 | if (!async) |
3907 | return false; /* *pfn has correct page already */ | |
3908 | ||
9bc1f09f | 3909 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 3910 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3911 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3912 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3913 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3914 | return true; | |
3915 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3916 | return true; | |
3917 | } | |
3918 | ||
3520469d | 3919 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3920 | return false; |
3921 | } | |
3922 | ||
1261bfa3 | 3923 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3924 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3925 | { |
3926 | int r = 1; | |
3927 | ||
3928 | switch (vcpu->arch.apf.host_apf_reason) { | |
3929 | default: | |
3930 | trace_kvm_page_fault(fault_address, error_code); | |
3931 | ||
d0006530 | 3932 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3933 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3934 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3935 | insn_len); | |
3936 | break; | |
3937 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
3938 | vcpu->arch.apf.host_apf_reason = 0; | |
3939 | local_irq_disable(); | |
a2b7861b | 3940 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
3941 | local_irq_enable(); |
3942 | break; | |
3943 | case KVM_PV_REASON_PAGE_READY: | |
3944 | vcpu->arch.apf.host_apf_reason = 0; | |
3945 | local_irq_disable(); | |
3946 | kvm_async_pf_task_wake(fault_address); | |
3947 | local_irq_enable(); | |
3948 | break; | |
3949 | } | |
3950 | return r; | |
3951 | } | |
3952 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3953 | ||
6a39bbc5 XG |
3954 | static bool |
3955 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3956 | { | |
3957 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3958 | ||
3959 | gfn &= ~(page_num - 1); | |
3960 | ||
3961 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3962 | } | |
3963 | ||
56028d08 | 3964 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3965 | bool prefault) |
fb72d167 | 3966 | { |
ba049e93 | 3967 | kvm_pfn_t pfn; |
fb72d167 | 3968 | int r; |
852e3c19 | 3969 | int level; |
cd1872f0 | 3970 | bool force_pt_level; |
05da4558 | 3971 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3972 | unsigned long mmu_seq; |
612819c3 MT |
3973 | int write = error_code & PFERR_WRITE_MASK; |
3974 | bool map_writable; | |
fb72d167 | 3975 | |
fa4a2c08 | 3976 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3977 | |
3d0c27ad | 3978 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3979 | return RET_PF_EMULATE; |
ce88decf | 3980 | |
fb72d167 JR |
3981 | r = mmu_topup_memory_caches(vcpu); |
3982 | if (r) | |
3983 | return r; | |
3984 | ||
fd136902 TY |
3985 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3986 | PT_DIRECTORY_LEVEL); | |
3987 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3988 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3989 | if (level > PT_DIRECTORY_LEVEL && |
3990 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3991 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3992 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3993 | } |
852e3c19 | 3994 | |
c7ba5b48 | 3995 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
9b8ebbdb | 3996 | return RET_PF_RETRY; |
c7ba5b48 | 3997 | |
e930bffe | 3998 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3999 | smp_rmb(); |
af585b92 | 4000 | |
78b2c54a | 4001 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
9b8ebbdb | 4002 | return RET_PF_RETRY; |
af585b92 | 4003 | |
d7c55201 XG |
4004 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
4005 | return r; | |
4006 | ||
fb72d167 | 4007 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 4008 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 4009 | goto out_unlock; |
26eeb53c WL |
4010 | if (make_mmu_pages_available(vcpu) < 0) |
4011 | goto out_unlock; | |
936a5fe6 AA |
4012 | if (likely(!force_pt_level)) |
4013 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 4014 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 4015 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
4016 | |
4017 | return r; | |
e930bffe AA |
4018 | |
4019 | out_unlock: | |
4020 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4021 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 4022 | return RET_PF_RETRY; |
fb72d167 JR |
4023 | } |
4024 | ||
8a3c1a33 PB |
4025 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
4026 | struct kvm_mmu *context) | |
6aa8b732 | 4027 | { |
6aa8b732 | 4028 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4029 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4030 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4031 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4032 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 4033 | context->root_level = 0; |
6aa8b732 | 4034 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4035 | context->direct_map = true; |
2d48a985 | 4036 | context->nx = false; |
6aa8b732 AK |
4037 | } |
4038 | ||
0aab33e4 JS |
4039 | static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
4040 | union kvm_mmu_page_role new_role) | |
7c390d35 JS |
4041 | { |
4042 | struct kvm_mmu *mmu = &vcpu->arch.mmu; | |
4043 | ||
4044 | /* | |
4045 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4046 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4047 | * later if necessary. | |
4048 | */ | |
4049 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
4050 | mmu->root_level >= PT64_ROOT_4LEVEL) { | |
4051 | gpa_t prev_cr3 = mmu->prev_root.cr3; | |
4052 | ||
4053 | if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT)) | |
4054 | return false; | |
4055 | ||
4056 | swap(mmu->root_hpa, mmu->prev_root.hpa); | |
4057 | mmu->prev_root.cr3 = kvm_read_cr3(vcpu); | |
4058 | ||
0aab33e4 JS |
4059 | if (new_cr3 == prev_cr3 && |
4060 | VALID_PAGE(mmu->root_hpa) && | |
4061 | page_header(mmu->root_hpa) != NULL && | |
4062 | new_role.word == page_header(mmu->root_hpa)->role.word) { | |
7c390d35 JS |
4063 | /* |
4064 | * It is possible that the cached previous root page is | |
4065 | * obsolete because of a change in the MMU | |
4066 | * generation number. However, that is accompanied by | |
4067 | * KVM_REQ_MMU_RELOAD, which will free the root that we | |
4068 | * have set here and allocate a new one. | |
4069 | */ | |
4070 | ||
0aab33e4 | 4071 | kvm_make_request(KVM_REQ_LOAD_CR3, vcpu); |
7c390d35 JS |
4072 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
4073 | __clear_sp_write_flooding_count( | |
4074 | page_header(mmu->root_hpa)); | |
4075 | ||
7c390d35 JS |
4076 | return true; |
4077 | } | |
4078 | } | |
4079 | ||
4080 | return false; | |
4081 | } | |
4082 | ||
0aab33e4 JS |
4083 | static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
4084 | union kvm_mmu_page_role new_role) | |
6aa8b732 | 4085 | { |
0aab33e4 | 4086 | if (!fast_cr3_switch(vcpu, new_cr3, new_role)) |
7c390d35 | 4087 | kvm_mmu_free_roots(vcpu, false); |
6aa8b732 AK |
4088 | } |
4089 | ||
0aab33e4 JS |
4090 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3) |
4091 | { | |
4092 | __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu)); | |
4093 | } | |
4094 | ||
5777ed34 JR |
4095 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4096 | { | |
9f8fe504 | 4097 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4098 | } |
4099 | ||
6389ee94 AK |
4100 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
4101 | struct x86_exception *fault) | |
6aa8b732 | 4102 | { |
6389ee94 | 4103 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
4104 | } |
4105 | ||
54bf36aa | 4106 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 4107 | unsigned access, int *nr_present) |
ce88decf XG |
4108 | { |
4109 | if (unlikely(is_mmio_spte(*sptep))) { | |
4110 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4111 | mmu_spte_clear_no_track(sptep); | |
4112 | return true; | |
4113 | } | |
4114 | ||
4115 | (*nr_present)++; | |
54bf36aa | 4116 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4117 | return true; |
4118 | } | |
4119 | ||
4120 | return false; | |
4121 | } | |
4122 | ||
6bb69c9b PB |
4123 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4124 | unsigned level, unsigned gpte) | |
6fd01b71 | 4125 | { |
6bb69c9b PB |
4126 | /* |
4127 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4128 | * If it is clear, there are no large pages at this level, so clear | |
4129 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4130 | */ | |
4131 | gpte &= level - mmu->last_nonleaf_level; | |
4132 | ||
829ee279 LP |
4133 | /* |
4134 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
4135 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
4136 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
4137 | */ | |
4138 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
4139 | ||
6bb69c9b | 4140 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4141 | } |
4142 | ||
37406aaa NHE |
4143 | #define PTTYPE_EPT 18 /* arbitrary */ |
4144 | #define PTTYPE PTTYPE_EPT | |
4145 | #include "paging_tmpl.h" | |
4146 | #undef PTTYPE | |
4147 | ||
6aa8b732 AK |
4148 | #define PTTYPE 64 |
4149 | #include "paging_tmpl.h" | |
4150 | #undef PTTYPE | |
4151 | ||
4152 | #define PTTYPE 32 | |
4153 | #include "paging_tmpl.h" | |
4154 | #undef PTTYPE | |
4155 | ||
6dc98b86 XG |
4156 | static void |
4157 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4158 | struct rsvd_bits_validate *rsvd_check, | |
4159 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4160 | bool pse, bool amd) |
82725b20 | 4161 | { |
82725b20 | 4162 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4163 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4164 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4165 | |
a0a64f50 | 4166 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4167 | |
6dc98b86 | 4168 | if (!nx) |
82725b20 | 4169 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4170 | if (!gbpages) |
5f7dde7b | 4171 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4172 | |
4173 | /* | |
4174 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4175 | * leaf entries) on AMD CPUs only. | |
4176 | */ | |
6fec2144 | 4177 | if (amd) |
a0c0feb5 PB |
4178 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4179 | ||
6dc98b86 | 4180 | switch (level) { |
82725b20 DE |
4181 | case PT32_ROOT_LEVEL: |
4182 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4183 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4184 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4185 | rsvd_check->rsvd_bits_mask[1][0] = | |
4186 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4187 | |
6dc98b86 | 4188 | if (!pse) { |
a0a64f50 | 4189 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4190 | break; |
4191 | } | |
4192 | ||
82725b20 DE |
4193 | if (is_cpuid_PSE36()) |
4194 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4195 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4196 | else |
4197 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4198 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4199 | break; |
4200 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4201 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4202 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4203 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4204 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4205 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4206 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4207 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4208 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4209 | rsvd_bits(maxphyaddr, 62) | |
4210 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4211 | rsvd_check->rsvd_bits_mask[1][0] = |
4212 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4213 | break; |
855feb67 YZ |
4214 | case PT64_ROOT_5LEVEL: |
4215 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4216 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4217 | rsvd_bits(maxphyaddr, 51); | |
4218 | rsvd_check->rsvd_bits_mask[1][4] = | |
4219 | rsvd_check->rsvd_bits_mask[0][4]; | |
2a7266a8 | 4220 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4221 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4222 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4223 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4224 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4225 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4226 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4227 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4228 | rsvd_bits(maxphyaddr, 51); | |
4229 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4230 | rsvd_bits(maxphyaddr, 51); | |
4231 | rsvd_check->rsvd_bits_mask[1][3] = | |
4232 | rsvd_check->rsvd_bits_mask[0][3]; | |
4233 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4234 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4235 | rsvd_bits(13, 29); |
a0a64f50 | 4236 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4237 | rsvd_bits(maxphyaddr, 51) | |
4238 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4239 | rsvd_check->rsvd_bits_mask[1][0] = |
4240 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4241 | break; |
4242 | } | |
4243 | } | |
4244 | ||
6dc98b86 XG |
4245 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4246 | struct kvm_mmu *context) | |
4247 | { | |
4248 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4249 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4250 | context->nx, |
4251 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4252 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4253 | } |
4254 | ||
81b8eebb XG |
4255 | static void |
4256 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4257 | int maxphyaddr, bool execonly) | |
25d92081 | 4258 | { |
951f9fd7 | 4259 | u64 bad_mt_xwr; |
25d92081 | 4260 | |
855feb67 YZ |
4261 | rsvd_check->rsvd_bits_mask[0][4] = |
4262 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4263 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4264 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4265 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4266 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4267 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4268 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4269 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4270 | |
4271 | /* large page */ | |
855feb67 | 4272 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4273 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4274 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4275 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4276 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4277 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4278 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4279 | |
951f9fd7 PB |
4280 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4281 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4282 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4283 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4284 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4285 | if (!execonly) { | |
4286 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4287 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4288 | } |
951f9fd7 | 4289 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4290 | } |
4291 | ||
81b8eebb XG |
4292 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4293 | struct kvm_mmu *context, bool execonly) | |
4294 | { | |
4295 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4296 | cpuid_maxphyaddr(vcpu), execonly); | |
4297 | } | |
4298 | ||
c258b62b XG |
4299 | /* |
4300 | * the page table on host is the shadow page table for the page | |
4301 | * table in guest or amd nested guest, its mmu features completely | |
4302 | * follow the features in guest. | |
4303 | */ | |
4304 | void | |
4305 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4306 | { | |
5f0b8199 | 4307 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
ea2800dd BS |
4308 | struct rsvd_bits_validate *shadow_zero_check; |
4309 | int i; | |
5f0b8199 | 4310 | |
6fec2144 PB |
4311 | /* |
4312 | * Passing "true" to the last argument is okay; it adds a check | |
4313 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4314 | */ | |
ea2800dd BS |
4315 | shadow_zero_check = &context->shadow_zero_check; |
4316 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
c258b62b | 4317 | boot_cpu_data.x86_phys_bits, |
5f0b8199 | 4318 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4319 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4320 | is_pse(vcpu), true); | |
ea2800dd BS |
4321 | |
4322 | if (!shadow_me_mask) | |
4323 | return; | |
4324 | ||
4325 | for (i = context->shadow_root_level; --i >= 0;) { | |
4326 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4327 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4328 | } | |
4329 | ||
c258b62b XG |
4330 | } |
4331 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4332 | ||
6fec2144 PB |
4333 | static inline bool boot_cpu_is_amd(void) |
4334 | { | |
4335 | WARN_ON_ONCE(!tdp_enabled); | |
4336 | return shadow_x_mask == 0; | |
4337 | } | |
4338 | ||
c258b62b XG |
4339 | /* |
4340 | * the direct page table on host, use as much mmu features as | |
4341 | * possible, however, kvm currently does not do execution-protection. | |
4342 | */ | |
4343 | static void | |
4344 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4345 | struct kvm_mmu *context) | |
4346 | { | |
ea2800dd BS |
4347 | struct rsvd_bits_validate *shadow_zero_check; |
4348 | int i; | |
4349 | ||
4350 | shadow_zero_check = &context->shadow_zero_check; | |
4351 | ||
6fec2144 | 4352 | if (boot_cpu_is_amd()) |
ea2800dd | 4353 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
c258b62b XG |
4354 | boot_cpu_data.x86_phys_bits, |
4355 | context->shadow_root_level, false, | |
b8291adc BP |
4356 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4357 | true, true); | |
c258b62b | 4358 | else |
ea2800dd | 4359 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
c258b62b XG |
4360 | boot_cpu_data.x86_phys_bits, |
4361 | false); | |
4362 | ||
ea2800dd BS |
4363 | if (!shadow_me_mask) |
4364 | return; | |
4365 | ||
4366 | for (i = context->shadow_root_level; --i >= 0;) { | |
4367 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4368 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4369 | } | |
c258b62b XG |
4370 | } |
4371 | ||
4372 | /* | |
4373 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4374 | * is the shadow page table for intel nested guest. | |
4375 | */ | |
4376 | static void | |
4377 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4378 | struct kvm_mmu *context, bool execonly) | |
4379 | { | |
4380 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4381 | boot_cpu_data.x86_phys_bits, execonly); | |
4382 | } | |
4383 | ||
09f037aa PB |
4384 | #define BYTE_MASK(access) \ |
4385 | ((1 & (access) ? 2 : 0) | \ | |
4386 | (2 & (access) ? 4 : 0) | \ | |
4387 | (3 & (access) ? 8 : 0) | \ | |
4388 | (4 & (access) ? 16 : 0) | \ | |
4389 | (5 & (access) ? 32 : 0) | \ | |
4390 | (6 & (access) ? 64 : 0) | \ | |
4391 | (7 & (access) ? 128 : 0)) | |
4392 | ||
4393 | ||
edc90b7d XG |
4394 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4395 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4396 | { |
09f037aa PB |
4397 | unsigned byte; |
4398 | ||
4399 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4400 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4401 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4402 | ||
4403 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4404 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4405 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4406 | |
97d64b78 | 4407 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4408 | unsigned pfec = byte << 1; |
4409 | ||
97ec8c06 | 4410 | /* |
09f037aa PB |
4411 | * Each "*f" variable has a 1 bit for each UWX value |
4412 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4413 | */ |
97d64b78 | 4414 | |
09f037aa PB |
4415 | /* Faults from writes to non-writable pages */ |
4416 | u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; | |
4417 | /* Faults from user mode accesses to supervisor pages */ | |
4418 | u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; | |
4419 | /* Faults from fetches of non-executable pages*/ | |
4420 | u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; | |
4421 | /* Faults from kernel mode fetches of user pages */ | |
4422 | u8 smepf = 0; | |
4423 | /* Faults from kernel mode accesses of user pages */ | |
4424 | u8 smapf = 0; | |
4425 | ||
4426 | if (!ept) { | |
4427 | /* Faults from kernel mode accesses to user pages */ | |
4428 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4429 | ||
4430 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4431 | if (!mmu->nx) | |
4432 | ff = 0; | |
4433 | ||
4434 | /* Allow supervisor writes if !cr0.wp */ | |
4435 | if (!cr0_wp) | |
4436 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4437 | ||
4438 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4439 | if (cr4_smep) | |
4440 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4441 | ||
4442 | /* | |
4443 | * SMAP:kernel-mode data accesses from user-mode | |
4444 | * mappings should fault. A fault is considered | |
4445 | * as a SMAP violation if all of the following | |
4446 | * conditions are ture: | |
4447 | * - X86_CR4_SMAP is set in CR4 | |
4448 | * - A user page is accessed | |
4449 | * - The access is not a fetch | |
4450 | * - Page fault in kernel mode | |
4451 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4452 | * | |
4453 | * Here, we cover the first three conditions. | |
4454 | * The fourth is computed dynamically in permission_fault(); | |
4455 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4456 | * *not* subject to SMAP restrictions. | |
4457 | */ | |
4458 | if (cr4_smap) | |
4459 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4460 | } |
09f037aa PB |
4461 | |
4462 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4463 | } |
4464 | } | |
4465 | ||
2d344105 HH |
4466 | /* |
4467 | * PKU is an additional mechanism by which the paging controls access to | |
4468 | * user-mode addresses based on the value in the PKRU register. Protection | |
4469 | * key violations are reported through a bit in the page fault error code. | |
4470 | * Unlike other bits of the error code, the PK bit is not known at the | |
4471 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4472 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4473 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4474 | * | |
4475 | * In particular the following conditions come from the error code, the | |
4476 | * page tables and the machine state: | |
4477 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4478 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4479 | * - PK is always zero if U=0 in the page tables | |
4480 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4481 | * | |
4482 | * The PKRU bitmask caches the result of these four conditions. The error | |
4483 | * code (minus the P bit) and the page table's U bit form an index into the | |
4484 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4485 | * with the two bits of the PKRU register corresponding to the protection key. | |
4486 | * For the first three conditions above the bits will be 00, thus masking | |
4487 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4488 | * only will be masked away. | |
4489 | */ | |
4490 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4491 | bool ept) | |
4492 | { | |
4493 | unsigned bit; | |
4494 | bool wp; | |
4495 | ||
4496 | if (ept) { | |
4497 | mmu->pkru_mask = 0; | |
4498 | return; | |
4499 | } | |
4500 | ||
4501 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4502 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4503 | mmu->pkru_mask = 0; | |
4504 | return; | |
4505 | } | |
4506 | ||
4507 | wp = is_write_protection(vcpu); | |
4508 | ||
4509 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4510 | unsigned pfec, pkey_bits; | |
4511 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4512 | ||
4513 | pfec = bit << 1; | |
4514 | ff = pfec & PFERR_FETCH_MASK; | |
4515 | uf = pfec & PFERR_USER_MASK; | |
4516 | wf = pfec & PFERR_WRITE_MASK; | |
4517 | ||
4518 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4519 | pte_user = pfec & PFERR_RSVD_MASK; | |
4520 | ||
4521 | /* | |
4522 | * Only need to check the access which is not an | |
4523 | * instruction fetch and is to a user page. | |
4524 | */ | |
4525 | check_pkey = (!ff && pte_user); | |
4526 | /* | |
4527 | * write access is controlled by PKRU if it is a | |
4528 | * user access or CR0.WP = 1. | |
4529 | */ | |
4530 | check_write = check_pkey && wf && (uf || wp); | |
4531 | ||
4532 | /* PKRU.AD stops both read and write access. */ | |
4533 | pkey_bits = !!check_pkey; | |
4534 | /* PKRU.WD stops write access. */ | |
4535 | pkey_bits |= (!!check_write) << 1; | |
4536 | ||
4537 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4538 | } | |
4539 | } | |
4540 | ||
6bb69c9b | 4541 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4542 | { |
6bb69c9b PB |
4543 | unsigned root_level = mmu->root_level; |
4544 | ||
4545 | mmu->last_nonleaf_level = root_level; | |
4546 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4547 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4548 | } |
4549 | ||
8a3c1a33 PB |
4550 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4551 | struct kvm_mmu *context, | |
4552 | int level) | |
6aa8b732 | 4553 | { |
2d48a985 | 4554 | context->nx = is_nx(vcpu); |
4d6931c3 | 4555 | context->root_level = level; |
2d48a985 | 4556 | |
4d6931c3 | 4557 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4558 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4559 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4560 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4561 | |
fa4a2c08 | 4562 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4563 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4564 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4565 | context->sync_page = paging64_sync_page; |
a7052897 | 4566 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4567 | context->update_pte = paging64_update_pte; |
17ac10ad | 4568 | context->shadow_root_level = level; |
c5a78f2b | 4569 | context->direct_map = false; |
6aa8b732 AK |
4570 | } |
4571 | ||
8a3c1a33 PB |
4572 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4573 | struct kvm_mmu *context) | |
17ac10ad | 4574 | { |
855feb67 YZ |
4575 | int root_level = is_la57_mode(vcpu) ? |
4576 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4577 | ||
4578 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4579 | } |
4580 | ||
8a3c1a33 PB |
4581 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4582 | struct kvm_mmu *context) | |
6aa8b732 | 4583 | { |
2d48a985 | 4584 | context->nx = false; |
4d6931c3 | 4585 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4586 | |
4d6931c3 | 4587 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4588 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4589 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4590 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4591 | |
6aa8b732 | 4592 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4593 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4594 | context->sync_page = paging32_sync_page; |
a7052897 | 4595 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4596 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4597 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4598 | context->direct_map = false; |
6aa8b732 AK |
4599 | } |
4600 | ||
8a3c1a33 PB |
4601 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4602 | struct kvm_mmu *context) | |
6aa8b732 | 4603 | { |
8a3c1a33 | 4604 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4605 | } |
4606 | ||
9fa72119 JS |
4607 | static union kvm_mmu_page_role |
4608 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu) | |
4609 | { | |
4610 | union kvm_mmu_page_role role = {0}; | |
4611 | ||
4612 | role.guest_mode = is_guest_mode(vcpu); | |
4613 | role.smm = is_smm(vcpu); | |
4614 | role.ad_disabled = (shadow_accessed_mask == 0); | |
4615 | role.level = kvm_x86_ops->get_tdp_level(vcpu); | |
4616 | role.direct = true; | |
4617 | role.access = ACC_ALL; | |
4618 | ||
4619 | return role; | |
4620 | } | |
4621 | ||
8a3c1a33 | 4622 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4623 | { |
ad896af0 | 4624 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4625 | |
9fa72119 JS |
4626 | context->base_role.word = mmu_base_role_mask.word & |
4627 | kvm_calc_tdp_mmu_root_page_role(vcpu).word; | |
fb72d167 | 4628 | context->page_fault = tdp_page_fault; |
e8bc217a | 4629 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4630 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4631 | context->update_pte = nonpaging_update_pte; |
855feb67 | 4632 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu); |
c5a78f2b | 4633 | context->direct_map = true; |
1c97f0a0 | 4634 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4635 | context->get_cr3 = get_cr3; |
e4e517b4 | 4636 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4637 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4638 | |
4639 | if (!is_paging(vcpu)) { | |
2d48a985 | 4640 | context->nx = false; |
fb72d167 JR |
4641 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4642 | context->root_level = 0; | |
4643 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4644 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4645 | context->root_level = is_la57_mode(vcpu) ? |
4646 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4647 | reset_rsvds_bits_mask(vcpu, context); |
4648 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4649 | } else if (is_pae(vcpu)) { |
2d48a985 | 4650 | context->nx = is_nx(vcpu); |
fb72d167 | 4651 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4652 | reset_rsvds_bits_mask(vcpu, context); |
4653 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4654 | } else { |
2d48a985 | 4655 | context->nx = false; |
fb72d167 | 4656 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4657 | reset_rsvds_bits_mask(vcpu, context); |
4658 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4659 | } |
4660 | ||
25d92081 | 4661 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4662 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4663 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4664 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4665 | } |
4666 | ||
9fa72119 JS |
4667 | static union kvm_mmu_page_role |
4668 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4669 | { |
9fa72119 | 4670 | union kvm_mmu_page_role role = {0}; |
411c588d | 4671 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4672 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
9fa72119 JS |
4673 | |
4674 | role.nxe = is_nx(vcpu); | |
4675 | role.cr4_pae = !!is_pae(vcpu); | |
4676 | role.cr0_wp = is_write_protection(vcpu); | |
4677 | role.smep_andnot_wp = smep && !is_write_protection(vcpu); | |
4678 | role.smap_andnot_wp = smap && !is_write_protection(vcpu); | |
4679 | role.guest_mode = is_guest_mode(vcpu); | |
4680 | role.smm = is_smm(vcpu); | |
4681 | role.direct = !is_paging(vcpu); | |
4682 | role.access = ACC_ALL; | |
4683 | ||
4684 | if (!is_long_mode(vcpu)) | |
4685 | role.level = PT32E_ROOT_LEVEL; | |
4686 | else if (is_la57_mode(vcpu)) | |
4687 | role.level = PT64_ROOT_5LEVEL; | |
4688 | else | |
4689 | role.level = PT64_ROOT_4LEVEL; | |
4690 | ||
4691 | return role; | |
4692 | } | |
4693 | ||
4694 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) | |
4695 | { | |
ad896af0 PB |
4696 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4697 | ||
6aa8b732 | 4698 | if (!is_paging(vcpu)) |
8a3c1a33 | 4699 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4700 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4701 | paging64_init_context(vcpu, context); |
6aa8b732 | 4702 | else if (is_pae(vcpu)) |
8a3c1a33 | 4703 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4704 | else |
8a3c1a33 | 4705 | paging32_init_context(vcpu, context); |
a770f6f2 | 4706 | |
9fa72119 JS |
4707 | context->base_role.word = mmu_base_role_mask.word & |
4708 | kvm_calc_shadow_mmu_root_page_role(vcpu).word; | |
c258b62b | 4709 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4710 | } |
4711 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4712 | ||
9fa72119 JS |
4713 | static union kvm_mmu_page_role |
4714 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty) | |
4715 | { | |
4716 | union kvm_mmu_page_role role = vcpu->arch.mmu.base_role; | |
4717 | ||
4718 | role.level = PT64_ROOT_4LEVEL; | |
4719 | role.direct = false; | |
4720 | role.ad_disabled = !accessed_dirty; | |
4721 | role.guest_mode = true; | |
4722 | role.access = ACC_ALL; | |
4723 | ||
4724 | return role; | |
4725 | } | |
4726 | ||
ae1e2d10 PB |
4727 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
4728 | bool accessed_dirty) | |
155a97a3 | 4729 | { |
ad896af0 | 4730 | struct kvm_mmu *context = &vcpu->arch.mmu; |
9fa72119 JS |
4731 | union kvm_mmu_page_role root_page_role = |
4732 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty); | |
ad896af0 | 4733 | |
855feb67 | 4734 | context->shadow_root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4735 | |
4736 | context->nx = true; | |
ae1e2d10 | 4737 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4738 | context->page_fault = ept_page_fault; |
4739 | context->gva_to_gpa = ept_gva_to_gpa; | |
4740 | context->sync_page = ept_sync_page; | |
4741 | context->invlpg = ept_invlpg; | |
4742 | context->update_pte = ept_update_pte; | |
855feb67 | 4743 | context->root_level = PT64_ROOT_4LEVEL; |
155a97a3 | 4744 | context->direct_map = false; |
9fa72119 | 4745 | context->base_role.word = root_page_role.word & mmu_base_role_mask.word; |
155a97a3 | 4746 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4747 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4748 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4749 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4750 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4751 | } |
4752 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4753 | ||
8a3c1a33 | 4754 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4755 | { |
ad896af0 PB |
4756 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4757 | ||
4758 | kvm_init_shadow_mmu(vcpu); | |
4759 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4760 | context->get_cr3 = get_cr3; | |
4761 | context->get_pdptr = kvm_pdptr_read; | |
4762 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4763 | } |
4764 | ||
8a3c1a33 | 4765 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4766 | { |
4767 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4768 | ||
4769 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4770 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4771 | g_context->inject_page_fault = kvm_inject_page_fault; |
4772 | ||
4773 | /* | |
0af2593b DM |
4774 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4775 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4776 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4777 | * L2's page tables as the first level of translation and L1's | |
4778 | * nested page tables as the second level of translation. Basically | |
4779 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4780 | */ |
4781 | if (!is_paging(vcpu)) { | |
2d48a985 | 4782 | g_context->nx = false; |
02f59dc9 JR |
4783 | g_context->root_level = 0; |
4784 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4785 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4786 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4787 | g_context->root_level = is_la57_mode(vcpu) ? |
4788 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4789 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4790 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4791 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4792 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4793 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4794 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4795 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4796 | } else { | |
2d48a985 | 4797 | g_context->nx = false; |
02f59dc9 | 4798 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4799 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4800 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4801 | } | |
4802 | ||
25d92081 | 4803 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4804 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4805 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4806 | } |
4807 | ||
1c53da3f | 4808 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 4809 | { |
1c53da3f JS |
4810 | if (reset_roots) { |
4811 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4812 | vcpu->arch.mmu.prev_root = KVM_MMU_ROOT_INFO_INVALID; | |
4813 | } | |
4814 | ||
02f59dc9 | 4815 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4816 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4817 | else if (tdp_enabled) |
e0c6db3e | 4818 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4819 | else |
e0c6db3e | 4820 | init_kvm_softmmu(vcpu); |
fb72d167 | 4821 | } |
1c53da3f | 4822 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4823 | |
9fa72119 JS |
4824 | static union kvm_mmu_page_role |
4825 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4826 | { | |
4827 | if (tdp_enabled) | |
4828 | return kvm_calc_tdp_mmu_root_page_role(vcpu); | |
4829 | else | |
4830 | return kvm_calc_shadow_mmu_root_page_role(vcpu); | |
4831 | } | |
4832 | ||
8a3c1a33 | 4833 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4834 | { |
95f93af4 | 4835 | kvm_mmu_unload(vcpu); |
1c53da3f | 4836 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 4837 | } |
8668a3c4 | 4838 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4839 | |
4840 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4841 | { |
714b93da AK |
4842 | int r; |
4843 | ||
e2dec939 | 4844 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4845 | if (r) |
4846 | goto out; | |
8986ecc0 | 4847 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4848 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4849 | if (r) |
4850 | goto out; | |
6e42782f | 4851 | kvm_mmu_load_cr3(vcpu); |
714b93da AK |
4852 | out: |
4853 | return r; | |
6aa8b732 | 4854 | } |
17c3ba9d AK |
4855 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4856 | ||
4857 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4858 | { | |
7c390d35 | 4859 | kvm_mmu_free_roots(vcpu, true); |
95f93af4 | 4860 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4861 | } |
4b16184c | 4862 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4863 | |
0028425f | 4864 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4865 | struct kvm_mmu_page *sp, u64 *spte, |
4866 | const void *new) | |
0028425f | 4867 | { |
30945387 | 4868 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4869 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4870 | return; | |
30945387 | 4871 | } |
0028425f | 4872 | |
4cee5764 | 4873 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4874 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4875 | } |
4876 | ||
79539cec AK |
4877 | static bool need_remote_flush(u64 old, u64 new) |
4878 | { | |
4879 | if (!is_shadow_present_pte(old)) | |
4880 | return false; | |
4881 | if (!is_shadow_present_pte(new)) | |
4882 | return true; | |
4883 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4884 | return true; | |
53166229 GN |
4885 | old ^= shadow_nx_mask; |
4886 | new ^= shadow_nx_mask; | |
79539cec AK |
4887 | return (old & ~new & PT64_PERM_MASK) != 0; |
4888 | } | |
4889 | ||
889e5cbc XG |
4890 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4891 | const u8 *new, int *bytes) | |
da4a00f0 | 4892 | { |
889e5cbc XG |
4893 | u64 gentry; |
4894 | int r; | |
72016f3a | 4895 | |
72016f3a AK |
4896 | /* |
4897 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4898 | * as the current vcpu paging mode since we update the sptes only |
4899 | * when they have the same mode. | |
72016f3a | 4900 | */ |
889e5cbc | 4901 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4902 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4903 | *gpa &= ~(gpa_t)7; |
4904 | *bytes = 8; | |
54bf36aa | 4905 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4906 | if (r) |
4907 | gentry = 0; | |
08e850c6 AK |
4908 | new = (const u8 *)&gentry; |
4909 | } | |
4910 | ||
889e5cbc | 4911 | switch (*bytes) { |
08e850c6 AK |
4912 | case 4: |
4913 | gentry = *(const u32 *)new; | |
4914 | break; | |
4915 | case 8: | |
4916 | gentry = *(const u64 *)new; | |
4917 | break; | |
4918 | default: | |
4919 | gentry = 0; | |
4920 | break; | |
72016f3a AK |
4921 | } |
4922 | ||
889e5cbc XG |
4923 | return gentry; |
4924 | } | |
4925 | ||
4926 | /* | |
4927 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4928 | * or we may be forking, in which case it is better to unmap the page. | |
4929 | */ | |
a138fe75 | 4930 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4931 | { |
a30f47cb XG |
4932 | /* |
4933 | * Skip write-flooding detected for the sp whose level is 1, because | |
4934 | * it can become unsync, then the guest page is not write-protected. | |
4935 | */ | |
f71fa31f | 4936 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4937 | return false; |
3246af0e | 4938 | |
e5691a81 XG |
4939 | atomic_inc(&sp->write_flooding_count); |
4940 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4941 | } |
4942 | ||
4943 | /* | |
4944 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4945 | * indicate a page is not used as a page table. | |
4946 | */ | |
4947 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4948 | int bytes) | |
4949 | { | |
4950 | unsigned offset, pte_size, misaligned; | |
4951 | ||
4952 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4953 | gpa, bytes, sp->role.word); | |
4954 | ||
4955 | offset = offset_in_page(gpa); | |
4956 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4957 | |
4958 | /* | |
4959 | * Sometimes, the OS only writes the last one bytes to update status | |
4960 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4961 | */ | |
4962 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4963 | return false; | |
4964 | ||
889e5cbc XG |
4965 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4966 | misaligned |= bytes < 4; | |
4967 | ||
4968 | return misaligned; | |
4969 | } | |
4970 | ||
4971 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4972 | { | |
4973 | unsigned page_offset, quadrant; | |
4974 | u64 *spte; | |
4975 | int level; | |
4976 | ||
4977 | page_offset = offset_in_page(gpa); | |
4978 | level = sp->role.level; | |
4979 | *nspte = 1; | |
4980 | if (!sp->role.cr4_pae) { | |
4981 | page_offset <<= 1; /* 32->64 */ | |
4982 | /* | |
4983 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4984 | * only 2MB. So we need to double the offset again | |
4985 | * and zap two pdes instead of one. | |
4986 | */ | |
4987 | if (level == PT32_ROOT_LEVEL) { | |
4988 | page_offset &= ~7; /* kill rounding error */ | |
4989 | page_offset <<= 1; | |
4990 | *nspte = 2; | |
4991 | } | |
4992 | quadrant = page_offset >> PAGE_SHIFT; | |
4993 | page_offset &= ~PAGE_MASK; | |
4994 | if (quadrant != sp->role.quadrant) | |
4995 | return NULL; | |
4996 | } | |
4997 | ||
4998 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4999 | return spte; | |
5000 | } | |
5001 | ||
13d268ca | 5002 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5003 | const u8 *new, int bytes, |
5004 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5005 | { |
5006 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5007 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5008 | LIST_HEAD(invalid_list); |
5009 | u64 entry, gentry, *spte; | |
5010 | int npte; | |
b8c67b7a | 5011 | bool remote_flush, local_flush; |
889e5cbc XG |
5012 | |
5013 | /* | |
5014 | * If we don't have indirect shadow pages, it means no page is | |
5015 | * write-protected, so we can exit simply. | |
5016 | */ | |
6aa7de05 | 5017 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5018 | return; |
5019 | ||
b8c67b7a | 5020 | remote_flush = local_flush = false; |
889e5cbc XG |
5021 | |
5022 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5023 | ||
5024 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
5025 | ||
5026 | /* | |
5027 | * No need to care whether allocation memory is successful | |
5028 | * or not since pte prefetch is skiped if it does not have | |
5029 | * enough objects in the cache. | |
5030 | */ | |
5031 | mmu_topup_memory_caches(vcpu); | |
5032 | ||
5033 | spin_lock(&vcpu->kvm->mmu_lock); | |
5034 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 5035 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5036 | |
b67bfe0d | 5037 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5038 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5039 | detect_write_flooding(sp)) { |
b8c67b7a | 5040 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5041 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5042 | continue; |
5043 | } | |
889e5cbc XG |
5044 | |
5045 | spte = get_written_sptes(sp, gpa, &npte); | |
5046 | if (!spte) | |
5047 | continue; | |
5048 | ||
0671a8e7 | 5049 | local_flush = true; |
ac1b714e | 5050 | while (npte--) { |
79539cec | 5051 | entry = *spte; |
38e3b2b2 | 5052 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
5053 | if (gentry && |
5054 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
9fa72119 | 5055 | & mmu_base_role_mask.word) && rmap_can_add(vcpu)) |
7c562522 | 5056 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5057 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5058 | remote_flush = true; |
ac1b714e | 5059 | ++spte; |
9b7a0325 | 5060 | } |
9b7a0325 | 5061 | } |
b8c67b7a | 5062 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5063 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5064 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5065 | } |
5066 | ||
a436036b AK |
5067 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5068 | { | |
10589a46 MT |
5069 | gpa_t gpa; |
5070 | int r; | |
a436036b | 5071 | |
c5a78f2b | 5072 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
5073 | return 0; |
5074 | ||
1871c602 | 5075 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5076 | |
10589a46 | 5077 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5078 | |
10589a46 | 5079 | return r; |
a436036b | 5080 | } |
577bdc49 | 5081 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5082 | |
26eeb53c | 5083 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 5084 | { |
d98ba053 | 5085 | LIST_HEAD(invalid_list); |
103ad25a | 5086 | |
81f4f76b | 5087 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 5088 | return 0; |
81f4f76b | 5089 | |
5da59607 TY |
5090 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
5091 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
5092 | break; | |
ebeace86 | 5093 | |
4cee5764 | 5094 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 5095 | } |
aa6bd187 | 5096 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
5097 | |
5098 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
5099 | return -ENOSPC; | |
5100 | return 0; | |
ebeace86 | 5101 | } |
ebeace86 | 5102 | |
14727754 | 5103 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 5104 | void *insn, int insn_len) |
3067714c | 5105 | { |
1cb3f3ae | 5106 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 5107 | enum emulation_result er; |
9034e6e8 | 5108 | bool direct = vcpu->arch.mmu.direct_map; |
3067714c | 5109 | |
618232e2 BS |
5110 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
5111 | if (vcpu->arch.mmu.direct_map) { | |
5112 | vcpu->arch.gpa_available = true; | |
5113 | vcpu->arch.gpa_val = cr2; | |
5114 | } | |
3067714c | 5115 | |
9b8ebbdb | 5116 | r = RET_PF_INVALID; |
e9ee956e TY |
5117 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
5118 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
9b8ebbdb | 5119 | if (r == RET_PF_EMULATE) { |
e9ee956e TY |
5120 | emulation_type = 0; |
5121 | goto emulate; | |
5122 | } | |
e9ee956e | 5123 | } |
3067714c | 5124 | |
9b8ebbdb PB |
5125 | if (r == RET_PF_INVALID) { |
5126 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code), | |
5127 | false); | |
5128 | WARN_ON(r == RET_PF_INVALID); | |
5129 | } | |
5130 | ||
5131 | if (r == RET_PF_RETRY) | |
5132 | return 1; | |
3067714c | 5133 | if (r < 0) |
e9ee956e | 5134 | return r; |
3067714c | 5135 | |
14727754 TL |
5136 | /* |
5137 | * Before emulating the instruction, check if the error code | |
5138 | * was due to a RO violation while translating the guest page. | |
5139 | * This can occur when using nested virtualization with nested | |
5140 | * paging in both guests. If true, we simply unprotect the page | |
5141 | * and resume the guest. | |
14727754 | 5142 | */ |
64531a3b | 5143 | if (vcpu->arch.mmu.direct_map && |
eebed243 | 5144 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
5145 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
5146 | return 1; | |
5147 | } | |
5148 | ||
ded58749 | 5149 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 5150 | emulation_type = 0; |
e9ee956e | 5151 | emulate: |
00b10fe1 BS |
5152 | /* |
5153 | * On AMD platforms, under certain conditions insn_len may be zero on #NPF. | |
5154 | * This can happen if a guest gets a page-fault on data access but the HW | |
5155 | * table walker is not able to read the instruction page (e.g instruction | |
5156 | * page is not present in memory). In those cases we simply restart the | |
5157 | * guest. | |
5158 | */ | |
5159 | if (unlikely(insn && !insn_len)) | |
5160 | return 1; | |
5161 | ||
1cb3f3ae | 5162 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
5163 | |
5164 | switch (er) { | |
5165 | case EMULATE_DONE: | |
5166 | return 1; | |
ac0a48c3 | 5167 | case EMULATE_USER_EXIT: |
3067714c | 5168 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 5169 | /* fall through */ |
3067714c | 5170 | case EMULATE_FAIL: |
3f5d18a9 | 5171 | return 0; |
3067714c AK |
5172 | default: |
5173 | BUG(); | |
5174 | } | |
3067714c AK |
5175 | } |
5176 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5177 | ||
a7052897 MT |
5178 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5179 | { | |
a7052897 | 5180 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 5181 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
5182 | ++vcpu->stat.invlpg; |
5183 | } | |
5184 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5185 | ||
18552672 JR |
5186 | void kvm_enable_tdp(void) |
5187 | { | |
5188 | tdp_enabled = true; | |
5189 | } | |
5190 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
5191 | ||
5f4cb662 JR |
5192 | void kvm_disable_tdp(void) |
5193 | { | |
5194 | tdp_enabled = false; | |
5195 | } | |
5196 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
5197 | ||
6aa8b732 AK |
5198 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
5199 | { | |
ad312c7c | 5200 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
87ca74ad | 5201 | free_page((unsigned long)vcpu->arch.mmu.lm_root); |
6aa8b732 AK |
5202 | } |
5203 | ||
5204 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
5205 | { | |
17ac10ad | 5206 | struct page *page; |
6aa8b732 AK |
5207 | int i; |
5208 | ||
17ac10ad AK |
5209 | /* |
5210 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
5211 | * Therefore we need to allocate shadow page tables in the first | |
5212 | * 4GB of memory, which happens to fit the DMA32 zone. | |
5213 | */ | |
5214 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
5215 | if (!page) | |
d7fa6ab2 WY |
5216 | return -ENOMEM; |
5217 | ||
ad312c7c | 5218 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 5219 | for (i = 0; i < 4; ++i) |
ad312c7c | 5220 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 5221 | |
6aa8b732 | 5222 | return 0; |
6aa8b732 AK |
5223 | } |
5224 | ||
8018c27b | 5225 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5226 | { |
e459e322 XG |
5227 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
5228 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
7c390d35 | 5229 | vcpu->arch.mmu.prev_root = KVM_MMU_ROOT_INFO_INVALID; |
e459e322 XG |
5230 | vcpu->arch.mmu.translate_gpa = translate_gpa; |
5231 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 5232 | |
8018c27b IM |
5233 | return alloc_mmu_pages(vcpu); |
5234 | } | |
6aa8b732 | 5235 | |
8a3c1a33 | 5236 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 5237 | { |
fa4a2c08 | 5238 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 5239 | |
1c53da3f | 5240 | kvm_init_mmu(vcpu, true); |
6aa8b732 AK |
5241 | } |
5242 | ||
b5f5fdca | 5243 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5244 | struct kvm_memory_slot *slot, |
5245 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
5246 | { |
5247 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
5248 | } | |
5249 | ||
13d268ca XG |
5250 | void kvm_mmu_init_vm(struct kvm *kvm) |
5251 | { | |
5252 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5253 | ||
5254 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 5255 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
5256 | kvm_page_track_register_notifier(kvm, node); |
5257 | } | |
5258 | ||
5259 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
5260 | { | |
5261 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5262 | ||
5263 | kvm_page_track_unregister_notifier(kvm, node); | |
5264 | } | |
5265 | ||
1bad2b2a | 5266 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 5267 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
5268 | |
5269 | /* The caller should hold mmu-lock before calling this function. */ | |
928a4c39 | 5270 | static __always_inline bool |
1bad2b2a XG |
5271 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5272 | slot_level_handler fn, int start_level, int end_level, | |
5273 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5274 | { | |
5275 | struct slot_rmap_walk_iterator iterator; | |
5276 | bool flush = false; | |
5277 | ||
5278 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5279 | end_gfn, &iterator) { | |
5280 | if (iterator.rmap) | |
5281 | flush |= fn(kvm, iterator.rmap); | |
5282 | ||
5283 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5284 | if (flush && lock_flush_tlb) { | |
5285 | kvm_flush_remote_tlbs(kvm); | |
5286 | flush = false; | |
5287 | } | |
5288 | cond_resched_lock(&kvm->mmu_lock); | |
5289 | } | |
5290 | } | |
5291 | ||
5292 | if (flush && lock_flush_tlb) { | |
5293 | kvm_flush_remote_tlbs(kvm); | |
5294 | flush = false; | |
5295 | } | |
5296 | ||
5297 | return flush; | |
5298 | } | |
5299 | ||
928a4c39 | 5300 | static __always_inline bool |
1bad2b2a XG |
5301 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5302 | slot_level_handler fn, int start_level, int end_level, | |
5303 | bool lock_flush_tlb) | |
5304 | { | |
5305 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5306 | end_level, memslot->base_gfn, | |
5307 | memslot->base_gfn + memslot->npages - 1, | |
5308 | lock_flush_tlb); | |
5309 | } | |
5310 | ||
928a4c39 | 5311 | static __always_inline bool |
1bad2b2a XG |
5312 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5313 | slot_level_handler fn, bool lock_flush_tlb) | |
5314 | { | |
5315 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5316 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5317 | } | |
5318 | ||
928a4c39 | 5319 | static __always_inline bool |
1bad2b2a XG |
5320 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5321 | slot_level_handler fn, bool lock_flush_tlb) | |
5322 | { | |
5323 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5324 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5325 | } | |
5326 | ||
928a4c39 | 5327 | static __always_inline bool |
1bad2b2a XG |
5328 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5329 | slot_level_handler fn, bool lock_flush_tlb) | |
5330 | { | |
5331 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5332 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5333 | } | |
5334 | ||
efdfe536 XG |
5335 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5336 | { | |
5337 | struct kvm_memslots *slots; | |
5338 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5339 | int i; |
efdfe536 XG |
5340 | |
5341 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5342 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5343 | slots = __kvm_memslots(kvm, i); | |
5344 | kvm_for_each_memslot(memslot, slots) { | |
5345 | gfn_t start, end; | |
5346 | ||
5347 | start = max(gfn_start, memslot->base_gfn); | |
5348 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5349 | if (start >= end) | |
5350 | continue; | |
efdfe536 | 5351 | |
9da0e4d5 PB |
5352 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5353 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5354 | start, end - 1, true); | |
5355 | } | |
efdfe536 XG |
5356 | } |
5357 | ||
5358 | spin_unlock(&kvm->mmu_lock); | |
5359 | } | |
5360 | ||
018aabb5 TY |
5361 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5362 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5363 | { |
018aabb5 | 5364 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5365 | } |
5366 | ||
1c91cad4 KH |
5367 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5368 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5369 | { |
d77aa73c | 5370 | bool flush; |
6aa8b732 | 5371 | |
9d1beefb | 5372 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5373 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5374 | false); | |
9d1beefb | 5375 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5376 | |
5377 | /* | |
5378 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5379 | * which do tlb flush out of mmu-lock should be serialized by | |
5380 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5381 | */ | |
5382 | lockdep_assert_held(&kvm->slots_lock); | |
5383 | ||
5384 | /* | |
5385 | * We can flush all the TLBs out of the mmu lock without TLB | |
5386 | * corruption since we just change the spte from writable to | |
5387 | * readonly so that we only need to care the case of changing | |
5388 | * spte from present to present (changing the spte from present | |
5389 | * to nonpresent will flush all the TLBs immediately), in other | |
5390 | * words, the only case we care is mmu_spte_update() where we | |
5391 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
5392 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
5393 | * on PT_WRITABLE_MASK anymore. | |
5394 | */ | |
d91ffee9 KH |
5395 | if (flush) |
5396 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 5397 | } |
37a7d8b0 | 5398 | |
3ea3b7fa | 5399 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5400 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5401 | { |
5402 | u64 *sptep; | |
5403 | struct rmap_iterator iter; | |
5404 | int need_tlb_flush = 0; | |
ba049e93 | 5405 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5406 | struct kvm_mmu_page *sp; |
5407 | ||
0d536790 | 5408 | restart: |
018aabb5 | 5409 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5410 | sp = page_header(__pa(sptep)); |
5411 | pfn = spte_to_pfn(*sptep); | |
5412 | ||
5413 | /* | |
decf6333 XG |
5414 | * We cannot do huge page mapping for indirect shadow pages, |
5415 | * which are found on the last rmap (level = 1) when not using | |
5416 | * tdp; such shadow pages are synced with the page table in | |
5417 | * the guest, and the guest page table is using 4K page size | |
5418 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5419 | */ |
5420 | if (sp->role.direct && | |
5421 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5422 | PageTransCompoundMap(pfn_to_page(pfn))) { |
3ea3b7fa | 5423 | drop_spte(kvm, sptep); |
3ea3b7fa | 5424 | need_tlb_flush = 1; |
0d536790 XG |
5425 | goto restart; |
5426 | } | |
3ea3b7fa WL |
5427 | } |
5428 | ||
5429 | return need_tlb_flush; | |
5430 | } | |
5431 | ||
5432 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5433 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5434 | { |
f36f3f28 | 5435 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5436 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5437 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5438 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5439 | spin_unlock(&kvm->mmu_lock); |
5440 | } | |
5441 | ||
f4b4b180 KH |
5442 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5443 | struct kvm_memory_slot *memslot) | |
5444 | { | |
d77aa73c | 5445 | bool flush; |
f4b4b180 KH |
5446 | |
5447 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5448 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5449 | spin_unlock(&kvm->mmu_lock); |
5450 | ||
5451 | lockdep_assert_held(&kvm->slots_lock); | |
5452 | ||
5453 | /* | |
5454 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5455 | * function is only used for dirty logging, in which case flushing TLB | |
5456 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5457 | * dirty_bitmap. | |
5458 | */ | |
5459 | if (flush) | |
5460 | kvm_flush_remote_tlbs(kvm); | |
5461 | } | |
5462 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5463 | ||
5464 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5465 | struct kvm_memory_slot *memslot) | |
5466 | { | |
d77aa73c | 5467 | bool flush; |
f4b4b180 KH |
5468 | |
5469 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5470 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5471 | false); | |
f4b4b180 KH |
5472 | spin_unlock(&kvm->mmu_lock); |
5473 | ||
5474 | /* see kvm_mmu_slot_remove_write_access */ | |
5475 | lockdep_assert_held(&kvm->slots_lock); | |
5476 | ||
5477 | if (flush) | |
5478 | kvm_flush_remote_tlbs(kvm); | |
5479 | } | |
5480 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5481 | ||
5482 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5483 | struct kvm_memory_slot *memslot) | |
5484 | { | |
d77aa73c | 5485 | bool flush; |
f4b4b180 KH |
5486 | |
5487 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5488 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5489 | spin_unlock(&kvm->mmu_lock); |
5490 | ||
5491 | lockdep_assert_held(&kvm->slots_lock); | |
5492 | ||
5493 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5494 | if (flush) | |
5495 | kvm_flush_remote_tlbs(kvm); | |
5496 | } | |
5497 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5498 | ||
e7d11c7a | 5499 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5500 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5501 | { | |
5502 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5503 | int batch = 0; |
5304b8d3 XG |
5504 | |
5505 | restart: | |
5506 | list_for_each_entry_safe_reverse(sp, node, | |
5507 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5508 | int ret; |
5509 | ||
5304b8d3 XG |
5510 | /* |
5511 | * No obsolete page exists before new created page since | |
5512 | * active_mmu_pages is the FIFO list. | |
5513 | */ | |
5514 | if (!is_obsolete_sp(kvm, sp)) | |
5515 | break; | |
5516 | ||
5517 | /* | |
5304b8d3 XG |
5518 | * Since we are reversely walking the list and the invalid |
5519 | * list will be moved to the head, skip the invalid page | |
5520 | * can help us to avoid the infinity list walking. | |
5521 | */ | |
5522 | if (sp->role.invalid) | |
5523 | continue; | |
5524 | ||
f34d251d XG |
5525 | /* |
5526 | * Need not flush tlb since we only zap the sp with invalid | |
5527 | * generation number. | |
5528 | */ | |
e7d11c7a | 5529 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5530 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5531 | batch = 0; |
5304b8d3 XG |
5532 | goto restart; |
5533 | } | |
5534 | ||
365c8868 XG |
5535 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5536 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5537 | batch += ret; |
5538 | ||
5539 | if (ret) | |
5304b8d3 XG |
5540 | goto restart; |
5541 | } | |
5542 | ||
f34d251d XG |
5543 | /* |
5544 | * Should flush tlb before free page tables since lockless-walking | |
5545 | * may use the pages. | |
5546 | */ | |
365c8868 | 5547 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5548 | } |
5549 | ||
5550 | /* | |
5551 | * Fast invalidate all shadow pages and use lock-break technique | |
5552 | * to zap obsolete pages. | |
5553 | * | |
5554 | * It's required when memslot is being deleted or VM is being | |
5555 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5556 | * not use any resource of the being-deleted slot or all slots | |
5557 | * after calling the function. | |
5558 | */ | |
5559 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5560 | { | |
5561 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5562 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5563 | kvm->arch.mmu_valid_gen++; |
5564 | ||
f34d251d XG |
5565 | /* |
5566 | * Notify all vcpus to reload its shadow page table | |
5567 | * and flush TLB. Then all vcpus will switch to new | |
5568 | * shadow page table with the new mmu_valid_gen. | |
5569 | * | |
5570 | * Note: we should do this under the protection of | |
5571 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5572 | * but miss tlb flush. | |
5573 | */ | |
5574 | kvm_reload_remote_mmus(kvm); | |
5575 | ||
5304b8d3 XG |
5576 | kvm_zap_obsolete_pages(kvm); |
5577 | spin_unlock(&kvm->mmu_lock); | |
5578 | } | |
5579 | ||
365c8868 XG |
5580 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5581 | { | |
5582 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5583 | } | |
5584 | ||
54bf36aa | 5585 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5586 | { |
5587 | /* | |
5588 | * The very rare case: if the generation-number is round, | |
5589 | * zap all shadow pages. | |
f8f55942 | 5590 | */ |
54bf36aa | 5591 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5592 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5593 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5594 | } |
f8f55942 XG |
5595 | } |
5596 | ||
70534a73 DC |
5597 | static unsigned long |
5598 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5599 | { |
5600 | struct kvm *kvm; | |
1495f230 | 5601 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5602 | unsigned long freed = 0; |
3ee16c81 | 5603 | |
2f303b74 | 5604 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5605 | |
5606 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5607 | int idx; |
d98ba053 | 5608 | LIST_HEAD(invalid_list); |
3ee16c81 | 5609 | |
35f2d16b TY |
5610 | /* |
5611 | * Never scan more than sc->nr_to_scan VM instances. | |
5612 | * Will not hit this condition practically since we do not try | |
5613 | * to shrink more than one VM and it is very unlikely to see | |
5614 | * !n_used_mmu_pages so many times. | |
5615 | */ | |
5616 | if (!nr_to_scan--) | |
5617 | break; | |
19526396 GN |
5618 | /* |
5619 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5620 | * here. We may skip a VM instance errorneosly, but we do not | |
5621 | * want to shrink a VM that only started to populate its MMU | |
5622 | * anyway. | |
5623 | */ | |
365c8868 XG |
5624 | if (!kvm->arch.n_used_mmu_pages && |
5625 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5626 | continue; |
19526396 | 5627 | |
f656ce01 | 5628 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5629 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5630 | |
365c8868 XG |
5631 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5632 | kvm_mmu_commit_zap_page(kvm, | |
5633 | &kvm->arch.zapped_obsolete_pages); | |
5634 | goto unlock; | |
5635 | } | |
5636 | ||
70534a73 DC |
5637 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5638 | freed++; | |
d98ba053 | 5639 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5640 | |
365c8868 | 5641 | unlock: |
3ee16c81 | 5642 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5643 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5644 | |
70534a73 DC |
5645 | /* |
5646 | * unfair on small ones | |
5647 | * per-vm shrinkers cry out | |
5648 | * sadness comes quickly | |
5649 | */ | |
19526396 GN |
5650 | list_move_tail(&kvm->vm_list, &vm_list); |
5651 | break; | |
3ee16c81 | 5652 | } |
3ee16c81 | 5653 | |
2f303b74 | 5654 | spin_unlock(&kvm_lock); |
70534a73 | 5655 | return freed; |
70534a73 DC |
5656 | } |
5657 | ||
5658 | static unsigned long | |
5659 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5660 | { | |
45221ab6 | 5661 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5662 | } |
5663 | ||
5664 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5665 | .count_objects = mmu_shrink_count, |
5666 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5667 | .seeks = DEFAULT_SEEKS * 10, |
5668 | }; | |
5669 | ||
2ddfd20e | 5670 | static void mmu_destroy_caches(void) |
b5a33a75 | 5671 | { |
c1bd743e TH |
5672 | kmem_cache_destroy(pte_list_desc_cache); |
5673 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5674 | } |
5675 | ||
5676 | int kvm_mmu_module_init(void) | |
5677 | { | |
ab271bd4 AB |
5678 | int ret = -ENOMEM; |
5679 | ||
f160c7b7 JS |
5680 | kvm_mmu_clear_all_pte_masks(); |
5681 | ||
53c07b18 XG |
5682 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5683 | sizeof(struct pte_list_desc), | |
46bea48a | 5684 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5685 | if (!pte_list_desc_cache) |
ab271bd4 | 5686 | goto out; |
b5a33a75 | 5687 | |
d3d25b04 AK |
5688 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5689 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5690 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5691 | if (!mmu_page_header_cache) |
ab271bd4 | 5692 | goto out; |
d3d25b04 | 5693 | |
908c7f19 | 5694 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5695 | goto out; |
45bf21a8 | 5696 | |
ab271bd4 AB |
5697 | ret = register_shrinker(&mmu_shrinker); |
5698 | if (ret) | |
5699 | goto out; | |
3ee16c81 | 5700 | |
b5a33a75 AK |
5701 | return 0; |
5702 | ||
ab271bd4 | 5703 | out: |
3ee16c81 | 5704 | mmu_destroy_caches(); |
ab271bd4 | 5705 | return ret; |
b5a33a75 AK |
5706 | } |
5707 | ||
3ad82a7e ZX |
5708 | /* |
5709 | * Caculate mmu pages needed for kvm. | |
5710 | */ | |
5711 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5712 | { | |
3ad82a7e ZX |
5713 | unsigned int nr_mmu_pages; |
5714 | unsigned int nr_pages = 0; | |
bc6678a3 | 5715 | struct kvm_memslots *slots; |
be6ba0f0 | 5716 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5717 | int i; |
3ad82a7e | 5718 | |
9da0e4d5 PB |
5719 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5720 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5721 | |
9da0e4d5 PB |
5722 | kvm_for_each_memslot(memslot, slots) |
5723 | nr_pages += memslot->npages; | |
5724 | } | |
3ad82a7e ZX |
5725 | |
5726 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5727 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5728 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5729 | |
5730 | return nr_mmu_pages; | |
5731 | } | |
5732 | ||
c42fffe3 XG |
5733 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5734 | { | |
95f93af4 | 5735 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5736 | free_mmu_pages(vcpu); |
5737 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5738 | } |
5739 | ||
b034cf01 XG |
5740 | void kvm_mmu_module_exit(void) |
5741 | { | |
5742 | mmu_destroy_caches(); | |
5743 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5744 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5745 | mmu_audit_disable(); |
5746 | } |