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KVM: MMU: split kvm_sync_page() function
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
bf998156 35#include <linux/uaccess.h>
6aa8b732 36
e495606d
AK		 37#include <asm/page.h>
38#include <asm/cmpxchg.h>
4e542370 39#include <asm/io.h>
13673a90 40#include <asm/vmx.h>
6aa8b732 41
18552672
JR		 42/*
43 * When setting this variable to true it enables Two-Dimensional-Paging
44 * where the hardware walks 2 page tables:
45 * 1. the guest-virtual to guest-physical
46 * 2. while doing 1. it walks guest-physical to host-physical
47 * If the hardware supports that we don't need to do shadow paging.
48 */
2f333bcb 49bool tdp_enabled = false;
18552672 50
37a7d8b0
AK		 51#undef MMU_DEBUG
52
53#undef AUDIT
54
55#ifdef AUDIT
56static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
57#else
58static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
59#endif
60
61#ifdef MMU_DEBUG
62
63#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
64#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
65
66#else
67
68#define pgprintk(x...) do { } while (0)
69#define rmap_printk(x...) do { } while (0)
70
71#endif
72
73#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 74static int dbg = 0;
75module_param(dbg, bool, 0644);
37a7d8b0 76#endif
6aa8b732 77
582801a9
MT		 78static int oos_shadow = 1;
79module_param(oos_shadow, bool, 0644);
80
d6c69ee9
YD		 81#ifndef MMU_DEBUG
82#define ASSERT(x) do { } while (0)
83#else
6aa8b732
AK		 84#define ASSERT(x) \
85 if (!(x)) { \
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
88 }
d6c69ee9 89#endif
6aa8b732 90
6aa8b732
AK		 91#define PT_FIRST_AVAIL_BITS_SHIFT 9
92#define PT64_SECOND_AVAIL_BITS_SHIFT 52
93
6aa8b732
AK		 94#define VALID_PAGE(x) ((x) != INVALID_PAGE)
95
96#define PT64_LEVEL_BITS 9
97
98#define PT64_LEVEL_SHIFT(level) \
d77c26fc 99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 100
101#define PT64_LEVEL_MASK(level) \
102 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
103
104#define PT64_INDEX(address, level)\
105 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
106
107
108#define PT32_LEVEL_BITS 10
109
110#define PT32_LEVEL_SHIFT(level) \
d77c26fc 111 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 112
113#define PT32_LEVEL_MASK(level) \
114 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 115#define PT32_LVL_OFFSET_MASK(level) \
116 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 118
119#define PT32_INDEX(address, level)\
120 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
121
122
27aba766 123#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 124#define PT64_DIR_BASE_ADDR_MASK \
125 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 126#define PT64_LVL_ADDR_MASK(level) \
127 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
128 * PT64_LEVEL_BITS))) - 1))
129#define PT64_LVL_OFFSET_MASK(level) \
130 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
131 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 132
133#define PT32_BASE_ADDR_MASK PAGE_MASK
134#define PT32_DIR_BASE_ADDR_MASK \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 136#define PT32_LVL_ADDR_MASK(level) \
137 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT32_LEVEL_BITS))) - 1))
6aa8b732 139
79539cec
AK		 140#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
141 | PT64_NX_MASK)
6aa8b732 142
cd4a4e53
AK		 143#define RMAP_EXT 4
144
fe135d2c
AK		 145#define ACC_EXEC_MASK 1
146#define ACC_WRITE_MASK PT_WRITABLE_MASK
147#define ACC_USER_MASK PT_USER_MASK
148#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
149
90bb6fc5
AK		 150#include <trace/events/kvm.h>
151
07420171
AK		 152#define CREATE_TRACE_POINTS
153#include "mmutrace.h"
154
1403283a
IE		 155#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
156
135f8c2b
AK		 157#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
158
cd4a4e53 159struct kvm_rmap_desc {
d555c333 160 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 161 struct kvm_rmap_desc *more;
162};
163
2d11123a
AK		 164struct kvm_shadow_walk_iterator {
165 u64 addr;
166 hpa_t shadow_addr;
167 int level;
168 u64 *sptep;
169 unsigned index;
170};
171
172#define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
176
6b18493d 177typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
ad8cfbe3 178
b5a33a75
AK		 179static struct kmem_cache *pte_chain_cache;
180static struct kmem_cache *rmap_desc_cache;
d3d25b04 181static struct kmem_cache *mmu_page_header_cache;
b5a33a75 182
c7addb90
AK		 183static u64 __read_mostly shadow_trap_nonpresent_pte;
184static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 185static u64 __read_mostly shadow_base_present_pte;
186static u64 __read_mostly shadow_nx_mask;
187static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
188static u64 __read_mostly shadow_user_mask;
189static u64 __read_mostly shadow_accessed_mask;
190static u64 __read_mostly shadow_dirty_mask;
c7addb90 191
82725b20
DE		 192static inline u64 rsvd_bits(int s, int e)
193{
194 return ((1ULL << (e - s + 1)) - 1) << s;
195}
196
c7addb90
AK		 197void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
198{
199 shadow_trap_nonpresent_pte = trap_pte;
200 shadow_notrap_nonpresent_pte = notrap_pte;
201}
202EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
203
7b52345e
SY		 204void kvm_mmu_set_base_ptes(u64 base_pte)
205{
206 shadow_base_present_pte = base_pte;
207}
208EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
209
210void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 211 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 212{
213 shadow_user_mask = user_mask;
214 shadow_accessed_mask = accessed_mask;
215 shadow_dirty_mask = dirty_mask;
216 shadow_nx_mask = nx_mask;
217 shadow_x_mask = x_mask;
218}
219EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
220
3dbe1415 221static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 222{
4d4ec087 223 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 224}
225
226static int is_cpuid_PSE36(void)
227{
228 return 1;
229}
230
73b1087e
AK		 231static int is_nx(struct kvm_vcpu *vcpu)
232{
f6801dff 233 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 234}
235
c7addb90
AK		 236static int is_shadow_present_pte(u64 pte)
237{
c7addb90
AK		 238 return pte != shadow_trap_nonpresent_pte
239 && pte != shadow_notrap_nonpresent_pte;
240}
241
05da4558
MT		 242static int is_large_pte(u64 pte)
243{
244 return pte & PT_PAGE_SIZE_MASK;
245}
246
8dae4445 247static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 248{
249 return pte & PT_WRITABLE_MASK;
250}
251
43a3795a 252static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 253{
439e218a 254 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 255}
256
43a3795a 257static int is_rmap_spte(u64 pte)
cd4a4e53 258{
4b1a80fa 259 return is_shadow_present_pte(pte);
cd4a4e53
AK		 260}
261
776e6633
MT		 262static int is_last_spte(u64 pte, int level)
263{
264 if (level == PT_PAGE_TABLE_LEVEL)
265 return 1;
852e3c19 266 if (is_large_pte(pte))
776e6633
MT		 267 return 1;
268 return 0;
269}
270
35149e21 271static pfn_t spte_to_pfn(u64 pte)
0b49ea86 272{
35149e21 273 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 274}
275
da928521
AK		 276static gfn_t pse36_gfn_delta(u32 gpte)
277{
278 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
279
280 return (gpte & PT32_DIR_PSE36_MASK) << shift;
281}
282
d555c333 283static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 284{
285#ifdef CONFIG_X86_64
286 set_64bit((unsigned long *)sptep, spte);
287#else
288 set_64bit((unsigned long long *)sptep, spte);
289#endif
290}
291
e2dec939 292static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 293 struct kmem_cache *base_cache, int min)
714b93da
AK		 294{
295 void *obj;
296
297 if (cache->nobjs >= min)
e2dec939 298 return 0;
714b93da 299 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 300 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 301 if (!obj)
e2dec939 302 return -ENOMEM;
714b93da
AK		 303 cache->objects[cache->nobjs++] = obj;
304 }
e2dec939 305 return 0;
714b93da
AK		 306}
307
e8ad9a70
XG		 308static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
309 struct kmem_cache *cache)
714b93da
AK		 310{
311 while (mc->nobjs)
e8ad9a70 312 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK		 313}
314
c1158e63 315static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 316 int min)
c1158e63
AK		 317{
318 struct page *page;
319
320 if (cache->nobjs >= min)
321 return 0;
322 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 323 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 324 if (!page)
325 return -ENOMEM;
c1158e63
AK		 326 cache->objects[cache->nobjs++] = page_address(page);
327 }
328 return 0;
329}
330
331static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
332{
333 while (mc->nobjs)
c4d198d5 334 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 335}
336
2e3e5882 337static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 338{
e2dec939
AK		 339 int r;
340
ad312c7c 341 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 342 pte_chain_cache, 4);
e2dec939
AK		 343 if (r)
344 goto out;
ad312c7c 345 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 346 rmap_desc_cache, 4);
d3d25b04
AK		 347 if (r)
348 goto out;
ad312c7c 349 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 350 if (r)
351 goto out;
ad312c7c 352 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 353 mmu_page_header_cache, 4);
e2dec939
AK		 354out:
355 return r;
714b93da
AK		 356}
357
358static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
359{
e8ad9a70
XG		 360 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
361 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
ad312c7c 362 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG		 363 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
364 mmu_page_header_cache);
714b93da
AK		 365}
366
367static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
368 size_t size)
369{
370 void *p;
371
372 BUG_ON(!mc->nobjs);
373 p = mc->objects[--mc->nobjs];
714b93da
AK		 374 return p;
375}
376
714b93da
AK		 377static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
378{
ad312c7c 379 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 380 sizeof(struct kvm_pte_chain));
381}
382
90cb0529 383static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 384{
e8ad9a70 385 kmem_cache_free(pte_chain_cache, pc);
714b93da
AK		 386}
387
388static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
389{
ad312c7c 390 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 391 sizeof(struct kvm_rmap_desc));
392}
393
90cb0529 394static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 395{
e8ad9a70 396 kmem_cache_free(rmap_desc_cache, rd);
714b93da
AK		 397}
398
05da4558
MT		 399/*
400 * Return the pointer to the largepage write count for a given
401 * gfn, handling slots that are not large page aligned.
402 */
d25797b2
JR		 403static int *slot_largepage_idx(gfn_t gfn,
404 struct kvm_memory_slot *slot,
405 int level)
05da4558
MT		 406{
407 unsigned long idx;
408
d25797b2
JR		 409 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
410 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
411 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 412}
413
414static void account_shadowed(struct kvm *kvm, gfn_t gfn)
415{
d25797b2 416 struct kvm_memory_slot *slot;
05da4558 417 int *write_count;
d25797b2 418 int i;
05da4558 419
2843099f 420 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 421
422 slot = gfn_to_memslot_unaliased(kvm, gfn);
423 for (i = PT_DIRECTORY_LEVEL;
424 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
425 write_count = slot_largepage_idx(gfn, slot, i);
426 *write_count += 1;
427 }
05da4558
MT		 428}
429
430static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
431{
d25797b2 432 struct kvm_memory_slot *slot;
05da4558 433 int *write_count;
d25797b2 434 int i;
05da4558 435
2843099f 436 gfn = unalias_gfn(kvm, gfn);
77a1a715 437 slot = gfn_to_memslot_unaliased(kvm, gfn);
d25797b2
JR		 438 for (i = PT_DIRECTORY_LEVEL;
439 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR		 440 write_count = slot_largepage_idx(gfn, slot, i);
441 *write_count -= 1;
442 WARN_ON(*write_count < 0);
443 }
05da4558
MT		 444}
445
d25797b2
JR		 446static int has_wrprotected_page(struct kvm *kvm,
447 gfn_t gfn,
448 int level)
05da4558 449{
2843099f 450 struct kvm_memory_slot *slot;
05da4558
MT		 451 int *largepage_idx;
452
2843099f
IE		 453 gfn = unalias_gfn(kvm, gfn);
454 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 455 if (slot) {
d25797b2 456 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 457 return *largepage_idx;
458 }
459
460 return 1;
461}
462
d25797b2 463static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 464{
8f0b1ab6 465 unsigned long page_size;
d25797b2 466 int i, ret = 0;
05da4558 467
8f0b1ab6 468 page_size = kvm_host_page_size(kvm, gfn);
05da4558 469
d25797b2
JR		 470 for (i = PT_PAGE_TABLE_LEVEL;
471 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
472 if (page_size >= KVM_HPAGE_SIZE(i))
473 ret = i;
474 else
475 break;
476 }
477
4c2155ce 478 return ret;
05da4558
MT		 479}
480
d25797b2 481static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 482{
483 struct kvm_memory_slot *slot;
878403b7 484 int host_level, level, max_level;
05da4558
MT		 485
486 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
487 if (slot && slot->dirty_bitmap)
d25797b2 488 return PT_PAGE_TABLE_LEVEL;
05da4558 489
d25797b2
JR		 490 host_level = host_mapping_level(vcpu->kvm, large_gfn);
491
492 if (host_level == PT_PAGE_TABLE_LEVEL)
493 return host_level;
494
878403b7
SY		 495 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
496 kvm_x86_ops->get_lpage_level() : host_level;
497
498 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 499 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
500 break;
d25797b2
JR		 501
502 return level - 1;
05da4558
MT		 503}
504
290fc38d
IE		 505/*
506 * Take gfn and return the reverse mapping to it.
507 * Note: gfn must be unaliased before this function get called
508 */
509
44ad9944 510static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 511{
512 struct kvm_memory_slot *slot;
05da4558 513 unsigned long idx;
290fc38d
IE		 514
515 slot = gfn_to_memslot(kvm, gfn);
44ad9944 516 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 517 return &slot->rmap[gfn - slot->base_gfn];
518
44ad9944
JR		 519 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
520 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 521
44ad9944 522 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 523}
524
cd4a4e53
AK		 525/*
526 * Reverse mapping data structures:
527 *
290fc38d
IE		 528 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
529 * that points to page_address(page).
cd4a4e53 530 *
290fc38d
IE		 531 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
532 * containing more mappings.
53a27b39
MT		 533 *
534 * Returns the number of rmap entries before the spte was added or zero if
535 * the spte was not added.
536 *
cd4a4e53 537 */
44ad9944 538static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 539{
4db35314 540 struct kvm_mmu_page *sp;
cd4a4e53 541 struct kvm_rmap_desc *desc;
290fc38d 542 unsigned long *rmapp;
53a27b39 543 int i, count = 0;
cd4a4e53 544
43a3795a 545 if (!is_rmap_spte(*spte))
53a27b39 546 return count;
290fc38d 547 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 548 sp = page_header(__pa(spte));
549 sp->gfns[spte - sp->spt] = gfn;
44ad9944 550 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 551 if (!*rmapp) {
cd4a4e53 552 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 553 *rmapp = (unsigned long)spte;
554 } else if (!(*rmapp & 1)) {
cd4a4e53 555 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 556 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 557 desc->sptes[0] = (u64 *)*rmapp;
558 desc->sptes[1] = spte;
290fc38d 559 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 560 } else {
561 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 562 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 563 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 564 desc = desc->more;
53a27b39
MT		 565 count += RMAP_EXT;
566 }
d555c333 567 if (desc->sptes[RMAP_EXT-1]) {
714b93da 568 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 569 desc = desc->more;
570 }
d555c333 571 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 572 ;
d555c333 573 desc->sptes[i] = spte;
cd4a4e53 574 }
53a27b39 575 return count;
cd4a4e53
AK		 576}
577
290fc38d 578static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 579 struct kvm_rmap_desc *desc,
580 int i,
581 struct kvm_rmap_desc *prev_desc)
582{
583 int j;
584
d555c333 585 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 586 ;
d555c333
AK		 587 desc->sptes[i] = desc->sptes[j];
588 desc->sptes[j] = NULL;
cd4a4e53
AK		 589 if (j != 0)
590 return;
591 if (!prev_desc && !desc->more)
d555c333 592 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 593 else
594 if (prev_desc)
595 prev_desc->more = desc->more;
596 else
290fc38d 597 *rmapp = (unsigned long)desc->more | 1;
90cb0529 598 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 599}
600
290fc38d 601static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 602{
cd4a4e53
AK		 603 struct kvm_rmap_desc *desc;
604 struct kvm_rmap_desc *prev_desc;
4db35314 605 struct kvm_mmu_page *sp;
35149e21 606 pfn_t pfn;
290fc38d 607 unsigned long *rmapp;
cd4a4e53
AK		 608 int i;
609
43a3795a 610 if (!is_rmap_spte(*spte))
cd4a4e53 611 return;
4db35314 612 sp = page_header(__pa(spte));
35149e21 613 pfn = spte_to_pfn(*spte);
7b52345e 614 if (*spte & shadow_accessed_mask)
35149e21 615 kvm_set_pfn_accessed(pfn);
8dae4445 616 if (is_writable_pte(*spte))
acb66dd0 617 kvm_set_pfn_dirty(pfn);
44ad9944 618 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 619 if (!*rmapp) {
cd4a4e53
AK		 620 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
621 BUG();
290fc38d 622 } else if (!(*rmapp & 1)) {
cd4a4e53 623 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 624 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 625 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
626 spte, *spte);
627 BUG();
628 }
290fc38d 629 *rmapp = 0;
cd4a4e53
AK		 630 } else {
631 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 632 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 633 prev_desc = NULL;
634 while (desc) {
d555c333
AK		 635 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
636 if (desc->sptes[i] == spte) {
290fc38d 637 rmap_desc_remove_entry(rmapp,
714b93da 638 desc, i,
cd4a4e53
AK		 639 prev_desc);
640 return;
641 }
642 prev_desc = desc;
643 desc = desc->more;
644 }
186a3e52 645 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 646 BUG();
647 }
648}
649
98348e95 650static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 651{
374cbac0 652 struct kvm_rmap_desc *desc;
98348e95
IE		 653 u64 *prev_spte;
654 int i;
655
656 if (!*rmapp)
657 return NULL;
658 else if (!(*rmapp & 1)) {
659 if (!spte)
660 return (u64 *)*rmapp;
661 return NULL;
662 }
663 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE		 664 prev_spte = NULL;
665 while (desc) {
d555c333 666 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 667 if (prev_spte == spte)
d555c333
AK		 668 return desc->sptes[i];
669 prev_spte = desc->sptes[i];
98348e95
IE		 670 }
671 desc = desc->more;
672 }
673 return NULL;
674}
675
b1a36821 676static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 677{
290fc38d 678 unsigned long *rmapp;
374cbac0 679 u64 *spte;
44ad9944 680 int i, write_protected = 0;
374cbac0 681
4a4c9924 682 gfn = unalias_gfn(kvm, gfn);
44ad9944 683 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 684
98348e95
IE		 685 spte = rmap_next(kvm, rmapp, NULL);
686 while (spte) {
374cbac0 687 BUG_ON(!spte);
374cbac0 688 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 689 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 690 if (is_writable_pte(*spte)) {
d555c333 691 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 692 write_protected = 1;
693 }
9647c14c 694 spte = rmap_next(kvm, rmapp, spte);
374cbac0 695 }
855149aa 696 if (write_protected) {
35149e21 697 pfn_t pfn;
855149aa
IE		 698
699 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 700 pfn = spte_to_pfn(*spte);
701 kvm_set_pfn_dirty(pfn);
855149aa
IE		 702 }
703
05da4558 704 /* check for huge page mappings */
44ad9944
JR		 705 for (i = PT_DIRECTORY_LEVEL;
706 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
707 rmapp = gfn_to_rmap(kvm, gfn, i);
708 spte = rmap_next(kvm, rmapp, NULL);
709 while (spte) {
710 BUG_ON(!spte);
711 BUG_ON(!(*spte & PT_PRESENT_MASK));
712 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
713 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 714 if (is_writable_pte(*spte)) {
44ad9944
JR		 715 rmap_remove(kvm, spte);
716 --kvm->stat.lpages;
717 __set_spte(spte, shadow_trap_nonpresent_pte);
718 spte = NULL;
719 write_protected = 1;
720 }
721 spte = rmap_next(kvm, rmapp, spte);
05da4558 722 }
05da4558
MT		 723 }
724
b1a36821 725 return write_protected;
374cbac0
AK		 726}
727
8a8365c5
FD		 728static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
729 unsigned long data)
e930bffe
AA		 730{
731 u64 *spte;
732 int need_tlb_flush = 0;
733
734 while ((spte = rmap_next(kvm, rmapp, NULL))) {
735 BUG_ON(!(*spte & PT_PRESENT_MASK));
736 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
737 rmap_remove(kvm, spte);
d555c333 738 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 739 need_tlb_flush = 1;
740 }
741 return need_tlb_flush;
742}
743
8a8365c5
FD		 744static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
745 unsigned long data)
3da0dd43
IE		 746{
747 int need_flush = 0;
748 u64 *spte, new_spte;
749 pte_t *ptep = (pte_t *)data;
750 pfn_t new_pfn;
751
752 WARN_ON(pte_huge(*ptep));
753 new_pfn = pte_pfn(*ptep);
754 spte = rmap_next(kvm, rmapp, NULL);
755 while (spte) {
756 BUG_ON(!is_shadow_present_pte(*spte));
757 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
758 need_flush = 1;
759 if (pte_write(*ptep)) {
760 rmap_remove(kvm, spte);
761 __set_spte(spte, shadow_trap_nonpresent_pte);
762 spte = rmap_next(kvm, rmapp, NULL);
763 } else {
764 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
765 new_spte |= (u64)new_pfn << PAGE_SHIFT;
766
767 new_spte &= ~PT_WRITABLE_MASK;
768 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 769 if (is_writable_pte(*spte))
3da0dd43
IE		 770 kvm_set_pfn_dirty(spte_to_pfn(*spte));
771 __set_spte(spte, new_spte);
772 spte = rmap_next(kvm, rmapp, spte);
773 }
774 }
775 if (need_flush)
776 kvm_flush_remote_tlbs(kvm);
777
778 return 0;
779}
780
8a8365c5
FD		 781static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
782 unsigned long data,
3da0dd43 783 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 784 unsigned long data))
e930bffe 785{
852e3c19 786 int i, j;
90bb6fc5 787 int ret;
e930bffe 788 int retval = 0;
bc6678a3
MT		 789 struct kvm_memslots *slots;
790
90d83dc3 791 slots = kvm_memslots(kvm);
e930bffe 792
46a26bf5
MT		 793 for (i = 0; i < slots->nmemslots; i++) {
794 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 795 unsigned long start = memslot->userspace_addr;
796 unsigned long end;
797
e930bffe
AA		 798 end = start + (memslot->npages << PAGE_SHIFT);
799 if (hva >= start && hva < end) {
800 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 801
90bb6fc5 802 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 803
804 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
805 int idx = gfn_offset;
806 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 807 ret |= handler(kvm,
3da0dd43
IE		 808 &memslot->lpage_info[j][idx].rmap_pde,
809 data);
852e3c19 810 }
90bb6fc5
AK		 811 trace_kvm_age_page(hva, memslot, ret);
812 retval |= ret;
e930bffe
AA		 813 }
814 }
815
816 return retval;
817}
818
819int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
820{
3da0dd43
IE		 821 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
822}
823
824void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
825{
8a8365c5 826 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 827}
828
8a8365c5
FD		 829static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
830 unsigned long data)
e930bffe
AA		 831{
832 u64 *spte;
833 int young = 0;
834
6316e1c8
RR		 835 /*
836 * Emulate the accessed bit for EPT, by checking if this page has
837 * an EPT mapping, and clearing it if it does. On the next access,
838 * a new EPT mapping will be established.
839 * This has some overhead, but not as much as the cost of swapping
840 * out actively used pages or breaking up actively used hugepages.
841 */
534e38b4 842 if (!shadow_accessed_mask)
6316e1c8 843 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 844
e930bffe
AA		 845 spte = rmap_next(kvm, rmapp, NULL);
846 while (spte) {
847 int _young;
848 u64 _spte = *spte;
849 BUG_ON(!(_spte & PT_PRESENT_MASK));
850 _young = _spte & PT_ACCESSED_MASK;
851 if (_young) {
852 young = 1;
853 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
854 }
855 spte = rmap_next(kvm, rmapp, spte);
856 }
857 return young;
858}
859
53a27b39
MT		 860#define RMAP_RECYCLE_THRESHOLD 1000
861
852e3c19 862static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 863{
864 unsigned long *rmapp;
852e3c19
JR		 865 struct kvm_mmu_page *sp;
866
867 sp = page_header(__pa(spte));
53a27b39
MT		 868
869 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 870 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 871
3da0dd43 872 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 873 kvm_flush_remote_tlbs(vcpu->kvm);
874}
875
e930bffe
AA		 876int kvm_age_hva(struct kvm *kvm, unsigned long hva)
877{
3da0dd43 878 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 879}
880
d6c69ee9 881#ifdef MMU_DEBUG
47ad8e68 882static int is_empty_shadow_page(u64 *spt)
6aa8b732 883{
139bdb2d
AK		 884 u64 *pos;
885 u64 *end;
886
47ad8e68 887 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 888 if (is_shadow_present_pte(*pos)) {
b8688d51 889 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 890 pos, *pos);
6aa8b732 891 return 0;
139bdb2d 892 }
6aa8b732
AK		 893 return 1;
894}
d6c69ee9 895#endif
6aa8b732 896
4db35314 897static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 898{
4db35314
AK		 899 ASSERT(is_empty_shadow_page(sp->spt));
900 list_del(&sp->link);
901 __free_page(virt_to_page(sp->spt));
902 __free_page(virt_to_page(sp->gfns));
e8ad9a70 903 kmem_cache_free(mmu_page_header_cache, sp);
f05e70ac 904 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 905}
906
cea0f0e7
AK		 907static unsigned kvm_page_table_hashfn(gfn_t gfn)
908{
1ae0a13d 909 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 910}
911
25c0de2c
AK		 912static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
913 u64 *parent_pte)
6aa8b732 914{
4db35314 915 struct kvm_mmu_page *sp;
6aa8b732 916
ad312c7c
ZX		 917 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
918 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
919 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 920 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 921 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 922 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 923 sp->multimapped = 0;
924 sp->parent_pte = parent_pte;
f05e70ac 925 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 926 return sp;
6aa8b732
AK		 927}
928
714b93da 929static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 930 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 931{
932 struct kvm_pte_chain *pte_chain;
933 struct hlist_node *node;
934 int i;
935
936 if (!parent_pte)
937 return;
4db35314
AK		 938 if (!sp->multimapped) {
939 u64 *old = sp->parent_pte;
cea0f0e7
AK		 940
941 if (!old) {
4db35314 942 sp->parent_pte = parent_pte;
cea0f0e7
AK		 943 return;
944 }
4db35314 945 sp->multimapped = 1;
714b93da 946 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 947 INIT_HLIST_HEAD(&sp->parent_ptes);
948 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 949 pte_chain->parent_ptes[0] = old;
950 }
4db35314 951 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 952 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
953 continue;
954 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
955 if (!pte_chain->parent_ptes[i]) {
956 pte_chain->parent_ptes[i] = parent_pte;
957 return;
958 }
959 }
714b93da 960 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 961 BUG_ON(!pte_chain);
4db35314 962 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 963 pte_chain->parent_ptes[0] = parent_pte;
964}
965
4db35314 966static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 967 u64 *parent_pte)
968{
969 struct kvm_pte_chain *pte_chain;
970 struct hlist_node *node;
971 int i;
972
4db35314
AK		 973 if (!sp->multimapped) {
974 BUG_ON(sp->parent_pte != parent_pte);
975 sp->parent_pte = NULL;
cea0f0e7
AK		 976 return;
977 }
4db35314 978 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 979 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
980 if (!pte_chain->parent_ptes[i])
981 break;
982 if (pte_chain->parent_ptes[i] != parent_pte)
983 continue;
697fe2e2
AK		 984 while (i + 1 < NR_PTE_CHAIN_ENTRIES
985 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 986 pte_chain->parent_ptes[i]
987 = pte_chain->parent_ptes[i + 1];
988 ++i;
989 }
990 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 991 if (i == 0) {
992 hlist_del(&pte_chain->link);
90cb0529 993 mmu_free_pte_chain(pte_chain);
4db35314
AK		 994 if (hlist_empty(&sp->parent_ptes)) {
995 sp->multimapped = 0;
996 sp->parent_pte = NULL;
697fe2e2
AK		 997 }
998 }
cea0f0e7
AK		 999 return;
1000 }
1001 BUG();
1002}
1003
ad8cfbe3 1004
6b18493d 1005static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT		 1006{
1007 struct kvm_pte_chain *pte_chain;
1008 struct hlist_node *node;
1009 struct kvm_mmu_page *parent_sp;
1010 int i;
1011
1012 if (!sp->multimapped && sp->parent_pte) {
1013 parent_sp = page_header(__pa(sp->parent_pte));
6b18493d
XG		 1014 fn(parent_sp);
1015 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1016 return;
1017 }
1018 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1019 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1020 if (!pte_chain->parent_ptes[i])
1021 break;
1022 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
6b18493d
XG		 1023 fn(parent_sp);
1024 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1025 }
1026}
1027
0074ff63
MT		 1028static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1029{
1030 unsigned int index;
1031 struct kvm_mmu_page *sp = page_header(__pa(spte));
1032
1033 index = spte - sp->spt;
60c8aec6
MT		 1034 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1035 sp->unsync_children++;
1036 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1037}
1038
1039static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1040{
1041 struct kvm_pte_chain *pte_chain;
1042 struct hlist_node *node;
1043 int i;
1044
1045 if (!sp->parent_pte)
1046 return;
1047
1048 if (!sp->multimapped) {
1049 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1050 return;
1051 }
1052
1053 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1054 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1055 if (!pte_chain->parent_ptes[i])
1056 break;
1057 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1058 }
1059}
1060
6b18493d 1061static int unsync_walk_fn(struct kvm_mmu_page *sp)
0074ff63 1062{
0074ff63
MT		 1063 kvm_mmu_update_parents_unsync(sp);
1064 return 1;
1065}
1066
6b18493d 1067static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1068{
6b18493d 1069 mmu_parent_walk(sp, unsync_walk_fn);
0074ff63
MT		 1070 kvm_mmu_update_parents_unsync(sp);
1071}
1072
d761a501
AK		 1073static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1074 struct kvm_mmu_page *sp)
1075{
1076 int i;
1077
1078 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1079 sp->spt[i] = shadow_trap_nonpresent_pte;
1080}
1081
e8bc217a
MT		 1082static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1083 struct kvm_mmu_page *sp)
1084{
1085 return 1;
1086}
1087
a7052897
MT		 1088static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1089{
1090}
1091
60c8aec6
MT		 1092#define KVM_PAGE_ARRAY_NR 16
1093
1094struct kvm_mmu_pages {
1095 struct mmu_page_and_offset {
1096 struct kvm_mmu_page *sp;
1097 unsigned int idx;
1098 } page[KVM_PAGE_ARRAY_NR];
1099 unsigned int nr;
1100};
1101
0074ff63
MT		 1102#define for_each_unsync_children(bitmap, idx) \
1103 for (idx = find_first_bit(bitmap, 512); \
1104 idx < 512; \
1105 idx = find_next_bit(bitmap, 512, idx+1))
1106
cded19f3
HE		 1107static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1108 int idx)
4731d4c7 1109{
60c8aec6 1110 int i;
4731d4c7 1111
60c8aec6
MT		 1112 if (sp->unsync)
1113 for (i=0; i < pvec->nr; i++)
1114 if (pvec->page[i].sp == sp)
1115 return 0;
1116
1117 pvec->page[pvec->nr].sp = sp;
1118 pvec->page[pvec->nr].idx = idx;
1119 pvec->nr++;
1120 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1121}
1122
1123static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1124 struct kvm_mmu_pages *pvec)
1125{
1126 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1127
0074ff63 1128 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1129 u64 ent = sp->spt[i];
1130
87917239 1131 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1132 struct kvm_mmu_page *child;
1133 child = page_header(ent & PT64_BASE_ADDR_MASK);
1134
1135 if (child->unsync_children) {
60c8aec6
MT		 1136 if (mmu_pages_add(pvec, child, i))
1137 return -ENOSPC;
1138
1139 ret = __mmu_unsync_walk(child, pvec);
1140 if (!ret)
1141 __clear_bit(i, sp->unsync_child_bitmap);
1142 else if (ret > 0)
1143 nr_unsync_leaf += ret;
1144 else
4731d4c7
MT		 1145 return ret;
1146 }
1147
1148 if (child->unsync) {
60c8aec6
MT		 1149 nr_unsync_leaf++;
1150 if (mmu_pages_add(pvec, child, i))
1151 return -ENOSPC;
4731d4c7
MT		 1152 }
1153 }
1154 }
1155
0074ff63 1156 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1157 sp->unsync_children = 0;
1158
60c8aec6
MT		 1159 return nr_unsync_leaf;
1160}
1161
1162static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1163 struct kvm_mmu_pages *pvec)
1164{
1165 if (!sp->unsync_children)
1166 return 0;
1167
1168 mmu_pages_add(pvec, sp, 0);
1169 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1170}
1171
4db35314 1172static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1173{
1174 unsigned index;
1175 struct hlist_head *bucket;
4db35314 1176 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1177 struct hlist_node *node;
1178
b8688d51 1179 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1180 index = kvm_page_table_hashfn(gfn);
f05e70ac 1181 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1182 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1183 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1184 && !sp->role.invalid) {
cea0f0e7 1185 pgprintk("%s: found role %x\n",
b8688d51 1186 __func__, sp->role.word);
4db35314 1187 return sp;
cea0f0e7
AK		 1188 }
1189 return NULL;
1190}
1191
4731d4c7
MT		 1192static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1193{
1194 WARN_ON(!sp->unsync);
5e1b3ddb 1195 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1196 sp->unsync = 0;
1197 --kvm->stat.mmu_unsync;
1198}
1199
1200static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1201
1d9dc7e0
XG		 1202static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1203 bool clear_unsync)
4731d4c7 1204{
5b7e0102 1205 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT		 1206 kvm_mmu_zap_page(vcpu->kvm, sp);
1207 return 1;
1208 }
1209
1d9dc7e0
XG		 1210 if (clear_unsync) {
1211 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1212 kvm_flush_remote_tlbs(vcpu->kvm);
1213 kvm_unlink_unsync_page(vcpu->kvm, sp);
1214 }
1215
4731d4c7
MT		 1216 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1217 kvm_mmu_zap_page(vcpu->kvm, sp);
1218 return 1;
1219 }
1220
1221 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1222 return 0;
1223}
1224
1d9dc7e0
XG		 1225static void mmu_convert_notrap(struct kvm_mmu_page *sp);
1226static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1227 struct kvm_mmu_page *sp)
1228{
1229 int ret;
1230
1231 ret = __kvm_sync_page(vcpu, sp, false);
1232 if (!ret)
1233 mmu_convert_notrap(sp);
1234 return ret;
1235}
1236
1237static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1238{
1239 return __kvm_sync_page(vcpu, sp, true);
1240}
1241
60c8aec6
MT		 1242struct mmu_page_path {
1243 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1244 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1245};
1246
60c8aec6
MT		 1247#define for_each_sp(pvec, sp, parents, i) \
1248 for (i = mmu_pages_next(&pvec, &parents, -1), \
1249 sp = pvec.page[i].sp; \
1250 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1251 i = mmu_pages_next(&pvec, &parents, i))
1252
cded19f3
HE		 1253static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1254 struct mmu_page_path *parents,
1255 int i)
60c8aec6
MT		 1256{
1257 int n;
1258
1259 for (n = i+1; n < pvec->nr; n++) {
1260 struct kvm_mmu_page *sp = pvec->page[n].sp;
1261
1262 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1263 parents->idx[0] = pvec->page[n].idx;
1264 return n;
1265 }
1266
1267 parents->parent[sp->role.level-2] = sp;
1268 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1269 }
1270
1271 return n;
1272}
1273
cded19f3 1274static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1275{
60c8aec6
MT		 1276 struct kvm_mmu_page *sp;
1277 unsigned int level = 0;
1278
1279 do {
1280 unsigned int idx = parents->idx[level];
4731d4c7 1281
60c8aec6
MT		 1282 sp = parents->parent[level];
1283 if (!sp)
1284 return;
1285
1286 --sp->unsync_children;
1287 WARN_ON((int)sp->unsync_children < 0);
1288 __clear_bit(idx, sp->unsync_child_bitmap);
1289 level++;
1290 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1291}
1292
60c8aec6
MT		 1293static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1294 struct mmu_page_path *parents,
1295 struct kvm_mmu_pages *pvec)
4731d4c7 1296{
60c8aec6
MT		 1297 parents->parent[parent->role.level-1] = NULL;
1298 pvec->nr = 0;
1299}
4731d4c7 1300
60c8aec6
MT		 1301static void mmu_sync_children(struct kvm_vcpu *vcpu,
1302 struct kvm_mmu_page *parent)
1303{
1304 int i;
1305 struct kvm_mmu_page *sp;
1306 struct mmu_page_path parents;
1307 struct kvm_mmu_pages pages;
1308
1309 kvm_mmu_pages_init(parent, &parents, &pages);
1310 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1311 int protected = 0;
1312
1313 for_each_sp(pages, sp, parents, i)
1314 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1315
1316 if (protected)
1317 kvm_flush_remote_tlbs(vcpu->kvm);
1318
60c8aec6
MT		 1319 for_each_sp(pages, sp, parents, i) {
1320 kvm_sync_page(vcpu, sp);
1321 mmu_pages_clear_parents(&parents);
1322 }
4731d4c7 1323 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1324 kvm_mmu_pages_init(parent, &parents, &pages);
1325 }
4731d4c7
MT		 1326}
1327
cea0f0e7
AK		 1328static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1329 gfn_t gfn,
1330 gva_t gaddr,
1331 unsigned level,
f6e2c02b 1332 int direct,
41074d07 1333 unsigned access,
f7d9c7b7 1334 u64 *parent_pte)
cea0f0e7
AK		 1335{
1336 union kvm_mmu_page_role role;
1337 unsigned index;
1338 unsigned quadrant;
1339 struct hlist_head *bucket;
4db35314 1340 struct kvm_mmu_page *sp;
4731d4c7 1341 struct hlist_node *node, *tmp;
cea0f0e7 1342
a770f6f2 1343 role = vcpu->arch.mmu.base_role;
cea0f0e7 1344 role.level = level;
f6e2c02b 1345 role.direct = direct;
84b0c8c6 1346 if (role.direct)
5b7e0102 1347 role.cr4_pae = 0;
41074d07 1348 role.access = access;
ad312c7c 1349 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1350 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1351 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1352 role.quadrant = quadrant;
1353 }
1ae0a13d 1354 index = kvm_page_table_hashfn(gfn);
f05e70ac 1355 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1356 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1357 if (sp->gfn == gfn) {
1358 if (sp->unsync)
1359 if (kvm_sync_page(vcpu, sp))
1360 continue;
1361
1362 if (sp->role.word != role.word)
1363 continue;
1364
4db35314 1365 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1366 if (sp->unsync_children) {
1367 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
6b18493d 1368 kvm_mmu_mark_parents_unsync(sp);
0074ff63 1369 }
f691fe1d 1370 trace_kvm_mmu_get_page(sp, false);
4db35314 1371 return sp;
cea0f0e7 1372 }
dfc5aa00 1373 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1374 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1375 if (!sp)
1376 return sp;
4db35314
AK		 1377 sp->gfn = gfn;
1378 sp->role = role;
1379 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1380 if (!direct) {
b1a36821
MT		 1381 if (rmap_write_protect(vcpu->kvm, gfn))
1382 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1383 account_shadowed(vcpu->kvm, gfn);
1384 }
131d8279
AK		 1385 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1386 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1387 else
1388 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1389 trace_kvm_mmu_get_page(sp, true);
4db35314 1390 return sp;
cea0f0e7
AK		 1391}
1392
2d11123a
AK		 1393static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1394 struct kvm_vcpu *vcpu, u64 addr)
1395{
1396 iterator->addr = addr;
1397 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1398 iterator->level = vcpu->arch.mmu.shadow_root_level;
1399 if (iterator->level == PT32E_ROOT_LEVEL) {
1400 iterator->shadow_addr
1401 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1402 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1403 --iterator->level;
1404 if (!iterator->shadow_addr)
1405 iterator->level = 0;
1406 }
1407}
1408
1409static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1410{
1411 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1412 return false;
4d88954d
MT		 1413
1414 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1415 if (is_large_pte(*iterator->sptep))
1416 return false;
1417
2d11123a
AK		 1418 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1419 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1420 return true;
1421}
1422
1423static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1424{
1425 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1426 --iterator->level;
1427}
1428
90cb0529 1429static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1430 struct kvm_mmu_page *sp)
a436036b 1431{
697fe2e2
AK		 1432 unsigned i;
1433 u64 *pt;
1434 u64 ent;
1435
4db35314 1436 pt = sp->spt;
697fe2e2 1437
697fe2e2
AK		 1438 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1439 ent = pt[i];
1440
05da4558 1441 if (is_shadow_present_pte(ent)) {
776e6633 1442 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1443 ent &= PT64_BASE_ADDR_MASK;
1444 mmu_page_remove_parent_pte(page_header(ent),
1445 &pt[i]);
1446 } else {
776e6633
MT		 1447 if (is_large_pte(ent))
1448 --kvm->stat.lpages;
05da4558
MT		 1449 rmap_remove(kvm, &pt[i]);
1450 }
1451 }
c7addb90 1452 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1453 }
a436036b
AK		 1454}
1455
4db35314 1456static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1457{
4db35314 1458 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1459}
1460
12b7d28f
AK		 1461static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1462{
1463 int i;
988a2cae 1464 struct kvm_vcpu *vcpu;
12b7d28f 1465
988a2cae
GN		 1466 kvm_for_each_vcpu(i, vcpu, kvm)
1467 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1468}
1469
31aa2b44 1470static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1471{
1472 u64 *parent_pte;
1473
4db35314
AK		 1474 while (sp->multimapped || sp->parent_pte) {
1475 if (!sp->multimapped)
1476 parent_pte = sp->parent_pte;
a436036b
AK		 1477 else {
1478 struct kvm_pte_chain *chain;
1479
4db35314 1480 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1481 struct kvm_pte_chain, link);
1482 parent_pte = chain->parent_ptes[0];
1483 }
697fe2e2 1484 BUG_ON(!parent_pte);
4db35314 1485 kvm_mmu_put_page(sp, parent_pte);
d555c333 1486 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1487 }
31aa2b44
AK		 1488}
1489
60c8aec6
MT		 1490static int mmu_zap_unsync_children(struct kvm *kvm,
1491 struct kvm_mmu_page *parent)
4731d4c7 1492{
60c8aec6
MT		 1493 int i, zapped = 0;
1494 struct mmu_page_path parents;
1495 struct kvm_mmu_pages pages;
4731d4c7 1496
60c8aec6 1497 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1498 return 0;
60c8aec6
MT		 1499
1500 kvm_mmu_pages_init(parent, &parents, &pages);
1501 while (mmu_unsync_walk(parent, &pages)) {
1502 struct kvm_mmu_page *sp;
1503
1504 for_each_sp(pages, sp, parents, i) {
1505 kvm_mmu_zap_page(kvm, sp);
1506 mmu_pages_clear_parents(&parents);
77662e00 1507 zapped++;
60c8aec6 1508 }
60c8aec6
MT		 1509 kvm_mmu_pages_init(parent, &parents, &pages);
1510 }
1511
1512 return zapped;
4731d4c7
MT		 1513}
1514
07385413 1515static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1516{
4731d4c7 1517 int ret;
f691fe1d
AK		 1518
1519 trace_kvm_mmu_zap_page(sp);
31aa2b44 1520 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1521 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1522 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1523 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1524 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1525 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1526 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1527 if (sp->unsync)
1528 kvm_unlink_unsync_page(kvm, sp);
4db35314 1529 if (!sp->root_count) {
54a4f023
GJ		 1530 /* Count self */
1531 ret++;
4db35314
AK		 1532 hlist_del(&sp->hash_link);
1533 kvm_mmu_free_page(kvm, sp);
2e53d63a 1534 } else {
2e53d63a 1535 sp->role.invalid = 1;
5b5c6a5a 1536 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1537 kvm_reload_remote_mmus(kvm);
1538 }
12b7d28f 1539 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1540 return ret;
a436036b
AK		 1541}
1542
82ce2c96
IE		 1543/*
1544 * Changing the number of mmu pages allocated to the vm
1545 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1546 */
1547void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1548{
025dbbf3
MT		 1549 int used_pages;
1550
1551 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1552 used_pages = max(0, used_pages);
1553
82ce2c96
IE		 1554 /*
1555 * If we set the number of mmu pages to be smaller be than the
1556 * number of actived pages , we must to free some mmu pages before we
1557 * change the value
1558 */
1559
025dbbf3 1560 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1561 while (used_pages > kvm_nr_mmu_pages &&
1562 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1563 struct kvm_mmu_page *page;
1564
f05e70ac 1565 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1566 struct kvm_mmu_page, link);
77662e00 1567 used_pages -= kvm_mmu_zap_page(kvm, page);
82ce2c96 1568 }
77662e00 1569 kvm_nr_mmu_pages = used_pages;
f05e70ac 1570 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1571 }
1572 else
f05e70ac
ZX		 1573 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1574 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1575
f05e70ac 1576 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1577}
1578
f67a46f4 1579static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1580{
1581 unsigned index;
1582 struct hlist_head *bucket;
4db35314 1583 struct kvm_mmu_page *sp;
a436036b
AK		 1584 struct hlist_node *node, *n;
1585 int r;
1586
b8688d51 1587 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1588 r = 0;
1ae0a13d 1589 index = kvm_page_table_hashfn(gfn);
f05e70ac 1590 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1591restart:
4db35314 1592 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1593 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1594 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1595 sp->role.word);
a436036b 1596 r = 1;
07385413 1597 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1598 goto restart;
a436036b
AK		 1599 }
1600 return r;
cea0f0e7
AK		 1601}
1602
f67a46f4 1603static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1604{
4677a3b6
AK		 1605 unsigned index;
1606 struct hlist_head *bucket;
4db35314 1607 struct kvm_mmu_page *sp;
4677a3b6 1608 struct hlist_node *node, *nn;
97a0a01e 1609
4677a3b6
AK		 1610 index = kvm_page_table_hashfn(gfn);
1611 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1612restart:
4677a3b6 1613 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1614 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1615 && !sp->role.invalid) {
1616 pgprintk("%s: zap %lx %x\n",
1617 __func__, gfn, sp->role.word);
77662e00 1618 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1619 goto restart;
4677a3b6 1620 }
97a0a01e
AK		 1621 }
1622}
1623
38c335f1 1624static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1625{
bc6678a3 1626 int slot = memslot_id(kvm, gfn);
4db35314 1627 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1628
291f26bc 1629 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1630}
1631
6844dec6
MT		 1632static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1633{
1634 int i;
1635 u64 *pt = sp->spt;
1636
1637 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1638 return;
1639
1640 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1641 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1642 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1643 }
1644}
1645
74be52e3
SY		 1646/*
1647 * The function is based on mtrr_type_lookup() in
1648 * arch/x86/kernel/cpu/mtrr/generic.c
1649 */
1650static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1651 u64 start, u64 end)
1652{
1653 int i;
1654 u64 base, mask;
1655 u8 prev_match, curr_match;
1656 int num_var_ranges = KVM_NR_VAR_MTRR;
1657
1658 if (!mtrr_state->enabled)
1659 return 0xFF;
1660
1661 /* Make end inclusive end, instead of exclusive */
1662 end--;
1663
1664 /* Look in fixed ranges. Just return the type as per start */
1665 if (mtrr_state->have_fixed && (start < 0x100000)) {
1666 int idx;
1667
1668 if (start < 0x80000) {
1669 idx = 0;
1670 idx += (start >> 16);
1671 return mtrr_state->fixed_ranges[idx];
1672 } else if (start < 0xC0000) {
1673 idx = 1 * 8;
1674 idx += ((start - 0x80000) >> 14);
1675 return mtrr_state->fixed_ranges[idx];
1676 } else if (start < 0x1000000) {
1677 idx = 3 * 8;
1678 idx += ((start - 0xC0000) >> 12);
1679 return mtrr_state->fixed_ranges[idx];
1680 }
1681 }
1682
1683 /*
1684 * Look in variable ranges
1685 * Look of multiple ranges matching this address and pick type
1686 * as per MTRR precedence
1687 */
1688 if (!(mtrr_state->enabled & 2))
1689 return mtrr_state->def_type;
1690
1691 prev_match = 0xFF;
1692 for (i = 0; i < num_var_ranges; ++i) {
1693 unsigned short start_state, end_state;
1694
1695 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1696 continue;
1697
1698 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1699 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1700 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1701 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1702
1703 start_state = ((start & mask) == (base & mask));
1704 end_state = ((end & mask) == (base & mask));
1705 if (start_state != end_state)
1706 return 0xFE;
1707
1708 if ((start & mask) != (base & mask))
1709 continue;
1710
1711 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1712 if (prev_match == 0xFF) {
1713 prev_match = curr_match;
1714 continue;
1715 }
1716
1717 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1718 curr_match == MTRR_TYPE_UNCACHABLE)
1719 return MTRR_TYPE_UNCACHABLE;
1720
1721 if ((prev_match == MTRR_TYPE_WRBACK &&
1722 curr_match == MTRR_TYPE_WRTHROUGH) ||
1723 (prev_match == MTRR_TYPE_WRTHROUGH &&
1724 curr_match == MTRR_TYPE_WRBACK)) {
1725 prev_match = MTRR_TYPE_WRTHROUGH;
1726 curr_match = MTRR_TYPE_WRTHROUGH;
1727 }
1728
1729 if (prev_match != curr_match)
1730 return MTRR_TYPE_UNCACHABLE;
1731 }
1732
1733 if (prev_match != 0xFF)
1734 return prev_match;
1735
1736 return mtrr_state->def_type;
1737}
1738
4b12f0de 1739u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1740{
1741 u8 mtrr;
1742
1743 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1744 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1745 if (mtrr == 0xfe || mtrr == 0xff)
1746 mtrr = MTRR_TYPE_WRBACK;
1747 return mtrr;
1748}
4b12f0de 1749EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1750
4731d4c7
MT		 1751static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1752{
1753 unsigned index;
1754 struct hlist_head *bucket;
1755 struct kvm_mmu_page *s;
1756 struct hlist_node *node, *n;
1757
1758 index = kvm_page_table_hashfn(sp->gfn);
1759 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1760 /* don't unsync if pagetable is shadowed with multiple roles */
1761 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1762 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1763 continue;
1764 if (s->role.word != sp->role.word)
1765 return 1;
1766 }
5e1b3ddb 1767 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1768 ++vcpu->kvm->stat.mmu_unsync;
1769 sp->unsync = 1;
6cffe8ca 1770
6b18493d 1771 kvm_mmu_mark_parents_unsync(sp);
6cffe8ca 1772
4731d4c7
MT		 1773 mmu_convert_notrap(sp);
1774 return 0;
1775}
1776
1777static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1778 bool can_unsync)
1779{
1780 struct kvm_mmu_page *shadow;
1781
1782 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1783 if (shadow) {
1784 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1785 return 1;
1786 if (shadow->unsync)
1787 return 0;
582801a9 1788 if (can_unsync && oos_shadow)
4731d4c7
MT		 1789 return kvm_unsync_page(vcpu, shadow);
1790 return 1;
1791 }
1792 return 0;
1793}
1794
d555c333 1795static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1796 unsigned pte_access, int user_fault,
852e3c19 1797 int write_fault, int dirty, int level,
c2d0ee46 1798 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1799 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1800{
1801 u64 spte;
1e73f9dd 1802 int ret = 0;
64d4d521 1803
1c4f1fd6
AK		 1804 /*
1805 * We don't set the accessed bit, since we sometimes want to see
1806 * whether the guest actually used the pte (in order to detect
1807 * demand paging).
1808 */
7b52345e 1809 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1810 if (!speculative)
3201b5d9 1811 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1812 if (!dirty)
1813 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1814 if (pte_access & ACC_EXEC_MASK)
1815 spte |= shadow_x_mask;
1816 else
1817 spte |= shadow_nx_mask;
1c4f1fd6 1818 if (pte_access & ACC_USER_MASK)
7b52345e 1819 spte |= shadow_user_mask;
852e3c19 1820 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1821 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1822 if (tdp_enabled)
1823 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1824 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1825
1403283a
IE		 1826 if (reset_host_protection)
1827 spte |= SPTE_HOST_WRITEABLE;
1828
35149e21 1829 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1830
1831 if ((pte_access & ACC_WRITE_MASK)
1832 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1833
852e3c19
JR		 1834 if (level > PT_PAGE_TABLE_LEVEL &&
1835 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83 1836 ret = 1;
6d74229f 1837 rmap_remove(vcpu->kvm, sptep);
38187c83
MT		 1838 spte = shadow_trap_nonpresent_pte;
1839 goto set_pte;
1840 }
1841
1c4f1fd6 1842 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1843
69325a12
AK		 1844 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1845 spte &= ~PT_USER_MASK;
1846
ecc5589f
MT		 1847 /*
1848 * Optimization: for pte sync, if spte was writable the hash
1849 * lookup is unnecessary (and expensive). Write protection
1850 * is responsibility of mmu_get_page / kvm_sync_page.
1851 * Same reasoning can be applied to dirty page accounting.
1852 */
8dae4445 1853 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1854 goto set_pte;
1855
4731d4c7 1856 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1857 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1858 __func__, gfn);
1e73f9dd 1859 ret = 1;
1c4f1fd6 1860 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1861 if (is_writable_pte(spte))
1c4f1fd6 1862 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1863 }
1864 }
1865
1c4f1fd6
AK		 1866 if (pte_access & ACC_WRITE_MASK)
1867 mark_page_dirty(vcpu->kvm, gfn);
1868
38187c83 1869set_pte:
d555c333 1870 __set_spte(sptep, spte);
1e73f9dd
MT		 1871 return ret;
1872}
1873
d555c333 1874static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1875 unsigned pt_access, unsigned pte_access,
1876 int user_fault, int write_fault, int dirty,
852e3c19 1877 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1878 pfn_t pfn, bool speculative,
1879 bool reset_host_protection)
1e73f9dd
MT		 1880{
1881 int was_rmapped = 0;
8dae4445 1882 int was_writable = is_writable_pte(*sptep);
53a27b39 1883 int rmap_count;
1e73f9dd
MT		 1884
1885 pgprintk("%s: spte %llx access %x write_fault %d"
1886 " user_fault %d gfn %lx\n",
d555c333 1887 __func__, *sptep, pt_access,
1e73f9dd
MT		 1888 write_fault, user_fault, gfn);
1889
d555c333 1890 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1891 /*
1892 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1893 * the parent of the now unreachable PTE.
1894 */
852e3c19
JR		 1895 if (level > PT_PAGE_TABLE_LEVEL &&
1896 !is_large_pte(*sptep)) {
1e73f9dd 1897 struct kvm_mmu_page *child;
d555c333 1898 u64 pte = *sptep;
1e73f9dd
MT		 1899
1900 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1901 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT		 1902 __set_spte(sptep, shadow_trap_nonpresent_pte);
1903 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1904 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1905 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1906 spte_to_pfn(*sptep), pfn);
1907 rmap_remove(vcpu->kvm, sptep);
91546356
XG		 1908 __set_spte(sptep, shadow_trap_nonpresent_pte);
1909 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 1910 } else
1911 was_rmapped = 1;
1e73f9dd 1912 }
852e3c19 1913
d555c333 1914 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1915 dirty, level, gfn, pfn, speculative, true,
1916 reset_host_protection)) {
1e73f9dd
MT		 1917 if (write_fault)
1918 *ptwrite = 1;
a378b4e6
MT		 1919 kvm_x86_ops->tlb_flush(vcpu);
1920 }
1e73f9dd 1921
d555c333 1922 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1923 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1924 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1925 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1926 *sptep, sptep);
d555c333 1927 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1928 ++vcpu->kvm->stat.lpages;
1929
d555c333 1930 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1931 if (!was_rmapped) {
44ad9944 1932 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1933 kvm_release_pfn_clean(pfn);
53a27b39 1934 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1935 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1936 } else {
8dae4445 1937 if (was_writable)
35149e21 1938 kvm_release_pfn_dirty(pfn);
75e68e60 1939 else
35149e21 1940 kvm_release_pfn_clean(pfn);
1c4f1fd6 1941 }
1b7fcd32 1942 if (speculative) {
d555c333 1943 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1944 vcpu->arch.last_pte_gfn = gfn;
1945 }
1c4f1fd6
AK		 1946}
1947
6aa8b732
AK		 1948static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1949{
1950}
1951
9f652d21 1952static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1953 int level, gfn_t gfn, pfn_t pfn)
140754bc 1954{
9f652d21 1955 struct kvm_shadow_walk_iterator iterator;
140754bc 1956 struct kvm_mmu_page *sp;
9f652d21 1957 int pt_write = 0;
140754bc 1958 gfn_t pseudo_gfn;
6aa8b732 1959
9f652d21 1960 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1961 if (iterator.level == level) {
9f652d21
AK		 1962 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1963 0, write, 1, &pt_write,
1403283a 1964 level, gfn, pfn, false, true);
9f652d21
AK		 1965 ++vcpu->stat.pf_fixed;
1966 break;
6aa8b732
AK		 1967 }
1968
9f652d21
AK		 1969 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1970 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1971 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1972 iterator.level - 1,
1973 1, ACC_ALL, iterator.sptep);
1974 if (!sp) {
1975 pgprintk("nonpaging_map: ENOMEM\n");
1976 kvm_release_pfn_clean(pfn);
1977 return -ENOMEM;
1978 }
140754bc 1979
d555c333
AK		 1980 __set_spte(iterator.sptep,
1981 __pa(sp->spt)
1982 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1983 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1984 }
1985 }
1986 return pt_write;
6aa8b732
AK		 1987}
1988
bf998156
HY		 1989static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
1990{
1991 char buf[1];
1992 void __user *hva;
1993 int r;
1994
1995 /* Touch the page, so send SIGBUS */
1996 hva = (void __user *)gfn_to_hva(kvm, gfn);
1997 r = copy_from_user(buf, hva, 1);
1998}
1999
2000static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2001{
2002 kvm_release_pfn_clean(pfn);
2003 if (is_hwpoison_pfn(pfn)) {
2004 kvm_send_hwpoison_signal(kvm, gfn);
2005 return 0;
2006 }
2007 return 1;
2008}
2009
10589a46
MT		 2010static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2011{
2012 int r;
852e3c19 2013 int level;
35149e21 2014 pfn_t pfn;
e930bffe 2015 unsigned long mmu_seq;
aaee2c94 2016
852e3c19
JR		 2017 level = mapping_level(vcpu, gfn);
2018
2019 /*
2020 * This path builds a PAE pagetable - so we can map 2mb pages at
2021 * maximum. Therefore check if the level is larger than that.
2022 */
2023 if (level > PT_DIRECTORY_LEVEL)
2024 level = PT_DIRECTORY_LEVEL;
2025
2026 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2027
e930bffe 2028 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2029 smp_rmb();
35149e21 2030 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2031
d196e343 2032 /* mmio */
bf998156
HY		 2033 if (is_error_pfn(pfn))
2034 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2035
aaee2c94 2036 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2037 if (mmu_notifier_retry(vcpu, mmu_seq))
2038 goto out_unlock;
eb787d10 2039 kvm_mmu_free_some_pages(vcpu);
852e3c19 2040 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2041 spin_unlock(&vcpu->kvm->mmu_lock);
2042
aaee2c94 2043
10589a46 2044 return r;
e930bffe
AA		 2045
2046out_unlock:
2047 spin_unlock(&vcpu->kvm->mmu_lock);
2048 kvm_release_pfn_clean(pfn);
2049 return 0;
10589a46
MT		 2050}
2051
2052
17ac10ad
AK		 2053static void mmu_free_roots(struct kvm_vcpu *vcpu)
2054{
2055 int i;
4db35314 2056 struct kvm_mmu_page *sp;
17ac10ad 2057
ad312c7c 2058 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2059 return;
aaee2c94 2060 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2061 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2062 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2063
4db35314
AK		 2064 sp = page_header(root);
2065 --sp->root_count;
2e53d63a
MT		 2066 if (!sp->root_count && sp->role.invalid)
2067 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2068 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2069 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2070 return;
2071 }
17ac10ad 2072 for (i = 0; i < 4; ++i) {
ad312c7c 2073 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2074
417726a3 2075 if (root) {
417726a3 2076 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2077 sp = page_header(root);
2078 --sp->root_count;
2e53d63a
MT		 2079 if (!sp->root_count && sp->role.invalid)
2080 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2081 }
ad312c7c 2082 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2083 }
aaee2c94 2084 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2085 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2086}
2087
8986ecc0
MT		 2088static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2089{
2090 int ret = 0;
2091
2092 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2093 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2094 ret = 1;
2095 }
2096
2097 return ret;
2098}
2099
2100static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2101{
2102 int i;
cea0f0e7 2103 gfn_t root_gfn;
4db35314 2104 struct kvm_mmu_page *sp;
f6e2c02b 2105 int direct = 0;
6de4f3ad 2106 u64 pdptr;
3bb65a22 2107
ad312c7c 2108 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2109
ad312c7c
ZX		 2110 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2111 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2112
2113 ASSERT(!VALID_PAGE(root));
8986ecc0
MT		 2114 if (mmu_check_root(vcpu, root_gfn))
2115 return 1;
5a7388c2
EN		 2116 if (tdp_enabled) {
2117 direct = 1;
2118 root_gfn = 0;
2119 }
8facbbff 2120 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2121 kvm_mmu_free_some_pages(vcpu);
4db35314 2122 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2123 PT64_ROOT_LEVEL, direct,
fb72d167 2124 ACC_ALL, NULL);
4db35314
AK		 2125 root = __pa(sp->spt);
2126 ++sp->root_count;
8facbbff 2127 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2128 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2129 return 0;
17ac10ad 2130 }
f6e2c02b 2131 direct = !is_paging(vcpu);
17ac10ad 2132 for (i = 0; i < 4; ++i) {
ad312c7c 2133 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2134
2135 ASSERT(!VALID_PAGE(root));
ad312c7c 2136 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2137 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2138 if (!is_present_gpte(pdptr)) {
ad312c7c 2139 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2140 continue;
2141 }
6de4f3ad 2142 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2143 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2144 root_gfn = 0;
8986ecc0
MT		 2145 if (mmu_check_root(vcpu, root_gfn))
2146 return 1;
5a7388c2
EN		 2147 if (tdp_enabled) {
2148 direct = 1;
2149 root_gfn = i << 30;
2150 }
8facbbff 2151 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2152 kvm_mmu_free_some_pages(vcpu);
4db35314 2153 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2154 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2155 ACC_ALL, NULL);
4db35314
AK		 2156 root = __pa(sp->spt);
2157 ++sp->root_count;
8facbbff
AK		 2158 spin_unlock(&vcpu->kvm->mmu_lock);
2159
ad312c7c 2160 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2161 }
ad312c7c 2162 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2163 return 0;
17ac10ad
AK		 2164}
2165
0ba73cda
MT		 2166static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2167{
2168 int i;
2169 struct kvm_mmu_page *sp;
2170
2171 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2172 return;
2173 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2174 hpa_t root = vcpu->arch.mmu.root_hpa;
2175 sp = page_header(root);
2176 mmu_sync_children(vcpu, sp);
2177 return;
2178 }
2179 for (i = 0; i < 4; ++i) {
2180 hpa_t root = vcpu->arch.mmu.pae_root[i];
2181
8986ecc0 2182 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2183 root &= PT64_BASE_ADDR_MASK;
2184 sp = page_header(root);
2185 mmu_sync_children(vcpu, sp);
2186 }
2187 }
2188}
2189
2190void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2191{
2192 spin_lock(&vcpu->kvm->mmu_lock);
2193 mmu_sync_roots(vcpu);
6cffe8ca 2194 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2195}
2196
1871c602
GN		 2197static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2198 u32 access, u32 *error)
6aa8b732 2199{
1871c602
GN		 2200 if (error)
2201 *error = 0;
6aa8b732
AK		 2202 return vaddr;
2203}
2204
2205static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2206 u32 error_code)
6aa8b732 2207{
e833240f 2208 gfn_t gfn;
e2dec939 2209 int r;
6aa8b732 2210
b8688d51 2211 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2212 r = mmu_topup_memory_caches(vcpu);
2213 if (r)
2214 return r;
714b93da 2215
6aa8b732 2216 ASSERT(vcpu);
ad312c7c 2217 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2218
e833240f 2219 gfn = gva >> PAGE_SHIFT;
6aa8b732 2220
e833240f
AK		 2221 return nonpaging_map(vcpu, gva & PAGE_MASK,
2222 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2223}
2224
fb72d167
JR		 2225static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2226 u32 error_code)
2227{
35149e21 2228 pfn_t pfn;
fb72d167 2229 int r;
852e3c19 2230 int level;
05da4558 2231 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2232 unsigned long mmu_seq;
fb72d167
JR		 2233
2234 ASSERT(vcpu);
2235 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2236
2237 r = mmu_topup_memory_caches(vcpu);
2238 if (r)
2239 return r;
2240
852e3c19
JR		 2241 level = mapping_level(vcpu, gfn);
2242
2243 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2244
e930bffe 2245 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2246 smp_rmb();
35149e21 2247 pfn = gfn_to_pfn(vcpu->kvm, gfn);
bf998156
HY		 2248 if (is_error_pfn(pfn))
2249 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2250 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2251 if (mmu_notifier_retry(vcpu, mmu_seq))
2252 goto out_unlock;
fb72d167
JR		 2253 kvm_mmu_free_some_pages(vcpu);
2254 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2255 level, gfn, pfn);
fb72d167 2256 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2257
2258 return r;
e930bffe
AA		 2259
2260out_unlock:
2261 spin_unlock(&vcpu->kvm->mmu_lock);
2262 kvm_release_pfn_clean(pfn);
2263 return 0;
fb72d167
JR		 2264}
2265
6aa8b732
AK		 2266static void nonpaging_free(struct kvm_vcpu *vcpu)
2267{
17ac10ad 2268 mmu_free_roots(vcpu);
6aa8b732
AK		 2269}
2270
2271static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2272{
ad312c7c 2273 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2274
2275 context->new_cr3 = nonpaging_new_cr3;
2276 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2277 context->gva_to_gpa = nonpaging_gva_to_gpa;
2278 context->free = nonpaging_free;
c7addb90 2279 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2280 context->sync_page = nonpaging_sync_page;
a7052897 2281 context->invlpg = nonpaging_invlpg;
cea0f0e7 2282 context->root_level = 0;
6aa8b732 2283 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2284 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2285 return 0;
2286}
2287
d835dfec 2288void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2289{
1165f5fe 2290 ++vcpu->stat.tlb_flush;
cbdd1bea 2291 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2292}
2293
2294static void paging_new_cr3(struct kvm_vcpu *vcpu)
2295{
b8688d51 2296 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2297 mmu_free_roots(vcpu);
6aa8b732
AK		 2298}
2299
6aa8b732
AK		 2300static void inject_page_fault(struct kvm_vcpu *vcpu,
2301 u64 addr,
2302 u32 err_code)
2303{
c3c91fee 2304 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2305}
2306
6aa8b732
AK		 2307static void paging_free(struct kvm_vcpu *vcpu)
2308{
2309 nonpaging_free(vcpu);
2310}
2311
82725b20
DE		 2312static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2313{
2314 int bit7;
2315
2316 bit7 = (gpte >> 7) & 1;
2317 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2318}
2319
6aa8b732
AK		 2320#define PTTYPE 64
2321#include "paging_tmpl.h"
2322#undef PTTYPE
2323
2324#define PTTYPE 32
2325#include "paging_tmpl.h"
2326#undef PTTYPE
2327
82725b20
DE		 2328static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2329{
2330 struct kvm_mmu *context = &vcpu->arch.mmu;
2331 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2332 u64 exb_bit_rsvd = 0;
2333
2334 if (!is_nx(vcpu))
2335 exb_bit_rsvd = rsvd_bits(63, 63);
2336 switch (level) {
2337 case PT32_ROOT_LEVEL:
2338 /* no rsvd bits for 2 level 4K page table entries */
2339 context->rsvd_bits_mask[0][1] = 0;
2340 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2341 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2342
2343 if (!is_pse(vcpu)) {
2344 context->rsvd_bits_mask[1][1] = 0;
2345 break;
2346 }
2347
82725b20
DE		 2348 if (is_cpuid_PSE36())
2349 /* 36bits PSE 4MB page */
2350 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2351 else
2352 /* 32 bits PSE 4MB page */
2353 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2354 break;
2355 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2356 context->rsvd_bits_mask[0][2] =
2357 rsvd_bits(maxphyaddr, 63) |
2358 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2359 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2360 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2361 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2362 rsvd_bits(maxphyaddr, 62); /* PTE */
2363 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2364 rsvd_bits(maxphyaddr, 62) |
2365 rsvd_bits(13, 20); /* large page */
f815bce8 2366 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2367 break;
2368 case PT64_ROOT_LEVEL:
2369 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2370 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2371 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2372 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2373 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2374 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2375 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2376 rsvd_bits(maxphyaddr, 51);
2377 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2378 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2379 rsvd_bits(maxphyaddr, 51) |
2380 rsvd_bits(13, 29);
82725b20 2381 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2382 rsvd_bits(maxphyaddr, 51) |
2383 rsvd_bits(13, 20); /* large page */
f815bce8 2384 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2385 break;
2386 }
2387}
2388
17ac10ad 2389static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2390{
ad312c7c 2391 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2392
2393 ASSERT(is_pae(vcpu));
2394 context->new_cr3 = paging_new_cr3;
2395 context->page_fault = paging64_page_fault;
6aa8b732 2396 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2397 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2398 context->sync_page = paging64_sync_page;
a7052897 2399 context->invlpg = paging64_invlpg;
6aa8b732 2400 context->free = paging_free;
17ac10ad
AK		 2401 context->root_level = level;
2402 context->shadow_root_level = level;
17c3ba9d 2403 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2404 return 0;
2405}
2406
17ac10ad
AK		 2407static int paging64_init_context(struct kvm_vcpu *vcpu)
2408{
82725b20 2409 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2410 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2411}
2412
6aa8b732
AK		 2413static int paging32_init_context(struct kvm_vcpu *vcpu)
2414{
ad312c7c 2415 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2416
82725b20 2417 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2418 context->new_cr3 = paging_new_cr3;
2419 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2420 context->gva_to_gpa = paging32_gva_to_gpa;
2421 context->free = paging_free;
c7addb90 2422 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2423 context->sync_page = paging32_sync_page;
a7052897 2424 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2425 context->root_level = PT32_ROOT_LEVEL;
2426 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2427 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2428 return 0;
2429}
2430
2431static int paging32E_init_context(struct kvm_vcpu *vcpu)
2432{
82725b20 2433 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2434 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2435}
2436
fb72d167
JR		 2437static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2438{
2439 struct kvm_mmu *context = &vcpu->arch.mmu;
2440
2441 context->new_cr3 = nonpaging_new_cr3;
2442 context->page_fault = tdp_page_fault;
2443 context->free = nonpaging_free;
2444 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2445 context->sync_page = nonpaging_sync_page;
a7052897 2446 context->invlpg = nonpaging_invlpg;
67253af5 2447 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2448 context->root_hpa = INVALID_PAGE;
2449
2450 if (!is_paging(vcpu)) {
2451 context->gva_to_gpa = nonpaging_gva_to_gpa;
2452 context->root_level = 0;
2453 } else if (is_long_mode(vcpu)) {
82725b20 2454 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2455 context->gva_to_gpa = paging64_gva_to_gpa;
2456 context->root_level = PT64_ROOT_LEVEL;
2457 } else if (is_pae(vcpu)) {
82725b20 2458 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2459 context->gva_to_gpa = paging64_gva_to_gpa;
2460 context->root_level = PT32E_ROOT_LEVEL;
2461 } else {
82725b20 2462 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2463 context->gva_to_gpa = paging32_gva_to_gpa;
2464 context->root_level = PT32_ROOT_LEVEL;
2465 }
2466
2467 return 0;
2468}
2469
2470static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2471{
a770f6f2
AK		 2472 int r;
2473
6aa8b732 2474 ASSERT(vcpu);
ad312c7c 2475 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2476
2477 if (!is_paging(vcpu))
a770f6f2 2478 r = nonpaging_init_context(vcpu);
a9058ecd 2479 else if (is_long_mode(vcpu))
a770f6f2 2480 r = paging64_init_context(vcpu);
6aa8b732 2481 else if (is_pae(vcpu))
a770f6f2 2482 r = paging32E_init_context(vcpu);
6aa8b732 2483 else
a770f6f2
AK		 2484 r = paging32_init_context(vcpu);
2485
5b7e0102 2486 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2487 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK		 2488
2489 return r;
6aa8b732
AK		 2490}
2491
fb72d167
JR		 2492static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2493{
35149e21
AL		 2494 vcpu->arch.update_pte.pfn = bad_pfn;
2495
fb72d167
JR		 2496 if (tdp_enabled)
2497 return init_kvm_tdp_mmu(vcpu);
2498 else
2499 return init_kvm_softmmu(vcpu);
2500}
2501
6aa8b732
AK		 2502static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2503{
2504 ASSERT(vcpu);
62ad0755
SY		 2505 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2506 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 2507 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK		 2508}
2509
2510int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2511{
2512 destroy_kvm_mmu(vcpu);
2513 return init_kvm_mmu(vcpu);
2514}
8668a3c4 2515EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2516
2517int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2518{
714b93da
AK		 2519 int r;
2520
e2dec939 2521 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2522 if (r)
2523 goto out;
8986ecc0 2524 r = mmu_alloc_roots(vcpu);
8facbbff 2525 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2526 mmu_sync_roots(vcpu);
aaee2c94 2527 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2528 if (r)
2529 goto out;
3662cb1c 2530 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2531 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2532out:
2533 return r;
6aa8b732 2534}
17c3ba9d
AK		 2535EXPORT_SYMBOL_GPL(kvm_mmu_load);
2536
2537void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2538{
2539 mmu_free_roots(vcpu);
2540}
6aa8b732 2541
09072daf 2542static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2543 struct kvm_mmu_page *sp,
ac1b714e
AK		 2544 u64 *spte)
2545{
2546 u64 pte;
2547 struct kvm_mmu_page *child;
2548
2549 pte = *spte;
c7addb90 2550 if (is_shadow_present_pte(pte)) {
776e6633 2551 if (is_last_spte(pte, sp->role.level))
290fc38d 2552 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2553 else {
2554 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2555 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2556 }
2557 }
d555c333 2558 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2559 if (is_large_pte(pte))
2560 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2561}
2562
0028425f 2563static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2564 struct kvm_mmu_page *sp,
0028425f 2565 u64 *spte,
489f1d65 2566 const void *new)
0028425f 2567{
30945387 2568 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2569 ++vcpu->kvm->stat.mmu_pde_zapped;
2570 return;
30945387 2571 }
0028425f 2572
4cee5764 2573 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2574 if (!sp->role.cr4_pae)
489f1d65 2575 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2576 else
489f1d65 2577 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2578}
2579
79539cec
AK		 2580static bool need_remote_flush(u64 old, u64 new)
2581{
2582 if (!is_shadow_present_pte(old))
2583 return false;
2584 if (!is_shadow_present_pte(new))
2585 return true;
2586 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2587 return true;
2588 old ^= PT64_NX_MASK;
2589 new ^= PT64_NX_MASK;
2590 return (old & ~new & PT64_PERM_MASK) != 0;
2591}
2592
2593static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2594{
2595 if (need_remote_flush(old, new))
2596 kvm_flush_remote_tlbs(vcpu->kvm);
2597 else
2598 kvm_mmu_flush_tlb(vcpu);
2599}
2600
12b7d28f
AK		 2601static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2602{
ad312c7c 2603 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2604
7b52345e 2605 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2606}
2607
d7824fff 2608static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2609 u64 gpte)
d7824fff
AK		 2610{
2611 gfn_t gfn;
35149e21 2612 pfn_t pfn;
d7824fff 2613
43a3795a 2614 if (!is_present_gpte(gpte))
d7824fff
AK		 2615 return;
2616 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2617
e930bffe 2618 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2619 smp_rmb();
35149e21 2620 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2621
35149e21
AL		 2622 if (is_error_pfn(pfn)) {
2623 kvm_release_pfn_clean(pfn);
d196e343
AK		 2624 return;
2625 }
d7824fff 2626 vcpu->arch.update_pte.gfn = gfn;
35149e21 2627 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2628}
2629
1b7fcd32
AK		 2630static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2631{
2632 u64 *spte = vcpu->arch.last_pte_updated;
2633
2634 if (spte
2635 && vcpu->arch.last_pte_gfn == gfn
2636 && shadow_accessed_mask
2637 && !(*spte & shadow_accessed_mask)
2638 && is_shadow_present_pte(*spte))
2639 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2640}
2641
09072daf 2642void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2643 const u8 *new, int bytes,
2644 bool guest_initiated)
da4a00f0 2645{
9b7a0325 2646 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2647 struct kvm_mmu_page *sp;
0e7bc4b9 2648 struct hlist_node *node, *n;
9b7a0325
AK		 2649 struct hlist_head *bucket;
2650 unsigned index;
489f1d65 2651 u64 entry, gentry;
9b7a0325 2652 u64 *spte;
9b7a0325 2653 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2654 unsigned pte_size;
9b7a0325 2655 unsigned page_offset;
0e7bc4b9 2656 unsigned misaligned;
fce0657f 2657 unsigned quadrant;
9b7a0325 2658 int level;
86a5ba02 2659 int flooded = 0;
ac1b714e 2660 int npte;
489f1d65 2661 int r;
08e850c6 2662 int invlpg_counter;
9b7a0325 2663
b8688d51 2664 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2665
08e850c6 2666 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2667
2668 /*
2669 * Assume that the pte write on a page table of the same type
2670 * as the current vcpu paging mode. This is nearly always true
2671 * (might be false while changing modes). Note it is verified later
2672 * by update_pte().
2673 */
08e850c6 2674 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2675 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2676 if (is_pae(vcpu)) {
2677 gpa &= ~(gpa_t)7;
2678 bytes = 8;
2679 }
2680 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2681 if (r)
2682 gentry = 0;
08e850c6
AK		 2683 new = (const u8 *)&gentry;
2684 }
2685
2686 switch (bytes) {
2687 case 4:
2688 gentry = *(const u32 *)new;
2689 break;
2690 case 8:
2691 gentry = *(const u64 *)new;
2692 break;
2693 default:
2694 gentry = 0;
2695 break;
72016f3a
AK		 2696 }
2697
2698 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2699 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2700 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2701 gentry = 0;
1b7fcd32 2702 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2703 kvm_mmu_free_some_pages(vcpu);
4cee5764 2704 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2705 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2706 if (guest_initiated) {
2707 if (gfn == vcpu->arch.last_pt_write_gfn
2708 && !last_updated_pte_accessed(vcpu)) {
2709 ++vcpu->arch.last_pt_write_count;
2710 if (vcpu->arch.last_pt_write_count >= 3)
2711 flooded = 1;
2712 } else {
2713 vcpu->arch.last_pt_write_gfn = gfn;
2714 vcpu->arch.last_pt_write_count = 1;
2715 vcpu->arch.last_pte_updated = NULL;
2716 }
86a5ba02 2717 }
1ae0a13d 2718 index = kvm_page_table_hashfn(gfn);
f05e70ac 2719 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
3246af0e
XG		 2720
2721restart:
4db35314 2722 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2723 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2724 continue;
5b7e0102 2725 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2726 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2727 misaligned |= bytes < 4;
86a5ba02 2728 if (misaligned || flooded) {
0e7bc4b9
AK		 2729 /*
2730 * Misaligned accesses are too much trouble to fix
2731 * up; also, they usually indicate a page is not used
2732 * as a page table.
86a5ba02
AK		 2733 *
2734 * If we're seeing too many writes to a page,
2735 * it may no longer be a page table, or we may be
2736 * forking, in which case it is better to unmap the
2737 * page.
0e7bc4b9
AK		 2738 */
2739 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2740 gpa, bytes, sp->role.word);
07385413 2741 if (kvm_mmu_zap_page(vcpu->kvm, sp))
3246af0e 2742 goto restart;
4cee5764 2743 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2744 continue;
2745 }
9b7a0325 2746 page_offset = offset;
4db35314 2747 level = sp->role.level;
ac1b714e 2748 npte = 1;
5b7e0102 2749 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2750 page_offset <<= 1; /* 32->64 */
2751 /*
2752 * A 32-bit pde maps 4MB while the shadow pdes map
2753 * only 2MB. So we need to double the offset again
2754 * and zap two pdes instead of one.
2755 */
2756 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2757 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2758 page_offset <<= 1;
2759 npte = 2;
2760 }
fce0657f 2761 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2762 page_offset &= ~PAGE_MASK;
4db35314 2763 if (quadrant != sp->role.quadrant)
fce0657f 2764 continue;
9b7a0325 2765 }
4db35314 2766 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2767 while (npte--) {
79539cec 2768 entry = *spte;
4db35314 2769 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2770 if (gentry)
2771 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2772 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2773 ++spte;
9b7a0325 2774 }
9b7a0325 2775 }
c7addb90 2776 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2777 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2778 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2779 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2780 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2781 }
da4a00f0
AK		 2782}
2783
a436036b
AK		 2784int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2785{
10589a46
MT		 2786 gpa_t gpa;
2787 int r;
a436036b 2788
60f24784
AK		 2789 if (tdp_enabled)
2790 return 0;
2791
1871c602 2792 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2793
aaee2c94 2794 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2795 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2796 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2797 return r;
a436036b 2798}
577bdc49 2799EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2800
22d95b12 2801void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2802{
3b80fffe
IE		 2803 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2804 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2805 struct kvm_mmu_page *sp;
ebeace86 2806
f05e70ac 2807 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2808 struct kvm_mmu_page, link);
2809 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2810 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2811 }
2812}
ebeace86 2813
3067714c
AK		 2814int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2815{
2816 int r;
2817 enum emulation_result er;
2818
ad312c7c 2819 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2820 if (r < 0)
2821 goto out;
2822
2823 if (!r) {
2824 r = 1;
2825 goto out;
2826 }
2827
b733bfb5
AK		 2828 r = mmu_topup_memory_caches(vcpu);
2829 if (r)
2830 goto out;
2831
851ba692 2832 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2833
2834 switch (er) {
2835 case EMULATE_DONE:
2836 return 1;
2837 case EMULATE_DO_MMIO:
2838 ++vcpu->stat.mmio_exits;
6d77dbfc 2839 /* fall through */
3067714c 2840 case EMULATE_FAIL:
3f5d18a9 2841 return 0;
3067714c
AK		 2842 default:
2843 BUG();
2844 }
2845out:
3067714c
AK		 2846 return r;
2847}
2848EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2849
a7052897
MT		 2850void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2851{
a7052897 2852 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2853 kvm_mmu_flush_tlb(vcpu);
2854 ++vcpu->stat.invlpg;
2855}
2856EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2857
18552672
JR		 2858void kvm_enable_tdp(void)
2859{
2860 tdp_enabled = true;
2861}
2862EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2863
5f4cb662
JR		 2864void kvm_disable_tdp(void)
2865{
2866 tdp_enabled = false;
2867}
2868EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2869
6aa8b732
AK		 2870static void free_mmu_pages(struct kvm_vcpu *vcpu)
2871{
ad312c7c 2872 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2873}
2874
2875static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2876{
17ac10ad 2877 struct page *page;
6aa8b732
AK		 2878 int i;
2879
2880 ASSERT(vcpu);
2881
17ac10ad
AK		 2882 /*
2883 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2884 * Therefore we need to allocate shadow page tables in the first
2885 * 4GB of memory, which happens to fit the DMA32 zone.
2886 */
2887 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2888 if (!page)
d7fa6ab2
WY		 2889 return -ENOMEM;
2890
ad312c7c 2891 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2892 for (i = 0; i < 4; ++i)
ad312c7c 2893 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2894
6aa8b732 2895 return 0;
6aa8b732
AK		 2896}
2897
8018c27b 2898int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2899{
6aa8b732 2900 ASSERT(vcpu);
ad312c7c 2901 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2902
8018c27b
IM		 2903 return alloc_mmu_pages(vcpu);
2904}
6aa8b732 2905
8018c27b
IM		 2906int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2907{
2908 ASSERT(vcpu);
ad312c7c 2909 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2910
8018c27b 2911 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2912}
2913
2914void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2915{
2916 ASSERT(vcpu);
2917
2918 destroy_kvm_mmu(vcpu);
2919 free_mmu_pages(vcpu);
714b93da 2920 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2921}
2922
90cb0529 2923void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2924{
4db35314 2925 struct kvm_mmu_page *sp;
6aa8b732 2926
f05e70ac 2927 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2928 int i;
2929 u64 *pt;
2930
291f26bc 2931 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2932 continue;
2933
4db35314 2934 pt = sp->spt;
6aa8b732
AK		 2935 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2936 /* avoid RMW */
9647c14c 2937 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2938 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2939 }
171d595d 2940 kvm_flush_remote_tlbs(kvm);
6aa8b732 2941}
37a7d8b0 2942
90cb0529 2943void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2944{
4db35314 2945 struct kvm_mmu_page *sp, *node;
e0fa826f 2946
aaee2c94 2947 spin_lock(&kvm->mmu_lock);
3246af0e 2948restart:
f05e70ac 2949 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413 2950 if (kvm_mmu_zap_page(kvm, sp))
3246af0e
XG		 2951 goto restart;
2952
aaee2c94 2953 spin_unlock(&kvm->mmu_lock);
e0fa826f 2954
90cb0529 2955 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2956}
2957
d35b8dd9 2958static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
3ee16c81
IE		 2959{
2960 struct kvm_mmu_page *page;
2961
2962 page = container_of(kvm->arch.active_mmu_pages.prev,
2963 struct kvm_mmu_page, link);
54a4f023 2964 return kvm_mmu_zap_page(kvm, page);
3ee16c81
IE		 2965}
2966
7f8275d0 2967static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3ee16c81
IE		 2968{
2969 struct kvm *kvm;
2970 struct kvm *kvm_freed = NULL;
2971 int cache_count = 0;
2972
2973 spin_lock(&kvm_lock);
2974
2975 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 2976 int npages, idx, freed_pages;
3ee16c81 2977
f656ce01 2978 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2979 spin_lock(&kvm->mmu_lock);
2980 npages = kvm->arch.n_alloc_mmu_pages -
2981 kvm->arch.n_free_mmu_pages;
2982 cache_count += npages;
2983 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d35b8dd9
GJ		 2984 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
2985 cache_count -= freed_pages;
3ee16c81
IE		 2986 kvm_freed = kvm;
2987 }
2988 nr_to_scan--;
2989
2990 spin_unlock(&kvm->mmu_lock);
f656ce01 2991 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2992 }
2993 if (kvm_freed)
2994 list_move_tail(&kvm_freed->vm_list, &vm_list);
2995
2996 spin_unlock(&kvm_lock);
2997
2998 return cache_count;
2999}
3000
3001static struct shrinker mmu_shrinker = {
3002 .shrink = mmu_shrink,
3003 .seeks = DEFAULT_SEEKS * 10,
3004};
3005
2ddfd20e 3006static void mmu_destroy_caches(void)
b5a33a75
AK		 3007{
3008 if (pte_chain_cache)
3009 kmem_cache_destroy(pte_chain_cache);
3010 if (rmap_desc_cache)
3011 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 3012 if (mmu_page_header_cache)
3013 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 3014}
3015
3ee16c81
IE		 3016void kvm_mmu_module_exit(void)
3017{
3018 mmu_destroy_caches();
3019 unregister_shrinker(&mmu_shrinker);
3020}
3021
b5a33a75
AK		 3022int kvm_mmu_module_init(void)
3023{
3024 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3025 sizeof(struct kvm_pte_chain),
20c2df83 3026 0, 0, NULL);
b5a33a75
AK		 3027 if (!pte_chain_cache)
3028 goto nomem;
3029 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3030 sizeof(struct kvm_rmap_desc),
20c2df83 3031 0, 0, NULL);
b5a33a75
AK		 3032 if (!rmap_desc_cache)
3033 goto nomem;
3034
d3d25b04
AK		 3035 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3036 sizeof(struct kvm_mmu_page),
20c2df83 3037 0, 0, NULL);
d3d25b04
AK		 3038 if (!mmu_page_header_cache)
3039 goto nomem;
3040
3ee16c81
IE		 3041 register_shrinker(&mmu_shrinker);
3042
b5a33a75
AK		 3043 return 0;
3044
3045nomem:
3ee16c81 3046 mmu_destroy_caches();
b5a33a75
AK		 3047 return -ENOMEM;
3048}
3049
3ad82a7e
ZX		 3050/*
3051 * Caculate mmu pages needed for kvm.
3052 */
3053unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3054{
3055 int i;
3056 unsigned int nr_mmu_pages;
3057 unsigned int nr_pages = 0;
bc6678a3 3058 struct kvm_memslots *slots;
3ad82a7e 3059
90d83dc3
LJ		 3060 slots = kvm_memslots(kvm);
3061
bc6678a3
MT		 3062 for (i = 0; i < slots->nmemslots; i++)
3063 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3064
3065 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3066 nr_mmu_pages = max(nr_mmu_pages,
3067 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3068
3069 return nr_mmu_pages;
3070}
3071
2f333bcb
MT		 3072static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3073 unsigned len)
3074{
3075 if (len > buffer->len)
3076 return NULL;
3077 return buffer->ptr;
3078}
3079
3080static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3081 unsigned len)
3082{
3083 void *ret;
3084
3085 ret = pv_mmu_peek_buffer(buffer, len);
3086 if (!ret)
3087 return ret;
3088 buffer->ptr += len;
3089 buffer->len -= len;
3090 buffer->processed += len;
3091 return ret;
3092}
3093
3094static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3095 gpa_t addr, gpa_t value)
3096{
3097 int bytes = 8;
3098 int r;
3099
3100 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3101 bytes = 4;
3102
3103 r = mmu_topup_memory_caches(vcpu);
3104 if (r)
3105 return r;
3106
3200f405 3107 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3108 return -EFAULT;
3109
3110 return 1;
3111}
3112
3113static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3114{
a8cd0244 3115 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3116 return 1;
3117}
3118
3119static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3120{
3121 spin_lock(&vcpu->kvm->mmu_lock);
3122 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3123 spin_unlock(&vcpu->kvm->mmu_lock);
3124 return 1;
3125}
3126
3127static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3128 struct kvm_pv_mmu_op_buffer *buffer)
3129{
3130 struct kvm_mmu_op_header *header;
3131
3132 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3133 if (!header)
3134 return 0;
3135 switch (header->op) {
3136 case KVM_MMU_OP_WRITE_PTE: {
3137 struct kvm_mmu_op_write_pte *wpte;
3138
3139 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3140 if (!wpte)
3141 return 0;
3142 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3143 wpte->pte_val);
3144 }
3145 case KVM_MMU_OP_FLUSH_TLB: {
3146 struct kvm_mmu_op_flush_tlb *ftlb;
3147
3148 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3149 if (!ftlb)
3150 return 0;
3151 return kvm_pv_mmu_flush_tlb(vcpu);
3152 }
3153 case KVM_MMU_OP_RELEASE_PT: {
3154 struct kvm_mmu_op_release_pt *rpt;
3155
3156 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3157 if (!rpt)
3158 return 0;
3159 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3160 }
3161 default: return 0;
3162 }
3163}
3164
3165int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3166 gpa_t addr, unsigned long *ret)
3167{
3168 int r;
6ad18fba 3169 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3170
6ad18fba
DH		 3171 buffer->ptr = buffer->buf;
3172 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3173 buffer->processed = 0;
2f333bcb 3174
6ad18fba 3175 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3176 if (r)
3177 goto out;
3178
6ad18fba
DH		 3179 while (buffer->len) {
3180 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3181 if (r < 0)
3182 goto out;
3183 if (r == 0)
3184 break;
3185 }
3186
3187 r = 1;
3188out:
6ad18fba 3189 *ret = buffer->processed;
2f333bcb
MT		 3190 return r;
3191}
3192
94d8b056
MT		 3193int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3194{
3195 struct kvm_shadow_walk_iterator iterator;
3196 int nr_sptes = 0;
3197
3198 spin_lock(&vcpu->kvm->mmu_lock);
3199 for_each_shadow_entry(vcpu, addr, iterator) {
3200 sptes[iterator.level-1] = *iterator.sptep;
3201 nr_sptes++;
3202 if (!is_shadow_present_pte(*iterator.sptep))
3203 break;
3204 }
3205 spin_unlock(&vcpu->kvm->mmu_lock);
3206
3207 return nr_sptes;
3208}
3209EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3210
37a7d8b0
AK		 3211#ifdef AUDIT
3212
3213static const char *audit_msg;
3214
3215static gva_t canonicalize(gva_t gva)
3216{
3217#ifdef CONFIG_X86_64
3218 gva = (long long)(gva << 16) >> 16;
3219#endif
3220 return gva;
3221}
3222
08a3732b 3223
805d32de 3224typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3225
3226static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3227 inspect_spte_fn fn)
3228{
3229 int i;
3230
3231 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3232 u64 ent = sp->spt[i];
3233
3234 if (is_shadow_present_pte(ent)) {
2920d728 3235 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3236 struct kvm_mmu_page *child;
3237 child = page_header(ent & PT64_BASE_ADDR_MASK);
3238 __mmu_spte_walk(kvm, child, fn);
2920d728 3239 } else
805d32de 3240 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3241 }
3242 }
3243}
3244
3245static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3246{
3247 int i;
3248 struct kvm_mmu_page *sp;
3249
3250 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3251 return;
3252 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3253 hpa_t root = vcpu->arch.mmu.root_hpa;
3254 sp = page_header(root);
3255 __mmu_spte_walk(vcpu->kvm, sp, fn);
3256 return;
3257 }
3258 for (i = 0; i < 4; ++i) {
3259 hpa_t root = vcpu->arch.mmu.pae_root[i];
3260
3261 if (root && VALID_PAGE(root)) {
3262 root &= PT64_BASE_ADDR_MASK;
3263 sp = page_header(root);
3264 __mmu_spte_walk(vcpu->kvm, sp, fn);
3265 }
3266 }
3267 return;
3268}
3269
37a7d8b0
AK		 3270static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3271 gva_t va, int level)
3272{
3273 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3274 int i;
3275 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3276
3277 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3278 u64 ent = pt[i];
3279
c7addb90 3280 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3281 continue;
3282
3283 va = canonicalize(va);
2920d728
MT		 3284 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3285 audit_mappings_page(vcpu, ent, va, level - 1);
3286 else {
1871c602 3287 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3288 gfn_t gfn = gpa >> PAGE_SHIFT;
3289 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3290 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3291
2aaf65e8
MT		 3292 if (is_error_pfn(pfn)) {
3293 kvm_release_pfn_clean(pfn);
3294 continue;
3295 }
3296
c7addb90 3297 if (is_shadow_present_pte(ent)
37a7d8b0 3298 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3299 printk(KERN_ERR "xx audit error: (%s) levels %d"
3300 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3301 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3302 va, gpa, hpa, ent,
3303 is_shadow_present_pte(ent));
c7addb90
AK		 3304 else if (ent == shadow_notrap_nonpresent_pte
3305 && !is_error_hpa(hpa))
3306 printk(KERN_ERR "audit: (%s) notrap shadow,"
3307 " valid guest gva %lx\n", audit_msg, va);
35149e21 3308 kvm_release_pfn_clean(pfn);
c7addb90 3309
37a7d8b0
AK		 3310 }
3311 }
3312}
3313
3314static void audit_mappings(struct kvm_vcpu *vcpu)
3315{
1ea252af 3316 unsigned i;
37a7d8b0 3317
ad312c7c
ZX		 3318 if (vcpu->arch.mmu.root_level == 4)
3319 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3320 else
3321 for (i = 0; i < 4; ++i)
ad312c7c 3322 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3323 audit_mappings_page(vcpu,
ad312c7c 3324 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3325 i << 30,
3326 2);
3327}
3328
3329static int count_rmaps(struct kvm_vcpu *vcpu)
3330{
805d32de
XG		 3331 struct kvm *kvm = vcpu->kvm;
3332 struct kvm_memslots *slots;
37a7d8b0 3333 int nmaps = 0;
bc6678a3 3334 int i, j, k, idx;
37a7d8b0 3335
bc6678a3 3336 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3337 slots = kvm_memslots(kvm);
37a7d8b0 3338 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3339 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3340 struct kvm_rmap_desc *d;
3341
3342 for (j = 0; j < m->npages; ++j) {
290fc38d 3343 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3344
290fc38d 3345 if (!*rmapp)
37a7d8b0 3346 continue;
290fc38d 3347 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3348 ++nmaps;
3349 continue;
3350 }
290fc38d 3351 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3352 while (d) {
3353 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3354 if (d->sptes[k])
37a7d8b0
AK		 3355 ++nmaps;
3356 else
3357 break;
3358 d = d->more;
3359 }
3360 }
3361 }
bc6678a3 3362 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3363 return nmaps;
3364}
3365
805d32de 3366void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3367{
3368 unsigned long *rmapp;
3369 struct kvm_mmu_page *rev_sp;
3370 gfn_t gfn;
3371
3372 if (*sptep & PT_WRITABLE_MASK) {
3373 rev_sp = page_header(__pa(sptep));
3374 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3375
3376 if (!gfn_to_memslot(kvm, gfn)) {
3377 if (!printk_ratelimit())
3378 return;
3379 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3380 audit_msg, gfn);
3381 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3382 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3383 rev_sp->gfn);
3384 dump_stack();
3385 return;
3386 }
3387
2920d728 3388 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3389 rev_sp->role.level);
08a3732b
MT		 3390 if (!*rmapp) {
3391 if (!printk_ratelimit())
3392 return;
3393 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3394 audit_msg, *sptep);
3395 dump_stack();
3396 }
3397 }
3398
3399}
3400
3401void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3402{
3403 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3404}
3405
3406static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3407{
4db35314 3408 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3409 int i;
3410
f05e70ac 3411 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3412 u64 *pt = sp->spt;
37a7d8b0 3413
4db35314 3414 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3415 continue;
3416
3417 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3418 u64 ent = pt[i];
3419
3420 if (!(ent & PT_PRESENT_MASK))
3421 continue;
3422 if (!(ent & PT_WRITABLE_MASK))
3423 continue;
805d32de 3424 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3425 }
3426 }
08a3732b 3427 return;
37a7d8b0
AK		 3428}
3429
3430static void audit_rmap(struct kvm_vcpu *vcpu)
3431{
08a3732b
MT		 3432 check_writable_mappings_rmap(vcpu);
3433 count_rmaps(vcpu);
37a7d8b0
AK		 3434}
3435
3436static void audit_write_protection(struct kvm_vcpu *vcpu)
3437{
4db35314 3438 struct kvm_mmu_page *sp;
290fc38d
IE		 3439 struct kvm_memory_slot *slot;
3440 unsigned long *rmapp;
e58b0f9e 3441 u64 *spte;
290fc38d 3442 gfn_t gfn;
37a7d8b0 3443
f05e70ac 3444 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3445 if (sp->role.direct)
37a7d8b0 3446 continue;
e58b0f9e
MT		 3447 if (sp->unsync)
3448 continue;
37a7d8b0 3449
4db35314 3450 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3451 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3452 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3453
3454 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3455 while (spte) {
3456 if (*spte & PT_WRITABLE_MASK)
3457 printk(KERN_ERR "%s: (%s) shadow page has "
3458 "writable mappings: gfn %lx role %x\n",
b8688d51 3459 __func__, audit_msg, sp->gfn,
4db35314 3460 sp->role.word);
e58b0f9e
MT		 3461 spte = rmap_next(vcpu->kvm, rmapp, spte);
3462 }
37a7d8b0
AK		 3463 }
3464}
3465
3466static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3467{
3468 int olddbg = dbg;
3469
3470 dbg = 0;
3471 audit_msg = msg;
3472 audit_rmap(vcpu);
3473 audit_write_protection(vcpu);
2aaf65e8
MT		 3474 if (strcmp("pre pte write", audit_msg) != 0)
3475 audit_mappings(vcpu);
08a3732b 3476 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3477 dbg = olddbg;
3478}
3479
3480#endif
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