]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 113 | |
6aa8b732 AK |
114 | #define PT64_INDEX(address, level)\ |
115 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
118 | #define PT32_LEVEL_BITS 10 | |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
27aba766 | 131 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
132 | #define PT64_DIR_BASE_ADDR_MASK \ |
133 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT64_LVL_ADDR_MASK(level) \ |
135 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT64_LEVEL_BITS))) - 1)) | |
137 | #define PT64_LVL_OFFSET_MASK(level) \ | |
138 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
140 | |
141 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
142 | #define PT32_DIR_BASE_ADDR_MASK \ | |
143 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
144 | #define PT32_LVL_ADDR_MASK(level) \ |
145 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
146 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 147 | |
79539cec AK |
148 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
149 | | PT64_NX_MASK) | |
6aa8b732 | 150 | |
53c07b18 | 151 | #define PTE_LIST_EXT 4 |
cd4a4e53 | 152 | |
fe135d2c AK |
153 | #define ACC_EXEC_MASK 1 |
154 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
155 | #define ACC_USER_MASK PT_USER_MASK | |
156 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
157 | ||
90bb6fc5 AK |
158 | #include <trace/events/kvm.h> |
159 | ||
07420171 AK |
160 | #define CREATE_TRACE_POINTS |
161 | #include "mmutrace.h" | |
162 | ||
1403283a IE |
163 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
164 | ||
135f8c2b AK |
165 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
166 | ||
53c07b18 XG |
167 | struct pte_list_desc { |
168 | u64 *sptes[PTE_LIST_EXT]; | |
169 | struct pte_list_desc *more; | |
cd4a4e53 AK |
170 | }; |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
175 | int level; | |
176 | u64 *sptep; | |
177 | unsigned index; | |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
53c07b18 | 185 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 186 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 187 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 188 | |
7b52345e SY |
189 | static u64 __read_mostly shadow_nx_mask; |
190 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
191 | static u64 __read_mostly shadow_user_mask; | |
192 | static u64 __read_mostly shadow_accessed_mask; | |
193 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 194 | |
82725b20 DE |
195 | static inline u64 rsvd_bits(int s, int e) |
196 | { | |
197 | return ((1ULL << (e - s + 1)) - 1) << s; | |
198 | } | |
199 | ||
7b52345e | 200 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 201 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
202 | { |
203 | shadow_user_mask = user_mask; | |
204 | shadow_accessed_mask = accessed_mask; | |
205 | shadow_dirty_mask = dirty_mask; | |
206 | shadow_nx_mask = nx_mask; | |
207 | shadow_x_mask = x_mask; | |
208 | } | |
209 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
210 | ||
6aa8b732 AK |
211 | static int is_cpuid_PSE36(void) |
212 | { | |
213 | return 1; | |
214 | } | |
215 | ||
73b1087e AK |
216 | static int is_nx(struct kvm_vcpu *vcpu) |
217 | { | |
f6801dff | 218 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
219 | } |
220 | ||
c7addb90 AK |
221 | static int is_shadow_present_pte(u64 pte) |
222 | { | |
c3707958 | 223 | return pte & PT_PRESENT_MASK; |
c7addb90 AK |
224 | } |
225 | ||
05da4558 MT |
226 | static int is_large_pte(u64 pte) |
227 | { | |
228 | return pte & PT_PAGE_SIZE_MASK; | |
229 | } | |
230 | ||
43a3795a | 231 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 232 | { |
439e218a | 233 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
234 | } |
235 | ||
43a3795a | 236 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 237 | { |
4b1a80fa | 238 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
239 | } |
240 | ||
776e6633 MT |
241 | static int is_last_spte(u64 pte, int level) |
242 | { | |
243 | if (level == PT_PAGE_TABLE_LEVEL) | |
244 | return 1; | |
852e3c19 | 245 | if (is_large_pte(pte)) |
776e6633 MT |
246 | return 1; |
247 | return 0; | |
248 | } | |
249 | ||
35149e21 | 250 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 251 | { |
35149e21 | 252 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
253 | } |
254 | ||
da928521 AK |
255 | static gfn_t pse36_gfn_delta(u32 gpte) |
256 | { | |
257 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
258 | ||
259 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
260 | } | |
261 | ||
d555c333 | 262 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 263 | { |
7645e432 | 264 | set_64bit(sptep, spte); |
e663ee64 AK |
265 | } |
266 | ||
a9221dd5 AK |
267 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
268 | { | |
269 | #ifdef CONFIG_X86_64 | |
270 | return xchg(sptep, new_spte); | |
271 | #else | |
272 | u64 old_spte; | |
273 | ||
274 | do { | |
275 | old_spte = *sptep; | |
276 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
277 | ||
278 | return old_spte; | |
279 | #endif | |
280 | } | |
281 | ||
8672b721 XG |
282 | static bool spte_has_volatile_bits(u64 spte) |
283 | { | |
284 | if (!shadow_accessed_mask) | |
285 | return false; | |
286 | ||
287 | if (!is_shadow_present_pte(spte)) | |
288 | return false; | |
289 | ||
4132779b XG |
290 | if ((spte & shadow_accessed_mask) && |
291 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
292 | return false; |
293 | ||
294 | return true; | |
295 | } | |
296 | ||
4132779b XG |
297 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
298 | { | |
299 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
300 | } | |
301 | ||
1df9f2dc XG |
302 | /* Rules for using mmu_spte_set: |
303 | * Set the sptep from nonpresent to present. | |
304 | * Note: the sptep being assigned *must* be either not present | |
305 | * or in a state where the hardware will not attempt to update | |
306 | * the spte. | |
307 | */ | |
308 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
309 | { | |
310 | WARN_ON(is_shadow_present_pte(*sptep)); | |
311 | __set_spte(sptep, new_spte); | |
312 | } | |
313 | ||
314 | /* Rules for using mmu_spte_update: | |
315 | * Update the state bits, it means the mapped pfn is not changged. | |
316 | */ | |
317 | static void mmu_spte_update(u64 *sptep, u64 new_spte) | |
b79b93f9 | 318 | { |
4132779b XG |
319 | u64 mask, old_spte = *sptep; |
320 | ||
321 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 322 | |
1df9f2dc XG |
323 | if (!is_shadow_present_pte(old_spte)) |
324 | return mmu_spte_set(sptep, new_spte); | |
325 | ||
4132779b XG |
326 | new_spte |= old_spte & shadow_dirty_mask; |
327 | ||
328 | mask = shadow_accessed_mask; | |
329 | if (is_writable_pte(old_spte)) | |
330 | mask |= shadow_dirty_mask; | |
331 | ||
332 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 333 | __set_spte(sptep, new_spte); |
4132779b | 334 | else |
b79b93f9 | 335 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
336 | |
337 | if (!shadow_accessed_mask) | |
338 | return; | |
339 | ||
340 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
341 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
342 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
343 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
344 | } |
345 | ||
1df9f2dc XG |
346 | /* |
347 | * Rules for using mmu_spte_clear_track_bits: | |
348 | * It sets the sptep from present to nonpresent, and track the | |
349 | * state bits, it is used to clear the last level sptep. | |
350 | */ | |
351 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
352 | { | |
353 | pfn_t pfn; | |
354 | u64 old_spte = *sptep; | |
355 | ||
356 | if (!spte_has_volatile_bits(old_spte)) | |
357 | __set_spte(sptep, 0ull); | |
358 | else | |
359 | old_spte = __xchg_spte(sptep, 0ull); | |
360 | ||
361 | if (!is_rmap_spte(old_spte)) | |
362 | return 0; | |
363 | ||
364 | pfn = spte_to_pfn(old_spte); | |
365 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) | |
366 | kvm_set_pfn_accessed(pfn); | |
367 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
368 | kvm_set_pfn_dirty(pfn); | |
369 | return 1; | |
370 | } | |
371 | ||
372 | /* | |
373 | * Rules for using mmu_spte_clear_no_track: | |
374 | * Directly clear spte without caring the state bits of sptep, | |
375 | * it is used to set the upper level spte. | |
376 | */ | |
377 | static void mmu_spte_clear_no_track(u64 *sptep) | |
378 | { | |
379 | __set_spte(sptep, 0ull); | |
380 | } | |
381 | ||
e2dec939 | 382 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 383 | struct kmem_cache *base_cache, int min) |
714b93da AK |
384 | { |
385 | void *obj; | |
386 | ||
387 | if (cache->nobjs >= min) | |
e2dec939 | 388 | return 0; |
714b93da | 389 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 390 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 391 | if (!obj) |
e2dec939 | 392 | return -ENOMEM; |
714b93da AK |
393 | cache->objects[cache->nobjs++] = obj; |
394 | } | |
e2dec939 | 395 | return 0; |
714b93da AK |
396 | } |
397 | ||
e8ad9a70 XG |
398 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
399 | struct kmem_cache *cache) | |
714b93da AK |
400 | { |
401 | while (mc->nobjs) | |
e8ad9a70 | 402 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
403 | } |
404 | ||
c1158e63 | 405 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 406 | int min) |
c1158e63 | 407 | { |
842f22ed | 408 | void *page; |
c1158e63 AK |
409 | |
410 | if (cache->nobjs >= min) | |
411 | return 0; | |
412 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 413 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
414 | if (!page) |
415 | return -ENOMEM; | |
842f22ed | 416 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
417 | } |
418 | return 0; | |
419 | } | |
420 | ||
421 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
422 | { | |
423 | while (mc->nobjs) | |
c4d198d5 | 424 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
425 | } |
426 | ||
2e3e5882 | 427 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 428 | { |
e2dec939 AK |
429 | int r; |
430 | ||
53c07b18 | 431 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 432 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
433 | if (r) |
434 | goto out; | |
ad312c7c | 435 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
436 | if (r) |
437 | goto out; | |
ad312c7c | 438 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 439 | mmu_page_header_cache, 4); |
e2dec939 AK |
440 | out: |
441 | return r; | |
714b93da AK |
442 | } |
443 | ||
444 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
445 | { | |
53c07b18 XG |
446 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
447 | pte_list_desc_cache); | |
ad312c7c | 448 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
449 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
450 | mmu_page_header_cache); | |
714b93da AK |
451 | } |
452 | ||
453 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
454 | size_t size) | |
455 | { | |
456 | void *p; | |
457 | ||
458 | BUG_ON(!mc->nobjs); | |
459 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
460 | return p; |
461 | } | |
462 | ||
53c07b18 | 463 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 464 | { |
53c07b18 XG |
465 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
466 | sizeof(struct pte_list_desc)); | |
714b93da AK |
467 | } |
468 | ||
53c07b18 | 469 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 470 | { |
53c07b18 | 471 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
472 | } |
473 | ||
2032a93d LJ |
474 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
475 | { | |
476 | if (!sp->role.direct) | |
477 | return sp->gfns[index]; | |
478 | ||
479 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
480 | } | |
481 | ||
482 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
483 | { | |
484 | if (sp->role.direct) | |
485 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
486 | else | |
487 | sp->gfns[index] = gfn; | |
488 | } | |
489 | ||
05da4558 | 490 | /* |
d4dbf470 TY |
491 | * Return the pointer to the large page information for a given gfn, |
492 | * handling slots that are not large page aligned. | |
05da4558 | 493 | */ |
d4dbf470 TY |
494 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
495 | struct kvm_memory_slot *slot, | |
496 | int level) | |
05da4558 MT |
497 | { |
498 | unsigned long idx; | |
499 | ||
82855413 JR |
500 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
501 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d4dbf470 | 502 | return &slot->lpage_info[level - 2][idx]; |
05da4558 MT |
503 | } |
504 | ||
505 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
506 | { | |
d25797b2 | 507 | struct kvm_memory_slot *slot; |
d4dbf470 | 508 | struct kvm_lpage_info *linfo; |
d25797b2 | 509 | int i; |
05da4558 | 510 | |
a1f4d395 | 511 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
512 | for (i = PT_DIRECTORY_LEVEL; |
513 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
514 | linfo = lpage_info_slot(gfn, slot, i); |
515 | linfo->write_count += 1; | |
d25797b2 | 516 | } |
332b207d | 517 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
518 | } |
519 | ||
520 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
521 | { | |
d25797b2 | 522 | struct kvm_memory_slot *slot; |
d4dbf470 | 523 | struct kvm_lpage_info *linfo; |
d25797b2 | 524 | int i; |
05da4558 | 525 | |
a1f4d395 | 526 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
527 | for (i = PT_DIRECTORY_LEVEL; |
528 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
529 | linfo = lpage_info_slot(gfn, slot, i); |
530 | linfo->write_count -= 1; | |
531 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 532 | } |
332b207d | 533 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
534 | } |
535 | ||
d25797b2 JR |
536 | static int has_wrprotected_page(struct kvm *kvm, |
537 | gfn_t gfn, | |
538 | int level) | |
05da4558 | 539 | { |
2843099f | 540 | struct kvm_memory_slot *slot; |
d4dbf470 | 541 | struct kvm_lpage_info *linfo; |
05da4558 | 542 | |
a1f4d395 | 543 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 544 | if (slot) { |
d4dbf470 TY |
545 | linfo = lpage_info_slot(gfn, slot, level); |
546 | return linfo->write_count; | |
05da4558 MT |
547 | } |
548 | ||
549 | return 1; | |
550 | } | |
551 | ||
d25797b2 | 552 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 553 | { |
8f0b1ab6 | 554 | unsigned long page_size; |
d25797b2 | 555 | int i, ret = 0; |
05da4558 | 556 | |
8f0b1ab6 | 557 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 558 | |
d25797b2 JR |
559 | for (i = PT_PAGE_TABLE_LEVEL; |
560 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
561 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
562 | ret = i; | |
563 | else | |
564 | break; | |
565 | } | |
566 | ||
4c2155ce | 567 | return ret; |
05da4558 MT |
568 | } |
569 | ||
5d163b1c XG |
570 | static struct kvm_memory_slot * |
571 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
572 | bool no_dirty_log) | |
05da4558 MT |
573 | { |
574 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
575 | |
576 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
577 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
578 | (no_dirty_log && slot->dirty_bitmap)) | |
579 | slot = NULL; | |
580 | ||
581 | return slot; | |
582 | } | |
583 | ||
584 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
585 | { | |
a0a8eaba | 586 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
587 | } |
588 | ||
589 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
590 | { | |
591 | int host_level, level, max_level; | |
05da4558 | 592 | |
d25797b2 JR |
593 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
594 | ||
595 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
596 | return host_level; | |
597 | ||
878403b7 SY |
598 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
599 | kvm_x86_ops->get_lpage_level() : host_level; | |
600 | ||
601 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
602 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
603 | break; | |
d25797b2 JR |
604 | |
605 | return level - 1; | |
05da4558 MT |
606 | } |
607 | ||
290fc38d | 608 | /* |
53c07b18 | 609 | * Pte mapping structures: |
cd4a4e53 | 610 | * |
53c07b18 | 611 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 612 | * |
53c07b18 XG |
613 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
614 | * pte_list_desc containing more mappings. | |
53a27b39 | 615 | * |
53c07b18 | 616 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
617 | * the spte was not added. |
618 | * | |
cd4a4e53 | 619 | */ |
53c07b18 XG |
620 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
621 | unsigned long *pte_list) | |
cd4a4e53 | 622 | { |
53c07b18 | 623 | struct pte_list_desc *desc; |
53a27b39 | 624 | int i, count = 0; |
cd4a4e53 | 625 | |
53c07b18 XG |
626 | if (!*pte_list) { |
627 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
628 | *pte_list = (unsigned long)spte; | |
629 | } else if (!(*pte_list & 1)) { | |
630 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
631 | desc = mmu_alloc_pte_list_desc(vcpu); | |
632 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 633 | desc->sptes[1] = spte; |
53c07b18 | 634 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 635 | ++count; |
cd4a4e53 | 636 | } else { |
53c07b18 XG |
637 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
638 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
639 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 640 | desc = desc->more; |
53c07b18 | 641 | count += PTE_LIST_EXT; |
53a27b39 | 642 | } |
53c07b18 XG |
643 | if (desc->sptes[PTE_LIST_EXT-1]) { |
644 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
645 | desc = desc->more; |
646 | } | |
d555c333 | 647 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 648 | ++count; |
d555c333 | 649 | desc->sptes[i] = spte; |
cd4a4e53 | 650 | } |
53a27b39 | 651 | return count; |
cd4a4e53 AK |
652 | } |
653 | ||
53c07b18 XG |
654 | static u64 *pte_list_next(unsigned long *pte_list, u64 *spte) |
655 | { | |
656 | struct pte_list_desc *desc; | |
657 | u64 *prev_spte; | |
658 | int i; | |
659 | ||
660 | if (!*pte_list) | |
661 | return NULL; | |
662 | else if (!(*pte_list & 1)) { | |
663 | if (!spte) | |
664 | return (u64 *)*pte_list; | |
665 | return NULL; | |
666 | } | |
667 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
668 | prev_spte = NULL; | |
669 | while (desc) { | |
670 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { | |
671 | if (prev_spte == spte) | |
672 | return desc->sptes[i]; | |
673 | prev_spte = desc->sptes[i]; | |
674 | } | |
675 | desc = desc->more; | |
676 | } | |
677 | return NULL; | |
678 | } | |
679 | ||
680 | static void | |
681 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
682 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
683 | { |
684 | int j; | |
685 | ||
53c07b18 | 686 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 687 | ; |
d555c333 AK |
688 | desc->sptes[i] = desc->sptes[j]; |
689 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
690 | if (j != 0) |
691 | return; | |
692 | if (!prev_desc && !desc->more) | |
53c07b18 | 693 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
694 | else |
695 | if (prev_desc) | |
696 | prev_desc->more = desc->more; | |
697 | else | |
53c07b18 XG |
698 | *pte_list = (unsigned long)desc->more | 1; |
699 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
700 | } |
701 | ||
53c07b18 | 702 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 703 | { |
53c07b18 XG |
704 | struct pte_list_desc *desc; |
705 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
706 | int i; |
707 | ||
53c07b18 XG |
708 | if (!*pte_list) { |
709 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 710 | BUG(); |
53c07b18 XG |
711 | } else if (!(*pte_list & 1)) { |
712 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
713 | if ((u64 *)*pte_list != spte) { | |
714 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
715 | BUG(); |
716 | } | |
53c07b18 | 717 | *pte_list = 0; |
cd4a4e53 | 718 | } else { |
53c07b18 XG |
719 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
720 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
721 | prev_desc = NULL; |
722 | while (desc) { | |
53c07b18 | 723 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 724 | if (desc->sptes[i] == spte) { |
53c07b18 | 725 | pte_list_desc_remove_entry(pte_list, |
714b93da | 726 | desc, i, |
cd4a4e53 AK |
727 | prev_desc); |
728 | return; | |
729 | } | |
730 | prev_desc = desc; | |
731 | desc = desc->more; | |
732 | } | |
53c07b18 | 733 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
734 | BUG(); |
735 | } | |
736 | } | |
737 | ||
67052b35 XG |
738 | typedef void (*pte_list_walk_fn) (u64 *spte); |
739 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
740 | { | |
741 | struct pte_list_desc *desc; | |
742 | int i; | |
743 | ||
744 | if (!*pte_list) | |
745 | return; | |
746 | ||
747 | if (!(*pte_list & 1)) | |
748 | return fn((u64 *)*pte_list); | |
749 | ||
750 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
751 | while (desc) { | |
752 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
753 | fn(desc->sptes[i]); | |
754 | desc = desc->more; | |
755 | } | |
756 | } | |
757 | ||
53c07b18 XG |
758 | /* |
759 | * Take gfn and return the reverse mapping to it. | |
760 | */ | |
761 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
762 | { | |
763 | struct kvm_memory_slot *slot; | |
764 | struct kvm_lpage_info *linfo; | |
765 | ||
766 | slot = gfn_to_memslot(kvm, gfn); | |
767 | if (likely(level == PT_PAGE_TABLE_LEVEL)) | |
768 | return &slot->rmap[gfn - slot->base_gfn]; | |
769 | ||
770 | linfo = lpage_info_slot(gfn, slot, level); | |
771 | ||
772 | return &linfo->rmap_pde; | |
773 | } | |
774 | ||
775 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) | |
776 | { | |
777 | struct kvm_mmu_page *sp; | |
778 | unsigned long *rmapp; | |
779 | ||
53c07b18 XG |
780 | sp = page_header(__pa(spte)); |
781 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
782 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
783 | return pte_list_add(vcpu, spte, rmapp); | |
784 | } | |
785 | ||
786 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) | |
787 | { | |
788 | return pte_list_next(rmapp, spte); | |
789 | } | |
790 | ||
791 | static void rmap_remove(struct kvm *kvm, u64 *spte) | |
792 | { | |
793 | struct kvm_mmu_page *sp; | |
794 | gfn_t gfn; | |
795 | unsigned long *rmapp; | |
796 | ||
797 | sp = page_header(__pa(spte)); | |
798 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
799 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
800 | pte_list_remove(spte, rmapp); | |
801 | } | |
802 | ||
c3707958 | 803 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 804 | { |
1df9f2dc | 805 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 806 | rmap_remove(kvm, sptep); |
be38d276 AK |
807 | } |
808 | ||
b1a36821 | 809 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 810 | { |
290fc38d | 811 | unsigned long *rmapp; |
374cbac0 | 812 | u64 *spte; |
44ad9944 | 813 | int i, write_protected = 0; |
374cbac0 | 814 | |
44ad9944 | 815 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 816 | |
98348e95 IE |
817 | spte = rmap_next(kvm, rmapp, NULL); |
818 | while (spte) { | |
374cbac0 | 819 | BUG_ON(!spte); |
374cbac0 | 820 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 821 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 822 | if (is_writable_pte(*spte)) { |
1df9f2dc | 823 | mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
824 | write_protected = 1; |
825 | } | |
9647c14c | 826 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 827 | } |
855149aa | 828 | |
05da4558 | 829 | /* check for huge page mappings */ |
44ad9944 JR |
830 | for (i = PT_DIRECTORY_LEVEL; |
831 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
832 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
833 | spte = rmap_next(kvm, rmapp, NULL); | |
834 | while (spte) { | |
835 | BUG_ON(!spte); | |
836 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
837 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
838 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 839 | if (is_writable_pte(*spte)) { |
c3707958 | 840 | drop_spte(kvm, spte); |
44ad9944 | 841 | --kvm->stat.lpages; |
44ad9944 JR |
842 | spte = NULL; |
843 | write_protected = 1; | |
844 | } | |
845 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 846 | } |
05da4558 MT |
847 | } |
848 | ||
b1a36821 | 849 | return write_protected; |
374cbac0 AK |
850 | } |
851 | ||
8a8365c5 FD |
852 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
853 | unsigned long data) | |
e930bffe AA |
854 | { |
855 | u64 *spte; | |
856 | int need_tlb_flush = 0; | |
857 | ||
858 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
859 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
860 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
c3707958 | 861 | drop_spte(kvm, spte); |
e930bffe AA |
862 | need_tlb_flush = 1; |
863 | } | |
864 | return need_tlb_flush; | |
865 | } | |
866 | ||
8a8365c5 FD |
867 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
868 | unsigned long data) | |
3da0dd43 IE |
869 | { |
870 | int need_flush = 0; | |
e4b502ea | 871 | u64 *spte, new_spte; |
3da0dd43 IE |
872 | pte_t *ptep = (pte_t *)data; |
873 | pfn_t new_pfn; | |
874 | ||
875 | WARN_ON(pte_huge(*ptep)); | |
876 | new_pfn = pte_pfn(*ptep); | |
877 | spte = rmap_next(kvm, rmapp, NULL); | |
878 | while (spte) { | |
879 | BUG_ON(!is_shadow_present_pte(*spte)); | |
880 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
881 | need_flush = 1; | |
882 | if (pte_write(*ptep)) { | |
c3707958 | 883 | drop_spte(kvm, spte); |
3da0dd43 IE |
884 | spte = rmap_next(kvm, rmapp, NULL); |
885 | } else { | |
886 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
887 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
888 | ||
889 | new_spte &= ~PT_WRITABLE_MASK; | |
890 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 891 | new_spte &= ~shadow_accessed_mask; |
1df9f2dc XG |
892 | mmu_spte_clear_track_bits(spte); |
893 | mmu_spte_set(spte, new_spte); | |
3da0dd43 IE |
894 | spte = rmap_next(kvm, rmapp, spte); |
895 | } | |
896 | } | |
897 | if (need_flush) | |
898 | kvm_flush_remote_tlbs(kvm); | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
8a8365c5 FD |
903 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
904 | unsigned long data, | |
3da0dd43 | 905 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 906 | unsigned long data)) |
e930bffe | 907 | { |
852e3c19 | 908 | int i, j; |
90bb6fc5 | 909 | int ret; |
e930bffe | 910 | int retval = 0; |
bc6678a3 MT |
911 | struct kvm_memslots *slots; |
912 | ||
90d83dc3 | 913 | slots = kvm_memslots(kvm); |
e930bffe | 914 | |
46a26bf5 MT |
915 | for (i = 0; i < slots->nmemslots; i++) { |
916 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
917 | unsigned long start = memslot->userspace_addr; |
918 | unsigned long end; | |
919 | ||
e930bffe AA |
920 | end = start + (memslot->npages << PAGE_SHIFT); |
921 | if (hva >= start && hva < end) { | |
922 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 923 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 924 | |
90bb6fc5 | 925 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
926 | |
927 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
928 | struct kvm_lpage_info *linfo; |
929 | ||
930 | linfo = lpage_info_slot(gfn, memslot, | |
931 | PT_DIRECTORY_LEVEL + j); | |
932 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 933 | } |
90bb6fc5 AK |
934 | trace_kvm_age_page(hva, memslot, ret); |
935 | retval |= ret; | |
e930bffe AA |
936 | } |
937 | } | |
938 | ||
939 | return retval; | |
940 | } | |
941 | ||
942 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
943 | { | |
3da0dd43 IE |
944 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
945 | } | |
946 | ||
947 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
948 | { | |
8a8365c5 | 949 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
950 | } |
951 | ||
8a8365c5 FD |
952 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
953 | unsigned long data) | |
e930bffe AA |
954 | { |
955 | u64 *spte; | |
956 | int young = 0; | |
957 | ||
6316e1c8 RR |
958 | /* |
959 | * Emulate the accessed bit for EPT, by checking if this page has | |
960 | * an EPT mapping, and clearing it if it does. On the next access, | |
961 | * a new EPT mapping will be established. | |
962 | * This has some overhead, but not as much as the cost of swapping | |
963 | * out actively used pages or breaking up actively used hugepages. | |
964 | */ | |
534e38b4 | 965 | if (!shadow_accessed_mask) |
6316e1c8 | 966 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 967 | |
e930bffe AA |
968 | spte = rmap_next(kvm, rmapp, NULL); |
969 | while (spte) { | |
970 | int _young; | |
971 | u64 _spte = *spte; | |
972 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
973 | _young = _spte & PT_ACCESSED_MASK; | |
974 | if (_young) { | |
975 | young = 1; | |
976 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
977 | } | |
978 | spte = rmap_next(kvm, rmapp, spte); | |
979 | } | |
980 | return young; | |
981 | } | |
982 | ||
8ee53820 AA |
983 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
984 | unsigned long data) | |
985 | { | |
986 | u64 *spte; | |
987 | int young = 0; | |
988 | ||
989 | /* | |
990 | * If there's no access bit in the secondary pte set by the | |
991 | * hardware it's up to gup-fast/gup to set the access bit in | |
992 | * the primary pte or in the page structure. | |
993 | */ | |
994 | if (!shadow_accessed_mask) | |
995 | goto out; | |
996 | ||
997 | spte = rmap_next(kvm, rmapp, NULL); | |
998 | while (spte) { | |
999 | u64 _spte = *spte; | |
1000 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
1001 | young = _spte & PT_ACCESSED_MASK; | |
1002 | if (young) { | |
1003 | young = 1; | |
1004 | break; | |
1005 | } | |
1006 | spte = rmap_next(kvm, rmapp, spte); | |
1007 | } | |
1008 | out: | |
1009 | return young; | |
1010 | } | |
1011 | ||
53a27b39 MT |
1012 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1013 | ||
852e3c19 | 1014 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1015 | { |
1016 | unsigned long *rmapp; | |
852e3c19 JR |
1017 | struct kvm_mmu_page *sp; |
1018 | ||
1019 | sp = page_header(__pa(spte)); | |
53a27b39 | 1020 | |
852e3c19 | 1021 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1022 | |
3da0dd43 | 1023 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1024 | kvm_flush_remote_tlbs(vcpu->kvm); |
1025 | } | |
1026 | ||
e930bffe AA |
1027 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1028 | { | |
3da0dd43 | 1029 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1030 | } |
1031 | ||
8ee53820 AA |
1032 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1033 | { | |
1034 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1035 | } | |
1036 | ||
d6c69ee9 | 1037 | #ifdef MMU_DEBUG |
47ad8e68 | 1038 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1039 | { |
139bdb2d AK |
1040 | u64 *pos; |
1041 | u64 *end; | |
1042 | ||
47ad8e68 | 1043 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1044 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1045 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1046 | pos, *pos); |
6aa8b732 | 1047 | return 0; |
139bdb2d | 1048 | } |
6aa8b732 AK |
1049 | return 1; |
1050 | } | |
d6c69ee9 | 1051 | #endif |
6aa8b732 | 1052 | |
45221ab6 DH |
1053 | /* |
1054 | * This value is the sum of all of the kvm instances's | |
1055 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1056 | * aggregate version in order to make the slab shrinker | |
1057 | * faster | |
1058 | */ | |
1059 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1060 | { | |
1061 | kvm->arch.n_used_mmu_pages += nr; | |
1062 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1063 | } | |
1064 | ||
bd4c86ea XG |
1065 | /* |
1066 | * Remove the sp from shadow page cache, after call it, | |
1067 | * we can not find this sp from the cache, and the shadow | |
1068 | * page table is still valid. | |
1069 | * It should be under the protection of mmu lock. | |
1070 | */ | |
1071 | static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp) | |
260746c0 | 1072 | { |
4db35314 | 1073 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1074 | hlist_del(&sp->hash_link); |
2032a93d | 1075 | if (!sp->role.direct) |
842f22ed | 1076 | free_page((unsigned long)sp->gfns); |
bd4c86ea XG |
1077 | } |
1078 | ||
1079 | /* | |
1080 | * Free the shadow page table and the sp, we can do it | |
1081 | * out of the protection of mmu lock. | |
1082 | */ | |
1083 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) | |
1084 | { | |
1085 | list_del(&sp->link); | |
1086 | free_page((unsigned long)sp->spt); | |
e8ad9a70 | 1087 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1088 | } |
1089 | ||
cea0f0e7 AK |
1090 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1091 | { | |
1ae0a13d | 1092 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1093 | } |
1094 | ||
714b93da | 1095 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1096 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1097 | { |
cea0f0e7 AK |
1098 | if (!parent_pte) |
1099 | return; | |
cea0f0e7 | 1100 | |
67052b35 | 1101 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1102 | } |
1103 | ||
4db35314 | 1104 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1105 | u64 *parent_pte) |
1106 | { | |
67052b35 | 1107 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1108 | } |
1109 | ||
bcdd9a93 XG |
1110 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1111 | u64 *parent_pte) | |
1112 | { | |
1113 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1114 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1115 | } |
1116 | ||
67052b35 XG |
1117 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1118 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1119 | { |
67052b35 XG |
1120 | struct kvm_mmu_page *sp; |
1121 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, | |
1122 | sizeof *sp); | |
1123 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
1124 | if (!direct) | |
1125 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1126 | PAGE_SIZE); | |
1127 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); | |
1128 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
1129 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); | |
1130 | sp->parent_ptes = 0; | |
1131 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1132 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1133 | return sp; | |
ad8cfbe3 MT |
1134 | } |
1135 | ||
67052b35 | 1136 | static void mark_unsync(u64 *spte); |
1047df1f | 1137 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1138 | { |
67052b35 | 1139 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1140 | } |
1141 | ||
67052b35 | 1142 | static void mark_unsync(u64 *spte) |
0074ff63 | 1143 | { |
67052b35 | 1144 | struct kvm_mmu_page *sp; |
1047df1f | 1145 | unsigned int index; |
0074ff63 | 1146 | |
67052b35 | 1147 | sp = page_header(__pa(spte)); |
1047df1f XG |
1148 | index = spte - sp->spt; |
1149 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1150 | return; |
1047df1f | 1151 | if (sp->unsync_children++) |
0074ff63 | 1152 | return; |
1047df1f | 1153 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1154 | } |
1155 | ||
e8bc217a | 1156 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1157 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1158 | { |
1159 | return 1; | |
1160 | } | |
1161 | ||
a7052897 MT |
1162 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1163 | { | |
1164 | } | |
1165 | ||
0f53b5b1 XG |
1166 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1167 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1168 | const void *pte) |
0f53b5b1 XG |
1169 | { |
1170 | WARN_ON(1); | |
1171 | } | |
1172 | ||
60c8aec6 MT |
1173 | #define KVM_PAGE_ARRAY_NR 16 |
1174 | ||
1175 | struct kvm_mmu_pages { | |
1176 | struct mmu_page_and_offset { | |
1177 | struct kvm_mmu_page *sp; | |
1178 | unsigned int idx; | |
1179 | } page[KVM_PAGE_ARRAY_NR]; | |
1180 | unsigned int nr; | |
1181 | }; | |
1182 | ||
0074ff63 MT |
1183 | #define for_each_unsync_children(bitmap, idx) \ |
1184 | for (idx = find_first_bit(bitmap, 512); \ | |
1185 | idx < 512; \ | |
1186 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1187 | ||
cded19f3 HE |
1188 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1189 | int idx) | |
4731d4c7 | 1190 | { |
60c8aec6 | 1191 | int i; |
4731d4c7 | 1192 | |
60c8aec6 MT |
1193 | if (sp->unsync) |
1194 | for (i=0; i < pvec->nr; i++) | |
1195 | if (pvec->page[i].sp == sp) | |
1196 | return 0; | |
1197 | ||
1198 | pvec->page[pvec->nr].sp = sp; | |
1199 | pvec->page[pvec->nr].idx = idx; | |
1200 | pvec->nr++; | |
1201 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1202 | } | |
1203 | ||
1204 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1205 | struct kvm_mmu_pages *pvec) | |
1206 | { | |
1207 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1208 | |
0074ff63 | 1209 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1210 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1211 | u64 ent = sp->spt[i]; |
1212 | ||
7a8f1a74 XG |
1213 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1214 | goto clear_child_bitmap; | |
1215 | ||
1216 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1217 | ||
1218 | if (child->unsync_children) { | |
1219 | if (mmu_pages_add(pvec, child, i)) | |
1220 | return -ENOSPC; | |
1221 | ||
1222 | ret = __mmu_unsync_walk(child, pvec); | |
1223 | if (!ret) | |
1224 | goto clear_child_bitmap; | |
1225 | else if (ret > 0) | |
1226 | nr_unsync_leaf += ret; | |
1227 | else | |
1228 | return ret; | |
1229 | } else if (child->unsync) { | |
1230 | nr_unsync_leaf++; | |
1231 | if (mmu_pages_add(pvec, child, i)) | |
1232 | return -ENOSPC; | |
1233 | } else | |
1234 | goto clear_child_bitmap; | |
1235 | ||
1236 | continue; | |
1237 | ||
1238 | clear_child_bitmap: | |
1239 | __clear_bit(i, sp->unsync_child_bitmap); | |
1240 | sp->unsync_children--; | |
1241 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1242 | } |
1243 | ||
4731d4c7 | 1244 | |
60c8aec6 MT |
1245 | return nr_unsync_leaf; |
1246 | } | |
1247 | ||
1248 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1249 | struct kvm_mmu_pages *pvec) | |
1250 | { | |
1251 | if (!sp->unsync_children) | |
1252 | return 0; | |
1253 | ||
1254 | mmu_pages_add(pvec, sp, 0); | |
1255 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1256 | } |
1257 | ||
4731d4c7 MT |
1258 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1259 | { | |
1260 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1261 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1262 | sp->unsync = 0; |
1263 | --kvm->stat.mmu_unsync; | |
1264 | } | |
1265 | ||
7775834a XG |
1266 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1267 | struct list_head *invalid_list); | |
1268 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1269 | struct list_head *invalid_list); | |
4731d4c7 | 1270 | |
f41d335a XG |
1271 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1272 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1273 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1274 | if ((sp)->gfn != (gfn)) {} else | |
1275 | ||
f41d335a XG |
1276 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1277 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1278 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1279 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1280 | (sp)->role.invalid) {} else | |
1281 | ||
f918b443 | 1282 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1283 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1284 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1285 | { |
5b7e0102 | 1286 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1287 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1288 | return 1; |
1289 | } | |
1290 | ||
f918b443 | 1291 | if (clear_unsync) |
1d9dc7e0 | 1292 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1293 | |
a4a8e6f7 | 1294 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1295 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1296 | return 1; |
1297 | } | |
1298 | ||
1299 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1300 | return 0; |
1301 | } | |
1302 | ||
1d9dc7e0 XG |
1303 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1304 | struct kvm_mmu_page *sp) | |
1305 | { | |
d98ba053 | 1306 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1307 | int ret; |
1308 | ||
d98ba053 | 1309 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1310 | if (ret) |
d98ba053 XG |
1311 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1312 | ||
1d9dc7e0 XG |
1313 | return ret; |
1314 | } | |
1315 | ||
d98ba053 XG |
1316 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1317 | struct list_head *invalid_list) | |
1d9dc7e0 | 1318 | { |
d98ba053 | 1319 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1320 | } |
1321 | ||
9f1a122f XG |
1322 | /* @gfn should be write-protected at the call site */ |
1323 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1324 | { | |
9f1a122f | 1325 | struct kvm_mmu_page *s; |
f41d335a | 1326 | struct hlist_node *node; |
d98ba053 | 1327 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1328 | bool flush = false; |
1329 | ||
f41d335a | 1330 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1331 | if (!s->unsync) |
9f1a122f XG |
1332 | continue; |
1333 | ||
1334 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1335 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1336 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1337 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1338 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1339 | continue; |
1340 | } | |
9f1a122f XG |
1341 | flush = true; |
1342 | } | |
1343 | ||
d98ba053 | 1344 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1345 | if (flush) |
1346 | kvm_mmu_flush_tlb(vcpu); | |
1347 | } | |
1348 | ||
60c8aec6 MT |
1349 | struct mmu_page_path { |
1350 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1351 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1352 | }; |
1353 | ||
60c8aec6 MT |
1354 | #define for_each_sp(pvec, sp, parents, i) \ |
1355 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1356 | sp = pvec.page[i].sp; \ | |
1357 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1358 | i = mmu_pages_next(&pvec, &parents, i)) | |
1359 | ||
cded19f3 HE |
1360 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1361 | struct mmu_page_path *parents, | |
1362 | int i) | |
60c8aec6 MT |
1363 | { |
1364 | int n; | |
1365 | ||
1366 | for (n = i+1; n < pvec->nr; n++) { | |
1367 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1368 | ||
1369 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1370 | parents->idx[0] = pvec->page[n].idx; | |
1371 | return n; | |
1372 | } | |
1373 | ||
1374 | parents->parent[sp->role.level-2] = sp; | |
1375 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1376 | } | |
1377 | ||
1378 | return n; | |
1379 | } | |
1380 | ||
cded19f3 | 1381 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1382 | { |
60c8aec6 MT |
1383 | struct kvm_mmu_page *sp; |
1384 | unsigned int level = 0; | |
1385 | ||
1386 | do { | |
1387 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1388 | |
60c8aec6 MT |
1389 | sp = parents->parent[level]; |
1390 | if (!sp) | |
1391 | return; | |
1392 | ||
1393 | --sp->unsync_children; | |
1394 | WARN_ON((int)sp->unsync_children < 0); | |
1395 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1396 | level++; | |
1397 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1398 | } |
1399 | ||
60c8aec6 MT |
1400 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1401 | struct mmu_page_path *parents, | |
1402 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1403 | { |
60c8aec6 MT |
1404 | parents->parent[parent->role.level-1] = NULL; |
1405 | pvec->nr = 0; | |
1406 | } | |
4731d4c7 | 1407 | |
60c8aec6 MT |
1408 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1409 | struct kvm_mmu_page *parent) | |
1410 | { | |
1411 | int i; | |
1412 | struct kvm_mmu_page *sp; | |
1413 | struct mmu_page_path parents; | |
1414 | struct kvm_mmu_pages pages; | |
d98ba053 | 1415 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1416 | |
1417 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1418 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1419 | int protected = 0; |
1420 | ||
1421 | for_each_sp(pages, sp, parents, i) | |
1422 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1423 | ||
1424 | if (protected) | |
1425 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1426 | ||
60c8aec6 | 1427 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1428 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1429 | mmu_pages_clear_parents(&parents); |
1430 | } | |
d98ba053 | 1431 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1432 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1433 | kvm_mmu_pages_init(parent, &parents, &pages); |
1434 | } | |
4731d4c7 MT |
1435 | } |
1436 | ||
c3707958 XG |
1437 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1438 | { | |
1439 | int i; | |
1440 | ||
1441 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1442 | sp->spt[i] = 0ull; | |
1443 | } | |
1444 | ||
cea0f0e7 AK |
1445 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1446 | gfn_t gfn, | |
1447 | gva_t gaddr, | |
1448 | unsigned level, | |
f6e2c02b | 1449 | int direct, |
41074d07 | 1450 | unsigned access, |
f7d9c7b7 | 1451 | u64 *parent_pte) |
cea0f0e7 AK |
1452 | { |
1453 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1454 | unsigned quadrant; |
9f1a122f | 1455 | struct kvm_mmu_page *sp; |
f41d335a | 1456 | struct hlist_node *node; |
9f1a122f | 1457 | bool need_sync = false; |
cea0f0e7 | 1458 | |
a770f6f2 | 1459 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1460 | role.level = level; |
f6e2c02b | 1461 | role.direct = direct; |
84b0c8c6 | 1462 | if (role.direct) |
5b7e0102 | 1463 | role.cr4_pae = 0; |
41074d07 | 1464 | role.access = access; |
c5a78f2b JR |
1465 | if (!vcpu->arch.mmu.direct_map |
1466 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1467 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1468 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1469 | role.quadrant = quadrant; | |
1470 | } | |
f41d335a | 1471 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1472 | if (!need_sync && sp->unsync) |
1473 | need_sync = true; | |
4731d4c7 | 1474 | |
7ae680eb XG |
1475 | if (sp->role.word != role.word) |
1476 | continue; | |
4731d4c7 | 1477 | |
7ae680eb XG |
1478 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1479 | break; | |
e02aa901 | 1480 | |
7ae680eb XG |
1481 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1482 | if (sp->unsync_children) { | |
a8eeb04a | 1483 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1484 | kvm_mmu_mark_parents_unsync(sp); |
1485 | } else if (sp->unsync) | |
1486 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1487 | |
7ae680eb XG |
1488 | trace_kvm_mmu_get_page(sp, false); |
1489 | return sp; | |
1490 | } | |
dfc5aa00 | 1491 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1492 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1493 | if (!sp) |
1494 | return sp; | |
4db35314 AK |
1495 | sp->gfn = gfn; |
1496 | sp->role = role; | |
7ae680eb XG |
1497 | hlist_add_head(&sp->hash_link, |
1498 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1499 | if (!direct) { |
b1a36821 MT |
1500 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1501 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1502 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1503 | kvm_sync_pages(vcpu, gfn); | |
1504 | ||
4731d4c7 MT |
1505 | account_shadowed(vcpu->kvm, gfn); |
1506 | } | |
c3707958 | 1507 | init_shadow_page_table(sp); |
f691fe1d | 1508 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1509 | return sp; |
cea0f0e7 AK |
1510 | } |
1511 | ||
2d11123a AK |
1512 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1513 | struct kvm_vcpu *vcpu, u64 addr) | |
1514 | { | |
1515 | iterator->addr = addr; | |
1516 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1517 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1518 | |
1519 | if (iterator->level == PT64_ROOT_LEVEL && | |
1520 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1521 | !vcpu->arch.mmu.direct_map) | |
1522 | --iterator->level; | |
1523 | ||
2d11123a AK |
1524 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1525 | iterator->shadow_addr | |
1526 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1527 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1528 | --iterator->level; | |
1529 | if (!iterator->shadow_addr) | |
1530 | iterator->level = 0; | |
1531 | } | |
1532 | } | |
1533 | ||
1534 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1535 | { | |
1536 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1537 | return false; | |
4d88954d | 1538 | |
2d11123a AK |
1539 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1540 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1541 | return true; | |
1542 | } | |
1543 | ||
1544 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1545 | { | |
052331be XG |
1546 | if (is_last_spte(*iterator->sptep, iterator->level)) { |
1547 | iterator->level = 0; | |
1548 | return; | |
1549 | } | |
1550 | ||
2d11123a AK |
1551 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; |
1552 | --iterator->level; | |
1553 | } | |
1554 | ||
32ef26a3 AK |
1555 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1556 | { | |
1557 | u64 spte; | |
1558 | ||
1559 | spte = __pa(sp->spt) | |
1560 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1561 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
1df9f2dc | 1562 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1563 | } |
1564 | ||
a3aa51cf AK |
1565 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1566 | { | |
1567 | if (is_large_pte(*sptep)) { | |
c3707958 | 1568 | drop_spte(vcpu->kvm, sptep); |
a3aa51cf AK |
1569 | kvm_flush_remote_tlbs(vcpu->kvm); |
1570 | } | |
1571 | } | |
1572 | ||
a357bd22 AK |
1573 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1574 | unsigned direct_access) | |
1575 | { | |
1576 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1577 | struct kvm_mmu_page *child; | |
1578 | ||
1579 | /* | |
1580 | * For the direct sp, if the guest pte's dirty bit | |
1581 | * changed form clean to dirty, it will corrupt the | |
1582 | * sp's access: allow writable in the read-only sp, | |
1583 | * so we should update the spte at this point to get | |
1584 | * a new sp with the correct access. | |
1585 | */ | |
1586 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1587 | if (child->role.access == direct_access) | |
1588 | return; | |
1589 | ||
bcdd9a93 | 1590 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1591 | kvm_flush_remote_tlbs(vcpu->kvm); |
1592 | } | |
1593 | } | |
1594 | ||
38e3b2b2 XG |
1595 | static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
1596 | u64 *spte) | |
1597 | { | |
1598 | u64 pte; | |
1599 | struct kvm_mmu_page *child; | |
1600 | ||
1601 | pte = *spte; | |
1602 | if (is_shadow_present_pte(pte)) { | |
1603 | if (is_last_spte(pte, sp->role.level)) | |
c3707958 | 1604 | drop_spte(kvm, spte); |
38e3b2b2 XG |
1605 | else { |
1606 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 1607 | drop_parent_pte(child, spte); |
38e3b2b2 XG |
1608 | } |
1609 | } | |
c3707958 | 1610 | |
38e3b2b2 XG |
1611 | if (is_large_pte(pte)) |
1612 | --kvm->stat.lpages; | |
1613 | } | |
1614 | ||
90cb0529 | 1615 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1616 | struct kvm_mmu_page *sp) |
a436036b | 1617 | { |
697fe2e2 | 1618 | unsigned i; |
697fe2e2 | 1619 | |
38e3b2b2 XG |
1620 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1621 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
1622 | } |
1623 | ||
4db35314 | 1624 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1625 | { |
4db35314 | 1626 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1627 | } |
1628 | ||
12b7d28f AK |
1629 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1630 | { | |
1631 | int i; | |
988a2cae | 1632 | struct kvm_vcpu *vcpu; |
12b7d28f | 1633 | |
988a2cae GN |
1634 | kvm_for_each_vcpu(i, vcpu, kvm) |
1635 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1636 | } |
1637 | ||
31aa2b44 | 1638 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1639 | { |
1640 | u64 *parent_pte; | |
1641 | ||
bcdd9a93 XG |
1642 | while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL))) |
1643 | drop_parent_pte(sp, parent_pte); | |
31aa2b44 AK |
1644 | } |
1645 | ||
60c8aec6 | 1646 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1647 | struct kvm_mmu_page *parent, |
1648 | struct list_head *invalid_list) | |
4731d4c7 | 1649 | { |
60c8aec6 MT |
1650 | int i, zapped = 0; |
1651 | struct mmu_page_path parents; | |
1652 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1653 | |
60c8aec6 | 1654 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1655 | return 0; |
60c8aec6 MT |
1656 | |
1657 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1658 | while (mmu_unsync_walk(parent, &pages)) { | |
1659 | struct kvm_mmu_page *sp; | |
1660 | ||
1661 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1662 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1663 | mmu_pages_clear_parents(&parents); |
77662e00 | 1664 | zapped++; |
60c8aec6 | 1665 | } |
60c8aec6 MT |
1666 | kvm_mmu_pages_init(parent, &parents, &pages); |
1667 | } | |
1668 | ||
1669 | return zapped; | |
4731d4c7 MT |
1670 | } |
1671 | ||
7775834a XG |
1672 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1673 | struct list_head *invalid_list) | |
31aa2b44 | 1674 | { |
4731d4c7 | 1675 | int ret; |
f691fe1d | 1676 | |
7775834a | 1677 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1678 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1679 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1680 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1681 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1682 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1683 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1684 | if (sp->unsync) |
1685 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1686 | if (!sp->root_count) { |
54a4f023 GJ |
1687 | /* Count self */ |
1688 | ret++; | |
7775834a | 1689 | list_move(&sp->link, invalid_list); |
aa6bd187 | 1690 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 1691 | } else { |
5b5c6a5a | 1692 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1693 | kvm_reload_remote_mmus(kvm); |
1694 | } | |
7775834a XG |
1695 | |
1696 | sp->role.invalid = 1; | |
12b7d28f | 1697 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1698 | return ret; |
a436036b AK |
1699 | } |
1700 | ||
7775834a XG |
1701 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1702 | struct list_head *invalid_list) | |
1703 | { | |
1704 | struct kvm_mmu_page *sp; | |
1705 | ||
1706 | if (list_empty(invalid_list)) | |
1707 | return; | |
1708 | ||
1709 | kvm_flush_remote_tlbs(kvm); | |
1710 | ||
1711 | do { | |
1712 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1713 | WARN_ON(!sp->role.invalid || sp->root_count); | |
bd4c86ea | 1714 | kvm_mmu_isolate_page(sp); |
aa6bd187 | 1715 | kvm_mmu_free_page(sp); |
7775834a XG |
1716 | } while (!list_empty(invalid_list)); |
1717 | ||
1718 | } | |
1719 | ||
82ce2c96 IE |
1720 | /* |
1721 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1722 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1723 | */ |
49d5ca26 | 1724 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1725 | { |
d98ba053 | 1726 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1727 | /* |
1728 | * If we set the number of mmu pages to be smaller be than the | |
1729 | * number of actived pages , we must to free some mmu pages before we | |
1730 | * change the value | |
1731 | */ | |
1732 | ||
49d5ca26 DH |
1733 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1734 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1735 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1736 | struct kvm_mmu_page *page; |
1737 | ||
f05e70ac | 1738 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1739 | struct kvm_mmu_page, link); |
80b63faf | 1740 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 1741 | } |
aa6bd187 | 1742 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 1743 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1744 | } |
82ce2c96 | 1745 | |
49d5ca26 | 1746 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1747 | } |
1748 | ||
f67a46f4 | 1749 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1750 | { |
4db35314 | 1751 | struct kvm_mmu_page *sp; |
f41d335a | 1752 | struct hlist_node *node; |
d98ba053 | 1753 | LIST_HEAD(invalid_list); |
a436036b AK |
1754 | int r; |
1755 | ||
9ad17b10 | 1756 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1757 | r = 0; |
f41d335a XG |
1758 | |
1759 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1760 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1761 | sp->role.word); |
1762 | r = 1; | |
f41d335a | 1763 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1764 | } |
d98ba053 | 1765 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1766 | return r; |
cea0f0e7 AK |
1767 | } |
1768 | ||
f67a46f4 | 1769 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1770 | { |
4db35314 | 1771 | struct kvm_mmu_page *sp; |
f41d335a | 1772 | struct hlist_node *node; |
d98ba053 | 1773 | LIST_HEAD(invalid_list); |
97a0a01e | 1774 | |
f41d335a | 1775 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1776 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1777 | __func__, gfn, sp->role.word); |
f41d335a | 1778 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1779 | } |
d98ba053 | 1780 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1781 | } |
1782 | ||
38c335f1 | 1783 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1784 | { |
bc6678a3 | 1785 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1786 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1787 | |
291f26bc | 1788 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1789 | } |
1790 | ||
74be52e3 SY |
1791 | /* |
1792 | * The function is based on mtrr_type_lookup() in | |
1793 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1794 | */ | |
1795 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1796 | u64 start, u64 end) | |
1797 | { | |
1798 | int i; | |
1799 | u64 base, mask; | |
1800 | u8 prev_match, curr_match; | |
1801 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1802 | ||
1803 | if (!mtrr_state->enabled) | |
1804 | return 0xFF; | |
1805 | ||
1806 | /* Make end inclusive end, instead of exclusive */ | |
1807 | end--; | |
1808 | ||
1809 | /* Look in fixed ranges. Just return the type as per start */ | |
1810 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1811 | int idx; | |
1812 | ||
1813 | if (start < 0x80000) { | |
1814 | idx = 0; | |
1815 | idx += (start >> 16); | |
1816 | return mtrr_state->fixed_ranges[idx]; | |
1817 | } else if (start < 0xC0000) { | |
1818 | idx = 1 * 8; | |
1819 | idx += ((start - 0x80000) >> 14); | |
1820 | return mtrr_state->fixed_ranges[idx]; | |
1821 | } else if (start < 0x1000000) { | |
1822 | idx = 3 * 8; | |
1823 | idx += ((start - 0xC0000) >> 12); | |
1824 | return mtrr_state->fixed_ranges[idx]; | |
1825 | } | |
1826 | } | |
1827 | ||
1828 | /* | |
1829 | * Look in variable ranges | |
1830 | * Look of multiple ranges matching this address and pick type | |
1831 | * as per MTRR precedence | |
1832 | */ | |
1833 | if (!(mtrr_state->enabled & 2)) | |
1834 | return mtrr_state->def_type; | |
1835 | ||
1836 | prev_match = 0xFF; | |
1837 | for (i = 0; i < num_var_ranges; ++i) { | |
1838 | unsigned short start_state, end_state; | |
1839 | ||
1840 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1841 | continue; | |
1842 | ||
1843 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1844 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1845 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1846 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1847 | ||
1848 | start_state = ((start & mask) == (base & mask)); | |
1849 | end_state = ((end & mask) == (base & mask)); | |
1850 | if (start_state != end_state) | |
1851 | return 0xFE; | |
1852 | ||
1853 | if ((start & mask) != (base & mask)) | |
1854 | continue; | |
1855 | ||
1856 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1857 | if (prev_match == 0xFF) { | |
1858 | prev_match = curr_match; | |
1859 | continue; | |
1860 | } | |
1861 | ||
1862 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1863 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1864 | return MTRR_TYPE_UNCACHABLE; | |
1865 | ||
1866 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1867 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1868 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1869 | curr_match == MTRR_TYPE_WRBACK)) { | |
1870 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1871 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1872 | } | |
1873 | ||
1874 | if (prev_match != curr_match) | |
1875 | return MTRR_TYPE_UNCACHABLE; | |
1876 | } | |
1877 | ||
1878 | if (prev_match != 0xFF) | |
1879 | return prev_match; | |
1880 | ||
1881 | return mtrr_state->def_type; | |
1882 | } | |
1883 | ||
4b12f0de | 1884 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1885 | { |
1886 | u8 mtrr; | |
1887 | ||
1888 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1889 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1890 | if (mtrr == 0xfe || mtrr == 0xff) | |
1891 | mtrr = MTRR_TYPE_WRBACK; | |
1892 | return mtrr; | |
1893 | } | |
4b12f0de | 1894 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1895 | |
9cf5cf5a XG |
1896 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1897 | { | |
1898 | trace_kvm_mmu_unsync_page(sp); | |
1899 | ++vcpu->kvm->stat.mmu_unsync; | |
1900 | sp->unsync = 1; | |
1901 | ||
1902 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
1903 | } |
1904 | ||
1905 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1906 | { |
4731d4c7 | 1907 | struct kvm_mmu_page *s; |
f41d335a | 1908 | struct hlist_node *node; |
9cf5cf5a | 1909 | |
f41d335a | 1910 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1911 | if (s->unsync) |
4731d4c7 | 1912 | continue; |
9cf5cf5a XG |
1913 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1914 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1915 | } |
4731d4c7 MT |
1916 | } |
1917 | ||
1918 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1919 | bool can_unsync) | |
1920 | { | |
9cf5cf5a | 1921 | struct kvm_mmu_page *s; |
f41d335a | 1922 | struct hlist_node *node; |
9cf5cf5a XG |
1923 | bool need_unsync = false; |
1924 | ||
f41d335a | 1925 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1926 | if (!can_unsync) |
1927 | return 1; | |
1928 | ||
9cf5cf5a | 1929 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1930 | return 1; |
9cf5cf5a XG |
1931 | |
1932 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1933 | if (!oos_shadow) |
9cf5cf5a XG |
1934 | return 1; |
1935 | need_unsync = true; | |
1936 | } | |
4731d4c7 | 1937 | } |
9cf5cf5a XG |
1938 | if (need_unsync) |
1939 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1940 | return 0; |
1941 | } | |
1942 | ||
d555c333 | 1943 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1944 | unsigned pte_access, int user_fault, |
640d9b0d | 1945 | int write_fault, int level, |
c2d0ee46 | 1946 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 1947 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 1948 | { |
b330aa0c | 1949 | u64 spte, entry = *sptep; |
1e73f9dd | 1950 | int ret = 0; |
64d4d521 | 1951 | |
1c4f1fd6 AK |
1952 | /* |
1953 | * We don't set the accessed bit, since we sometimes want to see | |
1954 | * whether the guest actually used the pte (in order to detect | |
1955 | * demand paging). | |
1956 | */ | |
982c2565 | 1957 | spte = PT_PRESENT_MASK; |
947da538 | 1958 | if (!speculative) |
3201b5d9 | 1959 | spte |= shadow_accessed_mask; |
640d9b0d | 1960 | |
7b52345e SY |
1961 | if (pte_access & ACC_EXEC_MASK) |
1962 | spte |= shadow_x_mask; | |
1963 | else | |
1964 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1965 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1966 | spte |= shadow_user_mask; |
852e3c19 | 1967 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1968 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 1969 | if (tdp_enabled) |
4b12f0de SY |
1970 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
1971 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1972 | |
9bdbba13 | 1973 | if (host_writable) |
1403283a | 1974 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
1975 | else |
1976 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 1977 | |
35149e21 | 1978 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1979 | |
1980 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
1981 | || (!vcpu->arch.mmu.direct_map && write_fault |
1982 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1983 | |
852e3c19 JR |
1984 | if (level > PT_PAGE_TABLE_LEVEL && |
1985 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1986 | ret = 1; |
c3707958 | 1987 | drop_spte(vcpu->kvm, sptep); |
be38d276 | 1988 | goto done; |
38187c83 MT |
1989 | } |
1990 | ||
1c4f1fd6 | 1991 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1992 | |
c5a78f2b | 1993 | if (!vcpu->arch.mmu.direct_map |
411c588d | 1994 | && !(pte_access & ACC_WRITE_MASK)) { |
69325a12 | 1995 | spte &= ~PT_USER_MASK; |
411c588d AK |
1996 | /* |
1997 | * If we converted a user page to a kernel page, | |
1998 | * so that the kernel can write to it when cr0.wp=0, | |
1999 | * then we should prevent the kernel from executing it | |
2000 | * if SMEP is enabled. | |
2001 | */ | |
2002 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
2003 | spte |= PT64_NX_MASK; | |
2004 | } | |
69325a12 | 2005 | |
ecc5589f MT |
2006 | /* |
2007 | * Optimization: for pte sync, if spte was writable the hash | |
2008 | * lookup is unnecessary (and expensive). Write protection | |
2009 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2010 | * Same reasoning can be applied to dirty page accounting. | |
2011 | */ | |
8dae4445 | 2012 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2013 | goto set_pte; |
2014 | ||
4731d4c7 | 2015 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2016 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2017 | __func__, gfn); |
1e73f9dd | 2018 | ret = 1; |
1c4f1fd6 | 2019 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2020 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2021 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2022 | } |
2023 | } | |
2024 | ||
1c4f1fd6 AK |
2025 | if (pte_access & ACC_WRITE_MASK) |
2026 | mark_page_dirty(vcpu->kvm, gfn); | |
2027 | ||
38187c83 | 2028 | set_pte: |
1df9f2dc | 2029 | mmu_spte_update(sptep, spte); |
b330aa0c XG |
2030 | /* |
2031 | * If we overwrite a writable spte with a read-only one we | |
2032 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2033 | * will find a read-only spte, even though the writable spte | |
2034 | * might be cached on a CPU's TLB. | |
2035 | */ | |
2036 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2037 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2038 | done: |
1e73f9dd MT |
2039 | return ret; |
2040 | } | |
2041 | ||
d555c333 | 2042 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2043 | unsigned pt_access, unsigned pte_access, |
640d9b0d | 2044 | int user_fault, int write_fault, |
b90a0e6c | 2045 | int *emulate, int level, gfn_t gfn, |
1403283a | 2046 | pfn_t pfn, bool speculative, |
9bdbba13 | 2047 | bool host_writable) |
1e73f9dd MT |
2048 | { |
2049 | int was_rmapped = 0; | |
53a27b39 | 2050 | int rmap_count; |
1e73f9dd MT |
2051 | |
2052 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2053 | " user_fault %d gfn %llx\n", |
d555c333 | 2054 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2055 | write_fault, user_fault, gfn); |
2056 | ||
d555c333 | 2057 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2058 | /* |
2059 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2060 | * the parent of the now unreachable PTE. | |
2061 | */ | |
852e3c19 JR |
2062 | if (level > PT_PAGE_TABLE_LEVEL && |
2063 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2064 | struct kvm_mmu_page *child; |
d555c333 | 2065 | u64 pte = *sptep; |
1e73f9dd MT |
2066 | |
2067 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2068 | drop_parent_pte(child, sptep); |
3be2264b | 2069 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2070 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2071 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2072 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2073 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2074 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2075 | } else |
2076 | was_rmapped = 1; | |
1e73f9dd | 2077 | } |
852e3c19 | 2078 | |
d555c333 | 2079 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
640d9b0d | 2080 | level, gfn, pfn, speculative, true, |
9bdbba13 | 2081 | host_writable)) { |
1e73f9dd | 2082 | if (write_fault) |
b90a0e6c | 2083 | *emulate = 1; |
5304efde | 2084 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2085 | } |
1e73f9dd | 2086 | |
d555c333 | 2087 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2088 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2089 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2090 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2091 | *sptep, sptep); | |
d555c333 | 2092 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2093 | ++vcpu->kvm->stat.lpages; |
2094 | ||
ffb61bb3 XG |
2095 | if (is_shadow_present_pte(*sptep)) { |
2096 | page_header_update_slot(vcpu->kvm, sptep, gfn); | |
2097 | if (!was_rmapped) { | |
2098 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2099 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2100 | rmap_recycle(vcpu, sptep, gfn); | |
2101 | } | |
1c4f1fd6 | 2102 | } |
9ed5520d | 2103 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2104 | if (speculative) { |
d555c333 | 2105 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2106 | vcpu->arch.last_pte_gfn = gfn; |
2107 | } | |
1c4f1fd6 AK |
2108 | } |
2109 | ||
6aa8b732 AK |
2110 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2111 | { | |
2112 | } | |
2113 | ||
957ed9ef XG |
2114 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2115 | bool no_dirty_log) | |
2116 | { | |
2117 | struct kvm_memory_slot *slot; | |
2118 | unsigned long hva; | |
2119 | ||
5d163b1c | 2120 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef | 2121 | if (!slot) { |
fce92dce XG |
2122 | get_page(fault_page); |
2123 | return page_to_pfn(fault_page); | |
957ed9ef XG |
2124 | } |
2125 | ||
2126 | hva = gfn_to_hva_memslot(slot, gfn); | |
2127 | ||
2128 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2129 | } | |
2130 | ||
2131 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2132 | struct kvm_mmu_page *sp, | |
2133 | u64 *start, u64 *end) | |
2134 | { | |
2135 | struct page *pages[PTE_PREFETCH_NUM]; | |
2136 | unsigned access = sp->role.access; | |
2137 | int i, ret; | |
2138 | gfn_t gfn; | |
2139 | ||
2140 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2141 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2142 | return -1; |
2143 | ||
2144 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2145 | if (ret <= 0) | |
2146 | return -1; | |
2147 | ||
2148 | for (i = 0; i < ret; i++, gfn++, start++) | |
2149 | mmu_set_spte(vcpu, start, ACC_ALL, | |
640d9b0d | 2150 | access, 0, 0, NULL, |
957ed9ef XG |
2151 | sp->role.level, gfn, |
2152 | page_to_pfn(pages[i]), true, true); | |
2153 | ||
2154 | return 0; | |
2155 | } | |
2156 | ||
2157 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2158 | struct kvm_mmu_page *sp, u64 *sptep) | |
2159 | { | |
2160 | u64 *spte, *start = NULL; | |
2161 | int i; | |
2162 | ||
2163 | WARN_ON(!sp->role.direct); | |
2164 | ||
2165 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2166 | spte = sp->spt + i; | |
2167 | ||
2168 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2169 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2170 | if (!start) |
2171 | continue; | |
2172 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2173 | break; | |
2174 | start = NULL; | |
2175 | } else if (!start) | |
2176 | start = spte; | |
2177 | } | |
2178 | } | |
2179 | ||
2180 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2181 | { | |
2182 | struct kvm_mmu_page *sp; | |
2183 | ||
2184 | /* | |
2185 | * Since it's no accessed bit on EPT, it's no way to | |
2186 | * distinguish between actually accessed translations | |
2187 | * and prefetched, so disable pte prefetch if EPT is | |
2188 | * enabled. | |
2189 | */ | |
2190 | if (!shadow_accessed_mask) | |
2191 | return; | |
2192 | ||
2193 | sp = page_header(__pa(sptep)); | |
2194 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2195 | return; | |
2196 | ||
2197 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2198 | } | |
2199 | ||
9f652d21 | 2200 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2201 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2202 | bool prefault) | |
140754bc | 2203 | { |
9f652d21 | 2204 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2205 | struct kvm_mmu_page *sp; |
b90a0e6c | 2206 | int emulate = 0; |
140754bc | 2207 | gfn_t pseudo_gfn; |
6aa8b732 | 2208 | |
9f652d21 | 2209 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2210 | if (iterator.level == level) { |
612819c3 MT |
2211 | unsigned pte_access = ACC_ALL; |
2212 | ||
612819c3 | 2213 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
b90a0e6c | 2214 | 0, write, &emulate, |
2ec4739d | 2215 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2216 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2217 | ++vcpu->stat.pf_fixed; |
2218 | break; | |
6aa8b732 AK |
2219 | } |
2220 | ||
c3707958 | 2221 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2222 | u64 base_addr = iterator.addr; |
2223 | ||
2224 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2225 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2226 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2227 | iterator.level - 1, | |
2228 | 1, ACC_ALL, iterator.sptep); | |
2229 | if (!sp) { | |
2230 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2231 | kvm_release_pfn_clean(pfn); | |
2232 | return -ENOMEM; | |
2233 | } | |
140754bc | 2234 | |
1df9f2dc XG |
2235 | mmu_spte_set(iterator.sptep, |
2236 | __pa(sp->spt) | |
2237 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2238 | | shadow_user_mask | shadow_x_mask | |
2239 | | shadow_accessed_mask); | |
9f652d21 AK |
2240 | } |
2241 | } | |
b90a0e6c | 2242 | return emulate; |
6aa8b732 AK |
2243 | } |
2244 | ||
77db5cbd | 2245 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2246 | { |
77db5cbd HY |
2247 | siginfo_t info; |
2248 | ||
2249 | info.si_signo = SIGBUS; | |
2250 | info.si_errno = 0; | |
2251 | info.si_code = BUS_MCEERR_AR; | |
2252 | info.si_addr = (void __user *)address; | |
2253 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2254 | |
77db5cbd | 2255 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2256 | } |
2257 | ||
d7c55201 | 2258 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 HY |
2259 | { |
2260 | kvm_release_pfn_clean(pfn); | |
2261 | if (is_hwpoison_pfn(pfn)) { | |
bebb106a | 2262 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2263 | return 0; |
d7c55201 | 2264 | } |
edba23e5 | 2265 | |
d7c55201 | 2266 | return -EFAULT; |
bf998156 HY |
2267 | } |
2268 | ||
936a5fe6 AA |
2269 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2270 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2271 | { | |
2272 | pfn_t pfn = *pfnp; | |
2273 | gfn_t gfn = *gfnp; | |
2274 | int level = *levelp; | |
2275 | ||
2276 | /* | |
2277 | * Check if it's a transparent hugepage. If this would be an | |
2278 | * hugetlbfs page, level wouldn't be set to | |
2279 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2280 | * here. | |
2281 | */ | |
2282 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2283 | level == PT_PAGE_TABLE_LEVEL && | |
2284 | PageTransCompound(pfn_to_page(pfn)) && | |
2285 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2286 | unsigned long mask; | |
2287 | /* | |
2288 | * mmu_notifier_retry was successful and we hold the | |
2289 | * mmu_lock here, so the pmd can't become splitting | |
2290 | * from under us, and in turn | |
2291 | * __split_huge_page_refcount() can't run from under | |
2292 | * us and we can safely transfer the refcount from | |
2293 | * PG_tail to PG_head as we switch the pfn to tail to | |
2294 | * head. | |
2295 | */ | |
2296 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2297 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2298 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2299 | if (pfn & mask) { | |
2300 | gfn &= ~mask; | |
2301 | *gfnp = gfn; | |
2302 | kvm_release_pfn_clean(pfn); | |
2303 | pfn &= ~mask; | |
2304 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2305 | BUG(); | |
2306 | *pfnp = pfn; | |
2307 | } | |
2308 | } | |
2309 | } | |
2310 | ||
d7c55201 XG |
2311 | static bool mmu_invalid_pfn(pfn_t pfn) |
2312 | { | |
2313 | return unlikely(is_invalid_pfn(pfn) || is_noslot_pfn(pfn)); | |
2314 | } | |
2315 | ||
2316 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, | |
2317 | pfn_t pfn, unsigned access, int *ret_val) | |
2318 | { | |
2319 | bool ret = true; | |
2320 | ||
2321 | /* The pfn is invalid, report the error! */ | |
2322 | if (unlikely(is_invalid_pfn(pfn))) { | |
2323 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); | |
2324 | goto exit; | |
2325 | } | |
2326 | ||
2327 | if (unlikely(is_noslot_pfn(pfn))) { | |
2328 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); | |
2329 | *ret_val = 1; | |
2330 | goto exit; | |
2331 | } | |
2332 | ||
2333 | ret = false; | |
2334 | exit: | |
2335 | return ret; | |
2336 | } | |
2337 | ||
78b2c54a | 2338 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2339 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2340 | ||
2341 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2342 | bool prefault) |
10589a46 MT |
2343 | { |
2344 | int r; | |
852e3c19 | 2345 | int level; |
936a5fe6 | 2346 | int force_pt_level; |
35149e21 | 2347 | pfn_t pfn; |
e930bffe | 2348 | unsigned long mmu_seq; |
612819c3 | 2349 | bool map_writable; |
aaee2c94 | 2350 | |
936a5fe6 AA |
2351 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2352 | if (likely(!force_pt_level)) { | |
2353 | level = mapping_level(vcpu, gfn); | |
2354 | /* | |
2355 | * This path builds a PAE pagetable - so we can map | |
2356 | * 2mb pages at maximum. Therefore check if the level | |
2357 | * is larger than that. | |
2358 | */ | |
2359 | if (level > PT_DIRECTORY_LEVEL) | |
2360 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2361 | |
936a5fe6 AA |
2362 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2363 | } else | |
2364 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2365 | |
e930bffe | 2366 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2367 | smp_rmb(); |
060c2abe | 2368 | |
78b2c54a | 2369 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2370 | return 0; |
aaee2c94 | 2371 | |
d7c55201 XG |
2372 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2373 | return r; | |
d196e343 | 2374 | |
aaee2c94 | 2375 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2376 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2377 | goto out_unlock; | |
eb787d10 | 2378 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2379 | if (likely(!force_pt_level)) |
2380 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2381 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2382 | prefault); | |
aaee2c94 MT |
2383 | spin_unlock(&vcpu->kvm->mmu_lock); |
2384 | ||
aaee2c94 | 2385 | |
10589a46 | 2386 | return r; |
e930bffe AA |
2387 | |
2388 | out_unlock: | |
2389 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2390 | kvm_release_pfn_clean(pfn); | |
2391 | return 0; | |
10589a46 MT |
2392 | } |
2393 | ||
2394 | ||
17ac10ad AK |
2395 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2396 | { | |
2397 | int i; | |
4db35314 | 2398 | struct kvm_mmu_page *sp; |
d98ba053 | 2399 | LIST_HEAD(invalid_list); |
17ac10ad | 2400 | |
ad312c7c | 2401 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2402 | return; |
aaee2c94 | 2403 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2404 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2405 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2406 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2407 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2408 | |
4db35314 AK |
2409 | sp = page_header(root); |
2410 | --sp->root_count; | |
d98ba053 XG |
2411 | if (!sp->root_count && sp->role.invalid) { |
2412 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2413 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2414 | } | |
ad312c7c | 2415 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2416 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2417 | return; |
2418 | } | |
17ac10ad | 2419 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2420 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2421 | |
417726a3 | 2422 | if (root) { |
417726a3 | 2423 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2424 | sp = page_header(root); |
2425 | --sp->root_count; | |
2e53d63a | 2426 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2427 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2428 | &invalid_list); | |
417726a3 | 2429 | } |
ad312c7c | 2430 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2431 | } |
d98ba053 | 2432 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2433 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2434 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2435 | } |
2436 | ||
8986ecc0 MT |
2437 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2438 | { | |
2439 | int ret = 0; | |
2440 | ||
2441 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2442 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2443 | ret = 1; |
2444 | } | |
2445 | ||
2446 | return ret; | |
2447 | } | |
2448 | ||
651dd37a JR |
2449 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2450 | { | |
2451 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2452 | unsigned i; |
651dd37a JR |
2453 | |
2454 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2455 | spin_lock(&vcpu->kvm->mmu_lock); | |
2456 | kvm_mmu_free_some_pages(vcpu); | |
2457 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2458 | 1, ACC_ALL, NULL); | |
2459 | ++sp->root_count; | |
2460 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2461 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2462 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2463 | for (i = 0; i < 4; ++i) { | |
2464 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2465 | ||
2466 | ASSERT(!VALID_PAGE(root)); | |
2467 | spin_lock(&vcpu->kvm->mmu_lock); | |
2468 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2469 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2470 | i << 30, | |
651dd37a JR |
2471 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2472 | NULL); | |
2473 | root = __pa(sp->spt); | |
2474 | ++sp->root_count; | |
2475 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2476 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2477 | } |
6292757f | 2478 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2479 | } else |
2480 | BUG(); | |
2481 | ||
2482 | return 0; | |
2483 | } | |
2484 | ||
2485 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2486 | { |
4db35314 | 2487 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2488 | u64 pdptr, pm_mask; |
2489 | gfn_t root_gfn; | |
2490 | int i; | |
3bb65a22 | 2491 | |
5777ed34 | 2492 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2493 | |
651dd37a JR |
2494 | if (mmu_check_root(vcpu, root_gfn)) |
2495 | return 1; | |
2496 | ||
2497 | /* | |
2498 | * Do we shadow a long mode page table? If so we need to | |
2499 | * write-protect the guests page table root. | |
2500 | */ | |
2501 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2502 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2503 | |
2504 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2505 | |
8facbbff | 2506 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2507 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2508 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2509 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2510 | root = __pa(sp->spt); |
2511 | ++sp->root_count; | |
8facbbff | 2512 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2513 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2514 | return 0; |
17ac10ad | 2515 | } |
f87f9288 | 2516 | |
651dd37a JR |
2517 | /* |
2518 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2519 | * or a PAE 3-level page table. In either case we need to be aware that |
2520 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2521 | */ |
81407ca5 JR |
2522 | pm_mask = PT_PRESENT_MASK; |
2523 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2524 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2525 | ||
17ac10ad | 2526 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2527 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2528 | |
2529 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2530 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2531 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2532 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2533 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2534 | continue; |
2535 | } | |
6de4f3ad | 2536 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2537 | if (mmu_check_root(vcpu, root_gfn)) |
2538 | return 1; | |
5a7388c2 | 2539 | } |
8facbbff | 2540 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2541 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2542 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2543 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2544 | ACC_ALL, NULL); |
4db35314 AK |
2545 | root = __pa(sp->spt); |
2546 | ++sp->root_count; | |
8facbbff AK |
2547 | spin_unlock(&vcpu->kvm->mmu_lock); |
2548 | ||
81407ca5 | 2549 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2550 | } |
6292757f | 2551 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2552 | |
2553 | /* | |
2554 | * If we shadow a 32 bit page table with a long mode page | |
2555 | * table we enter this path. | |
2556 | */ | |
2557 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2558 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2559 | /* | |
2560 | * The additional page necessary for this is only | |
2561 | * allocated on demand. | |
2562 | */ | |
2563 | ||
2564 | u64 *lm_root; | |
2565 | ||
2566 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2567 | if (lm_root == NULL) | |
2568 | return 1; | |
2569 | ||
2570 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2571 | ||
2572 | vcpu->arch.mmu.lm_root = lm_root; | |
2573 | } | |
2574 | ||
2575 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2576 | } | |
2577 | ||
8986ecc0 | 2578 | return 0; |
17ac10ad AK |
2579 | } |
2580 | ||
651dd37a JR |
2581 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2582 | { | |
2583 | if (vcpu->arch.mmu.direct_map) | |
2584 | return mmu_alloc_direct_roots(vcpu); | |
2585 | else | |
2586 | return mmu_alloc_shadow_roots(vcpu); | |
2587 | } | |
2588 | ||
0ba73cda MT |
2589 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2590 | { | |
2591 | int i; | |
2592 | struct kvm_mmu_page *sp; | |
2593 | ||
81407ca5 JR |
2594 | if (vcpu->arch.mmu.direct_map) |
2595 | return; | |
2596 | ||
0ba73cda MT |
2597 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2598 | return; | |
6903074c | 2599 | |
bebb106a | 2600 | vcpu_clear_mmio_info(vcpu, ~0ul); |
6903074c | 2601 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 2602 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2603 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2604 | sp = page_header(root); | |
2605 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2606 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2607 | return; |
2608 | } | |
2609 | for (i = 0; i < 4; ++i) { | |
2610 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2611 | ||
8986ecc0 | 2612 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2613 | root &= PT64_BASE_ADDR_MASK; |
2614 | sp = page_header(root); | |
2615 | mmu_sync_children(vcpu, sp); | |
2616 | } | |
2617 | } | |
6903074c | 2618 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2619 | } |
2620 | ||
2621 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2622 | { | |
2623 | spin_lock(&vcpu->kvm->mmu_lock); | |
2624 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2625 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2626 | } |
2627 | ||
1871c602 | 2628 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2629 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2630 | { |
ab9ae313 AK |
2631 | if (exception) |
2632 | exception->error_code = 0; | |
6aa8b732 AK |
2633 | return vaddr; |
2634 | } | |
2635 | ||
6539e738 | 2636 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2637 | u32 access, |
2638 | struct x86_exception *exception) | |
6539e738 | 2639 | { |
ab9ae313 AK |
2640 | if (exception) |
2641 | exception->error_code = 0; | |
6539e738 JR |
2642 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2643 | } | |
2644 | ||
6aa8b732 | 2645 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2646 | u32 error_code, bool prefault) |
6aa8b732 | 2647 | { |
e833240f | 2648 | gfn_t gfn; |
e2dec939 | 2649 | int r; |
6aa8b732 | 2650 | |
b8688d51 | 2651 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2652 | r = mmu_topup_memory_caches(vcpu); |
2653 | if (r) | |
2654 | return r; | |
714b93da | 2655 | |
6aa8b732 | 2656 | ASSERT(vcpu); |
ad312c7c | 2657 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2658 | |
e833240f | 2659 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2660 | |
e833240f | 2661 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2662 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2663 | } |
2664 | ||
7e1fbeac | 2665 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2666 | { |
2667 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2668 | |
7c90705b | 2669 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2670 | arch.gfn = gfn; |
c4806acd | 2671 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2672 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2673 | |
2674 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2675 | } | |
2676 | ||
2677 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2678 | { | |
2679 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2680 | kvm_event_needs_reinjection(vcpu))) | |
2681 | return false; | |
2682 | ||
2683 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2684 | } | |
2685 | ||
78b2c54a | 2686 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2687 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2688 | { |
2689 | bool async; | |
2690 | ||
612819c3 | 2691 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2692 | |
2693 | if (!async) | |
2694 | return false; /* *pfn has correct page already */ | |
2695 | ||
2696 | put_page(pfn_to_page(*pfn)); | |
2697 | ||
78b2c54a | 2698 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2699 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2700 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2701 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2702 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2703 | return true; | |
2704 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2705 | return true; | |
2706 | } | |
2707 | ||
612819c3 | 2708 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2709 | |
2710 | return false; | |
2711 | } | |
2712 | ||
56028d08 | 2713 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2714 | bool prefault) |
fb72d167 | 2715 | { |
35149e21 | 2716 | pfn_t pfn; |
fb72d167 | 2717 | int r; |
852e3c19 | 2718 | int level; |
936a5fe6 | 2719 | int force_pt_level; |
05da4558 | 2720 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2721 | unsigned long mmu_seq; |
612819c3 MT |
2722 | int write = error_code & PFERR_WRITE_MASK; |
2723 | bool map_writable; | |
fb72d167 JR |
2724 | |
2725 | ASSERT(vcpu); | |
2726 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2727 | ||
2728 | r = mmu_topup_memory_caches(vcpu); | |
2729 | if (r) | |
2730 | return r; | |
2731 | ||
936a5fe6 AA |
2732 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2733 | if (likely(!force_pt_level)) { | |
2734 | level = mapping_level(vcpu, gfn); | |
2735 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2736 | } else | |
2737 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 2738 | |
e930bffe | 2739 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2740 | smp_rmb(); |
af585b92 | 2741 | |
78b2c54a | 2742 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2743 | return 0; |
2744 | ||
d7c55201 XG |
2745 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
2746 | return r; | |
2747 | ||
fb72d167 | 2748 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2749 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2750 | goto out_unlock; | |
fb72d167 | 2751 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2752 | if (likely(!force_pt_level)) |
2753 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 2754 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2755 | level, gfn, pfn, prefault); |
fb72d167 | 2756 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2757 | |
2758 | return r; | |
e930bffe AA |
2759 | |
2760 | out_unlock: | |
2761 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2762 | kvm_release_pfn_clean(pfn); | |
2763 | return 0; | |
fb72d167 JR |
2764 | } |
2765 | ||
6aa8b732 AK |
2766 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2767 | { | |
17ac10ad | 2768 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2769 | } |
2770 | ||
52fde8df JR |
2771 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2772 | struct kvm_mmu *context) | |
6aa8b732 | 2773 | { |
6aa8b732 AK |
2774 | context->new_cr3 = nonpaging_new_cr3; |
2775 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2776 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2777 | context->free = nonpaging_free; | |
e8bc217a | 2778 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2779 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2780 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 2781 | context->root_level = 0; |
6aa8b732 | 2782 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2783 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2784 | context->direct_map = true; |
2d48a985 | 2785 | context->nx = false; |
6aa8b732 AK |
2786 | return 0; |
2787 | } | |
2788 | ||
d835dfec | 2789 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2790 | { |
1165f5fe | 2791 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2792 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2793 | } |
2794 | ||
2795 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2796 | { | |
9f8fe504 | 2797 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 2798 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2799 | } |
2800 | ||
5777ed34 JR |
2801 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2802 | { | |
9f8fe504 | 2803 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
2804 | } |
2805 | ||
6389ee94 AK |
2806 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2807 | struct x86_exception *fault) | |
6aa8b732 | 2808 | { |
6389ee94 | 2809 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2810 | } |
2811 | ||
6aa8b732 AK |
2812 | static void paging_free(struct kvm_vcpu *vcpu) |
2813 | { | |
2814 | nonpaging_free(vcpu); | |
2815 | } | |
2816 | ||
3241f22d | 2817 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2818 | { |
2819 | int bit7; | |
2820 | ||
2821 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2822 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2823 | } |
2824 | ||
6aa8b732 AK |
2825 | #define PTTYPE 64 |
2826 | #include "paging_tmpl.h" | |
2827 | #undef PTTYPE | |
2828 | ||
2829 | #define PTTYPE 32 | |
2830 | #include "paging_tmpl.h" | |
2831 | #undef PTTYPE | |
2832 | ||
52fde8df JR |
2833 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2834 | struct kvm_mmu *context, | |
2835 | int level) | |
82725b20 | 2836 | { |
82725b20 DE |
2837 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2838 | u64 exb_bit_rsvd = 0; | |
2839 | ||
2d48a985 | 2840 | if (!context->nx) |
82725b20 DE |
2841 | exb_bit_rsvd = rsvd_bits(63, 63); |
2842 | switch (level) { | |
2843 | case PT32_ROOT_LEVEL: | |
2844 | /* no rsvd bits for 2 level 4K page table entries */ | |
2845 | context->rsvd_bits_mask[0][1] = 0; | |
2846 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2847 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2848 | ||
2849 | if (!is_pse(vcpu)) { | |
2850 | context->rsvd_bits_mask[1][1] = 0; | |
2851 | break; | |
2852 | } | |
2853 | ||
82725b20 DE |
2854 | if (is_cpuid_PSE36()) |
2855 | /* 36bits PSE 4MB page */ | |
2856 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2857 | else | |
2858 | /* 32 bits PSE 4MB page */ | |
2859 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2860 | break; |
2861 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2862 | context->rsvd_bits_mask[0][2] = |
2863 | rsvd_bits(maxphyaddr, 63) | | |
2864 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2865 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2866 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2867 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2868 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2869 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2870 | rsvd_bits(maxphyaddr, 62) | | |
2871 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2872 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2873 | break; |
2874 | case PT64_ROOT_LEVEL: | |
2875 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2876 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2877 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2878 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2879 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2880 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2881 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2882 | rsvd_bits(maxphyaddr, 51); | |
2883 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2884 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2885 | rsvd_bits(maxphyaddr, 51) | | |
2886 | rsvd_bits(13, 29); | |
82725b20 | 2887 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2888 | rsvd_bits(maxphyaddr, 51) | |
2889 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2890 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2891 | break; |
2892 | } | |
2893 | } | |
2894 | ||
52fde8df JR |
2895 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2896 | struct kvm_mmu *context, | |
2897 | int level) | |
6aa8b732 | 2898 | { |
2d48a985 JR |
2899 | context->nx = is_nx(vcpu); |
2900 | ||
52fde8df | 2901 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2902 | |
2903 | ASSERT(is_pae(vcpu)); | |
2904 | context->new_cr3 = paging_new_cr3; | |
2905 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2906 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 2907 | context->sync_page = paging64_sync_page; |
a7052897 | 2908 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 2909 | context->update_pte = paging64_update_pte; |
6aa8b732 | 2910 | context->free = paging_free; |
17ac10ad AK |
2911 | context->root_level = level; |
2912 | context->shadow_root_level = level; | |
17c3ba9d | 2913 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2914 | context->direct_map = false; |
6aa8b732 AK |
2915 | return 0; |
2916 | } | |
2917 | ||
52fde8df JR |
2918 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2919 | struct kvm_mmu *context) | |
17ac10ad | 2920 | { |
52fde8df | 2921 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2922 | } |
2923 | ||
52fde8df JR |
2924 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2925 | struct kvm_mmu *context) | |
6aa8b732 | 2926 | { |
2d48a985 JR |
2927 | context->nx = false; |
2928 | ||
52fde8df | 2929 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2930 | |
2931 | context->new_cr3 = paging_new_cr3; | |
2932 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2933 | context->gva_to_gpa = paging32_gva_to_gpa; |
2934 | context->free = paging_free; | |
e8bc217a | 2935 | context->sync_page = paging32_sync_page; |
a7052897 | 2936 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 2937 | context->update_pte = paging32_update_pte; |
6aa8b732 AK |
2938 | context->root_level = PT32_ROOT_LEVEL; |
2939 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2940 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2941 | context->direct_map = false; |
6aa8b732 AK |
2942 | return 0; |
2943 | } | |
2944 | ||
52fde8df JR |
2945 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2946 | struct kvm_mmu *context) | |
6aa8b732 | 2947 | { |
52fde8df | 2948 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2949 | } |
2950 | ||
fb72d167 JR |
2951 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2952 | { | |
14dfe855 | 2953 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 2954 | |
c445f8ef | 2955 | context->base_role.word = 0; |
fb72d167 JR |
2956 | context->new_cr3 = nonpaging_new_cr3; |
2957 | context->page_fault = tdp_page_fault; | |
2958 | context->free = nonpaging_free; | |
e8bc217a | 2959 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2960 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2961 | context->update_pte = nonpaging_update_pte; |
67253af5 | 2962 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2963 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2964 | context->direct_map = true; |
1c97f0a0 | 2965 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2966 | context->get_cr3 = get_cr3; |
cb659db8 | 2967 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 2968 | context->nx = is_nx(vcpu); |
fb72d167 JR |
2969 | |
2970 | if (!is_paging(vcpu)) { | |
2d48a985 | 2971 | context->nx = false; |
fb72d167 JR |
2972 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2973 | context->root_level = 0; | |
2974 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2975 | context->nx = is_nx(vcpu); |
52fde8df | 2976 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
2977 | context->gva_to_gpa = paging64_gva_to_gpa; |
2978 | context->root_level = PT64_ROOT_LEVEL; | |
2979 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2980 | context->nx = is_nx(vcpu); |
52fde8df | 2981 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2982 | context->gva_to_gpa = paging64_gva_to_gpa; |
2983 | context->root_level = PT32E_ROOT_LEVEL; | |
2984 | } else { | |
2d48a985 | 2985 | context->nx = false; |
52fde8df | 2986 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
2987 | context->gva_to_gpa = paging32_gva_to_gpa; |
2988 | context->root_level = PT32_ROOT_LEVEL; | |
2989 | } | |
2990 | ||
2991 | return 0; | |
2992 | } | |
2993 | ||
52fde8df | 2994 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 2995 | { |
a770f6f2 | 2996 | int r; |
411c588d | 2997 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 2998 | ASSERT(vcpu); |
ad312c7c | 2999 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3000 | |
3001 | if (!is_paging(vcpu)) | |
52fde8df | 3002 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3003 | else if (is_long_mode(vcpu)) |
52fde8df | 3004 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3005 | else if (is_pae(vcpu)) |
52fde8df | 3006 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3007 | else |
52fde8df | 3008 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3009 | |
5b7e0102 | 3010 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3011 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3012 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3013 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3014 | |
3015 | return r; | |
3016 | } | |
3017 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3018 | ||
3019 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3020 | { | |
14dfe855 | 3021 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3022 | |
14dfe855 JR |
3023 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3024 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
3025 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
3026 | |
3027 | return r; | |
6aa8b732 AK |
3028 | } |
3029 | ||
02f59dc9 JR |
3030 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3031 | { | |
3032 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3033 | ||
3034 | g_context->get_cr3 = get_cr3; | |
3035 | g_context->inject_page_fault = kvm_inject_page_fault; | |
3036 | ||
3037 | /* | |
3038 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3039 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3040 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3041 | * functions between mmu and nested_mmu are swapped. | |
3042 | */ | |
3043 | if (!is_paging(vcpu)) { | |
2d48a985 | 3044 | g_context->nx = false; |
02f59dc9 JR |
3045 | g_context->root_level = 0; |
3046 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3047 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3048 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3049 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
3050 | g_context->root_level = PT64_ROOT_LEVEL; | |
3051 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3052 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3053 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3054 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
3055 | g_context->root_level = PT32E_ROOT_LEVEL; | |
3056 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3057 | } else { | |
2d48a985 | 3058 | g_context->nx = false; |
02f59dc9 JR |
3059 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
3060 | g_context->root_level = PT32_ROOT_LEVEL; | |
3061 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
3062 | } | |
3063 | ||
3064 | return 0; | |
3065 | } | |
3066 | ||
fb72d167 JR |
3067 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3068 | { | |
02f59dc9 JR |
3069 | if (mmu_is_nested(vcpu)) |
3070 | return init_kvm_nested_mmu(vcpu); | |
3071 | else if (tdp_enabled) | |
fb72d167 JR |
3072 | return init_kvm_tdp_mmu(vcpu); |
3073 | else | |
3074 | return init_kvm_softmmu(vcpu); | |
3075 | } | |
3076 | ||
6aa8b732 AK |
3077 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3078 | { | |
3079 | ASSERT(vcpu); | |
62ad0755 SY |
3080 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3081 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3082 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3083 | } |
3084 | ||
3085 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3086 | { |
3087 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3088 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3089 | } |
8668a3c4 | 3090 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3091 | |
3092 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3093 | { |
714b93da AK |
3094 | int r; |
3095 | ||
e2dec939 | 3096 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3097 | if (r) |
3098 | goto out; | |
8986ecc0 | 3099 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3100 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3101 | mmu_sync_roots(vcpu); |
aaee2c94 | 3102 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3103 | if (r) |
3104 | goto out; | |
3662cb1c | 3105 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3106 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3107 | out: |
3108 | return r; | |
6aa8b732 | 3109 | } |
17c3ba9d AK |
3110 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3111 | ||
3112 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3113 | { | |
3114 | mmu_free_roots(vcpu); | |
3115 | } | |
4b16184c | 3116 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3117 | |
0028425f | 3118 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3119 | struct kvm_mmu_page *sp, u64 *spte, |
3120 | const void *new) | |
0028425f | 3121 | { |
30945387 | 3122 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3123 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3124 | return; | |
30945387 | 3125 | } |
0028425f | 3126 | |
4cee5764 | 3127 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3128 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3129 | } |
3130 | ||
79539cec AK |
3131 | static bool need_remote_flush(u64 old, u64 new) |
3132 | { | |
3133 | if (!is_shadow_present_pte(old)) | |
3134 | return false; | |
3135 | if (!is_shadow_present_pte(new)) | |
3136 | return true; | |
3137 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3138 | return true; | |
3139 | old ^= PT64_NX_MASK; | |
3140 | new ^= PT64_NX_MASK; | |
3141 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3142 | } | |
3143 | ||
0671a8e7 XG |
3144 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3145 | bool remote_flush, bool local_flush) | |
79539cec | 3146 | { |
0671a8e7 XG |
3147 | if (zap_page) |
3148 | return; | |
3149 | ||
3150 | if (remote_flush) | |
79539cec | 3151 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3152 | else if (local_flush) |
79539cec AK |
3153 | kvm_mmu_flush_tlb(vcpu); |
3154 | } | |
3155 | ||
12b7d28f AK |
3156 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3157 | { | |
ad312c7c | 3158 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3159 | |
7b52345e | 3160 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3161 | } |
3162 | ||
1b7fcd32 AK |
3163 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3164 | { | |
3165 | u64 *spte = vcpu->arch.last_pte_updated; | |
3166 | ||
3167 | if (spte | |
3168 | && vcpu->arch.last_pte_gfn == gfn | |
3169 | && shadow_accessed_mask | |
3170 | && !(*spte & shadow_accessed_mask) | |
3171 | && is_shadow_present_pte(*spte)) | |
3172 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3173 | } | |
3174 | ||
09072daf | 3175 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3176 | const u8 *new, int bytes, |
3177 | bool guest_initiated) | |
da4a00f0 | 3178 | { |
9b7a0325 | 3179 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3180 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3181 | struct kvm_mmu_page *sp; |
f41d335a | 3182 | struct hlist_node *node; |
d98ba053 | 3183 | LIST_HEAD(invalid_list); |
0f53b5b1 XG |
3184 | u64 entry, gentry, *spte; |
3185 | unsigned pte_size, page_offset, misaligned, quadrant, offset; | |
3186 | int level, npte, invlpg_counter, r, flooded = 0; | |
0671a8e7 XG |
3187 | bool remote_flush, local_flush, zap_page; |
3188 | ||
332b207d XG |
3189 | /* |
3190 | * If we don't have indirect shadow pages, it means no page is | |
3191 | * write-protected, so we can exit simply. | |
3192 | */ | |
3193 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3194 | return; | |
3195 | ||
0671a8e7 | 3196 | zap_page = remote_flush = local_flush = false; |
0f53b5b1 | 3197 | offset = offset_in_page(gpa); |
9b7a0325 | 3198 | |
b8688d51 | 3199 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3200 | |
08e850c6 | 3201 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3202 | |
3203 | /* | |
3204 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3205 | * as the current vcpu paging mode since we update the sptes only |
3206 | * when they have the same mode. | |
72016f3a | 3207 | */ |
08e850c6 | 3208 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3209 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3210 | if (is_pae(vcpu)) { |
3211 | gpa &= ~(gpa_t)7; | |
3212 | bytes = 8; | |
3213 | } | |
3214 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3215 | if (r) |
3216 | gentry = 0; | |
08e850c6 AK |
3217 | new = (const u8 *)&gentry; |
3218 | } | |
3219 | ||
3220 | switch (bytes) { | |
3221 | case 4: | |
3222 | gentry = *(const u32 *)new; | |
3223 | break; | |
3224 | case 8: | |
3225 | gentry = *(const u64 *)new; | |
3226 | break; | |
3227 | default: | |
3228 | gentry = 0; | |
3229 | break; | |
72016f3a AK |
3230 | } |
3231 | ||
aaee2c94 | 3232 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3233 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3234 | gentry = 0; | |
eb787d10 | 3235 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3236 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3237 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 | 3238 | if (guest_initiated) { |
1b7fd45c | 3239 | kvm_mmu_access_page(vcpu, gfn); |
ad218f85 MT |
3240 | if (gfn == vcpu->arch.last_pt_write_gfn |
3241 | && !last_updated_pte_accessed(vcpu)) { | |
3242 | ++vcpu->arch.last_pt_write_count; | |
3243 | if (vcpu->arch.last_pt_write_count >= 3) | |
3244 | flooded = 1; | |
3245 | } else { | |
3246 | vcpu->arch.last_pt_write_gfn = gfn; | |
3247 | vcpu->arch.last_pt_write_count = 1; | |
3248 | vcpu->arch.last_pte_updated = NULL; | |
3249 | } | |
86a5ba02 | 3250 | } |
3246af0e | 3251 | |
fa1de2bf | 3252 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3253 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3254 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3255 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3256 | misaligned |= bytes < 4; |
86a5ba02 | 3257 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3258 | /* |
3259 | * Misaligned accesses are too much trouble to fix | |
3260 | * up; also, they usually indicate a page is not used | |
3261 | * as a page table. | |
86a5ba02 AK |
3262 | * |
3263 | * If we're seeing too many writes to a page, | |
3264 | * it may no longer be a page table, or we may be | |
3265 | * forking, in which case it is better to unmap the | |
3266 | * page. | |
0e7bc4b9 AK |
3267 | */ |
3268 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3269 | gpa, bytes, sp->role.word); |
0671a8e7 | 3270 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3271 | &invalid_list); |
4cee5764 | 3272 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3273 | continue; |
3274 | } | |
9b7a0325 | 3275 | page_offset = offset; |
4db35314 | 3276 | level = sp->role.level; |
ac1b714e | 3277 | npte = 1; |
5b7e0102 | 3278 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3279 | page_offset <<= 1; /* 32->64 */ |
3280 | /* | |
3281 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3282 | * only 2MB. So we need to double the offset again | |
3283 | * and zap two pdes instead of one. | |
3284 | */ | |
3285 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3286 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3287 | page_offset <<= 1; |
3288 | npte = 2; | |
3289 | } | |
fce0657f | 3290 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3291 | page_offset &= ~PAGE_MASK; |
4db35314 | 3292 | if (quadrant != sp->role.quadrant) |
fce0657f | 3293 | continue; |
9b7a0325 | 3294 | } |
0671a8e7 | 3295 | local_flush = true; |
4db35314 | 3296 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3297 | while (npte--) { |
79539cec | 3298 | entry = *spte; |
38e3b2b2 | 3299 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3300 | if (gentry && |
3301 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3302 | & mask.word)) | |
7c562522 | 3303 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3304 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3305 | remote_flush = true; | |
ac1b714e | 3306 | ++spte; |
9b7a0325 | 3307 | } |
9b7a0325 | 3308 | } |
0671a8e7 | 3309 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3310 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3311 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3312 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3313 | } |
3314 | ||
a436036b AK |
3315 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3316 | { | |
10589a46 MT |
3317 | gpa_t gpa; |
3318 | int r; | |
a436036b | 3319 | |
c5a78f2b | 3320 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3321 | return 0; |
3322 | ||
1871c602 | 3323 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3324 | |
aaee2c94 | 3325 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3326 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3327 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3328 | return r; |
a436036b | 3329 | } |
577bdc49 | 3330 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3331 | |
22d95b12 | 3332 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3333 | { |
d98ba053 | 3334 | LIST_HEAD(invalid_list); |
103ad25a | 3335 | |
e0df7b9f | 3336 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3337 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3338 | struct kvm_mmu_page *sp; |
ebeace86 | 3339 | |
f05e70ac | 3340 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3341 | struct kvm_mmu_page, link); |
e0df7b9f | 3342 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 3343 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 3344 | } |
aa6bd187 | 3345 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 3346 | } |
ebeace86 | 3347 | |
dc25e89e AP |
3348 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3349 | void *insn, int insn_len) | |
3067714c AK |
3350 | { |
3351 | int r; | |
3352 | enum emulation_result er; | |
3353 | ||
56028d08 | 3354 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3355 | if (r < 0) |
3356 | goto out; | |
3357 | ||
3358 | if (!r) { | |
3359 | r = 1; | |
3360 | goto out; | |
3361 | } | |
3362 | ||
b733bfb5 AK |
3363 | r = mmu_topup_memory_caches(vcpu); |
3364 | if (r) | |
3365 | goto out; | |
3366 | ||
dc25e89e | 3367 | er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len); |
3067714c AK |
3368 | |
3369 | switch (er) { | |
3370 | case EMULATE_DONE: | |
3371 | return 1; | |
3372 | case EMULATE_DO_MMIO: | |
3373 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3374 | /* fall through */ |
3067714c | 3375 | case EMULATE_FAIL: |
3f5d18a9 | 3376 | return 0; |
3067714c AK |
3377 | default: |
3378 | BUG(); | |
3379 | } | |
3380 | out: | |
3067714c AK |
3381 | return r; |
3382 | } | |
3383 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3384 | ||
a7052897 MT |
3385 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3386 | { | |
a7052897 | 3387 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3388 | kvm_mmu_flush_tlb(vcpu); |
3389 | ++vcpu->stat.invlpg; | |
3390 | } | |
3391 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3392 | ||
18552672 JR |
3393 | void kvm_enable_tdp(void) |
3394 | { | |
3395 | tdp_enabled = true; | |
3396 | } | |
3397 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3398 | ||
5f4cb662 JR |
3399 | void kvm_disable_tdp(void) |
3400 | { | |
3401 | tdp_enabled = false; | |
3402 | } | |
3403 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3404 | ||
6aa8b732 AK |
3405 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3406 | { | |
ad312c7c | 3407 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3408 | if (vcpu->arch.mmu.lm_root != NULL) |
3409 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3410 | } |
3411 | ||
3412 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3413 | { | |
17ac10ad | 3414 | struct page *page; |
6aa8b732 AK |
3415 | int i; |
3416 | ||
3417 | ASSERT(vcpu); | |
3418 | ||
17ac10ad AK |
3419 | /* |
3420 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3421 | * Therefore we need to allocate shadow page tables in the first | |
3422 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3423 | */ | |
3424 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3425 | if (!page) | |
d7fa6ab2 WY |
3426 | return -ENOMEM; |
3427 | ||
ad312c7c | 3428 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3429 | for (i = 0; i < 4; ++i) |
ad312c7c | 3430 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3431 | |
6aa8b732 | 3432 | return 0; |
6aa8b732 AK |
3433 | } |
3434 | ||
8018c27b | 3435 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3436 | { |
6aa8b732 | 3437 | ASSERT(vcpu); |
ad312c7c | 3438 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3439 | |
8018c27b IM |
3440 | return alloc_mmu_pages(vcpu); |
3441 | } | |
6aa8b732 | 3442 | |
8018c27b IM |
3443 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3444 | { | |
3445 | ASSERT(vcpu); | |
ad312c7c | 3446 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3447 | |
8018c27b | 3448 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3449 | } |
3450 | ||
90cb0529 | 3451 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3452 | { |
4db35314 | 3453 | struct kvm_mmu_page *sp; |
6aa8b732 | 3454 | |
f05e70ac | 3455 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3456 | int i; |
3457 | u64 *pt; | |
3458 | ||
291f26bc | 3459 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3460 | continue; |
3461 | ||
4db35314 | 3462 | pt = sp->spt; |
8234b22e | 3463 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3464 | if (!is_shadow_present_pte(pt[i]) || |
3465 | !is_last_spte(pt[i], sp->role.level)) | |
3466 | continue; | |
3467 | ||
3468 | if (is_large_pte(pt[i])) { | |
c3707958 | 3469 | drop_spte(kvm, &pt[i]); |
8234b22e | 3470 | --kvm->stat.lpages; |
da8dc75f | 3471 | continue; |
8234b22e | 3472 | } |
da8dc75f | 3473 | |
6aa8b732 | 3474 | /* avoid RMW */ |
01c168ac | 3475 | if (is_writable_pte(pt[i])) |
1df9f2dc XG |
3476 | mmu_spte_update(&pt[i], |
3477 | pt[i] & ~PT_WRITABLE_MASK); | |
8234b22e | 3478 | } |
6aa8b732 | 3479 | } |
171d595d | 3480 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3481 | } |
37a7d8b0 | 3482 | |
90cb0529 | 3483 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3484 | { |
4db35314 | 3485 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3486 | LIST_HEAD(invalid_list); |
e0fa826f | 3487 | |
aaee2c94 | 3488 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3489 | restart: |
f05e70ac | 3490 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3491 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3492 | goto restart; |
3493 | ||
d98ba053 | 3494 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3495 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3496 | } |
3497 | ||
d98ba053 XG |
3498 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3499 | struct list_head *invalid_list) | |
3ee16c81 IE |
3500 | { |
3501 | struct kvm_mmu_page *page; | |
3502 | ||
3503 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3504 | struct kvm_mmu_page, link); | |
d98ba053 | 3505 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3506 | } |
3507 | ||
1495f230 | 3508 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3509 | { |
3510 | struct kvm *kvm; | |
3511 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3512 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3513 | |
3514 | if (nr_to_scan == 0) | |
3515 | goto out; | |
3ee16c81 | 3516 | |
e935b837 | 3517 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3518 | |
3519 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3520 | int idx, freed_pages; |
d98ba053 | 3521 | LIST_HEAD(invalid_list); |
3ee16c81 | 3522 | |
f656ce01 | 3523 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3524 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3525 | if (!kvm_freed && nr_to_scan > 0 && |
3526 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3527 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3528 | &invalid_list); | |
3ee16c81 IE |
3529 | kvm_freed = kvm; |
3530 | } | |
3531 | nr_to_scan--; | |
3532 | ||
d98ba053 | 3533 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3534 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3535 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3536 | } |
3537 | if (kvm_freed) | |
3538 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3539 | ||
e935b837 | 3540 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3541 | |
45221ab6 DH |
3542 | out: |
3543 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3544 | } |
3545 | ||
3546 | static struct shrinker mmu_shrinker = { | |
3547 | .shrink = mmu_shrink, | |
3548 | .seeks = DEFAULT_SEEKS * 10, | |
3549 | }; | |
3550 | ||
2ddfd20e | 3551 | static void mmu_destroy_caches(void) |
b5a33a75 | 3552 | { |
53c07b18 XG |
3553 | if (pte_list_desc_cache) |
3554 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
3555 | if (mmu_page_header_cache) |
3556 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3557 | } |
3558 | ||
3559 | int kvm_mmu_module_init(void) | |
3560 | { | |
53c07b18 XG |
3561 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
3562 | sizeof(struct pte_list_desc), | |
20c2df83 | 3563 | 0, 0, NULL); |
53c07b18 | 3564 | if (!pte_list_desc_cache) |
b5a33a75 AK |
3565 | goto nomem; |
3566 | ||
d3d25b04 AK |
3567 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3568 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3569 | 0, 0, NULL); |
d3d25b04 AK |
3570 | if (!mmu_page_header_cache) |
3571 | goto nomem; | |
3572 | ||
45bf21a8 WY |
3573 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3574 | goto nomem; | |
3575 | ||
3ee16c81 IE |
3576 | register_shrinker(&mmu_shrinker); |
3577 | ||
b5a33a75 AK |
3578 | return 0; |
3579 | ||
3580 | nomem: | |
3ee16c81 | 3581 | mmu_destroy_caches(); |
b5a33a75 AK |
3582 | return -ENOMEM; |
3583 | } | |
3584 | ||
3ad82a7e ZX |
3585 | /* |
3586 | * Caculate mmu pages needed for kvm. | |
3587 | */ | |
3588 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3589 | { | |
3590 | int i; | |
3591 | unsigned int nr_mmu_pages; | |
3592 | unsigned int nr_pages = 0; | |
bc6678a3 | 3593 | struct kvm_memslots *slots; |
3ad82a7e | 3594 | |
90d83dc3 LJ |
3595 | slots = kvm_memslots(kvm); |
3596 | ||
bc6678a3 MT |
3597 | for (i = 0; i < slots->nmemslots; i++) |
3598 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3599 | |
3600 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3601 | nr_mmu_pages = max(nr_mmu_pages, | |
3602 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3603 | ||
3604 | return nr_mmu_pages; | |
3605 | } | |
3606 | ||
2f333bcb MT |
3607 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3608 | unsigned len) | |
3609 | { | |
3610 | if (len > buffer->len) | |
3611 | return NULL; | |
3612 | return buffer->ptr; | |
3613 | } | |
3614 | ||
3615 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3616 | unsigned len) | |
3617 | { | |
3618 | void *ret; | |
3619 | ||
3620 | ret = pv_mmu_peek_buffer(buffer, len); | |
3621 | if (!ret) | |
3622 | return ret; | |
3623 | buffer->ptr += len; | |
3624 | buffer->len -= len; | |
3625 | buffer->processed += len; | |
3626 | return ret; | |
3627 | } | |
3628 | ||
3629 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3630 | gpa_t addr, gpa_t value) | |
3631 | { | |
3632 | int bytes = 8; | |
3633 | int r; | |
3634 | ||
3635 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3636 | bytes = 4; | |
3637 | ||
3638 | r = mmu_topup_memory_caches(vcpu); | |
3639 | if (r) | |
3640 | return r; | |
3641 | ||
3200f405 | 3642 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3643 | return -EFAULT; |
3644 | ||
3645 | return 1; | |
3646 | } | |
3647 | ||
3648 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3649 | { | |
9f8fe504 | 3650 | (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu)); |
2f333bcb MT |
3651 | return 1; |
3652 | } | |
3653 | ||
3654 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3655 | { | |
3656 | spin_lock(&vcpu->kvm->mmu_lock); | |
3657 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3658 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3659 | return 1; | |
3660 | } | |
3661 | ||
3662 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3663 | struct kvm_pv_mmu_op_buffer *buffer) | |
3664 | { | |
3665 | struct kvm_mmu_op_header *header; | |
3666 | ||
3667 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3668 | if (!header) | |
3669 | return 0; | |
3670 | switch (header->op) { | |
3671 | case KVM_MMU_OP_WRITE_PTE: { | |
3672 | struct kvm_mmu_op_write_pte *wpte; | |
3673 | ||
3674 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3675 | if (!wpte) | |
3676 | return 0; | |
3677 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3678 | wpte->pte_val); | |
3679 | } | |
3680 | case KVM_MMU_OP_FLUSH_TLB: { | |
3681 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3682 | ||
3683 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3684 | if (!ftlb) | |
3685 | return 0; | |
3686 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3687 | } | |
3688 | case KVM_MMU_OP_RELEASE_PT: { | |
3689 | struct kvm_mmu_op_release_pt *rpt; | |
3690 | ||
3691 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3692 | if (!rpt) | |
3693 | return 0; | |
3694 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3695 | } | |
3696 | default: return 0; | |
3697 | } | |
3698 | } | |
3699 | ||
3700 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3701 | gpa_t addr, unsigned long *ret) | |
3702 | { | |
3703 | int r; | |
6ad18fba | 3704 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3705 | |
6ad18fba DH |
3706 | buffer->ptr = buffer->buf; |
3707 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3708 | buffer->processed = 0; | |
2f333bcb | 3709 | |
6ad18fba | 3710 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3711 | if (r) |
3712 | goto out; | |
3713 | ||
6ad18fba DH |
3714 | while (buffer->len) { |
3715 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3716 | if (r < 0) |
3717 | goto out; | |
3718 | if (r == 0) | |
3719 | break; | |
3720 | } | |
3721 | ||
3722 | r = 1; | |
3723 | out: | |
6ad18fba | 3724 | *ret = buffer->processed; |
2f333bcb MT |
3725 | return r; |
3726 | } | |
3727 | ||
94d8b056 MT |
3728 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3729 | { | |
3730 | struct kvm_shadow_walk_iterator iterator; | |
3731 | int nr_sptes = 0; | |
3732 | ||
3733 | spin_lock(&vcpu->kvm->mmu_lock); | |
3734 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3735 | sptes[iterator.level-1] = *iterator.sptep; | |
3736 | nr_sptes++; | |
3737 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3738 | break; | |
3739 | } | |
3740 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3741 | ||
3742 | return nr_sptes; | |
3743 | } | |
3744 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3745 | ||
c42fffe3 XG |
3746 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
3747 | { | |
3748 | ASSERT(vcpu); | |
3749 | ||
3750 | destroy_kvm_mmu(vcpu); | |
3751 | free_mmu_pages(vcpu); | |
3752 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
3753 | } |
3754 | ||
3755 | #ifdef CONFIG_KVM_MMU_AUDIT | |
3756 | #include "mmu_audit.c" | |
3757 | #else | |
3758 | static void mmu_audit_disable(void) { } | |
3759 | #endif | |
3760 | ||
3761 | void kvm_mmu_module_exit(void) | |
3762 | { | |
3763 | mmu_destroy_caches(); | |
3764 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
3765 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
3766 | mmu_audit_disable(); |
3767 | } |