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KVM: trivial document fixes
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
6de4f3ad 21#include "kvm_cache_regs.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732
AK		 24#include <linux/types.h>
25#include <linux/string.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
05da4558 30#include <linux/hugetlb.h>
2f333bcb 31#include <linux/compiler.h>
6aa8b732 32
e495606d
AK		 33#include <asm/page.h>
34#include <asm/cmpxchg.h>
4e542370 35#include <asm/io.h>
13673a90 36#include <asm/vmx.h>
6aa8b732 37
18552672
JR		 38/*
39 * When setting this variable to true it enables Two-Dimensional-Paging
40 * where the hardware walks 2 page tables:
41 * 1. the guest-virtual to guest-physical
42 * 2. while doing 1. it walks guest-physical to host-physical
43 * If the hardware supports that we don't need to do shadow paging.
44 */
2f333bcb 45bool tdp_enabled = false;
18552672 46
37a7d8b0
AK		 47#undef MMU_DEBUG
48
49#undef AUDIT
50
51#ifdef AUDIT
52static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
53#else
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
55#endif
56
57#ifdef MMU_DEBUG
58
59#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
60#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
61
62#else
63
64#define pgprintk(x...) do { } while (0)
65#define rmap_printk(x...) do { } while (0)
66
67#endif
68
69#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 70static int dbg = 0;
71module_param(dbg, bool, 0644);
37a7d8b0 72#endif
6aa8b732 73
582801a9
MT		 74static int oos_shadow = 1;
75module_param(oos_shadow, bool, 0644);
76
d6c69ee9
YD		 77#ifndef MMU_DEBUG
78#define ASSERT(x) do { } while (0)
79#else
6aa8b732
AK		 80#define ASSERT(x) \
81 if (!(x)) { \
82 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
83 __FILE__, __LINE__, #x); \
84 }
d6c69ee9 85#endif
6aa8b732 86
6aa8b732
AK		 87#define PT_FIRST_AVAIL_BITS_SHIFT 9
88#define PT64_SECOND_AVAIL_BITS_SHIFT 52
89
6aa8b732
AK		 90#define VALID_PAGE(x) ((x) != INVALID_PAGE)
91
92#define PT64_LEVEL_BITS 9
93
94#define PT64_LEVEL_SHIFT(level) \
d77c26fc 95 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 96
97#define PT64_LEVEL_MASK(level) \
98 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
99
100#define PT64_INDEX(address, level)\
101 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
102
103
104#define PT32_LEVEL_BITS 10
105
106#define PT32_LEVEL_SHIFT(level) \
d77c26fc 107 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 108
109#define PT32_LEVEL_MASK(level) \
110 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 111#define PT32_LVL_OFFSET_MASK(level) \
112 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 114
115#define PT32_INDEX(address, level)\
116 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
117
118
27aba766 119#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 120#define PT64_DIR_BASE_ADDR_MASK \
121 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 122#define PT64_LVL_ADDR_MASK(level) \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT64_LEVEL_BITS))) - 1))
125#define PT64_LVL_OFFSET_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 128
129#define PT32_BASE_ADDR_MASK PAGE_MASK
130#define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 132#define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
6aa8b732 135
79539cec
AK		 136#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
137 | PT64_NX_MASK)
6aa8b732
AK		 138
139#define PFERR_PRESENT_MASK (1U << 0)
140#define PFERR_WRITE_MASK (1U << 1)
141#define PFERR_USER_MASK (1U << 2)
82725b20 142#define PFERR_RSVD_MASK (1U << 3)
73b1087e 143#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 144
e04da980 145#define PT_PDPE_LEVEL 3
6aa8b732
AK		 146#define PT_DIRECTORY_LEVEL 2
147#define PT_PAGE_TABLE_LEVEL 1
148
cd4a4e53
AK		 149#define RMAP_EXT 4
150
fe135d2c
AK		 151#define ACC_EXEC_MASK 1
152#define ACC_WRITE_MASK PT_WRITABLE_MASK
153#define ACC_USER_MASK PT_USER_MASK
154#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
155
07420171
AK		 156#define CREATE_TRACE_POINTS
157#include "mmutrace.h"
158
1403283a
IE		 159#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
160
135f8c2b
AK		 161#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
162
cd4a4e53 163struct kvm_rmap_desc {
d555c333 164 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 165 struct kvm_rmap_desc *more;
166};
167
2d11123a
AK		 168struct kvm_shadow_walk_iterator {
169 u64 addr;
170 hpa_t shadow_addr;
171 int level;
172 u64 *sptep;
173 unsigned index;
174};
175
176#define for_each_shadow_entry(_vcpu, _addr, _walker) \
177 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
178 shadow_walk_okay(&(_walker)); \
179 shadow_walk_next(&(_walker)))
180
181
4731d4c7
MT		 182struct kvm_unsync_walk {
183 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
184};
185
ad8cfbe3
MT		 186typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
187
b5a33a75
AK		 188static struct kmem_cache *pte_chain_cache;
189static struct kmem_cache *rmap_desc_cache;
d3d25b04 190static struct kmem_cache *mmu_page_header_cache;
b5a33a75 191
c7addb90
AK		 192static u64 __read_mostly shadow_trap_nonpresent_pte;
193static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 194static u64 __read_mostly shadow_base_present_pte;
195static u64 __read_mostly shadow_nx_mask;
196static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
197static u64 __read_mostly shadow_user_mask;
198static u64 __read_mostly shadow_accessed_mask;
199static u64 __read_mostly shadow_dirty_mask;
c7addb90 200
82725b20
DE		 201static inline u64 rsvd_bits(int s, int e)
202{
203 return ((1ULL << (e - s + 1)) - 1) << s;
204}
205
c7addb90
AK		 206void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
207{
208 shadow_trap_nonpresent_pte = trap_pte;
209 shadow_notrap_nonpresent_pte = notrap_pte;
210}
211EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
212
7b52345e
SY		 213void kvm_mmu_set_base_ptes(u64 base_pte)
214{
215 shadow_base_present_pte = base_pte;
216}
217EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
218
219void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 220 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 221{
222 shadow_user_mask = user_mask;
223 shadow_accessed_mask = accessed_mask;
224 shadow_dirty_mask = dirty_mask;
225 shadow_nx_mask = nx_mask;
226 shadow_x_mask = x_mask;
227}
228EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
229
6aa8b732
AK		 230static int is_write_protection(struct kvm_vcpu *vcpu)
231{
ad312c7c 232 return vcpu->arch.cr0 & X86_CR0_WP;
6aa8b732
AK		 233}
234
235static int is_cpuid_PSE36(void)
236{
237 return 1;
238}
239
73b1087e
AK		 240static int is_nx(struct kvm_vcpu *vcpu)
241{
ad312c7c 242 return vcpu->arch.shadow_efer & EFER_NX;
73b1087e
AK		 243}
244
c7addb90
AK		 245static int is_shadow_present_pte(u64 pte)
246{
c7addb90
AK		 247 return pte != shadow_trap_nonpresent_pte
248 && pte != shadow_notrap_nonpresent_pte;
249}
250
05da4558
MT		 251static int is_large_pte(u64 pte)
252{
253 return pte & PT_PAGE_SIZE_MASK;
254}
255
6aa8b732
AK		 256static int is_writeble_pte(unsigned long pte)
257{
258 return pte & PT_WRITABLE_MASK;
259}
260
43a3795a 261static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 262{
439e218a 263 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 264}
265
43a3795a 266static int is_rmap_spte(u64 pte)
cd4a4e53 267{
4b1a80fa 268 return is_shadow_present_pte(pte);
cd4a4e53
AK		 269}
270
776e6633
MT		 271static int is_last_spte(u64 pte, int level)
272{
273 if (level == PT_PAGE_TABLE_LEVEL)
274 return 1;
852e3c19 275 if (is_large_pte(pte))
776e6633
MT		 276 return 1;
277 return 0;
278}
279
35149e21 280static pfn_t spte_to_pfn(u64 pte)
0b49ea86 281{
35149e21 282 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 283}
284
da928521
AK		 285static gfn_t pse36_gfn_delta(u32 gpte)
286{
287 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
288
289 return (gpte & PT32_DIR_PSE36_MASK) << shift;
290}
291
d555c333 292static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 293{
294#ifdef CONFIG_X86_64
295 set_64bit((unsigned long *)sptep, spte);
296#else
297 set_64bit((unsigned long long *)sptep, spte);
298#endif
299}
300
e2dec939 301static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 302 struct kmem_cache *base_cache, int min)
714b93da
AK		 303{
304 void *obj;
305
306 if (cache->nobjs >= min)
e2dec939 307 return 0;
714b93da 308 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 309 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 310 if (!obj)
e2dec939 311 return -ENOMEM;
714b93da
AK		 312 cache->objects[cache->nobjs++] = obj;
313 }
e2dec939 314 return 0;
714b93da
AK		 315}
316
317static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
318{
319 while (mc->nobjs)
320 kfree(mc->objects[--mc->nobjs]);
321}
322
c1158e63 323static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 324 int min)
c1158e63
AK		 325{
326 struct page *page;
327
328 if (cache->nobjs >= min)
329 return 0;
330 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 331 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 332 if (!page)
333 return -ENOMEM;
334 set_page_private(page, 0);
335 cache->objects[cache->nobjs++] = page_address(page);
336 }
337 return 0;
338}
339
340static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
341{
342 while (mc->nobjs)
c4d198d5 343 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 344}
345
2e3e5882 346static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 347{
e2dec939
AK		 348 int r;
349
ad312c7c 350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 351 pte_chain_cache, 4);
e2dec939
AK		 352 if (r)
353 goto out;
ad312c7c 354 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 355 rmap_desc_cache, 4);
d3d25b04
AK		 356 if (r)
357 goto out;
ad312c7c 358 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 359 if (r)
360 goto out;
ad312c7c 361 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 362 mmu_page_header_cache, 4);
e2dec939
AK		 363out:
364 return r;
714b93da
AK		 365}
366
367static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
368{
ad312c7c
ZX		 369 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
370 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
371 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
372 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 373}
374
375static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
376 size_t size)
377{
378 void *p;
379
380 BUG_ON(!mc->nobjs);
381 p = mc->objects[--mc->nobjs];
714b93da
AK		 382 return p;
383}
384
714b93da
AK		 385static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
386{
ad312c7c 387 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 388 sizeof(struct kvm_pte_chain));
389}
390
90cb0529 391static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 392{
90cb0529 393 kfree(pc);
714b93da
AK		 394}
395
396static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
397{
ad312c7c 398 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 399 sizeof(struct kvm_rmap_desc));
400}
401
90cb0529 402static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 403{
90cb0529 404 kfree(rd);
714b93da
AK		 405}
406
05da4558
MT		 407/*
408 * Return the pointer to the largepage write count for a given
409 * gfn, handling slots that are not large page aligned.
410 */
d25797b2
JR		 411static int *slot_largepage_idx(gfn_t gfn,
412 struct kvm_memory_slot *slot,
413 int level)
05da4558
MT		 414{
415 unsigned long idx;
416
d25797b2
JR		 417 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
418 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
419 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 420}
421
422static void account_shadowed(struct kvm *kvm, gfn_t gfn)
423{
d25797b2 424 struct kvm_memory_slot *slot;
05da4558 425 int *write_count;
d25797b2 426 int i;
05da4558 427
2843099f 428 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 429
430 slot = gfn_to_memslot_unaliased(kvm, gfn);
431 for (i = PT_DIRECTORY_LEVEL;
432 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
433 write_count = slot_largepage_idx(gfn, slot, i);
434 *write_count += 1;
435 }
05da4558
MT		 436}
437
438static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
439{
d25797b2 440 struct kvm_memory_slot *slot;
05da4558 441 int *write_count;
d25797b2 442 int i;
05da4558 443
2843099f 444 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 445 for (i = PT_DIRECTORY_LEVEL;
446 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
447 slot = gfn_to_memslot_unaliased(kvm, gfn);
448 write_count = slot_largepage_idx(gfn, slot, i);
449 *write_count -= 1;
450 WARN_ON(*write_count < 0);
451 }
05da4558
MT		 452}
453
d25797b2
JR		 454static int has_wrprotected_page(struct kvm *kvm,
455 gfn_t gfn,
456 int level)
05da4558 457{
2843099f 458 struct kvm_memory_slot *slot;
05da4558
MT		 459 int *largepage_idx;
460
2843099f
IE		 461 gfn = unalias_gfn(kvm, gfn);
462 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 463 if (slot) {
d25797b2 464 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 465 return *largepage_idx;
466 }
467
468 return 1;
469}
470
d25797b2 471static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 472{
d25797b2 473 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 474 struct vm_area_struct *vma;
475 unsigned long addr;
d25797b2 476 int i, ret = 0;
05da4558
MT		 477
478 addr = gfn_to_hva(kvm, gfn);
479 if (kvm_is_error_hva(addr))
82b7005f 480 return PT_PAGE_TABLE_LEVEL;
05da4558 481
4c2155ce 482 down_read(&current->mm->mmap_sem);
05da4558 483 vma = find_vma(current->mm, addr);
d25797b2
JR		 484 if (!vma)
485 goto out;
486
487 page_size = vma_kernel_pagesize(vma);
488
489out:
4c2155ce 490 up_read(&current->mm->mmap_sem);
05da4558 491
d25797b2
JR		 492 for (i = PT_PAGE_TABLE_LEVEL;
493 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
494 if (page_size >= KVM_HPAGE_SIZE(i))
495 ret = i;
496 else
497 break;
498 }
499
4c2155ce 500 return ret;
05da4558
MT		 501}
502
d25797b2 503static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 504{
505 struct kvm_memory_slot *slot;
d25797b2
JR		 506 int host_level;
507 int level = PT_PAGE_TABLE_LEVEL;
05da4558
MT		 508
509 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
510 if (slot && slot->dirty_bitmap)
d25797b2 511 return PT_PAGE_TABLE_LEVEL;
05da4558 512
d25797b2
JR		 513 host_level = host_mapping_level(vcpu->kvm, large_gfn);
514
515 if (host_level == PT_PAGE_TABLE_LEVEL)
516 return host_level;
517
82b7005f 518 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level)
d25797b2
JR		 519 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
520 break;
d25797b2
JR		 521
522 return level - 1;
05da4558
MT		 523}
524
290fc38d
IE		 525/*
526 * Take gfn and return the reverse mapping to it.
527 * Note: gfn must be unaliased before this function get called
528 */
529
44ad9944 530static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 531{
532 struct kvm_memory_slot *slot;
05da4558 533 unsigned long idx;
290fc38d
IE		 534
535 slot = gfn_to_memslot(kvm, gfn);
44ad9944 536 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 537 return &slot->rmap[gfn - slot->base_gfn];
538
44ad9944
JR		 539 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
540 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 541
44ad9944 542 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 543}
544
cd4a4e53
AK		 545/*
546 * Reverse mapping data structures:
547 *
290fc38d
IE		 548 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
549 * that points to page_address(page).
cd4a4e53 550 *
290fc38d
IE		 551 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
552 * containing more mappings.
53a27b39
MT		 553 *
554 * Returns the number of rmap entries before the spte was added or zero if
555 * the spte was not added.
556 *
cd4a4e53 557 */
44ad9944 558static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 559{
4db35314 560 struct kvm_mmu_page *sp;
cd4a4e53 561 struct kvm_rmap_desc *desc;
290fc38d 562 unsigned long *rmapp;
53a27b39 563 int i, count = 0;
cd4a4e53 564
43a3795a 565 if (!is_rmap_spte(*spte))
53a27b39 566 return count;
290fc38d 567 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 568 sp = page_header(__pa(spte));
569 sp->gfns[spte - sp->spt] = gfn;
44ad9944 570 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 571 if (!*rmapp) {
cd4a4e53 572 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 573 *rmapp = (unsigned long)spte;
574 } else if (!(*rmapp & 1)) {
cd4a4e53 575 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 576 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 577 desc->sptes[0] = (u64 *)*rmapp;
578 desc->sptes[1] = spte;
290fc38d 579 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 580 } else {
581 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 582 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 583 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 584 desc = desc->more;
53a27b39
MT		 585 count += RMAP_EXT;
586 }
d555c333 587 if (desc->sptes[RMAP_EXT-1]) {
714b93da 588 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 589 desc = desc->more;
590 }
d555c333 591 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 592 ;
d555c333 593 desc->sptes[i] = spte;
cd4a4e53 594 }
53a27b39 595 return count;
cd4a4e53
AK		 596}
597
290fc38d 598static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 599 struct kvm_rmap_desc *desc,
600 int i,
601 struct kvm_rmap_desc *prev_desc)
602{
603 int j;
604
d555c333 605 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 606 ;
d555c333
AK		 607 desc->sptes[i] = desc->sptes[j];
608 desc->sptes[j] = NULL;
cd4a4e53
AK		 609 if (j != 0)
610 return;
611 if (!prev_desc && !desc->more)
d555c333 612 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 613 else
614 if (prev_desc)
615 prev_desc->more = desc->more;
616 else
290fc38d 617 *rmapp = (unsigned long)desc->more | 1;
90cb0529 618 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 619}
620
290fc38d 621static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 622{
cd4a4e53
AK		 623 struct kvm_rmap_desc *desc;
624 struct kvm_rmap_desc *prev_desc;
4db35314 625 struct kvm_mmu_page *sp;
35149e21 626 pfn_t pfn;
290fc38d 627 unsigned long *rmapp;
cd4a4e53
AK		 628 int i;
629
43a3795a 630 if (!is_rmap_spte(*spte))
cd4a4e53 631 return;
4db35314 632 sp = page_header(__pa(spte));
35149e21 633 pfn = spte_to_pfn(*spte);
7b52345e 634 if (*spte & shadow_accessed_mask)
35149e21 635 kvm_set_pfn_accessed(pfn);
b4231d61 636 if (is_writeble_pte(*spte))
acb66dd0 637 kvm_set_pfn_dirty(pfn);
44ad9944 638 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 639 if (!*rmapp) {
cd4a4e53
AK		 640 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
641 BUG();
290fc38d 642 } else if (!(*rmapp & 1)) {
cd4a4e53 643 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 644 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 645 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
646 spte, *spte);
647 BUG();
648 }
290fc38d 649 *rmapp = 0;
cd4a4e53
AK		 650 } else {
651 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 652 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 653 prev_desc = NULL;
654 while (desc) {
d555c333
AK		 655 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
656 if (desc->sptes[i] == spte) {
290fc38d 657 rmap_desc_remove_entry(rmapp,
714b93da 658 desc, i,
cd4a4e53
AK		 659 prev_desc);
660 return;
661 }
662 prev_desc = desc;
663 desc = desc->more;
664 }
186a3e52 665 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 666 BUG();
667 }
668}
669
98348e95 670static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 671{
374cbac0 672 struct kvm_rmap_desc *desc;
98348e95
IE		 673 struct kvm_rmap_desc *prev_desc;
674 u64 *prev_spte;
675 int i;
676
677 if (!*rmapp)
678 return NULL;
679 else if (!(*rmapp & 1)) {
680 if (!spte)
681 return (u64 *)*rmapp;
682 return NULL;
683 }
684 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
685 prev_desc = NULL;
686 prev_spte = NULL;
687 while (desc) {
d555c333 688 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 689 if (prev_spte == spte)
d555c333
AK		 690 return desc->sptes[i];
691 prev_spte = desc->sptes[i];
98348e95
IE		 692 }
693 desc = desc->more;
694 }
695 return NULL;
696}
697
b1a36821 698static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 699{
290fc38d 700 unsigned long *rmapp;
374cbac0 701 u64 *spte;
44ad9944 702 int i, write_protected = 0;
374cbac0 703
4a4c9924 704 gfn = unalias_gfn(kvm, gfn);
44ad9944 705 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 706
98348e95
IE		 707 spte = rmap_next(kvm, rmapp, NULL);
708 while (spte) {
374cbac0 709 BUG_ON(!spte);
374cbac0 710 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 711 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 712 if (is_writeble_pte(*spte)) {
d555c333 713 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 714 write_protected = 1;
715 }
9647c14c 716 spte = rmap_next(kvm, rmapp, spte);
374cbac0 717 }
855149aa 718 if (write_protected) {
35149e21 719 pfn_t pfn;
855149aa
IE		 720
721 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 722 pfn = spte_to_pfn(*spte);
723 kvm_set_pfn_dirty(pfn);
855149aa
IE		 724 }
725
05da4558 726 /* check for huge page mappings */
44ad9944
JR		 727 for (i = PT_DIRECTORY_LEVEL;
728 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
729 rmapp = gfn_to_rmap(kvm, gfn, i);
730 spte = rmap_next(kvm, rmapp, NULL);
731 while (spte) {
732 BUG_ON(!spte);
733 BUG_ON(!(*spte & PT_PRESENT_MASK));
734 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
735 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
736 if (is_writeble_pte(*spte)) {
737 rmap_remove(kvm, spte);
738 --kvm->stat.lpages;
739 __set_spte(spte, shadow_trap_nonpresent_pte);
740 spte = NULL;
741 write_protected = 1;
742 }
743 spte = rmap_next(kvm, rmapp, spte);
05da4558 744 }
05da4558
MT		 745 }
746
b1a36821 747 return write_protected;
374cbac0
AK		 748}
749
8a8365c5
FD		 750static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
751 unsigned long data)
e930bffe
AA		 752{
753 u64 *spte;
754 int need_tlb_flush = 0;
755
756 while ((spte = rmap_next(kvm, rmapp, NULL))) {
757 BUG_ON(!(*spte & PT_PRESENT_MASK));
758 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
759 rmap_remove(kvm, spte);
d555c333 760 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 761 need_tlb_flush = 1;
762 }
763 return need_tlb_flush;
764}
765
8a8365c5
FD		 766static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
767 unsigned long data)
3da0dd43
IE		 768{
769 int need_flush = 0;
770 u64 *spte, new_spte;
771 pte_t *ptep = (pte_t *)data;
772 pfn_t new_pfn;
773
774 WARN_ON(pte_huge(*ptep));
775 new_pfn = pte_pfn(*ptep);
776 spte = rmap_next(kvm, rmapp, NULL);
777 while (spte) {
778 BUG_ON(!is_shadow_present_pte(*spte));
779 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
780 need_flush = 1;
781 if (pte_write(*ptep)) {
782 rmap_remove(kvm, spte);
783 __set_spte(spte, shadow_trap_nonpresent_pte);
784 spte = rmap_next(kvm, rmapp, NULL);
785 } else {
786 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
787 new_spte |= (u64)new_pfn << PAGE_SHIFT;
788
789 new_spte &= ~PT_WRITABLE_MASK;
790 new_spte &= ~SPTE_HOST_WRITEABLE;
791 if (is_writeble_pte(*spte))
792 kvm_set_pfn_dirty(spte_to_pfn(*spte));
793 __set_spte(spte, new_spte);
794 spte = rmap_next(kvm, rmapp, spte);
795 }
796 }
797 if (need_flush)
798 kvm_flush_remote_tlbs(kvm);
799
800 return 0;
801}
802
8a8365c5
FD		 803static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
804 unsigned long data,
3da0dd43 805 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 806 unsigned long data))
e930bffe 807{
852e3c19 808 int i, j;
e930bffe
AA		 809 int retval = 0;
810
811 /*
812 * If mmap_sem isn't taken, we can look the memslots with only
813 * the mmu_lock by skipping over the slots with userspace_addr == 0.
814 */
815 for (i = 0; i < kvm->nmemslots; i++) {
816 struct kvm_memory_slot *memslot = &kvm->memslots[i];
817 unsigned long start = memslot->userspace_addr;
818 unsigned long end;
819
820 /* mmu_lock protects userspace_addr */
821 if (!start)
822 continue;
823
824 end = start + (memslot->npages << PAGE_SHIFT);
825 if (hva >= start && hva < end) {
826 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 827
3da0dd43
IE		 828 retval |= handler(kvm, &memslot->rmap[gfn_offset],
829 data);
852e3c19
JR		 830
831 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
832 int idx = gfn_offset;
833 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
834 retval |= handler(kvm,
3da0dd43
IE		 835 &memslot->lpage_info[j][idx].rmap_pde,
836 data);
852e3c19 837 }
e930bffe
AA		 838 }
839 }
840
841 return retval;
842}
843
844int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
845{
3da0dd43
IE		 846 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
847}
848
849void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
850{
8a8365c5 851 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 852}
853
8a8365c5
FD		 854static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
855 unsigned long data)
e930bffe
AA		 856{
857 u64 *spte;
858 int young = 0;
859
534e38b4
SY		 860 /* always return old for EPT */
861 if (!shadow_accessed_mask)
862 return 0;
863
e930bffe
AA		 864 spte = rmap_next(kvm, rmapp, NULL);
865 while (spte) {
866 int _young;
867 u64 _spte = *spte;
868 BUG_ON(!(_spte & PT_PRESENT_MASK));
869 _young = _spte & PT_ACCESSED_MASK;
870 if (_young) {
871 young = 1;
872 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
873 }
874 spte = rmap_next(kvm, rmapp, spte);
875 }
876 return young;
877}
878
53a27b39
MT		 879#define RMAP_RECYCLE_THRESHOLD 1000
880
852e3c19 881static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 882{
883 unsigned long *rmapp;
852e3c19
JR		 884 struct kvm_mmu_page *sp;
885
886 sp = page_header(__pa(spte));
53a27b39
MT		 887
888 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 889 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 890
3da0dd43 891 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 892 kvm_flush_remote_tlbs(vcpu->kvm);
893}
894
e930bffe
AA		 895int kvm_age_hva(struct kvm *kvm, unsigned long hva)
896{
3da0dd43 897 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 898}
899
d6c69ee9 900#ifdef MMU_DEBUG
47ad8e68 901static int is_empty_shadow_page(u64 *spt)
6aa8b732 902{
139bdb2d
AK		 903 u64 *pos;
904 u64 *end;
905
47ad8e68 906 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 907 if (is_shadow_present_pte(*pos)) {
b8688d51 908 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 909 pos, *pos);
6aa8b732 910 return 0;
139bdb2d 911 }
6aa8b732
AK		 912 return 1;
913}
d6c69ee9 914#endif
6aa8b732 915
4db35314 916static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 917{
4db35314
AK		 918 ASSERT(is_empty_shadow_page(sp->spt));
919 list_del(&sp->link);
920 __free_page(virt_to_page(sp->spt));
921 __free_page(virt_to_page(sp->gfns));
922 kfree(sp);
f05e70ac 923 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 924}
925
cea0f0e7
AK		 926static unsigned kvm_page_table_hashfn(gfn_t gfn)
927{
1ae0a13d 928 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 929}
930
25c0de2c
AK		 931static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
932 u64 *parent_pte)
6aa8b732 933{
4db35314 934 struct kvm_mmu_page *sp;
6aa8b732 935
ad312c7c
ZX		 936 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
937 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
938 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 939 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 940 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 941 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 942 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 943 sp->multimapped = 0;
944 sp->parent_pte = parent_pte;
f05e70ac 945 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 946 return sp;
6aa8b732
AK		 947}
948
714b93da 949static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 950 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 951{
952 struct kvm_pte_chain *pte_chain;
953 struct hlist_node *node;
954 int i;
955
956 if (!parent_pte)
957 return;
4db35314
AK		 958 if (!sp->multimapped) {
959 u64 *old = sp->parent_pte;
cea0f0e7
AK		 960
961 if (!old) {
4db35314 962 sp->parent_pte = parent_pte;
cea0f0e7
AK		 963 return;
964 }
4db35314 965 sp->multimapped = 1;
714b93da 966 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 967 INIT_HLIST_HEAD(&sp->parent_ptes);
968 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 969 pte_chain->parent_ptes[0] = old;
970 }
4db35314 971 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 972 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
973 continue;
974 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
975 if (!pte_chain->parent_ptes[i]) {
976 pte_chain->parent_ptes[i] = parent_pte;
977 return;
978 }
979 }
714b93da 980 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 981 BUG_ON(!pte_chain);
4db35314 982 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 983 pte_chain->parent_ptes[0] = parent_pte;
984}
985
4db35314 986static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 987 u64 *parent_pte)
988{
989 struct kvm_pte_chain *pte_chain;
990 struct hlist_node *node;
991 int i;
992
4db35314
AK		 993 if (!sp->multimapped) {
994 BUG_ON(sp->parent_pte != parent_pte);
995 sp->parent_pte = NULL;
cea0f0e7
AK		 996 return;
997 }
4db35314 998 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 999 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1000 if (!pte_chain->parent_ptes[i])
1001 break;
1002 if (pte_chain->parent_ptes[i] != parent_pte)
1003 continue;
697fe2e2
AK		 1004 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1005 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1006 pte_chain->parent_ptes[i]
1007 = pte_chain->parent_ptes[i + 1];
1008 ++i;
1009 }
1010 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1011 if (i == 0) {
1012 hlist_del(&pte_chain->link);
90cb0529 1013 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1014 if (hlist_empty(&sp->parent_ptes)) {
1015 sp->multimapped = 0;
1016 sp->parent_pte = NULL;
697fe2e2
AK		 1017 }
1018 }
cea0f0e7
AK		 1019 return;
1020 }
1021 BUG();
1022}
1023
ad8cfbe3
MT		 1024
1025static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1026 mmu_parent_walk_fn fn)
1027{
1028 struct kvm_pte_chain *pte_chain;
1029 struct hlist_node *node;
1030 struct kvm_mmu_page *parent_sp;
1031 int i;
1032
1033 if (!sp->multimapped && sp->parent_pte) {
1034 parent_sp = page_header(__pa(sp->parent_pte));
1035 fn(vcpu, parent_sp);
1036 mmu_parent_walk(vcpu, parent_sp, fn);
1037 return;
1038 }
1039 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1040 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1041 if (!pte_chain->parent_ptes[i])
1042 break;
1043 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1044 fn(vcpu, parent_sp);
1045 mmu_parent_walk(vcpu, parent_sp, fn);
1046 }
1047}
1048
0074ff63
MT		 1049static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1050{
1051 unsigned int index;
1052 struct kvm_mmu_page *sp = page_header(__pa(spte));
1053
1054 index = spte - sp->spt;
60c8aec6
MT		 1055 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1056 sp->unsync_children++;
1057 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1058}
1059
1060static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1061{
1062 struct kvm_pte_chain *pte_chain;
1063 struct hlist_node *node;
1064 int i;
1065
1066 if (!sp->parent_pte)
1067 return;
1068
1069 if (!sp->multimapped) {
1070 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1071 return;
1072 }
1073
1074 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1075 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1076 if (!pte_chain->parent_ptes[i])
1077 break;
1078 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1079 }
1080}
1081
1082static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1083{
0074ff63
MT		 1084 kvm_mmu_update_parents_unsync(sp);
1085 return 1;
1086}
1087
1088static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1089 struct kvm_mmu_page *sp)
1090{
1091 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1092 kvm_mmu_update_parents_unsync(sp);
1093}
1094
d761a501
AK		 1095static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1096 struct kvm_mmu_page *sp)
1097{
1098 int i;
1099
1100 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1101 sp->spt[i] = shadow_trap_nonpresent_pte;
1102}
1103
e8bc217a
MT		 1104static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1105 struct kvm_mmu_page *sp)
1106{
1107 return 1;
1108}
1109
a7052897
MT		 1110static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1111{
1112}
1113
60c8aec6
MT		 1114#define KVM_PAGE_ARRAY_NR 16
1115
1116struct kvm_mmu_pages {
1117 struct mmu_page_and_offset {
1118 struct kvm_mmu_page *sp;
1119 unsigned int idx;
1120 } page[KVM_PAGE_ARRAY_NR];
1121 unsigned int nr;
1122};
1123
0074ff63
MT		 1124#define for_each_unsync_children(bitmap, idx) \
1125 for (idx = find_first_bit(bitmap, 512); \
1126 idx < 512; \
1127 idx = find_next_bit(bitmap, 512, idx+1))
1128
cded19f3
HE		 1129static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1130 int idx)
4731d4c7 1131{
60c8aec6 1132 int i;
4731d4c7 1133
60c8aec6
MT		 1134 if (sp->unsync)
1135 for (i=0; i < pvec->nr; i++)
1136 if (pvec->page[i].sp == sp)
1137 return 0;
1138
1139 pvec->page[pvec->nr].sp = sp;
1140 pvec->page[pvec->nr].idx = idx;
1141 pvec->nr++;
1142 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1143}
1144
1145static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1146 struct kvm_mmu_pages *pvec)
1147{
1148 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1149
0074ff63 1150 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1151 u64 ent = sp->spt[i];
1152
87917239 1153 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1154 struct kvm_mmu_page *child;
1155 child = page_header(ent & PT64_BASE_ADDR_MASK);
1156
1157 if (child->unsync_children) {
60c8aec6
MT		 1158 if (mmu_pages_add(pvec, child, i))
1159 return -ENOSPC;
1160
1161 ret = __mmu_unsync_walk(child, pvec);
1162 if (!ret)
1163 __clear_bit(i, sp->unsync_child_bitmap);
1164 else if (ret > 0)
1165 nr_unsync_leaf += ret;
1166 else
4731d4c7
MT		 1167 return ret;
1168 }
1169
1170 if (child->unsync) {
60c8aec6
MT		 1171 nr_unsync_leaf++;
1172 if (mmu_pages_add(pvec, child, i))
1173 return -ENOSPC;
4731d4c7
MT		 1174 }
1175 }
1176 }
1177
0074ff63 1178 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1179 sp->unsync_children = 0;
1180
60c8aec6
MT		 1181 return nr_unsync_leaf;
1182}
1183
1184static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1185 struct kvm_mmu_pages *pvec)
1186{
1187 if (!sp->unsync_children)
1188 return 0;
1189
1190 mmu_pages_add(pvec, sp, 0);
1191 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1192}
1193
4db35314 1194static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1195{
1196 unsigned index;
1197 struct hlist_head *bucket;
4db35314 1198 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1199 struct hlist_node *node;
1200
b8688d51 1201 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1202 index = kvm_page_table_hashfn(gfn);
f05e70ac 1203 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1204 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1205 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1206 && !sp->role.invalid) {
cea0f0e7 1207 pgprintk("%s: found role %x\n",
b8688d51 1208 __func__, sp->role.word);
4db35314 1209 return sp;
cea0f0e7
AK		 1210 }
1211 return NULL;
1212}
1213
4731d4c7
MT		 1214static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1215{
1216 WARN_ON(!sp->unsync);
1217 sp->unsync = 0;
1218 --kvm->stat.mmu_unsync;
1219}
1220
1221static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1222
1223static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1224{
1225 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1226 kvm_mmu_zap_page(vcpu->kvm, sp);
1227 return 1;
1228 }
1229
f691fe1d 1230 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1231 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1232 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1233 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1234 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1235 kvm_mmu_zap_page(vcpu->kvm, sp);
1236 return 1;
1237 }
1238
1239 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1240 return 0;
1241}
1242
60c8aec6
MT		 1243struct mmu_page_path {
1244 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1245 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1246};
1247
60c8aec6
MT		 1248#define for_each_sp(pvec, sp, parents, i) \
1249 for (i = mmu_pages_next(&pvec, &parents, -1), \
1250 sp = pvec.page[i].sp; \
1251 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1252 i = mmu_pages_next(&pvec, &parents, i))
1253
cded19f3
HE		 1254static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1255 struct mmu_page_path *parents,
1256 int i)
60c8aec6
MT		 1257{
1258 int n;
1259
1260 for (n = i+1; n < pvec->nr; n++) {
1261 struct kvm_mmu_page *sp = pvec->page[n].sp;
1262
1263 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1264 parents->idx[0] = pvec->page[n].idx;
1265 return n;
1266 }
1267
1268 parents->parent[sp->role.level-2] = sp;
1269 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1270 }
1271
1272 return n;
1273}
1274
cded19f3 1275static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1276{
60c8aec6
MT		 1277 struct kvm_mmu_page *sp;
1278 unsigned int level = 0;
1279
1280 do {
1281 unsigned int idx = parents->idx[level];
4731d4c7 1282
60c8aec6
MT		 1283 sp = parents->parent[level];
1284 if (!sp)
1285 return;
1286
1287 --sp->unsync_children;
1288 WARN_ON((int)sp->unsync_children < 0);
1289 __clear_bit(idx, sp->unsync_child_bitmap);
1290 level++;
1291 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1292}
1293
60c8aec6
MT		 1294static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1295 struct mmu_page_path *parents,
1296 struct kvm_mmu_pages *pvec)
4731d4c7 1297{
60c8aec6
MT		 1298 parents->parent[parent->role.level-1] = NULL;
1299 pvec->nr = 0;
1300}
4731d4c7 1301
60c8aec6
MT		 1302static void mmu_sync_children(struct kvm_vcpu *vcpu,
1303 struct kvm_mmu_page *parent)
1304{
1305 int i;
1306 struct kvm_mmu_page *sp;
1307 struct mmu_page_path parents;
1308 struct kvm_mmu_pages pages;
1309
1310 kvm_mmu_pages_init(parent, &parents, &pages);
1311 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1312 int protected = 0;
1313
1314 for_each_sp(pages, sp, parents, i)
1315 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1316
1317 if (protected)
1318 kvm_flush_remote_tlbs(vcpu->kvm);
1319
60c8aec6
MT		 1320 for_each_sp(pages, sp, parents, i) {
1321 kvm_sync_page(vcpu, sp);
1322 mmu_pages_clear_parents(&parents);
1323 }
4731d4c7 1324 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1325 kvm_mmu_pages_init(parent, &parents, &pages);
1326 }
4731d4c7
MT		 1327}
1328
cea0f0e7
AK		 1329static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1330 gfn_t gfn,
1331 gva_t gaddr,
1332 unsigned level,
f6e2c02b 1333 int direct,
41074d07 1334 unsigned access,
f7d9c7b7 1335 u64 *parent_pte)
cea0f0e7
AK		 1336{
1337 union kvm_mmu_page_role role;
1338 unsigned index;
1339 unsigned quadrant;
1340 struct hlist_head *bucket;
4db35314 1341 struct kvm_mmu_page *sp;
4731d4c7 1342 struct hlist_node *node, *tmp;
cea0f0e7 1343
a770f6f2 1344 role = vcpu->arch.mmu.base_role;
cea0f0e7 1345 role.level = level;
f6e2c02b 1346 role.direct = direct;
41074d07 1347 role.access = access;
ad312c7c 1348 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1349 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1350 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1351 role.quadrant = quadrant;
1352 }
1ae0a13d 1353 index = kvm_page_table_hashfn(gfn);
f05e70ac 1354 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1355 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1356 if (sp->gfn == gfn) {
1357 if (sp->unsync)
1358 if (kvm_sync_page(vcpu, sp))
1359 continue;
1360
1361 if (sp->role.word != role.word)
1362 continue;
1363
4db35314 1364 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1365 if (sp->unsync_children) {
1366 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1367 kvm_mmu_mark_parents_unsync(vcpu, sp);
1368 }
f691fe1d 1369 trace_kvm_mmu_get_page(sp, false);
4db35314 1370 return sp;
cea0f0e7 1371 }
dfc5aa00 1372 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1373 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1374 if (!sp)
1375 return sp;
4db35314
AK		 1376 sp->gfn = gfn;
1377 sp->role = role;
1378 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1379 if (!direct) {
b1a36821
MT		 1380 if (rmap_write_protect(vcpu->kvm, gfn))
1381 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1382 account_shadowed(vcpu->kvm, gfn);
1383 }
131d8279
AK		 1384 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1385 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1386 else
1387 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1388 trace_kvm_mmu_get_page(sp, true);
4db35314 1389 return sp;
cea0f0e7
AK		 1390}
1391
2d11123a
AK		 1392static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1393 struct kvm_vcpu *vcpu, u64 addr)
1394{
1395 iterator->addr = addr;
1396 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1397 iterator->level = vcpu->arch.mmu.shadow_root_level;
1398 if (iterator->level == PT32E_ROOT_LEVEL) {
1399 iterator->shadow_addr
1400 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1401 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1402 --iterator->level;
1403 if (!iterator->shadow_addr)
1404 iterator->level = 0;
1405 }
1406}
1407
1408static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1409{
1410 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1411 return false;
4d88954d
MT		 1412
1413 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1414 if (is_large_pte(*iterator->sptep))
1415 return false;
1416
2d11123a
AK		 1417 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1418 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1419 return true;
1420}
1421
1422static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1423{
1424 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1425 --iterator->level;
1426}
1427
90cb0529 1428static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1429 struct kvm_mmu_page *sp)
a436036b 1430{
697fe2e2
AK		 1431 unsigned i;
1432 u64 *pt;
1433 u64 ent;
1434
4db35314 1435 pt = sp->spt;
697fe2e2 1436
697fe2e2
AK		 1437 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1438 ent = pt[i];
1439
05da4558 1440 if (is_shadow_present_pte(ent)) {
776e6633 1441 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1442 ent &= PT64_BASE_ADDR_MASK;
1443 mmu_page_remove_parent_pte(page_header(ent),
1444 &pt[i]);
1445 } else {
776e6633
MT		 1446 if (is_large_pte(ent))
1447 --kvm->stat.lpages;
05da4558
MT		 1448 rmap_remove(kvm, &pt[i]);
1449 }
1450 }
c7addb90 1451 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1452 }
a436036b
AK		 1453}
1454
4db35314 1455static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1456{
4db35314 1457 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1458}
1459
12b7d28f
AK		 1460static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1461{
1462 int i;
988a2cae 1463 struct kvm_vcpu *vcpu;
12b7d28f 1464
988a2cae
GN		 1465 kvm_for_each_vcpu(i, vcpu, kvm)
1466 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1467}
1468
31aa2b44 1469static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1470{
1471 u64 *parent_pte;
1472
4db35314
AK		 1473 while (sp->multimapped || sp->parent_pte) {
1474 if (!sp->multimapped)
1475 parent_pte = sp->parent_pte;
a436036b
AK		 1476 else {
1477 struct kvm_pte_chain *chain;
1478
4db35314 1479 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1480 struct kvm_pte_chain, link);
1481 parent_pte = chain->parent_ptes[0];
1482 }
697fe2e2 1483 BUG_ON(!parent_pte);
4db35314 1484 kvm_mmu_put_page(sp, parent_pte);
d555c333 1485 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1486 }
31aa2b44
AK		 1487}
1488
60c8aec6
MT		 1489static int mmu_zap_unsync_children(struct kvm *kvm,
1490 struct kvm_mmu_page *parent)
4731d4c7 1491{
60c8aec6
MT		 1492 int i, zapped = 0;
1493 struct mmu_page_path parents;
1494 struct kvm_mmu_pages pages;
4731d4c7 1495
60c8aec6 1496 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1497 return 0;
60c8aec6
MT		 1498
1499 kvm_mmu_pages_init(parent, &parents, &pages);
1500 while (mmu_unsync_walk(parent, &pages)) {
1501 struct kvm_mmu_page *sp;
1502
1503 for_each_sp(pages, sp, parents, i) {
1504 kvm_mmu_zap_page(kvm, sp);
1505 mmu_pages_clear_parents(&parents);
1506 }
1507 zapped += pages.nr;
1508 kvm_mmu_pages_init(parent, &parents, &pages);
1509 }
1510
1511 return zapped;
4731d4c7
MT		 1512}
1513
07385413 1514static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1515{
4731d4c7 1516 int ret;
f691fe1d
AK		 1517
1518 trace_kvm_mmu_zap_page(sp);
31aa2b44 1519 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1520 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1521 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1522 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1523 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1524 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1525 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1526 if (sp->unsync)
1527 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1528 if (!sp->root_count) {
1529 hlist_del(&sp->hash_link);
1530 kvm_mmu_free_page(kvm, sp);
2e53d63a 1531 } else {
2e53d63a 1532 sp->role.invalid = 1;
5b5c6a5a 1533 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1534 kvm_reload_remote_mmus(kvm);
1535 }
12b7d28f 1536 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1537 return ret;
a436036b
AK		 1538}
1539
82ce2c96
IE		 1540/*
1541 * Changing the number of mmu pages allocated to the vm
1542 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1543 */
1544void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1545{
025dbbf3
MT		 1546 int used_pages;
1547
1548 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1549 used_pages = max(0, used_pages);
1550
82ce2c96
IE		 1551 /*
1552 * If we set the number of mmu pages to be smaller be than the
1553 * number of actived pages , we must to free some mmu pages before we
1554 * change the value
1555 */
1556
025dbbf3
MT		 1557 if (used_pages > kvm_nr_mmu_pages) {
1558 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1559 struct kvm_mmu_page *page;
1560
f05e70ac 1561 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1562 struct kvm_mmu_page, link);
1563 kvm_mmu_zap_page(kvm, page);
025dbbf3 1564 used_pages--;
82ce2c96 1565 }
f05e70ac 1566 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1567 }
1568 else
f05e70ac
ZX		 1569 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1570 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1571
f05e70ac 1572 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1573}
1574
f67a46f4 1575static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1576{
1577 unsigned index;
1578 struct hlist_head *bucket;
4db35314 1579 struct kvm_mmu_page *sp;
a436036b
AK		 1580 struct hlist_node *node, *n;
1581 int r;
1582
b8688d51 1583 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1584 r = 0;
1ae0a13d 1585 index = kvm_page_table_hashfn(gfn);
f05e70ac 1586 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1587 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1588 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1589 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1590 sp->role.word);
a436036b 1591 r = 1;
07385413
MT		 1592 if (kvm_mmu_zap_page(kvm, sp))
1593 n = bucket->first;
a436036b
AK		 1594 }
1595 return r;
cea0f0e7
AK		 1596}
1597
f67a46f4 1598static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1599{
4677a3b6
AK		 1600 unsigned index;
1601 struct hlist_head *bucket;
4db35314 1602 struct kvm_mmu_page *sp;
4677a3b6 1603 struct hlist_node *node, *nn;
97a0a01e 1604
4677a3b6
AK		 1605 index = kvm_page_table_hashfn(gfn);
1606 bucket = &kvm->arch.mmu_page_hash[index];
1607 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1608 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1609 && !sp->role.invalid) {
1610 pgprintk("%s: zap %lx %x\n",
1611 __func__, gfn, sp->role.word);
1612 kvm_mmu_zap_page(kvm, sp);
1613 }
97a0a01e
AK		 1614 }
1615}
1616
38c335f1 1617static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1618{
38c335f1 1619 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 1620 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1621
291f26bc 1622 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1623}
1624
6844dec6
MT		 1625static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1626{
1627 int i;
1628 u64 *pt = sp->spt;
1629
1630 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1631 return;
1632
1633 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1634 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1635 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1636 }
1637}
1638
039576c0
AK		 1639struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1640{
72dc67a6
IE		 1641 struct page *page;
1642
ad312c7c 1643 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1644
1645 if (gpa == UNMAPPED_GVA)
1646 return NULL;
72dc67a6 1647
72dc67a6 1648 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1649
1650 return page;
039576c0
AK		 1651}
1652
74be52e3
SY		 1653/*
1654 * The function is based on mtrr_type_lookup() in
1655 * arch/x86/kernel/cpu/mtrr/generic.c
1656 */
1657static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1658 u64 start, u64 end)
1659{
1660 int i;
1661 u64 base, mask;
1662 u8 prev_match, curr_match;
1663 int num_var_ranges = KVM_NR_VAR_MTRR;
1664
1665 if (!mtrr_state->enabled)
1666 return 0xFF;
1667
1668 /* Make end inclusive end, instead of exclusive */
1669 end--;
1670
1671 /* Look in fixed ranges. Just return the type as per start */
1672 if (mtrr_state->have_fixed && (start < 0x100000)) {
1673 int idx;
1674
1675 if (start < 0x80000) {
1676 idx = 0;
1677 idx += (start >> 16);
1678 return mtrr_state->fixed_ranges[idx];
1679 } else if (start < 0xC0000) {
1680 idx = 1 * 8;
1681 idx += ((start - 0x80000) >> 14);
1682 return mtrr_state->fixed_ranges[idx];
1683 } else if (start < 0x1000000) {
1684 idx = 3 * 8;
1685 idx += ((start - 0xC0000) >> 12);
1686 return mtrr_state->fixed_ranges[idx];
1687 }
1688 }
1689
1690 /*
1691 * Look in variable ranges
1692 * Look of multiple ranges matching this address and pick type
1693 * as per MTRR precedence
1694 */
1695 if (!(mtrr_state->enabled & 2))
1696 return mtrr_state->def_type;
1697
1698 prev_match = 0xFF;
1699 for (i = 0; i < num_var_ranges; ++i) {
1700 unsigned short start_state, end_state;
1701
1702 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1703 continue;
1704
1705 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1706 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1707 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1708 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1709
1710 start_state = ((start & mask) == (base & mask));
1711 end_state = ((end & mask) == (base & mask));
1712 if (start_state != end_state)
1713 return 0xFE;
1714
1715 if ((start & mask) != (base & mask))
1716 continue;
1717
1718 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1719 if (prev_match == 0xFF) {
1720 prev_match = curr_match;
1721 continue;
1722 }
1723
1724 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1725 curr_match == MTRR_TYPE_UNCACHABLE)
1726 return MTRR_TYPE_UNCACHABLE;
1727
1728 if ((prev_match == MTRR_TYPE_WRBACK &&
1729 curr_match == MTRR_TYPE_WRTHROUGH) ||
1730 (prev_match == MTRR_TYPE_WRTHROUGH &&
1731 curr_match == MTRR_TYPE_WRBACK)) {
1732 prev_match = MTRR_TYPE_WRTHROUGH;
1733 curr_match = MTRR_TYPE_WRTHROUGH;
1734 }
1735
1736 if (prev_match != curr_match)
1737 return MTRR_TYPE_UNCACHABLE;
1738 }
1739
1740 if (prev_match != 0xFF)
1741 return prev_match;
1742
1743 return mtrr_state->def_type;
1744}
1745
4b12f0de 1746u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1747{
1748 u8 mtrr;
1749
1750 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1751 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1752 if (mtrr == 0xfe || mtrr == 0xff)
1753 mtrr = MTRR_TYPE_WRBACK;
1754 return mtrr;
1755}
4b12f0de 1756EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1757
4731d4c7
MT		 1758static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1759{
1760 unsigned index;
1761 struct hlist_head *bucket;
1762 struct kvm_mmu_page *s;
1763 struct hlist_node *node, *n;
1764
f691fe1d 1765 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1766 index = kvm_page_table_hashfn(sp->gfn);
1767 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1768 /* don't unsync if pagetable is shadowed with multiple roles */
1769 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1770 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1771 continue;
1772 if (s->role.word != sp->role.word)
1773 return 1;
1774 }
4731d4c7
MT		 1775 ++vcpu->kvm->stat.mmu_unsync;
1776 sp->unsync = 1;
6cffe8ca 1777
c2d0ee46 1778 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1779
4731d4c7
MT		 1780 mmu_convert_notrap(sp);
1781 return 0;
1782}
1783
1784static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1785 bool can_unsync)
1786{
1787 struct kvm_mmu_page *shadow;
1788
1789 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1790 if (shadow) {
1791 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1792 return 1;
1793 if (shadow->unsync)
1794 return 0;
582801a9 1795 if (can_unsync && oos_shadow)
4731d4c7
MT		 1796 return kvm_unsync_page(vcpu, shadow);
1797 return 1;
1798 }
1799 return 0;
1800}
1801
d555c333 1802static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1803 unsigned pte_access, int user_fault,
852e3c19 1804 int write_fault, int dirty, int level,
c2d0ee46 1805 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1806 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1807{
1808 u64 spte;
1e73f9dd 1809 int ret = 0;
64d4d521 1810
1c4f1fd6
AK		 1811 /*
1812 * We don't set the accessed bit, since we sometimes want to see
1813 * whether the guest actually used the pte (in order to detect
1814 * demand paging).
1815 */
7b52345e 1816 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1817 if (!speculative)
3201b5d9 1818 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1819 if (!dirty)
1820 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1821 if (pte_access & ACC_EXEC_MASK)
1822 spte |= shadow_x_mask;
1823 else
1824 spte |= shadow_nx_mask;
1c4f1fd6 1825 if (pte_access & ACC_USER_MASK)
7b52345e 1826 spte |= shadow_user_mask;
852e3c19 1827 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1828 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1829 if (tdp_enabled)
1830 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1831 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1832
1403283a
IE		 1833 if (reset_host_protection)
1834 spte |= SPTE_HOST_WRITEABLE;
1835
35149e21 1836 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1837
1838 if ((pte_access & ACC_WRITE_MASK)
1839 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1840
852e3c19
JR		 1841 if (level > PT_PAGE_TABLE_LEVEL &&
1842 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1843 ret = 1;
1844 spte = shadow_trap_nonpresent_pte;
1845 goto set_pte;
1846 }
1847
1c4f1fd6 1848 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1849
ecc5589f
MT		 1850 /*
1851 * Optimization: for pte sync, if spte was writable the hash
1852 * lookup is unnecessary (and expensive). Write protection
1853 * is responsibility of mmu_get_page / kvm_sync_page.
1854 * Same reasoning can be applied to dirty page accounting.
1855 */
d555c333 1856 if (!can_unsync && is_writeble_pte(*sptep))
ecc5589f
MT		 1857 goto set_pte;
1858
4731d4c7 1859 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1860 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1861 __func__, gfn);
1e73f9dd 1862 ret = 1;
1c4f1fd6 1863 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1864 if (is_writeble_pte(spte))
1c4f1fd6 1865 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1866 }
1867 }
1868
1c4f1fd6
AK		 1869 if (pte_access & ACC_WRITE_MASK)
1870 mark_page_dirty(vcpu->kvm, gfn);
1871
38187c83 1872set_pte:
d555c333 1873 __set_spte(sptep, spte);
1e73f9dd
MT		 1874 return ret;
1875}
1876
d555c333 1877static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1878 unsigned pt_access, unsigned pte_access,
1879 int user_fault, int write_fault, int dirty,
852e3c19 1880 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1881 pfn_t pfn, bool speculative,
1882 bool reset_host_protection)
1e73f9dd
MT		 1883{
1884 int was_rmapped = 0;
d555c333 1885 int was_writeble = is_writeble_pte(*sptep);
53a27b39 1886 int rmap_count;
1e73f9dd
MT		 1887
1888 pgprintk("%s: spte %llx access %x write_fault %d"
1889 " user_fault %d gfn %lx\n",
d555c333 1890 __func__, *sptep, pt_access,
1e73f9dd
MT		 1891 write_fault, user_fault, gfn);
1892
d555c333 1893 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1894 /*
1895 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1896 * the parent of the now unreachable PTE.
1897 */
852e3c19
JR		 1898 if (level > PT_PAGE_TABLE_LEVEL &&
1899 !is_large_pte(*sptep)) {
1e73f9dd 1900 struct kvm_mmu_page *child;
d555c333 1901 u64 pte = *sptep;
1e73f9dd
MT		 1902
1903 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1904 mmu_page_remove_parent_pte(child, sptep);
1905 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1906 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1907 spte_to_pfn(*sptep), pfn);
1908 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1909 } else
1910 was_rmapped = 1;
1e73f9dd 1911 }
852e3c19 1912
d555c333 1913 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1914 dirty, level, gfn, pfn, speculative, true,
1915 reset_host_protection)) {
1e73f9dd
MT		 1916 if (write_fault)
1917 *ptwrite = 1;
a378b4e6
MT		 1918 kvm_x86_ops->tlb_flush(vcpu);
1919 }
1e73f9dd 1920
d555c333 1921 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1922 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1923 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1924 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1925 *sptep, sptep);
d555c333 1926 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1927 ++vcpu->kvm->stat.lpages;
1928
d555c333 1929 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1930 if (!was_rmapped) {
44ad9944 1931 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1932 kvm_release_pfn_clean(pfn);
53a27b39 1933 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1934 rmap_recycle(vcpu, sptep, gfn);
75e68e60
IE		 1935 } else {
1936 if (was_writeble)
35149e21 1937 kvm_release_pfn_dirty(pfn);
75e68e60 1938 else
35149e21 1939 kvm_release_pfn_clean(pfn);
1c4f1fd6 1940 }
1b7fcd32 1941 if (speculative) {
d555c333 1942 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1943 vcpu->arch.last_pte_gfn = gfn;
1944 }
1c4f1fd6
AK		 1945}
1946
6aa8b732
AK		 1947static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1948{
1949}
1950
9f652d21 1951static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1952 int level, gfn_t gfn, pfn_t pfn)
140754bc 1953{
9f652d21 1954 struct kvm_shadow_walk_iterator iterator;
140754bc 1955 struct kvm_mmu_page *sp;
9f652d21 1956 int pt_write = 0;
140754bc 1957 gfn_t pseudo_gfn;
6aa8b732 1958
9f652d21 1959 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1960 if (iterator.level == level) {
9f652d21
AK		 1961 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1962 0, write, 1, &pt_write,
1403283a 1963 level, gfn, pfn, false, true);
9f652d21
AK		 1964 ++vcpu->stat.pf_fixed;
1965 break;
6aa8b732
AK		 1966 }
1967
9f652d21
AK		 1968 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1969 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1970 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1971 iterator.level - 1,
1972 1, ACC_ALL, iterator.sptep);
1973 if (!sp) {
1974 pgprintk("nonpaging_map: ENOMEM\n");
1975 kvm_release_pfn_clean(pfn);
1976 return -ENOMEM;
1977 }
140754bc 1978
d555c333
AK		 1979 __set_spte(iterator.sptep,
1980 __pa(sp->spt)
1981 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1982 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1983 }
1984 }
1985 return pt_write;
6aa8b732
AK		 1986}
1987
10589a46
MT		 1988static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1989{
1990 int r;
852e3c19 1991 int level;
35149e21 1992 pfn_t pfn;
e930bffe 1993 unsigned long mmu_seq;
aaee2c94 1994
852e3c19
JR		 1995 level = mapping_level(vcpu, gfn);
1996
1997 /*
1998 * This path builds a PAE pagetable - so we can map 2mb pages at
1999 * maximum. Therefore check if the level is larger than that.
2000 */
2001 if (level > PT_DIRECTORY_LEVEL)
2002 level = PT_DIRECTORY_LEVEL;
2003
2004 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2005
e930bffe 2006 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2007 smp_rmb();
35149e21 2008 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2009
d196e343 2010 /* mmio */
35149e21
AL		 2011 if (is_error_pfn(pfn)) {
2012 kvm_release_pfn_clean(pfn);
d196e343
AK		 2013 return 1;
2014 }
2015
aaee2c94 2016 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2017 if (mmu_notifier_retry(vcpu, mmu_seq))
2018 goto out_unlock;
eb787d10 2019 kvm_mmu_free_some_pages(vcpu);
852e3c19 2020 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2021 spin_unlock(&vcpu->kvm->mmu_lock);
2022
aaee2c94 2023
10589a46 2024 return r;
e930bffe
AA		 2025
2026out_unlock:
2027 spin_unlock(&vcpu->kvm->mmu_lock);
2028 kvm_release_pfn_clean(pfn);
2029 return 0;
10589a46
MT		 2030}
2031
2032
17ac10ad
AK		 2033static void mmu_free_roots(struct kvm_vcpu *vcpu)
2034{
2035 int i;
4db35314 2036 struct kvm_mmu_page *sp;
17ac10ad 2037
ad312c7c 2038 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2039 return;
aaee2c94 2040 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2041 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2042 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2043
4db35314
AK		 2044 sp = page_header(root);
2045 --sp->root_count;
2e53d63a
MT		 2046 if (!sp->root_count && sp->role.invalid)
2047 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2048 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2049 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2050 return;
2051 }
17ac10ad 2052 for (i = 0; i < 4; ++i) {
ad312c7c 2053 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2054
417726a3 2055 if (root) {
417726a3 2056 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2057 sp = page_header(root);
2058 --sp->root_count;
2e53d63a
MT		 2059 if (!sp->root_count && sp->role.invalid)
2060 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2061 }
ad312c7c 2062 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2063 }
aaee2c94 2064 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2065 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2066}
2067
8986ecc0
MT		 2068static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2069{
2070 int ret = 0;
2071
2072 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2073 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2074 ret = 1;
2075 }
2076
2077 return ret;
2078}
2079
2080static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2081{
2082 int i;
cea0f0e7 2083 gfn_t root_gfn;
4db35314 2084 struct kvm_mmu_page *sp;
f6e2c02b 2085 int direct = 0;
6de4f3ad 2086 u64 pdptr;
3bb65a22 2087
ad312c7c 2088 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2089
ad312c7c
ZX		 2090 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2091 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2092
2093 ASSERT(!VALID_PAGE(root));
fb72d167 2094 if (tdp_enabled)
f6e2c02b 2095 direct = 1;
8986ecc0
MT		 2096 if (mmu_check_root(vcpu, root_gfn))
2097 return 1;
4db35314 2098 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2099 PT64_ROOT_LEVEL, direct,
fb72d167 2100 ACC_ALL, NULL);
4db35314
AK		 2101 root = __pa(sp->spt);
2102 ++sp->root_count;
ad312c7c 2103 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2104 return 0;
17ac10ad 2105 }
f6e2c02b 2106 direct = !is_paging(vcpu);
fb72d167 2107 if (tdp_enabled)
f6e2c02b 2108 direct = 1;
17ac10ad 2109 for (i = 0; i < 4; ++i) {
ad312c7c 2110 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2111
2112 ASSERT(!VALID_PAGE(root));
ad312c7c 2113 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2114 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2115 if (!is_present_gpte(pdptr)) {
ad312c7c 2116 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2117 continue;
2118 }
6de4f3ad 2119 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2120 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2121 root_gfn = 0;
8986ecc0
MT		 2122 if (mmu_check_root(vcpu, root_gfn))
2123 return 1;
4db35314 2124 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2125 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2126 ACC_ALL, NULL);
4db35314
AK		 2127 root = __pa(sp->spt);
2128 ++sp->root_count;
ad312c7c 2129 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2130 }
ad312c7c 2131 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2132 return 0;
17ac10ad
AK		 2133}
2134
0ba73cda
MT		 2135static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2136{
2137 int i;
2138 struct kvm_mmu_page *sp;
2139
2140 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2141 return;
2142 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2143 hpa_t root = vcpu->arch.mmu.root_hpa;
2144 sp = page_header(root);
2145 mmu_sync_children(vcpu, sp);
2146 return;
2147 }
2148 for (i = 0; i < 4; ++i) {
2149 hpa_t root = vcpu->arch.mmu.pae_root[i];
2150
8986ecc0 2151 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2152 root &= PT64_BASE_ADDR_MASK;
2153 sp = page_header(root);
2154 mmu_sync_children(vcpu, sp);
2155 }
2156 }
2157}
2158
2159void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2160{
2161 spin_lock(&vcpu->kvm->mmu_lock);
2162 mmu_sync_roots(vcpu);
6cffe8ca 2163 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2164}
2165
6aa8b732
AK		 2166static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2167{
2168 return vaddr;
2169}
2170
2171static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2172 u32 error_code)
6aa8b732 2173{
e833240f 2174 gfn_t gfn;
e2dec939 2175 int r;
6aa8b732 2176
b8688d51 2177 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2178 r = mmu_topup_memory_caches(vcpu);
2179 if (r)
2180 return r;
714b93da 2181
6aa8b732 2182 ASSERT(vcpu);
ad312c7c 2183 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2184
e833240f 2185 gfn = gva >> PAGE_SHIFT;
6aa8b732 2186
e833240f
AK		 2187 return nonpaging_map(vcpu, gva & PAGE_MASK,
2188 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2189}
2190
fb72d167
JR		 2191static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2192 u32 error_code)
2193{
35149e21 2194 pfn_t pfn;
fb72d167 2195 int r;
852e3c19 2196 int level;
05da4558 2197 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2198 unsigned long mmu_seq;
fb72d167
JR		 2199
2200 ASSERT(vcpu);
2201 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2202
2203 r = mmu_topup_memory_caches(vcpu);
2204 if (r)
2205 return r;
2206
852e3c19
JR		 2207 level = mapping_level(vcpu, gfn);
2208
2209 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2210
e930bffe 2211 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2212 smp_rmb();
35149e21 2213 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2214 if (is_error_pfn(pfn)) {
2215 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2216 return 1;
2217 }
2218 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2219 if (mmu_notifier_retry(vcpu, mmu_seq))
2220 goto out_unlock;
fb72d167
JR		 2221 kvm_mmu_free_some_pages(vcpu);
2222 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2223 level, gfn, pfn);
fb72d167 2224 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2225
2226 return r;
e930bffe
AA		 2227
2228out_unlock:
2229 spin_unlock(&vcpu->kvm->mmu_lock);
2230 kvm_release_pfn_clean(pfn);
2231 return 0;
fb72d167
JR		 2232}
2233
6aa8b732
AK		 2234static void nonpaging_free(struct kvm_vcpu *vcpu)
2235{
17ac10ad 2236 mmu_free_roots(vcpu);
6aa8b732
AK		 2237}
2238
2239static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2240{
ad312c7c 2241 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2242
2243 context->new_cr3 = nonpaging_new_cr3;
2244 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2245 context->gva_to_gpa = nonpaging_gva_to_gpa;
2246 context->free = nonpaging_free;
c7addb90 2247 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2248 context->sync_page = nonpaging_sync_page;
a7052897 2249 context->invlpg = nonpaging_invlpg;
cea0f0e7 2250 context->root_level = 0;
6aa8b732 2251 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2252 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2253 return 0;
2254}
2255
d835dfec 2256void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2257{
1165f5fe 2258 ++vcpu->stat.tlb_flush;
cbdd1bea 2259 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2260}
2261
2262static void paging_new_cr3(struct kvm_vcpu *vcpu)
2263{
b8688d51 2264 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2265 mmu_free_roots(vcpu);
6aa8b732
AK		 2266}
2267
6aa8b732
AK		 2268static void inject_page_fault(struct kvm_vcpu *vcpu,
2269 u64 addr,
2270 u32 err_code)
2271{
c3c91fee 2272 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2273}
2274
6aa8b732
AK		 2275static void paging_free(struct kvm_vcpu *vcpu)
2276{
2277 nonpaging_free(vcpu);
2278}
2279
82725b20
DE		 2280static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2281{
2282 int bit7;
2283
2284 bit7 = (gpte >> 7) & 1;
2285 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2286}
2287
6aa8b732
AK		 2288#define PTTYPE 64
2289#include "paging_tmpl.h"
2290#undef PTTYPE
2291
2292#define PTTYPE 32
2293#include "paging_tmpl.h"
2294#undef PTTYPE
2295
82725b20
DE		 2296static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2297{
2298 struct kvm_mmu *context = &vcpu->arch.mmu;
2299 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2300 u64 exb_bit_rsvd = 0;
2301
2302 if (!is_nx(vcpu))
2303 exb_bit_rsvd = rsvd_bits(63, 63);
2304 switch (level) {
2305 case PT32_ROOT_LEVEL:
2306 /* no rsvd bits for 2 level 4K page table entries */
2307 context->rsvd_bits_mask[0][1] = 0;
2308 context->rsvd_bits_mask[0][0] = 0;
2309 if (is_cpuid_PSE36())
2310 /* 36bits PSE 4MB page */
2311 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2312 else
2313 /* 32 bits PSE 4MB page */
2314 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2315 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2316 break;
2317 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2318 context->rsvd_bits_mask[0][2] =
2319 rsvd_bits(maxphyaddr, 63) |
2320 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2321 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2322 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2323 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2324 rsvd_bits(maxphyaddr, 62); /* PTE */
2325 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2326 rsvd_bits(maxphyaddr, 62) |
2327 rsvd_bits(13, 20); /* large page */
29a4b933 2328 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2329 break;
2330 case PT64_ROOT_LEVEL:
2331 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2332 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2333 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2334 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2335 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2336 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2337 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2338 rsvd_bits(maxphyaddr, 51);
2339 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2340 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2341 rsvd_bits(maxphyaddr, 51) |
2342 rsvd_bits(13, 29);
82725b20 2343 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2344 rsvd_bits(maxphyaddr, 51) |
2345 rsvd_bits(13, 20); /* large page */
29a4b933 2346 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2347 break;
2348 }
2349}
2350
17ac10ad 2351static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2352{
ad312c7c 2353 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2354
2355 ASSERT(is_pae(vcpu));
2356 context->new_cr3 = paging_new_cr3;
2357 context->page_fault = paging64_page_fault;
6aa8b732 2358 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2359 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2360 context->sync_page = paging64_sync_page;
a7052897 2361 context->invlpg = paging64_invlpg;
6aa8b732 2362 context->free = paging_free;
17ac10ad
AK		 2363 context->root_level = level;
2364 context->shadow_root_level = level;
17c3ba9d 2365 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2366 return 0;
2367}
2368
17ac10ad
AK		 2369static int paging64_init_context(struct kvm_vcpu *vcpu)
2370{
82725b20 2371 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2372 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2373}
2374
6aa8b732
AK		 2375static int paging32_init_context(struct kvm_vcpu *vcpu)
2376{
ad312c7c 2377 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2378
82725b20 2379 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2380 context->new_cr3 = paging_new_cr3;
2381 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2382 context->gva_to_gpa = paging32_gva_to_gpa;
2383 context->free = paging_free;
c7addb90 2384 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2385 context->sync_page = paging32_sync_page;
a7052897 2386 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2387 context->root_level = PT32_ROOT_LEVEL;
2388 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2389 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2390 return 0;
2391}
2392
2393static int paging32E_init_context(struct kvm_vcpu *vcpu)
2394{
82725b20 2395 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2396 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2397}
2398
fb72d167
JR		 2399static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2400{
2401 struct kvm_mmu *context = &vcpu->arch.mmu;
2402
2403 context->new_cr3 = nonpaging_new_cr3;
2404 context->page_fault = tdp_page_fault;
2405 context->free = nonpaging_free;
2406 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2407 context->sync_page = nonpaging_sync_page;
a7052897 2408 context->invlpg = nonpaging_invlpg;
67253af5 2409 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2410 context->root_hpa = INVALID_PAGE;
2411
2412 if (!is_paging(vcpu)) {
2413 context->gva_to_gpa = nonpaging_gva_to_gpa;
2414 context->root_level = 0;
2415 } else if (is_long_mode(vcpu)) {
82725b20 2416 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2417 context->gva_to_gpa = paging64_gva_to_gpa;
2418 context->root_level = PT64_ROOT_LEVEL;
2419 } else if (is_pae(vcpu)) {
82725b20 2420 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2421 context->gva_to_gpa = paging64_gva_to_gpa;
2422 context->root_level = PT32E_ROOT_LEVEL;
2423 } else {
82725b20 2424 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2425 context->gva_to_gpa = paging32_gva_to_gpa;
2426 context->root_level = PT32_ROOT_LEVEL;
2427 }
2428
2429 return 0;
2430}
2431
2432static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2433{
a770f6f2
AK		 2434 int r;
2435
6aa8b732 2436 ASSERT(vcpu);
ad312c7c 2437 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2438
2439 if (!is_paging(vcpu))
a770f6f2 2440 r = nonpaging_init_context(vcpu);
a9058ecd 2441 else if (is_long_mode(vcpu))
a770f6f2 2442 r = paging64_init_context(vcpu);
6aa8b732 2443 else if (is_pae(vcpu))
a770f6f2 2444 r = paging32E_init_context(vcpu);
6aa8b732 2445 else
a770f6f2
AK		 2446 r = paging32_init_context(vcpu);
2447
2448 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2449
2450 return r;
6aa8b732
AK		 2451}
2452
fb72d167
JR		 2453static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2454{
35149e21
AL		 2455 vcpu->arch.update_pte.pfn = bad_pfn;
2456
fb72d167
JR		 2457 if (tdp_enabled)
2458 return init_kvm_tdp_mmu(vcpu);
2459 else
2460 return init_kvm_softmmu(vcpu);
2461}
2462
6aa8b732
AK		 2463static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2464{
2465 ASSERT(vcpu);
ad312c7c
ZX		 2466 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2467 vcpu->arch.mmu.free(vcpu);
2468 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2469 }
2470}
2471
2472int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2473{
2474 destroy_kvm_mmu(vcpu);
2475 return init_kvm_mmu(vcpu);
2476}
8668a3c4 2477EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2478
2479int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2480{
714b93da
AK		 2481 int r;
2482
e2dec939 2483 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2484 if (r)
2485 goto out;
aaee2c94 2486 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2487 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2488 r = mmu_alloc_roots(vcpu);
0ba73cda 2489 mmu_sync_roots(vcpu);
aaee2c94 2490 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2491 if (r)
2492 goto out;
3662cb1c 2493 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2494 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2495out:
2496 return r;
6aa8b732 2497}
17c3ba9d
AK		 2498EXPORT_SYMBOL_GPL(kvm_mmu_load);
2499
2500void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2501{
2502 mmu_free_roots(vcpu);
2503}
6aa8b732 2504
09072daf 2505static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2506 struct kvm_mmu_page *sp,
ac1b714e
AK		 2507 u64 *spte)
2508{
2509 u64 pte;
2510 struct kvm_mmu_page *child;
2511
2512 pte = *spte;
c7addb90 2513 if (is_shadow_present_pte(pte)) {
776e6633 2514 if (is_last_spte(pte, sp->role.level))
290fc38d 2515 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2516 else {
2517 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2518 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2519 }
2520 }
d555c333 2521 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2522 if (is_large_pte(pte))
2523 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2524}
2525
0028425f 2526static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2527 struct kvm_mmu_page *sp,
0028425f 2528 u64 *spte,
489f1d65 2529 const void *new)
0028425f 2530{
30945387 2531 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2532 ++vcpu->kvm->stat.mmu_pde_zapped;
2533 return;
30945387 2534 }
0028425f 2535
4cee5764 2536 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2537 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2538 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2539 else
489f1d65 2540 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2541}
2542
79539cec
AK		 2543static bool need_remote_flush(u64 old, u64 new)
2544{
2545 if (!is_shadow_present_pte(old))
2546 return false;
2547 if (!is_shadow_present_pte(new))
2548 return true;
2549 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2550 return true;
2551 old ^= PT64_NX_MASK;
2552 new ^= PT64_NX_MASK;
2553 return (old & ~new & PT64_PERM_MASK) != 0;
2554}
2555
2556static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2557{
2558 if (need_remote_flush(old, new))
2559 kvm_flush_remote_tlbs(vcpu->kvm);
2560 else
2561 kvm_mmu_flush_tlb(vcpu);
2562}
2563
12b7d28f
AK		 2564static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2565{
ad312c7c 2566 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2567
7b52345e 2568 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2569}
2570
d7824fff
AK		 2571static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2572 const u8 *new, int bytes)
2573{
2574 gfn_t gfn;
2575 int r;
2576 u64 gpte = 0;
35149e21 2577 pfn_t pfn;
d7824fff
AK		 2578
2579 if (bytes != 4 && bytes != 8)
2580 return;
2581
2582 /*
2583 * Assume that the pte write on a page table of the same type
2584 * as the current vcpu paging mode. This is nearly always true
2585 * (might be false while changing modes). Note it is verified later
2586 * by update_pte().
2587 */
2588 if (is_pae(vcpu)) {
2589 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2590 if ((bytes == 4) && (gpa % 4 == 0)) {
2591 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2592 if (r)
2593 return;
2594 memcpy((void *)&gpte + (gpa % 8), new, 4);
2595 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2596 memcpy((void *)&gpte, new, 8);
2597 }
2598 } else {
2599 if ((bytes == 4) && (gpa % 4 == 0))
2600 memcpy((void *)&gpte, new, 4);
2601 }
43a3795a 2602 if (!is_present_gpte(gpte))
d7824fff
AK		 2603 return;
2604 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2605
e930bffe 2606 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2607 smp_rmb();
35149e21 2608 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2609
35149e21
AL		 2610 if (is_error_pfn(pfn)) {
2611 kvm_release_pfn_clean(pfn);
d196e343
AK		 2612 return;
2613 }
d7824fff 2614 vcpu->arch.update_pte.gfn = gfn;
35149e21 2615 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2616}
2617
1b7fcd32
AK		 2618static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2619{
2620 u64 *spte = vcpu->arch.last_pte_updated;
2621
2622 if (spte
2623 && vcpu->arch.last_pte_gfn == gfn
2624 && shadow_accessed_mask
2625 && !(*spte & shadow_accessed_mask)
2626 && is_shadow_present_pte(*spte))
2627 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2628}
2629
09072daf 2630void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2631 const u8 *new, int bytes,
2632 bool guest_initiated)
da4a00f0 2633{
9b7a0325 2634 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2635 struct kvm_mmu_page *sp;
0e7bc4b9 2636 struct hlist_node *node, *n;
9b7a0325
AK		 2637 struct hlist_head *bucket;
2638 unsigned index;
489f1d65 2639 u64 entry, gentry;
9b7a0325 2640 u64 *spte;
9b7a0325 2641 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2642 unsigned pte_size;
9b7a0325 2643 unsigned page_offset;
0e7bc4b9 2644 unsigned misaligned;
fce0657f 2645 unsigned quadrant;
9b7a0325 2646 int level;
86a5ba02 2647 int flooded = 0;
ac1b714e 2648 int npte;
489f1d65 2649 int r;
9b7a0325 2650
b8688d51 2651 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2652 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2653 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2654 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2655 kvm_mmu_free_some_pages(vcpu);
4cee5764 2656 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2657 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2658 if (guest_initiated) {
2659 if (gfn == vcpu->arch.last_pt_write_gfn
2660 && !last_updated_pte_accessed(vcpu)) {
2661 ++vcpu->arch.last_pt_write_count;
2662 if (vcpu->arch.last_pt_write_count >= 3)
2663 flooded = 1;
2664 } else {
2665 vcpu->arch.last_pt_write_gfn = gfn;
2666 vcpu->arch.last_pt_write_count = 1;
2667 vcpu->arch.last_pte_updated = NULL;
2668 }
86a5ba02 2669 }
1ae0a13d 2670 index = kvm_page_table_hashfn(gfn);
f05e70ac 2671 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2672 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2673 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2674 continue;
4db35314 2675 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2676 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2677 misaligned |= bytes < 4;
86a5ba02 2678 if (misaligned || flooded) {
0e7bc4b9
AK		 2679 /*
2680 * Misaligned accesses are too much trouble to fix
2681 * up; also, they usually indicate a page is not used
2682 * as a page table.
86a5ba02
AK		 2683 *
2684 * If we're seeing too many writes to a page,
2685 * it may no longer be a page table, or we may be
2686 * forking, in which case it is better to unmap the
2687 * page.
0e7bc4b9
AK		 2688 */
2689 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2690 gpa, bytes, sp->role.word);
07385413
MT		 2691 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2692 n = bucket->first;
4cee5764 2693 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2694 continue;
2695 }
9b7a0325 2696 page_offset = offset;
4db35314 2697 level = sp->role.level;
ac1b714e 2698 npte = 1;
4db35314 2699 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2700 page_offset <<= 1; /* 32->64 */
2701 /*
2702 * A 32-bit pde maps 4MB while the shadow pdes map
2703 * only 2MB. So we need to double the offset again
2704 * and zap two pdes instead of one.
2705 */
2706 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2707 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2708 page_offset <<= 1;
2709 npte = 2;
2710 }
fce0657f 2711 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2712 page_offset &= ~PAGE_MASK;
4db35314 2713 if (quadrant != sp->role.quadrant)
fce0657f 2714 continue;
9b7a0325 2715 }
4db35314 2716 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2717 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2718 gentry = 0;
2719 r = kvm_read_guest_atomic(vcpu->kvm,
2720 gpa & ~(u64)(pte_size - 1),
2721 &gentry, pte_size);
2722 new = (const void *)&gentry;
2723 if (r < 0)
2724 new = NULL;
2725 }
ac1b714e 2726 while (npte--) {
79539cec 2727 entry = *spte;
4db35314 2728 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2729 if (new)
2730 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2731 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2732 ++spte;
9b7a0325 2733 }
9b7a0325 2734 }
c7addb90 2735 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2736 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2737 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2738 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2739 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2740 }
da4a00f0
AK		 2741}
2742
a436036b
AK		 2743int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2744{
10589a46
MT		 2745 gpa_t gpa;
2746 int r;
a436036b 2747
60f24784
AK		 2748 if (tdp_enabled)
2749 return 0;
2750
10589a46 2751 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2752
aaee2c94 2753 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2754 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2755 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2756 return r;
a436036b 2757}
577bdc49 2758EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2759
22d95b12 2760void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2761{
3b80fffe
IE		 2762 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2763 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2764 struct kvm_mmu_page *sp;
ebeace86 2765
f05e70ac 2766 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2767 struct kvm_mmu_page, link);
2768 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2769 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2770 }
2771}
ebeace86 2772
3067714c
AK		 2773int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2774{
2775 int r;
2776 enum emulation_result er;
2777
ad312c7c 2778 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2779 if (r < 0)
2780 goto out;
2781
2782 if (!r) {
2783 r = 1;
2784 goto out;
2785 }
2786
b733bfb5
AK		 2787 r = mmu_topup_memory_caches(vcpu);
2788 if (r)
2789 goto out;
2790
851ba692 2791 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2792
2793 switch (er) {
2794 case EMULATE_DONE:
2795 return 1;
2796 case EMULATE_DO_MMIO:
2797 ++vcpu->stat.mmio_exits;
2798 return 0;
2799 case EMULATE_FAIL:
3f5d18a9
AK		 2800 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2801 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2802 vcpu->run->internal.ndata = 0;
3f5d18a9 2803 return 0;
3067714c
AK		 2804 default:
2805 BUG();
2806 }
2807out:
3067714c
AK		 2808 return r;
2809}
2810EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2811
a7052897
MT		 2812void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2813{
a7052897 2814 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2815 kvm_mmu_flush_tlb(vcpu);
2816 ++vcpu->stat.invlpg;
2817}
2818EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2819
18552672
JR		 2820void kvm_enable_tdp(void)
2821{
2822 tdp_enabled = true;
2823}
2824EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2825
5f4cb662
JR		 2826void kvm_disable_tdp(void)
2827{
2828 tdp_enabled = false;
2829}
2830EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2831
6aa8b732
AK		 2832static void free_mmu_pages(struct kvm_vcpu *vcpu)
2833{
ad312c7c 2834 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2835}
2836
2837static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2838{
17ac10ad 2839 struct page *page;
6aa8b732
AK		 2840 int i;
2841
2842 ASSERT(vcpu);
2843
17ac10ad
AK		 2844 /*
2845 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2846 * Therefore we need to allocate shadow page tables in the first
2847 * 4GB of memory, which happens to fit the DMA32 zone.
2848 */
2849 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2850 if (!page)
2851 goto error_1;
ad312c7c 2852 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2853 for (i = 0; i < 4; ++i)
ad312c7c 2854 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2855
6aa8b732
AK		 2856 return 0;
2857
2858error_1:
2859 free_mmu_pages(vcpu);
2860 return -ENOMEM;
2861}
2862
8018c27b 2863int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2864{
6aa8b732 2865 ASSERT(vcpu);
ad312c7c 2866 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2867
8018c27b
IM		 2868 return alloc_mmu_pages(vcpu);
2869}
6aa8b732 2870
8018c27b
IM		 2871int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2872{
2873 ASSERT(vcpu);
ad312c7c 2874 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2875
8018c27b 2876 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2877}
2878
2879void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2880{
2881 ASSERT(vcpu);
2882
2883 destroy_kvm_mmu(vcpu);
2884 free_mmu_pages(vcpu);
714b93da 2885 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2886}
2887
90cb0529 2888void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2889{
4db35314 2890 struct kvm_mmu_page *sp;
6aa8b732 2891
f05e70ac 2892 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2893 int i;
2894 u64 *pt;
2895
291f26bc 2896 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2897 continue;
2898
4db35314 2899 pt = sp->spt;
6aa8b732
AK		 2900 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2901 /* avoid RMW */
9647c14c 2902 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2903 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2904 }
171d595d 2905 kvm_flush_remote_tlbs(kvm);
6aa8b732 2906}
37a7d8b0 2907
90cb0529 2908void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2909{
4db35314 2910 struct kvm_mmu_page *sp, *node;
e0fa826f 2911
aaee2c94 2912 spin_lock(&kvm->mmu_lock);
f05e70ac 2913 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2914 if (kvm_mmu_zap_page(kvm, sp))
2915 node = container_of(kvm->arch.active_mmu_pages.next,
2916 struct kvm_mmu_page, link);
aaee2c94 2917 spin_unlock(&kvm->mmu_lock);
e0fa826f 2918
90cb0529 2919 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2920}
2921
8b2cf73c 2922static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2923{
2924 struct kvm_mmu_page *page;
2925
2926 page = container_of(kvm->arch.active_mmu_pages.prev,
2927 struct kvm_mmu_page, link);
2928 kvm_mmu_zap_page(kvm, page);
2929}
2930
2931static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2932{
2933 struct kvm *kvm;
2934 struct kvm *kvm_freed = NULL;
2935 int cache_count = 0;
2936
2937 spin_lock(&kvm_lock);
2938
2939 list_for_each_entry(kvm, &vm_list, vm_list) {
2940 int npages;
2941
5a4c9288
MT		 2942 if (!down_read_trylock(&kvm->slots_lock))
2943 continue;
3ee16c81
IE		 2944 spin_lock(&kvm->mmu_lock);
2945 npages = kvm->arch.n_alloc_mmu_pages -
2946 kvm->arch.n_free_mmu_pages;
2947 cache_count += npages;
2948 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2949 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2950 cache_count--;
2951 kvm_freed = kvm;
2952 }
2953 nr_to_scan--;
2954
2955 spin_unlock(&kvm->mmu_lock);
5a4c9288 2956 up_read(&kvm->slots_lock);
3ee16c81
IE		 2957 }
2958 if (kvm_freed)
2959 list_move_tail(&kvm_freed->vm_list, &vm_list);
2960
2961 spin_unlock(&kvm_lock);
2962
2963 return cache_count;
2964}
2965
2966static struct shrinker mmu_shrinker = {
2967 .shrink = mmu_shrink,
2968 .seeks = DEFAULT_SEEKS * 10,
2969};
2970
2ddfd20e 2971static void mmu_destroy_caches(void)
b5a33a75
AK		 2972{
2973 if (pte_chain_cache)
2974 kmem_cache_destroy(pte_chain_cache);
2975 if (rmap_desc_cache)
2976 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2977 if (mmu_page_header_cache)
2978 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2979}
2980
3ee16c81
IE		 2981void kvm_mmu_module_exit(void)
2982{
2983 mmu_destroy_caches();
2984 unregister_shrinker(&mmu_shrinker);
2985}
2986
b5a33a75
AK		 2987int kvm_mmu_module_init(void)
2988{
2989 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2990 sizeof(struct kvm_pte_chain),
20c2df83 2991 0, 0, NULL);
b5a33a75
AK		 2992 if (!pte_chain_cache)
2993 goto nomem;
2994 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2995 sizeof(struct kvm_rmap_desc),
20c2df83 2996 0, 0, NULL);
b5a33a75
AK		 2997 if (!rmap_desc_cache)
2998 goto nomem;
2999
d3d25b04
AK		 3000 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3001 sizeof(struct kvm_mmu_page),
20c2df83 3002 0, 0, NULL);
d3d25b04
AK		 3003 if (!mmu_page_header_cache)
3004 goto nomem;
3005
3ee16c81
IE		 3006 register_shrinker(&mmu_shrinker);
3007
b5a33a75
AK		 3008 return 0;
3009
3010nomem:
3ee16c81 3011 mmu_destroy_caches();
b5a33a75
AK		 3012 return -ENOMEM;
3013}
3014
3ad82a7e
ZX		 3015/*
3016 * Caculate mmu pages needed for kvm.
3017 */
3018unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3019{
3020 int i;
3021 unsigned int nr_mmu_pages;
3022 unsigned int nr_pages = 0;
3023
3024 for (i = 0; i < kvm->nmemslots; i++)
3025 nr_pages += kvm->memslots[i].npages;
3026
3027 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3028 nr_mmu_pages = max(nr_mmu_pages,
3029 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3030
3031 return nr_mmu_pages;
3032}
3033
2f333bcb
MT		 3034static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3035 unsigned len)
3036{
3037 if (len > buffer->len)
3038 return NULL;
3039 return buffer->ptr;
3040}
3041
3042static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3043 unsigned len)
3044{
3045 void *ret;
3046
3047 ret = pv_mmu_peek_buffer(buffer, len);
3048 if (!ret)
3049 return ret;
3050 buffer->ptr += len;
3051 buffer->len -= len;
3052 buffer->processed += len;
3053 return ret;
3054}
3055
3056static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3057 gpa_t addr, gpa_t value)
3058{
3059 int bytes = 8;
3060 int r;
3061
3062 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3063 bytes = 4;
3064
3065 r = mmu_topup_memory_caches(vcpu);
3066 if (r)
3067 return r;
3068
3200f405 3069 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3070 return -EFAULT;
3071
3072 return 1;
3073}
3074
3075static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3076{
a8cd0244 3077 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3078 return 1;
3079}
3080
3081static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3082{
3083 spin_lock(&vcpu->kvm->mmu_lock);
3084 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3085 spin_unlock(&vcpu->kvm->mmu_lock);
3086 return 1;
3087}
3088
3089static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3090 struct kvm_pv_mmu_op_buffer *buffer)
3091{
3092 struct kvm_mmu_op_header *header;
3093
3094 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3095 if (!header)
3096 return 0;
3097 switch (header->op) {
3098 case KVM_MMU_OP_WRITE_PTE: {
3099 struct kvm_mmu_op_write_pte *wpte;
3100
3101 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3102 if (!wpte)
3103 return 0;
3104 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3105 wpte->pte_val);
3106 }
3107 case KVM_MMU_OP_FLUSH_TLB: {
3108 struct kvm_mmu_op_flush_tlb *ftlb;
3109
3110 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3111 if (!ftlb)
3112 return 0;
3113 return kvm_pv_mmu_flush_tlb(vcpu);
3114 }
3115 case KVM_MMU_OP_RELEASE_PT: {
3116 struct kvm_mmu_op_release_pt *rpt;
3117
3118 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3119 if (!rpt)
3120 return 0;
3121 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3122 }
3123 default: return 0;
3124 }
3125}
3126
3127int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3128 gpa_t addr, unsigned long *ret)
3129{
3130 int r;
6ad18fba 3131 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3132
6ad18fba
DH		 3133 buffer->ptr = buffer->buf;
3134 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3135 buffer->processed = 0;
2f333bcb 3136
6ad18fba 3137 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3138 if (r)
3139 goto out;
3140
6ad18fba
DH		 3141 while (buffer->len) {
3142 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3143 if (r < 0)
3144 goto out;
3145 if (r == 0)
3146 break;
3147 }
3148
3149 r = 1;
3150out:
6ad18fba 3151 *ret = buffer->processed;
2f333bcb
MT		 3152 return r;
3153}
3154
94d8b056
MT		 3155int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3156{
3157 struct kvm_shadow_walk_iterator iterator;
3158 int nr_sptes = 0;
3159
3160 spin_lock(&vcpu->kvm->mmu_lock);
3161 for_each_shadow_entry(vcpu, addr, iterator) {
3162 sptes[iterator.level-1] = *iterator.sptep;
3163 nr_sptes++;
3164 if (!is_shadow_present_pte(*iterator.sptep))
3165 break;
3166 }
3167 spin_unlock(&vcpu->kvm->mmu_lock);
3168
3169 return nr_sptes;
3170}
3171EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3172
37a7d8b0
AK		 3173#ifdef AUDIT
3174
3175static const char *audit_msg;
3176
3177static gva_t canonicalize(gva_t gva)
3178{
3179#ifdef CONFIG_X86_64
3180 gva = (long long)(gva << 16) >> 16;
3181#endif
3182 return gva;
3183}
3184
08a3732b
MT		 3185
3186typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3187 u64 *sptep);
3188
3189static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3190 inspect_spte_fn fn)
3191{
3192 int i;
3193
3194 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3195 u64 ent = sp->spt[i];
3196
3197 if (is_shadow_present_pte(ent)) {
2920d728 3198 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3199 struct kvm_mmu_page *child;
3200 child = page_header(ent & PT64_BASE_ADDR_MASK);
3201 __mmu_spte_walk(kvm, child, fn);
2920d728 3202 } else
08a3732b
MT		 3203 fn(kvm, sp, &sp->spt[i]);
3204 }
3205 }
3206}
3207
3208static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3209{
3210 int i;
3211 struct kvm_mmu_page *sp;
3212
3213 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3214 return;
3215 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3216 hpa_t root = vcpu->arch.mmu.root_hpa;
3217 sp = page_header(root);
3218 __mmu_spte_walk(vcpu->kvm, sp, fn);
3219 return;
3220 }
3221 for (i = 0; i < 4; ++i) {
3222 hpa_t root = vcpu->arch.mmu.pae_root[i];
3223
3224 if (root && VALID_PAGE(root)) {
3225 root &= PT64_BASE_ADDR_MASK;
3226 sp = page_header(root);
3227 __mmu_spte_walk(vcpu->kvm, sp, fn);
3228 }
3229 }
3230 return;
3231}
3232
37a7d8b0
AK		 3233static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3234 gva_t va, int level)
3235{
3236 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3237 int i;
3238 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3239
3240 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3241 u64 ent = pt[i];
3242
c7addb90 3243 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3244 continue;
3245
3246 va = canonicalize(va);
2920d728
MT		 3247 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3248 audit_mappings_page(vcpu, ent, va, level - 1);
3249 else {
ad312c7c 3250 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3251 gfn_t gfn = gpa >> PAGE_SHIFT;
3252 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3253 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3254
2aaf65e8
MT		 3255 if (is_error_pfn(pfn)) {
3256 kvm_release_pfn_clean(pfn);
3257 continue;
3258 }
3259
c7addb90 3260 if (is_shadow_present_pte(ent)
37a7d8b0 3261 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3262 printk(KERN_ERR "xx audit error: (%s) levels %d"
3263 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3264 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3265 va, gpa, hpa, ent,
3266 is_shadow_present_pte(ent));
c7addb90
AK		 3267 else if (ent == shadow_notrap_nonpresent_pte
3268 && !is_error_hpa(hpa))
3269 printk(KERN_ERR "audit: (%s) notrap shadow,"
3270 " valid guest gva %lx\n", audit_msg, va);
35149e21 3271 kvm_release_pfn_clean(pfn);
c7addb90 3272
37a7d8b0
AK		 3273 }
3274 }
3275}
3276
3277static void audit_mappings(struct kvm_vcpu *vcpu)
3278{
1ea252af 3279 unsigned i;
37a7d8b0 3280
ad312c7c
ZX		 3281 if (vcpu->arch.mmu.root_level == 4)
3282 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3283 else
3284 for (i = 0; i < 4; ++i)
ad312c7c 3285 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3286 audit_mappings_page(vcpu,
ad312c7c 3287 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3288 i << 30,
3289 2);
3290}
3291
3292static int count_rmaps(struct kvm_vcpu *vcpu)
3293{
3294 int nmaps = 0;
3295 int i, j, k;
3296
3297 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3298 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3299 struct kvm_rmap_desc *d;
3300
3301 for (j = 0; j < m->npages; ++j) {
290fc38d 3302 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3303
290fc38d 3304 if (!*rmapp)
37a7d8b0 3305 continue;
290fc38d 3306 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3307 ++nmaps;
3308 continue;
3309 }
290fc38d 3310 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3311 while (d) {
3312 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3313 if (d->sptes[k])
37a7d8b0
AK		 3314 ++nmaps;
3315 else
3316 break;
3317 d = d->more;
3318 }
3319 }
3320 }
3321 return nmaps;
3322}
3323
08a3732b
MT		 3324void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3325{
3326 unsigned long *rmapp;
3327 struct kvm_mmu_page *rev_sp;
3328 gfn_t gfn;
3329
3330 if (*sptep & PT_WRITABLE_MASK) {
3331 rev_sp = page_header(__pa(sptep));
3332 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3333
3334 if (!gfn_to_memslot(kvm, gfn)) {
3335 if (!printk_ratelimit())
3336 return;
3337 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3338 audit_msg, gfn);
3339 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3340 audit_msg, sptep - rev_sp->spt,
3341 rev_sp->gfn);
3342 dump_stack();
3343 return;
3344 }
3345
2920d728
MT		 3346 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3347 is_large_pte(*sptep));
08a3732b
MT		 3348 if (!*rmapp) {
3349 if (!printk_ratelimit())
3350 return;
3351 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3352 audit_msg, *sptep);
3353 dump_stack();
3354 }
3355 }
3356
3357}
3358
3359void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3360{
3361 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3362}
3363
3364static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3365{
4db35314 3366 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3367 int i;
3368
f05e70ac 3369 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3370 u64 *pt = sp->spt;
37a7d8b0 3371
4db35314 3372 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3373 continue;
3374
3375 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3376 u64 ent = pt[i];
3377
3378 if (!(ent & PT_PRESENT_MASK))
3379 continue;
3380 if (!(ent & PT_WRITABLE_MASK))
3381 continue;
08a3732b 3382 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3383 }
3384 }
08a3732b 3385 return;
37a7d8b0
AK		 3386}
3387
3388static void audit_rmap(struct kvm_vcpu *vcpu)
3389{
08a3732b
MT		 3390 check_writable_mappings_rmap(vcpu);
3391 count_rmaps(vcpu);
37a7d8b0
AK		 3392}
3393
3394static void audit_write_protection(struct kvm_vcpu *vcpu)
3395{
4db35314 3396 struct kvm_mmu_page *sp;
290fc38d
IE		 3397 struct kvm_memory_slot *slot;
3398 unsigned long *rmapp;
e58b0f9e 3399 u64 *spte;
290fc38d 3400 gfn_t gfn;
37a7d8b0 3401
f05e70ac 3402 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3403 if (sp->role.direct)
37a7d8b0 3404 continue;
e58b0f9e
MT		 3405 if (sp->unsync)
3406 continue;
37a7d8b0 3407
4db35314 3408 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3409 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3410 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3411
3412 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3413 while (spte) {
3414 if (*spte & PT_WRITABLE_MASK)
3415 printk(KERN_ERR "%s: (%s) shadow page has "
3416 "writable mappings: gfn %lx role %x\n",
b8688d51 3417 __func__, audit_msg, sp->gfn,
4db35314 3418 sp->role.word);
e58b0f9e
MT		 3419 spte = rmap_next(vcpu->kvm, rmapp, spte);
3420 }
37a7d8b0
AK		 3421 }
3422}
3423
3424static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3425{
3426 int olddbg = dbg;
3427
3428 dbg = 0;
3429 audit_msg = msg;
3430 audit_rmap(vcpu);
3431 audit_write_protection(vcpu);
2aaf65e8
MT		 3432 if (strcmp("pre pte write", audit_msg) != 0)
3433 audit_mappings(vcpu);
08a3732b 3434 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3435 dbg = olddbg;
3436}
3437
3438#endif
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