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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
221d059d 10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
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11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
e495606d 20
1d737c8a 21#include "mmu.h"
836a1b3c 22#include "x86.h"
6de4f3ad 23#include "kvm_cache_regs.h"
e495606d 24
edf88417 25#include <linux/kvm_host.h>
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26#include <linux/types.h>
27#include <linux/string.h>
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28#include <linux/mm.h>
29#include <linux/highmem.h>
30#include <linux/module.h>
448353ca 31#include <linux/swap.h>
05da4558 32#include <linux/hugetlb.h>
2f333bcb 33#include <linux/compiler.h>
bc6678a3 34#include <linux/srcu.h>
5a0e3ad6 35#include <linux/slab.h>
bf998156 36#include <linux/uaccess.h>
6aa8b732 37
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38#include <asm/page.h>
39#include <asm/cmpxchg.h>
4e542370 40#include <asm/io.h>
13673a90 41#include <asm/vmx.h>
6aa8b732 42
18552672
JR
43/*
44 * When setting this variable to true it enables Two-Dimensional-Paging
45 * where the hardware walks 2 page tables:
46 * 1. the guest-virtual to guest-physical
47 * 2. while doing 1. it walks guest-physical to host-physical
48 * If the hardware supports that we don't need to do shadow paging.
49 */
2f333bcb 50bool tdp_enabled = false;
18552672 51
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52#undef MMU_DEBUG
53
54#undef AUDIT
55
56#ifdef AUDIT
57static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
58#else
59static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
60#endif
61
62#ifdef MMU_DEBUG
63
64#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
65#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
66
67#else
68
69#define pgprintk(x...) do { } while (0)
70#define rmap_printk(x...) do { } while (0)
71
72#endif
73
74#if defined(MMU_DEBUG) || defined(AUDIT)
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75static int dbg = 0;
76module_param(dbg, bool, 0644);
37a7d8b0 77#endif
6aa8b732 78
582801a9
MT
79static int oos_shadow = 1;
80module_param(oos_shadow, bool, 0644);
81
d6c69ee9
YD
82#ifndef MMU_DEBUG
83#define ASSERT(x) do { } while (0)
84#else
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85#define ASSERT(x) \
86 if (!(x)) { \
87 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
88 __FILE__, __LINE__, #x); \
89 }
d6c69ee9 90#endif
6aa8b732 91
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92#define PT_FIRST_AVAIL_BITS_SHIFT 9
93#define PT64_SECOND_AVAIL_BITS_SHIFT 52
94
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95#define VALID_PAGE(x) ((x) != INVALID_PAGE)
96
97#define PT64_LEVEL_BITS 9
98
99#define PT64_LEVEL_SHIFT(level) \
d77c26fc 100 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
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101
102#define PT64_LEVEL_MASK(level) \
103 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
104
105#define PT64_INDEX(address, level)\
106 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
107
108
109#define PT32_LEVEL_BITS 10
110
111#define PT32_LEVEL_SHIFT(level) \
d77c26fc 112 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
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113
114#define PT32_LEVEL_MASK(level) \
115 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR
116#define PT32_LVL_OFFSET_MASK(level) \
117 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
118 * PT32_LEVEL_BITS))) - 1))
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119
120#define PT32_INDEX(address, level)\
121 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
122
123
27aba766 124#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
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125#define PT64_DIR_BASE_ADDR_MASK \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
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JR
127#define PT64_LVL_ADDR_MASK(level) \
128 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
129 * PT64_LEVEL_BITS))) - 1))
130#define PT64_LVL_OFFSET_MASK(level) \
131 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
132 * PT64_LEVEL_BITS))) - 1))
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133
134#define PT32_BASE_ADDR_MASK PAGE_MASK
135#define PT32_DIR_BASE_ADDR_MASK \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
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JR
137#define PT32_LVL_ADDR_MASK(level) \
138 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT32_LEVEL_BITS))) - 1))
6aa8b732 140
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141#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
142 | PT64_NX_MASK)
6aa8b732 143
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144#define RMAP_EXT 4
145
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146#define ACC_EXEC_MASK 1
147#define ACC_WRITE_MASK PT_WRITABLE_MASK
148#define ACC_USER_MASK PT_USER_MASK
149#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
150
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151#include <trace/events/kvm.h>
152
07420171
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153#define CREATE_TRACE_POINTS
154#include "mmutrace.h"
155
1403283a
IE
156#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
157
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158#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
159
cd4a4e53 160struct kvm_rmap_desc {
d555c333 161 u64 *sptes[RMAP_EXT];
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162 struct kvm_rmap_desc *more;
163};
164
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165struct kvm_shadow_walk_iterator {
166 u64 addr;
167 hpa_t shadow_addr;
168 int level;
169 u64 *sptep;
170 unsigned index;
171};
172
173#define for_each_shadow_entry(_vcpu, _addr, _walker) \
174 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
175 shadow_walk_okay(&(_walker)); \
176 shadow_walk_next(&(_walker)))
177
6b18493d 178typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
ad8cfbe3 179
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180static struct kmem_cache *pte_chain_cache;
181static struct kmem_cache *rmap_desc_cache;
d3d25b04 182static struct kmem_cache *mmu_page_header_cache;
b5a33a75 183
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184static u64 __read_mostly shadow_trap_nonpresent_pte;
185static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY
186static u64 __read_mostly shadow_base_present_pte;
187static u64 __read_mostly shadow_nx_mask;
188static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
189static u64 __read_mostly shadow_user_mask;
190static u64 __read_mostly shadow_accessed_mask;
191static u64 __read_mostly shadow_dirty_mask;
c7addb90 192
82725b20
DE
193static inline u64 rsvd_bits(int s, int e)
194{
195 return ((1ULL << (e - s + 1)) - 1) << s;
196}
197
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198void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
199{
200 shadow_trap_nonpresent_pte = trap_pte;
201 shadow_notrap_nonpresent_pte = notrap_pte;
202}
203EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
204
7b52345e
SY
205void kvm_mmu_set_base_ptes(u64 base_pte)
206{
207 shadow_base_present_pte = base_pte;
208}
209EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
210
211void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 212 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY
213{
214 shadow_user_mask = user_mask;
215 shadow_accessed_mask = accessed_mask;
216 shadow_dirty_mask = dirty_mask;
217 shadow_nx_mask = nx_mask;
218 shadow_x_mask = x_mask;
219}
220EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
221
3dbe1415 222static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 223{
4d4ec087 224 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
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225}
226
227static int is_cpuid_PSE36(void)
228{
229 return 1;
230}
231
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232static int is_nx(struct kvm_vcpu *vcpu)
233{
f6801dff 234 return vcpu->arch.efer & EFER_NX;
73b1087e
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235}
236
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237static int is_shadow_present_pte(u64 pte)
238{
c7addb90
AK
239 return pte != shadow_trap_nonpresent_pte
240 && pte != shadow_notrap_nonpresent_pte;
241}
242
05da4558
MT
243static int is_large_pte(u64 pte)
244{
245 return pte & PT_PAGE_SIZE_MASK;
246}
247
8dae4445 248static int is_writable_pte(unsigned long pte)
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249{
250 return pte & PT_WRITABLE_MASK;
251}
252
43a3795a 253static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 254{
439e218a 255 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK
256}
257
43a3795a 258static int is_rmap_spte(u64 pte)
cd4a4e53 259{
4b1a80fa 260 return is_shadow_present_pte(pte);
cd4a4e53
AK
261}
262
776e6633
MT
263static int is_last_spte(u64 pte, int level)
264{
265 if (level == PT_PAGE_TABLE_LEVEL)
266 return 1;
852e3c19 267 if (is_large_pte(pte))
776e6633
MT
268 return 1;
269 return 0;
270}
271
35149e21 272static pfn_t spte_to_pfn(u64 pte)
0b49ea86 273{
35149e21 274 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK
275}
276
da928521
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277static gfn_t pse36_gfn_delta(u32 gpte)
278{
279 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
280
281 return (gpte & PT32_DIR_PSE36_MASK) << shift;
282}
283
d555c333 284static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK
285{
286#ifdef CONFIG_X86_64
287 set_64bit((unsigned long *)sptep, spte);
288#else
289 set_64bit((unsigned long long *)sptep, spte);
290#endif
291}
292
e2dec939 293static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 294 struct kmem_cache *base_cache, int min)
714b93da
AK
295{
296 void *obj;
297
298 if (cache->nobjs >= min)
e2dec939 299 return 0;
714b93da 300 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 301 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 302 if (!obj)
e2dec939 303 return -ENOMEM;
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AK
304 cache->objects[cache->nobjs++] = obj;
305 }
e2dec939 306 return 0;
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307}
308
e8ad9a70
XG
309static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
310 struct kmem_cache *cache)
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AK
311{
312 while (mc->nobjs)
e8ad9a70 313 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
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314}
315
c1158e63 316static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 317 int min)
c1158e63
AK
318{
319 struct page *page;
320
321 if (cache->nobjs >= min)
322 return 0;
323 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 324 page = alloc_page(GFP_KERNEL);
c1158e63
AK
325 if (!page)
326 return -ENOMEM;
c1158e63
AK
327 cache->objects[cache->nobjs++] = page_address(page);
328 }
329 return 0;
330}
331
332static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
333{
334 while (mc->nobjs)
c4d198d5 335 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK
336}
337
2e3e5882 338static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 339{
e2dec939
AK
340 int r;
341
ad312c7c 342 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 343 pte_chain_cache, 4);
e2dec939
AK
344 if (r)
345 goto out;
ad312c7c 346 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 347 rmap_desc_cache, 4);
d3d25b04
AK
348 if (r)
349 goto out;
ad312c7c 350 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK
351 if (r)
352 goto out;
ad312c7c 353 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 354 mmu_page_header_cache, 4);
e2dec939
AK
355out:
356 return r;
714b93da
AK
357}
358
359static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
360{
e8ad9a70
XG
361 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
362 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
ad312c7c 363 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG
364 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
365 mmu_page_header_cache);
714b93da
AK
366}
367
368static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
369 size_t size)
370{
371 void *p;
372
373 BUG_ON(!mc->nobjs);
374 p = mc->objects[--mc->nobjs];
714b93da
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375 return p;
376}
377
714b93da
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378static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
379{
ad312c7c 380 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK
381 sizeof(struct kvm_pte_chain));
382}
383
90cb0529 384static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 385{
e8ad9a70 386 kmem_cache_free(pte_chain_cache, pc);
714b93da
AK
387}
388
389static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
390{
ad312c7c 391 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK
392 sizeof(struct kvm_rmap_desc));
393}
394
90cb0529 395static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 396{
e8ad9a70 397 kmem_cache_free(rmap_desc_cache, rd);
714b93da
AK
398}
399
05da4558
MT
400/*
401 * Return the pointer to the largepage write count for a given
402 * gfn, handling slots that are not large page aligned.
403 */
d25797b2
JR
404static int *slot_largepage_idx(gfn_t gfn,
405 struct kvm_memory_slot *slot,
406 int level)
05da4558
MT
407{
408 unsigned long idx;
409
d25797b2
JR
410 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
411 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
412 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT
413}
414
415static void account_shadowed(struct kvm *kvm, gfn_t gfn)
416{
d25797b2 417 struct kvm_memory_slot *slot;
05da4558 418 int *write_count;
d25797b2 419 int i;
05da4558 420
2843099f 421 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR
422
423 slot = gfn_to_memslot_unaliased(kvm, gfn);
424 for (i = PT_DIRECTORY_LEVEL;
425 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
426 write_count = slot_largepage_idx(gfn, slot, i);
427 *write_count += 1;
428 }
05da4558
MT
429}
430
431static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
432{
d25797b2 433 struct kvm_memory_slot *slot;
05da4558 434 int *write_count;
d25797b2 435 int i;
05da4558 436
2843099f 437 gfn = unalias_gfn(kvm, gfn);
77a1a715 438 slot = gfn_to_memslot_unaliased(kvm, gfn);
d25797b2
JR
439 for (i = PT_DIRECTORY_LEVEL;
440 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR
441 write_count = slot_largepage_idx(gfn, slot, i);
442 *write_count -= 1;
443 WARN_ON(*write_count < 0);
444 }
05da4558
MT
445}
446
d25797b2
JR
447static int has_wrprotected_page(struct kvm *kvm,
448 gfn_t gfn,
449 int level)
05da4558 450{
2843099f 451 struct kvm_memory_slot *slot;
05da4558
MT
452 int *largepage_idx;
453
2843099f
IE
454 gfn = unalias_gfn(kvm, gfn);
455 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 456 if (slot) {
d25797b2 457 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT
458 return *largepage_idx;
459 }
460
461 return 1;
462}
463
d25797b2 464static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 465{
8f0b1ab6 466 unsigned long page_size;
d25797b2 467 int i, ret = 0;
05da4558 468
8f0b1ab6 469 page_size = kvm_host_page_size(kvm, gfn);
05da4558 470
d25797b2
JR
471 for (i = PT_PAGE_TABLE_LEVEL;
472 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
473 if (page_size >= KVM_HPAGE_SIZE(i))
474 ret = i;
475 else
476 break;
477 }
478
4c2155ce 479 return ret;
05da4558
MT
480}
481
d25797b2 482static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT
483{
484 struct kvm_memory_slot *slot;
878403b7 485 int host_level, level, max_level;
05da4558
MT
486
487 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
488 if (slot && slot->dirty_bitmap)
d25797b2 489 return PT_PAGE_TABLE_LEVEL;
05da4558 490
d25797b2
JR
491 host_level = host_mapping_level(vcpu->kvm, large_gfn);
492
493 if (host_level == PT_PAGE_TABLE_LEVEL)
494 return host_level;
495
878403b7
SY
496 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
497 kvm_x86_ops->get_lpage_level() : host_level;
498
499 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR
500 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
501 break;
d25797b2
JR
502
503 return level - 1;
05da4558
MT
504}
505
290fc38d
IE
506/*
507 * Take gfn and return the reverse mapping to it.
508 * Note: gfn must be unaliased before this function get called
509 */
510
44ad9944 511static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE
512{
513 struct kvm_memory_slot *slot;
05da4558 514 unsigned long idx;
290fc38d
IE
515
516 slot = gfn_to_memslot(kvm, gfn);
44ad9944 517 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT
518 return &slot->rmap[gfn - slot->base_gfn];
519
44ad9944
JR
520 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
521 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 522
44ad9944 523 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE
524}
525
cd4a4e53
AK
526/*
527 * Reverse mapping data structures:
528 *
290fc38d
IE
529 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
530 * that points to page_address(page).
cd4a4e53 531 *
290fc38d
IE
532 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
533 * containing more mappings.
53a27b39
MT
534 *
535 * Returns the number of rmap entries before the spte was added or zero if
536 * the spte was not added.
537 *
cd4a4e53 538 */
44ad9944 539static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 540{
4db35314 541 struct kvm_mmu_page *sp;
cd4a4e53 542 struct kvm_rmap_desc *desc;
290fc38d 543 unsigned long *rmapp;
53a27b39 544 int i, count = 0;
cd4a4e53 545
43a3795a 546 if (!is_rmap_spte(*spte))
53a27b39 547 return count;
290fc38d 548 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK
549 sp = page_header(__pa(spte));
550 sp->gfns[spte - sp->spt] = gfn;
44ad9944 551 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 552 if (!*rmapp) {
cd4a4e53 553 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE
554 *rmapp = (unsigned long)spte;
555 } else if (!(*rmapp & 1)) {
cd4a4e53 556 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 557 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK
558 desc->sptes[0] = (u64 *)*rmapp;
559 desc->sptes[1] = spte;
290fc38d 560 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK
561 } else {
562 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 563 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 564 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 565 desc = desc->more;
53a27b39
MT
566 count += RMAP_EXT;
567 }
d555c333 568 if (desc->sptes[RMAP_EXT-1]) {
714b93da 569 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK
570 desc = desc->more;
571 }
d555c333 572 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 573 ;
d555c333 574 desc->sptes[i] = spte;
cd4a4e53 575 }
53a27b39 576 return count;
cd4a4e53
AK
577}
578
290fc38d 579static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK
580 struct kvm_rmap_desc *desc,
581 int i,
582 struct kvm_rmap_desc *prev_desc)
583{
584 int j;
585
d555c333 586 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 587 ;
d555c333
AK
588 desc->sptes[i] = desc->sptes[j];
589 desc->sptes[j] = NULL;
cd4a4e53
AK
590 if (j != 0)
591 return;
592 if (!prev_desc && !desc->more)
d555c333 593 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK
594 else
595 if (prev_desc)
596 prev_desc->more = desc->more;
597 else
290fc38d 598 *rmapp = (unsigned long)desc->more | 1;
90cb0529 599 mmu_free_rmap_desc(desc);
cd4a4e53
AK
600}
601
290fc38d 602static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 603{
cd4a4e53
AK
604 struct kvm_rmap_desc *desc;
605 struct kvm_rmap_desc *prev_desc;
4db35314 606 struct kvm_mmu_page *sp;
35149e21 607 pfn_t pfn;
290fc38d 608 unsigned long *rmapp;
cd4a4e53
AK
609 int i;
610
43a3795a 611 if (!is_rmap_spte(*spte))
cd4a4e53 612 return;
4db35314 613 sp = page_header(__pa(spte));
35149e21 614 pfn = spte_to_pfn(*spte);
7b52345e 615 if (*spte & shadow_accessed_mask)
35149e21 616 kvm_set_pfn_accessed(pfn);
8dae4445 617 if (is_writable_pte(*spte))
acb66dd0 618 kvm_set_pfn_dirty(pfn);
44ad9944 619 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 620 if (!*rmapp) {
cd4a4e53
AK
621 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
622 BUG();
290fc38d 623 } else if (!(*rmapp & 1)) {
cd4a4e53 624 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 625 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK
626 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
627 spte, *spte);
628 BUG();
629 }
290fc38d 630 *rmapp = 0;
cd4a4e53
AK
631 } else {
632 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 633 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK
634 prev_desc = NULL;
635 while (desc) {
d555c333
AK
636 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
637 if (desc->sptes[i] == spte) {
290fc38d 638 rmap_desc_remove_entry(rmapp,
714b93da 639 desc, i,
cd4a4e53
AK
640 prev_desc);
641 return;
642 }
643 prev_desc = desc;
644 desc = desc->more;
645 }
186a3e52 646 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK
647 BUG();
648 }
649}
650
98348e95 651static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 652{
374cbac0 653 struct kvm_rmap_desc *desc;
98348e95
IE
654 u64 *prev_spte;
655 int i;
656
657 if (!*rmapp)
658 return NULL;
659 else if (!(*rmapp & 1)) {
660 if (!spte)
661 return (u64 *)*rmapp;
662 return NULL;
663 }
664 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE
665 prev_spte = NULL;
666 while (desc) {
d555c333 667 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 668 if (prev_spte == spte)
d555c333
AK
669 return desc->sptes[i];
670 prev_spte = desc->sptes[i];
98348e95
IE
671 }
672 desc = desc->more;
673 }
674 return NULL;
675}
676
b1a36821 677static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 678{
290fc38d 679 unsigned long *rmapp;
374cbac0 680 u64 *spte;
44ad9944 681 int i, write_protected = 0;
374cbac0 682
4a4c9924 683 gfn = unalias_gfn(kvm, gfn);
44ad9944 684 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 685
98348e95
IE
686 spte = rmap_next(kvm, rmapp, NULL);
687 while (spte) {
374cbac0 688 BUG_ON(!spte);
374cbac0 689 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 690 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 691 if (is_writable_pte(*spte)) {
d555c333 692 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED
693 write_protected = 1;
694 }
9647c14c 695 spte = rmap_next(kvm, rmapp, spte);
374cbac0 696 }
855149aa 697 if (write_protected) {
35149e21 698 pfn_t pfn;
855149aa
IE
699
700 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL
701 pfn = spte_to_pfn(*spte);
702 kvm_set_pfn_dirty(pfn);
855149aa
IE
703 }
704
05da4558 705 /* check for huge page mappings */
44ad9944
JR
706 for (i = PT_DIRECTORY_LEVEL;
707 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
708 rmapp = gfn_to_rmap(kvm, gfn, i);
709 spte = rmap_next(kvm, rmapp, NULL);
710 while (spte) {
711 BUG_ON(!spte);
712 BUG_ON(!(*spte & PT_PRESENT_MASK));
713 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
714 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 715 if (is_writable_pte(*spte)) {
44ad9944
JR
716 rmap_remove(kvm, spte);
717 --kvm->stat.lpages;
718 __set_spte(spte, shadow_trap_nonpresent_pte);
719 spte = NULL;
720 write_protected = 1;
721 }
722 spte = rmap_next(kvm, rmapp, spte);
05da4558 723 }
05da4558
MT
724 }
725
b1a36821 726 return write_protected;
374cbac0
AK
727}
728
8a8365c5
FD
729static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
730 unsigned long data)
e930bffe
AA
731{
732 u64 *spte;
733 int need_tlb_flush = 0;
734
735 while ((spte = rmap_next(kvm, rmapp, NULL))) {
736 BUG_ON(!(*spte & PT_PRESENT_MASK));
737 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
738 rmap_remove(kvm, spte);
d555c333 739 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA
740 need_tlb_flush = 1;
741 }
742 return need_tlb_flush;
743}
744
8a8365c5
FD
745static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
746 unsigned long data)
3da0dd43
IE
747{
748 int need_flush = 0;
749 u64 *spte, new_spte;
750 pte_t *ptep = (pte_t *)data;
751 pfn_t new_pfn;
752
753 WARN_ON(pte_huge(*ptep));
754 new_pfn = pte_pfn(*ptep);
755 spte = rmap_next(kvm, rmapp, NULL);
756 while (spte) {
757 BUG_ON(!is_shadow_present_pte(*spte));
758 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
759 need_flush = 1;
760 if (pte_write(*ptep)) {
761 rmap_remove(kvm, spte);
762 __set_spte(spte, shadow_trap_nonpresent_pte);
763 spte = rmap_next(kvm, rmapp, NULL);
764 } else {
765 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
766 new_spte |= (u64)new_pfn << PAGE_SHIFT;
767
768 new_spte &= ~PT_WRITABLE_MASK;
769 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 770 if (is_writable_pte(*spte))
3da0dd43
IE
771 kvm_set_pfn_dirty(spte_to_pfn(*spte));
772 __set_spte(spte, new_spte);
773 spte = rmap_next(kvm, rmapp, spte);
774 }
775 }
776 if (need_flush)
777 kvm_flush_remote_tlbs(kvm);
778
779 return 0;
780}
781
8a8365c5
FD
782static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
783 unsigned long data,
3da0dd43 784 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 785 unsigned long data))
e930bffe 786{
852e3c19 787 int i, j;
90bb6fc5 788 int ret;
e930bffe 789 int retval = 0;
bc6678a3
MT
790 struct kvm_memslots *slots;
791
90d83dc3 792 slots = kvm_memslots(kvm);
e930bffe 793
46a26bf5
MT
794 for (i = 0; i < slots->nmemslots; i++) {
795 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA
796 unsigned long start = memslot->userspace_addr;
797 unsigned long end;
798
e930bffe
AA
799 end = start + (memslot->npages << PAGE_SHIFT);
800 if (hva >= start && hva < end) {
801 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 802
90bb6fc5 803 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR
804
805 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
806 int idx = gfn_offset;
807 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 808 ret |= handler(kvm,
3da0dd43
IE
809 &memslot->lpage_info[j][idx].rmap_pde,
810 data);
852e3c19 811 }
90bb6fc5
AK
812 trace_kvm_age_page(hva, memslot, ret);
813 retval |= ret;
e930bffe
AA
814 }
815 }
816
817 return retval;
818}
819
820int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
821{
3da0dd43
IE
822 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
823}
824
825void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
826{
8a8365c5 827 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA
828}
829
8a8365c5
FD
830static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
831 unsigned long data)
e930bffe
AA
832{
833 u64 *spte;
834 int young = 0;
835
6316e1c8
RR
836 /*
837 * Emulate the accessed bit for EPT, by checking if this page has
838 * an EPT mapping, and clearing it if it does. On the next access,
839 * a new EPT mapping will be established.
840 * This has some overhead, but not as much as the cost of swapping
841 * out actively used pages or breaking up actively used hugepages.
842 */
534e38b4 843 if (!shadow_accessed_mask)
6316e1c8 844 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 845
e930bffe
AA
846 spte = rmap_next(kvm, rmapp, NULL);
847 while (spte) {
848 int _young;
849 u64 _spte = *spte;
850 BUG_ON(!(_spte & PT_PRESENT_MASK));
851 _young = _spte & PT_ACCESSED_MASK;
852 if (_young) {
853 young = 1;
854 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
855 }
856 spte = rmap_next(kvm, rmapp, spte);
857 }
858 return young;
859}
860
53a27b39
MT
861#define RMAP_RECYCLE_THRESHOLD 1000
862
852e3c19 863static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT
864{
865 unsigned long *rmapp;
852e3c19
JR
866 struct kvm_mmu_page *sp;
867
868 sp = page_header(__pa(spte));
53a27b39
MT
869
870 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 871 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 872
3da0dd43 873 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT
874 kvm_flush_remote_tlbs(vcpu->kvm);
875}
876
e930bffe
AA
877int kvm_age_hva(struct kvm *kvm, unsigned long hva)
878{
3da0dd43 879 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA
880}
881
d6c69ee9 882#ifdef MMU_DEBUG
47ad8e68 883static int is_empty_shadow_page(u64 *spt)
6aa8b732 884{
139bdb2d
AK
885 u64 *pos;
886 u64 *end;
887
47ad8e68 888 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 889 if (is_shadow_present_pte(*pos)) {
b8688d51 890 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 891 pos, *pos);
6aa8b732 892 return 0;
139bdb2d 893 }
6aa8b732
AK
894 return 1;
895}
d6c69ee9 896#endif
6aa8b732 897
4db35314 898static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 899{
4db35314
AK
900 ASSERT(is_empty_shadow_page(sp->spt));
901 list_del(&sp->link);
902 __free_page(virt_to_page(sp->spt));
903 __free_page(virt_to_page(sp->gfns));
e8ad9a70 904 kmem_cache_free(mmu_page_header_cache, sp);
f05e70ac 905 ++kvm->arch.n_free_mmu_pages;
260746c0
AK
906}
907
cea0f0e7
AK
908static unsigned kvm_page_table_hashfn(gfn_t gfn)
909{
1ae0a13d 910 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK
911}
912
25c0de2c
AK
913static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
914 u64 *parent_pte)
6aa8b732 915{
4db35314 916 struct kvm_mmu_page *sp;
6aa8b732 917
ad312c7c
ZX
918 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
919 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
920 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 921 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 922 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 923 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK
924 sp->multimapped = 0;
925 sp->parent_pte = parent_pte;
f05e70ac 926 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 927 return sp;
6aa8b732
AK
928}
929
714b93da 930static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 931 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK
932{
933 struct kvm_pte_chain *pte_chain;
934 struct hlist_node *node;
935 int i;
936
937 if (!parent_pte)
938 return;
4db35314
AK
939 if (!sp->multimapped) {
940 u64 *old = sp->parent_pte;
cea0f0e7
AK
941
942 if (!old) {
4db35314 943 sp->parent_pte = parent_pte;
cea0f0e7
AK
944 return;
945 }
4db35314 946 sp->multimapped = 1;
714b93da 947 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK
948 INIT_HLIST_HEAD(&sp->parent_ptes);
949 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK
950 pte_chain->parent_ptes[0] = old;
951 }
4db35314 952 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK
953 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
954 continue;
955 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
956 if (!pte_chain->parent_ptes[i]) {
957 pte_chain->parent_ptes[i] = parent_pte;
958 return;
959 }
960 }
714b93da 961 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 962 BUG_ON(!pte_chain);
4db35314 963 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK
964 pte_chain->parent_ptes[0] = parent_pte;
965}
966
4db35314 967static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK
968 u64 *parent_pte)
969{
970 struct kvm_pte_chain *pte_chain;
971 struct hlist_node *node;
972 int i;
973
4db35314
AK
974 if (!sp->multimapped) {
975 BUG_ON(sp->parent_pte != parent_pte);
976 sp->parent_pte = NULL;
cea0f0e7
AK
977 return;
978 }
4db35314 979 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK
980 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
981 if (!pte_chain->parent_ptes[i])
982 break;
983 if (pte_chain->parent_ptes[i] != parent_pte)
984 continue;
697fe2e2
AK
985 while (i + 1 < NR_PTE_CHAIN_ENTRIES
986 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK
987 pte_chain->parent_ptes[i]
988 = pte_chain->parent_ptes[i + 1];
989 ++i;
990 }
991 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK
992 if (i == 0) {
993 hlist_del(&pte_chain->link);
90cb0529 994 mmu_free_pte_chain(pte_chain);
4db35314
AK
995 if (hlist_empty(&sp->parent_ptes)) {
996 sp->multimapped = 0;
997 sp->parent_pte = NULL;
697fe2e2
AK
998 }
999 }
cea0f0e7
AK
1000 return;
1001 }
1002 BUG();
1003}
1004
ad8cfbe3 1005
6b18493d 1006static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT
1007{
1008 struct kvm_pte_chain *pte_chain;
1009 struct hlist_node *node;
1010 struct kvm_mmu_page *parent_sp;
1011 int i;
1012
1013 if (!sp->multimapped && sp->parent_pte) {
1014 parent_sp = page_header(__pa(sp->parent_pte));
6b18493d
XG
1015 fn(parent_sp);
1016 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT
1017 return;
1018 }
1019 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1020 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1021 if (!pte_chain->parent_ptes[i])
1022 break;
1023 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
6b18493d
XG
1024 fn(parent_sp);
1025 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT
1026 }
1027}
1028
0074ff63
MT
1029static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1030{
1031 unsigned int index;
1032 struct kvm_mmu_page *sp = page_header(__pa(spte));
1033
1034 index = spte - sp->spt;
60c8aec6
MT
1035 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1036 sp->unsync_children++;
1037 WARN_ON(!sp->unsync_children);
0074ff63
MT
1038}
1039
1040static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1041{
1042 struct kvm_pte_chain *pte_chain;
1043 struct hlist_node *node;
1044 int i;
1045
1046 if (!sp->parent_pte)
1047 return;
1048
1049 if (!sp->multimapped) {
1050 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1051 return;
1052 }
1053
1054 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1055 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1056 if (!pte_chain->parent_ptes[i])
1057 break;
1058 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1059 }
1060}
1061
6b18493d 1062static int unsync_walk_fn(struct kvm_mmu_page *sp)
0074ff63 1063{
0074ff63
MT
1064 kvm_mmu_update_parents_unsync(sp);
1065 return 1;
1066}
1067
6b18493d 1068static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1069{
6b18493d 1070 mmu_parent_walk(sp, unsync_walk_fn);
0074ff63
MT
1071 kvm_mmu_update_parents_unsync(sp);
1072}
1073
d761a501
AK
1074static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1075 struct kvm_mmu_page *sp)
1076{
1077 int i;
1078
1079 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1080 sp->spt[i] = shadow_trap_nonpresent_pte;
1081}
1082
e8bc217a
MT
1083static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1084 struct kvm_mmu_page *sp)
1085{
1086 return 1;
1087}
1088
a7052897
MT
1089static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1090{
1091}
1092
60c8aec6
MT
1093#define KVM_PAGE_ARRAY_NR 16
1094
1095struct kvm_mmu_pages {
1096 struct mmu_page_and_offset {
1097 struct kvm_mmu_page *sp;
1098 unsigned int idx;
1099 } page[KVM_PAGE_ARRAY_NR];
1100 unsigned int nr;
1101};
1102
0074ff63
MT
1103#define for_each_unsync_children(bitmap, idx) \
1104 for (idx = find_first_bit(bitmap, 512); \
1105 idx < 512; \
1106 idx = find_next_bit(bitmap, 512, idx+1))
1107
cded19f3
HE
1108static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1109 int idx)
4731d4c7 1110{
60c8aec6 1111 int i;
4731d4c7 1112
60c8aec6
MT
1113 if (sp->unsync)
1114 for (i=0; i < pvec->nr; i++)
1115 if (pvec->page[i].sp == sp)
1116 return 0;
1117
1118 pvec->page[pvec->nr].sp = sp;
1119 pvec->page[pvec->nr].idx = idx;
1120 pvec->nr++;
1121 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1122}
1123
1124static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1125 struct kvm_mmu_pages *pvec)
1126{
1127 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1128
0074ff63 1129 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT
1130 u64 ent = sp->spt[i];
1131
87917239 1132 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT
1133 struct kvm_mmu_page *child;
1134 child = page_header(ent & PT64_BASE_ADDR_MASK);
1135
1136 if (child->unsync_children) {
60c8aec6
MT
1137 if (mmu_pages_add(pvec, child, i))
1138 return -ENOSPC;
1139
1140 ret = __mmu_unsync_walk(child, pvec);
1141 if (!ret)
1142 __clear_bit(i, sp->unsync_child_bitmap);
1143 else if (ret > 0)
1144 nr_unsync_leaf += ret;
1145 else
4731d4c7
MT
1146 return ret;
1147 }
1148
1149 if (child->unsync) {
60c8aec6
MT
1150 nr_unsync_leaf++;
1151 if (mmu_pages_add(pvec, child, i))
1152 return -ENOSPC;
4731d4c7
MT
1153 }
1154 }
1155 }
1156
0074ff63 1157 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT
1158 sp->unsync_children = 0;
1159
60c8aec6
MT
1160 return nr_unsync_leaf;
1161}
1162
1163static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1164 struct kvm_mmu_pages *pvec)
1165{
1166 if (!sp->unsync_children)
1167 return 0;
1168
1169 mmu_pages_add(pvec, sp, 0);
1170 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT
1171}
1172
4db35314 1173static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK
1174{
1175 unsigned index;
1176 struct hlist_head *bucket;
4db35314 1177 struct kvm_mmu_page *sp;
cea0f0e7
AK
1178 struct hlist_node *node;
1179
b8688d51 1180 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1181 index = kvm_page_table_hashfn(gfn);
f05e70ac 1182 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1183 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1184 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1185 && !sp->role.invalid) {
cea0f0e7 1186 pgprintk("%s: found role %x\n",
b8688d51 1187 __func__, sp->role.word);
4db35314 1188 return sp;
cea0f0e7
AK
1189 }
1190 return NULL;
1191}
1192
4731d4c7
MT
1193static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1194{
1195 WARN_ON(!sp->unsync);
5e1b3ddb 1196 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT
1197 sp->unsync = 0;
1198 --kvm->stat.mmu_unsync;
1199}
1200
1201static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1202
1d9dc7e0
XG
1203static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1204 bool clear_unsync)
4731d4c7 1205{
5b7e0102 1206 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT
1207 kvm_mmu_zap_page(vcpu->kvm, sp);
1208 return 1;
1209 }
1210
1d9dc7e0
XG
1211 if (clear_unsync) {
1212 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1213 kvm_flush_remote_tlbs(vcpu->kvm);
1214 kvm_unlink_unsync_page(vcpu->kvm, sp);
1215 }
1216
4731d4c7
MT
1217 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1218 kvm_mmu_zap_page(vcpu->kvm, sp);
1219 return 1;
1220 }
1221
1222 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT
1223 return 0;
1224}
1225
1d9dc7e0
XG
1226static void mmu_convert_notrap(struct kvm_mmu_page *sp);
1227static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1228 struct kvm_mmu_page *sp)
1229{
1230 int ret;
1231
1232 ret = __kvm_sync_page(vcpu, sp, false);
1233 if (!ret)
1234 mmu_convert_notrap(sp);
1235 return ret;
1236}
1237
1238static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1239{
1240 return __kvm_sync_page(vcpu, sp, true);
1241}
1242
60c8aec6
MT
1243struct mmu_page_path {
1244 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1245 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT
1246};
1247
60c8aec6
MT
1248#define for_each_sp(pvec, sp, parents, i) \
1249 for (i = mmu_pages_next(&pvec, &parents, -1), \
1250 sp = pvec.page[i].sp; \
1251 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1252 i = mmu_pages_next(&pvec, &parents, i))
1253
cded19f3
HE
1254static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1255 struct mmu_page_path *parents,
1256 int i)
60c8aec6
MT
1257{
1258 int n;
1259
1260 for (n = i+1; n < pvec->nr; n++) {
1261 struct kvm_mmu_page *sp = pvec->page[n].sp;
1262
1263 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1264 parents->idx[0] = pvec->page[n].idx;
1265 return n;
1266 }
1267
1268 parents->parent[sp->role.level-2] = sp;
1269 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1270 }
1271
1272 return n;
1273}
1274
cded19f3 1275static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1276{
60c8aec6
MT
1277 struct kvm_mmu_page *sp;
1278 unsigned int level = 0;
1279
1280 do {
1281 unsigned int idx = parents->idx[level];
4731d4c7 1282
60c8aec6
MT
1283 sp = parents->parent[level];
1284 if (!sp)
1285 return;
1286
1287 --sp->unsync_children;
1288 WARN_ON((int)sp->unsync_children < 0);
1289 __clear_bit(idx, sp->unsync_child_bitmap);
1290 level++;
1291 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT
1292}
1293
60c8aec6
MT
1294static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1295 struct mmu_page_path *parents,
1296 struct kvm_mmu_pages *pvec)
4731d4c7 1297{
60c8aec6
MT
1298 parents->parent[parent->role.level-1] = NULL;
1299 pvec->nr = 0;
1300}
4731d4c7 1301
60c8aec6
MT
1302static void mmu_sync_children(struct kvm_vcpu *vcpu,
1303 struct kvm_mmu_page *parent)
1304{
1305 int i;
1306 struct kvm_mmu_page *sp;
1307 struct mmu_page_path parents;
1308 struct kvm_mmu_pages pages;
1309
1310 kvm_mmu_pages_init(parent, &parents, &pages);
1311 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT
1312 int protected = 0;
1313
1314 for_each_sp(pages, sp, parents, i)
1315 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1316
1317 if (protected)
1318 kvm_flush_remote_tlbs(vcpu->kvm);
1319
60c8aec6
MT
1320 for_each_sp(pages, sp, parents, i) {
1321 kvm_sync_page(vcpu, sp);
1322 mmu_pages_clear_parents(&parents);
1323 }
4731d4c7 1324 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT
1325 kvm_mmu_pages_init(parent, &parents, &pages);
1326 }
4731d4c7
MT
1327}
1328
cea0f0e7
AK
1329static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1330 gfn_t gfn,
1331 gva_t gaddr,
1332 unsigned level,
f6e2c02b 1333 int direct,
41074d07 1334 unsigned access,
f7d9c7b7 1335 u64 *parent_pte)
cea0f0e7
AK
1336{
1337 union kvm_mmu_page_role role;
1338 unsigned index;
1339 unsigned quadrant;
1340 struct hlist_head *bucket;
e02aa901 1341 struct kvm_mmu_page *sp, *unsync_sp = NULL;
4731d4c7 1342 struct hlist_node *node, *tmp;
cea0f0e7 1343
a770f6f2 1344 role = vcpu->arch.mmu.base_role;
cea0f0e7 1345 role.level = level;
f6e2c02b 1346 role.direct = direct;
84b0c8c6 1347 if (role.direct)
5b7e0102 1348 role.cr4_pae = 0;
41074d07 1349 role.access = access;
ad312c7c 1350 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK
1351 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1352 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1353 role.quadrant = quadrant;
1354 }
1ae0a13d 1355 index = kvm_page_table_hashfn(gfn);
f05e70ac 1356 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT
1357 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1358 if (sp->gfn == gfn) {
1359 if (sp->unsync)
e02aa901 1360 unsync_sp = sp;
4731d4c7
MT
1361
1362 if (sp->role.word != role.word)
1363 continue;
1364
e02aa901
XG
1365 if (!direct && unsync_sp &&
1366 kvm_sync_page_transient(vcpu, unsync_sp)) {
1367 unsync_sp = NULL;
1368 break;
1369 }
1370
4db35314 1371 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT
1372 if (sp->unsync_children) {
1373 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
6b18493d 1374 kvm_mmu_mark_parents_unsync(sp);
e02aa901
XG
1375 } else if (sp->unsync)
1376 kvm_mmu_mark_parents_unsync(sp);
1377
f691fe1d 1378 trace_kvm_mmu_get_page(sp, false);
4db35314 1379 return sp;
cea0f0e7 1380 }
e02aa901
XG
1381 if (!direct && unsync_sp)
1382 kvm_sync_page(vcpu, unsync_sp);
1383
dfc5aa00 1384 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK
1385 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1386 if (!sp)
1387 return sp;
4db35314
AK
1388 sp->gfn = gfn;
1389 sp->role = role;
1390 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1391 if (!direct) {
b1a36821
MT
1392 if (rmap_write_protect(vcpu->kvm, gfn))
1393 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT
1394 account_shadowed(vcpu->kvm, gfn);
1395 }
131d8279
AK
1396 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1397 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1398 else
1399 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1400 trace_kvm_mmu_get_page(sp, true);
4db35314 1401 return sp;
cea0f0e7
AK
1402}
1403
2d11123a
AK
1404static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1405 struct kvm_vcpu *vcpu, u64 addr)
1406{
1407 iterator->addr = addr;
1408 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1409 iterator->level = vcpu->arch.mmu.shadow_root_level;
1410 if (iterator->level == PT32E_ROOT_LEVEL) {
1411 iterator->shadow_addr
1412 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1413 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1414 --iterator->level;
1415 if (!iterator->shadow_addr)
1416 iterator->level = 0;
1417 }
1418}
1419
1420static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1421{
1422 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1423 return false;
4d88954d
MT
1424
1425 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1426 if (is_large_pte(*iterator->sptep))
1427 return false;
1428
2d11123a
AK
1429 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1430 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1431 return true;
1432}
1433
1434static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1435{
1436 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1437 --iterator->level;
1438}
1439
90cb0529 1440static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1441 struct kvm_mmu_page *sp)
a436036b 1442{
697fe2e2
AK
1443 unsigned i;
1444 u64 *pt;
1445 u64 ent;
1446
4db35314 1447 pt = sp->spt;
697fe2e2 1448
697fe2e2
AK
1449 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1450 ent = pt[i];
1451
05da4558 1452 if (is_shadow_present_pte(ent)) {
776e6633 1453 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT
1454 ent &= PT64_BASE_ADDR_MASK;
1455 mmu_page_remove_parent_pte(page_header(ent),
1456 &pt[i]);
1457 } else {
776e6633
MT
1458 if (is_large_pte(ent))
1459 --kvm->stat.lpages;
05da4558
MT
1460 rmap_remove(kvm, &pt[i]);
1461 }
1462 }
c7addb90 1463 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1464 }
a436036b
AK
1465}
1466
4db35314 1467static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1468{
4db35314 1469 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK
1470}
1471
12b7d28f
AK
1472static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1473{
1474 int i;
988a2cae 1475 struct kvm_vcpu *vcpu;
12b7d28f 1476
988a2cae
GN
1477 kvm_for_each_vcpu(i, vcpu, kvm)
1478 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK
1479}
1480
31aa2b44 1481static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK
1482{
1483 u64 *parent_pte;
1484
4db35314
AK
1485 while (sp->multimapped || sp->parent_pte) {
1486 if (!sp->multimapped)
1487 parent_pte = sp->parent_pte;
a436036b
AK
1488 else {
1489 struct kvm_pte_chain *chain;
1490
4db35314 1491 chain = container_of(sp->parent_ptes.first,
a436036b
AK
1492 struct kvm_pte_chain, link);
1493 parent_pte = chain->parent_ptes[0];
1494 }
697fe2e2 1495 BUG_ON(!parent_pte);
4db35314 1496 kvm_mmu_put_page(sp, parent_pte);
d555c333 1497 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1498 }
31aa2b44
AK
1499}
1500
60c8aec6
MT
1501static int mmu_zap_unsync_children(struct kvm *kvm,
1502 struct kvm_mmu_page *parent)
4731d4c7 1503{
60c8aec6
MT
1504 int i, zapped = 0;
1505 struct mmu_page_path parents;
1506 struct kvm_mmu_pages pages;
4731d4c7 1507
60c8aec6 1508 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1509 return 0;
60c8aec6
MT
1510
1511 kvm_mmu_pages_init(parent, &parents, &pages);
1512 while (mmu_unsync_walk(parent, &pages)) {
1513 struct kvm_mmu_page *sp;
1514
1515 for_each_sp(pages, sp, parents, i) {
1516 kvm_mmu_zap_page(kvm, sp);
1517 mmu_pages_clear_parents(&parents);
77662e00 1518 zapped++;
60c8aec6 1519 }
60c8aec6
MT
1520 kvm_mmu_pages_init(parent, &parents, &pages);
1521 }
1522
1523 return zapped;
4731d4c7
MT
1524}
1525
07385413 1526static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1527{
4731d4c7 1528 int ret;
f691fe1d
AK
1529
1530 trace_kvm_mmu_zap_page(sp);
31aa2b44 1531 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1532 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1533 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1534 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1535 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1536 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1537 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT
1538 if (sp->unsync)
1539 kvm_unlink_unsync_page(kvm, sp);
4db35314 1540 if (!sp->root_count) {
54a4f023
GJ
1541 /* Count self */
1542 ret++;
4db35314
AK
1543 hlist_del(&sp->hash_link);
1544 kvm_mmu_free_page(kvm, sp);
2e53d63a 1545 } else {
2e53d63a 1546 sp->role.invalid = 1;
5b5c6a5a 1547 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT
1548 kvm_reload_remote_mmus(kvm);
1549 }
12b7d28f 1550 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1551 return ret;
a436036b
AK
1552}
1553
82ce2c96
IE
1554/*
1555 * Changing the number of mmu pages allocated to the vm
1556 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1557 */
1558void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1559{
025dbbf3
MT
1560 int used_pages;
1561
1562 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1563 used_pages = max(0, used_pages);
1564
82ce2c96
IE
1565 /*
1566 * If we set the number of mmu pages to be smaller be than the
1567 * number of actived pages , we must to free some mmu pages before we
1568 * change the value
1569 */
1570
025dbbf3 1571 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG
1572 while (used_pages > kvm_nr_mmu_pages &&
1573 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE
1574 struct kvm_mmu_page *page;
1575
f05e70ac 1576 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1577 struct kvm_mmu_page, link);
77662e00 1578 used_pages -= kvm_mmu_zap_page(kvm, page);
82ce2c96 1579 }
77662e00 1580 kvm_nr_mmu_pages = used_pages;
f05e70ac 1581 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE
1582 }
1583 else
f05e70ac
ZX
1584 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1585 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1586
f05e70ac 1587 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE
1588}
1589
f67a46f4 1590static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK
1591{
1592 unsigned index;
1593 struct hlist_head *bucket;
4db35314 1594 struct kvm_mmu_page *sp;
a436036b
AK
1595 struct hlist_node *node, *n;
1596 int r;
1597
b8688d51 1598 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1599 r = 0;
1ae0a13d 1600 index = kvm_page_table_hashfn(gfn);
f05e70ac 1601 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1602restart:
4db35314 1603 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1604 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1605 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1606 sp->role.word);
a436036b 1607 r = 1;
07385413 1608 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1609 goto restart;
a436036b
AK
1610 }
1611 return r;
cea0f0e7
AK
1612}
1613
f67a46f4 1614static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1615{
4677a3b6
AK
1616 unsigned index;
1617 struct hlist_head *bucket;
4db35314 1618 struct kvm_mmu_page *sp;
4677a3b6 1619 struct hlist_node *node, *nn;
97a0a01e 1620
4677a3b6
AK
1621 index = kvm_page_table_hashfn(gfn);
1622 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1623restart:
4677a3b6 1624 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1625 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK
1626 && !sp->role.invalid) {
1627 pgprintk("%s: zap %lx %x\n",
1628 __func__, gfn, sp->role.word);
77662e00 1629 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1630 goto restart;
4677a3b6 1631 }
97a0a01e
AK
1632 }
1633}
1634
38c335f1 1635static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1636{
bc6678a3 1637 int slot = memslot_id(kvm, gfn);
4db35314 1638 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1639
291f26bc 1640 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK
1641}
1642
6844dec6
MT
1643static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1644{
1645 int i;
1646 u64 *pt = sp->spt;
1647
1648 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1649 return;
1650
1651 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1652 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1653 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT
1654 }
1655}
1656
74be52e3
SY
1657/*
1658 * The function is based on mtrr_type_lookup() in
1659 * arch/x86/kernel/cpu/mtrr/generic.c
1660 */
1661static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1662 u64 start, u64 end)
1663{
1664 int i;
1665 u64 base, mask;
1666 u8 prev_match, curr_match;
1667 int num_var_ranges = KVM_NR_VAR_MTRR;
1668
1669 if (!mtrr_state->enabled)
1670 return 0xFF;
1671
1672 /* Make end inclusive end, instead of exclusive */
1673 end--;
1674
1675 /* Look in fixed ranges. Just return the type as per start */
1676 if (mtrr_state->have_fixed && (start < 0x100000)) {
1677 int idx;
1678
1679 if (start < 0x80000) {
1680 idx = 0;
1681 idx += (start >> 16);
1682 return mtrr_state->fixed_ranges[idx];
1683 } else if (start < 0xC0000) {
1684 idx = 1 * 8;
1685 idx += ((start - 0x80000) >> 14);
1686 return mtrr_state->fixed_ranges[idx];
1687 } else if (start < 0x1000000) {
1688 idx = 3 * 8;
1689 idx += ((start - 0xC0000) >> 12);
1690 return mtrr_state->fixed_ranges[idx];
1691 }
1692 }
1693
1694 /*
1695 * Look in variable ranges
1696 * Look of multiple ranges matching this address and pick type
1697 * as per MTRR precedence
1698 */
1699 if (!(mtrr_state->enabled & 2))
1700 return mtrr_state->def_type;
1701
1702 prev_match = 0xFF;
1703 for (i = 0; i < num_var_ranges; ++i) {
1704 unsigned short start_state, end_state;
1705
1706 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1707 continue;
1708
1709 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1710 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1711 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1712 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1713
1714 start_state = ((start & mask) == (base & mask));
1715 end_state = ((end & mask) == (base & mask));
1716 if (start_state != end_state)
1717 return 0xFE;
1718
1719 if ((start & mask) != (base & mask))
1720 continue;
1721
1722 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1723 if (prev_match == 0xFF) {
1724 prev_match = curr_match;
1725 continue;
1726 }
1727
1728 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1729 curr_match == MTRR_TYPE_UNCACHABLE)
1730 return MTRR_TYPE_UNCACHABLE;
1731
1732 if ((prev_match == MTRR_TYPE_WRBACK &&
1733 curr_match == MTRR_TYPE_WRTHROUGH) ||
1734 (prev_match == MTRR_TYPE_WRTHROUGH &&
1735 curr_match == MTRR_TYPE_WRBACK)) {
1736 prev_match = MTRR_TYPE_WRTHROUGH;
1737 curr_match = MTRR_TYPE_WRTHROUGH;
1738 }
1739
1740 if (prev_match != curr_match)
1741 return MTRR_TYPE_UNCACHABLE;
1742 }
1743
1744 if (prev_match != 0xFF)
1745 return prev_match;
1746
1747 return mtrr_state->def_type;
1748}
1749
4b12f0de 1750u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY
1751{
1752 u8 mtrr;
1753
1754 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1755 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1756 if (mtrr == 0xfe || mtrr == 0xff)
1757 mtrr = MTRR_TYPE_WRBACK;
1758 return mtrr;
1759}
4b12f0de 1760EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1761
4731d4c7
MT
1762static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1763{
1764 unsigned index;
1765 struct hlist_head *bucket;
1766 struct kvm_mmu_page *s;
1767 struct hlist_node *node, *n;
1768
1769 index = kvm_page_table_hashfn(sp->gfn);
1770 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1771 /* don't unsync if pagetable is shadowed with multiple roles */
1772 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1773 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT
1774 continue;
1775 if (s->role.word != sp->role.word)
1776 return 1;
1777 }
5e1b3ddb 1778 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT
1779 ++vcpu->kvm->stat.mmu_unsync;
1780 sp->unsync = 1;
6cffe8ca 1781
6b18493d 1782 kvm_mmu_mark_parents_unsync(sp);
6cffe8ca 1783
4731d4c7
MT
1784 mmu_convert_notrap(sp);
1785 return 0;
1786}
1787
1788static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1789 bool can_unsync)
1790{
1791 struct kvm_mmu_page *shadow;
1792
1793 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1794 if (shadow) {
1795 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1796 return 1;
1797 if (shadow->unsync)
1798 return 0;
582801a9 1799 if (can_unsync && oos_shadow)
4731d4c7
MT
1800 return kvm_unsync_page(vcpu, shadow);
1801 return 1;
1802 }
1803 return 0;
1804}
1805
d555c333 1806static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1807 unsigned pte_access, int user_fault,
852e3c19 1808 int write_fault, int dirty, int level,
c2d0ee46 1809 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1810 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK
1811{
1812 u64 spte;
1e73f9dd 1813 int ret = 0;
64d4d521 1814
1c4f1fd6
AK
1815 /*
1816 * We don't set the accessed bit, since we sometimes want to see
1817 * whether the guest actually used the pte (in order to detect
1818 * demand paging).
1819 */
7b52345e 1820 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1821 if (!speculative)
3201b5d9 1822 spte |= shadow_accessed_mask;
1c4f1fd6
AK
1823 if (!dirty)
1824 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY
1825 if (pte_access & ACC_EXEC_MASK)
1826 spte |= shadow_x_mask;
1827 else
1828 spte |= shadow_nx_mask;
1c4f1fd6 1829 if (pte_access & ACC_USER_MASK)
7b52345e 1830 spte |= shadow_user_mask;
852e3c19 1831 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1832 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY
1833 if (tdp_enabled)
1834 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1835 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1836
1403283a
IE
1837 if (reset_host_protection)
1838 spte |= SPTE_HOST_WRITEABLE;
1839
35149e21 1840 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK
1841
1842 if ((pte_access & ACC_WRITE_MASK)
1843 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1844
852e3c19
JR
1845 if (level > PT_PAGE_TABLE_LEVEL &&
1846 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83 1847 ret = 1;
6d74229f 1848 rmap_remove(vcpu->kvm, sptep);
38187c83
MT
1849 spte = shadow_trap_nonpresent_pte;
1850 goto set_pte;
1851 }
1852
1c4f1fd6 1853 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1854
69325a12
AK
1855 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1856 spte &= ~PT_USER_MASK;
1857
ecc5589f
MT
1858 /*
1859 * Optimization: for pte sync, if spte was writable the hash
1860 * lookup is unnecessary (and expensive). Write protection
1861 * is responsibility of mmu_get_page / kvm_sync_page.
1862 * Same reasoning can be applied to dirty page accounting.
1863 */
8dae4445 1864 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT
1865 goto set_pte;
1866
4731d4c7 1867 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1868 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1869 __func__, gfn);
1e73f9dd 1870 ret = 1;
1c4f1fd6 1871 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1872 if (is_writable_pte(spte))
1c4f1fd6 1873 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK
1874 }
1875 }
1876
1c4f1fd6
AK
1877 if (pte_access & ACC_WRITE_MASK)
1878 mark_page_dirty(vcpu->kvm, gfn);
1879
38187c83 1880set_pte:
d555c333 1881 __set_spte(sptep, spte);
1e73f9dd
MT
1882 return ret;
1883}
1884
d555c333 1885static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT
1886 unsigned pt_access, unsigned pte_access,
1887 int user_fault, int write_fault, int dirty,
852e3c19 1888 int *ptwrite, int level, gfn_t gfn,
1403283a
IE
1889 pfn_t pfn, bool speculative,
1890 bool reset_host_protection)
1e73f9dd
MT
1891{
1892 int was_rmapped = 0;
8dae4445 1893 int was_writable = is_writable_pte(*sptep);
53a27b39 1894 int rmap_count;
1e73f9dd
MT
1895
1896 pgprintk("%s: spte %llx access %x write_fault %d"
1897 " user_fault %d gfn %lx\n",
d555c333 1898 __func__, *sptep, pt_access,
1e73f9dd
MT
1899 write_fault, user_fault, gfn);
1900
d555c333 1901 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT
1902 /*
1903 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1904 * the parent of the now unreachable PTE.
1905 */
852e3c19
JR
1906 if (level > PT_PAGE_TABLE_LEVEL &&
1907 !is_large_pte(*sptep)) {
1e73f9dd 1908 struct kvm_mmu_page *child;
d555c333 1909 u64 pte = *sptep;
1e73f9dd
MT
1910
1911 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1912 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT
1913 __set_spte(sptep, shadow_trap_nonpresent_pte);
1914 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1915 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1916 pgprintk("hfn old %lx new %lx\n",
d555c333
AK
1917 spte_to_pfn(*sptep), pfn);
1918 rmap_remove(vcpu->kvm, sptep);
91546356
XG
1919 __set_spte(sptep, shadow_trap_nonpresent_pte);
1920 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR
1921 } else
1922 was_rmapped = 1;
1e73f9dd 1923 }
852e3c19 1924
d555c333 1925 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE
1926 dirty, level, gfn, pfn, speculative, true,
1927 reset_host_protection)) {
1e73f9dd
MT
1928 if (write_fault)
1929 *ptwrite = 1;
a378b4e6
MT
1930 kvm_x86_ops->tlb_flush(vcpu);
1931 }
1e73f9dd 1932
d555c333 1933 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1934 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1935 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR
1936 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1937 *sptep, sptep);
d555c333 1938 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT
1939 ++vcpu->kvm->stat.lpages;
1940
d555c333 1941 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1942 if (!was_rmapped) {
44ad9944 1943 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1944 kvm_release_pfn_clean(pfn);
53a27b39 1945 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1946 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1947 } else {
8dae4445 1948 if (was_writable)
35149e21 1949 kvm_release_pfn_dirty(pfn);
75e68e60 1950 else
35149e21 1951 kvm_release_pfn_clean(pfn);
1c4f1fd6 1952 }
1b7fcd32 1953 if (speculative) {
d555c333 1954 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK
1955 vcpu->arch.last_pte_gfn = gfn;
1956 }
1c4f1fd6
AK
1957}
1958
6aa8b732
AK
1959static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1960{
1961}
1962
9f652d21 1963static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1964 int level, gfn_t gfn, pfn_t pfn)
140754bc 1965{
9f652d21 1966 struct kvm_shadow_walk_iterator iterator;
140754bc 1967 struct kvm_mmu_page *sp;
9f652d21 1968 int pt_write = 0;
140754bc 1969 gfn_t pseudo_gfn;
6aa8b732 1970
9f652d21 1971 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1972 if (iterator.level == level) {
9f652d21
AK
1973 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1974 0, write, 1, &pt_write,
1403283a 1975 level, gfn, pfn, false, true);
9f652d21
AK
1976 ++vcpu->stat.pf_fixed;
1977 break;
6aa8b732
AK
1978 }
1979
9f652d21
AK
1980 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1981 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1982 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1983 iterator.level - 1,
1984 1, ACC_ALL, iterator.sptep);
1985 if (!sp) {
1986 pgprintk("nonpaging_map: ENOMEM\n");
1987 kvm_release_pfn_clean(pfn);
1988 return -ENOMEM;
1989 }
140754bc 1990
d555c333
AK
1991 __set_spte(iterator.sptep,
1992 __pa(sp->spt)
1993 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1994 | shadow_user_mask | shadow_x_mask);
9f652d21
AK
1995 }
1996 }
1997 return pt_write;
6aa8b732
AK
1998}
1999
bf998156
HY
2000static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
2001{
2002 char buf[1];
2003 void __user *hva;
2004 int r;
2005
2006 /* Touch the page, so send SIGBUS */
2007 hva = (void __user *)gfn_to_hva(kvm, gfn);
2008 r = copy_from_user(buf, hva, 1);
2009}
2010
2011static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2012{
2013 kvm_release_pfn_clean(pfn);
2014 if (is_hwpoison_pfn(pfn)) {
2015 kvm_send_hwpoison_signal(kvm, gfn);
2016 return 0;
2017 }
2018 return 1;
2019}
2020
10589a46
MT
2021static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2022{
2023 int r;
852e3c19 2024 int level;
35149e21 2025 pfn_t pfn;
e930bffe 2026 unsigned long mmu_seq;
aaee2c94 2027
852e3c19
JR
2028 level = mapping_level(vcpu, gfn);
2029
2030 /*
2031 * This path builds a PAE pagetable - so we can map 2mb pages at
2032 * maximum. Therefore check if the level is larger than that.
2033 */
2034 if (level > PT_DIRECTORY_LEVEL)
2035 level = PT_DIRECTORY_LEVEL;
2036
2037 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2038
e930bffe 2039 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2040 smp_rmb();
35149e21 2041 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2042
d196e343 2043 /* mmio */
bf998156
HY
2044 if (is_error_pfn(pfn))
2045 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2046
aaee2c94 2047 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
2048 if (mmu_notifier_retry(vcpu, mmu_seq))
2049 goto out_unlock;
eb787d10 2050 kvm_mmu_free_some_pages(vcpu);
852e3c19 2051 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT
2052 spin_unlock(&vcpu->kvm->mmu_lock);
2053
aaee2c94 2054
10589a46 2055 return r;
e930bffe
AA
2056
2057out_unlock:
2058 spin_unlock(&vcpu->kvm->mmu_lock);
2059 kvm_release_pfn_clean(pfn);
2060 return 0;
10589a46
MT
2061}
2062
2063
17ac10ad
AK
2064static void mmu_free_roots(struct kvm_vcpu *vcpu)
2065{
2066 int i;
4db35314 2067 struct kvm_mmu_page *sp;
17ac10ad 2068
ad312c7c 2069 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2070 return;
aaee2c94 2071 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX
2072 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2073 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2074
4db35314
AK
2075 sp = page_header(root);
2076 --sp->root_count;
2e53d63a
MT
2077 if (!sp->root_count && sp->role.invalid)
2078 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2079 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2080 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK
2081 return;
2082 }
17ac10ad 2083 for (i = 0; i < 4; ++i) {
ad312c7c 2084 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2085
417726a3 2086 if (root) {
417726a3 2087 root &= PT64_BASE_ADDR_MASK;
4db35314
AK
2088 sp = page_header(root);
2089 --sp->root_count;
2e53d63a
MT
2090 if (!sp->root_count && sp->role.invalid)
2091 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2092 }
ad312c7c 2093 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2094 }
aaee2c94 2095 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2096 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK
2097}
2098
8986ecc0
MT
2099static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2100{
2101 int ret = 0;
2102
2103 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2104 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2105 ret = 1;
2106 }
2107
2108 return ret;
2109}
2110
2111static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK
2112{
2113 int i;
cea0f0e7 2114 gfn_t root_gfn;
4db35314 2115 struct kvm_mmu_page *sp;
f6e2c02b 2116 int direct = 0;
6de4f3ad 2117 u64 pdptr;
3bb65a22 2118
ad312c7c 2119 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2120
ad312c7c
ZX
2121 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2122 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK
2123
2124 ASSERT(!VALID_PAGE(root));
8986ecc0
MT
2125 if (mmu_check_root(vcpu, root_gfn))
2126 return 1;
5a7388c2
EN
2127 if (tdp_enabled) {
2128 direct = 1;
2129 root_gfn = 0;
2130 }
8facbbff 2131 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2132 kvm_mmu_free_some_pages(vcpu);
4db35314 2133 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2134 PT64_ROOT_LEVEL, direct,
fb72d167 2135 ACC_ALL, NULL);
4db35314
AK
2136 root = __pa(sp->spt);
2137 ++sp->root_count;
8facbbff 2138 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2139 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2140 return 0;
17ac10ad 2141 }
f6e2c02b 2142 direct = !is_paging(vcpu);
17ac10ad 2143 for (i = 0; i < 4; ++i) {
ad312c7c 2144 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK
2145
2146 ASSERT(!VALID_PAGE(root));
ad312c7c 2147 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2148 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2149 if (!is_present_gpte(pdptr)) {
ad312c7c 2150 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK
2151 continue;
2152 }
6de4f3ad 2153 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2154 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2155 root_gfn = 0;
8986ecc0
MT
2156 if (mmu_check_root(vcpu, root_gfn))
2157 return 1;
5a7388c2
EN
2158 if (tdp_enabled) {
2159 direct = 1;
2160 root_gfn = i << 30;
2161 }
8facbbff 2162 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2163 kvm_mmu_free_some_pages(vcpu);
4db35314 2164 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2165 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2166 ACC_ALL, NULL);
4db35314
AK
2167 root = __pa(sp->spt);
2168 ++sp->root_count;
8facbbff
AK
2169 spin_unlock(&vcpu->kvm->mmu_lock);
2170
ad312c7c 2171 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2172 }
ad312c7c 2173 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2174 return 0;
17ac10ad
AK
2175}
2176
0ba73cda
MT
2177static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2178{
2179 int i;
2180 struct kvm_mmu_page *sp;
2181
2182 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2183 return;
2184 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2185 hpa_t root = vcpu->arch.mmu.root_hpa;
2186 sp = page_header(root);
2187 mmu_sync_children(vcpu, sp);
2188 return;
2189 }
2190 for (i = 0; i < 4; ++i) {
2191 hpa_t root = vcpu->arch.mmu.pae_root[i];
2192
8986ecc0 2193 if (root && VALID_PAGE(root)) {
0ba73cda
MT
2194 root &= PT64_BASE_ADDR_MASK;
2195 sp = page_header(root);
2196 mmu_sync_children(vcpu, sp);
2197 }
2198 }
2199}
2200
2201void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2202{
2203 spin_lock(&vcpu->kvm->mmu_lock);
2204 mmu_sync_roots(vcpu);
6cffe8ca 2205 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT
2206}
2207
1871c602
GN
2208static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2209 u32 access, u32 *error)
6aa8b732 2210{
1871c602
GN
2211 if (error)
2212 *error = 0;
6aa8b732
AK
2213 return vaddr;
2214}
2215
2216static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2217 u32 error_code)
6aa8b732 2218{
e833240f 2219 gfn_t gfn;
e2dec939 2220 int r;
6aa8b732 2221
b8688d51 2222 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK
2223 r = mmu_topup_memory_caches(vcpu);
2224 if (r)
2225 return r;
714b93da 2226
6aa8b732 2227 ASSERT(vcpu);
ad312c7c 2228 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2229
e833240f 2230 gfn = gva >> PAGE_SHIFT;
6aa8b732 2231
e833240f
AK
2232 return nonpaging_map(vcpu, gva & PAGE_MASK,
2233 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK
2234}
2235
fb72d167
JR
2236static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2237 u32 error_code)
2238{
35149e21 2239 pfn_t pfn;
fb72d167 2240 int r;
852e3c19 2241 int level;
05da4558 2242 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2243 unsigned long mmu_seq;
fb72d167
JR
2244
2245 ASSERT(vcpu);
2246 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2247
2248 r = mmu_topup_memory_caches(vcpu);
2249 if (r)
2250 return r;
2251
852e3c19
JR
2252 level = mapping_level(vcpu, gfn);
2253
2254 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2255
e930bffe 2256 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2257 smp_rmb();
35149e21 2258 pfn = gfn_to_pfn(vcpu->kvm, gfn);
bf998156
HY
2259 if (is_error_pfn(pfn))
2260 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2261 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
2262 if (mmu_notifier_retry(vcpu, mmu_seq))
2263 goto out_unlock;
fb72d167
JR
2264 kvm_mmu_free_some_pages(vcpu);
2265 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2266 level, gfn, pfn);
fb72d167 2267 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR
2268
2269 return r;
e930bffe
AA
2270
2271out_unlock:
2272 spin_unlock(&vcpu->kvm->mmu_lock);
2273 kvm_release_pfn_clean(pfn);
2274 return 0;
fb72d167
JR
2275}
2276
6aa8b732
AK
2277static void nonpaging_free(struct kvm_vcpu *vcpu)
2278{
17ac10ad 2279 mmu_free_roots(vcpu);
6aa8b732
AK
2280}
2281
2282static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2283{
ad312c7c 2284 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
2285
2286 context->new_cr3 = nonpaging_new_cr3;
2287 context->page_fault = nonpaging_page_fault;
6aa8b732
AK
2288 context->gva_to_gpa = nonpaging_gva_to_gpa;
2289 context->free = nonpaging_free;
c7addb90 2290 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2291 context->sync_page = nonpaging_sync_page;
a7052897 2292 context->invlpg = nonpaging_invlpg;
cea0f0e7 2293 context->root_level = 0;
6aa8b732 2294 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2295 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2296 return 0;
2297}
2298
d835dfec 2299void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2300{
1165f5fe 2301 ++vcpu->stat.tlb_flush;
cbdd1bea 2302 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK
2303}
2304
2305static void paging_new_cr3(struct kvm_vcpu *vcpu)
2306{
b8688d51 2307 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2308 mmu_free_roots(vcpu);
6aa8b732
AK
2309}
2310
6aa8b732
AK
2311static void inject_page_fault(struct kvm_vcpu *vcpu,
2312 u64 addr,
2313 u32 err_code)
2314{
c3c91fee 2315 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK
2316}
2317
6aa8b732
AK
2318static void paging_free(struct kvm_vcpu *vcpu)
2319{
2320 nonpaging_free(vcpu);
2321}
2322
82725b20
DE
2323static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2324{
2325 int bit7;
2326
2327 bit7 = (gpte >> 7) & 1;
2328 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2329}
2330
6aa8b732
AK
2331#define PTTYPE 64
2332#include "paging_tmpl.h"
2333#undef PTTYPE
2334
2335#define PTTYPE 32
2336#include "paging_tmpl.h"
2337#undef PTTYPE
2338
82725b20
DE
2339static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2340{
2341 struct kvm_mmu *context = &vcpu->arch.mmu;
2342 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2343 u64 exb_bit_rsvd = 0;
2344
2345 if (!is_nx(vcpu))
2346 exb_bit_rsvd = rsvd_bits(63, 63);
2347 switch (level) {
2348 case PT32_ROOT_LEVEL:
2349 /* no rsvd bits for 2 level 4K page table entries */
2350 context->rsvd_bits_mask[0][1] = 0;
2351 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG
2352 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2353
2354 if (!is_pse(vcpu)) {
2355 context->rsvd_bits_mask[1][1] = 0;
2356 break;
2357 }
2358
82725b20
DE
2359 if (is_cpuid_PSE36())
2360 /* 36bits PSE 4MB page */
2361 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2362 else
2363 /* 32 bits PSE 4MB page */
2364 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE
2365 break;
2366 case PT32E_ROOT_LEVEL:
20c466b5
DE
2367 context->rsvd_bits_mask[0][2] =
2368 rsvd_bits(maxphyaddr, 63) |
2369 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2370 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2371 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE
2372 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2373 rsvd_bits(maxphyaddr, 62); /* PTE */
2374 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2375 rsvd_bits(maxphyaddr, 62) |
2376 rsvd_bits(13, 20); /* large page */
f815bce8 2377 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE
2378 break;
2379 case PT64_ROOT_LEVEL:
2380 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2381 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2382 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2383 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2384 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2385 rsvd_bits(maxphyaddr, 51);
82725b20
DE
2386 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2387 rsvd_bits(maxphyaddr, 51);
2388 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR
2389 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2390 rsvd_bits(maxphyaddr, 51) |
2391 rsvd_bits(13, 29);
82725b20 2392 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY
2393 rsvd_bits(maxphyaddr, 51) |
2394 rsvd_bits(13, 20); /* large page */
f815bce8 2395 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE
2396 break;
2397 }
2398}
2399
17ac10ad 2400static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2401{
ad312c7c 2402 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
2403
2404 ASSERT(is_pae(vcpu));
2405 context->new_cr3 = paging_new_cr3;
2406 context->page_fault = paging64_page_fault;
6aa8b732 2407 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2408 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2409 context->sync_page = paging64_sync_page;
a7052897 2410 context->invlpg = paging64_invlpg;
6aa8b732 2411 context->free = paging_free;
17ac10ad
AK
2412 context->root_level = level;
2413 context->shadow_root_level = level;
17c3ba9d 2414 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2415 return 0;
2416}
2417
17ac10ad
AK
2418static int paging64_init_context(struct kvm_vcpu *vcpu)
2419{
82725b20 2420 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK
2421 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2422}
2423
6aa8b732
AK
2424static int paging32_init_context(struct kvm_vcpu *vcpu)
2425{
ad312c7c 2426 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2427
82725b20 2428 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK
2429 context->new_cr3 = paging_new_cr3;
2430 context->page_fault = paging32_page_fault;
6aa8b732
AK
2431 context->gva_to_gpa = paging32_gva_to_gpa;
2432 context->free = paging_free;
c7addb90 2433 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2434 context->sync_page = paging32_sync_page;
a7052897 2435 context->invlpg = paging32_invlpg;
6aa8b732
AK
2436 context->root_level = PT32_ROOT_LEVEL;
2437 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2438 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
2439 return 0;
2440}
2441
2442static int paging32E_init_context(struct kvm_vcpu *vcpu)
2443{
82725b20 2444 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2445 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK
2446}
2447
fb72d167
JR
2448static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2449{
2450 struct kvm_mmu *context = &vcpu->arch.mmu;
2451
2452 context->new_cr3 = nonpaging_new_cr3;
2453 context->page_fault = tdp_page_fault;
2454 context->free = nonpaging_free;
2455 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2456 context->sync_page = nonpaging_sync_page;
a7052897 2457 context->invlpg = nonpaging_invlpg;
67253af5 2458 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR
2459 context->root_hpa = INVALID_PAGE;
2460
2461 if (!is_paging(vcpu)) {
2462 context->gva_to_gpa = nonpaging_gva_to_gpa;
2463 context->root_level = 0;
2464 } else if (is_long_mode(vcpu)) {
82725b20 2465 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR
2466 context->gva_to_gpa = paging64_gva_to_gpa;
2467 context->root_level = PT64_ROOT_LEVEL;
2468 } else if (is_pae(vcpu)) {
82725b20 2469 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR
2470 context->gva_to_gpa = paging64_gva_to_gpa;
2471 context->root_level = PT32E_ROOT_LEVEL;
2472 } else {
82725b20 2473 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR
2474 context->gva_to_gpa = paging32_gva_to_gpa;
2475 context->root_level = PT32_ROOT_LEVEL;
2476 }
2477
2478 return 0;
2479}
2480
2481static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2482{
a770f6f2
AK
2483 int r;
2484
6aa8b732 2485 ASSERT(vcpu);
ad312c7c 2486 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK
2487
2488 if (!is_paging(vcpu))
a770f6f2 2489 r = nonpaging_init_context(vcpu);
a9058ecd 2490 else if (is_long_mode(vcpu))
a770f6f2 2491 r = paging64_init_context(vcpu);
6aa8b732 2492 else if (is_pae(vcpu))
a770f6f2 2493 r = paging32E_init_context(vcpu);
6aa8b732 2494 else
a770f6f2
AK
2495 r = paging32_init_context(vcpu);
2496
5b7e0102 2497 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2498 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK
2499
2500 return r;
6aa8b732
AK
2501}
2502
fb72d167
JR
2503static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2504{
35149e21
AL
2505 vcpu->arch.update_pte.pfn = bad_pfn;
2506
fb72d167
JR
2507 if (tdp_enabled)
2508 return init_kvm_tdp_mmu(vcpu);
2509 else
2510 return init_kvm_softmmu(vcpu);
2511}
2512
6aa8b732
AK
2513static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2514{
2515 ASSERT(vcpu);
62ad0755
SY
2516 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2517 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 2518 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK
2519}
2520
2521int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK
2522{
2523 destroy_kvm_mmu(vcpu);
2524 return init_kvm_mmu(vcpu);
2525}
8668a3c4 2526EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK
2527
2528int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2529{
714b93da
AK
2530 int r;
2531
e2dec939 2532 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK
2533 if (r)
2534 goto out;
8986ecc0 2535 r = mmu_alloc_roots(vcpu);
8facbbff 2536 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2537 mmu_sync_roots(vcpu);
aaee2c94 2538 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT
2539 if (r)
2540 goto out;
3662cb1c 2541 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2542 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK
2543out:
2544 return r;
6aa8b732 2545}
17c3ba9d
AK
2546EXPORT_SYMBOL_GPL(kvm_mmu_load);
2547
2548void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2549{
2550 mmu_free_roots(vcpu);
2551}
6aa8b732 2552
09072daf 2553static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2554 struct kvm_mmu_page *sp,
ac1b714e
AK
2555 u64 *spte)
2556{
2557 u64 pte;
2558 struct kvm_mmu_page *child;
2559
2560 pte = *spte;
c7addb90 2561 if (is_shadow_present_pte(pte)) {
776e6633 2562 if (is_last_spte(pte, sp->role.level))
290fc38d 2563 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK
2564 else {
2565 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2566 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK
2567 }
2568 }
d555c333 2569 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT
2570 if (is_large_pte(pte))
2571 --vcpu->kvm->stat.lpages;
ac1b714e
AK
2572}
2573
0028425f 2574static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2575 struct kvm_mmu_page *sp,
0028425f 2576 u64 *spte,
489f1d65 2577 const void *new)
0028425f 2578{
30945387 2579 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR
2580 ++vcpu->kvm->stat.mmu_pde_zapped;
2581 return;
30945387 2582 }
0028425f 2583
4cee5764 2584 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2585 if (!sp->role.cr4_pae)
489f1d65 2586 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2587 else
489f1d65 2588 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK
2589}
2590
79539cec
AK
2591static bool need_remote_flush(u64 old, u64 new)
2592{
2593 if (!is_shadow_present_pte(old))
2594 return false;
2595 if (!is_shadow_present_pte(new))
2596 return true;
2597 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2598 return true;
2599 old ^= PT64_NX_MASK;
2600 new ^= PT64_NX_MASK;
2601 return (old & ~new & PT64_PERM_MASK) != 0;
2602}
2603
2604static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2605{
2606 if (need_remote_flush(old, new))
2607 kvm_flush_remote_tlbs(vcpu->kvm);
2608 else
2609 kvm_mmu_flush_tlb(vcpu);
2610}
2611
12b7d28f
AK
2612static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2613{
ad312c7c 2614 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2615
7b52345e 2616 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK
2617}
2618
d7824fff 2619static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2620 u64 gpte)
d7824fff
AK
2621{
2622 gfn_t gfn;
35149e21 2623 pfn_t pfn;
d7824fff 2624
43a3795a 2625 if (!is_present_gpte(gpte))
d7824fff
AK
2626 return;
2627 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2628
e930bffe 2629 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2630 smp_rmb();
35149e21 2631 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2632
35149e21
AL
2633 if (is_error_pfn(pfn)) {
2634 kvm_release_pfn_clean(pfn);
d196e343
AK
2635 return;
2636 }
d7824fff 2637 vcpu->arch.update_pte.gfn = gfn;
35149e21 2638 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK
2639}
2640
1b7fcd32
AK
2641static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2642{
2643 u64 *spte = vcpu->arch.last_pte_updated;
2644
2645 if (spte
2646 && vcpu->arch.last_pte_gfn == gfn
2647 && shadow_accessed_mask
2648 && !(*spte & shadow_accessed_mask)
2649 && is_shadow_present_pte(*spte))
2650 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2651}
2652
09072daf 2653void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT
2654 const u8 *new, int bytes,
2655 bool guest_initiated)
da4a00f0 2656{
9b7a0325 2657 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2658 struct kvm_mmu_page *sp;
0e7bc4b9 2659 struct hlist_node *node, *n;
9b7a0325
AK
2660 struct hlist_head *bucket;
2661 unsigned index;
489f1d65 2662 u64 entry, gentry;
9b7a0325 2663 u64 *spte;
9b7a0325 2664 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2665 unsigned pte_size;
9b7a0325 2666 unsigned page_offset;
0e7bc4b9 2667 unsigned misaligned;
fce0657f 2668 unsigned quadrant;
9b7a0325 2669 int level;
86a5ba02 2670 int flooded = 0;
ac1b714e 2671 int npte;
489f1d65 2672 int r;
08e850c6 2673 int invlpg_counter;
9b7a0325 2674
b8688d51 2675 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2676
08e850c6 2677 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK
2678
2679 /*
2680 * Assume that the pte write on a page table of the same type
2681 * as the current vcpu paging mode. This is nearly always true
2682 * (might be false while changing modes). Note it is verified later
2683 * by update_pte().
2684 */
08e850c6 2685 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2686 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK
2687 if (is_pae(vcpu)) {
2688 gpa &= ~(gpa_t)7;
2689 bytes = 8;
2690 }
2691 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK
2692 if (r)
2693 gentry = 0;
08e850c6
AK
2694 new = (const u8 *)&gentry;
2695 }
2696
2697 switch (bytes) {
2698 case 4:
2699 gentry = *(const u32 *)new;
2700 break;
2701 case 8:
2702 gentry = *(const u64 *)new;
2703 break;
2704 default:
2705 gentry = 0;
2706 break;
72016f3a
AK
2707 }
2708
2709 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2710 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK
2711 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2712 gentry = 0;
1b7fcd32 2713 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2714 kvm_mmu_free_some_pages(vcpu);
4cee5764 2715 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2716 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT
2717 if (guest_initiated) {
2718 if (gfn == vcpu->arch.last_pt_write_gfn
2719 && !last_updated_pte_accessed(vcpu)) {
2720 ++vcpu->arch.last_pt_write_count;
2721 if (vcpu->arch.last_pt_write_count >= 3)
2722 flooded = 1;
2723 } else {
2724 vcpu->arch.last_pt_write_gfn = gfn;
2725 vcpu->arch.last_pt_write_count = 1;
2726 vcpu->arch.last_pte_updated = NULL;
2727 }
86a5ba02 2728 }
1ae0a13d 2729 index = kvm_page_table_hashfn(gfn);
f05e70ac 2730 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
3246af0e
XG
2731
2732restart:
4db35314 2733 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2734 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2735 continue;
5b7e0102 2736 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2737 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2738 misaligned |= bytes < 4;
86a5ba02 2739 if (misaligned || flooded) {
0e7bc4b9
AK
2740 /*
2741 * Misaligned accesses are too much trouble to fix
2742 * up; also, they usually indicate a page is not used
2743 * as a page table.
86a5ba02
AK
2744 *
2745 * If we're seeing too many writes to a page,
2746 * it may no longer be a page table, or we may be
2747 * forking, in which case it is better to unmap the
2748 * page.
0e7bc4b9
AK
2749 */
2750 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2751 gpa, bytes, sp->role.word);
07385413 2752 if (kvm_mmu_zap_page(vcpu->kvm, sp))
3246af0e 2753 goto restart;
4cee5764 2754 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK
2755 continue;
2756 }
9b7a0325 2757 page_offset = offset;
4db35314 2758 level = sp->role.level;
ac1b714e 2759 npte = 1;
5b7e0102 2760 if (!sp->role.cr4_pae) {
ac1b714e
AK
2761 page_offset <<= 1; /* 32->64 */
2762 /*
2763 * A 32-bit pde maps 4MB while the shadow pdes map
2764 * only 2MB. So we need to double the offset again
2765 * and zap two pdes instead of one.
2766 */
2767 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2768 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK
2769 page_offset <<= 1;
2770 npte = 2;
2771 }
fce0657f 2772 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2773 page_offset &= ~PAGE_MASK;
4db35314 2774 if (quadrant != sp->role.quadrant)
fce0657f 2775 continue;
9b7a0325 2776 }
4db35314 2777 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2778 while (npte--) {
79539cec 2779 entry = *spte;
4db35314 2780 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK
2781 if (gentry)
2782 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2783 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2784 ++spte;
9b7a0325 2785 }
9b7a0325 2786 }
c7addb90 2787 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2788 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL
2789 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2790 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2791 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2792 }
da4a00f0
AK
2793}
2794
a436036b
AK
2795int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2796{
10589a46
MT
2797 gpa_t gpa;
2798 int r;
a436036b 2799
60f24784
AK
2800 if (tdp_enabled)
2801 return 0;
2802
1871c602 2803 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2804
aaee2c94 2805 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2806 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2807 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2808 return r;
a436036b 2809}
577bdc49 2810EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2811
22d95b12 2812void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2813{
3b80fffe
IE
2814 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2815 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2816 struct kvm_mmu_page *sp;
ebeace86 2817
f05e70ac 2818 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK
2819 struct kvm_mmu_page, link);
2820 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2821 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK
2822 }
2823}
ebeace86 2824
3067714c
AK
2825int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2826{
2827 int r;
2828 enum emulation_result er;
2829
ad312c7c 2830 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK
2831 if (r < 0)
2832 goto out;
2833
2834 if (!r) {
2835 r = 1;
2836 goto out;
2837 }
2838
b733bfb5
AK
2839 r = mmu_topup_memory_caches(vcpu);
2840 if (r)
2841 goto out;
2842
851ba692 2843 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK
2844
2845 switch (er) {
2846 case EMULATE_DONE:
2847 return 1;
2848 case EMULATE_DO_MMIO:
2849 ++vcpu->stat.mmio_exits;
6d77dbfc 2850 /* fall through */
3067714c 2851 case EMULATE_FAIL:
3f5d18a9 2852 return 0;
3067714c
AK
2853 default:
2854 BUG();
2855 }
2856out:
3067714c
AK
2857 return r;
2858}
2859EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2860
a7052897
MT
2861void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2862{
a7052897 2863 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT
2864 kvm_mmu_flush_tlb(vcpu);
2865 ++vcpu->stat.invlpg;
2866}
2867EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2868
18552672
JR
2869void kvm_enable_tdp(void)
2870{
2871 tdp_enabled = true;
2872}
2873EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2874
5f4cb662
JR
2875void kvm_disable_tdp(void)
2876{
2877 tdp_enabled = false;
2878}
2879EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2880
6aa8b732
AK
2881static void free_mmu_pages(struct kvm_vcpu *vcpu)
2882{
ad312c7c 2883 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK
2884}
2885
2886static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2887{
17ac10ad 2888 struct page *page;
6aa8b732
AK
2889 int i;
2890
2891 ASSERT(vcpu);
2892
17ac10ad
AK
2893 /*
2894 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2895 * Therefore we need to allocate shadow page tables in the first
2896 * 4GB of memory, which happens to fit the DMA32 zone.
2897 */
2898 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2899 if (!page)
d7fa6ab2
WY
2900 return -ENOMEM;
2901
ad312c7c 2902 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2903 for (i = 0; i < 4; ++i)
ad312c7c 2904 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2905
6aa8b732 2906 return 0;
6aa8b732
AK
2907}
2908
8018c27b 2909int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2910{
6aa8b732 2911 ASSERT(vcpu);
ad312c7c 2912 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2913
8018c27b
IM
2914 return alloc_mmu_pages(vcpu);
2915}
6aa8b732 2916
8018c27b
IM
2917int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2918{
2919 ASSERT(vcpu);
ad312c7c 2920 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2921
8018c27b 2922 return init_kvm_mmu(vcpu);
6aa8b732
AK
2923}
2924
2925void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2926{
2927 ASSERT(vcpu);
2928
2929 destroy_kvm_mmu(vcpu);
2930 free_mmu_pages(vcpu);
714b93da 2931 mmu_free_memory_caches(vcpu);
6aa8b732
AK
2932}
2933
90cb0529 2934void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2935{
4db35314 2936 struct kvm_mmu_page *sp;
6aa8b732 2937
f05e70ac 2938 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK
2939 int i;
2940 u64 *pt;
2941
291f26bc 2942 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK
2943 continue;
2944
4db35314 2945 pt = sp->spt;
6aa8b732
AK
2946 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2947 /* avoid RMW */
9647c14c 2948 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2949 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2950 }
171d595d 2951 kvm_flush_remote_tlbs(kvm);
6aa8b732 2952}
37a7d8b0 2953
90cb0529 2954void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2955{
4db35314 2956 struct kvm_mmu_page *sp, *node;
e0fa826f 2957
aaee2c94 2958 spin_lock(&kvm->mmu_lock);
3246af0e 2959restart:
f05e70ac 2960 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413 2961 if (kvm_mmu_zap_page(kvm, sp))
3246af0e
XG
2962 goto restart;
2963
aaee2c94 2964 spin_unlock(&kvm->mmu_lock);
e0fa826f 2965
90cb0529 2966 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL
2967}
2968
d35b8dd9 2969static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
3ee16c81
IE
2970{
2971 struct kvm_mmu_page *page;
2972
2973 page = container_of(kvm->arch.active_mmu_pages.prev,
2974 struct kvm_mmu_page, link);
54a4f023 2975 return kvm_mmu_zap_page(kvm, page);
3ee16c81
IE
2976}
2977
7f8275d0 2978static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3ee16c81
IE
2979{
2980 struct kvm *kvm;
2981 struct kvm *kvm_freed = NULL;
2982 int cache_count = 0;
2983
2984 spin_lock(&kvm_lock);
2985
2986 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 2987 int npages, idx, freed_pages;
3ee16c81 2988
f656ce01 2989 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE
2990 spin_lock(&kvm->mmu_lock);
2991 npages = kvm->arch.n_alloc_mmu_pages -
2992 kvm->arch.n_free_mmu_pages;
2993 cache_count += npages;
2994 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d35b8dd9
GJ
2995 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
2996 cache_count -= freed_pages;
3ee16c81
IE
2997 kvm_freed = kvm;
2998 }
2999 nr_to_scan--;
3000
3001 spin_unlock(&kvm->mmu_lock);
f656ce01 3002 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE
3003 }
3004 if (kvm_freed)
3005 list_move_tail(&kvm_freed->vm_list, &vm_list);
3006
3007 spin_unlock(&kvm_lock);
3008
3009 return cache_count;
3010}
3011
3012static struct shrinker mmu_shrinker = {
3013 .shrink = mmu_shrink,
3014 .seeks = DEFAULT_SEEKS * 10,
3015};
3016
2ddfd20e 3017static void mmu_destroy_caches(void)
b5a33a75
AK
3018{
3019 if (pte_chain_cache)
3020 kmem_cache_destroy(pte_chain_cache);
3021 if (rmap_desc_cache)
3022 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK
3023 if (mmu_page_header_cache)
3024 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
3025}
3026
3ee16c81
IE
3027void kvm_mmu_module_exit(void)
3028{
3029 mmu_destroy_caches();
3030 unregister_shrinker(&mmu_shrinker);
3031}
3032
b5a33a75
AK
3033int kvm_mmu_module_init(void)
3034{
3035 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3036 sizeof(struct kvm_pte_chain),
20c2df83 3037 0, 0, NULL);
b5a33a75
AK
3038 if (!pte_chain_cache)
3039 goto nomem;
3040 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3041 sizeof(struct kvm_rmap_desc),
20c2df83 3042 0, 0, NULL);
b5a33a75
AK
3043 if (!rmap_desc_cache)
3044 goto nomem;
3045
d3d25b04
AK
3046 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3047 sizeof(struct kvm_mmu_page),
20c2df83 3048 0, 0, NULL);
d3d25b04
AK
3049 if (!mmu_page_header_cache)
3050 goto nomem;
3051
3ee16c81
IE
3052 register_shrinker(&mmu_shrinker);
3053
b5a33a75
AK
3054 return 0;
3055
3056nomem:
3ee16c81 3057 mmu_destroy_caches();
b5a33a75
AK
3058 return -ENOMEM;
3059}
3060
3ad82a7e
ZX
3061/*
3062 * Caculate mmu pages needed for kvm.
3063 */
3064unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3065{
3066 int i;
3067 unsigned int nr_mmu_pages;
3068 unsigned int nr_pages = 0;
bc6678a3 3069 struct kvm_memslots *slots;
3ad82a7e 3070
90d83dc3
LJ
3071 slots = kvm_memslots(kvm);
3072
bc6678a3
MT
3073 for (i = 0; i < slots->nmemslots; i++)
3074 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX
3075
3076 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3077 nr_mmu_pages = max(nr_mmu_pages,
3078 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3079
3080 return nr_mmu_pages;
3081}
3082
2f333bcb
MT
3083static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3084 unsigned len)
3085{
3086 if (len > buffer->len)
3087 return NULL;
3088 return buffer->ptr;
3089}
3090
3091static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3092 unsigned len)
3093{
3094 void *ret;
3095
3096 ret = pv_mmu_peek_buffer(buffer, len);
3097 if (!ret)
3098 return ret;
3099 buffer->ptr += len;
3100 buffer->len -= len;
3101 buffer->processed += len;
3102 return ret;
3103}
3104
3105static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3106 gpa_t addr, gpa_t value)
3107{
3108 int bytes = 8;
3109 int r;
3110
3111 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3112 bytes = 4;
3113
3114 r = mmu_topup_memory_caches(vcpu);
3115 if (r)
3116 return r;
3117
3200f405 3118 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT
3119 return -EFAULT;
3120
3121 return 1;
3122}
3123
3124static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3125{
a8cd0244 3126 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT
3127 return 1;
3128}
3129
3130static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3131{
3132 spin_lock(&vcpu->kvm->mmu_lock);
3133 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3134 spin_unlock(&vcpu->kvm->mmu_lock);
3135 return 1;
3136}
3137
3138static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3139 struct kvm_pv_mmu_op_buffer *buffer)
3140{
3141 struct kvm_mmu_op_header *header;
3142
3143 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3144 if (!header)
3145 return 0;
3146 switch (header->op) {
3147 case KVM_MMU_OP_WRITE_PTE: {
3148 struct kvm_mmu_op_write_pte *wpte;
3149
3150 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3151 if (!wpte)
3152 return 0;
3153 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3154 wpte->pte_val);
3155 }
3156 case KVM_MMU_OP_FLUSH_TLB: {
3157 struct kvm_mmu_op_flush_tlb *ftlb;
3158
3159 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3160 if (!ftlb)
3161 return 0;
3162 return kvm_pv_mmu_flush_tlb(vcpu);
3163 }
3164 case KVM_MMU_OP_RELEASE_PT: {
3165 struct kvm_mmu_op_release_pt *rpt;
3166
3167 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3168 if (!rpt)
3169 return 0;
3170 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3171 }
3172 default: return 0;
3173 }
3174}
3175
3176int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3177 gpa_t addr, unsigned long *ret)
3178{
3179 int r;
6ad18fba 3180 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3181
6ad18fba
DH
3182 buffer->ptr = buffer->buf;
3183 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3184 buffer->processed = 0;
2f333bcb 3185
6ad18fba 3186 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT
3187 if (r)
3188 goto out;
3189
6ad18fba
DH
3190 while (buffer->len) {
3191 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT
3192 if (r < 0)
3193 goto out;
3194 if (r == 0)
3195 break;
3196 }
3197
3198 r = 1;
3199out:
6ad18fba 3200 *ret = buffer->processed;
2f333bcb
MT
3201 return r;
3202}
3203
94d8b056
MT
3204int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3205{
3206 struct kvm_shadow_walk_iterator iterator;
3207 int nr_sptes = 0;
3208
3209 spin_lock(&vcpu->kvm->mmu_lock);
3210 for_each_shadow_entry(vcpu, addr, iterator) {
3211 sptes[iterator.level-1] = *iterator.sptep;
3212 nr_sptes++;
3213 if (!is_shadow_present_pte(*iterator.sptep))
3214 break;
3215 }
3216 spin_unlock(&vcpu->kvm->mmu_lock);
3217
3218 return nr_sptes;
3219}
3220EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3221
37a7d8b0
AK
3222#ifdef AUDIT
3223
3224static const char *audit_msg;
3225
3226static gva_t canonicalize(gva_t gva)
3227{
3228#ifdef CONFIG_X86_64
3229 gva = (long long)(gva << 16) >> 16;
3230#endif
3231 return gva;
3232}
3233
08a3732b 3234
805d32de 3235typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT
3236
3237static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3238 inspect_spte_fn fn)
3239{
3240 int i;
3241
3242 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3243 u64 ent = sp->spt[i];
3244
3245 if (is_shadow_present_pte(ent)) {
2920d728 3246 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT
3247 struct kvm_mmu_page *child;
3248 child = page_header(ent & PT64_BASE_ADDR_MASK);
3249 __mmu_spte_walk(kvm, child, fn);
2920d728 3250 } else
805d32de 3251 fn(kvm, &sp->spt[i]);
08a3732b
MT
3252 }
3253 }
3254}
3255
3256static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3257{
3258 int i;
3259 struct kvm_mmu_page *sp;
3260
3261 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3262 return;
3263 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3264 hpa_t root = vcpu->arch.mmu.root_hpa;
3265 sp = page_header(root);
3266 __mmu_spte_walk(vcpu->kvm, sp, fn);
3267 return;
3268 }
3269 for (i = 0; i < 4; ++i) {
3270 hpa_t root = vcpu->arch.mmu.pae_root[i];
3271
3272 if (root && VALID_PAGE(root)) {
3273 root &= PT64_BASE_ADDR_MASK;
3274 sp = page_header(root);
3275 __mmu_spte_walk(vcpu->kvm, sp, fn);
3276 }
3277 }
3278 return;
3279}
3280
37a7d8b0
AK
3281static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3282 gva_t va, int level)
3283{
3284 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3285 int i;
3286 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3287
3288 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3289 u64 ent = pt[i];
3290
c7addb90 3291 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK
3292 continue;
3293
3294 va = canonicalize(va);
2920d728
MT
3295 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3296 audit_mappings_page(vcpu, ent, va, level - 1);
3297 else {
1871c602 3298 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK
3299 gfn_t gfn = gpa >> PAGE_SHIFT;
3300 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3301 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3302
2aaf65e8
MT
3303 if (is_error_pfn(pfn)) {
3304 kvm_release_pfn_clean(pfn);
3305 continue;
3306 }
3307
c7addb90 3308 if (is_shadow_present_pte(ent)
37a7d8b0 3309 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK
3310 printk(KERN_ERR "xx audit error: (%s) levels %d"
3311 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3312 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD
3313 va, gpa, hpa, ent,
3314 is_shadow_present_pte(ent));
c7addb90
AK
3315 else if (ent == shadow_notrap_nonpresent_pte
3316 && !is_error_hpa(hpa))
3317 printk(KERN_ERR "audit: (%s) notrap shadow,"
3318 " valid guest gva %lx\n", audit_msg, va);
35149e21 3319 kvm_release_pfn_clean(pfn);
c7addb90 3320
37a7d8b0
AK
3321 }
3322 }
3323}
3324
3325static void audit_mappings(struct kvm_vcpu *vcpu)
3326{
1ea252af 3327 unsigned i;
37a7d8b0 3328
ad312c7c
ZX
3329 if (vcpu->arch.mmu.root_level == 4)
3330 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK
3331 else
3332 for (i = 0; i < 4; ++i)
ad312c7c 3333 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3334 audit_mappings_page(vcpu,
ad312c7c 3335 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK
3336 i << 30,
3337 2);
3338}
3339
3340static int count_rmaps(struct kvm_vcpu *vcpu)
3341{
805d32de
XG
3342 struct kvm *kvm = vcpu->kvm;
3343 struct kvm_memslots *slots;
37a7d8b0 3344 int nmaps = 0;
bc6678a3 3345 int i, j, k, idx;
37a7d8b0 3346
bc6678a3 3347 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3348 slots = kvm_memslots(kvm);
37a7d8b0 3349 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3350 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK
3351 struct kvm_rmap_desc *d;
3352
3353 for (j = 0; j < m->npages; ++j) {
290fc38d 3354 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3355
290fc38d 3356 if (!*rmapp)
37a7d8b0 3357 continue;
290fc38d 3358 if (!(*rmapp & 1)) {
37a7d8b0
AK
3359 ++nmaps;
3360 continue;
3361 }
290fc38d 3362 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK
3363 while (d) {
3364 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3365 if (d->sptes[k])
37a7d8b0
AK
3366 ++nmaps;
3367 else
3368 break;
3369 d = d->more;
3370 }
3371 }
3372 }
bc6678a3 3373 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK
3374 return nmaps;
3375}
3376
805d32de 3377void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT
3378{
3379 unsigned long *rmapp;
3380 struct kvm_mmu_page *rev_sp;
3381 gfn_t gfn;
3382
3383 if (*sptep & PT_WRITABLE_MASK) {
3384 rev_sp = page_header(__pa(sptep));
3385 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3386
3387 if (!gfn_to_memslot(kvm, gfn)) {
3388 if (!printk_ratelimit())
3389 return;
3390 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3391 audit_msg, gfn);
3392 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3393 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT
3394 rev_sp->gfn);
3395 dump_stack();
3396 return;
3397 }
3398
2920d728 3399 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3400 rev_sp->role.level);
08a3732b
MT
3401 if (!*rmapp) {
3402 if (!printk_ratelimit())
3403 return;
3404 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3405 audit_msg, *sptep);
3406 dump_stack();
3407 }
3408 }
3409
3410}
3411
3412void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3413{
3414 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3415}
3416
3417static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3418{
4db35314 3419 struct kvm_mmu_page *sp;
37a7d8b0
AK
3420 int i;
3421
f05e70ac 3422 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3423 u64 *pt = sp->spt;
37a7d8b0 3424
4db35314 3425 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK
3426 continue;
3427
3428 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3429 u64 ent = pt[i];
3430
3431 if (!(ent & PT_PRESENT_MASK))
3432 continue;
3433 if (!(ent & PT_WRITABLE_MASK))
3434 continue;
805d32de 3435 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK
3436 }
3437 }
08a3732b 3438 return;
37a7d8b0
AK
3439}
3440
3441static void audit_rmap(struct kvm_vcpu *vcpu)
3442{
08a3732b
MT
3443 check_writable_mappings_rmap(vcpu);
3444 count_rmaps(vcpu);
37a7d8b0
AK
3445}
3446
3447static void audit_write_protection(struct kvm_vcpu *vcpu)
3448{
4db35314 3449 struct kvm_mmu_page *sp;
290fc38d
IE
3450 struct kvm_memory_slot *slot;
3451 unsigned long *rmapp;
e58b0f9e 3452 u64 *spte;
290fc38d 3453 gfn_t gfn;
37a7d8b0 3454
f05e70ac 3455 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3456 if (sp->role.direct)
37a7d8b0 3457 continue;
e58b0f9e
MT
3458 if (sp->unsync)
3459 continue;
37a7d8b0 3460
4db35314 3461 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3462 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3463 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT
3464
3465 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3466 while (spte) {
3467 if (*spte & PT_WRITABLE_MASK)
3468 printk(KERN_ERR "%s: (%s) shadow page has "
3469 "writable mappings: gfn %lx role %x\n",
b8688d51 3470 __func__, audit_msg, sp->gfn,
4db35314 3471 sp->role.word);
e58b0f9e
MT
3472 spte = rmap_next(vcpu->kvm, rmapp, spte);
3473 }
37a7d8b0
AK
3474 }
3475}
3476
3477static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3478{
3479 int olddbg = dbg;
3480
3481 dbg = 0;
3482 audit_msg = msg;
3483 audit_rmap(vcpu);
3484 audit_write_protection(vcpu);
2aaf65e8
MT
3485 if (strcmp("pre pte write", audit_msg) != 0)
3486 audit_mappings(vcpu);
08a3732b 3487 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK
3488 dbg = olddbg;
3489}
3490
3491#endif