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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
37a7d8b0 AK |
52 | #undef MMU_DEBUG |
53 | ||
54 | #undef AUDIT | |
55 | ||
56 | #ifdef AUDIT | |
57 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
58 | #else | |
59 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
60 | #endif | |
61 | ||
62 | #ifdef MMU_DEBUG | |
63 | ||
64 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
65 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
66 | ||
67 | #else | |
68 | ||
69 | #define pgprintk(x...) do { } while (0) | |
70 | #define rmap_printk(x...) do { } while (0) | |
71 | ||
72 | #endif | |
73 | ||
74 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
75 | static int dbg = 0; |
76 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 77 | #endif |
6aa8b732 | 78 | |
582801a9 MT |
79 | static int oos_shadow = 1; |
80 | module_param(oos_shadow, bool, 0644); | |
81 | ||
d6c69ee9 YD |
82 | #ifndef MMU_DEBUG |
83 | #define ASSERT(x) do { } while (0) | |
84 | #else | |
6aa8b732 AK |
85 | #define ASSERT(x) \ |
86 | if (!(x)) { \ | |
87 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
88 | __FILE__, __LINE__, #x); \ | |
89 | } | |
d6c69ee9 | 90 | #endif |
6aa8b732 | 91 | |
6aa8b732 AK |
92 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
93 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
94 | ||
6aa8b732 AK |
95 | #define PT64_LEVEL_BITS 9 |
96 | ||
97 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 98 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
99 | |
100 | #define PT64_LEVEL_MASK(level) \ | |
101 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
102 | ||
103 | #define PT64_INDEX(address, level)\ | |
104 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
105 | ||
106 | ||
107 | #define PT32_LEVEL_BITS 10 | |
108 | ||
109 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 110 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
111 | |
112 | #define PT32_LEVEL_MASK(level) \ | |
113 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
114 | #define PT32_LVL_OFFSET_MASK(level) \ |
115 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
117 | |
118 | #define PT32_INDEX(address, level)\ | |
119 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
120 | ||
121 | ||
27aba766 | 122 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
123 | #define PT64_DIR_BASE_ADDR_MASK \ |
124 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT64_LVL_ADDR_MASK(level) \ |
126 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
128 | #define PT64_LVL_OFFSET_MASK(level) \ | |
129 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
131 | |
132 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
133 | #define PT32_DIR_BASE_ADDR_MASK \ | |
134 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
135 | #define PT32_LVL_ADDR_MASK(level) \ |
136 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
137 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 138 | |
79539cec AK |
139 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
140 | | PT64_NX_MASK) | |
6aa8b732 | 141 | |
cd4a4e53 AK |
142 | #define RMAP_EXT 4 |
143 | ||
fe135d2c AK |
144 | #define ACC_EXEC_MASK 1 |
145 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
146 | #define ACC_USER_MASK PT_USER_MASK | |
147 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
148 | ||
90bb6fc5 AK |
149 | #include <trace/events/kvm.h> |
150 | ||
07420171 AK |
151 | #define CREATE_TRACE_POINTS |
152 | #include "mmutrace.h" | |
153 | ||
1403283a IE |
154 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
155 | ||
135f8c2b AK |
156 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
157 | ||
cd4a4e53 | 158 | struct kvm_rmap_desc { |
d555c333 | 159 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
160 | struct kvm_rmap_desc *more; |
161 | }; | |
162 | ||
2d11123a AK |
163 | struct kvm_shadow_walk_iterator { |
164 | u64 addr; | |
165 | hpa_t shadow_addr; | |
166 | int level; | |
167 | u64 *sptep; | |
168 | unsigned index; | |
169 | }; | |
170 | ||
171 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
172 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
173 | shadow_walk_okay(&(_walker)); \ | |
174 | shadow_walk_next(&(_walker))) | |
175 | ||
1047df1f | 176 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 177 | |
b5a33a75 AK |
178 | static struct kmem_cache *pte_chain_cache; |
179 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 180 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 181 | |
c7addb90 AK |
182 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
183 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
184 | static u64 __read_mostly shadow_base_present_pte; |
185 | static u64 __read_mostly shadow_nx_mask; | |
186 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
187 | static u64 __read_mostly shadow_user_mask; | |
188 | static u64 __read_mostly shadow_accessed_mask; | |
189 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 190 | |
82725b20 DE |
191 | static inline u64 rsvd_bits(int s, int e) |
192 | { | |
193 | return ((1ULL << (e - s + 1)) - 1) << s; | |
194 | } | |
195 | ||
c7addb90 AK |
196 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
197 | { | |
198 | shadow_trap_nonpresent_pte = trap_pte; | |
199 | shadow_notrap_nonpresent_pte = notrap_pte; | |
200 | } | |
201 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
202 | ||
7b52345e SY |
203 | void kvm_mmu_set_base_ptes(u64 base_pte) |
204 | { | |
205 | shadow_base_present_pte = base_pte; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
208 | ||
209 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 210 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
211 | { |
212 | shadow_user_mask = user_mask; | |
213 | shadow_accessed_mask = accessed_mask; | |
214 | shadow_dirty_mask = dirty_mask; | |
215 | shadow_nx_mask = nx_mask; | |
216 | shadow_x_mask = x_mask; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
219 | ||
3dbe1415 | 220 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 221 | { |
4d4ec087 | 222 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
223 | } |
224 | ||
225 | static int is_cpuid_PSE36(void) | |
226 | { | |
227 | return 1; | |
228 | } | |
229 | ||
73b1087e AK |
230 | static int is_nx(struct kvm_vcpu *vcpu) |
231 | { | |
f6801dff | 232 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
233 | } |
234 | ||
c7addb90 AK |
235 | static int is_shadow_present_pte(u64 pte) |
236 | { | |
c7addb90 AK |
237 | return pte != shadow_trap_nonpresent_pte |
238 | && pte != shadow_notrap_nonpresent_pte; | |
239 | } | |
240 | ||
05da4558 MT |
241 | static int is_large_pte(u64 pte) |
242 | { | |
243 | return pte & PT_PAGE_SIZE_MASK; | |
244 | } | |
245 | ||
8dae4445 | 246 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
247 | { |
248 | return pte & PT_WRITABLE_MASK; | |
249 | } | |
250 | ||
43a3795a | 251 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 252 | { |
439e218a | 253 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
254 | } |
255 | ||
43a3795a | 256 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 257 | { |
4b1a80fa | 258 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
259 | } |
260 | ||
776e6633 MT |
261 | static int is_last_spte(u64 pte, int level) |
262 | { | |
263 | if (level == PT_PAGE_TABLE_LEVEL) | |
264 | return 1; | |
852e3c19 | 265 | if (is_large_pte(pte)) |
776e6633 MT |
266 | return 1; |
267 | return 0; | |
268 | } | |
269 | ||
35149e21 | 270 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 271 | { |
35149e21 | 272 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
273 | } |
274 | ||
da928521 AK |
275 | static gfn_t pse36_gfn_delta(u32 gpte) |
276 | { | |
277 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
278 | ||
279 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
280 | } | |
281 | ||
d555c333 | 282 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 283 | { |
7645e432 | 284 | set_64bit(sptep, spte); |
e663ee64 AK |
285 | } |
286 | ||
a9221dd5 AK |
287 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
288 | { | |
289 | #ifdef CONFIG_X86_64 | |
290 | return xchg(sptep, new_spte); | |
291 | #else | |
292 | u64 old_spte; | |
293 | ||
294 | do { | |
295 | old_spte = *sptep; | |
296 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
297 | ||
298 | return old_spte; | |
299 | #endif | |
300 | } | |
301 | ||
b79b93f9 AK |
302 | static void update_spte(u64 *sptep, u64 new_spte) |
303 | { | |
304 | u64 old_spte; | |
305 | ||
be233d49 XG |
306 | if (!shadow_accessed_mask || (new_spte & shadow_accessed_mask) || |
307 | !is_rmap_spte(*sptep)) | |
b79b93f9 | 308 | __set_spte(sptep, new_spte); |
be233d49 | 309 | else { |
b79b93f9 AK |
310 | old_spte = __xchg_spte(sptep, new_spte); |
311 | if (old_spte & shadow_accessed_mask) | |
251464c4 | 312 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
b79b93f9 AK |
313 | } |
314 | } | |
315 | ||
e2dec939 | 316 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 317 | struct kmem_cache *base_cache, int min) |
714b93da AK |
318 | { |
319 | void *obj; | |
320 | ||
321 | if (cache->nobjs >= min) | |
e2dec939 | 322 | return 0; |
714b93da | 323 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 324 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 325 | if (!obj) |
e2dec939 | 326 | return -ENOMEM; |
714b93da AK |
327 | cache->objects[cache->nobjs++] = obj; |
328 | } | |
e2dec939 | 329 | return 0; |
714b93da AK |
330 | } |
331 | ||
e8ad9a70 XG |
332 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
333 | struct kmem_cache *cache) | |
714b93da AK |
334 | { |
335 | while (mc->nobjs) | |
e8ad9a70 | 336 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
337 | } |
338 | ||
c1158e63 | 339 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 340 | int min) |
c1158e63 AK |
341 | { |
342 | struct page *page; | |
343 | ||
344 | if (cache->nobjs >= min) | |
345 | return 0; | |
346 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 347 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
348 | if (!page) |
349 | return -ENOMEM; | |
c1158e63 AK |
350 | cache->objects[cache->nobjs++] = page_address(page); |
351 | } | |
352 | return 0; | |
353 | } | |
354 | ||
355 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
356 | { | |
357 | while (mc->nobjs) | |
c4d198d5 | 358 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
359 | } |
360 | ||
2e3e5882 | 361 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 362 | { |
e2dec939 AK |
363 | int r; |
364 | ||
ad312c7c | 365 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 366 | pte_chain_cache, 4); |
e2dec939 AK |
367 | if (r) |
368 | goto out; | |
ad312c7c | 369 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
c41ef344 | 370 | rmap_desc_cache, 4); |
d3d25b04 AK |
371 | if (r) |
372 | goto out; | |
ad312c7c | 373 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
374 | if (r) |
375 | goto out; | |
ad312c7c | 376 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 377 | mmu_page_header_cache, 4); |
e2dec939 AK |
378 | out: |
379 | return r; | |
714b93da AK |
380 | } |
381 | ||
382 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
383 | { | |
e8ad9a70 XG |
384 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
385 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 386 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
387 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
388 | mmu_page_header_cache); | |
714b93da AK |
389 | } |
390 | ||
391 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
392 | size_t size) | |
393 | { | |
394 | void *p; | |
395 | ||
396 | BUG_ON(!mc->nobjs); | |
397 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
398 | return p; |
399 | } | |
400 | ||
714b93da AK |
401 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
402 | { | |
ad312c7c | 403 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
404 | sizeof(struct kvm_pte_chain)); |
405 | } | |
406 | ||
90cb0529 | 407 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 408 | { |
e8ad9a70 | 409 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
410 | } |
411 | ||
412 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
413 | { | |
ad312c7c | 414 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
415 | sizeof(struct kvm_rmap_desc)); |
416 | } | |
417 | ||
90cb0529 | 418 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 419 | { |
e8ad9a70 | 420 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
421 | } |
422 | ||
2032a93d LJ |
423 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
424 | { | |
425 | if (!sp->role.direct) | |
426 | return sp->gfns[index]; | |
427 | ||
428 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
429 | } | |
430 | ||
431 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
432 | { | |
433 | if (sp->role.direct) | |
434 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
435 | else | |
436 | sp->gfns[index] = gfn; | |
437 | } | |
438 | ||
05da4558 MT |
439 | /* |
440 | * Return the pointer to the largepage write count for a given | |
441 | * gfn, handling slots that are not large page aligned. | |
442 | */ | |
d25797b2 JR |
443 | static int *slot_largepage_idx(gfn_t gfn, |
444 | struct kvm_memory_slot *slot, | |
445 | int level) | |
05da4558 MT |
446 | { |
447 | unsigned long idx; | |
448 | ||
82855413 JR |
449 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
450 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 451 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
452 | } |
453 | ||
454 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
455 | { | |
d25797b2 | 456 | struct kvm_memory_slot *slot; |
05da4558 | 457 | int *write_count; |
d25797b2 | 458 | int i; |
05da4558 | 459 | |
a1f4d395 | 460 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
461 | for (i = PT_DIRECTORY_LEVEL; |
462 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
463 | write_count = slot_largepage_idx(gfn, slot, i); | |
464 | *write_count += 1; | |
465 | } | |
05da4558 MT |
466 | } |
467 | ||
468 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
469 | { | |
d25797b2 | 470 | struct kvm_memory_slot *slot; |
05da4558 | 471 | int *write_count; |
d25797b2 | 472 | int i; |
05da4558 | 473 | |
a1f4d395 | 474 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
475 | for (i = PT_DIRECTORY_LEVEL; |
476 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
477 | write_count = slot_largepage_idx(gfn, slot, i); |
478 | *write_count -= 1; | |
479 | WARN_ON(*write_count < 0); | |
480 | } | |
05da4558 MT |
481 | } |
482 | ||
d25797b2 JR |
483 | static int has_wrprotected_page(struct kvm *kvm, |
484 | gfn_t gfn, | |
485 | int level) | |
05da4558 | 486 | { |
2843099f | 487 | struct kvm_memory_slot *slot; |
05da4558 MT |
488 | int *largepage_idx; |
489 | ||
a1f4d395 | 490 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 491 | if (slot) { |
d25797b2 | 492 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
493 | return *largepage_idx; |
494 | } | |
495 | ||
496 | return 1; | |
497 | } | |
498 | ||
d25797b2 | 499 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 500 | { |
8f0b1ab6 | 501 | unsigned long page_size; |
d25797b2 | 502 | int i, ret = 0; |
05da4558 | 503 | |
8f0b1ab6 | 504 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 505 | |
d25797b2 JR |
506 | for (i = PT_PAGE_TABLE_LEVEL; |
507 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
508 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
509 | ret = i; | |
510 | else | |
511 | break; | |
512 | } | |
513 | ||
4c2155ce | 514 | return ret; |
05da4558 MT |
515 | } |
516 | ||
d25797b2 | 517 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
518 | { |
519 | struct kvm_memory_slot *slot; | |
878403b7 | 520 | int host_level, level, max_level; |
05da4558 MT |
521 | |
522 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
523 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 524 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 525 | |
d25797b2 JR |
526 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
527 | ||
528 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
529 | return host_level; | |
530 | ||
878403b7 SY |
531 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
532 | kvm_x86_ops->get_lpage_level() : host_level; | |
533 | ||
534 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
535 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
536 | break; | |
d25797b2 JR |
537 | |
538 | return level - 1; | |
05da4558 MT |
539 | } |
540 | ||
290fc38d IE |
541 | /* |
542 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
543 | */ |
544 | ||
44ad9944 | 545 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
546 | { |
547 | struct kvm_memory_slot *slot; | |
05da4558 | 548 | unsigned long idx; |
290fc38d IE |
549 | |
550 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 551 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
552 | return &slot->rmap[gfn - slot->base_gfn]; |
553 | ||
82855413 JR |
554 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
555 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 556 | |
44ad9944 | 557 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
558 | } |
559 | ||
cd4a4e53 AK |
560 | /* |
561 | * Reverse mapping data structures: | |
562 | * | |
290fc38d IE |
563 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
564 | * that points to page_address(page). | |
cd4a4e53 | 565 | * |
290fc38d IE |
566 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
567 | * containing more mappings. | |
53a27b39 MT |
568 | * |
569 | * Returns the number of rmap entries before the spte was added or zero if | |
570 | * the spte was not added. | |
571 | * | |
cd4a4e53 | 572 | */ |
44ad9944 | 573 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 574 | { |
4db35314 | 575 | struct kvm_mmu_page *sp; |
cd4a4e53 | 576 | struct kvm_rmap_desc *desc; |
290fc38d | 577 | unsigned long *rmapp; |
53a27b39 | 578 | int i, count = 0; |
cd4a4e53 | 579 | |
43a3795a | 580 | if (!is_rmap_spte(*spte)) |
53a27b39 | 581 | return count; |
4db35314 | 582 | sp = page_header(__pa(spte)); |
2032a93d | 583 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 584 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 585 | if (!*rmapp) { |
cd4a4e53 | 586 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
587 | *rmapp = (unsigned long)spte; |
588 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 589 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 590 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
591 | desc->sptes[0] = (u64 *)*rmapp; |
592 | desc->sptes[1] = spte; | |
290fc38d | 593 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
594 | } else { |
595 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 596 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 597 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 598 | desc = desc->more; |
53a27b39 MT |
599 | count += RMAP_EXT; |
600 | } | |
d555c333 | 601 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 602 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
603 | desc = desc->more; |
604 | } | |
d555c333 | 605 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 606 | ; |
d555c333 | 607 | desc->sptes[i] = spte; |
cd4a4e53 | 608 | } |
53a27b39 | 609 | return count; |
cd4a4e53 AK |
610 | } |
611 | ||
290fc38d | 612 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
613 | struct kvm_rmap_desc *desc, |
614 | int i, | |
615 | struct kvm_rmap_desc *prev_desc) | |
616 | { | |
617 | int j; | |
618 | ||
d555c333 | 619 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 620 | ; |
d555c333 AK |
621 | desc->sptes[i] = desc->sptes[j]; |
622 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
623 | if (j != 0) |
624 | return; | |
625 | if (!prev_desc && !desc->more) | |
d555c333 | 626 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
627 | else |
628 | if (prev_desc) | |
629 | prev_desc->more = desc->more; | |
630 | else | |
290fc38d | 631 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 632 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
633 | } |
634 | ||
290fc38d | 635 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 636 | { |
cd4a4e53 AK |
637 | struct kvm_rmap_desc *desc; |
638 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 639 | struct kvm_mmu_page *sp; |
2032a93d | 640 | gfn_t gfn; |
290fc38d | 641 | unsigned long *rmapp; |
cd4a4e53 AK |
642 | int i; |
643 | ||
4db35314 | 644 | sp = page_header(__pa(spte)); |
2032a93d LJ |
645 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
646 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 647 | if (!*rmapp) { |
19ada5c4 | 648 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 649 | BUG(); |
290fc38d | 650 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 651 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 652 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 653 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
654 | BUG(); |
655 | } | |
290fc38d | 656 | *rmapp = 0; |
cd4a4e53 | 657 | } else { |
19ada5c4 | 658 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 659 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
660 | prev_desc = NULL; |
661 | while (desc) { | |
d555c333 AK |
662 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
663 | if (desc->sptes[i] == spte) { | |
290fc38d | 664 | rmap_desc_remove_entry(rmapp, |
714b93da | 665 | desc, i, |
cd4a4e53 AK |
666 | prev_desc); |
667 | return; | |
668 | } | |
669 | prev_desc = desc; | |
670 | desc = desc->more; | |
671 | } | |
19ada5c4 | 672 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
673 | BUG(); |
674 | } | |
675 | } | |
676 | ||
e4b502ea | 677 | static void set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 678 | { |
ce061867 | 679 | pfn_t pfn; |
9a3aad70 XG |
680 | u64 old_spte = *sptep; |
681 | ||
682 | if (!shadow_accessed_mask || !is_shadow_present_pte(old_spte) || | |
683 | old_spte & shadow_accessed_mask) { | |
684 | __set_spte(sptep, new_spte); | |
685 | } else | |
686 | old_spte = __xchg_spte(sptep, new_spte); | |
ce061867 | 687 | |
a9221dd5 | 688 | if (!is_rmap_spte(old_spte)) |
ce061867 | 689 | return; |
a9221dd5 | 690 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 691 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 692 | kvm_set_pfn_accessed(pfn); |
a9221dd5 | 693 | if (is_writable_pte(old_spte)) |
ce061867 | 694 | kvm_set_pfn_dirty(pfn); |
e4b502ea XG |
695 | } |
696 | ||
697 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
698 | { | |
699 | set_spte_track_bits(sptep, new_spte); | |
be38d276 | 700 | rmap_remove(kvm, sptep); |
be38d276 AK |
701 | } |
702 | ||
98348e95 | 703 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 704 | { |
374cbac0 | 705 | struct kvm_rmap_desc *desc; |
98348e95 IE |
706 | u64 *prev_spte; |
707 | int i; | |
708 | ||
709 | if (!*rmapp) | |
710 | return NULL; | |
711 | else if (!(*rmapp & 1)) { | |
712 | if (!spte) | |
713 | return (u64 *)*rmapp; | |
714 | return NULL; | |
715 | } | |
716 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
717 | prev_spte = NULL; |
718 | while (desc) { | |
d555c333 | 719 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 720 | if (prev_spte == spte) |
d555c333 AK |
721 | return desc->sptes[i]; |
722 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
723 | } |
724 | desc = desc->more; | |
725 | } | |
726 | return NULL; | |
727 | } | |
728 | ||
b1a36821 | 729 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 730 | { |
290fc38d | 731 | unsigned long *rmapp; |
374cbac0 | 732 | u64 *spte; |
44ad9944 | 733 | int i, write_protected = 0; |
374cbac0 | 734 | |
44ad9944 | 735 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 736 | |
98348e95 IE |
737 | spte = rmap_next(kvm, rmapp, NULL); |
738 | while (spte) { | |
374cbac0 | 739 | BUG_ON(!spte); |
374cbac0 | 740 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 741 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 742 | if (is_writable_pte(*spte)) { |
b79b93f9 | 743 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
744 | write_protected = 1; |
745 | } | |
9647c14c | 746 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 747 | } |
855149aa | 748 | if (write_protected) { |
35149e21 | 749 | pfn_t pfn; |
855149aa IE |
750 | |
751 | spte = rmap_next(kvm, rmapp, NULL); | |
35149e21 AL |
752 | pfn = spte_to_pfn(*spte); |
753 | kvm_set_pfn_dirty(pfn); | |
855149aa IE |
754 | } |
755 | ||
05da4558 | 756 | /* check for huge page mappings */ |
44ad9944 JR |
757 | for (i = PT_DIRECTORY_LEVEL; |
758 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
759 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
760 | spte = rmap_next(kvm, rmapp, NULL); | |
761 | while (spte) { | |
762 | BUG_ON(!spte); | |
763 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
764 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
765 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 766 | if (is_writable_pte(*spte)) { |
be38d276 AK |
767 | drop_spte(kvm, spte, |
768 | shadow_trap_nonpresent_pte); | |
44ad9944 | 769 | --kvm->stat.lpages; |
44ad9944 JR |
770 | spte = NULL; |
771 | write_protected = 1; | |
772 | } | |
773 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 774 | } |
05da4558 MT |
775 | } |
776 | ||
b1a36821 | 777 | return write_protected; |
374cbac0 AK |
778 | } |
779 | ||
8a8365c5 FD |
780 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
781 | unsigned long data) | |
e930bffe AA |
782 | { |
783 | u64 *spte; | |
784 | int need_tlb_flush = 0; | |
785 | ||
786 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
787 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
788 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 789 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
790 | need_tlb_flush = 1; |
791 | } | |
792 | return need_tlb_flush; | |
793 | } | |
794 | ||
8a8365c5 FD |
795 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
796 | unsigned long data) | |
3da0dd43 IE |
797 | { |
798 | int need_flush = 0; | |
e4b502ea | 799 | u64 *spte, new_spte; |
3da0dd43 IE |
800 | pte_t *ptep = (pte_t *)data; |
801 | pfn_t new_pfn; | |
802 | ||
803 | WARN_ON(pte_huge(*ptep)); | |
804 | new_pfn = pte_pfn(*ptep); | |
805 | spte = rmap_next(kvm, rmapp, NULL); | |
806 | while (spte) { | |
807 | BUG_ON(!is_shadow_present_pte(*spte)); | |
808 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
809 | need_flush = 1; | |
810 | if (pte_write(*ptep)) { | |
be38d276 | 811 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
812 | spte = rmap_next(kvm, rmapp, NULL); |
813 | } else { | |
814 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
815 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
816 | ||
817 | new_spte &= ~PT_WRITABLE_MASK; | |
818 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 819 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 820 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
821 | spte = rmap_next(kvm, rmapp, spte); |
822 | } | |
823 | } | |
824 | if (need_flush) | |
825 | kvm_flush_remote_tlbs(kvm); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
8a8365c5 FD |
830 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
831 | unsigned long data, | |
3da0dd43 | 832 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 833 | unsigned long data)) |
e930bffe | 834 | { |
852e3c19 | 835 | int i, j; |
90bb6fc5 | 836 | int ret; |
e930bffe | 837 | int retval = 0; |
bc6678a3 MT |
838 | struct kvm_memslots *slots; |
839 | ||
90d83dc3 | 840 | slots = kvm_memslots(kvm); |
e930bffe | 841 | |
46a26bf5 MT |
842 | for (i = 0; i < slots->nmemslots; i++) { |
843 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
844 | unsigned long start = memslot->userspace_addr; |
845 | unsigned long end; | |
846 | ||
e930bffe AA |
847 | end = start + (memslot->npages << PAGE_SHIFT); |
848 | if (hva >= start && hva < end) { | |
849 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 850 | |
90bb6fc5 | 851 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
852 | |
853 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
6e3e243c AA |
854 | unsigned long idx; |
855 | int sh; | |
856 | ||
857 | sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j); | |
858 | idx = ((memslot->base_gfn+gfn_offset) >> sh) - | |
859 | (memslot->base_gfn >> sh); | |
90bb6fc5 | 860 | ret |= handler(kvm, |
3da0dd43 IE |
861 | &memslot->lpage_info[j][idx].rmap_pde, |
862 | data); | |
852e3c19 | 863 | } |
90bb6fc5 AK |
864 | trace_kvm_age_page(hva, memslot, ret); |
865 | retval |= ret; | |
e930bffe AA |
866 | } |
867 | } | |
868 | ||
869 | return retval; | |
870 | } | |
871 | ||
872 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
873 | { | |
3da0dd43 IE |
874 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
875 | } | |
876 | ||
877 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
878 | { | |
8a8365c5 | 879 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
880 | } |
881 | ||
8a8365c5 FD |
882 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
883 | unsigned long data) | |
e930bffe AA |
884 | { |
885 | u64 *spte; | |
886 | int young = 0; | |
887 | ||
6316e1c8 RR |
888 | /* |
889 | * Emulate the accessed bit for EPT, by checking if this page has | |
890 | * an EPT mapping, and clearing it if it does. On the next access, | |
891 | * a new EPT mapping will be established. | |
892 | * This has some overhead, but not as much as the cost of swapping | |
893 | * out actively used pages or breaking up actively used hugepages. | |
894 | */ | |
534e38b4 | 895 | if (!shadow_accessed_mask) |
6316e1c8 | 896 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 897 | |
e930bffe AA |
898 | spte = rmap_next(kvm, rmapp, NULL); |
899 | while (spte) { | |
900 | int _young; | |
901 | u64 _spte = *spte; | |
902 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
903 | _young = _spte & PT_ACCESSED_MASK; | |
904 | if (_young) { | |
905 | young = 1; | |
906 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
907 | } | |
908 | spte = rmap_next(kvm, rmapp, spte); | |
909 | } | |
910 | return young; | |
911 | } | |
912 | ||
53a27b39 MT |
913 | #define RMAP_RECYCLE_THRESHOLD 1000 |
914 | ||
852e3c19 | 915 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
916 | { |
917 | unsigned long *rmapp; | |
852e3c19 JR |
918 | struct kvm_mmu_page *sp; |
919 | ||
920 | sp = page_header(__pa(spte)); | |
53a27b39 | 921 | |
852e3c19 | 922 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 923 | |
3da0dd43 | 924 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
925 | kvm_flush_remote_tlbs(vcpu->kvm); |
926 | } | |
927 | ||
e930bffe AA |
928 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
929 | { | |
3da0dd43 | 930 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
931 | } |
932 | ||
d6c69ee9 | 933 | #ifdef MMU_DEBUG |
47ad8e68 | 934 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 935 | { |
139bdb2d AK |
936 | u64 *pos; |
937 | u64 *end; | |
938 | ||
47ad8e68 | 939 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 940 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 941 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 942 | pos, *pos); |
6aa8b732 | 943 | return 0; |
139bdb2d | 944 | } |
6aa8b732 AK |
945 | return 1; |
946 | } | |
d6c69ee9 | 947 | #endif |
6aa8b732 | 948 | |
4db35314 | 949 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 950 | { |
4db35314 | 951 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 952 | hlist_del(&sp->hash_link); |
4db35314 AK |
953 | list_del(&sp->link); |
954 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
955 | if (!sp->role.direct) |
956 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 957 | kmem_cache_free(mmu_page_header_cache, sp); |
f05e70ac | 958 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
959 | } |
960 | ||
cea0f0e7 AK |
961 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
962 | { | |
1ae0a13d | 963 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
964 | } |
965 | ||
25c0de2c | 966 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 967 | u64 *parent_pte, int direct) |
6aa8b732 | 968 | { |
4db35314 | 969 | struct kvm_mmu_page *sp; |
6aa8b732 | 970 | |
ad312c7c ZX |
971 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
972 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
973 | if (!direct) |
974 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
975 | PAGE_SIZE); | |
4db35314 | 976 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 977 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 978 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
979 | sp->multimapped = 0; |
980 | sp->parent_pte = parent_pte; | |
f05e70ac | 981 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 982 | return sp; |
6aa8b732 AK |
983 | } |
984 | ||
714b93da | 985 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 986 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
987 | { |
988 | struct kvm_pte_chain *pte_chain; | |
989 | struct hlist_node *node; | |
990 | int i; | |
991 | ||
992 | if (!parent_pte) | |
993 | return; | |
4db35314 AK |
994 | if (!sp->multimapped) { |
995 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
996 | |
997 | if (!old) { | |
4db35314 | 998 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
999 | return; |
1000 | } | |
4db35314 | 1001 | sp->multimapped = 1; |
714b93da | 1002 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1003 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1004 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1005 | pte_chain->parent_ptes[0] = old; |
1006 | } | |
4db35314 | 1007 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1008 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1009 | continue; | |
1010 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1011 | if (!pte_chain->parent_ptes[i]) { | |
1012 | pte_chain->parent_ptes[i] = parent_pte; | |
1013 | return; | |
1014 | } | |
1015 | } | |
714b93da | 1016 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1017 | BUG_ON(!pte_chain); |
4db35314 | 1018 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1019 | pte_chain->parent_ptes[0] = parent_pte; |
1020 | } | |
1021 | ||
4db35314 | 1022 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1023 | u64 *parent_pte) |
1024 | { | |
1025 | struct kvm_pte_chain *pte_chain; | |
1026 | struct hlist_node *node; | |
1027 | int i; | |
1028 | ||
4db35314 AK |
1029 | if (!sp->multimapped) { |
1030 | BUG_ON(sp->parent_pte != parent_pte); | |
1031 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1032 | return; |
1033 | } | |
4db35314 | 1034 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1035 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1036 | if (!pte_chain->parent_ptes[i]) | |
1037 | break; | |
1038 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1039 | continue; | |
697fe2e2 AK |
1040 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1041 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1042 | pte_chain->parent_ptes[i] |
1043 | = pte_chain->parent_ptes[i + 1]; | |
1044 | ++i; | |
1045 | } | |
1046 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1047 | if (i == 0) { |
1048 | hlist_del(&pte_chain->link); | |
90cb0529 | 1049 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1050 | if (hlist_empty(&sp->parent_ptes)) { |
1051 | sp->multimapped = 0; | |
1052 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1053 | } |
1054 | } | |
cea0f0e7 AK |
1055 | return; |
1056 | } | |
1057 | BUG(); | |
1058 | } | |
1059 | ||
6b18493d | 1060 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1061 | { |
1062 | struct kvm_pte_chain *pte_chain; | |
1063 | struct hlist_node *node; | |
1064 | struct kvm_mmu_page *parent_sp; | |
1065 | int i; | |
1066 | ||
1067 | if (!sp->multimapped && sp->parent_pte) { | |
1068 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1069 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1070 | return; |
1071 | } | |
1047df1f | 1072 | |
ad8cfbe3 MT |
1073 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1074 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1075 | u64 *spte = pte_chain->parent_ptes[i]; |
1076 | ||
1077 | if (!spte) | |
ad8cfbe3 | 1078 | break; |
1047df1f XG |
1079 | parent_sp = page_header(__pa(spte)); |
1080 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1081 | } |
1082 | } | |
1083 | ||
1047df1f XG |
1084 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1085 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1086 | { |
1047df1f | 1087 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1088 | } |
1089 | ||
1047df1f | 1090 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1091 | { |
1047df1f | 1092 | unsigned int index; |
0074ff63 | 1093 | |
1047df1f XG |
1094 | index = spte - sp->spt; |
1095 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1096 | return; |
1047df1f | 1097 | if (sp->unsync_children++) |
0074ff63 | 1098 | return; |
1047df1f | 1099 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1100 | } |
1101 | ||
d761a501 AK |
1102 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1103 | struct kvm_mmu_page *sp) | |
1104 | { | |
1105 | int i; | |
1106 | ||
1107 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1108 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1109 | } | |
1110 | ||
e8bc217a | 1111 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1112 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1113 | { |
1114 | return 1; | |
1115 | } | |
1116 | ||
a7052897 MT |
1117 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1118 | { | |
1119 | } | |
1120 | ||
60c8aec6 MT |
1121 | #define KVM_PAGE_ARRAY_NR 16 |
1122 | ||
1123 | struct kvm_mmu_pages { | |
1124 | struct mmu_page_and_offset { | |
1125 | struct kvm_mmu_page *sp; | |
1126 | unsigned int idx; | |
1127 | } page[KVM_PAGE_ARRAY_NR]; | |
1128 | unsigned int nr; | |
1129 | }; | |
1130 | ||
0074ff63 MT |
1131 | #define for_each_unsync_children(bitmap, idx) \ |
1132 | for (idx = find_first_bit(bitmap, 512); \ | |
1133 | idx < 512; \ | |
1134 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1135 | ||
cded19f3 HE |
1136 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1137 | int idx) | |
4731d4c7 | 1138 | { |
60c8aec6 | 1139 | int i; |
4731d4c7 | 1140 | |
60c8aec6 MT |
1141 | if (sp->unsync) |
1142 | for (i=0; i < pvec->nr; i++) | |
1143 | if (pvec->page[i].sp == sp) | |
1144 | return 0; | |
1145 | ||
1146 | pvec->page[pvec->nr].sp = sp; | |
1147 | pvec->page[pvec->nr].idx = idx; | |
1148 | pvec->nr++; | |
1149 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1150 | } | |
1151 | ||
1152 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1153 | struct kvm_mmu_pages *pvec) | |
1154 | { | |
1155 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1156 | |
0074ff63 | 1157 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1158 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1159 | u64 ent = sp->spt[i]; |
1160 | ||
7a8f1a74 XG |
1161 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1162 | goto clear_child_bitmap; | |
1163 | ||
1164 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1165 | ||
1166 | if (child->unsync_children) { | |
1167 | if (mmu_pages_add(pvec, child, i)) | |
1168 | return -ENOSPC; | |
1169 | ||
1170 | ret = __mmu_unsync_walk(child, pvec); | |
1171 | if (!ret) | |
1172 | goto clear_child_bitmap; | |
1173 | else if (ret > 0) | |
1174 | nr_unsync_leaf += ret; | |
1175 | else | |
1176 | return ret; | |
1177 | } else if (child->unsync) { | |
1178 | nr_unsync_leaf++; | |
1179 | if (mmu_pages_add(pvec, child, i)) | |
1180 | return -ENOSPC; | |
1181 | } else | |
1182 | goto clear_child_bitmap; | |
1183 | ||
1184 | continue; | |
1185 | ||
1186 | clear_child_bitmap: | |
1187 | __clear_bit(i, sp->unsync_child_bitmap); | |
1188 | sp->unsync_children--; | |
1189 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1190 | } |
1191 | ||
4731d4c7 | 1192 | |
60c8aec6 MT |
1193 | return nr_unsync_leaf; |
1194 | } | |
1195 | ||
1196 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1197 | struct kvm_mmu_pages *pvec) | |
1198 | { | |
1199 | if (!sp->unsync_children) | |
1200 | return 0; | |
1201 | ||
1202 | mmu_pages_add(pvec, sp, 0); | |
1203 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1204 | } |
1205 | ||
4731d4c7 MT |
1206 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1207 | { | |
1208 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1209 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1210 | sp->unsync = 0; |
1211 | --kvm->stat.mmu_unsync; | |
1212 | } | |
1213 | ||
7775834a XG |
1214 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1215 | struct list_head *invalid_list); | |
1216 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1217 | struct list_head *invalid_list); | |
4731d4c7 | 1218 | |
f41d335a XG |
1219 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1220 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1221 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1222 | if ((sp)->gfn != (gfn)) {} else | |
1223 | ||
f41d335a XG |
1224 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1225 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1226 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1227 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1228 | (sp)->role.invalid) {} else | |
1229 | ||
f918b443 | 1230 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1231 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1232 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1233 | { |
5b7e0102 | 1234 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1235 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1236 | return 1; |
1237 | } | |
1238 | ||
f918b443 | 1239 | if (clear_unsync) |
1d9dc7e0 | 1240 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1241 | |
be71e061 | 1242 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1243 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1244 | return 1; |
1245 | } | |
1246 | ||
1247 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1248 | return 0; |
1249 | } | |
1250 | ||
1d9dc7e0 XG |
1251 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1252 | struct kvm_mmu_page *sp) | |
1253 | { | |
d98ba053 | 1254 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1255 | int ret; |
1256 | ||
d98ba053 | 1257 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1258 | if (ret) |
d98ba053 XG |
1259 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1260 | ||
1d9dc7e0 XG |
1261 | return ret; |
1262 | } | |
1263 | ||
d98ba053 XG |
1264 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1265 | struct list_head *invalid_list) | |
1d9dc7e0 | 1266 | { |
d98ba053 | 1267 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1268 | } |
1269 | ||
9f1a122f XG |
1270 | /* @gfn should be write-protected at the call site */ |
1271 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1272 | { | |
9f1a122f | 1273 | struct kvm_mmu_page *s; |
f41d335a | 1274 | struct hlist_node *node; |
d98ba053 | 1275 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1276 | bool flush = false; |
1277 | ||
f41d335a | 1278 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1279 | if (!s->unsync) |
9f1a122f XG |
1280 | continue; |
1281 | ||
1282 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1283 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1284 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1285 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1286 | continue; |
1287 | } | |
1288 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1289 | flush = true; | |
1290 | } | |
1291 | ||
d98ba053 | 1292 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1293 | if (flush) |
1294 | kvm_mmu_flush_tlb(vcpu); | |
1295 | } | |
1296 | ||
60c8aec6 MT |
1297 | struct mmu_page_path { |
1298 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1299 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1300 | }; |
1301 | ||
60c8aec6 MT |
1302 | #define for_each_sp(pvec, sp, parents, i) \ |
1303 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1304 | sp = pvec.page[i].sp; \ | |
1305 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1306 | i = mmu_pages_next(&pvec, &parents, i)) | |
1307 | ||
cded19f3 HE |
1308 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1309 | struct mmu_page_path *parents, | |
1310 | int i) | |
60c8aec6 MT |
1311 | { |
1312 | int n; | |
1313 | ||
1314 | for (n = i+1; n < pvec->nr; n++) { | |
1315 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1316 | ||
1317 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1318 | parents->idx[0] = pvec->page[n].idx; | |
1319 | return n; | |
1320 | } | |
1321 | ||
1322 | parents->parent[sp->role.level-2] = sp; | |
1323 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1324 | } | |
1325 | ||
1326 | return n; | |
1327 | } | |
1328 | ||
cded19f3 | 1329 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1330 | { |
60c8aec6 MT |
1331 | struct kvm_mmu_page *sp; |
1332 | unsigned int level = 0; | |
1333 | ||
1334 | do { | |
1335 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1336 | |
60c8aec6 MT |
1337 | sp = parents->parent[level]; |
1338 | if (!sp) | |
1339 | return; | |
1340 | ||
1341 | --sp->unsync_children; | |
1342 | WARN_ON((int)sp->unsync_children < 0); | |
1343 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1344 | level++; | |
1345 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1346 | } |
1347 | ||
60c8aec6 MT |
1348 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1349 | struct mmu_page_path *parents, | |
1350 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1351 | { |
60c8aec6 MT |
1352 | parents->parent[parent->role.level-1] = NULL; |
1353 | pvec->nr = 0; | |
1354 | } | |
4731d4c7 | 1355 | |
60c8aec6 MT |
1356 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1357 | struct kvm_mmu_page *parent) | |
1358 | { | |
1359 | int i; | |
1360 | struct kvm_mmu_page *sp; | |
1361 | struct mmu_page_path parents; | |
1362 | struct kvm_mmu_pages pages; | |
d98ba053 | 1363 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1364 | |
1365 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1366 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1367 | int protected = 0; |
1368 | ||
1369 | for_each_sp(pages, sp, parents, i) | |
1370 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1371 | ||
1372 | if (protected) | |
1373 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1374 | ||
60c8aec6 | 1375 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1376 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1377 | mmu_pages_clear_parents(&parents); |
1378 | } | |
d98ba053 | 1379 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1380 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1381 | kvm_mmu_pages_init(parent, &parents, &pages); |
1382 | } | |
4731d4c7 MT |
1383 | } |
1384 | ||
cea0f0e7 AK |
1385 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1386 | gfn_t gfn, | |
1387 | gva_t gaddr, | |
1388 | unsigned level, | |
f6e2c02b | 1389 | int direct, |
41074d07 | 1390 | unsigned access, |
f7d9c7b7 | 1391 | u64 *parent_pte) |
cea0f0e7 AK |
1392 | { |
1393 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1394 | unsigned quadrant; |
9f1a122f | 1395 | struct kvm_mmu_page *sp; |
f41d335a | 1396 | struct hlist_node *node; |
9f1a122f | 1397 | bool need_sync = false; |
cea0f0e7 | 1398 | |
a770f6f2 | 1399 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1400 | role.level = level; |
f6e2c02b | 1401 | role.direct = direct; |
84b0c8c6 | 1402 | if (role.direct) |
5b7e0102 | 1403 | role.cr4_pae = 0; |
41074d07 | 1404 | role.access = access; |
b66d8000 | 1405 | if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1406 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1407 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1408 | role.quadrant = quadrant; | |
1409 | } | |
f41d335a | 1410 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1411 | if (!need_sync && sp->unsync) |
1412 | need_sync = true; | |
4731d4c7 | 1413 | |
7ae680eb XG |
1414 | if (sp->role.word != role.word) |
1415 | continue; | |
4731d4c7 | 1416 | |
7ae680eb XG |
1417 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1418 | break; | |
e02aa901 | 1419 | |
7ae680eb XG |
1420 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1421 | if (sp->unsync_children) { | |
a8eeb04a | 1422 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1423 | kvm_mmu_mark_parents_unsync(sp); |
1424 | } else if (sp->unsync) | |
1425 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1426 | |
7ae680eb XG |
1427 | trace_kvm_mmu_get_page(sp, false); |
1428 | return sp; | |
1429 | } | |
dfc5aa00 | 1430 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1431 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1432 | if (!sp) |
1433 | return sp; | |
4db35314 AK |
1434 | sp->gfn = gfn; |
1435 | sp->role = role; | |
7ae680eb XG |
1436 | hlist_add_head(&sp->hash_link, |
1437 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1438 | if (!direct) { |
b1a36821 MT |
1439 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1440 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1441 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1442 | kvm_sync_pages(vcpu, gfn); | |
1443 | ||
4731d4c7 MT |
1444 | account_shadowed(vcpu->kvm, gfn); |
1445 | } | |
131d8279 AK |
1446 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1447 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1448 | else | |
1449 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1450 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1451 | return sp; |
cea0f0e7 AK |
1452 | } |
1453 | ||
2d11123a AK |
1454 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1455 | struct kvm_vcpu *vcpu, u64 addr) | |
1456 | { | |
1457 | iterator->addr = addr; | |
1458 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1459 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1460 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1461 | iterator->shadow_addr | |
1462 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1463 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1464 | --iterator->level; | |
1465 | if (!iterator->shadow_addr) | |
1466 | iterator->level = 0; | |
1467 | } | |
1468 | } | |
1469 | ||
1470 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1471 | { | |
1472 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1473 | return false; | |
4d88954d MT |
1474 | |
1475 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1476 | if (is_large_pte(*iterator->sptep)) | |
1477 | return false; | |
1478 | ||
2d11123a AK |
1479 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1480 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1481 | return true; | |
1482 | } | |
1483 | ||
1484 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1485 | { | |
1486 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1487 | --iterator->level; | |
1488 | } | |
1489 | ||
32ef26a3 AK |
1490 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1491 | { | |
1492 | u64 spte; | |
1493 | ||
1494 | spte = __pa(sp->spt) | |
1495 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1496 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1497 | __set_spte(sptep, spte); |
32ef26a3 AK |
1498 | } |
1499 | ||
a3aa51cf AK |
1500 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1501 | { | |
1502 | if (is_large_pte(*sptep)) { | |
1503 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1504 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1505 | } | |
1506 | } | |
1507 | ||
a357bd22 AK |
1508 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1509 | unsigned direct_access) | |
1510 | { | |
1511 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1512 | struct kvm_mmu_page *child; | |
1513 | ||
1514 | /* | |
1515 | * For the direct sp, if the guest pte's dirty bit | |
1516 | * changed form clean to dirty, it will corrupt the | |
1517 | * sp's access: allow writable in the read-only sp, | |
1518 | * so we should update the spte at this point to get | |
1519 | * a new sp with the correct access. | |
1520 | */ | |
1521 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1522 | if (child->role.access == direct_access) | |
1523 | return; | |
1524 | ||
1525 | mmu_page_remove_parent_pte(child, sptep); | |
1526 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1527 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1528 | } | |
1529 | } | |
1530 | ||
90cb0529 | 1531 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1532 | struct kvm_mmu_page *sp) |
a436036b | 1533 | { |
697fe2e2 AK |
1534 | unsigned i; |
1535 | u64 *pt; | |
1536 | u64 ent; | |
1537 | ||
4db35314 | 1538 | pt = sp->spt; |
697fe2e2 | 1539 | |
697fe2e2 AK |
1540 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1541 | ent = pt[i]; | |
1542 | ||
05da4558 | 1543 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1544 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1545 | ent &= PT64_BASE_ADDR_MASK; |
1546 | mmu_page_remove_parent_pte(page_header(ent), | |
1547 | &pt[i]); | |
1548 | } else { | |
776e6633 MT |
1549 | if (is_large_pte(ent)) |
1550 | --kvm->stat.lpages; | |
be38d276 AK |
1551 | drop_spte(kvm, &pt[i], |
1552 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1553 | } |
1554 | } | |
c7addb90 | 1555 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1556 | } |
a436036b AK |
1557 | } |
1558 | ||
4db35314 | 1559 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1560 | { |
4db35314 | 1561 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1562 | } |
1563 | ||
12b7d28f AK |
1564 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1565 | { | |
1566 | int i; | |
988a2cae | 1567 | struct kvm_vcpu *vcpu; |
12b7d28f | 1568 | |
988a2cae GN |
1569 | kvm_for_each_vcpu(i, vcpu, kvm) |
1570 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1571 | } |
1572 | ||
31aa2b44 | 1573 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1574 | { |
1575 | u64 *parent_pte; | |
1576 | ||
4db35314 AK |
1577 | while (sp->multimapped || sp->parent_pte) { |
1578 | if (!sp->multimapped) | |
1579 | parent_pte = sp->parent_pte; | |
a436036b AK |
1580 | else { |
1581 | struct kvm_pte_chain *chain; | |
1582 | ||
4db35314 | 1583 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1584 | struct kvm_pte_chain, link); |
1585 | parent_pte = chain->parent_ptes[0]; | |
1586 | } | |
697fe2e2 | 1587 | BUG_ON(!parent_pte); |
4db35314 | 1588 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1589 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1590 | } |
31aa2b44 AK |
1591 | } |
1592 | ||
60c8aec6 | 1593 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1594 | struct kvm_mmu_page *parent, |
1595 | struct list_head *invalid_list) | |
4731d4c7 | 1596 | { |
60c8aec6 MT |
1597 | int i, zapped = 0; |
1598 | struct mmu_page_path parents; | |
1599 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1600 | |
60c8aec6 | 1601 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1602 | return 0; |
60c8aec6 MT |
1603 | |
1604 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1605 | while (mmu_unsync_walk(parent, &pages)) { | |
1606 | struct kvm_mmu_page *sp; | |
1607 | ||
1608 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1609 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1610 | mmu_pages_clear_parents(&parents); |
77662e00 | 1611 | zapped++; |
60c8aec6 | 1612 | } |
60c8aec6 MT |
1613 | kvm_mmu_pages_init(parent, &parents, &pages); |
1614 | } | |
1615 | ||
1616 | return zapped; | |
4731d4c7 MT |
1617 | } |
1618 | ||
7775834a XG |
1619 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1620 | struct list_head *invalid_list) | |
31aa2b44 | 1621 | { |
4731d4c7 | 1622 | int ret; |
f691fe1d | 1623 | |
7775834a | 1624 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1625 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1626 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1627 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1628 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1629 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1630 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1631 | if (sp->unsync) |
1632 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1633 | if (!sp->root_count) { |
54a4f023 GJ |
1634 | /* Count self */ |
1635 | ret++; | |
7775834a | 1636 | list_move(&sp->link, invalid_list); |
2e53d63a | 1637 | } else { |
5b5c6a5a | 1638 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1639 | kvm_reload_remote_mmus(kvm); |
1640 | } | |
7775834a XG |
1641 | |
1642 | sp->role.invalid = 1; | |
12b7d28f | 1643 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1644 | return ret; |
a436036b AK |
1645 | } |
1646 | ||
7775834a XG |
1647 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1648 | struct list_head *invalid_list) | |
1649 | { | |
1650 | struct kvm_mmu_page *sp; | |
1651 | ||
1652 | if (list_empty(invalid_list)) | |
1653 | return; | |
1654 | ||
1655 | kvm_flush_remote_tlbs(kvm); | |
1656 | ||
1657 | do { | |
1658 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1659 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1660 | kvm_mmu_free_page(kvm, sp); | |
1661 | } while (!list_empty(invalid_list)); | |
1662 | ||
1663 | } | |
1664 | ||
82ce2c96 IE |
1665 | /* |
1666 | * Changing the number of mmu pages allocated to the vm | |
1667 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
1668 | */ | |
1669 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
1670 | { | |
025dbbf3 | 1671 | int used_pages; |
d98ba053 | 1672 | LIST_HEAD(invalid_list); |
025dbbf3 MT |
1673 | |
1674 | used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages; | |
1675 | used_pages = max(0, used_pages); | |
1676 | ||
82ce2c96 IE |
1677 | /* |
1678 | * If we set the number of mmu pages to be smaller be than the | |
1679 | * number of actived pages , we must to free some mmu pages before we | |
1680 | * change the value | |
1681 | */ | |
1682 | ||
025dbbf3 | 1683 | if (used_pages > kvm_nr_mmu_pages) { |
77662e00 XG |
1684 | while (used_pages > kvm_nr_mmu_pages && |
1685 | !list_empty(&kvm->arch.active_mmu_pages)) { | |
82ce2c96 IE |
1686 | struct kvm_mmu_page *page; |
1687 | ||
f05e70ac | 1688 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1689 | struct kvm_mmu_page, link); |
d98ba053 XG |
1690 | used_pages -= kvm_mmu_prepare_zap_page(kvm, page, |
1691 | &invalid_list); | |
82ce2c96 | 1692 | } |
d98ba053 | 1693 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
77662e00 | 1694 | kvm_nr_mmu_pages = used_pages; |
f05e70ac | 1695 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
1696 | } |
1697 | else | |
f05e70ac ZX |
1698 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
1699 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 1700 | |
f05e70ac | 1701 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
1702 | } |
1703 | ||
f67a46f4 | 1704 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1705 | { |
4db35314 | 1706 | struct kvm_mmu_page *sp; |
f41d335a | 1707 | struct hlist_node *node; |
d98ba053 | 1708 | LIST_HEAD(invalid_list); |
a436036b AK |
1709 | int r; |
1710 | ||
b8688d51 | 1711 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1712 | r = 0; |
f41d335a XG |
1713 | |
1714 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
7ae680eb XG |
1715 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
1716 | sp->role.word); | |
1717 | r = 1; | |
f41d335a | 1718 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1719 | } |
d98ba053 | 1720 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1721 | return r; |
cea0f0e7 AK |
1722 | } |
1723 | ||
f67a46f4 | 1724 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1725 | { |
4db35314 | 1726 | struct kvm_mmu_page *sp; |
f41d335a | 1727 | struct hlist_node *node; |
d98ba053 | 1728 | LIST_HEAD(invalid_list); |
97a0a01e | 1729 | |
f41d335a | 1730 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
7ae680eb XG |
1731 | pgprintk("%s: zap %lx %x\n", |
1732 | __func__, gfn, sp->role.word); | |
f41d335a | 1733 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1734 | } |
d98ba053 | 1735 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1736 | } |
1737 | ||
38c335f1 | 1738 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1739 | { |
bc6678a3 | 1740 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1741 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1742 | |
291f26bc | 1743 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1744 | } |
1745 | ||
6844dec6 MT |
1746 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1747 | { | |
1748 | int i; | |
1749 | u64 *pt = sp->spt; | |
1750 | ||
1751 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1752 | return; | |
1753 | ||
1754 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1755 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1756 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1757 | } |
1758 | } | |
1759 | ||
74be52e3 SY |
1760 | /* |
1761 | * The function is based on mtrr_type_lookup() in | |
1762 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1763 | */ | |
1764 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1765 | u64 start, u64 end) | |
1766 | { | |
1767 | int i; | |
1768 | u64 base, mask; | |
1769 | u8 prev_match, curr_match; | |
1770 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1771 | ||
1772 | if (!mtrr_state->enabled) | |
1773 | return 0xFF; | |
1774 | ||
1775 | /* Make end inclusive end, instead of exclusive */ | |
1776 | end--; | |
1777 | ||
1778 | /* Look in fixed ranges. Just return the type as per start */ | |
1779 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1780 | int idx; | |
1781 | ||
1782 | if (start < 0x80000) { | |
1783 | idx = 0; | |
1784 | idx += (start >> 16); | |
1785 | return mtrr_state->fixed_ranges[idx]; | |
1786 | } else if (start < 0xC0000) { | |
1787 | idx = 1 * 8; | |
1788 | idx += ((start - 0x80000) >> 14); | |
1789 | return mtrr_state->fixed_ranges[idx]; | |
1790 | } else if (start < 0x1000000) { | |
1791 | idx = 3 * 8; | |
1792 | idx += ((start - 0xC0000) >> 12); | |
1793 | return mtrr_state->fixed_ranges[idx]; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | /* | |
1798 | * Look in variable ranges | |
1799 | * Look of multiple ranges matching this address and pick type | |
1800 | * as per MTRR precedence | |
1801 | */ | |
1802 | if (!(mtrr_state->enabled & 2)) | |
1803 | return mtrr_state->def_type; | |
1804 | ||
1805 | prev_match = 0xFF; | |
1806 | for (i = 0; i < num_var_ranges; ++i) { | |
1807 | unsigned short start_state, end_state; | |
1808 | ||
1809 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1810 | continue; | |
1811 | ||
1812 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1813 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1814 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1815 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1816 | ||
1817 | start_state = ((start & mask) == (base & mask)); | |
1818 | end_state = ((end & mask) == (base & mask)); | |
1819 | if (start_state != end_state) | |
1820 | return 0xFE; | |
1821 | ||
1822 | if ((start & mask) != (base & mask)) | |
1823 | continue; | |
1824 | ||
1825 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1826 | if (prev_match == 0xFF) { | |
1827 | prev_match = curr_match; | |
1828 | continue; | |
1829 | } | |
1830 | ||
1831 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1832 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1833 | return MTRR_TYPE_UNCACHABLE; | |
1834 | ||
1835 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1836 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1837 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1838 | curr_match == MTRR_TYPE_WRBACK)) { | |
1839 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1840 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1841 | } | |
1842 | ||
1843 | if (prev_match != curr_match) | |
1844 | return MTRR_TYPE_UNCACHABLE; | |
1845 | } | |
1846 | ||
1847 | if (prev_match != 0xFF) | |
1848 | return prev_match; | |
1849 | ||
1850 | return mtrr_state->def_type; | |
1851 | } | |
1852 | ||
4b12f0de | 1853 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1854 | { |
1855 | u8 mtrr; | |
1856 | ||
1857 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1858 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1859 | if (mtrr == 0xfe || mtrr == 0xff) | |
1860 | mtrr = MTRR_TYPE_WRBACK; | |
1861 | return mtrr; | |
1862 | } | |
4b12f0de | 1863 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1864 | |
9cf5cf5a XG |
1865 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1866 | { | |
1867 | trace_kvm_mmu_unsync_page(sp); | |
1868 | ++vcpu->kvm->stat.mmu_unsync; | |
1869 | sp->unsync = 1; | |
1870 | ||
1871 | kvm_mmu_mark_parents_unsync(sp); | |
1872 | mmu_convert_notrap(sp); | |
1873 | } | |
1874 | ||
1875 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1876 | { |
4731d4c7 | 1877 | struct kvm_mmu_page *s; |
f41d335a | 1878 | struct hlist_node *node; |
9cf5cf5a | 1879 | |
f41d335a | 1880 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1881 | if (s->unsync) |
4731d4c7 | 1882 | continue; |
9cf5cf5a XG |
1883 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1884 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1885 | } |
4731d4c7 MT |
1886 | } |
1887 | ||
1888 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1889 | bool can_unsync) | |
1890 | { | |
9cf5cf5a | 1891 | struct kvm_mmu_page *s; |
f41d335a | 1892 | struct hlist_node *node; |
9cf5cf5a XG |
1893 | bool need_unsync = false; |
1894 | ||
f41d335a | 1895 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1896 | if (!can_unsync) |
1897 | return 1; | |
1898 | ||
9cf5cf5a | 1899 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1900 | return 1; |
9cf5cf5a XG |
1901 | |
1902 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1903 | if (!oos_shadow) |
9cf5cf5a XG |
1904 | return 1; |
1905 | need_unsync = true; | |
1906 | } | |
4731d4c7 | 1907 | } |
9cf5cf5a XG |
1908 | if (need_unsync) |
1909 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1910 | return 0; |
1911 | } | |
1912 | ||
d555c333 | 1913 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1914 | unsigned pte_access, int user_fault, |
852e3c19 | 1915 | int write_fault, int dirty, int level, |
c2d0ee46 | 1916 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1917 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1918 | { |
1919 | u64 spte; | |
1e73f9dd | 1920 | int ret = 0; |
64d4d521 | 1921 | |
1c4f1fd6 AK |
1922 | /* |
1923 | * We don't set the accessed bit, since we sometimes want to see | |
1924 | * whether the guest actually used the pte (in order to detect | |
1925 | * demand paging). | |
1926 | */ | |
7b52345e | 1927 | spte = shadow_base_present_pte | shadow_dirty_mask; |
947da538 | 1928 | if (!speculative) |
3201b5d9 | 1929 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1930 | if (!dirty) |
1931 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1932 | if (pte_access & ACC_EXEC_MASK) |
1933 | spte |= shadow_x_mask; | |
1934 | else | |
1935 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1936 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1937 | spte |= shadow_user_mask; |
852e3c19 | 1938 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1939 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1940 | if (tdp_enabled) |
1941 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1942 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1943 | |
1403283a IE |
1944 | if (reset_host_protection) |
1945 | spte |= SPTE_HOST_WRITEABLE; | |
1946 | ||
35149e21 | 1947 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1948 | |
1949 | if ((pte_access & ACC_WRITE_MASK) | |
8184dd38 AK |
1950 | || (!tdp_enabled && write_fault && !is_write_protection(vcpu) |
1951 | && !user_fault)) { | |
1c4f1fd6 | 1952 | |
852e3c19 JR |
1953 | if (level > PT_PAGE_TABLE_LEVEL && |
1954 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1955 | ret = 1; |
be38d276 AK |
1956 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
1957 | goto done; | |
38187c83 MT |
1958 | } |
1959 | ||
1c4f1fd6 | 1960 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1961 | |
69325a12 AK |
1962 | if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK)) |
1963 | spte &= ~PT_USER_MASK; | |
1964 | ||
ecc5589f MT |
1965 | /* |
1966 | * Optimization: for pte sync, if spte was writable the hash | |
1967 | * lookup is unnecessary (and expensive). Write protection | |
1968 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1969 | * Same reasoning can be applied to dirty page accounting. | |
1970 | */ | |
8dae4445 | 1971 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
1972 | goto set_pte; |
1973 | ||
4731d4c7 | 1974 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 1975 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 1976 | __func__, gfn); |
1e73f9dd | 1977 | ret = 1; |
1c4f1fd6 | 1978 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 1979 | if (is_writable_pte(spte)) |
1c4f1fd6 | 1980 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
1981 | } |
1982 | } | |
1983 | ||
1c4f1fd6 AK |
1984 | if (pte_access & ACC_WRITE_MASK) |
1985 | mark_page_dirty(vcpu->kvm, gfn); | |
1986 | ||
38187c83 | 1987 | set_pte: |
9ed5520d XG |
1988 | if (is_writable_pte(*sptep) && !is_writable_pte(spte)) |
1989 | kvm_set_pfn_dirty(pfn); | |
b79b93f9 | 1990 | update_spte(sptep, spte); |
be38d276 | 1991 | done: |
1e73f9dd MT |
1992 | return ret; |
1993 | } | |
1994 | ||
d555c333 | 1995 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
1996 | unsigned pt_access, unsigned pte_access, |
1997 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 1998 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
1999 | pfn_t pfn, bool speculative, |
2000 | bool reset_host_protection) | |
1e73f9dd MT |
2001 | { |
2002 | int was_rmapped = 0; | |
53a27b39 | 2003 | int rmap_count; |
1e73f9dd MT |
2004 | |
2005 | pgprintk("%s: spte %llx access %x write_fault %d" | |
2006 | " user_fault %d gfn %lx\n", | |
d555c333 | 2007 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2008 | write_fault, user_fault, gfn); |
2009 | ||
d555c333 | 2010 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2011 | /* |
2012 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2013 | * the parent of the now unreachable PTE. | |
2014 | */ | |
852e3c19 JR |
2015 | if (level > PT_PAGE_TABLE_LEVEL && |
2016 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2017 | struct kvm_mmu_page *child; |
d555c333 | 2018 | u64 pte = *sptep; |
1e73f9dd MT |
2019 | |
2020 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2021 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2022 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2023 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2024 | } else if (pfn != spte_to_pfn(*sptep)) { |
1e73f9dd | 2025 | pgprintk("hfn old %lx new %lx\n", |
d555c333 | 2026 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2027 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2028 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2029 | } else |
2030 | was_rmapped = 1; | |
1e73f9dd | 2031 | } |
852e3c19 | 2032 | |
d555c333 | 2033 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
2034 | dirty, level, gfn, pfn, speculative, true, |
2035 | reset_host_protection)) { | |
1e73f9dd MT |
2036 | if (write_fault) |
2037 | *ptwrite = 1; | |
5304efde | 2038 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2039 | } |
1e73f9dd | 2040 | |
d555c333 | 2041 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 2042 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 2043 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2044 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2045 | *sptep, sptep); | |
d555c333 | 2046 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2047 | ++vcpu->kvm->stat.lpages; |
2048 | ||
d555c333 | 2049 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2050 | if (!was_rmapped) { |
44ad9944 | 2051 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2052 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2053 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2054 | } |
9ed5520d | 2055 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2056 | if (speculative) { |
d555c333 | 2057 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2058 | vcpu->arch.last_pte_gfn = gfn; |
2059 | } | |
1c4f1fd6 AK |
2060 | } |
2061 | ||
6aa8b732 AK |
2062 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2063 | { | |
2064 | } | |
2065 | ||
9f652d21 | 2066 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 2067 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 2068 | { |
9f652d21 | 2069 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2070 | struct kvm_mmu_page *sp; |
9f652d21 | 2071 | int pt_write = 0; |
140754bc | 2072 | gfn_t pseudo_gfn; |
6aa8b732 | 2073 | |
9f652d21 | 2074 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2075 | if (iterator.level == level) { |
9f652d21 AK |
2076 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
2077 | 0, write, 1, &pt_write, | |
1403283a | 2078 | level, gfn, pfn, false, true); |
9f652d21 AK |
2079 | ++vcpu->stat.pf_fixed; |
2080 | break; | |
6aa8b732 AK |
2081 | } |
2082 | ||
9f652d21 | 2083 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2084 | u64 base_addr = iterator.addr; |
2085 | ||
2086 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2087 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2088 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2089 | iterator.level - 1, | |
2090 | 1, ACC_ALL, iterator.sptep); | |
2091 | if (!sp) { | |
2092 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2093 | kvm_release_pfn_clean(pfn); | |
2094 | return -ENOMEM; | |
2095 | } | |
140754bc | 2096 | |
d555c333 AK |
2097 | __set_spte(iterator.sptep, |
2098 | __pa(sp->spt) | |
2099 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2100 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
2101 | } |
2102 | } | |
2103 | return pt_write; | |
6aa8b732 AK |
2104 | } |
2105 | ||
bf998156 HY |
2106 | static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn) |
2107 | { | |
2108 | char buf[1]; | |
2109 | void __user *hva; | |
2110 | int r; | |
2111 | ||
2112 | /* Touch the page, so send SIGBUS */ | |
2113 | hva = (void __user *)gfn_to_hva(kvm, gfn); | |
2114 | r = copy_from_user(buf, hva, 1); | |
2115 | } | |
2116 | ||
2117 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2118 | { | |
2119 | kvm_release_pfn_clean(pfn); | |
2120 | if (is_hwpoison_pfn(pfn)) { | |
2121 | kvm_send_hwpoison_signal(kvm, gfn); | |
2122 | return 0; | |
edba23e5 GN |
2123 | } else if (is_fault_pfn(pfn)) |
2124 | return -EFAULT; | |
2125 | ||
bf998156 HY |
2126 | return 1; |
2127 | } | |
2128 | ||
10589a46 MT |
2129 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2130 | { | |
2131 | int r; | |
852e3c19 | 2132 | int level; |
35149e21 | 2133 | pfn_t pfn; |
e930bffe | 2134 | unsigned long mmu_seq; |
aaee2c94 | 2135 | |
852e3c19 JR |
2136 | level = mapping_level(vcpu, gfn); |
2137 | ||
2138 | /* | |
2139 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2140 | * maximum. Therefore check if the level is larger than that. | |
2141 | */ | |
2142 | if (level > PT_DIRECTORY_LEVEL) | |
2143 | level = PT_DIRECTORY_LEVEL; | |
2144 | ||
2145 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2146 | |
e930bffe | 2147 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2148 | smp_rmb(); |
35149e21 | 2149 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2150 | |
d196e343 | 2151 | /* mmio */ |
bf998156 HY |
2152 | if (is_error_pfn(pfn)) |
2153 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2154 | |
aaee2c94 | 2155 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2156 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2157 | goto out_unlock; | |
eb787d10 | 2158 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2159 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2160 | spin_unlock(&vcpu->kvm->mmu_lock); |
2161 | ||
aaee2c94 | 2162 | |
10589a46 | 2163 | return r; |
e930bffe AA |
2164 | |
2165 | out_unlock: | |
2166 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2167 | kvm_release_pfn_clean(pfn); | |
2168 | return 0; | |
10589a46 MT |
2169 | } |
2170 | ||
2171 | ||
17ac10ad AK |
2172 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2173 | { | |
2174 | int i; | |
4db35314 | 2175 | struct kvm_mmu_page *sp; |
d98ba053 | 2176 | LIST_HEAD(invalid_list); |
17ac10ad | 2177 | |
ad312c7c | 2178 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2179 | return; |
aaee2c94 | 2180 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2181 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2182 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2183 | |
4db35314 AK |
2184 | sp = page_header(root); |
2185 | --sp->root_count; | |
d98ba053 XG |
2186 | if (!sp->root_count && sp->role.invalid) { |
2187 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2188 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2189 | } | |
ad312c7c | 2190 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2191 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2192 | return; |
2193 | } | |
17ac10ad | 2194 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2195 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2196 | |
417726a3 | 2197 | if (root) { |
417726a3 | 2198 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2199 | sp = page_header(root); |
2200 | --sp->root_count; | |
2e53d63a | 2201 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2202 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2203 | &invalid_list); | |
417726a3 | 2204 | } |
ad312c7c | 2205 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2206 | } |
d98ba053 | 2207 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2208 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2209 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2210 | } |
2211 | ||
8986ecc0 MT |
2212 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2213 | { | |
2214 | int ret = 0; | |
2215 | ||
2216 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2217 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2218 | ret = 1; |
2219 | } | |
2220 | ||
2221 | return ret; | |
2222 | } | |
2223 | ||
2224 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2225 | { |
2226 | int i; | |
cea0f0e7 | 2227 | gfn_t root_gfn; |
4db35314 | 2228 | struct kvm_mmu_page *sp; |
f6e2c02b | 2229 | int direct = 0; |
6de4f3ad | 2230 | u64 pdptr; |
3bb65a22 | 2231 | |
ad312c7c | 2232 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2233 | |
ad312c7c ZX |
2234 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2235 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2236 | |
2237 | ASSERT(!VALID_PAGE(root)); | |
8986ecc0 MT |
2238 | if (mmu_check_root(vcpu, root_gfn)) |
2239 | return 1; | |
5a7388c2 EN |
2240 | if (tdp_enabled) { |
2241 | direct = 1; | |
2242 | root_gfn = 0; | |
2243 | } | |
8facbbff | 2244 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2245 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2246 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2247 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2248 | ACC_ALL, NULL); |
4db35314 AK |
2249 | root = __pa(sp->spt); |
2250 | ++sp->root_count; | |
8facbbff | 2251 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2252 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2253 | return 0; |
17ac10ad | 2254 | } |
f6e2c02b | 2255 | direct = !is_paging(vcpu); |
17ac10ad | 2256 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2257 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2258 | |
2259 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2260 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2261 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2262 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2263 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2264 | continue; |
2265 | } | |
6de4f3ad | 2266 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2267 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2268 | root_gfn = 0; |
8986ecc0 MT |
2269 | if (mmu_check_root(vcpu, root_gfn)) |
2270 | return 1; | |
5a7388c2 EN |
2271 | if (tdp_enabled) { |
2272 | direct = 1; | |
2273 | root_gfn = i << 30; | |
2274 | } | |
8facbbff | 2275 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2276 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2277 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2278 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2279 | ACC_ALL, NULL); |
4db35314 AK |
2280 | root = __pa(sp->spt); |
2281 | ++sp->root_count; | |
8facbbff AK |
2282 | spin_unlock(&vcpu->kvm->mmu_lock); |
2283 | ||
ad312c7c | 2284 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2285 | } |
ad312c7c | 2286 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2287 | return 0; |
17ac10ad AK |
2288 | } |
2289 | ||
0ba73cda MT |
2290 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2291 | { | |
2292 | int i; | |
2293 | struct kvm_mmu_page *sp; | |
2294 | ||
2295 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2296 | return; | |
2297 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2298 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2299 | sp = page_header(root); | |
2300 | mmu_sync_children(vcpu, sp); | |
2301 | return; | |
2302 | } | |
2303 | for (i = 0; i < 4; ++i) { | |
2304 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2305 | ||
8986ecc0 | 2306 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2307 | root &= PT64_BASE_ADDR_MASK; |
2308 | sp = page_header(root); | |
2309 | mmu_sync_children(vcpu, sp); | |
2310 | } | |
2311 | } | |
2312 | } | |
2313 | ||
2314 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2315 | { | |
2316 | spin_lock(&vcpu->kvm->mmu_lock); | |
2317 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2318 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2319 | } |
2320 | ||
1871c602 GN |
2321 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2322 | u32 access, u32 *error) | |
6aa8b732 | 2323 | { |
1871c602 GN |
2324 | if (error) |
2325 | *error = 0; | |
6aa8b732 AK |
2326 | return vaddr; |
2327 | } | |
2328 | ||
2329 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2330 | u32 error_code) |
6aa8b732 | 2331 | { |
e833240f | 2332 | gfn_t gfn; |
e2dec939 | 2333 | int r; |
6aa8b732 | 2334 | |
b8688d51 | 2335 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2336 | r = mmu_topup_memory_caches(vcpu); |
2337 | if (r) | |
2338 | return r; | |
714b93da | 2339 | |
6aa8b732 | 2340 | ASSERT(vcpu); |
ad312c7c | 2341 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2342 | |
e833240f | 2343 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2344 | |
e833240f AK |
2345 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2346 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2347 | } |
2348 | ||
fb72d167 JR |
2349 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2350 | u32 error_code) | |
2351 | { | |
35149e21 | 2352 | pfn_t pfn; |
fb72d167 | 2353 | int r; |
852e3c19 | 2354 | int level; |
05da4558 | 2355 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2356 | unsigned long mmu_seq; |
fb72d167 JR |
2357 | |
2358 | ASSERT(vcpu); | |
2359 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2360 | ||
2361 | r = mmu_topup_memory_caches(vcpu); | |
2362 | if (r) | |
2363 | return r; | |
2364 | ||
852e3c19 JR |
2365 | level = mapping_level(vcpu, gfn); |
2366 | ||
2367 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2368 | ||
e930bffe | 2369 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2370 | smp_rmb(); |
35149e21 | 2371 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2372 | if (is_error_pfn(pfn)) |
2373 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2374 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2375 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2376 | goto out_unlock; | |
fb72d167 JR |
2377 | kvm_mmu_free_some_pages(vcpu); |
2378 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2379 | level, gfn, pfn); |
fb72d167 | 2380 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2381 | |
2382 | return r; | |
e930bffe AA |
2383 | |
2384 | out_unlock: | |
2385 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2386 | kvm_release_pfn_clean(pfn); | |
2387 | return 0; | |
fb72d167 JR |
2388 | } |
2389 | ||
6aa8b732 AK |
2390 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2391 | { | |
17ac10ad | 2392 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2393 | } |
2394 | ||
2395 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2396 | { | |
ad312c7c | 2397 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2398 | |
2399 | context->new_cr3 = nonpaging_new_cr3; | |
2400 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2401 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2402 | context->free = nonpaging_free; | |
c7addb90 | 2403 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2404 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2405 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2406 | context->root_level = 0; |
6aa8b732 | 2407 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2408 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2409 | return 0; |
2410 | } | |
2411 | ||
d835dfec | 2412 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2413 | { |
1165f5fe | 2414 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2415 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2416 | } |
2417 | ||
2418 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2419 | { | |
b8688d51 | 2420 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2421 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2422 | } |
2423 | ||
6aa8b732 AK |
2424 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2425 | u64 addr, | |
2426 | u32 err_code) | |
2427 | { | |
c3c91fee | 2428 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2429 | } |
2430 | ||
6aa8b732 AK |
2431 | static void paging_free(struct kvm_vcpu *vcpu) |
2432 | { | |
2433 | nonpaging_free(vcpu); | |
2434 | } | |
2435 | ||
82725b20 DE |
2436 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2437 | { | |
2438 | int bit7; | |
2439 | ||
2440 | bit7 = (gpte >> 7) & 1; | |
2441 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2442 | } | |
2443 | ||
6aa8b732 AK |
2444 | #define PTTYPE 64 |
2445 | #include "paging_tmpl.h" | |
2446 | #undef PTTYPE | |
2447 | ||
2448 | #define PTTYPE 32 | |
2449 | #include "paging_tmpl.h" | |
2450 | #undef PTTYPE | |
2451 | ||
82725b20 DE |
2452 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2453 | { | |
2454 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2455 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2456 | u64 exb_bit_rsvd = 0; | |
2457 | ||
2458 | if (!is_nx(vcpu)) | |
2459 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2460 | switch (level) { | |
2461 | case PT32_ROOT_LEVEL: | |
2462 | /* no rsvd bits for 2 level 4K page table entries */ | |
2463 | context->rsvd_bits_mask[0][1] = 0; | |
2464 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2465 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2466 | ||
2467 | if (!is_pse(vcpu)) { | |
2468 | context->rsvd_bits_mask[1][1] = 0; | |
2469 | break; | |
2470 | } | |
2471 | ||
82725b20 DE |
2472 | if (is_cpuid_PSE36()) |
2473 | /* 36bits PSE 4MB page */ | |
2474 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2475 | else | |
2476 | /* 32 bits PSE 4MB page */ | |
2477 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2478 | break; |
2479 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2480 | context->rsvd_bits_mask[0][2] = |
2481 | rsvd_bits(maxphyaddr, 63) | | |
2482 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2483 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2484 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2485 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2486 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2487 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2488 | rsvd_bits(maxphyaddr, 62) | | |
2489 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2490 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2491 | break; |
2492 | case PT64_ROOT_LEVEL: | |
2493 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2494 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2495 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2496 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2497 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2498 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2499 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2500 | rsvd_bits(maxphyaddr, 51); | |
2501 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2502 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2503 | rsvd_bits(maxphyaddr, 51) | | |
2504 | rsvd_bits(13, 29); | |
82725b20 | 2505 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2506 | rsvd_bits(maxphyaddr, 51) | |
2507 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2508 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2509 | break; |
2510 | } | |
2511 | } | |
2512 | ||
17ac10ad | 2513 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2514 | { |
ad312c7c | 2515 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2516 | |
2517 | ASSERT(is_pae(vcpu)); | |
2518 | context->new_cr3 = paging_new_cr3; | |
2519 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2520 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2521 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2522 | context->sync_page = paging64_sync_page; |
a7052897 | 2523 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2524 | context->free = paging_free; |
17ac10ad AK |
2525 | context->root_level = level; |
2526 | context->shadow_root_level = level; | |
17c3ba9d | 2527 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2528 | return 0; |
2529 | } | |
2530 | ||
17ac10ad AK |
2531 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2532 | { | |
82725b20 | 2533 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2534 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2535 | } | |
2536 | ||
6aa8b732 AK |
2537 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2538 | { | |
ad312c7c | 2539 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2540 | |
82725b20 | 2541 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2542 | context->new_cr3 = paging_new_cr3; |
2543 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2544 | context->gva_to_gpa = paging32_gva_to_gpa; |
2545 | context->free = paging_free; | |
c7addb90 | 2546 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2547 | context->sync_page = paging32_sync_page; |
a7052897 | 2548 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2549 | context->root_level = PT32_ROOT_LEVEL; |
2550 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2551 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2552 | return 0; |
2553 | } | |
2554 | ||
2555 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2556 | { | |
82725b20 | 2557 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2558 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2559 | } |
2560 | ||
fb72d167 JR |
2561 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2562 | { | |
2563 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2564 | ||
2565 | context->new_cr3 = nonpaging_new_cr3; | |
2566 | context->page_fault = tdp_page_fault; | |
2567 | context->free = nonpaging_free; | |
2568 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2569 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2570 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2571 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2572 | context->root_hpa = INVALID_PAGE; |
2573 | ||
2574 | if (!is_paging(vcpu)) { | |
2575 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2576 | context->root_level = 0; | |
2577 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2578 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2579 | context->gva_to_gpa = paging64_gva_to_gpa; |
2580 | context->root_level = PT64_ROOT_LEVEL; | |
2581 | } else if (is_pae(vcpu)) { | |
82725b20 | 2582 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2583 | context->gva_to_gpa = paging64_gva_to_gpa; |
2584 | context->root_level = PT32E_ROOT_LEVEL; | |
2585 | } else { | |
82725b20 | 2586 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2587 | context->gva_to_gpa = paging32_gva_to_gpa; |
2588 | context->root_level = PT32_ROOT_LEVEL; | |
2589 | } | |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
2594 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2595 | { |
a770f6f2 AK |
2596 | int r; |
2597 | ||
6aa8b732 | 2598 | ASSERT(vcpu); |
ad312c7c | 2599 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2600 | |
2601 | if (!is_paging(vcpu)) | |
a770f6f2 | 2602 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2603 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2604 | r = paging64_init_context(vcpu); |
6aa8b732 | 2605 | else if (is_pae(vcpu)) |
a770f6f2 | 2606 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2607 | else |
a770f6f2 AK |
2608 | r = paging32_init_context(vcpu); |
2609 | ||
5b7e0102 | 2610 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
3dbe1415 | 2611 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
a770f6f2 AK |
2612 | |
2613 | return r; | |
6aa8b732 AK |
2614 | } |
2615 | ||
fb72d167 JR |
2616 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2617 | { | |
35149e21 AL |
2618 | vcpu->arch.update_pte.pfn = bad_pfn; |
2619 | ||
fb72d167 JR |
2620 | if (tdp_enabled) |
2621 | return init_kvm_tdp_mmu(vcpu); | |
2622 | else | |
2623 | return init_kvm_softmmu(vcpu); | |
2624 | } | |
2625 | ||
6aa8b732 AK |
2626 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2627 | { | |
2628 | ASSERT(vcpu); | |
62ad0755 SY |
2629 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2630 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2631 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2632 | } |
2633 | ||
2634 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2635 | { |
2636 | destroy_kvm_mmu(vcpu); | |
2637 | return init_kvm_mmu(vcpu); | |
2638 | } | |
8668a3c4 | 2639 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2640 | |
2641 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2642 | { |
714b93da AK |
2643 | int r; |
2644 | ||
e2dec939 | 2645 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2646 | if (r) |
2647 | goto out; | |
8986ecc0 | 2648 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2649 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2650 | mmu_sync_roots(vcpu); |
aaee2c94 | 2651 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2652 | if (r) |
2653 | goto out; | |
3662cb1c | 2654 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2655 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2656 | out: |
2657 | return r; | |
6aa8b732 | 2658 | } |
17c3ba9d AK |
2659 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2660 | ||
2661 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2662 | { | |
2663 | mmu_free_roots(vcpu); | |
2664 | } | |
6aa8b732 | 2665 | |
09072daf | 2666 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2667 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2668 | u64 *spte) |
2669 | { | |
2670 | u64 pte; | |
2671 | struct kvm_mmu_page *child; | |
2672 | ||
2673 | pte = *spte; | |
c7addb90 | 2674 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2675 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 2676 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
2677 | else { |
2678 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2679 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2680 | } |
2681 | } | |
d555c333 | 2682 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2683 | if (is_large_pte(pte)) |
2684 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2685 | } |
2686 | ||
0028425f | 2687 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2688 | struct kvm_mmu_page *sp, |
0028425f | 2689 | u64 *spte, |
489f1d65 | 2690 | const void *new) |
0028425f | 2691 | { |
30945387 | 2692 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2693 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2694 | return; | |
30945387 | 2695 | } |
0028425f | 2696 | |
fa1de2bf XG |
2697 | if (is_rsvd_bits_set(vcpu, *(u64 *)new, PT_PAGE_TABLE_LEVEL)) |
2698 | return; | |
2699 | ||
4cee5764 | 2700 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 2701 | if (!sp->role.cr4_pae) |
489f1d65 | 2702 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2703 | else |
489f1d65 | 2704 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2705 | } |
2706 | ||
79539cec AK |
2707 | static bool need_remote_flush(u64 old, u64 new) |
2708 | { | |
2709 | if (!is_shadow_present_pte(old)) | |
2710 | return false; | |
2711 | if (!is_shadow_present_pte(new)) | |
2712 | return true; | |
2713 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2714 | return true; | |
2715 | old ^= PT64_NX_MASK; | |
2716 | new ^= PT64_NX_MASK; | |
2717 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2718 | } | |
2719 | ||
0671a8e7 XG |
2720 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
2721 | bool remote_flush, bool local_flush) | |
79539cec | 2722 | { |
0671a8e7 XG |
2723 | if (zap_page) |
2724 | return; | |
2725 | ||
2726 | if (remote_flush) | |
79539cec | 2727 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 2728 | else if (local_flush) |
79539cec AK |
2729 | kvm_mmu_flush_tlb(vcpu); |
2730 | } | |
2731 | ||
12b7d28f AK |
2732 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2733 | { | |
ad312c7c | 2734 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2735 | |
7b52345e | 2736 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2737 | } |
2738 | ||
d7824fff | 2739 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2740 | u64 gpte) |
d7824fff AK |
2741 | { |
2742 | gfn_t gfn; | |
35149e21 | 2743 | pfn_t pfn; |
d7824fff | 2744 | |
43a3795a | 2745 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2746 | return; |
2747 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2748 | |
e930bffe | 2749 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2750 | smp_rmb(); |
35149e21 | 2751 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2752 | |
35149e21 AL |
2753 | if (is_error_pfn(pfn)) { |
2754 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2755 | return; |
2756 | } | |
d7824fff | 2757 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2758 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2759 | } |
2760 | ||
1b7fcd32 AK |
2761 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2762 | { | |
2763 | u64 *spte = vcpu->arch.last_pte_updated; | |
2764 | ||
2765 | if (spte | |
2766 | && vcpu->arch.last_pte_gfn == gfn | |
2767 | && shadow_accessed_mask | |
2768 | && !(*spte & shadow_accessed_mask) | |
2769 | && is_shadow_present_pte(*spte)) | |
2770 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2771 | } | |
2772 | ||
09072daf | 2773 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2774 | const u8 *new, int bytes, |
2775 | bool guest_initiated) | |
da4a00f0 | 2776 | { |
9b7a0325 | 2777 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 2778 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 2779 | struct kvm_mmu_page *sp; |
f41d335a | 2780 | struct hlist_node *node; |
d98ba053 | 2781 | LIST_HEAD(invalid_list); |
489f1d65 | 2782 | u64 entry, gentry; |
9b7a0325 | 2783 | u64 *spte; |
9b7a0325 | 2784 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2785 | unsigned pte_size; |
9b7a0325 | 2786 | unsigned page_offset; |
0e7bc4b9 | 2787 | unsigned misaligned; |
fce0657f | 2788 | unsigned quadrant; |
9b7a0325 | 2789 | int level; |
86a5ba02 | 2790 | int flooded = 0; |
ac1b714e | 2791 | int npte; |
489f1d65 | 2792 | int r; |
08e850c6 | 2793 | int invlpg_counter; |
0671a8e7 XG |
2794 | bool remote_flush, local_flush, zap_page; |
2795 | ||
2796 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 2797 | |
b8688d51 | 2798 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2799 | |
08e850c6 | 2800 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2801 | |
2802 | /* | |
2803 | * Assume that the pte write on a page table of the same type | |
2804 | * as the current vcpu paging mode. This is nearly always true | |
2805 | * (might be false while changing modes). Note it is verified later | |
2806 | * by update_pte(). | |
2807 | */ | |
08e850c6 | 2808 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2809 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2810 | if (is_pae(vcpu)) { |
2811 | gpa &= ~(gpa_t)7; | |
2812 | bytes = 8; | |
2813 | } | |
2814 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2815 | if (r) |
2816 | gentry = 0; | |
08e850c6 AK |
2817 | new = (const u8 *)&gentry; |
2818 | } | |
2819 | ||
2820 | switch (bytes) { | |
2821 | case 4: | |
2822 | gentry = *(const u32 *)new; | |
2823 | break; | |
2824 | case 8: | |
2825 | gentry = *(const u64 *)new; | |
2826 | break; | |
2827 | default: | |
2828 | gentry = 0; | |
2829 | break; | |
72016f3a AK |
2830 | } |
2831 | ||
2832 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2833 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2834 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
2835 | gentry = 0; | |
1b7fcd32 | 2836 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2837 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2838 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2839 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2840 | if (guest_initiated) { |
2841 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2842 | && !last_updated_pte_accessed(vcpu)) { | |
2843 | ++vcpu->arch.last_pt_write_count; | |
2844 | if (vcpu->arch.last_pt_write_count >= 3) | |
2845 | flooded = 1; | |
2846 | } else { | |
2847 | vcpu->arch.last_pt_write_gfn = gfn; | |
2848 | vcpu->arch.last_pt_write_count = 1; | |
2849 | vcpu->arch.last_pte_updated = NULL; | |
2850 | } | |
86a5ba02 | 2851 | } |
3246af0e | 2852 | |
fa1de2bf | 2853 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 2854 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 2855 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 2856 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2857 | misaligned |= bytes < 4; |
86a5ba02 | 2858 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2859 | /* |
2860 | * Misaligned accesses are too much trouble to fix | |
2861 | * up; also, they usually indicate a page is not used | |
2862 | * as a page table. | |
86a5ba02 AK |
2863 | * |
2864 | * If we're seeing too many writes to a page, | |
2865 | * it may no longer be a page table, or we may be | |
2866 | * forking, in which case it is better to unmap the | |
2867 | * page. | |
0e7bc4b9 AK |
2868 | */ |
2869 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2870 | gpa, bytes, sp->role.word); |
0671a8e7 | 2871 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 2872 | &invalid_list); |
4cee5764 | 2873 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
2874 | continue; |
2875 | } | |
9b7a0325 | 2876 | page_offset = offset; |
4db35314 | 2877 | level = sp->role.level; |
ac1b714e | 2878 | npte = 1; |
5b7e0102 | 2879 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
2880 | page_offset <<= 1; /* 32->64 */ |
2881 | /* | |
2882 | * A 32-bit pde maps 4MB while the shadow pdes map | |
2883 | * only 2MB. So we need to double the offset again | |
2884 | * and zap two pdes instead of one. | |
2885 | */ | |
2886 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 2887 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
2888 | page_offset <<= 1; |
2889 | npte = 2; | |
2890 | } | |
fce0657f | 2891 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 2892 | page_offset &= ~PAGE_MASK; |
4db35314 | 2893 | if (quadrant != sp->role.quadrant) |
fce0657f | 2894 | continue; |
9b7a0325 | 2895 | } |
0671a8e7 | 2896 | local_flush = true; |
4db35314 | 2897 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 2898 | while (npte--) { |
79539cec | 2899 | entry = *spte; |
4db35314 | 2900 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
2901 | if (gentry && |
2902 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
2903 | & mask.word)) | |
72016f3a | 2904 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
2905 | if (!remote_flush && need_remote_flush(entry, *spte)) |
2906 | remote_flush = true; | |
ac1b714e | 2907 | ++spte; |
9b7a0325 | 2908 | } |
9b7a0325 | 2909 | } |
0671a8e7 | 2910 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 2911 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
c7addb90 | 2912 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 2913 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
2914 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
2915 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
2916 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 2917 | } |
da4a00f0 AK |
2918 | } |
2919 | ||
a436036b AK |
2920 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
2921 | { | |
10589a46 MT |
2922 | gpa_t gpa; |
2923 | int r; | |
a436036b | 2924 | |
60f24784 AK |
2925 | if (tdp_enabled) |
2926 | return 0; | |
2927 | ||
1871c602 | 2928 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 2929 | |
aaee2c94 | 2930 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 2931 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 2932 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 2933 | return r; |
a436036b | 2934 | } |
577bdc49 | 2935 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 2936 | |
22d95b12 | 2937 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 2938 | { |
103ad25a | 2939 | int free_pages; |
d98ba053 | 2940 | LIST_HEAD(invalid_list); |
103ad25a XG |
2941 | |
2942 | free_pages = vcpu->kvm->arch.n_free_mmu_pages; | |
2943 | while (free_pages < KVM_REFILL_PAGES && | |
3b80fffe | 2944 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 2945 | struct kvm_mmu_page *sp; |
ebeace86 | 2946 | |
f05e70ac | 2947 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 2948 | struct kvm_mmu_page, link); |
d98ba053 XG |
2949 | free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2950 | &invalid_list); | |
4cee5764 | 2951 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 2952 | } |
d98ba053 | 2953 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 2954 | } |
ebeace86 | 2955 | |
3067714c AK |
2956 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
2957 | { | |
2958 | int r; | |
2959 | enum emulation_result er; | |
2960 | ||
ad312c7c | 2961 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
2962 | if (r < 0) |
2963 | goto out; | |
2964 | ||
2965 | if (!r) { | |
2966 | r = 1; | |
2967 | goto out; | |
2968 | } | |
2969 | ||
b733bfb5 AK |
2970 | r = mmu_topup_memory_caches(vcpu); |
2971 | if (r) | |
2972 | goto out; | |
2973 | ||
851ba692 | 2974 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
2975 | |
2976 | switch (er) { | |
2977 | case EMULATE_DONE: | |
2978 | return 1; | |
2979 | case EMULATE_DO_MMIO: | |
2980 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 2981 | /* fall through */ |
3067714c | 2982 | case EMULATE_FAIL: |
3f5d18a9 | 2983 | return 0; |
3067714c AK |
2984 | default: |
2985 | BUG(); | |
2986 | } | |
2987 | out: | |
3067714c AK |
2988 | return r; |
2989 | } | |
2990 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
2991 | ||
a7052897 MT |
2992 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2993 | { | |
a7052897 | 2994 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
2995 | kvm_mmu_flush_tlb(vcpu); |
2996 | ++vcpu->stat.invlpg; | |
2997 | } | |
2998 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
2999 | ||
18552672 JR |
3000 | void kvm_enable_tdp(void) |
3001 | { | |
3002 | tdp_enabled = true; | |
3003 | } | |
3004 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3005 | ||
5f4cb662 JR |
3006 | void kvm_disable_tdp(void) |
3007 | { | |
3008 | tdp_enabled = false; | |
3009 | } | |
3010 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3011 | ||
6aa8b732 AK |
3012 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3013 | { | |
ad312c7c | 3014 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
3015 | } |
3016 | ||
3017 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3018 | { | |
17ac10ad | 3019 | struct page *page; |
6aa8b732 AK |
3020 | int i; |
3021 | ||
3022 | ASSERT(vcpu); | |
3023 | ||
17ac10ad AK |
3024 | /* |
3025 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3026 | * Therefore we need to allocate shadow page tables in the first | |
3027 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3028 | */ | |
3029 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3030 | if (!page) | |
d7fa6ab2 WY |
3031 | return -ENOMEM; |
3032 | ||
ad312c7c | 3033 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3034 | for (i = 0; i < 4; ++i) |
ad312c7c | 3035 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3036 | |
6aa8b732 | 3037 | return 0; |
6aa8b732 AK |
3038 | } |
3039 | ||
8018c27b | 3040 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3041 | { |
6aa8b732 | 3042 | ASSERT(vcpu); |
ad312c7c | 3043 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3044 | |
8018c27b IM |
3045 | return alloc_mmu_pages(vcpu); |
3046 | } | |
6aa8b732 | 3047 | |
8018c27b IM |
3048 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3049 | { | |
3050 | ASSERT(vcpu); | |
ad312c7c | 3051 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3052 | |
8018c27b | 3053 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3054 | } |
3055 | ||
3056 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3057 | { | |
3058 | ASSERT(vcpu); | |
3059 | ||
3060 | destroy_kvm_mmu(vcpu); | |
3061 | free_mmu_pages(vcpu); | |
714b93da | 3062 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
3063 | } |
3064 | ||
90cb0529 | 3065 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3066 | { |
4db35314 | 3067 | struct kvm_mmu_page *sp; |
6aa8b732 | 3068 | |
f05e70ac | 3069 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3070 | int i; |
3071 | u64 *pt; | |
3072 | ||
291f26bc | 3073 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3074 | continue; |
3075 | ||
4db35314 | 3076 | pt = sp->spt; |
6aa8b732 AK |
3077 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3078 | /* avoid RMW */ | |
01c168ac | 3079 | if (is_writable_pte(pt[i])) |
6aa8b732 | 3080 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 3081 | } |
171d595d | 3082 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3083 | } |
37a7d8b0 | 3084 | |
90cb0529 | 3085 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3086 | { |
4db35314 | 3087 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3088 | LIST_HEAD(invalid_list); |
e0fa826f | 3089 | |
aaee2c94 | 3090 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3091 | restart: |
f05e70ac | 3092 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3093 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3094 | goto restart; |
3095 | ||
d98ba053 | 3096 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3097 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3098 | } |
3099 | ||
d98ba053 XG |
3100 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3101 | struct list_head *invalid_list) | |
3ee16c81 IE |
3102 | { |
3103 | struct kvm_mmu_page *page; | |
3104 | ||
3105 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3106 | struct kvm_mmu_page, link); | |
d98ba053 | 3107 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3108 | } |
3109 | ||
7f8275d0 | 3110 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3111 | { |
3112 | struct kvm *kvm; | |
3113 | struct kvm *kvm_freed = NULL; | |
3114 | int cache_count = 0; | |
3115 | ||
3116 | spin_lock(&kvm_lock); | |
3117 | ||
3118 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
d35b8dd9 | 3119 | int npages, idx, freed_pages; |
d98ba053 | 3120 | LIST_HEAD(invalid_list); |
3ee16c81 | 3121 | |
f656ce01 | 3122 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 IE |
3123 | spin_lock(&kvm->mmu_lock); |
3124 | npages = kvm->arch.n_alloc_mmu_pages - | |
3125 | kvm->arch.n_free_mmu_pages; | |
3126 | cache_count += npages; | |
3127 | if (!kvm_freed && nr_to_scan > 0 && npages > 0) { | |
d98ba053 XG |
3128 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3129 | &invalid_list); | |
d35b8dd9 | 3130 | cache_count -= freed_pages; |
3ee16c81 IE |
3131 | kvm_freed = kvm; |
3132 | } | |
3133 | nr_to_scan--; | |
3134 | ||
d98ba053 | 3135 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3136 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3137 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3138 | } |
3139 | if (kvm_freed) | |
3140 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3141 | ||
3142 | spin_unlock(&kvm_lock); | |
3143 | ||
3144 | return cache_count; | |
3145 | } | |
3146 | ||
3147 | static struct shrinker mmu_shrinker = { | |
3148 | .shrink = mmu_shrink, | |
3149 | .seeks = DEFAULT_SEEKS * 10, | |
3150 | }; | |
3151 | ||
2ddfd20e | 3152 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3153 | { |
3154 | if (pte_chain_cache) | |
3155 | kmem_cache_destroy(pte_chain_cache); | |
3156 | if (rmap_desc_cache) | |
3157 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3158 | if (mmu_page_header_cache) |
3159 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3160 | } |
3161 | ||
3ee16c81 IE |
3162 | void kvm_mmu_module_exit(void) |
3163 | { | |
3164 | mmu_destroy_caches(); | |
3165 | unregister_shrinker(&mmu_shrinker); | |
3166 | } | |
3167 | ||
b5a33a75 AK |
3168 | int kvm_mmu_module_init(void) |
3169 | { | |
3170 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3171 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3172 | 0, 0, NULL); |
b5a33a75 AK |
3173 | if (!pte_chain_cache) |
3174 | goto nomem; | |
3175 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3176 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3177 | 0, 0, NULL); |
b5a33a75 AK |
3178 | if (!rmap_desc_cache) |
3179 | goto nomem; | |
3180 | ||
d3d25b04 AK |
3181 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3182 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3183 | 0, 0, NULL); |
d3d25b04 AK |
3184 | if (!mmu_page_header_cache) |
3185 | goto nomem; | |
3186 | ||
3ee16c81 IE |
3187 | register_shrinker(&mmu_shrinker); |
3188 | ||
b5a33a75 AK |
3189 | return 0; |
3190 | ||
3191 | nomem: | |
3ee16c81 | 3192 | mmu_destroy_caches(); |
b5a33a75 AK |
3193 | return -ENOMEM; |
3194 | } | |
3195 | ||
3ad82a7e ZX |
3196 | /* |
3197 | * Caculate mmu pages needed for kvm. | |
3198 | */ | |
3199 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3200 | { | |
3201 | int i; | |
3202 | unsigned int nr_mmu_pages; | |
3203 | unsigned int nr_pages = 0; | |
bc6678a3 | 3204 | struct kvm_memslots *slots; |
3ad82a7e | 3205 | |
90d83dc3 LJ |
3206 | slots = kvm_memslots(kvm); |
3207 | ||
bc6678a3 MT |
3208 | for (i = 0; i < slots->nmemslots; i++) |
3209 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3210 | |
3211 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3212 | nr_mmu_pages = max(nr_mmu_pages, | |
3213 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3214 | ||
3215 | return nr_mmu_pages; | |
3216 | } | |
3217 | ||
2f333bcb MT |
3218 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3219 | unsigned len) | |
3220 | { | |
3221 | if (len > buffer->len) | |
3222 | return NULL; | |
3223 | return buffer->ptr; | |
3224 | } | |
3225 | ||
3226 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3227 | unsigned len) | |
3228 | { | |
3229 | void *ret; | |
3230 | ||
3231 | ret = pv_mmu_peek_buffer(buffer, len); | |
3232 | if (!ret) | |
3233 | return ret; | |
3234 | buffer->ptr += len; | |
3235 | buffer->len -= len; | |
3236 | buffer->processed += len; | |
3237 | return ret; | |
3238 | } | |
3239 | ||
3240 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3241 | gpa_t addr, gpa_t value) | |
3242 | { | |
3243 | int bytes = 8; | |
3244 | int r; | |
3245 | ||
3246 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3247 | bytes = 4; | |
3248 | ||
3249 | r = mmu_topup_memory_caches(vcpu); | |
3250 | if (r) | |
3251 | return r; | |
3252 | ||
3200f405 | 3253 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3254 | return -EFAULT; |
3255 | ||
3256 | return 1; | |
3257 | } | |
3258 | ||
3259 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3260 | { | |
2390218b | 3261 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3262 | return 1; |
3263 | } | |
3264 | ||
3265 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3266 | { | |
3267 | spin_lock(&vcpu->kvm->mmu_lock); | |
3268 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3269 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3270 | return 1; | |
3271 | } | |
3272 | ||
3273 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3274 | struct kvm_pv_mmu_op_buffer *buffer) | |
3275 | { | |
3276 | struct kvm_mmu_op_header *header; | |
3277 | ||
3278 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3279 | if (!header) | |
3280 | return 0; | |
3281 | switch (header->op) { | |
3282 | case KVM_MMU_OP_WRITE_PTE: { | |
3283 | struct kvm_mmu_op_write_pte *wpte; | |
3284 | ||
3285 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3286 | if (!wpte) | |
3287 | return 0; | |
3288 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3289 | wpte->pte_val); | |
3290 | } | |
3291 | case KVM_MMU_OP_FLUSH_TLB: { | |
3292 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3293 | ||
3294 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3295 | if (!ftlb) | |
3296 | return 0; | |
3297 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3298 | } | |
3299 | case KVM_MMU_OP_RELEASE_PT: { | |
3300 | struct kvm_mmu_op_release_pt *rpt; | |
3301 | ||
3302 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3303 | if (!rpt) | |
3304 | return 0; | |
3305 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3306 | } | |
3307 | default: return 0; | |
3308 | } | |
3309 | } | |
3310 | ||
3311 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3312 | gpa_t addr, unsigned long *ret) | |
3313 | { | |
3314 | int r; | |
6ad18fba | 3315 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3316 | |
6ad18fba DH |
3317 | buffer->ptr = buffer->buf; |
3318 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3319 | buffer->processed = 0; | |
2f333bcb | 3320 | |
6ad18fba | 3321 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3322 | if (r) |
3323 | goto out; | |
3324 | ||
6ad18fba DH |
3325 | while (buffer->len) { |
3326 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3327 | if (r < 0) |
3328 | goto out; | |
3329 | if (r == 0) | |
3330 | break; | |
3331 | } | |
3332 | ||
3333 | r = 1; | |
3334 | out: | |
6ad18fba | 3335 | *ret = buffer->processed; |
2f333bcb MT |
3336 | return r; |
3337 | } | |
3338 | ||
94d8b056 MT |
3339 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3340 | { | |
3341 | struct kvm_shadow_walk_iterator iterator; | |
3342 | int nr_sptes = 0; | |
3343 | ||
3344 | spin_lock(&vcpu->kvm->mmu_lock); | |
3345 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3346 | sptes[iterator.level-1] = *iterator.sptep; | |
3347 | nr_sptes++; | |
3348 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3349 | break; | |
3350 | } | |
3351 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3352 | ||
3353 | return nr_sptes; | |
3354 | } | |
3355 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3356 | ||
37a7d8b0 AK |
3357 | #ifdef AUDIT |
3358 | ||
3359 | static const char *audit_msg; | |
3360 | ||
3361 | static gva_t canonicalize(gva_t gva) | |
3362 | { | |
3363 | #ifdef CONFIG_X86_64 | |
3364 | gva = (long long)(gva << 16) >> 16; | |
3365 | #endif | |
3366 | return gva; | |
3367 | } | |
3368 | ||
08a3732b | 3369 | |
805d32de | 3370 | typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep); |
08a3732b MT |
3371 | |
3372 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3373 | inspect_spte_fn fn) | |
3374 | { | |
3375 | int i; | |
3376 | ||
3377 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3378 | u64 ent = sp->spt[i]; | |
3379 | ||
3380 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3381 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3382 | struct kvm_mmu_page *child; |
3383 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3384 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3385 | } else |
805d32de | 3386 | fn(kvm, &sp->spt[i]); |
08a3732b MT |
3387 | } |
3388 | } | |
3389 | } | |
3390 | ||
3391 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3392 | { | |
3393 | int i; | |
3394 | struct kvm_mmu_page *sp; | |
3395 | ||
3396 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3397 | return; | |
3398 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3399 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3400 | sp = page_header(root); | |
3401 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3402 | return; | |
3403 | } | |
3404 | for (i = 0; i < 4; ++i) { | |
3405 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3406 | ||
3407 | if (root && VALID_PAGE(root)) { | |
3408 | root &= PT64_BASE_ADDR_MASK; | |
3409 | sp = page_header(root); | |
3410 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3411 | } | |
3412 | } | |
3413 | return; | |
3414 | } | |
3415 | ||
37a7d8b0 AK |
3416 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3417 | gva_t va, int level) | |
3418 | { | |
3419 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3420 | int i; | |
3421 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3422 | ||
3423 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3424 | u64 ent = pt[i]; | |
3425 | ||
c7addb90 | 3426 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3427 | continue; |
3428 | ||
3429 | va = canonicalize(va); | |
2920d728 MT |
3430 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3431 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3432 | else { | |
1871c602 | 3433 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL); |
34382539 JK |
3434 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3435 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3436 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3437 | |
2aaf65e8 MT |
3438 | if (is_error_pfn(pfn)) { |
3439 | kvm_release_pfn_clean(pfn); | |
3440 | continue; | |
3441 | } | |
3442 | ||
c7addb90 | 3443 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3444 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3445 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3446 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3447 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3448 | va, gpa, hpa, ent, |
3449 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3450 | else if (ent == shadow_notrap_nonpresent_pte |
3451 | && !is_error_hpa(hpa)) | |
3452 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3453 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3454 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3455 | |
37a7d8b0 AK |
3456 | } |
3457 | } | |
3458 | } | |
3459 | ||
3460 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3461 | { | |
1ea252af | 3462 | unsigned i; |
37a7d8b0 | 3463 | |
ad312c7c ZX |
3464 | if (vcpu->arch.mmu.root_level == 4) |
3465 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3466 | else |
3467 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3468 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3469 | audit_mappings_page(vcpu, |
ad312c7c | 3470 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3471 | i << 30, |
3472 | 2); | |
3473 | } | |
3474 | ||
3475 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3476 | { | |
805d32de XG |
3477 | struct kvm *kvm = vcpu->kvm; |
3478 | struct kvm_memslots *slots; | |
37a7d8b0 | 3479 | int nmaps = 0; |
bc6678a3 | 3480 | int i, j, k, idx; |
37a7d8b0 | 3481 | |
bc6678a3 | 3482 | idx = srcu_read_lock(&kvm->srcu); |
90d83dc3 | 3483 | slots = kvm_memslots(kvm); |
37a7d8b0 | 3484 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { |
bc6678a3 | 3485 | struct kvm_memory_slot *m = &slots->memslots[i]; |
37a7d8b0 AK |
3486 | struct kvm_rmap_desc *d; |
3487 | ||
3488 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3489 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3490 | |
290fc38d | 3491 | if (!*rmapp) |
37a7d8b0 | 3492 | continue; |
290fc38d | 3493 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3494 | ++nmaps; |
3495 | continue; | |
3496 | } | |
290fc38d | 3497 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3498 | while (d) { |
3499 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3500 | if (d->sptes[k]) |
37a7d8b0 AK |
3501 | ++nmaps; |
3502 | else | |
3503 | break; | |
3504 | d = d->more; | |
3505 | } | |
3506 | } | |
3507 | } | |
bc6678a3 | 3508 | srcu_read_unlock(&kvm->srcu, idx); |
37a7d8b0 AK |
3509 | return nmaps; |
3510 | } | |
3511 | ||
805d32de | 3512 | void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) |
08a3732b MT |
3513 | { |
3514 | unsigned long *rmapp; | |
3515 | struct kvm_mmu_page *rev_sp; | |
3516 | gfn_t gfn; | |
3517 | ||
01c168ac | 3518 | if (is_writable_pte(*sptep)) { |
08a3732b | 3519 | rev_sp = page_header(__pa(sptep)); |
2032a93d | 3520 | gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt); |
08a3732b MT |
3521 | |
3522 | if (!gfn_to_memslot(kvm, gfn)) { | |
3523 | if (!printk_ratelimit()) | |
3524 | return; | |
3525 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3526 | audit_msg, gfn); | |
3527 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
805d32de | 3528 | audit_msg, (long int)(sptep - rev_sp->spt), |
08a3732b MT |
3529 | rev_sp->gfn); |
3530 | dump_stack(); | |
3531 | return; | |
3532 | } | |
3533 | ||
2032a93d | 3534 | rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level); |
08a3732b MT |
3535 | if (!*rmapp) { |
3536 | if (!printk_ratelimit()) | |
3537 | return; | |
3538 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3539 | audit_msg, *sptep); | |
3540 | dump_stack(); | |
3541 | } | |
3542 | } | |
3543 | ||
3544 | } | |
3545 | ||
3546 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3547 | { | |
3548 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3549 | } | |
3550 | ||
3551 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3552 | { |
4db35314 | 3553 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3554 | int i; |
3555 | ||
f05e70ac | 3556 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3557 | u64 *pt = sp->spt; |
37a7d8b0 | 3558 | |
4db35314 | 3559 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3560 | continue; |
3561 | ||
3562 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3563 | u64 ent = pt[i]; | |
3564 | ||
3565 | if (!(ent & PT_PRESENT_MASK)) | |
3566 | continue; | |
01c168ac | 3567 | if (!is_writable_pte(ent)) |
37a7d8b0 | 3568 | continue; |
805d32de | 3569 | inspect_spte_has_rmap(vcpu->kvm, &pt[i]); |
37a7d8b0 AK |
3570 | } |
3571 | } | |
08a3732b | 3572 | return; |
37a7d8b0 AK |
3573 | } |
3574 | ||
3575 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3576 | { | |
08a3732b MT |
3577 | check_writable_mappings_rmap(vcpu); |
3578 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3579 | } |
3580 | ||
3581 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3582 | { | |
4db35314 | 3583 | struct kvm_mmu_page *sp; |
290fc38d IE |
3584 | struct kvm_memory_slot *slot; |
3585 | unsigned long *rmapp; | |
e58b0f9e | 3586 | u64 *spte; |
290fc38d | 3587 | gfn_t gfn; |
37a7d8b0 | 3588 | |
f05e70ac | 3589 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3590 | if (sp->role.direct) |
37a7d8b0 | 3591 | continue; |
e58b0f9e MT |
3592 | if (sp->unsync) |
3593 | continue; | |
37a7d8b0 | 3594 | |
a1f4d395 | 3595 | slot = gfn_to_memslot(vcpu->kvm, sp->gfn); |
290fc38d | 3596 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3597 | |
3598 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3599 | while (spte) { | |
01c168ac | 3600 | if (is_writable_pte(*spte)) |
e58b0f9e MT |
3601 | printk(KERN_ERR "%s: (%s) shadow page has " |
3602 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3603 | __func__, audit_msg, sp->gfn, |
4db35314 | 3604 | sp->role.word); |
e58b0f9e MT |
3605 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3606 | } | |
37a7d8b0 AK |
3607 | } |
3608 | } | |
3609 | ||
3610 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3611 | { | |
3612 | int olddbg = dbg; | |
3613 | ||
3614 | dbg = 0; | |
3615 | audit_msg = msg; | |
3616 | audit_rmap(vcpu); | |
3617 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3618 | if (strcmp("pre pte write", audit_msg) != 0) |
3619 | audit_mappings(vcpu); | |
08a3732b | 3620 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3621 | dbg = olddbg; |
3622 | } | |
3623 | ||
3624 | #endif |