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KVM: Fix Codestyle in virt/kvm/coalesced_mmio.c
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
6aa8b732 34
e495606d
AK		 35#include <asm/page.h>
36#include <asm/cmpxchg.h>
4e542370 37#include <asm/io.h>
13673a90 38#include <asm/vmx.h>
6aa8b732 39
18552672
JR		 40/*
41 * When setting this variable to true it enables Two-Dimensional-Paging
42 * where the hardware walks 2 page tables:
43 * 1. the guest-virtual to guest-physical
44 * 2. while doing 1. it walks guest-physical to host-physical
45 * If the hardware supports that we don't need to do shadow paging.
46 */
2f333bcb 47bool tdp_enabled = false;
18552672 48
37a7d8b0
AK		 49#undef MMU_DEBUG
50
51#undef AUDIT
52
53#ifdef AUDIT
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
55#else
56static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
57#endif
58
59#ifdef MMU_DEBUG
60
61#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
62#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
63
64#else
65
66#define pgprintk(x...) do { } while (0)
67#define rmap_printk(x...) do { } while (0)
68
69#endif
70
71#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 72static int dbg = 0;
73module_param(dbg, bool, 0644);
37a7d8b0 74#endif
6aa8b732 75
582801a9
MT		 76static int oos_shadow = 1;
77module_param(oos_shadow, bool, 0644);
78
d6c69ee9
YD		 79#ifndef MMU_DEBUG
80#define ASSERT(x) do { } while (0)
81#else
6aa8b732
AK		 82#define ASSERT(x) \
83 if (!(x)) { \
84 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
85 __FILE__, __LINE__, #x); \
86 }
d6c69ee9 87#endif
6aa8b732 88
6aa8b732
AK		 89#define PT_FIRST_AVAIL_BITS_SHIFT 9
90#define PT64_SECOND_AVAIL_BITS_SHIFT 52
91
6aa8b732
AK		 92#define VALID_PAGE(x) ((x) != INVALID_PAGE)
93
94#define PT64_LEVEL_BITS 9
95
96#define PT64_LEVEL_SHIFT(level) \
d77c26fc 97 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 98
99#define PT64_LEVEL_MASK(level) \
100 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
101
102#define PT64_INDEX(address, level)\
103 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
104
105
106#define PT32_LEVEL_BITS 10
107
108#define PT32_LEVEL_SHIFT(level) \
d77c26fc 109 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 110
111#define PT32_LEVEL_MASK(level) \
112 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 113#define PT32_LVL_OFFSET_MASK(level) \
114 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 116
117#define PT32_INDEX(address, level)\
118 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
119
120
27aba766 121#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 122#define PT64_DIR_BASE_ADDR_MASK \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 124#define PT64_LVL_ADDR_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
127#define PT64_LVL_OFFSET_MASK(level) \
128 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
129 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 130
131#define PT32_BASE_ADDR_MASK PAGE_MASK
132#define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 134#define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
6aa8b732 137
79539cec
AK		 138#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
139 | PT64_NX_MASK)
6aa8b732
AK		 140
141#define PFERR_PRESENT_MASK (1U << 0)
142#define PFERR_WRITE_MASK (1U << 1)
143#define PFERR_USER_MASK (1U << 2)
82725b20 144#define PFERR_RSVD_MASK (1U << 3)
73b1087e 145#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 146
cd4a4e53
AK		 147#define RMAP_EXT 4
148
fe135d2c
AK		 149#define ACC_EXEC_MASK 1
150#define ACC_WRITE_MASK PT_WRITABLE_MASK
151#define ACC_USER_MASK PT_USER_MASK
152#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
153
07420171
AK		 154#define CREATE_TRACE_POINTS
155#include "mmutrace.h"
156
1403283a
IE		 157#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
158
135f8c2b
AK		 159#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
160
cd4a4e53 161struct kvm_rmap_desc {
d555c333 162 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 163 struct kvm_rmap_desc *more;
164};
165
2d11123a
AK		 166struct kvm_shadow_walk_iterator {
167 u64 addr;
168 hpa_t shadow_addr;
169 int level;
170 u64 *sptep;
171 unsigned index;
172};
173
174#define for_each_shadow_entry(_vcpu, _addr, _walker) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)); \
177 shadow_walk_next(&(_walker)))
178
179
4731d4c7
MT		 180struct kvm_unsync_walk {
181 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
182};
183
ad8cfbe3
MT		 184typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
185
b5a33a75
AK		 186static struct kmem_cache *pte_chain_cache;
187static struct kmem_cache *rmap_desc_cache;
d3d25b04 188static struct kmem_cache *mmu_page_header_cache;
b5a33a75 189
c7addb90
AK		 190static u64 __read_mostly shadow_trap_nonpresent_pte;
191static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 192static u64 __read_mostly shadow_base_present_pte;
193static u64 __read_mostly shadow_nx_mask;
194static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
195static u64 __read_mostly shadow_user_mask;
196static u64 __read_mostly shadow_accessed_mask;
197static u64 __read_mostly shadow_dirty_mask;
c7addb90 198
82725b20
DE		 199static inline u64 rsvd_bits(int s, int e)
200{
201 return ((1ULL << (e - s + 1)) - 1) << s;
202}
203
c7addb90
AK		 204void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
205{
206 shadow_trap_nonpresent_pte = trap_pte;
207 shadow_notrap_nonpresent_pte = notrap_pte;
208}
209EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
210
7b52345e
SY		 211void kvm_mmu_set_base_ptes(u64 base_pte)
212{
213 shadow_base_present_pte = base_pte;
214}
215EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
216
217void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 218 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 219{
220 shadow_user_mask = user_mask;
221 shadow_accessed_mask = accessed_mask;
222 shadow_dirty_mask = dirty_mask;
223 shadow_nx_mask = nx_mask;
224 shadow_x_mask = x_mask;
225}
226EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
227
6aa8b732
AK		 228static int is_write_protection(struct kvm_vcpu *vcpu)
229{
4d4ec087 230 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 231}
232
233static int is_cpuid_PSE36(void)
234{
235 return 1;
236}
237
73b1087e
AK		 238static int is_nx(struct kvm_vcpu *vcpu)
239{
f6801dff 240 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 241}
242
c7addb90
AK		 243static int is_shadow_present_pte(u64 pte)
244{
c7addb90
AK		 245 return pte != shadow_trap_nonpresent_pte
246 && pte != shadow_notrap_nonpresent_pte;
247}
248
05da4558
MT		 249static int is_large_pte(u64 pte)
250{
251 return pte & PT_PAGE_SIZE_MASK;
252}
253
8dae4445 254static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 255{
256 return pte & PT_WRITABLE_MASK;
257}
258
43a3795a 259static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 260{
439e218a 261 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 262}
263
43a3795a 264static int is_rmap_spte(u64 pte)
cd4a4e53 265{
4b1a80fa 266 return is_shadow_present_pte(pte);
cd4a4e53
AK		 267}
268
776e6633
MT		 269static int is_last_spte(u64 pte, int level)
270{
271 if (level == PT_PAGE_TABLE_LEVEL)
272 return 1;
852e3c19 273 if (is_large_pte(pte))
776e6633
MT		 274 return 1;
275 return 0;
276}
277
35149e21 278static pfn_t spte_to_pfn(u64 pte)
0b49ea86 279{
35149e21 280 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 281}
282
da928521
AK		 283static gfn_t pse36_gfn_delta(u32 gpte)
284{
285 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
286
287 return (gpte & PT32_DIR_PSE36_MASK) << shift;
288}
289
d555c333 290static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 291{
292#ifdef CONFIG_X86_64
293 set_64bit((unsigned long *)sptep, spte);
294#else
295 set_64bit((unsigned long long *)sptep, spte);
296#endif
297}
298
e2dec939 299static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 300 struct kmem_cache *base_cache, int min)
714b93da
AK		 301{
302 void *obj;
303
304 if (cache->nobjs >= min)
e2dec939 305 return 0;
714b93da 306 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 307 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 308 if (!obj)
e2dec939 309 return -ENOMEM;
714b93da
AK		 310 cache->objects[cache->nobjs++] = obj;
311 }
e2dec939 312 return 0;
714b93da
AK		 313}
314
315static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
316{
317 while (mc->nobjs)
318 kfree(mc->objects[--mc->nobjs]);
319}
320
c1158e63 321static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 322 int min)
c1158e63
AK		 323{
324 struct page *page;
325
326 if (cache->nobjs >= min)
327 return 0;
328 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 329 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 330 if (!page)
331 return -ENOMEM;
332 set_page_private(page, 0);
333 cache->objects[cache->nobjs++] = page_address(page);
334 }
335 return 0;
336}
337
338static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
339{
340 while (mc->nobjs)
c4d198d5 341 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 342}
343
2e3e5882 344static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 345{
e2dec939
AK		 346 int r;
347
ad312c7c 348 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 349 pte_chain_cache, 4);
e2dec939
AK		 350 if (r)
351 goto out;
ad312c7c 352 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 353 rmap_desc_cache, 4);
d3d25b04
AK		 354 if (r)
355 goto out;
ad312c7c 356 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 357 if (r)
358 goto out;
ad312c7c 359 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 360 mmu_page_header_cache, 4);
e2dec939
AK		 361out:
362 return r;
714b93da
AK		 363}
364
365static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
366{
ad312c7c
ZX		 367 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
368 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
369 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
370 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 371}
372
373static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
374 size_t size)
375{
376 void *p;
377
378 BUG_ON(!mc->nobjs);
379 p = mc->objects[--mc->nobjs];
714b93da
AK		 380 return p;
381}
382
714b93da
AK		 383static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
384{
ad312c7c 385 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 386 sizeof(struct kvm_pte_chain));
387}
388
90cb0529 389static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 390{
90cb0529 391 kfree(pc);
714b93da
AK		 392}
393
394static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
395{
ad312c7c 396 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 397 sizeof(struct kvm_rmap_desc));
398}
399
90cb0529 400static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 401{
90cb0529 402 kfree(rd);
714b93da
AK		 403}
404
05da4558
MT		 405/*
406 * Return the pointer to the largepage write count for a given
407 * gfn, handling slots that are not large page aligned.
408 */
d25797b2
JR		 409static int *slot_largepage_idx(gfn_t gfn,
410 struct kvm_memory_slot *slot,
411 int level)
05da4558
MT		 412{
413 unsigned long idx;
414
d25797b2
JR		 415 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
416 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
417 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 418}
419
420static void account_shadowed(struct kvm *kvm, gfn_t gfn)
421{
d25797b2 422 struct kvm_memory_slot *slot;
05da4558 423 int *write_count;
d25797b2 424 int i;
05da4558 425
2843099f 426 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 427
428 slot = gfn_to_memslot_unaliased(kvm, gfn);
429 for (i = PT_DIRECTORY_LEVEL;
430 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
431 write_count = slot_largepage_idx(gfn, slot, i);
432 *write_count += 1;
433 }
05da4558
MT		 434}
435
436static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
437{
d25797b2 438 struct kvm_memory_slot *slot;
05da4558 439 int *write_count;
d25797b2 440 int i;
05da4558 441
2843099f 442 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 443 for (i = PT_DIRECTORY_LEVEL;
444 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
445 slot = gfn_to_memslot_unaliased(kvm, gfn);
446 write_count = slot_largepage_idx(gfn, slot, i);
447 *write_count -= 1;
448 WARN_ON(*write_count < 0);
449 }
05da4558
MT		 450}
451
d25797b2
JR		 452static int has_wrprotected_page(struct kvm *kvm,
453 gfn_t gfn,
454 int level)
05da4558 455{
2843099f 456 struct kvm_memory_slot *slot;
05da4558
MT		 457 int *largepage_idx;
458
2843099f
IE		 459 gfn = unalias_gfn(kvm, gfn);
460 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 461 if (slot) {
d25797b2 462 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 463 return *largepage_idx;
464 }
465
466 return 1;
467}
468
d25797b2 469static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 470{
8f0b1ab6 471 unsigned long page_size;
d25797b2 472 int i, ret = 0;
05da4558 473
8f0b1ab6 474 page_size = kvm_host_page_size(kvm, gfn);
05da4558 475
d25797b2
JR		 476 for (i = PT_PAGE_TABLE_LEVEL;
477 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
478 if (page_size >= KVM_HPAGE_SIZE(i))
479 ret = i;
480 else
481 break;
482 }
483
4c2155ce 484 return ret;
05da4558
MT		 485}
486
d25797b2 487static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 488{
489 struct kvm_memory_slot *slot;
878403b7 490 int host_level, level, max_level;
05da4558
MT		 491
492 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
493 if (slot && slot->dirty_bitmap)
d25797b2 494 return PT_PAGE_TABLE_LEVEL;
05da4558 495
d25797b2
JR		 496 host_level = host_mapping_level(vcpu->kvm, large_gfn);
497
498 if (host_level == PT_PAGE_TABLE_LEVEL)
499 return host_level;
500
878403b7
SY		 501 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
502 kvm_x86_ops->get_lpage_level() : host_level;
503
504 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 505 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
506 break;
d25797b2
JR		 507
508 return level - 1;
05da4558
MT		 509}
510
290fc38d
IE		 511/*
512 * Take gfn and return the reverse mapping to it.
513 * Note: gfn must be unaliased before this function get called
514 */
515
44ad9944 516static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 517{
518 struct kvm_memory_slot *slot;
05da4558 519 unsigned long idx;
290fc38d
IE		 520
521 slot = gfn_to_memslot(kvm, gfn);
44ad9944 522 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 523 return &slot->rmap[gfn - slot->base_gfn];
524
44ad9944
JR		 525 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
526 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 527
44ad9944 528 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 529}
530
cd4a4e53
AK		 531/*
532 * Reverse mapping data structures:
533 *
290fc38d
IE		 534 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
535 * that points to page_address(page).
cd4a4e53 536 *
290fc38d
IE		 537 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
538 * containing more mappings.
53a27b39
MT		 539 *
540 * Returns the number of rmap entries before the spte was added or zero if
541 * the spte was not added.
542 *
cd4a4e53 543 */
44ad9944 544static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 545{
4db35314 546 struct kvm_mmu_page *sp;
cd4a4e53 547 struct kvm_rmap_desc *desc;
290fc38d 548 unsigned long *rmapp;
53a27b39 549 int i, count = 0;
cd4a4e53 550
43a3795a 551 if (!is_rmap_spte(*spte))
53a27b39 552 return count;
290fc38d 553 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 554 sp = page_header(__pa(spte));
555 sp->gfns[spte - sp->spt] = gfn;
44ad9944 556 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 557 if (!*rmapp) {
cd4a4e53 558 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 559 *rmapp = (unsigned long)spte;
560 } else if (!(*rmapp & 1)) {
cd4a4e53 561 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 562 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 563 desc->sptes[0] = (u64 *)*rmapp;
564 desc->sptes[1] = spte;
290fc38d 565 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 566 } else {
567 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 568 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 569 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 570 desc = desc->more;
53a27b39
MT		 571 count += RMAP_EXT;
572 }
d555c333 573 if (desc->sptes[RMAP_EXT-1]) {
714b93da 574 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 575 desc = desc->more;
576 }
d555c333 577 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 578 ;
d555c333 579 desc->sptes[i] = spte;
cd4a4e53 580 }
53a27b39 581 return count;
cd4a4e53
AK		 582}
583
290fc38d 584static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 585 struct kvm_rmap_desc *desc,
586 int i,
587 struct kvm_rmap_desc *prev_desc)
588{
589 int j;
590
d555c333 591 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 592 ;
d555c333
AK		 593 desc->sptes[i] = desc->sptes[j];
594 desc->sptes[j] = NULL;
cd4a4e53
AK		 595 if (j != 0)
596 return;
597 if (!prev_desc && !desc->more)
d555c333 598 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 599 else
600 if (prev_desc)
601 prev_desc->more = desc->more;
602 else
290fc38d 603 *rmapp = (unsigned long)desc->more | 1;
90cb0529 604 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 605}
606
290fc38d 607static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 608{
cd4a4e53
AK		 609 struct kvm_rmap_desc *desc;
610 struct kvm_rmap_desc *prev_desc;
4db35314 611 struct kvm_mmu_page *sp;
35149e21 612 pfn_t pfn;
290fc38d 613 unsigned long *rmapp;
cd4a4e53
AK		 614 int i;
615
43a3795a 616 if (!is_rmap_spte(*spte))
cd4a4e53 617 return;
4db35314 618 sp = page_header(__pa(spte));
35149e21 619 pfn = spte_to_pfn(*spte);
7b52345e 620 if (*spte & shadow_accessed_mask)
35149e21 621 kvm_set_pfn_accessed(pfn);
8dae4445 622 if (is_writable_pte(*spte))
acb66dd0 623 kvm_set_pfn_dirty(pfn);
44ad9944 624 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 625 if (!*rmapp) {
cd4a4e53
AK		 626 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
627 BUG();
290fc38d 628 } else if (!(*rmapp & 1)) {
cd4a4e53 629 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 630 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 631 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
632 spte, *spte);
633 BUG();
634 }
290fc38d 635 *rmapp = 0;
cd4a4e53
AK		 636 } else {
637 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 638 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 639 prev_desc = NULL;
640 while (desc) {
d555c333
AK		 641 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
642 if (desc->sptes[i] == spte) {
290fc38d 643 rmap_desc_remove_entry(rmapp,
714b93da 644 desc, i,
cd4a4e53
AK		 645 prev_desc);
646 return;
647 }
648 prev_desc = desc;
649 desc = desc->more;
650 }
186a3e52 651 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 652 BUG();
653 }
654}
655
98348e95 656static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 657{
374cbac0 658 struct kvm_rmap_desc *desc;
98348e95
IE		 659 struct kvm_rmap_desc *prev_desc;
660 u64 *prev_spte;
661 int i;
662
663 if (!*rmapp)
664 return NULL;
665 else if (!(*rmapp & 1)) {
666 if (!spte)
667 return (u64 *)*rmapp;
668 return NULL;
669 }
670 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
671 prev_desc = NULL;
672 prev_spte = NULL;
673 while (desc) {
d555c333 674 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 675 if (prev_spte == spte)
d555c333
AK		 676 return desc->sptes[i];
677 prev_spte = desc->sptes[i];
98348e95
IE		 678 }
679 desc = desc->more;
680 }
681 return NULL;
682}
683
b1a36821 684static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 685{
290fc38d 686 unsigned long *rmapp;
374cbac0 687 u64 *spte;
44ad9944 688 int i, write_protected = 0;
374cbac0 689
4a4c9924 690 gfn = unalias_gfn(kvm, gfn);
44ad9944 691 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 692
98348e95
IE		 693 spte = rmap_next(kvm, rmapp, NULL);
694 while (spte) {
374cbac0 695 BUG_ON(!spte);
374cbac0 696 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 697 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 698 if (is_writable_pte(*spte)) {
d555c333 699 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 700 write_protected = 1;
701 }
9647c14c 702 spte = rmap_next(kvm, rmapp, spte);
374cbac0 703 }
855149aa 704 if (write_protected) {
35149e21 705 pfn_t pfn;
855149aa
IE		 706
707 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 708 pfn = spte_to_pfn(*spte);
709 kvm_set_pfn_dirty(pfn);
855149aa
IE		 710 }
711
05da4558 712 /* check for huge page mappings */
44ad9944
JR		 713 for (i = PT_DIRECTORY_LEVEL;
714 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
715 rmapp = gfn_to_rmap(kvm, gfn, i);
716 spte = rmap_next(kvm, rmapp, NULL);
717 while (spte) {
718 BUG_ON(!spte);
719 BUG_ON(!(*spte & PT_PRESENT_MASK));
720 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
721 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 722 if (is_writable_pte(*spte)) {
44ad9944
JR		 723 rmap_remove(kvm, spte);
724 --kvm->stat.lpages;
725 __set_spte(spte, shadow_trap_nonpresent_pte);
726 spte = NULL;
727 write_protected = 1;
728 }
729 spte = rmap_next(kvm, rmapp, spte);
05da4558 730 }
05da4558
MT		 731 }
732
b1a36821 733 return write_protected;
374cbac0
AK		 734}
735
8a8365c5
FD		 736static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
737 unsigned long data)
e930bffe
AA		 738{
739 u64 *spte;
740 int need_tlb_flush = 0;
741
742 while ((spte = rmap_next(kvm, rmapp, NULL))) {
743 BUG_ON(!(*spte & PT_PRESENT_MASK));
744 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
745 rmap_remove(kvm, spte);
d555c333 746 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 747 need_tlb_flush = 1;
748 }
749 return need_tlb_flush;
750}
751
8a8365c5
FD		 752static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
753 unsigned long data)
3da0dd43
IE		 754{
755 int need_flush = 0;
756 u64 *spte, new_spte;
757 pte_t *ptep = (pte_t *)data;
758 pfn_t new_pfn;
759
760 WARN_ON(pte_huge(*ptep));
761 new_pfn = pte_pfn(*ptep);
762 spte = rmap_next(kvm, rmapp, NULL);
763 while (spte) {
764 BUG_ON(!is_shadow_present_pte(*spte));
765 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
766 need_flush = 1;
767 if (pte_write(*ptep)) {
768 rmap_remove(kvm, spte);
769 __set_spte(spte, shadow_trap_nonpresent_pte);
770 spte = rmap_next(kvm, rmapp, NULL);
771 } else {
772 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
773 new_spte |= (u64)new_pfn << PAGE_SHIFT;
774
775 new_spte &= ~PT_WRITABLE_MASK;
776 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 777 if (is_writable_pte(*spte))
3da0dd43
IE		 778 kvm_set_pfn_dirty(spte_to_pfn(*spte));
779 __set_spte(spte, new_spte);
780 spte = rmap_next(kvm, rmapp, spte);
781 }
782 }
783 if (need_flush)
784 kvm_flush_remote_tlbs(kvm);
785
786 return 0;
787}
788
8a8365c5
FD		 789static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
790 unsigned long data,
3da0dd43 791 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 792 unsigned long data))
e930bffe 793{
852e3c19 794 int i, j;
e930bffe 795 int retval = 0;
bc6678a3
MT		 796 struct kvm_memslots *slots;
797
798 slots = rcu_dereference(kvm->memslots);
e930bffe 799
46a26bf5
MT		 800 for (i = 0; i < slots->nmemslots; i++) {
801 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 802 unsigned long start = memslot->userspace_addr;
803 unsigned long end;
804
e930bffe
AA		 805 end = start + (memslot->npages << PAGE_SHIFT);
806 if (hva >= start && hva < end) {
807 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 808
3da0dd43
IE		 809 retval |= handler(kvm, &memslot->rmap[gfn_offset],
810 data);
852e3c19
JR		 811
812 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
813 int idx = gfn_offset;
814 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
815 retval |= handler(kvm,
3da0dd43
IE		 816 &memslot->lpage_info[j][idx].rmap_pde,
817 data);
852e3c19 818 }
e930bffe
AA		 819 }
820 }
821
822 return retval;
823}
824
825int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
826{
3da0dd43
IE		 827 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
828}
829
830void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
831{
8a8365c5 832 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 833}
834
8a8365c5
FD		 835static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
836 unsigned long data)
e930bffe
AA		 837{
838 u64 *spte;
839 int young = 0;
840
6316e1c8
RR		 841 /*
842 * Emulate the accessed bit for EPT, by checking if this page has
843 * an EPT mapping, and clearing it if it does. On the next access,
844 * a new EPT mapping will be established.
845 * This has some overhead, but not as much as the cost of swapping
846 * out actively used pages or breaking up actively used hugepages.
847 */
534e38b4 848 if (!shadow_accessed_mask)
6316e1c8 849 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 850
e930bffe
AA		 851 spte = rmap_next(kvm, rmapp, NULL);
852 while (spte) {
853 int _young;
854 u64 _spte = *spte;
855 BUG_ON(!(_spte & PT_PRESENT_MASK));
856 _young = _spte & PT_ACCESSED_MASK;
857 if (_young) {
858 young = 1;
859 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
860 }
861 spte = rmap_next(kvm, rmapp, spte);
862 }
863 return young;
864}
865
53a27b39
MT		 866#define RMAP_RECYCLE_THRESHOLD 1000
867
852e3c19 868static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 869{
870 unsigned long *rmapp;
852e3c19
JR		 871 struct kvm_mmu_page *sp;
872
873 sp = page_header(__pa(spte));
53a27b39
MT		 874
875 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 876 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 877
3da0dd43 878 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 879 kvm_flush_remote_tlbs(vcpu->kvm);
880}
881
e930bffe
AA		 882int kvm_age_hva(struct kvm *kvm, unsigned long hva)
883{
3da0dd43 884 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 885}
886
d6c69ee9 887#ifdef MMU_DEBUG
47ad8e68 888static int is_empty_shadow_page(u64 *spt)
6aa8b732 889{
139bdb2d
AK		 890 u64 *pos;
891 u64 *end;
892
47ad8e68 893 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 894 if (is_shadow_present_pte(*pos)) {
b8688d51 895 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 896 pos, *pos);
6aa8b732 897 return 0;
139bdb2d 898 }
6aa8b732
AK		 899 return 1;
900}
d6c69ee9 901#endif
6aa8b732 902
4db35314 903static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 904{
4db35314
AK		 905 ASSERT(is_empty_shadow_page(sp->spt));
906 list_del(&sp->link);
907 __free_page(virt_to_page(sp->spt));
908 __free_page(virt_to_page(sp->gfns));
909 kfree(sp);
f05e70ac 910 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 911}
912
cea0f0e7
AK		 913static unsigned kvm_page_table_hashfn(gfn_t gfn)
914{
1ae0a13d 915 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 916}
917
25c0de2c
AK		 918static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
919 u64 *parent_pte)
6aa8b732 920{
4db35314 921 struct kvm_mmu_page *sp;
6aa8b732 922
ad312c7c
ZX		 923 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
924 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
925 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 926 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 927 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 928 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 929 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 930 sp->multimapped = 0;
931 sp->parent_pte = parent_pte;
f05e70ac 932 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 933 return sp;
6aa8b732
AK		 934}
935
714b93da 936static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 937 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 938{
939 struct kvm_pte_chain *pte_chain;
940 struct hlist_node *node;
941 int i;
942
943 if (!parent_pte)
944 return;
4db35314
AK		 945 if (!sp->multimapped) {
946 u64 *old = sp->parent_pte;
cea0f0e7
AK		 947
948 if (!old) {
4db35314 949 sp->parent_pte = parent_pte;
cea0f0e7
AK		 950 return;
951 }
4db35314 952 sp->multimapped = 1;
714b93da 953 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 954 INIT_HLIST_HEAD(&sp->parent_ptes);
955 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 956 pte_chain->parent_ptes[0] = old;
957 }
4db35314 958 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 959 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
960 continue;
961 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
962 if (!pte_chain->parent_ptes[i]) {
963 pte_chain->parent_ptes[i] = parent_pte;
964 return;
965 }
966 }
714b93da 967 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 968 BUG_ON(!pte_chain);
4db35314 969 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 970 pte_chain->parent_ptes[0] = parent_pte;
971}
972
4db35314 973static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 974 u64 *parent_pte)
975{
976 struct kvm_pte_chain *pte_chain;
977 struct hlist_node *node;
978 int i;
979
4db35314
AK		 980 if (!sp->multimapped) {
981 BUG_ON(sp->parent_pte != parent_pte);
982 sp->parent_pte = NULL;
cea0f0e7
AK		 983 return;
984 }
4db35314 985 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 986 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
987 if (!pte_chain->parent_ptes[i])
988 break;
989 if (pte_chain->parent_ptes[i] != parent_pte)
990 continue;
697fe2e2
AK		 991 while (i + 1 < NR_PTE_CHAIN_ENTRIES
992 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 993 pte_chain->parent_ptes[i]
994 = pte_chain->parent_ptes[i + 1];
995 ++i;
996 }
997 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 998 if (i == 0) {
999 hlist_del(&pte_chain->link);
90cb0529 1000 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1001 if (hlist_empty(&sp->parent_ptes)) {
1002 sp->multimapped = 0;
1003 sp->parent_pte = NULL;
697fe2e2
AK		 1004 }
1005 }
cea0f0e7
AK		 1006 return;
1007 }
1008 BUG();
1009}
1010
ad8cfbe3
MT		 1011
1012static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1013 mmu_parent_walk_fn fn)
1014{
1015 struct kvm_pte_chain *pte_chain;
1016 struct hlist_node *node;
1017 struct kvm_mmu_page *parent_sp;
1018 int i;
1019
1020 if (!sp->multimapped && sp->parent_pte) {
1021 parent_sp = page_header(__pa(sp->parent_pte));
1022 fn(vcpu, parent_sp);
1023 mmu_parent_walk(vcpu, parent_sp, fn);
1024 return;
1025 }
1026 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1027 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1028 if (!pte_chain->parent_ptes[i])
1029 break;
1030 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1031 fn(vcpu, parent_sp);
1032 mmu_parent_walk(vcpu, parent_sp, fn);
1033 }
1034}
1035
0074ff63
MT		 1036static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1037{
1038 unsigned int index;
1039 struct kvm_mmu_page *sp = page_header(__pa(spte));
1040
1041 index = spte - sp->spt;
60c8aec6
MT		 1042 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1043 sp->unsync_children++;
1044 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1045}
1046
1047static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1048{
1049 struct kvm_pte_chain *pte_chain;
1050 struct hlist_node *node;
1051 int i;
1052
1053 if (!sp->parent_pte)
1054 return;
1055
1056 if (!sp->multimapped) {
1057 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1058 return;
1059 }
1060
1061 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1062 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1063 if (!pte_chain->parent_ptes[i])
1064 break;
1065 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1066 }
1067}
1068
1069static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1070{
0074ff63
MT		 1071 kvm_mmu_update_parents_unsync(sp);
1072 return 1;
1073}
1074
1075static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1076 struct kvm_mmu_page *sp)
1077{
1078 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1079 kvm_mmu_update_parents_unsync(sp);
1080}
1081
d761a501
AK		 1082static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1083 struct kvm_mmu_page *sp)
1084{
1085 int i;
1086
1087 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1088 sp->spt[i] = shadow_trap_nonpresent_pte;
1089}
1090
e8bc217a
MT		 1091static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1092 struct kvm_mmu_page *sp)
1093{
1094 return 1;
1095}
1096
a7052897
MT		 1097static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1098{
1099}
1100
60c8aec6
MT		 1101#define KVM_PAGE_ARRAY_NR 16
1102
1103struct kvm_mmu_pages {
1104 struct mmu_page_and_offset {
1105 struct kvm_mmu_page *sp;
1106 unsigned int idx;
1107 } page[KVM_PAGE_ARRAY_NR];
1108 unsigned int nr;
1109};
1110
0074ff63
MT		 1111#define for_each_unsync_children(bitmap, idx) \
1112 for (idx = find_first_bit(bitmap, 512); \
1113 idx < 512; \
1114 idx = find_next_bit(bitmap, 512, idx+1))
1115
cded19f3
HE		 1116static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1117 int idx)
4731d4c7 1118{
60c8aec6 1119 int i;
4731d4c7 1120
60c8aec6
MT		 1121 if (sp->unsync)
1122 for (i=0; i < pvec->nr; i++)
1123 if (pvec->page[i].sp == sp)
1124 return 0;
1125
1126 pvec->page[pvec->nr].sp = sp;
1127 pvec->page[pvec->nr].idx = idx;
1128 pvec->nr++;
1129 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1130}
1131
1132static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1133 struct kvm_mmu_pages *pvec)
1134{
1135 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1136
0074ff63 1137 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1138 u64 ent = sp->spt[i];
1139
87917239 1140 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1141 struct kvm_mmu_page *child;
1142 child = page_header(ent & PT64_BASE_ADDR_MASK);
1143
1144 if (child->unsync_children) {
60c8aec6
MT		 1145 if (mmu_pages_add(pvec, child, i))
1146 return -ENOSPC;
1147
1148 ret = __mmu_unsync_walk(child, pvec);
1149 if (!ret)
1150 __clear_bit(i, sp->unsync_child_bitmap);
1151 else if (ret > 0)
1152 nr_unsync_leaf += ret;
1153 else
4731d4c7
MT		 1154 return ret;
1155 }
1156
1157 if (child->unsync) {
60c8aec6
MT		 1158 nr_unsync_leaf++;
1159 if (mmu_pages_add(pvec, child, i))
1160 return -ENOSPC;
4731d4c7
MT		 1161 }
1162 }
1163 }
1164
0074ff63 1165 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1166 sp->unsync_children = 0;
1167
60c8aec6
MT		 1168 return nr_unsync_leaf;
1169}
1170
1171static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1172 struct kvm_mmu_pages *pvec)
1173{
1174 if (!sp->unsync_children)
1175 return 0;
1176
1177 mmu_pages_add(pvec, sp, 0);
1178 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1179}
1180
4db35314 1181static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1182{
1183 unsigned index;
1184 struct hlist_head *bucket;
4db35314 1185 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1186 struct hlist_node *node;
1187
b8688d51 1188 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1189 index = kvm_page_table_hashfn(gfn);
f05e70ac 1190 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1191 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1192 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1193 && !sp->role.invalid) {
cea0f0e7 1194 pgprintk("%s: found role %x\n",
b8688d51 1195 __func__, sp->role.word);
4db35314 1196 return sp;
cea0f0e7
AK		 1197 }
1198 return NULL;
1199}
1200
4731d4c7
MT		 1201static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1202{
1203 WARN_ON(!sp->unsync);
1204 sp->unsync = 0;
1205 --kvm->stat.mmu_unsync;
1206}
1207
1208static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1209
1210static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1211{
1212 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1213 kvm_mmu_zap_page(vcpu->kvm, sp);
1214 return 1;
1215 }
1216
f691fe1d 1217 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1218 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1219 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1220 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1221 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1222 kvm_mmu_zap_page(vcpu->kvm, sp);
1223 return 1;
1224 }
1225
1226 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1227 return 0;
1228}
1229
60c8aec6
MT		 1230struct mmu_page_path {
1231 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1232 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1233};
1234
60c8aec6
MT		 1235#define for_each_sp(pvec, sp, parents, i) \
1236 for (i = mmu_pages_next(&pvec, &parents, -1), \
1237 sp = pvec.page[i].sp; \
1238 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1239 i = mmu_pages_next(&pvec, &parents, i))
1240
cded19f3
HE		 1241static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1242 struct mmu_page_path *parents,
1243 int i)
60c8aec6
MT		 1244{
1245 int n;
1246
1247 for (n = i+1; n < pvec->nr; n++) {
1248 struct kvm_mmu_page *sp = pvec->page[n].sp;
1249
1250 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1251 parents->idx[0] = pvec->page[n].idx;
1252 return n;
1253 }
1254
1255 parents->parent[sp->role.level-2] = sp;
1256 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1257 }
1258
1259 return n;
1260}
1261
cded19f3 1262static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1263{
60c8aec6
MT		 1264 struct kvm_mmu_page *sp;
1265 unsigned int level = 0;
1266
1267 do {
1268 unsigned int idx = parents->idx[level];
4731d4c7 1269
60c8aec6
MT		 1270 sp = parents->parent[level];
1271 if (!sp)
1272 return;
1273
1274 --sp->unsync_children;
1275 WARN_ON((int)sp->unsync_children < 0);
1276 __clear_bit(idx, sp->unsync_child_bitmap);
1277 level++;
1278 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1279}
1280
60c8aec6
MT		 1281static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1282 struct mmu_page_path *parents,
1283 struct kvm_mmu_pages *pvec)
4731d4c7 1284{
60c8aec6
MT		 1285 parents->parent[parent->role.level-1] = NULL;
1286 pvec->nr = 0;
1287}
4731d4c7 1288
60c8aec6
MT		 1289static void mmu_sync_children(struct kvm_vcpu *vcpu,
1290 struct kvm_mmu_page *parent)
1291{
1292 int i;
1293 struct kvm_mmu_page *sp;
1294 struct mmu_page_path parents;
1295 struct kvm_mmu_pages pages;
1296
1297 kvm_mmu_pages_init(parent, &parents, &pages);
1298 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1299 int protected = 0;
1300
1301 for_each_sp(pages, sp, parents, i)
1302 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1303
1304 if (protected)
1305 kvm_flush_remote_tlbs(vcpu->kvm);
1306
60c8aec6
MT		 1307 for_each_sp(pages, sp, parents, i) {
1308 kvm_sync_page(vcpu, sp);
1309 mmu_pages_clear_parents(&parents);
1310 }
4731d4c7 1311 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1312 kvm_mmu_pages_init(parent, &parents, &pages);
1313 }
4731d4c7
MT		 1314}
1315
cea0f0e7
AK		 1316static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1317 gfn_t gfn,
1318 gva_t gaddr,
1319 unsigned level,
f6e2c02b 1320 int direct,
41074d07 1321 unsigned access,
f7d9c7b7 1322 u64 *parent_pte)
cea0f0e7
AK		 1323{
1324 union kvm_mmu_page_role role;
1325 unsigned index;
1326 unsigned quadrant;
1327 struct hlist_head *bucket;
4db35314 1328 struct kvm_mmu_page *sp;
4731d4c7 1329 struct hlist_node *node, *tmp;
cea0f0e7 1330
a770f6f2 1331 role = vcpu->arch.mmu.base_role;
cea0f0e7 1332 role.level = level;
f6e2c02b 1333 role.direct = direct;
41074d07 1334 role.access = access;
ad312c7c 1335 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1336 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1337 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1338 role.quadrant = quadrant;
1339 }
1ae0a13d 1340 index = kvm_page_table_hashfn(gfn);
f05e70ac 1341 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1342 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1343 if (sp->gfn == gfn) {
1344 if (sp->unsync)
1345 if (kvm_sync_page(vcpu, sp))
1346 continue;
1347
1348 if (sp->role.word != role.word)
1349 continue;
1350
4db35314 1351 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1352 if (sp->unsync_children) {
1353 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1354 kvm_mmu_mark_parents_unsync(vcpu, sp);
1355 }
f691fe1d 1356 trace_kvm_mmu_get_page(sp, false);
4db35314 1357 return sp;
cea0f0e7 1358 }
dfc5aa00 1359 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1360 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1361 if (!sp)
1362 return sp;
4db35314
AK		 1363 sp->gfn = gfn;
1364 sp->role = role;
1365 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1366 if (!direct) {
b1a36821
MT		 1367 if (rmap_write_protect(vcpu->kvm, gfn))
1368 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1369 account_shadowed(vcpu->kvm, gfn);
1370 }
131d8279
AK		 1371 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1372 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1373 else
1374 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1375 trace_kvm_mmu_get_page(sp, true);
4db35314 1376 return sp;
cea0f0e7
AK		 1377}
1378
2d11123a
AK		 1379static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1380 struct kvm_vcpu *vcpu, u64 addr)
1381{
1382 iterator->addr = addr;
1383 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1384 iterator->level = vcpu->arch.mmu.shadow_root_level;
1385 if (iterator->level == PT32E_ROOT_LEVEL) {
1386 iterator->shadow_addr
1387 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1388 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1389 --iterator->level;
1390 if (!iterator->shadow_addr)
1391 iterator->level = 0;
1392 }
1393}
1394
1395static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1396{
1397 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1398 return false;
4d88954d
MT		 1399
1400 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1401 if (is_large_pte(*iterator->sptep))
1402 return false;
1403
2d11123a
AK		 1404 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1405 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1406 return true;
1407}
1408
1409static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1410{
1411 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1412 --iterator->level;
1413}
1414
90cb0529 1415static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1416 struct kvm_mmu_page *sp)
a436036b 1417{
697fe2e2
AK		 1418 unsigned i;
1419 u64 *pt;
1420 u64 ent;
1421
4db35314 1422 pt = sp->spt;
697fe2e2 1423
697fe2e2
AK		 1424 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1425 ent = pt[i];
1426
05da4558 1427 if (is_shadow_present_pte(ent)) {
776e6633 1428 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1429 ent &= PT64_BASE_ADDR_MASK;
1430 mmu_page_remove_parent_pte(page_header(ent),
1431 &pt[i]);
1432 } else {
776e6633
MT		 1433 if (is_large_pte(ent))
1434 --kvm->stat.lpages;
05da4558
MT		 1435 rmap_remove(kvm, &pt[i]);
1436 }
1437 }
c7addb90 1438 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1439 }
a436036b
AK		 1440}
1441
4db35314 1442static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1443{
4db35314 1444 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1445}
1446
12b7d28f
AK		 1447static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1448{
1449 int i;
988a2cae 1450 struct kvm_vcpu *vcpu;
12b7d28f 1451
988a2cae
GN		 1452 kvm_for_each_vcpu(i, vcpu, kvm)
1453 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1454}
1455
31aa2b44 1456static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1457{
1458 u64 *parent_pte;
1459
4db35314
AK		 1460 while (sp->multimapped || sp->parent_pte) {
1461 if (!sp->multimapped)
1462 parent_pte = sp->parent_pte;
a436036b
AK		 1463 else {
1464 struct kvm_pte_chain *chain;
1465
4db35314 1466 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1467 struct kvm_pte_chain, link);
1468 parent_pte = chain->parent_ptes[0];
1469 }
697fe2e2 1470 BUG_ON(!parent_pte);
4db35314 1471 kvm_mmu_put_page(sp, parent_pte);
d555c333 1472 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1473 }
31aa2b44
AK		 1474}
1475
60c8aec6
MT		 1476static int mmu_zap_unsync_children(struct kvm *kvm,
1477 struct kvm_mmu_page *parent)
4731d4c7 1478{
60c8aec6
MT		 1479 int i, zapped = 0;
1480 struct mmu_page_path parents;
1481 struct kvm_mmu_pages pages;
4731d4c7 1482
60c8aec6 1483 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1484 return 0;
60c8aec6
MT		 1485
1486 kvm_mmu_pages_init(parent, &parents, &pages);
1487 while (mmu_unsync_walk(parent, &pages)) {
1488 struct kvm_mmu_page *sp;
1489
1490 for_each_sp(pages, sp, parents, i) {
1491 kvm_mmu_zap_page(kvm, sp);
1492 mmu_pages_clear_parents(&parents);
1493 }
1494 zapped += pages.nr;
1495 kvm_mmu_pages_init(parent, &parents, &pages);
1496 }
1497
1498 return zapped;
4731d4c7
MT		 1499}
1500
07385413 1501static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1502{
4731d4c7 1503 int ret;
f691fe1d
AK		 1504
1505 trace_kvm_mmu_zap_page(sp);
31aa2b44 1506 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1507 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1508 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1509 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1510 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1511 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1512 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1513 if (sp->unsync)
1514 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1515 if (!sp->root_count) {
1516 hlist_del(&sp->hash_link);
1517 kvm_mmu_free_page(kvm, sp);
2e53d63a 1518 } else {
2e53d63a 1519 sp->role.invalid = 1;
5b5c6a5a 1520 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1521 kvm_reload_remote_mmus(kvm);
1522 }
12b7d28f 1523 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1524 return ret;
a436036b
AK		 1525}
1526
82ce2c96
IE		 1527/*
1528 * Changing the number of mmu pages allocated to the vm
1529 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1530 */
1531void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1532{
025dbbf3
MT		 1533 int used_pages;
1534
1535 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1536 used_pages = max(0, used_pages);
1537
82ce2c96
IE		 1538 /*
1539 * If we set the number of mmu pages to be smaller be than the
1540 * number of actived pages , we must to free some mmu pages before we
1541 * change the value
1542 */
1543
025dbbf3
MT		 1544 if (used_pages > kvm_nr_mmu_pages) {
1545 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1546 struct kvm_mmu_page *page;
1547
f05e70ac 1548 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1549 struct kvm_mmu_page, link);
1550 kvm_mmu_zap_page(kvm, page);
025dbbf3 1551 used_pages--;
82ce2c96 1552 }
f05e70ac 1553 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1554 }
1555 else
f05e70ac
ZX		 1556 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1557 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1558
f05e70ac 1559 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1560}
1561
f67a46f4 1562static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1563{
1564 unsigned index;
1565 struct hlist_head *bucket;
4db35314 1566 struct kvm_mmu_page *sp;
a436036b
AK		 1567 struct hlist_node *node, *n;
1568 int r;
1569
b8688d51 1570 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1571 r = 0;
1ae0a13d 1572 index = kvm_page_table_hashfn(gfn);
f05e70ac 1573 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1574 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1575 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1576 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1577 sp->role.word);
a436036b 1578 r = 1;
07385413
MT		 1579 if (kvm_mmu_zap_page(kvm, sp))
1580 n = bucket->first;
a436036b
AK		 1581 }
1582 return r;
cea0f0e7
AK		 1583}
1584
f67a46f4 1585static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1586{
4677a3b6
AK		 1587 unsigned index;
1588 struct hlist_head *bucket;
4db35314 1589 struct kvm_mmu_page *sp;
4677a3b6 1590 struct hlist_node *node, *nn;
97a0a01e 1591
4677a3b6
AK		 1592 index = kvm_page_table_hashfn(gfn);
1593 bucket = &kvm->arch.mmu_page_hash[index];
1594 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1595 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1596 && !sp->role.invalid) {
1597 pgprintk("%s: zap %lx %x\n",
1598 __func__, gfn, sp->role.word);
1599 kvm_mmu_zap_page(kvm, sp);
1600 }
97a0a01e
AK		 1601 }
1602}
1603
38c335f1 1604static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1605{
bc6678a3 1606 int slot = memslot_id(kvm, gfn);
4db35314 1607 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1608
291f26bc 1609 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1610}
1611
6844dec6
MT		 1612static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1613{
1614 int i;
1615 u64 *pt = sp->spt;
1616
1617 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1618 return;
1619
1620 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1621 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1622 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1623 }
1624}
1625
039576c0
AK		 1626struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1627{
72dc67a6
IE		 1628 struct page *page;
1629
ad312c7c 1630 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1631
1632 if (gpa == UNMAPPED_GVA)
1633 return NULL;
72dc67a6 1634
72dc67a6 1635 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1636
1637 return page;
039576c0
AK		 1638}
1639
74be52e3
SY		 1640/*
1641 * The function is based on mtrr_type_lookup() in
1642 * arch/x86/kernel/cpu/mtrr/generic.c
1643 */
1644static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1645 u64 start, u64 end)
1646{
1647 int i;
1648 u64 base, mask;
1649 u8 prev_match, curr_match;
1650 int num_var_ranges = KVM_NR_VAR_MTRR;
1651
1652 if (!mtrr_state->enabled)
1653 return 0xFF;
1654
1655 /* Make end inclusive end, instead of exclusive */
1656 end--;
1657
1658 /* Look in fixed ranges. Just return the type as per start */
1659 if (mtrr_state->have_fixed && (start < 0x100000)) {
1660 int idx;
1661
1662 if (start < 0x80000) {
1663 idx = 0;
1664 idx += (start >> 16);
1665 return mtrr_state->fixed_ranges[idx];
1666 } else if (start < 0xC0000) {
1667 idx = 1 * 8;
1668 idx += ((start - 0x80000) >> 14);
1669 return mtrr_state->fixed_ranges[idx];
1670 } else if (start < 0x1000000) {
1671 idx = 3 * 8;
1672 idx += ((start - 0xC0000) >> 12);
1673 return mtrr_state->fixed_ranges[idx];
1674 }
1675 }
1676
1677 /*
1678 * Look in variable ranges
1679 * Look of multiple ranges matching this address and pick type
1680 * as per MTRR precedence
1681 */
1682 if (!(mtrr_state->enabled & 2))
1683 return mtrr_state->def_type;
1684
1685 prev_match = 0xFF;
1686 for (i = 0; i < num_var_ranges; ++i) {
1687 unsigned short start_state, end_state;
1688
1689 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1690 continue;
1691
1692 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1693 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1694 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1695 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1696
1697 start_state = ((start & mask) == (base & mask));
1698 end_state = ((end & mask) == (base & mask));
1699 if (start_state != end_state)
1700 return 0xFE;
1701
1702 if ((start & mask) != (base & mask))
1703 continue;
1704
1705 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1706 if (prev_match == 0xFF) {
1707 prev_match = curr_match;
1708 continue;
1709 }
1710
1711 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1712 curr_match == MTRR_TYPE_UNCACHABLE)
1713 return MTRR_TYPE_UNCACHABLE;
1714
1715 if ((prev_match == MTRR_TYPE_WRBACK &&
1716 curr_match == MTRR_TYPE_WRTHROUGH) ||
1717 (prev_match == MTRR_TYPE_WRTHROUGH &&
1718 curr_match == MTRR_TYPE_WRBACK)) {
1719 prev_match = MTRR_TYPE_WRTHROUGH;
1720 curr_match = MTRR_TYPE_WRTHROUGH;
1721 }
1722
1723 if (prev_match != curr_match)
1724 return MTRR_TYPE_UNCACHABLE;
1725 }
1726
1727 if (prev_match != 0xFF)
1728 return prev_match;
1729
1730 return mtrr_state->def_type;
1731}
1732
4b12f0de 1733u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1734{
1735 u8 mtrr;
1736
1737 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1738 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1739 if (mtrr == 0xfe || mtrr == 0xff)
1740 mtrr = MTRR_TYPE_WRBACK;
1741 return mtrr;
1742}
4b12f0de 1743EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1744
4731d4c7
MT		 1745static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1746{
1747 unsigned index;
1748 struct hlist_head *bucket;
1749 struct kvm_mmu_page *s;
1750 struct hlist_node *node, *n;
1751
f691fe1d 1752 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1753 index = kvm_page_table_hashfn(sp->gfn);
1754 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1755 /* don't unsync if pagetable is shadowed with multiple roles */
1756 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1757 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1758 continue;
1759 if (s->role.word != sp->role.word)
1760 return 1;
1761 }
4731d4c7
MT		 1762 ++vcpu->kvm->stat.mmu_unsync;
1763 sp->unsync = 1;
6cffe8ca 1764
c2d0ee46 1765 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1766
4731d4c7
MT		 1767 mmu_convert_notrap(sp);
1768 return 0;
1769}
1770
1771static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1772 bool can_unsync)
1773{
1774 struct kvm_mmu_page *shadow;
1775
1776 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1777 if (shadow) {
1778 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1779 return 1;
1780 if (shadow->unsync)
1781 return 0;
582801a9 1782 if (can_unsync && oos_shadow)
4731d4c7
MT		 1783 return kvm_unsync_page(vcpu, shadow);
1784 return 1;
1785 }
1786 return 0;
1787}
1788
d555c333 1789static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1790 unsigned pte_access, int user_fault,
852e3c19 1791 int write_fault, int dirty, int level,
c2d0ee46 1792 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1793 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1794{
1795 u64 spte;
1e73f9dd 1796 int ret = 0;
64d4d521 1797
1c4f1fd6
AK		 1798 /*
1799 * We don't set the accessed bit, since we sometimes want to see
1800 * whether the guest actually used the pte (in order to detect
1801 * demand paging).
1802 */
7b52345e 1803 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1804 if (!speculative)
3201b5d9 1805 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1806 if (!dirty)
1807 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1808 if (pte_access & ACC_EXEC_MASK)
1809 spte |= shadow_x_mask;
1810 else
1811 spte |= shadow_nx_mask;
1c4f1fd6 1812 if (pte_access & ACC_USER_MASK)
7b52345e 1813 spte |= shadow_user_mask;
852e3c19 1814 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1815 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1816 if (tdp_enabled)
1817 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1818 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1819
1403283a
IE		 1820 if (reset_host_protection)
1821 spte |= SPTE_HOST_WRITEABLE;
1822
35149e21 1823 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1824
1825 if ((pte_access & ACC_WRITE_MASK)
1826 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1827
852e3c19
JR		 1828 if (level > PT_PAGE_TABLE_LEVEL &&
1829 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1830 ret = 1;
1831 spte = shadow_trap_nonpresent_pte;
1832 goto set_pte;
1833 }
1834
1c4f1fd6 1835 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1836
ecc5589f
MT		 1837 /*
1838 * Optimization: for pte sync, if spte was writable the hash
1839 * lookup is unnecessary (and expensive). Write protection
1840 * is responsibility of mmu_get_page / kvm_sync_page.
1841 * Same reasoning can be applied to dirty page accounting.
1842 */
8dae4445 1843 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1844 goto set_pte;
1845
4731d4c7 1846 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1847 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1848 __func__, gfn);
1e73f9dd 1849 ret = 1;
1c4f1fd6 1850 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1851 if (is_writable_pte(spte))
1c4f1fd6 1852 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1853 }
1854 }
1855
1c4f1fd6
AK		 1856 if (pte_access & ACC_WRITE_MASK)
1857 mark_page_dirty(vcpu->kvm, gfn);
1858
38187c83 1859set_pte:
d555c333 1860 __set_spte(sptep, spte);
1e73f9dd
MT		 1861 return ret;
1862}
1863
d555c333 1864static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1865 unsigned pt_access, unsigned pte_access,
1866 int user_fault, int write_fault, int dirty,
852e3c19 1867 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1868 pfn_t pfn, bool speculative,
1869 bool reset_host_protection)
1e73f9dd
MT		 1870{
1871 int was_rmapped = 0;
8dae4445 1872 int was_writable = is_writable_pte(*sptep);
53a27b39 1873 int rmap_count;
1e73f9dd
MT		 1874
1875 pgprintk("%s: spte %llx access %x write_fault %d"
1876 " user_fault %d gfn %lx\n",
d555c333 1877 __func__, *sptep, pt_access,
1e73f9dd
MT		 1878 write_fault, user_fault, gfn);
1879
d555c333 1880 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1881 /*
1882 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1883 * the parent of the now unreachable PTE.
1884 */
852e3c19
JR		 1885 if (level > PT_PAGE_TABLE_LEVEL &&
1886 !is_large_pte(*sptep)) {
1e73f9dd 1887 struct kvm_mmu_page *child;
d555c333 1888 u64 pte = *sptep;
1e73f9dd
MT		 1889
1890 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1891 mmu_page_remove_parent_pte(child, sptep);
1892 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1893 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1894 spte_to_pfn(*sptep), pfn);
1895 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1896 } else
1897 was_rmapped = 1;
1e73f9dd 1898 }
852e3c19 1899
d555c333 1900 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1901 dirty, level, gfn, pfn, speculative, true,
1902 reset_host_protection)) {
1e73f9dd
MT		 1903 if (write_fault)
1904 *ptwrite = 1;
a378b4e6
MT		 1905 kvm_x86_ops->tlb_flush(vcpu);
1906 }
1e73f9dd 1907
d555c333 1908 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1909 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1910 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1911 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1912 *sptep, sptep);
d555c333 1913 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1914 ++vcpu->kvm->stat.lpages;
1915
d555c333 1916 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1917 if (!was_rmapped) {
44ad9944 1918 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1919 kvm_release_pfn_clean(pfn);
53a27b39 1920 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1921 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1922 } else {
8dae4445 1923 if (was_writable)
35149e21 1924 kvm_release_pfn_dirty(pfn);
75e68e60 1925 else
35149e21 1926 kvm_release_pfn_clean(pfn);
1c4f1fd6 1927 }
1b7fcd32 1928 if (speculative) {
d555c333 1929 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1930 vcpu->arch.last_pte_gfn = gfn;
1931 }
1c4f1fd6
AK		 1932}
1933
6aa8b732
AK		 1934static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1935{
1936}
1937
9f652d21 1938static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1939 int level, gfn_t gfn, pfn_t pfn)
140754bc 1940{
9f652d21 1941 struct kvm_shadow_walk_iterator iterator;
140754bc 1942 struct kvm_mmu_page *sp;
9f652d21 1943 int pt_write = 0;
140754bc 1944 gfn_t pseudo_gfn;
6aa8b732 1945
9f652d21 1946 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1947 if (iterator.level == level) {
9f652d21
AK		 1948 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1949 0, write, 1, &pt_write,
1403283a 1950 level, gfn, pfn, false, true);
9f652d21
AK		 1951 ++vcpu->stat.pf_fixed;
1952 break;
6aa8b732
AK		 1953 }
1954
9f652d21
AK		 1955 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1956 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1957 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1958 iterator.level - 1,
1959 1, ACC_ALL, iterator.sptep);
1960 if (!sp) {
1961 pgprintk("nonpaging_map: ENOMEM\n");
1962 kvm_release_pfn_clean(pfn);
1963 return -ENOMEM;
1964 }
140754bc 1965
d555c333
AK		 1966 __set_spte(iterator.sptep,
1967 __pa(sp->spt)
1968 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1969 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1970 }
1971 }
1972 return pt_write;
6aa8b732
AK		 1973}
1974
10589a46
MT		 1975static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1976{
1977 int r;
852e3c19 1978 int level;
35149e21 1979 pfn_t pfn;
e930bffe 1980 unsigned long mmu_seq;
aaee2c94 1981
852e3c19
JR		 1982 level = mapping_level(vcpu, gfn);
1983
1984 /*
1985 * This path builds a PAE pagetable - so we can map 2mb pages at
1986 * maximum. Therefore check if the level is larger than that.
1987 */
1988 if (level > PT_DIRECTORY_LEVEL)
1989 level = PT_DIRECTORY_LEVEL;
1990
1991 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 1992
e930bffe 1993 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1994 smp_rmb();
35149e21 1995 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1996
d196e343 1997 /* mmio */
35149e21
AL		 1998 if (is_error_pfn(pfn)) {
1999 kvm_release_pfn_clean(pfn);
d196e343
AK		 2000 return 1;
2001 }
2002
aaee2c94 2003 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2004 if (mmu_notifier_retry(vcpu, mmu_seq))
2005 goto out_unlock;
eb787d10 2006 kvm_mmu_free_some_pages(vcpu);
852e3c19 2007 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2008 spin_unlock(&vcpu->kvm->mmu_lock);
2009
aaee2c94 2010
10589a46 2011 return r;
e930bffe
AA		 2012
2013out_unlock:
2014 spin_unlock(&vcpu->kvm->mmu_lock);
2015 kvm_release_pfn_clean(pfn);
2016 return 0;
10589a46
MT		 2017}
2018
2019
17ac10ad
AK		 2020static void mmu_free_roots(struct kvm_vcpu *vcpu)
2021{
2022 int i;
4db35314 2023 struct kvm_mmu_page *sp;
17ac10ad 2024
ad312c7c 2025 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2026 return;
aaee2c94 2027 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2028 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2029 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2030
4db35314
AK		 2031 sp = page_header(root);
2032 --sp->root_count;
2e53d63a
MT		 2033 if (!sp->root_count && sp->role.invalid)
2034 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2035 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2036 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2037 return;
2038 }
17ac10ad 2039 for (i = 0; i < 4; ++i) {
ad312c7c 2040 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2041
417726a3 2042 if (root) {
417726a3 2043 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2044 sp = page_header(root);
2045 --sp->root_count;
2e53d63a
MT		 2046 if (!sp->root_count && sp->role.invalid)
2047 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2048 }
ad312c7c 2049 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2050 }
aaee2c94 2051 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2052 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2053}
2054
8986ecc0
MT		 2055static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2056{
2057 int ret = 0;
2058
2059 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2060 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2061 ret = 1;
2062 }
2063
2064 return ret;
2065}
2066
2067static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2068{
2069 int i;
cea0f0e7 2070 gfn_t root_gfn;
4db35314 2071 struct kvm_mmu_page *sp;
f6e2c02b 2072 int direct = 0;
6de4f3ad 2073 u64 pdptr;
3bb65a22 2074
ad312c7c 2075 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2076
ad312c7c
ZX		 2077 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2078 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2079
2080 ASSERT(!VALID_PAGE(root));
fb72d167 2081 if (tdp_enabled)
f6e2c02b 2082 direct = 1;
8986ecc0
MT		 2083 if (mmu_check_root(vcpu, root_gfn))
2084 return 1;
4db35314 2085 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2086 PT64_ROOT_LEVEL, direct,
fb72d167 2087 ACC_ALL, NULL);
4db35314
AK		 2088 root = __pa(sp->spt);
2089 ++sp->root_count;
ad312c7c 2090 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2091 return 0;
17ac10ad 2092 }
f6e2c02b 2093 direct = !is_paging(vcpu);
fb72d167 2094 if (tdp_enabled)
f6e2c02b 2095 direct = 1;
17ac10ad 2096 for (i = 0; i < 4; ++i) {
ad312c7c 2097 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2098
2099 ASSERT(!VALID_PAGE(root));
ad312c7c 2100 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2101 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2102 if (!is_present_gpte(pdptr)) {
ad312c7c 2103 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2104 continue;
2105 }
6de4f3ad 2106 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2107 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2108 root_gfn = 0;
8986ecc0
MT		 2109 if (mmu_check_root(vcpu, root_gfn))
2110 return 1;
4db35314 2111 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2112 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2113 ACC_ALL, NULL);
4db35314
AK		 2114 root = __pa(sp->spt);
2115 ++sp->root_count;
ad312c7c 2116 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2117 }
ad312c7c 2118 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2119 return 0;
17ac10ad
AK		 2120}
2121
0ba73cda
MT		 2122static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2123{
2124 int i;
2125 struct kvm_mmu_page *sp;
2126
2127 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2128 return;
2129 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2130 hpa_t root = vcpu->arch.mmu.root_hpa;
2131 sp = page_header(root);
2132 mmu_sync_children(vcpu, sp);
2133 return;
2134 }
2135 for (i = 0; i < 4; ++i) {
2136 hpa_t root = vcpu->arch.mmu.pae_root[i];
2137
8986ecc0 2138 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2139 root &= PT64_BASE_ADDR_MASK;
2140 sp = page_header(root);
2141 mmu_sync_children(vcpu, sp);
2142 }
2143 }
2144}
2145
2146void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2147{
2148 spin_lock(&vcpu->kvm->mmu_lock);
2149 mmu_sync_roots(vcpu);
6cffe8ca 2150 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2151}
2152
6aa8b732
AK		 2153static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2154{
2155 return vaddr;
2156}
2157
2158static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2159 u32 error_code)
6aa8b732 2160{
e833240f 2161 gfn_t gfn;
e2dec939 2162 int r;
6aa8b732 2163
b8688d51 2164 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2165 r = mmu_topup_memory_caches(vcpu);
2166 if (r)
2167 return r;
714b93da 2168
6aa8b732 2169 ASSERT(vcpu);
ad312c7c 2170 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2171
e833240f 2172 gfn = gva >> PAGE_SHIFT;
6aa8b732 2173
e833240f
AK		 2174 return nonpaging_map(vcpu, gva & PAGE_MASK,
2175 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2176}
2177
fb72d167
JR		 2178static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2179 u32 error_code)
2180{
35149e21 2181 pfn_t pfn;
fb72d167 2182 int r;
852e3c19 2183 int level;
05da4558 2184 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2185 unsigned long mmu_seq;
fb72d167
JR		 2186
2187 ASSERT(vcpu);
2188 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2189
2190 r = mmu_topup_memory_caches(vcpu);
2191 if (r)
2192 return r;
2193
852e3c19
JR		 2194 level = mapping_level(vcpu, gfn);
2195
2196 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2197
e930bffe 2198 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2199 smp_rmb();
35149e21 2200 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2201 if (is_error_pfn(pfn)) {
2202 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2203 return 1;
2204 }
2205 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2206 if (mmu_notifier_retry(vcpu, mmu_seq))
2207 goto out_unlock;
fb72d167
JR		 2208 kvm_mmu_free_some_pages(vcpu);
2209 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2210 level, gfn, pfn);
fb72d167 2211 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2212
2213 return r;
e930bffe
AA		 2214
2215out_unlock:
2216 spin_unlock(&vcpu->kvm->mmu_lock);
2217 kvm_release_pfn_clean(pfn);
2218 return 0;
fb72d167
JR		 2219}
2220
6aa8b732
AK		 2221static void nonpaging_free(struct kvm_vcpu *vcpu)
2222{
17ac10ad 2223 mmu_free_roots(vcpu);
6aa8b732
AK		 2224}
2225
2226static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2227{
ad312c7c 2228 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2229
2230 context->new_cr3 = nonpaging_new_cr3;
2231 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2232 context->gva_to_gpa = nonpaging_gva_to_gpa;
2233 context->free = nonpaging_free;
c7addb90 2234 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2235 context->sync_page = nonpaging_sync_page;
a7052897 2236 context->invlpg = nonpaging_invlpg;
cea0f0e7 2237 context->root_level = 0;
6aa8b732 2238 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2239 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2240 return 0;
2241}
2242
d835dfec 2243void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2244{
1165f5fe 2245 ++vcpu->stat.tlb_flush;
cbdd1bea 2246 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2247}
2248
2249static void paging_new_cr3(struct kvm_vcpu *vcpu)
2250{
b8688d51 2251 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2252 mmu_free_roots(vcpu);
6aa8b732
AK		 2253}
2254
6aa8b732
AK		 2255static void inject_page_fault(struct kvm_vcpu *vcpu,
2256 u64 addr,
2257 u32 err_code)
2258{
c3c91fee 2259 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2260}
2261
6aa8b732
AK		 2262static void paging_free(struct kvm_vcpu *vcpu)
2263{
2264 nonpaging_free(vcpu);
2265}
2266
82725b20
DE		 2267static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2268{
2269 int bit7;
2270
2271 bit7 = (gpte >> 7) & 1;
2272 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2273}
2274
6aa8b732
AK		 2275#define PTTYPE 64
2276#include "paging_tmpl.h"
2277#undef PTTYPE
2278
2279#define PTTYPE 32
2280#include "paging_tmpl.h"
2281#undef PTTYPE
2282
82725b20
DE		 2283static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2284{
2285 struct kvm_mmu *context = &vcpu->arch.mmu;
2286 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2287 u64 exb_bit_rsvd = 0;
2288
2289 if (!is_nx(vcpu))
2290 exb_bit_rsvd = rsvd_bits(63, 63);
2291 switch (level) {
2292 case PT32_ROOT_LEVEL:
2293 /* no rsvd bits for 2 level 4K page table entries */
2294 context->rsvd_bits_mask[0][1] = 0;
2295 context->rsvd_bits_mask[0][0] = 0;
2296 if (is_cpuid_PSE36())
2297 /* 36bits PSE 4MB page */
2298 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2299 else
2300 /* 32 bits PSE 4MB page */
2301 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2302 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2303 break;
2304 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2305 context->rsvd_bits_mask[0][2] =
2306 rsvd_bits(maxphyaddr, 63) |
2307 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2308 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2309 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2310 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2311 rsvd_bits(maxphyaddr, 62); /* PTE */
2312 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2313 rsvd_bits(maxphyaddr, 62) |
2314 rsvd_bits(13, 20); /* large page */
29a4b933 2315 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2316 break;
2317 case PT64_ROOT_LEVEL:
2318 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2319 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2320 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2321 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2322 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2323 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2324 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2325 rsvd_bits(maxphyaddr, 51);
2326 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2327 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2328 rsvd_bits(maxphyaddr, 51) |
2329 rsvd_bits(13, 29);
82725b20 2330 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2331 rsvd_bits(maxphyaddr, 51) |
2332 rsvd_bits(13, 20); /* large page */
29a4b933 2333 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2334 break;
2335 }
2336}
2337
17ac10ad 2338static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2339{
ad312c7c 2340 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2341
2342 ASSERT(is_pae(vcpu));
2343 context->new_cr3 = paging_new_cr3;
2344 context->page_fault = paging64_page_fault;
6aa8b732 2345 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2346 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2347 context->sync_page = paging64_sync_page;
a7052897 2348 context->invlpg = paging64_invlpg;
6aa8b732 2349 context->free = paging_free;
17ac10ad
AK		 2350 context->root_level = level;
2351 context->shadow_root_level = level;
17c3ba9d 2352 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2353 return 0;
2354}
2355
17ac10ad
AK		 2356static int paging64_init_context(struct kvm_vcpu *vcpu)
2357{
82725b20 2358 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2359 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2360}
2361
6aa8b732
AK		 2362static int paging32_init_context(struct kvm_vcpu *vcpu)
2363{
ad312c7c 2364 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2365
82725b20 2366 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2367 context->new_cr3 = paging_new_cr3;
2368 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2369 context->gva_to_gpa = paging32_gva_to_gpa;
2370 context->free = paging_free;
c7addb90 2371 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2372 context->sync_page = paging32_sync_page;
a7052897 2373 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2374 context->root_level = PT32_ROOT_LEVEL;
2375 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2376 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2377 return 0;
2378}
2379
2380static int paging32E_init_context(struct kvm_vcpu *vcpu)
2381{
82725b20 2382 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2383 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2384}
2385
fb72d167
JR		 2386static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2387{
2388 struct kvm_mmu *context = &vcpu->arch.mmu;
2389
2390 context->new_cr3 = nonpaging_new_cr3;
2391 context->page_fault = tdp_page_fault;
2392 context->free = nonpaging_free;
2393 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2394 context->sync_page = nonpaging_sync_page;
a7052897 2395 context->invlpg = nonpaging_invlpg;
67253af5 2396 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2397 context->root_hpa = INVALID_PAGE;
2398
2399 if (!is_paging(vcpu)) {
2400 context->gva_to_gpa = nonpaging_gva_to_gpa;
2401 context->root_level = 0;
2402 } else if (is_long_mode(vcpu)) {
82725b20 2403 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2404 context->gva_to_gpa = paging64_gva_to_gpa;
2405 context->root_level = PT64_ROOT_LEVEL;
2406 } else if (is_pae(vcpu)) {
82725b20 2407 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2408 context->gva_to_gpa = paging64_gva_to_gpa;
2409 context->root_level = PT32E_ROOT_LEVEL;
2410 } else {
82725b20 2411 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2412 context->gva_to_gpa = paging32_gva_to_gpa;
2413 context->root_level = PT32_ROOT_LEVEL;
2414 }
2415
2416 return 0;
2417}
2418
2419static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2420{
a770f6f2
AK		 2421 int r;
2422
6aa8b732 2423 ASSERT(vcpu);
ad312c7c 2424 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2425
2426 if (!is_paging(vcpu))
a770f6f2 2427 r = nonpaging_init_context(vcpu);
a9058ecd 2428 else if (is_long_mode(vcpu))
a770f6f2 2429 r = paging64_init_context(vcpu);
6aa8b732 2430 else if (is_pae(vcpu))
a770f6f2 2431 r = paging32E_init_context(vcpu);
6aa8b732 2432 else
a770f6f2
AK		 2433 r = paging32_init_context(vcpu);
2434
2435 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2436
2437 return r;
6aa8b732
AK		 2438}
2439
fb72d167
JR		 2440static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2441{
35149e21
AL		 2442 vcpu->arch.update_pte.pfn = bad_pfn;
2443
fb72d167
JR		 2444 if (tdp_enabled)
2445 return init_kvm_tdp_mmu(vcpu);
2446 else
2447 return init_kvm_softmmu(vcpu);
2448}
2449
6aa8b732
AK		 2450static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2451{
2452 ASSERT(vcpu);
ad312c7c
ZX		 2453 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2454 vcpu->arch.mmu.free(vcpu);
2455 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2456 }
2457}
2458
2459int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2460{
2461 destroy_kvm_mmu(vcpu);
2462 return init_kvm_mmu(vcpu);
2463}
8668a3c4 2464EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2465
2466int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2467{
714b93da
AK		 2468 int r;
2469
e2dec939 2470 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2471 if (r)
2472 goto out;
aaee2c94 2473 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2474 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2475 r = mmu_alloc_roots(vcpu);
0ba73cda 2476 mmu_sync_roots(vcpu);
aaee2c94 2477 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2478 if (r)
2479 goto out;
3662cb1c 2480 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2481 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2482out:
2483 return r;
6aa8b732 2484}
17c3ba9d
AK		 2485EXPORT_SYMBOL_GPL(kvm_mmu_load);
2486
2487void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2488{
2489 mmu_free_roots(vcpu);
2490}
6aa8b732 2491
09072daf 2492static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2493 struct kvm_mmu_page *sp,
ac1b714e
AK		 2494 u64 *spte)
2495{
2496 u64 pte;
2497 struct kvm_mmu_page *child;
2498
2499 pte = *spte;
c7addb90 2500 if (is_shadow_present_pte(pte)) {
776e6633 2501 if (is_last_spte(pte, sp->role.level))
290fc38d 2502 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2503 else {
2504 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2505 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2506 }
2507 }
d555c333 2508 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2509 if (is_large_pte(pte))
2510 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2511}
2512
0028425f 2513static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2514 struct kvm_mmu_page *sp,
0028425f 2515 u64 *spte,
489f1d65 2516 const void *new)
0028425f 2517{
30945387 2518 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2519 ++vcpu->kvm->stat.mmu_pde_zapped;
2520 return;
30945387 2521 }
0028425f 2522
4cee5764 2523 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2524 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2525 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2526 else
489f1d65 2527 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2528}
2529
79539cec
AK		 2530static bool need_remote_flush(u64 old, u64 new)
2531{
2532 if (!is_shadow_present_pte(old))
2533 return false;
2534 if (!is_shadow_present_pte(new))
2535 return true;
2536 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2537 return true;
2538 old ^= PT64_NX_MASK;
2539 new ^= PT64_NX_MASK;
2540 return (old & ~new & PT64_PERM_MASK) != 0;
2541}
2542
2543static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2544{
2545 if (need_remote_flush(old, new))
2546 kvm_flush_remote_tlbs(vcpu->kvm);
2547 else
2548 kvm_mmu_flush_tlb(vcpu);
2549}
2550
12b7d28f
AK		 2551static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2552{
ad312c7c 2553 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2554
7b52345e 2555 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2556}
2557
d7824fff
AK		 2558static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2559 const u8 *new, int bytes)
2560{
2561 gfn_t gfn;
2562 int r;
2563 u64 gpte = 0;
35149e21 2564 pfn_t pfn;
d7824fff
AK		 2565
2566 if (bytes != 4 && bytes != 8)
2567 return;
2568
2569 /*
2570 * Assume that the pte write on a page table of the same type
2571 * as the current vcpu paging mode. This is nearly always true
2572 * (might be false while changing modes). Note it is verified later
2573 * by update_pte().
2574 */
2575 if (is_pae(vcpu)) {
2576 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2577 if ((bytes == 4) && (gpa % 4 == 0)) {
2578 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2579 if (r)
2580 return;
2581 memcpy((void *)&gpte + (gpa % 8), new, 4);
2582 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2583 memcpy((void *)&gpte, new, 8);
2584 }
2585 } else {
2586 if ((bytes == 4) && (gpa % 4 == 0))
2587 memcpy((void *)&gpte, new, 4);
2588 }
43a3795a 2589 if (!is_present_gpte(gpte))
d7824fff
AK		 2590 return;
2591 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2592
e930bffe 2593 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2594 smp_rmb();
35149e21 2595 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2596
35149e21
AL		 2597 if (is_error_pfn(pfn)) {
2598 kvm_release_pfn_clean(pfn);
d196e343
AK		 2599 return;
2600 }
d7824fff 2601 vcpu->arch.update_pte.gfn = gfn;
35149e21 2602 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2603}
2604
1b7fcd32
AK		 2605static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2606{
2607 u64 *spte = vcpu->arch.last_pte_updated;
2608
2609 if (spte
2610 && vcpu->arch.last_pte_gfn == gfn
2611 && shadow_accessed_mask
2612 && !(*spte & shadow_accessed_mask)
2613 && is_shadow_present_pte(*spte))
2614 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2615}
2616
09072daf 2617void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2618 const u8 *new, int bytes,
2619 bool guest_initiated)
da4a00f0 2620{
9b7a0325 2621 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2622 struct kvm_mmu_page *sp;
0e7bc4b9 2623 struct hlist_node *node, *n;
9b7a0325
AK		 2624 struct hlist_head *bucket;
2625 unsigned index;
489f1d65 2626 u64 entry, gentry;
9b7a0325 2627 u64 *spte;
9b7a0325 2628 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2629 unsigned pte_size;
9b7a0325 2630 unsigned page_offset;
0e7bc4b9 2631 unsigned misaligned;
fce0657f 2632 unsigned quadrant;
9b7a0325 2633 int level;
86a5ba02 2634 int flooded = 0;
ac1b714e 2635 int npte;
489f1d65 2636 int r;
9b7a0325 2637
b8688d51 2638 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2639 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2640 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2641 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2642 kvm_mmu_free_some_pages(vcpu);
4cee5764 2643 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2644 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2645 if (guest_initiated) {
2646 if (gfn == vcpu->arch.last_pt_write_gfn
2647 && !last_updated_pte_accessed(vcpu)) {
2648 ++vcpu->arch.last_pt_write_count;
2649 if (vcpu->arch.last_pt_write_count >= 3)
2650 flooded = 1;
2651 } else {
2652 vcpu->arch.last_pt_write_gfn = gfn;
2653 vcpu->arch.last_pt_write_count = 1;
2654 vcpu->arch.last_pte_updated = NULL;
2655 }
86a5ba02 2656 }
1ae0a13d 2657 index = kvm_page_table_hashfn(gfn);
f05e70ac 2658 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2659 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2660 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2661 continue;
4db35314 2662 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2663 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2664 misaligned |= bytes < 4;
86a5ba02 2665 if (misaligned || flooded) {
0e7bc4b9
AK		 2666 /*
2667 * Misaligned accesses are too much trouble to fix
2668 * up; also, they usually indicate a page is not used
2669 * as a page table.
86a5ba02
AK		 2670 *
2671 * If we're seeing too many writes to a page,
2672 * it may no longer be a page table, or we may be
2673 * forking, in which case it is better to unmap the
2674 * page.
0e7bc4b9
AK		 2675 */
2676 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2677 gpa, bytes, sp->role.word);
07385413
MT		 2678 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2679 n = bucket->first;
4cee5764 2680 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2681 continue;
2682 }
9b7a0325 2683 page_offset = offset;
4db35314 2684 level = sp->role.level;
ac1b714e 2685 npte = 1;
4db35314 2686 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2687 page_offset <<= 1; /* 32->64 */
2688 /*
2689 * A 32-bit pde maps 4MB while the shadow pdes map
2690 * only 2MB. So we need to double the offset again
2691 * and zap two pdes instead of one.
2692 */
2693 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2694 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2695 page_offset <<= 1;
2696 npte = 2;
2697 }
fce0657f 2698 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2699 page_offset &= ~PAGE_MASK;
4db35314 2700 if (quadrant != sp->role.quadrant)
fce0657f 2701 continue;
9b7a0325 2702 }
4db35314 2703 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2704 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2705 gentry = 0;
2706 r = kvm_read_guest_atomic(vcpu->kvm,
2707 gpa & ~(u64)(pte_size - 1),
2708 &gentry, pte_size);
2709 new = (const void *)&gentry;
2710 if (r < 0)
2711 new = NULL;
2712 }
ac1b714e 2713 while (npte--) {
79539cec 2714 entry = *spte;
4db35314 2715 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2716 if (new)
2717 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2718 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2719 ++spte;
9b7a0325 2720 }
9b7a0325 2721 }
c7addb90 2722 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2723 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2724 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2725 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2726 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2727 }
da4a00f0
AK		 2728}
2729
a436036b
AK		 2730int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2731{
10589a46
MT		 2732 gpa_t gpa;
2733 int r;
a436036b 2734
60f24784
AK		 2735 if (tdp_enabled)
2736 return 0;
2737
10589a46 2738 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2739
aaee2c94 2740 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2741 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2742 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2743 return r;
a436036b 2744}
577bdc49 2745EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2746
22d95b12 2747void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2748{
3b80fffe
IE		 2749 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2750 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2751 struct kvm_mmu_page *sp;
ebeace86 2752
f05e70ac 2753 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2754 struct kvm_mmu_page, link);
2755 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2756 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2757 }
2758}
ebeace86 2759
3067714c
AK		 2760int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2761{
2762 int r;
2763 enum emulation_result er;
2764
ad312c7c 2765 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2766 if (r < 0)
2767 goto out;
2768
2769 if (!r) {
2770 r = 1;
2771 goto out;
2772 }
2773
b733bfb5
AK		 2774 r = mmu_topup_memory_caches(vcpu);
2775 if (r)
2776 goto out;
2777
851ba692 2778 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2779
2780 switch (er) {
2781 case EMULATE_DONE:
2782 return 1;
2783 case EMULATE_DO_MMIO:
2784 ++vcpu->stat.mmio_exits;
2785 return 0;
2786 case EMULATE_FAIL:
3f5d18a9
AK		 2787 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2788 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2789 vcpu->run->internal.ndata = 0;
3f5d18a9 2790 return 0;
3067714c
AK		 2791 default:
2792 BUG();
2793 }
2794out:
3067714c
AK		 2795 return r;
2796}
2797EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2798
a7052897
MT		 2799void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2800{
a7052897 2801 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2802 kvm_mmu_flush_tlb(vcpu);
2803 ++vcpu->stat.invlpg;
2804}
2805EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2806
18552672
JR		 2807void kvm_enable_tdp(void)
2808{
2809 tdp_enabled = true;
2810}
2811EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2812
5f4cb662
JR		 2813void kvm_disable_tdp(void)
2814{
2815 tdp_enabled = false;
2816}
2817EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2818
6aa8b732
AK		 2819static void free_mmu_pages(struct kvm_vcpu *vcpu)
2820{
ad312c7c 2821 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2822}
2823
2824static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2825{
17ac10ad 2826 struct page *page;
6aa8b732
AK		 2827 int i;
2828
2829 ASSERT(vcpu);
2830
17ac10ad
AK		 2831 /*
2832 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2833 * Therefore we need to allocate shadow page tables in the first
2834 * 4GB of memory, which happens to fit the DMA32 zone.
2835 */
2836 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2837 if (!page)
d7fa6ab2
WY		 2838 return -ENOMEM;
2839
ad312c7c 2840 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2841 for (i = 0; i < 4; ++i)
ad312c7c 2842 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2843
6aa8b732 2844 return 0;
6aa8b732
AK		 2845}
2846
8018c27b 2847int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2848{
6aa8b732 2849 ASSERT(vcpu);
ad312c7c 2850 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2851
8018c27b
IM		 2852 return alloc_mmu_pages(vcpu);
2853}
6aa8b732 2854
8018c27b
IM		 2855int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2856{
2857 ASSERT(vcpu);
ad312c7c 2858 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2859
8018c27b 2860 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2861}
2862
2863void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2864{
2865 ASSERT(vcpu);
2866
2867 destroy_kvm_mmu(vcpu);
2868 free_mmu_pages(vcpu);
714b93da 2869 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2870}
2871
90cb0529 2872void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2873{
4db35314 2874 struct kvm_mmu_page *sp;
6aa8b732 2875
f05e70ac 2876 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2877 int i;
2878 u64 *pt;
2879
291f26bc 2880 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2881 continue;
2882
4db35314 2883 pt = sp->spt;
6aa8b732
AK		 2884 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2885 /* avoid RMW */
9647c14c 2886 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2887 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2888 }
171d595d 2889 kvm_flush_remote_tlbs(kvm);
6aa8b732 2890}
37a7d8b0 2891
90cb0529 2892void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2893{
4db35314 2894 struct kvm_mmu_page *sp, *node;
e0fa826f 2895
aaee2c94 2896 spin_lock(&kvm->mmu_lock);
f05e70ac 2897 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2898 if (kvm_mmu_zap_page(kvm, sp))
2899 node = container_of(kvm->arch.active_mmu_pages.next,
2900 struct kvm_mmu_page, link);
aaee2c94 2901 spin_unlock(&kvm->mmu_lock);
e0fa826f 2902
90cb0529 2903 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2904}
2905
8b2cf73c 2906static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2907{
2908 struct kvm_mmu_page *page;
2909
2910 page = container_of(kvm->arch.active_mmu_pages.prev,
2911 struct kvm_mmu_page, link);
2912 kvm_mmu_zap_page(kvm, page);
2913}
2914
2915static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2916{
2917 struct kvm *kvm;
2918 struct kvm *kvm_freed = NULL;
2919 int cache_count = 0;
2920
2921 spin_lock(&kvm_lock);
2922
2923 list_for_each_entry(kvm, &vm_list, vm_list) {
f656ce01 2924 int npages, idx;
3ee16c81 2925
f656ce01 2926 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2927 spin_lock(&kvm->mmu_lock);
2928 npages = kvm->arch.n_alloc_mmu_pages -
2929 kvm->arch.n_free_mmu_pages;
2930 cache_count += npages;
2931 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2932 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2933 cache_count--;
2934 kvm_freed = kvm;
2935 }
2936 nr_to_scan--;
2937
2938 spin_unlock(&kvm->mmu_lock);
f656ce01 2939 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2940 }
2941 if (kvm_freed)
2942 list_move_tail(&kvm_freed->vm_list, &vm_list);
2943
2944 spin_unlock(&kvm_lock);
2945
2946 return cache_count;
2947}
2948
2949static struct shrinker mmu_shrinker = {
2950 .shrink = mmu_shrink,
2951 .seeks = DEFAULT_SEEKS * 10,
2952};
2953
2ddfd20e 2954static void mmu_destroy_caches(void)
b5a33a75
AK		 2955{
2956 if (pte_chain_cache)
2957 kmem_cache_destroy(pte_chain_cache);
2958 if (rmap_desc_cache)
2959 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2960 if (mmu_page_header_cache)
2961 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2962}
2963
3ee16c81
IE		 2964void kvm_mmu_module_exit(void)
2965{
2966 mmu_destroy_caches();
2967 unregister_shrinker(&mmu_shrinker);
2968}
2969
b5a33a75
AK		 2970int kvm_mmu_module_init(void)
2971{
2972 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2973 sizeof(struct kvm_pte_chain),
20c2df83 2974 0, 0, NULL);
b5a33a75
AK		 2975 if (!pte_chain_cache)
2976 goto nomem;
2977 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2978 sizeof(struct kvm_rmap_desc),
20c2df83 2979 0, 0, NULL);
b5a33a75
AK		 2980 if (!rmap_desc_cache)
2981 goto nomem;
2982
d3d25b04
AK		 2983 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2984 sizeof(struct kvm_mmu_page),
20c2df83 2985 0, 0, NULL);
d3d25b04
AK		 2986 if (!mmu_page_header_cache)
2987 goto nomem;
2988
3ee16c81
IE		 2989 register_shrinker(&mmu_shrinker);
2990
b5a33a75
AK		 2991 return 0;
2992
2993nomem:
3ee16c81 2994 mmu_destroy_caches();
b5a33a75
AK		 2995 return -ENOMEM;
2996}
2997
3ad82a7e
ZX		 2998/*
2999 * Caculate mmu pages needed for kvm.
3000 */
3001unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3002{
3003 int i;
3004 unsigned int nr_mmu_pages;
3005 unsigned int nr_pages = 0;
bc6678a3 3006 struct kvm_memslots *slots;
3ad82a7e 3007
bc6678a3
MT		 3008 slots = rcu_dereference(kvm->memslots);
3009 for (i = 0; i < slots->nmemslots; i++)
3010 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3011
3012 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3013 nr_mmu_pages = max(nr_mmu_pages,
3014 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3015
3016 return nr_mmu_pages;
3017}
3018
2f333bcb
MT		 3019static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3020 unsigned len)
3021{
3022 if (len > buffer->len)
3023 return NULL;
3024 return buffer->ptr;
3025}
3026
3027static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3028 unsigned len)
3029{
3030 void *ret;
3031
3032 ret = pv_mmu_peek_buffer(buffer, len);
3033 if (!ret)
3034 return ret;
3035 buffer->ptr += len;
3036 buffer->len -= len;
3037 buffer->processed += len;
3038 return ret;
3039}
3040
3041static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3042 gpa_t addr, gpa_t value)
3043{
3044 int bytes = 8;
3045 int r;
3046
3047 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3048 bytes = 4;
3049
3050 r = mmu_topup_memory_caches(vcpu);
3051 if (r)
3052 return r;
3053
3200f405 3054 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3055 return -EFAULT;
3056
3057 return 1;
3058}
3059
3060static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3061{
a8cd0244 3062 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3063 return 1;
3064}
3065
3066static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3067{
3068 spin_lock(&vcpu->kvm->mmu_lock);
3069 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3070 spin_unlock(&vcpu->kvm->mmu_lock);
3071 return 1;
3072}
3073
3074static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3075 struct kvm_pv_mmu_op_buffer *buffer)
3076{
3077 struct kvm_mmu_op_header *header;
3078
3079 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3080 if (!header)
3081 return 0;
3082 switch (header->op) {
3083 case KVM_MMU_OP_WRITE_PTE: {
3084 struct kvm_mmu_op_write_pte *wpte;
3085
3086 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3087 if (!wpte)
3088 return 0;
3089 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3090 wpte->pte_val);
3091 }
3092 case KVM_MMU_OP_FLUSH_TLB: {
3093 struct kvm_mmu_op_flush_tlb *ftlb;
3094
3095 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3096 if (!ftlb)
3097 return 0;
3098 return kvm_pv_mmu_flush_tlb(vcpu);
3099 }
3100 case KVM_MMU_OP_RELEASE_PT: {
3101 struct kvm_mmu_op_release_pt *rpt;
3102
3103 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3104 if (!rpt)
3105 return 0;
3106 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3107 }
3108 default: return 0;
3109 }
3110}
3111
3112int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3113 gpa_t addr, unsigned long *ret)
3114{
3115 int r;
6ad18fba 3116 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3117
6ad18fba
DH		 3118 buffer->ptr = buffer->buf;
3119 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3120 buffer->processed = 0;
2f333bcb 3121
6ad18fba 3122 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3123 if (r)
3124 goto out;
3125
6ad18fba
DH		 3126 while (buffer->len) {
3127 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3128 if (r < 0)
3129 goto out;
3130 if (r == 0)
3131 break;
3132 }
3133
3134 r = 1;
3135out:
6ad18fba 3136 *ret = buffer->processed;
2f333bcb
MT		 3137 return r;
3138}
3139
94d8b056
MT		 3140int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3141{
3142 struct kvm_shadow_walk_iterator iterator;
3143 int nr_sptes = 0;
3144
3145 spin_lock(&vcpu->kvm->mmu_lock);
3146 for_each_shadow_entry(vcpu, addr, iterator) {
3147 sptes[iterator.level-1] = *iterator.sptep;
3148 nr_sptes++;
3149 if (!is_shadow_present_pte(*iterator.sptep))
3150 break;
3151 }
3152 spin_unlock(&vcpu->kvm->mmu_lock);
3153
3154 return nr_sptes;
3155}
3156EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3157
37a7d8b0
AK		 3158#ifdef AUDIT
3159
3160static const char *audit_msg;
3161
3162static gva_t canonicalize(gva_t gva)
3163{
3164#ifdef CONFIG_X86_64
3165 gva = (long long)(gva << 16) >> 16;
3166#endif
3167 return gva;
3168}
3169
08a3732b
MT		 3170
3171typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3172 u64 *sptep);
3173
3174static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3175 inspect_spte_fn fn)
3176{
3177 int i;
3178
3179 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3180 u64 ent = sp->spt[i];
3181
3182 if (is_shadow_present_pte(ent)) {
2920d728 3183 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3184 struct kvm_mmu_page *child;
3185 child = page_header(ent & PT64_BASE_ADDR_MASK);
3186 __mmu_spte_walk(kvm, child, fn);
2920d728 3187 } else
08a3732b
MT		 3188 fn(kvm, sp, &sp->spt[i]);
3189 }
3190 }
3191}
3192
3193static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3194{
3195 int i;
3196 struct kvm_mmu_page *sp;
3197
3198 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3199 return;
3200 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3201 hpa_t root = vcpu->arch.mmu.root_hpa;
3202 sp = page_header(root);
3203 __mmu_spte_walk(vcpu->kvm, sp, fn);
3204 return;
3205 }
3206 for (i = 0; i < 4; ++i) {
3207 hpa_t root = vcpu->arch.mmu.pae_root[i];
3208
3209 if (root && VALID_PAGE(root)) {
3210 root &= PT64_BASE_ADDR_MASK;
3211 sp = page_header(root);
3212 __mmu_spte_walk(vcpu->kvm, sp, fn);
3213 }
3214 }
3215 return;
3216}
3217
37a7d8b0
AK		 3218static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3219 gva_t va, int level)
3220{
3221 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3222 int i;
3223 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3224
3225 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3226 u64 ent = pt[i];
3227
c7addb90 3228 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3229 continue;
3230
3231 va = canonicalize(va);
2920d728
MT		 3232 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3233 audit_mappings_page(vcpu, ent, va, level - 1);
3234 else {
ad312c7c 3235 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3236 gfn_t gfn = gpa >> PAGE_SHIFT;
3237 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3238 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3239
2aaf65e8
MT		 3240 if (is_error_pfn(pfn)) {
3241 kvm_release_pfn_clean(pfn);
3242 continue;
3243 }
3244
c7addb90 3245 if (is_shadow_present_pte(ent)
37a7d8b0 3246 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3247 printk(KERN_ERR "xx audit error: (%s) levels %d"
3248 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3249 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3250 va, gpa, hpa, ent,
3251 is_shadow_present_pte(ent));
c7addb90
AK		 3252 else if (ent == shadow_notrap_nonpresent_pte
3253 && !is_error_hpa(hpa))
3254 printk(KERN_ERR "audit: (%s) notrap shadow,"
3255 " valid guest gva %lx\n", audit_msg, va);
35149e21 3256 kvm_release_pfn_clean(pfn);
c7addb90 3257
37a7d8b0
AK		 3258 }
3259 }
3260}
3261
3262static void audit_mappings(struct kvm_vcpu *vcpu)
3263{
1ea252af 3264 unsigned i;
37a7d8b0 3265
ad312c7c
ZX		 3266 if (vcpu->arch.mmu.root_level == 4)
3267 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3268 else
3269 for (i = 0; i < 4; ++i)
ad312c7c 3270 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3271 audit_mappings_page(vcpu,
ad312c7c 3272 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3273 i << 30,
3274 2);
3275}
3276
3277static int count_rmaps(struct kvm_vcpu *vcpu)
3278{
3279 int nmaps = 0;
bc6678a3 3280 int i, j, k, idx;
37a7d8b0 3281
bc6678a3
MT		 3282 idx = srcu_read_lock(&kvm->srcu);
3283 slots = rcu_dereference(kvm->memslots);
37a7d8b0 3284 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3285 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3286 struct kvm_rmap_desc *d;
3287
3288 for (j = 0; j < m->npages; ++j) {
290fc38d 3289 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3290
290fc38d 3291 if (!*rmapp)
37a7d8b0 3292 continue;
290fc38d 3293 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3294 ++nmaps;
3295 continue;
3296 }
290fc38d 3297 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3298 while (d) {
3299 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3300 if (d->sptes[k])
37a7d8b0
AK		 3301 ++nmaps;
3302 else
3303 break;
3304 d = d->more;
3305 }
3306 }
3307 }
bc6678a3 3308 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3309 return nmaps;
3310}
3311
08a3732b
MT		 3312void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3313{
3314 unsigned long *rmapp;
3315 struct kvm_mmu_page *rev_sp;
3316 gfn_t gfn;
3317
3318 if (*sptep & PT_WRITABLE_MASK) {
3319 rev_sp = page_header(__pa(sptep));
3320 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3321
3322 if (!gfn_to_memslot(kvm, gfn)) {
3323 if (!printk_ratelimit())
3324 return;
3325 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3326 audit_msg, gfn);
3327 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3328 audit_msg, sptep - rev_sp->spt,
3329 rev_sp->gfn);
3330 dump_stack();
3331 return;
3332 }
3333
2920d728
MT		 3334 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3335 is_large_pte(*sptep));
08a3732b
MT		 3336 if (!*rmapp) {
3337 if (!printk_ratelimit())
3338 return;
3339 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3340 audit_msg, *sptep);
3341 dump_stack();
3342 }
3343 }
3344
3345}
3346
3347void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3348{
3349 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3350}
3351
3352static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3353{
4db35314 3354 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3355 int i;
3356
f05e70ac 3357 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3358 u64 *pt = sp->spt;
37a7d8b0 3359
4db35314 3360 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3361 continue;
3362
3363 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3364 u64 ent = pt[i];
3365
3366 if (!(ent & PT_PRESENT_MASK))
3367 continue;
3368 if (!(ent & PT_WRITABLE_MASK))
3369 continue;
08a3732b 3370 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3371 }
3372 }
08a3732b 3373 return;
37a7d8b0
AK		 3374}
3375
3376static void audit_rmap(struct kvm_vcpu *vcpu)
3377{
08a3732b
MT		 3378 check_writable_mappings_rmap(vcpu);
3379 count_rmaps(vcpu);
37a7d8b0
AK		 3380}
3381
3382static void audit_write_protection(struct kvm_vcpu *vcpu)
3383{
4db35314 3384 struct kvm_mmu_page *sp;
290fc38d
IE		 3385 struct kvm_memory_slot *slot;
3386 unsigned long *rmapp;
e58b0f9e 3387 u64 *spte;
290fc38d 3388 gfn_t gfn;
37a7d8b0 3389
f05e70ac 3390 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3391 if (sp->role.direct)
37a7d8b0 3392 continue;
e58b0f9e
MT		 3393 if (sp->unsync)
3394 continue;
37a7d8b0 3395
4db35314 3396 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3397 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3398 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3399
3400 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3401 while (spte) {
3402 if (*spte & PT_WRITABLE_MASK)
3403 printk(KERN_ERR "%s: (%s) shadow page has "
3404 "writable mappings: gfn %lx role %x\n",
b8688d51 3405 __func__, audit_msg, sp->gfn,
4db35314 3406 sp->role.word);
e58b0f9e
MT		 3407 spte = rmap_next(vcpu->kvm, rmapp, spte);
3408 }
37a7d8b0
AK		 3409 }
3410}
3411
3412static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3413{
3414 int olddbg = dbg;
3415
3416 dbg = 0;
3417 audit_msg = msg;
3418 audit_rmap(vcpu);
3419 audit_write_protection(vcpu);
2aaf65e8
MT		 3420 if (strcmp("pre pte write", audit_msg) != 0)
3421 audit_mappings(vcpu);
08a3732b 3422 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3423 dbg = olddbg;
3424}
3425
3426#endif
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