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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
8b1fe17c XG |
52 | enum { |
53 | AUDIT_PRE_PAGE_FAULT, | |
54 | AUDIT_POST_PAGE_FAULT, | |
55 | AUDIT_PRE_PTE_WRITE, | |
56 | AUDIT_POST_PTE_WRITE | |
57 | }; | |
37a7d8b0 | 58 | |
8b1fe17c XG |
59 | char *audit_point_name[] = { |
60 | "pre page fault", | |
61 | "post page fault", | |
62 | "pre pte write", | |
63 | "post pte write" | |
64 | }; | |
37a7d8b0 | 65 | |
8b1fe17c | 66 | #undef MMU_DEBUG |
37a7d8b0 AK |
67 | |
68 | #ifdef MMU_DEBUG | |
69 | ||
70 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
71 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
72 | ||
73 | #else | |
74 | ||
75 | #define pgprintk(x...) do { } while (0) | |
76 | #define rmap_printk(x...) do { } while (0) | |
77 | ||
78 | #endif | |
79 | ||
8b1fe17c | 80 | #ifdef MMU_DEBUG |
6ada8cca AK |
81 | static int dbg = 0; |
82 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 83 | #endif |
6aa8b732 | 84 | |
582801a9 MT |
85 | static int oos_shadow = 1; |
86 | module_param(oos_shadow, bool, 0644); | |
87 | ||
d6c69ee9 YD |
88 | #ifndef MMU_DEBUG |
89 | #define ASSERT(x) do { } while (0) | |
90 | #else | |
6aa8b732 AK |
91 | #define ASSERT(x) \ |
92 | if (!(x)) { \ | |
93 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
94 | __FILE__, __LINE__, #x); \ | |
95 | } | |
d6c69ee9 | 96 | #endif |
6aa8b732 | 97 | |
957ed9ef XG |
98 | #define PTE_PREFETCH_NUM 8 |
99 | ||
6aa8b732 AK |
100 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
101 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
102 | ||
6aa8b732 AK |
103 | #define PT64_LEVEL_BITS 9 |
104 | ||
105 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 106 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
107 | |
108 | #define PT64_LEVEL_MASK(level) \ | |
109 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
110 | ||
111 | #define PT64_INDEX(address, level)\ | |
112 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
113 | ||
114 | ||
115 | #define PT32_LEVEL_BITS 10 | |
116 | ||
117 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 118 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
119 | |
120 | #define PT32_LEVEL_MASK(level) \ | |
121 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
122 | #define PT32_LVL_OFFSET_MASK(level) \ |
123 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
124 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
125 | |
126 | #define PT32_INDEX(address, level)\ | |
127 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
128 | ||
129 | ||
27aba766 | 130 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
131 | #define PT64_DIR_BASE_ADDR_MASK \ |
132 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
133 | #define PT64_LVL_ADDR_MASK(level) \ |
134 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
135 | * PT64_LEVEL_BITS))) - 1)) | |
136 | #define PT64_LVL_OFFSET_MASK(level) \ | |
137 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
138 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
139 | |
140 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
141 | #define PT32_DIR_BASE_ADDR_MASK \ | |
142 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
143 | #define PT32_LVL_ADDR_MASK(level) \ |
144 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
145 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 146 | |
79539cec AK |
147 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
148 | | PT64_NX_MASK) | |
6aa8b732 | 149 | |
cd4a4e53 AK |
150 | #define RMAP_EXT 4 |
151 | ||
fe135d2c AK |
152 | #define ACC_EXEC_MASK 1 |
153 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
154 | #define ACC_USER_MASK PT_USER_MASK | |
155 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
156 | ||
90bb6fc5 AK |
157 | #include <trace/events/kvm.h> |
158 | ||
07420171 AK |
159 | #define CREATE_TRACE_POINTS |
160 | #include "mmutrace.h" | |
161 | ||
1403283a IE |
162 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
163 | ||
135f8c2b AK |
164 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
165 | ||
cd4a4e53 | 166 | struct kvm_rmap_desc { |
d555c333 | 167 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
168 | struct kvm_rmap_desc *more; |
169 | }; | |
170 | ||
2d11123a AK |
171 | struct kvm_shadow_walk_iterator { |
172 | u64 addr; | |
173 | hpa_t shadow_addr; | |
174 | int level; | |
175 | u64 *sptep; | |
176 | unsigned index; | |
177 | }; | |
178 | ||
179 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
180 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
181 | shadow_walk_okay(&(_walker)); \ | |
182 | shadow_walk_next(&(_walker))) | |
183 | ||
1047df1f | 184 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 185 | |
b5a33a75 AK |
186 | static struct kmem_cache *pte_chain_cache; |
187 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 188 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 189 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 190 | |
c7addb90 AK |
191 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
192 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
193 | static u64 __read_mostly shadow_base_present_pte; |
194 | static u64 __read_mostly shadow_nx_mask; | |
195 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
196 | static u64 __read_mostly shadow_user_mask; | |
197 | static u64 __read_mostly shadow_accessed_mask; | |
198 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 199 | |
82725b20 DE |
200 | static inline u64 rsvd_bits(int s, int e) |
201 | { | |
202 | return ((1ULL << (e - s + 1)) - 1) << s; | |
203 | } | |
204 | ||
c7addb90 AK |
205 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
206 | { | |
207 | shadow_trap_nonpresent_pte = trap_pte; | |
208 | shadow_notrap_nonpresent_pte = notrap_pte; | |
209 | } | |
210 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
211 | ||
7b52345e SY |
212 | void kvm_mmu_set_base_ptes(u64 base_pte) |
213 | { | |
214 | shadow_base_present_pte = base_pte; | |
215 | } | |
216 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
217 | ||
218 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 219 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
220 | { |
221 | shadow_user_mask = user_mask; | |
222 | shadow_accessed_mask = accessed_mask; | |
223 | shadow_dirty_mask = dirty_mask; | |
224 | shadow_nx_mask = nx_mask; | |
225 | shadow_x_mask = x_mask; | |
226 | } | |
227 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
228 | ||
3dbe1415 | 229 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 230 | { |
4d4ec087 | 231 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
232 | } |
233 | ||
234 | static int is_cpuid_PSE36(void) | |
235 | { | |
236 | return 1; | |
237 | } | |
238 | ||
73b1087e AK |
239 | static int is_nx(struct kvm_vcpu *vcpu) |
240 | { | |
f6801dff | 241 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
242 | } |
243 | ||
c7addb90 AK |
244 | static int is_shadow_present_pte(u64 pte) |
245 | { | |
c7addb90 AK |
246 | return pte != shadow_trap_nonpresent_pte |
247 | && pte != shadow_notrap_nonpresent_pte; | |
248 | } | |
249 | ||
05da4558 MT |
250 | static int is_large_pte(u64 pte) |
251 | { | |
252 | return pte & PT_PAGE_SIZE_MASK; | |
253 | } | |
254 | ||
8dae4445 | 255 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
256 | { |
257 | return pte & PT_WRITABLE_MASK; | |
258 | } | |
259 | ||
43a3795a | 260 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 261 | { |
439e218a | 262 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
263 | } |
264 | ||
43a3795a | 265 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 266 | { |
4b1a80fa | 267 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
268 | } |
269 | ||
776e6633 MT |
270 | static int is_last_spte(u64 pte, int level) |
271 | { | |
272 | if (level == PT_PAGE_TABLE_LEVEL) | |
273 | return 1; | |
852e3c19 | 274 | if (is_large_pte(pte)) |
776e6633 MT |
275 | return 1; |
276 | return 0; | |
277 | } | |
278 | ||
35149e21 | 279 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 280 | { |
35149e21 | 281 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
282 | } |
283 | ||
da928521 AK |
284 | static gfn_t pse36_gfn_delta(u32 gpte) |
285 | { | |
286 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
287 | ||
288 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
289 | } | |
290 | ||
d555c333 | 291 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 292 | { |
7645e432 | 293 | set_64bit(sptep, spte); |
e663ee64 AK |
294 | } |
295 | ||
a9221dd5 AK |
296 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
297 | { | |
298 | #ifdef CONFIG_X86_64 | |
299 | return xchg(sptep, new_spte); | |
300 | #else | |
301 | u64 old_spte; | |
302 | ||
303 | do { | |
304 | old_spte = *sptep; | |
305 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
306 | ||
307 | return old_spte; | |
308 | #endif | |
309 | } | |
310 | ||
8672b721 XG |
311 | static bool spte_has_volatile_bits(u64 spte) |
312 | { | |
313 | if (!shadow_accessed_mask) | |
314 | return false; | |
315 | ||
316 | if (!is_shadow_present_pte(spte)) | |
317 | return false; | |
318 | ||
4132779b XG |
319 | if ((spte & shadow_accessed_mask) && |
320 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
321 | return false; |
322 | ||
323 | return true; | |
324 | } | |
325 | ||
4132779b XG |
326 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
327 | { | |
328 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
329 | } | |
330 | ||
b79b93f9 AK |
331 | static void update_spte(u64 *sptep, u64 new_spte) |
332 | { | |
4132779b XG |
333 | u64 mask, old_spte = *sptep; |
334 | ||
335 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 336 | |
4132779b XG |
337 | new_spte |= old_spte & shadow_dirty_mask; |
338 | ||
339 | mask = shadow_accessed_mask; | |
340 | if (is_writable_pte(old_spte)) | |
341 | mask |= shadow_dirty_mask; | |
342 | ||
343 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 344 | __set_spte(sptep, new_spte); |
4132779b | 345 | else |
b79b93f9 | 346 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
347 | |
348 | if (!shadow_accessed_mask) | |
349 | return; | |
350 | ||
351 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
352 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
353 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
354 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
355 | } |
356 | ||
e2dec939 | 357 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 358 | struct kmem_cache *base_cache, int min) |
714b93da AK |
359 | { |
360 | void *obj; | |
361 | ||
362 | if (cache->nobjs >= min) | |
e2dec939 | 363 | return 0; |
714b93da | 364 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 365 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 366 | if (!obj) |
e2dec939 | 367 | return -ENOMEM; |
714b93da AK |
368 | cache->objects[cache->nobjs++] = obj; |
369 | } | |
e2dec939 | 370 | return 0; |
714b93da AK |
371 | } |
372 | ||
e8ad9a70 XG |
373 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
374 | struct kmem_cache *cache) | |
714b93da AK |
375 | { |
376 | while (mc->nobjs) | |
e8ad9a70 | 377 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
378 | } |
379 | ||
c1158e63 | 380 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 381 | int min) |
c1158e63 AK |
382 | { |
383 | struct page *page; | |
384 | ||
385 | if (cache->nobjs >= min) | |
386 | return 0; | |
387 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 388 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
389 | if (!page) |
390 | return -ENOMEM; | |
c1158e63 AK |
391 | cache->objects[cache->nobjs++] = page_address(page); |
392 | } | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
397 | { | |
398 | while (mc->nobjs) | |
c4d198d5 | 399 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
400 | } |
401 | ||
2e3e5882 | 402 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 403 | { |
e2dec939 AK |
404 | int r; |
405 | ||
ad312c7c | 406 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 407 | pte_chain_cache, 4); |
e2dec939 AK |
408 | if (r) |
409 | goto out; | |
ad312c7c | 410 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
957ed9ef | 411 | rmap_desc_cache, 4 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
412 | if (r) |
413 | goto out; | |
ad312c7c | 414 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
415 | if (r) |
416 | goto out; | |
ad312c7c | 417 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 418 | mmu_page_header_cache, 4); |
e2dec939 AK |
419 | out: |
420 | return r; | |
714b93da AK |
421 | } |
422 | ||
423 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
424 | { | |
e8ad9a70 XG |
425 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
426 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 427 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
428 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
429 | mmu_page_header_cache); | |
714b93da AK |
430 | } |
431 | ||
432 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
433 | size_t size) | |
434 | { | |
435 | void *p; | |
436 | ||
437 | BUG_ON(!mc->nobjs); | |
438 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
439 | return p; |
440 | } | |
441 | ||
714b93da AK |
442 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
443 | { | |
ad312c7c | 444 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
445 | sizeof(struct kvm_pte_chain)); |
446 | } | |
447 | ||
90cb0529 | 448 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 449 | { |
e8ad9a70 | 450 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
451 | } |
452 | ||
453 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
454 | { | |
ad312c7c | 455 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
456 | sizeof(struct kvm_rmap_desc)); |
457 | } | |
458 | ||
90cb0529 | 459 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 460 | { |
e8ad9a70 | 461 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
462 | } |
463 | ||
2032a93d LJ |
464 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
465 | { | |
466 | if (!sp->role.direct) | |
467 | return sp->gfns[index]; | |
468 | ||
469 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
470 | } | |
471 | ||
472 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
473 | { | |
474 | if (sp->role.direct) | |
475 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
476 | else | |
477 | sp->gfns[index] = gfn; | |
478 | } | |
479 | ||
05da4558 MT |
480 | /* |
481 | * Return the pointer to the largepage write count for a given | |
482 | * gfn, handling slots that are not large page aligned. | |
483 | */ | |
d25797b2 JR |
484 | static int *slot_largepage_idx(gfn_t gfn, |
485 | struct kvm_memory_slot *slot, | |
486 | int level) | |
05da4558 MT |
487 | { |
488 | unsigned long idx; | |
489 | ||
82855413 JR |
490 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
491 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 492 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
493 | } |
494 | ||
495 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
496 | { | |
d25797b2 | 497 | struct kvm_memory_slot *slot; |
05da4558 | 498 | int *write_count; |
d25797b2 | 499 | int i; |
05da4558 | 500 | |
a1f4d395 | 501 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
502 | for (i = PT_DIRECTORY_LEVEL; |
503 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
504 | write_count = slot_largepage_idx(gfn, slot, i); | |
505 | *write_count += 1; | |
506 | } | |
05da4558 MT |
507 | } |
508 | ||
509 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
510 | { | |
d25797b2 | 511 | struct kvm_memory_slot *slot; |
05da4558 | 512 | int *write_count; |
d25797b2 | 513 | int i; |
05da4558 | 514 | |
a1f4d395 | 515 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
516 | for (i = PT_DIRECTORY_LEVEL; |
517 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
518 | write_count = slot_largepage_idx(gfn, slot, i); |
519 | *write_count -= 1; | |
520 | WARN_ON(*write_count < 0); | |
521 | } | |
05da4558 MT |
522 | } |
523 | ||
d25797b2 JR |
524 | static int has_wrprotected_page(struct kvm *kvm, |
525 | gfn_t gfn, | |
526 | int level) | |
05da4558 | 527 | { |
2843099f | 528 | struct kvm_memory_slot *slot; |
05da4558 MT |
529 | int *largepage_idx; |
530 | ||
a1f4d395 | 531 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 532 | if (slot) { |
d25797b2 | 533 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
534 | return *largepage_idx; |
535 | } | |
536 | ||
537 | return 1; | |
538 | } | |
539 | ||
d25797b2 | 540 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 541 | { |
8f0b1ab6 | 542 | unsigned long page_size; |
d25797b2 | 543 | int i, ret = 0; |
05da4558 | 544 | |
8f0b1ab6 | 545 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 546 | |
d25797b2 JR |
547 | for (i = PT_PAGE_TABLE_LEVEL; |
548 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
549 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
550 | ret = i; | |
551 | else | |
552 | break; | |
553 | } | |
554 | ||
4c2155ce | 555 | return ret; |
05da4558 MT |
556 | } |
557 | ||
d25797b2 | 558 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
559 | { |
560 | struct kvm_memory_slot *slot; | |
878403b7 | 561 | int host_level, level, max_level; |
05da4558 MT |
562 | |
563 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
564 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 565 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 566 | |
d25797b2 JR |
567 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
568 | ||
569 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
570 | return host_level; | |
571 | ||
878403b7 SY |
572 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
573 | kvm_x86_ops->get_lpage_level() : host_level; | |
574 | ||
575 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
576 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
577 | break; | |
d25797b2 JR |
578 | |
579 | return level - 1; | |
05da4558 MT |
580 | } |
581 | ||
290fc38d IE |
582 | /* |
583 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
584 | */ |
585 | ||
44ad9944 | 586 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
587 | { |
588 | struct kvm_memory_slot *slot; | |
05da4558 | 589 | unsigned long idx; |
290fc38d IE |
590 | |
591 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 592 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
593 | return &slot->rmap[gfn - slot->base_gfn]; |
594 | ||
82855413 JR |
595 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
596 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 597 | |
44ad9944 | 598 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
599 | } |
600 | ||
cd4a4e53 AK |
601 | /* |
602 | * Reverse mapping data structures: | |
603 | * | |
290fc38d IE |
604 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
605 | * that points to page_address(page). | |
cd4a4e53 | 606 | * |
290fc38d IE |
607 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
608 | * containing more mappings. | |
53a27b39 MT |
609 | * |
610 | * Returns the number of rmap entries before the spte was added or zero if | |
611 | * the spte was not added. | |
612 | * | |
cd4a4e53 | 613 | */ |
44ad9944 | 614 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 615 | { |
4db35314 | 616 | struct kvm_mmu_page *sp; |
cd4a4e53 | 617 | struct kvm_rmap_desc *desc; |
290fc38d | 618 | unsigned long *rmapp; |
53a27b39 | 619 | int i, count = 0; |
cd4a4e53 | 620 | |
43a3795a | 621 | if (!is_rmap_spte(*spte)) |
53a27b39 | 622 | return count; |
4db35314 | 623 | sp = page_header(__pa(spte)); |
2032a93d | 624 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 625 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 626 | if (!*rmapp) { |
cd4a4e53 | 627 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
628 | *rmapp = (unsigned long)spte; |
629 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 630 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 631 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
632 | desc->sptes[0] = (u64 *)*rmapp; |
633 | desc->sptes[1] = spte; | |
290fc38d | 634 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
635 | } else { |
636 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 637 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 638 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 639 | desc = desc->more; |
53a27b39 MT |
640 | count += RMAP_EXT; |
641 | } | |
d555c333 | 642 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 643 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
644 | desc = desc->more; |
645 | } | |
d555c333 | 646 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 647 | ; |
d555c333 | 648 | desc->sptes[i] = spte; |
cd4a4e53 | 649 | } |
53a27b39 | 650 | return count; |
cd4a4e53 AK |
651 | } |
652 | ||
290fc38d | 653 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
654 | struct kvm_rmap_desc *desc, |
655 | int i, | |
656 | struct kvm_rmap_desc *prev_desc) | |
657 | { | |
658 | int j; | |
659 | ||
d555c333 | 660 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 661 | ; |
d555c333 AK |
662 | desc->sptes[i] = desc->sptes[j]; |
663 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
664 | if (j != 0) |
665 | return; | |
666 | if (!prev_desc && !desc->more) | |
d555c333 | 667 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
668 | else |
669 | if (prev_desc) | |
670 | prev_desc->more = desc->more; | |
671 | else | |
290fc38d | 672 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 673 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
674 | } |
675 | ||
290fc38d | 676 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 677 | { |
cd4a4e53 AK |
678 | struct kvm_rmap_desc *desc; |
679 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 680 | struct kvm_mmu_page *sp; |
2032a93d | 681 | gfn_t gfn; |
290fc38d | 682 | unsigned long *rmapp; |
cd4a4e53 AK |
683 | int i; |
684 | ||
4db35314 | 685 | sp = page_header(__pa(spte)); |
2032a93d LJ |
686 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
687 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 688 | if (!*rmapp) { |
19ada5c4 | 689 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 690 | BUG(); |
290fc38d | 691 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 692 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 693 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 694 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
695 | BUG(); |
696 | } | |
290fc38d | 697 | *rmapp = 0; |
cd4a4e53 | 698 | } else { |
19ada5c4 | 699 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 700 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
701 | prev_desc = NULL; |
702 | while (desc) { | |
d555c333 AK |
703 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
704 | if (desc->sptes[i] == spte) { | |
290fc38d | 705 | rmap_desc_remove_entry(rmapp, |
714b93da | 706 | desc, i, |
cd4a4e53 AK |
707 | prev_desc); |
708 | return; | |
709 | } | |
710 | prev_desc = desc; | |
711 | desc = desc->more; | |
712 | } | |
19ada5c4 | 713 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
714 | BUG(); |
715 | } | |
716 | } | |
717 | ||
e4b502ea | 718 | static void set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 719 | { |
ce061867 | 720 | pfn_t pfn; |
9a3aad70 XG |
721 | u64 old_spte = *sptep; |
722 | ||
8672b721 | 723 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 724 | __set_spte(sptep, new_spte); |
8672b721 | 725 | else |
9a3aad70 | 726 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 727 | |
a9221dd5 | 728 | if (!is_rmap_spte(old_spte)) |
ce061867 | 729 | return; |
8672b721 | 730 | |
a9221dd5 | 731 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 732 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 733 | kvm_set_pfn_accessed(pfn); |
4132779b | 734 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 735 | kvm_set_pfn_dirty(pfn); |
e4b502ea XG |
736 | } |
737 | ||
738 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
739 | { | |
740 | set_spte_track_bits(sptep, new_spte); | |
be38d276 | 741 | rmap_remove(kvm, sptep); |
be38d276 AK |
742 | } |
743 | ||
98348e95 | 744 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 745 | { |
374cbac0 | 746 | struct kvm_rmap_desc *desc; |
98348e95 IE |
747 | u64 *prev_spte; |
748 | int i; | |
749 | ||
750 | if (!*rmapp) | |
751 | return NULL; | |
752 | else if (!(*rmapp & 1)) { | |
753 | if (!spte) | |
754 | return (u64 *)*rmapp; | |
755 | return NULL; | |
756 | } | |
757 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
758 | prev_spte = NULL; |
759 | while (desc) { | |
d555c333 | 760 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 761 | if (prev_spte == spte) |
d555c333 AK |
762 | return desc->sptes[i]; |
763 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
764 | } |
765 | desc = desc->more; | |
766 | } | |
767 | return NULL; | |
768 | } | |
769 | ||
b1a36821 | 770 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 771 | { |
290fc38d | 772 | unsigned long *rmapp; |
374cbac0 | 773 | u64 *spte; |
44ad9944 | 774 | int i, write_protected = 0; |
374cbac0 | 775 | |
44ad9944 | 776 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 777 | |
98348e95 IE |
778 | spte = rmap_next(kvm, rmapp, NULL); |
779 | while (spte) { | |
374cbac0 | 780 | BUG_ON(!spte); |
374cbac0 | 781 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 782 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 783 | if (is_writable_pte(*spte)) { |
b79b93f9 | 784 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
785 | write_protected = 1; |
786 | } | |
9647c14c | 787 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 788 | } |
855149aa | 789 | |
05da4558 | 790 | /* check for huge page mappings */ |
44ad9944 JR |
791 | for (i = PT_DIRECTORY_LEVEL; |
792 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
793 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
794 | spte = rmap_next(kvm, rmapp, NULL); | |
795 | while (spte) { | |
796 | BUG_ON(!spte); | |
797 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
798 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
799 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 800 | if (is_writable_pte(*spte)) { |
be38d276 AK |
801 | drop_spte(kvm, spte, |
802 | shadow_trap_nonpresent_pte); | |
44ad9944 | 803 | --kvm->stat.lpages; |
44ad9944 JR |
804 | spte = NULL; |
805 | write_protected = 1; | |
806 | } | |
807 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 808 | } |
05da4558 MT |
809 | } |
810 | ||
b1a36821 | 811 | return write_protected; |
374cbac0 AK |
812 | } |
813 | ||
8a8365c5 FD |
814 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
815 | unsigned long data) | |
e930bffe AA |
816 | { |
817 | u64 *spte; | |
818 | int need_tlb_flush = 0; | |
819 | ||
820 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
821 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
822 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 823 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
824 | need_tlb_flush = 1; |
825 | } | |
826 | return need_tlb_flush; | |
827 | } | |
828 | ||
8a8365c5 FD |
829 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
830 | unsigned long data) | |
3da0dd43 IE |
831 | { |
832 | int need_flush = 0; | |
e4b502ea | 833 | u64 *spte, new_spte; |
3da0dd43 IE |
834 | pte_t *ptep = (pte_t *)data; |
835 | pfn_t new_pfn; | |
836 | ||
837 | WARN_ON(pte_huge(*ptep)); | |
838 | new_pfn = pte_pfn(*ptep); | |
839 | spte = rmap_next(kvm, rmapp, NULL); | |
840 | while (spte) { | |
841 | BUG_ON(!is_shadow_present_pte(*spte)); | |
842 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
843 | need_flush = 1; | |
844 | if (pte_write(*ptep)) { | |
be38d276 | 845 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
846 | spte = rmap_next(kvm, rmapp, NULL); |
847 | } else { | |
848 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
849 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
850 | ||
851 | new_spte &= ~PT_WRITABLE_MASK; | |
852 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 853 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 854 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
855 | spte = rmap_next(kvm, rmapp, spte); |
856 | } | |
857 | } | |
858 | if (need_flush) | |
859 | kvm_flush_remote_tlbs(kvm); | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
8a8365c5 FD |
864 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
865 | unsigned long data, | |
3da0dd43 | 866 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 867 | unsigned long data)) |
e930bffe | 868 | { |
852e3c19 | 869 | int i, j; |
90bb6fc5 | 870 | int ret; |
e930bffe | 871 | int retval = 0; |
bc6678a3 MT |
872 | struct kvm_memslots *slots; |
873 | ||
90d83dc3 | 874 | slots = kvm_memslots(kvm); |
e930bffe | 875 | |
46a26bf5 MT |
876 | for (i = 0; i < slots->nmemslots; i++) { |
877 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
878 | unsigned long start = memslot->userspace_addr; |
879 | unsigned long end; | |
880 | ||
e930bffe AA |
881 | end = start + (memslot->npages << PAGE_SHIFT); |
882 | if (hva >= start && hva < end) { | |
883 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 884 | |
90bb6fc5 | 885 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
886 | |
887 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
6e3e243c AA |
888 | unsigned long idx; |
889 | int sh; | |
890 | ||
891 | sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j); | |
892 | idx = ((memslot->base_gfn+gfn_offset) >> sh) - | |
893 | (memslot->base_gfn >> sh); | |
90bb6fc5 | 894 | ret |= handler(kvm, |
3da0dd43 IE |
895 | &memslot->lpage_info[j][idx].rmap_pde, |
896 | data); | |
852e3c19 | 897 | } |
90bb6fc5 AK |
898 | trace_kvm_age_page(hva, memslot, ret); |
899 | retval |= ret; | |
e930bffe AA |
900 | } |
901 | } | |
902 | ||
903 | return retval; | |
904 | } | |
905 | ||
906 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
907 | { | |
3da0dd43 IE |
908 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
909 | } | |
910 | ||
911 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
912 | { | |
8a8365c5 | 913 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
914 | } |
915 | ||
8a8365c5 FD |
916 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
917 | unsigned long data) | |
e930bffe AA |
918 | { |
919 | u64 *spte; | |
920 | int young = 0; | |
921 | ||
6316e1c8 RR |
922 | /* |
923 | * Emulate the accessed bit for EPT, by checking if this page has | |
924 | * an EPT mapping, and clearing it if it does. On the next access, | |
925 | * a new EPT mapping will be established. | |
926 | * This has some overhead, but not as much as the cost of swapping | |
927 | * out actively used pages or breaking up actively used hugepages. | |
928 | */ | |
534e38b4 | 929 | if (!shadow_accessed_mask) |
6316e1c8 | 930 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 931 | |
e930bffe AA |
932 | spte = rmap_next(kvm, rmapp, NULL); |
933 | while (spte) { | |
934 | int _young; | |
935 | u64 _spte = *spte; | |
936 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
937 | _young = _spte & PT_ACCESSED_MASK; | |
938 | if (_young) { | |
939 | young = 1; | |
940 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
941 | } | |
942 | spte = rmap_next(kvm, rmapp, spte); | |
943 | } | |
944 | return young; | |
945 | } | |
946 | ||
53a27b39 MT |
947 | #define RMAP_RECYCLE_THRESHOLD 1000 |
948 | ||
852e3c19 | 949 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
950 | { |
951 | unsigned long *rmapp; | |
852e3c19 JR |
952 | struct kvm_mmu_page *sp; |
953 | ||
954 | sp = page_header(__pa(spte)); | |
53a27b39 | 955 | |
852e3c19 | 956 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 957 | |
3da0dd43 | 958 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
959 | kvm_flush_remote_tlbs(vcpu->kvm); |
960 | } | |
961 | ||
e930bffe AA |
962 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
963 | { | |
3da0dd43 | 964 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
965 | } |
966 | ||
d6c69ee9 | 967 | #ifdef MMU_DEBUG |
47ad8e68 | 968 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 969 | { |
139bdb2d AK |
970 | u64 *pos; |
971 | u64 *end; | |
972 | ||
47ad8e68 | 973 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 974 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 975 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 976 | pos, *pos); |
6aa8b732 | 977 | return 0; |
139bdb2d | 978 | } |
6aa8b732 AK |
979 | return 1; |
980 | } | |
d6c69ee9 | 981 | #endif |
6aa8b732 | 982 | |
45221ab6 DH |
983 | /* |
984 | * This value is the sum of all of the kvm instances's | |
985 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
986 | * aggregate version in order to make the slab shrinker | |
987 | * faster | |
988 | */ | |
989 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
990 | { | |
991 | kvm->arch.n_used_mmu_pages += nr; | |
992 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
993 | } | |
994 | ||
4db35314 | 995 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 996 | { |
4db35314 | 997 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 998 | hlist_del(&sp->hash_link); |
4db35314 AK |
999 | list_del(&sp->link); |
1000 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
1001 | if (!sp->role.direct) |
1002 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 1003 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 1004 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
1005 | } |
1006 | ||
cea0f0e7 AK |
1007 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1008 | { | |
1ae0a13d | 1009 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1010 | } |
1011 | ||
25c0de2c | 1012 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1013 | u64 *parent_pte, int direct) |
6aa8b732 | 1014 | { |
4db35314 | 1015 | struct kvm_mmu_page *sp; |
6aa8b732 | 1016 | |
ad312c7c ZX |
1017 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1018 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1019 | if (!direct) |
1020 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1021 | PAGE_SIZE); | |
4db35314 | 1022 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1023 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1024 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1025 | sp->multimapped = 0; |
1026 | sp->parent_pte = parent_pte; | |
45221ab6 | 1027 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1028 | return sp; |
6aa8b732 AK |
1029 | } |
1030 | ||
714b93da | 1031 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1032 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1033 | { |
1034 | struct kvm_pte_chain *pte_chain; | |
1035 | struct hlist_node *node; | |
1036 | int i; | |
1037 | ||
1038 | if (!parent_pte) | |
1039 | return; | |
4db35314 AK |
1040 | if (!sp->multimapped) { |
1041 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1042 | |
1043 | if (!old) { | |
4db35314 | 1044 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1045 | return; |
1046 | } | |
4db35314 | 1047 | sp->multimapped = 1; |
714b93da | 1048 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1049 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1050 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1051 | pte_chain->parent_ptes[0] = old; |
1052 | } | |
4db35314 | 1053 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1054 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1055 | continue; | |
1056 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1057 | if (!pte_chain->parent_ptes[i]) { | |
1058 | pte_chain->parent_ptes[i] = parent_pte; | |
1059 | return; | |
1060 | } | |
1061 | } | |
714b93da | 1062 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1063 | BUG_ON(!pte_chain); |
4db35314 | 1064 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1065 | pte_chain->parent_ptes[0] = parent_pte; |
1066 | } | |
1067 | ||
4db35314 | 1068 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1069 | u64 *parent_pte) |
1070 | { | |
1071 | struct kvm_pte_chain *pte_chain; | |
1072 | struct hlist_node *node; | |
1073 | int i; | |
1074 | ||
4db35314 AK |
1075 | if (!sp->multimapped) { |
1076 | BUG_ON(sp->parent_pte != parent_pte); | |
1077 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1078 | return; |
1079 | } | |
4db35314 | 1080 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1081 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1082 | if (!pte_chain->parent_ptes[i]) | |
1083 | break; | |
1084 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1085 | continue; | |
697fe2e2 AK |
1086 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1087 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1088 | pte_chain->parent_ptes[i] |
1089 | = pte_chain->parent_ptes[i + 1]; | |
1090 | ++i; | |
1091 | } | |
1092 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1093 | if (i == 0) { |
1094 | hlist_del(&pte_chain->link); | |
90cb0529 | 1095 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1096 | if (hlist_empty(&sp->parent_ptes)) { |
1097 | sp->multimapped = 0; | |
1098 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1099 | } |
1100 | } | |
cea0f0e7 AK |
1101 | return; |
1102 | } | |
1103 | BUG(); | |
1104 | } | |
1105 | ||
6b18493d | 1106 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1107 | { |
1108 | struct kvm_pte_chain *pte_chain; | |
1109 | struct hlist_node *node; | |
1110 | struct kvm_mmu_page *parent_sp; | |
1111 | int i; | |
1112 | ||
1113 | if (!sp->multimapped && sp->parent_pte) { | |
1114 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1115 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1116 | return; |
1117 | } | |
1047df1f | 1118 | |
ad8cfbe3 MT |
1119 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1120 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1121 | u64 *spte = pte_chain->parent_ptes[i]; |
1122 | ||
1123 | if (!spte) | |
ad8cfbe3 | 1124 | break; |
1047df1f XG |
1125 | parent_sp = page_header(__pa(spte)); |
1126 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1127 | } |
1128 | } | |
1129 | ||
1047df1f XG |
1130 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1131 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1132 | { |
1047df1f | 1133 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1134 | } |
1135 | ||
1047df1f | 1136 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1137 | { |
1047df1f | 1138 | unsigned int index; |
0074ff63 | 1139 | |
1047df1f XG |
1140 | index = spte - sp->spt; |
1141 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1142 | return; |
1047df1f | 1143 | if (sp->unsync_children++) |
0074ff63 | 1144 | return; |
1047df1f | 1145 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1146 | } |
1147 | ||
d761a501 AK |
1148 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1149 | struct kvm_mmu_page *sp) | |
1150 | { | |
1151 | int i; | |
1152 | ||
1153 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1154 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1155 | } | |
1156 | ||
e8bc217a | 1157 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1158 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1159 | { |
1160 | return 1; | |
1161 | } | |
1162 | ||
a7052897 MT |
1163 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1164 | { | |
1165 | } | |
1166 | ||
60c8aec6 MT |
1167 | #define KVM_PAGE_ARRAY_NR 16 |
1168 | ||
1169 | struct kvm_mmu_pages { | |
1170 | struct mmu_page_and_offset { | |
1171 | struct kvm_mmu_page *sp; | |
1172 | unsigned int idx; | |
1173 | } page[KVM_PAGE_ARRAY_NR]; | |
1174 | unsigned int nr; | |
1175 | }; | |
1176 | ||
0074ff63 MT |
1177 | #define for_each_unsync_children(bitmap, idx) \ |
1178 | for (idx = find_first_bit(bitmap, 512); \ | |
1179 | idx < 512; \ | |
1180 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1181 | ||
cded19f3 HE |
1182 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1183 | int idx) | |
4731d4c7 | 1184 | { |
60c8aec6 | 1185 | int i; |
4731d4c7 | 1186 | |
60c8aec6 MT |
1187 | if (sp->unsync) |
1188 | for (i=0; i < pvec->nr; i++) | |
1189 | if (pvec->page[i].sp == sp) | |
1190 | return 0; | |
1191 | ||
1192 | pvec->page[pvec->nr].sp = sp; | |
1193 | pvec->page[pvec->nr].idx = idx; | |
1194 | pvec->nr++; | |
1195 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1196 | } | |
1197 | ||
1198 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1199 | struct kvm_mmu_pages *pvec) | |
1200 | { | |
1201 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1202 | |
0074ff63 | 1203 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1204 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1205 | u64 ent = sp->spt[i]; |
1206 | ||
7a8f1a74 XG |
1207 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1208 | goto clear_child_bitmap; | |
1209 | ||
1210 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1211 | ||
1212 | if (child->unsync_children) { | |
1213 | if (mmu_pages_add(pvec, child, i)) | |
1214 | return -ENOSPC; | |
1215 | ||
1216 | ret = __mmu_unsync_walk(child, pvec); | |
1217 | if (!ret) | |
1218 | goto clear_child_bitmap; | |
1219 | else if (ret > 0) | |
1220 | nr_unsync_leaf += ret; | |
1221 | else | |
1222 | return ret; | |
1223 | } else if (child->unsync) { | |
1224 | nr_unsync_leaf++; | |
1225 | if (mmu_pages_add(pvec, child, i)) | |
1226 | return -ENOSPC; | |
1227 | } else | |
1228 | goto clear_child_bitmap; | |
1229 | ||
1230 | continue; | |
1231 | ||
1232 | clear_child_bitmap: | |
1233 | __clear_bit(i, sp->unsync_child_bitmap); | |
1234 | sp->unsync_children--; | |
1235 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1236 | } |
1237 | ||
4731d4c7 | 1238 | |
60c8aec6 MT |
1239 | return nr_unsync_leaf; |
1240 | } | |
1241 | ||
1242 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1243 | struct kvm_mmu_pages *pvec) | |
1244 | { | |
1245 | if (!sp->unsync_children) | |
1246 | return 0; | |
1247 | ||
1248 | mmu_pages_add(pvec, sp, 0); | |
1249 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1250 | } |
1251 | ||
4731d4c7 MT |
1252 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1253 | { | |
1254 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1255 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1256 | sp->unsync = 0; |
1257 | --kvm->stat.mmu_unsync; | |
1258 | } | |
1259 | ||
7775834a XG |
1260 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1261 | struct list_head *invalid_list); | |
1262 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1263 | struct list_head *invalid_list); | |
4731d4c7 | 1264 | |
f41d335a XG |
1265 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1266 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1267 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1268 | if ((sp)->gfn != (gfn)) {} else | |
1269 | ||
f41d335a XG |
1270 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1271 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1272 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1273 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1274 | (sp)->role.invalid) {} else | |
1275 | ||
f918b443 | 1276 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1277 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1278 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1279 | { |
5b7e0102 | 1280 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1281 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1282 | return 1; |
1283 | } | |
1284 | ||
f918b443 | 1285 | if (clear_unsync) |
1d9dc7e0 | 1286 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1287 | |
be71e061 | 1288 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1289 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1290 | return 1; |
1291 | } | |
1292 | ||
1293 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1294 | return 0; |
1295 | } | |
1296 | ||
1d9dc7e0 XG |
1297 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1298 | struct kvm_mmu_page *sp) | |
1299 | { | |
d98ba053 | 1300 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1301 | int ret; |
1302 | ||
d98ba053 | 1303 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1304 | if (ret) |
d98ba053 XG |
1305 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1306 | ||
1d9dc7e0 XG |
1307 | return ret; |
1308 | } | |
1309 | ||
d98ba053 XG |
1310 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1311 | struct list_head *invalid_list) | |
1d9dc7e0 | 1312 | { |
d98ba053 | 1313 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1314 | } |
1315 | ||
9f1a122f XG |
1316 | /* @gfn should be write-protected at the call site */ |
1317 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1318 | { | |
9f1a122f | 1319 | struct kvm_mmu_page *s; |
f41d335a | 1320 | struct hlist_node *node; |
d98ba053 | 1321 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1322 | bool flush = false; |
1323 | ||
f41d335a | 1324 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1325 | if (!s->unsync) |
9f1a122f XG |
1326 | continue; |
1327 | ||
1328 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1329 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1330 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1331 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1332 | continue; |
1333 | } | |
1334 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1335 | flush = true; | |
1336 | } | |
1337 | ||
d98ba053 | 1338 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1339 | if (flush) |
1340 | kvm_mmu_flush_tlb(vcpu); | |
1341 | } | |
1342 | ||
60c8aec6 MT |
1343 | struct mmu_page_path { |
1344 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1345 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1346 | }; |
1347 | ||
60c8aec6 MT |
1348 | #define for_each_sp(pvec, sp, parents, i) \ |
1349 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1350 | sp = pvec.page[i].sp; \ | |
1351 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1352 | i = mmu_pages_next(&pvec, &parents, i)) | |
1353 | ||
cded19f3 HE |
1354 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1355 | struct mmu_page_path *parents, | |
1356 | int i) | |
60c8aec6 MT |
1357 | { |
1358 | int n; | |
1359 | ||
1360 | for (n = i+1; n < pvec->nr; n++) { | |
1361 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1362 | ||
1363 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1364 | parents->idx[0] = pvec->page[n].idx; | |
1365 | return n; | |
1366 | } | |
1367 | ||
1368 | parents->parent[sp->role.level-2] = sp; | |
1369 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1370 | } | |
1371 | ||
1372 | return n; | |
1373 | } | |
1374 | ||
cded19f3 | 1375 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1376 | { |
60c8aec6 MT |
1377 | struct kvm_mmu_page *sp; |
1378 | unsigned int level = 0; | |
1379 | ||
1380 | do { | |
1381 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1382 | |
60c8aec6 MT |
1383 | sp = parents->parent[level]; |
1384 | if (!sp) | |
1385 | return; | |
1386 | ||
1387 | --sp->unsync_children; | |
1388 | WARN_ON((int)sp->unsync_children < 0); | |
1389 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1390 | level++; | |
1391 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1392 | } |
1393 | ||
60c8aec6 MT |
1394 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1395 | struct mmu_page_path *parents, | |
1396 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1397 | { |
60c8aec6 MT |
1398 | parents->parent[parent->role.level-1] = NULL; |
1399 | pvec->nr = 0; | |
1400 | } | |
4731d4c7 | 1401 | |
60c8aec6 MT |
1402 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1403 | struct kvm_mmu_page *parent) | |
1404 | { | |
1405 | int i; | |
1406 | struct kvm_mmu_page *sp; | |
1407 | struct mmu_page_path parents; | |
1408 | struct kvm_mmu_pages pages; | |
d98ba053 | 1409 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1410 | |
1411 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1412 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1413 | int protected = 0; |
1414 | ||
1415 | for_each_sp(pages, sp, parents, i) | |
1416 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1417 | ||
1418 | if (protected) | |
1419 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1420 | ||
60c8aec6 | 1421 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1422 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1423 | mmu_pages_clear_parents(&parents); |
1424 | } | |
d98ba053 | 1425 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1426 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1427 | kvm_mmu_pages_init(parent, &parents, &pages); |
1428 | } | |
4731d4c7 MT |
1429 | } |
1430 | ||
cea0f0e7 AK |
1431 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1432 | gfn_t gfn, | |
1433 | gva_t gaddr, | |
1434 | unsigned level, | |
f6e2c02b | 1435 | int direct, |
41074d07 | 1436 | unsigned access, |
f7d9c7b7 | 1437 | u64 *parent_pte) |
cea0f0e7 AK |
1438 | { |
1439 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1440 | unsigned quadrant; |
9f1a122f | 1441 | struct kvm_mmu_page *sp; |
f41d335a | 1442 | struct hlist_node *node; |
9f1a122f | 1443 | bool need_sync = false; |
cea0f0e7 | 1444 | |
a770f6f2 | 1445 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1446 | role.level = level; |
f6e2c02b | 1447 | role.direct = direct; |
84b0c8c6 | 1448 | if (role.direct) |
5b7e0102 | 1449 | role.cr4_pae = 0; |
41074d07 | 1450 | role.access = access; |
c5a78f2b JR |
1451 | if (!vcpu->arch.mmu.direct_map |
1452 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1453 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1454 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1455 | role.quadrant = quadrant; | |
1456 | } | |
f41d335a | 1457 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1458 | if (!need_sync && sp->unsync) |
1459 | need_sync = true; | |
4731d4c7 | 1460 | |
7ae680eb XG |
1461 | if (sp->role.word != role.word) |
1462 | continue; | |
4731d4c7 | 1463 | |
7ae680eb XG |
1464 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1465 | break; | |
e02aa901 | 1466 | |
7ae680eb XG |
1467 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1468 | if (sp->unsync_children) { | |
a8eeb04a | 1469 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1470 | kvm_mmu_mark_parents_unsync(sp); |
1471 | } else if (sp->unsync) | |
1472 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1473 | |
7ae680eb XG |
1474 | trace_kvm_mmu_get_page(sp, false); |
1475 | return sp; | |
1476 | } | |
dfc5aa00 | 1477 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1478 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1479 | if (!sp) |
1480 | return sp; | |
4db35314 AK |
1481 | sp->gfn = gfn; |
1482 | sp->role = role; | |
7ae680eb XG |
1483 | hlist_add_head(&sp->hash_link, |
1484 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1485 | if (!direct) { |
b1a36821 MT |
1486 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1487 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1488 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1489 | kvm_sync_pages(vcpu, gfn); | |
1490 | ||
4731d4c7 MT |
1491 | account_shadowed(vcpu->kvm, gfn); |
1492 | } | |
131d8279 AK |
1493 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1494 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1495 | else | |
1496 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1497 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1498 | return sp; |
cea0f0e7 AK |
1499 | } |
1500 | ||
2d11123a AK |
1501 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1502 | struct kvm_vcpu *vcpu, u64 addr) | |
1503 | { | |
1504 | iterator->addr = addr; | |
1505 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1506 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1507 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1508 | iterator->shadow_addr | |
1509 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1510 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1511 | --iterator->level; | |
1512 | if (!iterator->shadow_addr) | |
1513 | iterator->level = 0; | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1518 | { | |
1519 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1520 | return false; | |
4d88954d MT |
1521 | |
1522 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1523 | if (is_large_pte(*iterator->sptep)) | |
1524 | return false; | |
1525 | ||
2d11123a AK |
1526 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1527 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1528 | return true; | |
1529 | } | |
1530 | ||
1531 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1532 | { | |
1533 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1534 | --iterator->level; | |
1535 | } | |
1536 | ||
32ef26a3 AK |
1537 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1538 | { | |
1539 | u64 spte; | |
1540 | ||
1541 | spte = __pa(sp->spt) | |
1542 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1543 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1544 | __set_spte(sptep, spte); |
32ef26a3 AK |
1545 | } |
1546 | ||
a3aa51cf AK |
1547 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1548 | { | |
1549 | if (is_large_pte(*sptep)) { | |
1550 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1551 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1552 | } | |
1553 | } | |
1554 | ||
a357bd22 AK |
1555 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1556 | unsigned direct_access) | |
1557 | { | |
1558 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1559 | struct kvm_mmu_page *child; | |
1560 | ||
1561 | /* | |
1562 | * For the direct sp, if the guest pte's dirty bit | |
1563 | * changed form clean to dirty, it will corrupt the | |
1564 | * sp's access: allow writable in the read-only sp, | |
1565 | * so we should update the spte at this point to get | |
1566 | * a new sp with the correct access. | |
1567 | */ | |
1568 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1569 | if (child->role.access == direct_access) | |
1570 | return; | |
1571 | ||
1572 | mmu_page_remove_parent_pte(child, sptep); | |
1573 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1574 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1575 | } | |
1576 | } | |
1577 | ||
90cb0529 | 1578 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1579 | struct kvm_mmu_page *sp) |
a436036b | 1580 | { |
697fe2e2 AK |
1581 | unsigned i; |
1582 | u64 *pt; | |
1583 | u64 ent; | |
1584 | ||
4db35314 | 1585 | pt = sp->spt; |
697fe2e2 | 1586 | |
697fe2e2 AK |
1587 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1588 | ent = pt[i]; | |
1589 | ||
05da4558 | 1590 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1591 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1592 | ent &= PT64_BASE_ADDR_MASK; |
1593 | mmu_page_remove_parent_pte(page_header(ent), | |
1594 | &pt[i]); | |
1595 | } else { | |
776e6633 MT |
1596 | if (is_large_pte(ent)) |
1597 | --kvm->stat.lpages; | |
be38d276 AK |
1598 | drop_spte(kvm, &pt[i], |
1599 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1600 | } |
1601 | } | |
c7addb90 | 1602 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1603 | } |
a436036b AK |
1604 | } |
1605 | ||
4db35314 | 1606 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1607 | { |
4db35314 | 1608 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1609 | } |
1610 | ||
12b7d28f AK |
1611 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1612 | { | |
1613 | int i; | |
988a2cae | 1614 | struct kvm_vcpu *vcpu; |
12b7d28f | 1615 | |
988a2cae GN |
1616 | kvm_for_each_vcpu(i, vcpu, kvm) |
1617 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1618 | } |
1619 | ||
31aa2b44 | 1620 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1621 | { |
1622 | u64 *parent_pte; | |
1623 | ||
4db35314 AK |
1624 | while (sp->multimapped || sp->parent_pte) { |
1625 | if (!sp->multimapped) | |
1626 | parent_pte = sp->parent_pte; | |
a436036b AK |
1627 | else { |
1628 | struct kvm_pte_chain *chain; | |
1629 | ||
4db35314 | 1630 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1631 | struct kvm_pte_chain, link); |
1632 | parent_pte = chain->parent_ptes[0]; | |
1633 | } | |
697fe2e2 | 1634 | BUG_ON(!parent_pte); |
4db35314 | 1635 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1636 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1637 | } |
31aa2b44 AK |
1638 | } |
1639 | ||
60c8aec6 | 1640 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1641 | struct kvm_mmu_page *parent, |
1642 | struct list_head *invalid_list) | |
4731d4c7 | 1643 | { |
60c8aec6 MT |
1644 | int i, zapped = 0; |
1645 | struct mmu_page_path parents; | |
1646 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1647 | |
60c8aec6 | 1648 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1649 | return 0; |
60c8aec6 MT |
1650 | |
1651 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1652 | while (mmu_unsync_walk(parent, &pages)) { | |
1653 | struct kvm_mmu_page *sp; | |
1654 | ||
1655 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1656 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1657 | mmu_pages_clear_parents(&parents); |
77662e00 | 1658 | zapped++; |
60c8aec6 | 1659 | } |
60c8aec6 MT |
1660 | kvm_mmu_pages_init(parent, &parents, &pages); |
1661 | } | |
1662 | ||
1663 | return zapped; | |
4731d4c7 MT |
1664 | } |
1665 | ||
7775834a XG |
1666 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1667 | struct list_head *invalid_list) | |
31aa2b44 | 1668 | { |
4731d4c7 | 1669 | int ret; |
f691fe1d | 1670 | |
7775834a | 1671 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1672 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1673 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1674 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1675 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1676 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1677 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1678 | if (sp->unsync) |
1679 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1680 | if (!sp->root_count) { |
54a4f023 GJ |
1681 | /* Count self */ |
1682 | ret++; | |
7775834a | 1683 | list_move(&sp->link, invalid_list); |
2e53d63a | 1684 | } else { |
5b5c6a5a | 1685 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1686 | kvm_reload_remote_mmus(kvm); |
1687 | } | |
7775834a XG |
1688 | |
1689 | sp->role.invalid = 1; | |
12b7d28f | 1690 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1691 | return ret; |
a436036b AK |
1692 | } |
1693 | ||
7775834a XG |
1694 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1695 | struct list_head *invalid_list) | |
1696 | { | |
1697 | struct kvm_mmu_page *sp; | |
1698 | ||
1699 | if (list_empty(invalid_list)) | |
1700 | return; | |
1701 | ||
1702 | kvm_flush_remote_tlbs(kvm); | |
1703 | ||
1704 | do { | |
1705 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1706 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1707 | kvm_mmu_free_page(kvm, sp); | |
1708 | } while (!list_empty(invalid_list)); | |
1709 | ||
1710 | } | |
1711 | ||
82ce2c96 IE |
1712 | /* |
1713 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1714 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1715 | */ |
49d5ca26 | 1716 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1717 | { |
d98ba053 | 1718 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1719 | /* |
1720 | * If we set the number of mmu pages to be smaller be than the | |
1721 | * number of actived pages , we must to free some mmu pages before we | |
1722 | * change the value | |
1723 | */ | |
1724 | ||
49d5ca26 DH |
1725 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1726 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1727 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1728 | struct kvm_mmu_page *page; |
1729 | ||
f05e70ac | 1730 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1731 | struct kvm_mmu_page, link); |
80b63faf XF |
1732 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1733 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1734 | } |
49d5ca26 | 1735 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1736 | } |
82ce2c96 | 1737 | |
49d5ca26 | 1738 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1739 | } |
1740 | ||
f67a46f4 | 1741 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1742 | { |
4db35314 | 1743 | struct kvm_mmu_page *sp; |
f41d335a | 1744 | struct hlist_node *node; |
d98ba053 | 1745 | LIST_HEAD(invalid_list); |
a436036b AK |
1746 | int r; |
1747 | ||
9ad17b10 | 1748 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1749 | r = 0; |
f41d335a XG |
1750 | |
1751 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1752 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1753 | sp->role.word); |
1754 | r = 1; | |
f41d335a | 1755 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1756 | } |
d98ba053 | 1757 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1758 | return r; |
cea0f0e7 AK |
1759 | } |
1760 | ||
f67a46f4 | 1761 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1762 | { |
4db35314 | 1763 | struct kvm_mmu_page *sp; |
f41d335a | 1764 | struct hlist_node *node; |
d98ba053 | 1765 | LIST_HEAD(invalid_list); |
97a0a01e | 1766 | |
f41d335a | 1767 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1768 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1769 | __func__, gfn, sp->role.word); |
f41d335a | 1770 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1771 | } |
d98ba053 | 1772 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1773 | } |
1774 | ||
38c335f1 | 1775 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1776 | { |
bc6678a3 | 1777 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1778 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1779 | |
291f26bc | 1780 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1781 | } |
1782 | ||
6844dec6 MT |
1783 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1784 | { | |
1785 | int i; | |
1786 | u64 *pt = sp->spt; | |
1787 | ||
1788 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1789 | return; | |
1790 | ||
1791 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1792 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1793 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1794 | } |
1795 | } | |
1796 | ||
74be52e3 SY |
1797 | /* |
1798 | * The function is based on mtrr_type_lookup() in | |
1799 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1800 | */ | |
1801 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1802 | u64 start, u64 end) | |
1803 | { | |
1804 | int i; | |
1805 | u64 base, mask; | |
1806 | u8 prev_match, curr_match; | |
1807 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1808 | ||
1809 | if (!mtrr_state->enabled) | |
1810 | return 0xFF; | |
1811 | ||
1812 | /* Make end inclusive end, instead of exclusive */ | |
1813 | end--; | |
1814 | ||
1815 | /* Look in fixed ranges. Just return the type as per start */ | |
1816 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1817 | int idx; | |
1818 | ||
1819 | if (start < 0x80000) { | |
1820 | idx = 0; | |
1821 | idx += (start >> 16); | |
1822 | return mtrr_state->fixed_ranges[idx]; | |
1823 | } else if (start < 0xC0000) { | |
1824 | idx = 1 * 8; | |
1825 | idx += ((start - 0x80000) >> 14); | |
1826 | return mtrr_state->fixed_ranges[idx]; | |
1827 | } else if (start < 0x1000000) { | |
1828 | idx = 3 * 8; | |
1829 | idx += ((start - 0xC0000) >> 12); | |
1830 | return mtrr_state->fixed_ranges[idx]; | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | /* | |
1835 | * Look in variable ranges | |
1836 | * Look of multiple ranges matching this address and pick type | |
1837 | * as per MTRR precedence | |
1838 | */ | |
1839 | if (!(mtrr_state->enabled & 2)) | |
1840 | return mtrr_state->def_type; | |
1841 | ||
1842 | prev_match = 0xFF; | |
1843 | for (i = 0; i < num_var_ranges; ++i) { | |
1844 | unsigned short start_state, end_state; | |
1845 | ||
1846 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1847 | continue; | |
1848 | ||
1849 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1850 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1851 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1852 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1853 | ||
1854 | start_state = ((start & mask) == (base & mask)); | |
1855 | end_state = ((end & mask) == (base & mask)); | |
1856 | if (start_state != end_state) | |
1857 | return 0xFE; | |
1858 | ||
1859 | if ((start & mask) != (base & mask)) | |
1860 | continue; | |
1861 | ||
1862 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1863 | if (prev_match == 0xFF) { | |
1864 | prev_match = curr_match; | |
1865 | continue; | |
1866 | } | |
1867 | ||
1868 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1869 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1870 | return MTRR_TYPE_UNCACHABLE; | |
1871 | ||
1872 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1873 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1874 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1875 | curr_match == MTRR_TYPE_WRBACK)) { | |
1876 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1877 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1878 | } | |
1879 | ||
1880 | if (prev_match != curr_match) | |
1881 | return MTRR_TYPE_UNCACHABLE; | |
1882 | } | |
1883 | ||
1884 | if (prev_match != 0xFF) | |
1885 | return prev_match; | |
1886 | ||
1887 | return mtrr_state->def_type; | |
1888 | } | |
1889 | ||
4b12f0de | 1890 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1891 | { |
1892 | u8 mtrr; | |
1893 | ||
1894 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1895 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1896 | if (mtrr == 0xfe || mtrr == 0xff) | |
1897 | mtrr = MTRR_TYPE_WRBACK; | |
1898 | return mtrr; | |
1899 | } | |
4b12f0de | 1900 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1901 | |
9cf5cf5a XG |
1902 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1903 | { | |
1904 | trace_kvm_mmu_unsync_page(sp); | |
1905 | ++vcpu->kvm->stat.mmu_unsync; | |
1906 | sp->unsync = 1; | |
1907 | ||
1908 | kvm_mmu_mark_parents_unsync(sp); | |
1909 | mmu_convert_notrap(sp); | |
1910 | } | |
1911 | ||
1912 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1913 | { |
4731d4c7 | 1914 | struct kvm_mmu_page *s; |
f41d335a | 1915 | struct hlist_node *node; |
9cf5cf5a | 1916 | |
f41d335a | 1917 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1918 | if (s->unsync) |
4731d4c7 | 1919 | continue; |
9cf5cf5a XG |
1920 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1921 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1922 | } |
4731d4c7 MT |
1923 | } |
1924 | ||
1925 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1926 | bool can_unsync) | |
1927 | { | |
9cf5cf5a | 1928 | struct kvm_mmu_page *s; |
f41d335a | 1929 | struct hlist_node *node; |
9cf5cf5a XG |
1930 | bool need_unsync = false; |
1931 | ||
f41d335a | 1932 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1933 | if (!can_unsync) |
1934 | return 1; | |
1935 | ||
9cf5cf5a | 1936 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1937 | return 1; |
9cf5cf5a XG |
1938 | |
1939 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1940 | if (!oos_shadow) |
9cf5cf5a XG |
1941 | return 1; |
1942 | need_unsync = true; | |
1943 | } | |
4731d4c7 | 1944 | } |
9cf5cf5a XG |
1945 | if (need_unsync) |
1946 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1947 | return 0; |
1948 | } | |
1949 | ||
d555c333 | 1950 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1951 | unsigned pte_access, int user_fault, |
852e3c19 | 1952 | int write_fault, int dirty, int level, |
c2d0ee46 | 1953 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1954 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1955 | { |
1956 | u64 spte; | |
1e73f9dd | 1957 | int ret = 0; |
64d4d521 | 1958 | |
1c4f1fd6 AK |
1959 | /* |
1960 | * We don't set the accessed bit, since we sometimes want to see | |
1961 | * whether the guest actually used the pte (in order to detect | |
1962 | * demand paging). | |
1963 | */ | |
4132779b | 1964 | spte = shadow_base_present_pte; |
947da538 | 1965 | if (!speculative) |
3201b5d9 | 1966 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1967 | if (!dirty) |
1968 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1969 | if (pte_access & ACC_EXEC_MASK) |
1970 | spte |= shadow_x_mask; | |
1971 | else | |
1972 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1973 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1974 | spte |= shadow_user_mask; |
852e3c19 | 1975 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1976 | spte |= PT_PAGE_SIZE_MASK; |
c5a78f2b | 1977 | if (vcpu->arch.mmu.direct_map) |
4b12f0de SY |
1978 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
1979 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1980 | |
1403283a IE |
1981 | if (reset_host_protection) |
1982 | spte |= SPTE_HOST_WRITEABLE; | |
1983 | ||
35149e21 | 1984 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1985 | |
1986 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
1987 | || (!vcpu->arch.mmu.direct_map && write_fault |
1988 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1989 | |
852e3c19 JR |
1990 | if (level > PT_PAGE_TABLE_LEVEL && |
1991 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1992 | ret = 1; |
be38d276 AK |
1993 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
1994 | goto done; | |
38187c83 MT |
1995 | } |
1996 | ||
1c4f1fd6 | 1997 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1998 | |
c5a78f2b JR |
1999 | if (!vcpu->arch.mmu.direct_map |
2000 | && !(pte_access & ACC_WRITE_MASK)) | |
69325a12 AK |
2001 | spte &= ~PT_USER_MASK; |
2002 | ||
ecc5589f MT |
2003 | /* |
2004 | * Optimization: for pte sync, if spte was writable the hash | |
2005 | * lookup is unnecessary (and expensive). Write protection | |
2006 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2007 | * Same reasoning can be applied to dirty page accounting. | |
2008 | */ | |
8dae4445 | 2009 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2010 | goto set_pte; |
2011 | ||
4731d4c7 | 2012 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2013 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2014 | __func__, gfn); |
1e73f9dd | 2015 | ret = 1; |
1c4f1fd6 | 2016 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2017 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2018 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2019 | } |
2020 | } | |
2021 | ||
1c4f1fd6 AK |
2022 | if (pte_access & ACC_WRITE_MASK) |
2023 | mark_page_dirty(vcpu->kvm, gfn); | |
2024 | ||
38187c83 | 2025 | set_pte: |
b79b93f9 | 2026 | update_spte(sptep, spte); |
be38d276 | 2027 | done: |
1e73f9dd MT |
2028 | return ret; |
2029 | } | |
2030 | ||
d555c333 | 2031 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2032 | unsigned pt_access, unsigned pte_access, |
2033 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2034 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
2035 | pfn_t pfn, bool speculative, |
2036 | bool reset_host_protection) | |
1e73f9dd MT |
2037 | { |
2038 | int was_rmapped = 0; | |
53a27b39 | 2039 | int rmap_count; |
1e73f9dd MT |
2040 | |
2041 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2042 | " user_fault %d gfn %llx\n", |
d555c333 | 2043 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2044 | write_fault, user_fault, gfn); |
2045 | ||
d555c333 | 2046 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2047 | /* |
2048 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2049 | * the parent of the now unreachable PTE. | |
2050 | */ | |
852e3c19 JR |
2051 | if (level > PT_PAGE_TABLE_LEVEL && |
2052 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2053 | struct kvm_mmu_page *child; |
d555c333 | 2054 | u64 pte = *sptep; |
1e73f9dd MT |
2055 | |
2056 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2057 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2058 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2059 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2060 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2061 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2062 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2063 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2064 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2065 | } else |
2066 | was_rmapped = 1; | |
1e73f9dd | 2067 | } |
852e3c19 | 2068 | |
d555c333 | 2069 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
2070 | dirty, level, gfn, pfn, speculative, true, |
2071 | reset_host_protection)) { | |
1e73f9dd MT |
2072 | if (write_fault) |
2073 | *ptwrite = 1; | |
5304efde | 2074 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2075 | } |
1e73f9dd | 2076 | |
d555c333 | 2077 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2078 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2079 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2080 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2081 | *sptep, sptep); | |
d555c333 | 2082 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2083 | ++vcpu->kvm->stat.lpages; |
2084 | ||
d555c333 | 2085 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2086 | if (!was_rmapped) { |
44ad9944 | 2087 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2088 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2089 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2090 | } |
9ed5520d | 2091 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2092 | if (speculative) { |
d555c333 | 2093 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2094 | vcpu->arch.last_pte_gfn = gfn; |
2095 | } | |
1c4f1fd6 AK |
2096 | } |
2097 | ||
6aa8b732 AK |
2098 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2099 | { | |
2100 | } | |
2101 | ||
957ed9ef XG |
2102 | static struct kvm_memory_slot * |
2103 | pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log) | |
2104 | { | |
2105 | struct kvm_memory_slot *slot; | |
2106 | ||
2107 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
2108 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
2109 | (no_dirty_log && slot->dirty_bitmap)) | |
2110 | slot = NULL; | |
2111 | ||
2112 | return slot; | |
2113 | } | |
2114 | ||
2115 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2116 | bool no_dirty_log) | |
2117 | { | |
2118 | struct kvm_memory_slot *slot; | |
2119 | unsigned long hva; | |
2120 | ||
2121 | slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log); | |
2122 | if (!slot) { | |
2123 | get_page(bad_page); | |
2124 | return page_to_pfn(bad_page); | |
2125 | } | |
2126 | ||
2127 | hva = gfn_to_hva_memslot(slot, gfn); | |
2128 | ||
2129 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2130 | } | |
2131 | ||
2132 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2133 | struct kvm_mmu_page *sp, | |
2134 | u64 *start, u64 *end) | |
2135 | { | |
2136 | struct page *pages[PTE_PREFETCH_NUM]; | |
2137 | unsigned access = sp->role.access; | |
2138 | int i, ret; | |
2139 | gfn_t gfn; | |
2140 | ||
2141 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
2142 | if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK)) | |
2143 | return -1; | |
2144 | ||
2145 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2146 | if (ret <= 0) | |
2147 | return -1; | |
2148 | ||
2149 | for (i = 0; i < ret; i++, gfn++, start++) | |
2150 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2151 | access, 0, 0, 1, NULL, | |
2152 | sp->role.level, gfn, | |
2153 | page_to_pfn(pages[i]), true, true); | |
2154 | ||
2155 | return 0; | |
2156 | } | |
2157 | ||
2158 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2159 | struct kvm_mmu_page *sp, u64 *sptep) | |
2160 | { | |
2161 | u64 *spte, *start = NULL; | |
2162 | int i; | |
2163 | ||
2164 | WARN_ON(!sp->role.direct); | |
2165 | ||
2166 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2167 | spte = sp->spt + i; | |
2168 | ||
2169 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2170 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2171 | if (!start) | |
2172 | continue; | |
2173 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2174 | break; | |
2175 | start = NULL; | |
2176 | } else if (!start) | |
2177 | start = spte; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2182 | { | |
2183 | struct kvm_mmu_page *sp; | |
2184 | ||
2185 | /* | |
2186 | * Since it's no accessed bit on EPT, it's no way to | |
2187 | * distinguish between actually accessed translations | |
2188 | * and prefetched, so disable pte prefetch if EPT is | |
2189 | * enabled. | |
2190 | */ | |
2191 | if (!shadow_accessed_mask) | |
2192 | return; | |
2193 | ||
2194 | sp = page_header(__pa(sptep)); | |
2195 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2196 | return; | |
2197 | ||
2198 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2199 | } | |
2200 | ||
9f652d21 | 2201 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 2202 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 2203 | { |
9f652d21 | 2204 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2205 | struct kvm_mmu_page *sp; |
9f652d21 | 2206 | int pt_write = 0; |
140754bc | 2207 | gfn_t pseudo_gfn; |
6aa8b732 | 2208 | |
9f652d21 | 2209 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2210 | if (iterator.level == level) { |
9f652d21 AK |
2211 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
2212 | 0, write, 1, &pt_write, | |
1403283a | 2213 | level, gfn, pfn, false, true); |
957ed9ef | 2214 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2215 | ++vcpu->stat.pf_fixed; |
2216 | break; | |
6aa8b732 AK |
2217 | } |
2218 | ||
9f652d21 | 2219 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2220 | u64 base_addr = iterator.addr; |
2221 | ||
2222 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2223 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2224 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2225 | iterator.level - 1, | |
2226 | 1, ACC_ALL, iterator.sptep); | |
2227 | if (!sp) { | |
2228 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2229 | kvm_release_pfn_clean(pfn); | |
2230 | return -ENOMEM; | |
2231 | } | |
140754bc | 2232 | |
d555c333 AK |
2233 | __set_spte(iterator.sptep, |
2234 | __pa(sp->spt) | |
2235 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2236 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
2237 | } |
2238 | } | |
2239 | return pt_write; | |
6aa8b732 AK |
2240 | } |
2241 | ||
bf998156 HY |
2242 | static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn) |
2243 | { | |
2244 | char buf[1]; | |
2245 | void __user *hva; | |
2246 | int r; | |
2247 | ||
2248 | /* Touch the page, so send SIGBUS */ | |
2249 | hva = (void __user *)gfn_to_hva(kvm, gfn); | |
2250 | r = copy_from_user(buf, hva, 1); | |
2251 | } | |
2252 | ||
2253 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2254 | { | |
2255 | kvm_release_pfn_clean(pfn); | |
2256 | if (is_hwpoison_pfn(pfn)) { | |
2257 | kvm_send_hwpoison_signal(kvm, gfn); | |
2258 | return 0; | |
edba23e5 GN |
2259 | } else if (is_fault_pfn(pfn)) |
2260 | return -EFAULT; | |
2261 | ||
bf998156 HY |
2262 | return 1; |
2263 | } | |
2264 | ||
10589a46 MT |
2265 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2266 | { | |
2267 | int r; | |
852e3c19 | 2268 | int level; |
35149e21 | 2269 | pfn_t pfn; |
e930bffe | 2270 | unsigned long mmu_seq; |
aaee2c94 | 2271 | |
852e3c19 JR |
2272 | level = mapping_level(vcpu, gfn); |
2273 | ||
2274 | /* | |
2275 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2276 | * maximum. Therefore check if the level is larger than that. | |
2277 | */ | |
2278 | if (level > PT_DIRECTORY_LEVEL) | |
2279 | level = PT_DIRECTORY_LEVEL; | |
2280 | ||
2281 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2282 | |
e930bffe | 2283 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2284 | smp_rmb(); |
35149e21 | 2285 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2286 | |
d196e343 | 2287 | /* mmio */ |
bf998156 HY |
2288 | if (is_error_pfn(pfn)) |
2289 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2290 | |
aaee2c94 | 2291 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2292 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2293 | goto out_unlock; | |
eb787d10 | 2294 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2295 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2296 | spin_unlock(&vcpu->kvm->mmu_lock); |
2297 | ||
aaee2c94 | 2298 | |
10589a46 | 2299 | return r; |
e930bffe AA |
2300 | |
2301 | out_unlock: | |
2302 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2303 | kvm_release_pfn_clean(pfn); | |
2304 | return 0; | |
10589a46 MT |
2305 | } |
2306 | ||
2307 | ||
17ac10ad AK |
2308 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2309 | { | |
2310 | int i; | |
4db35314 | 2311 | struct kvm_mmu_page *sp; |
d98ba053 | 2312 | LIST_HEAD(invalid_list); |
17ac10ad | 2313 | |
ad312c7c | 2314 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2315 | return; |
aaee2c94 | 2316 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2317 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2318 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2319 | |
4db35314 AK |
2320 | sp = page_header(root); |
2321 | --sp->root_count; | |
d98ba053 XG |
2322 | if (!sp->root_count && sp->role.invalid) { |
2323 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2324 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2325 | } | |
ad312c7c | 2326 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2327 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2328 | return; |
2329 | } | |
17ac10ad | 2330 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2331 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2332 | |
417726a3 | 2333 | if (root) { |
417726a3 | 2334 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2335 | sp = page_header(root); |
2336 | --sp->root_count; | |
2e53d63a | 2337 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2338 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2339 | &invalid_list); | |
417726a3 | 2340 | } |
ad312c7c | 2341 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2342 | } |
d98ba053 | 2343 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2344 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2345 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2346 | } |
2347 | ||
8986ecc0 MT |
2348 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2349 | { | |
2350 | int ret = 0; | |
2351 | ||
2352 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2353 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2354 | ret = 1; |
2355 | } | |
2356 | ||
2357 | return ret; | |
2358 | } | |
2359 | ||
2360 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2361 | { |
2362 | int i; | |
cea0f0e7 | 2363 | gfn_t root_gfn; |
4db35314 | 2364 | struct kvm_mmu_page *sp; |
f6e2c02b | 2365 | int direct = 0; |
6de4f3ad | 2366 | u64 pdptr; |
3bb65a22 | 2367 | |
5777ed34 | 2368 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2369 | |
ad312c7c ZX |
2370 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2371 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2372 | |
2373 | ASSERT(!VALID_PAGE(root)); | |
8986ecc0 MT |
2374 | if (mmu_check_root(vcpu, root_gfn)) |
2375 | return 1; | |
c5a78f2b | 2376 | if (vcpu->arch.mmu.direct_map) { |
5a7388c2 EN |
2377 | direct = 1; |
2378 | root_gfn = 0; | |
2379 | } | |
8facbbff | 2380 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2381 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2382 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2383 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2384 | ACC_ALL, NULL); |
4db35314 AK |
2385 | root = __pa(sp->spt); |
2386 | ++sp->root_count; | |
8facbbff | 2387 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2388 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2389 | return 0; |
17ac10ad | 2390 | } |
f6e2c02b | 2391 | direct = !is_paging(vcpu); |
f87f9288 JR |
2392 | |
2393 | if (mmu_check_root(vcpu, root_gfn)) | |
2394 | return 1; | |
2395 | ||
17ac10ad | 2396 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2397 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2398 | |
2399 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2400 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2401 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2402 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2403 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2404 | continue; |
2405 | } | |
6de4f3ad | 2406 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2407 | if (mmu_check_root(vcpu, root_gfn)) |
2408 | return 1; | |
ad312c7c | 2409 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2410 | root_gfn = 0; |
c5a78f2b | 2411 | if (vcpu->arch.mmu.direct_map) { |
5a7388c2 EN |
2412 | direct = 1; |
2413 | root_gfn = i << 30; | |
2414 | } | |
8facbbff | 2415 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2416 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2417 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2418 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2419 | ACC_ALL, NULL); |
4db35314 AK |
2420 | root = __pa(sp->spt); |
2421 | ++sp->root_count; | |
8facbbff AK |
2422 | spin_unlock(&vcpu->kvm->mmu_lock); |
2423 | ||
ad312c7c | 2424 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2425 | } |
ad312c7c | 2426 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2427 | return 0; |
17ac10ad AK |
2428 | } |
2429 | ||
0ba73cda MT |
2430 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2431 | { | |
2432 | int i; | |
2433 | struct kvm_mmu_page *sp; | |
2434 | ||
2435 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2436 | return; | |
2437 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2438 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2439 | sp = page_header(root); | |
2440 | mmu_sync_children(vcpu, sp); | |
2441 | return; | |
2442 | } | |
2443 | for (i = 0; i < 4; ++i) { | |
2444 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2445 | ||
8986ecc0 | 2446 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2447 | root &= PT64_BASE_ADDR_MASK; |
2448 | sp = page_header(root); | |
2449 | mmu_sync_children(vcpu, sp); | |
2450 | } | |
2451 | } | |
2452 | } | |
2453 | ||
2454 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2455 | { | |
2456 | spin_lock(&vcpu->kvm->mmu_lock); | |
2457 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2458 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2459 | } |
2460 | ||
1871c602 GN |
2461 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2462 | u32 access, u32 *error) | |
6aa8b732 | 2463 | { |
1871c602 GN |
2464 | if (error) |
2465 | *error = 0; | |
6aa8b732 AK |
2466 | return vaddr; |
2467 | } | |
2468 | ||
2469 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2470 | u32 error_code) |
6aa8b732 | 2471 | { |
e833240f | 2472 | gfn_t gfn; |
e2dec939 | 2473 | int r; |
6aa8b732 | 2474 | |
b8688d51 | 2475 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2476 | r = mmu_topup_memory_caches(vcpu); |
2477 | if (r) | |
2478 | return r; | |
714b93da | 2479 | |
6aa8b732 | 2480 | ASSERT(vcpu); |
ad312c7c | 2481 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2482 | |
e833240f | 2483 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2484 | |
e833240f AK |
2485 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2486 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2487 | } |
2488 | ||
fb72d167 JR |
2489 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2490 | u32 error_code) | |
2491 | { | |
35149e21 | 2492 | pfn_t pfn; |
fb72d167 | 2493 | int r; |
852e3c19 | 2494 | int level; |
05da4558 | 2495 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2496 | unsigned long mmu_seq; |
fb72d167 JR |
2497 | |
2498 | ASSERT(vcpu); | |
2499 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2500 | ||
2501 | r = mmu_topup_memory_caches(vcpu); | |
2502 | if (r) | |
2503 | return r; | |
2504 | ||
852e3c19 JR |
2505 | level = mapping_level(vcpu, gfn); |
2506 | ||
2507 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2508 | ||
e930bffe | 2509 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2510 | smp_rmb(); |
35149e21 | 2511 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2512 | if (is_error_pfn(pfn)) |
2513 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2514 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2515 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2516 | goto out_unlock; | |
fb72d167 JR |
2517 | kvm_mmu_free_some_pages(vcpu); |
2518 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2519 | level, gfn, pfn); |
fb72d167 | 2520 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2521 | |
2522 | return r; | |
e930bffe AA |
2523 | |
2524 | out_unlock: | |
2525 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2526 | kvm_release_pfn_clean(pfn); | |
2527 | return 0; | |
fb72d167 JR |
2528 | } |
2529 | ||
6aa8b732 AK |
2530 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2531 | { | |
17ac10ad | 2532 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2533 | } |
2534 | ||
52fde8df JR |
2535 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2536 | struct kvm_mmu *context) | |
6aa8b732 | 2537 | { |
6aa8b732 AK |
2538 | context->new_cr3 = nonpaging_new_cr3; |
2539 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2540 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2541 | context->free = nonpaging_free; | |
c7addb90 | 2542 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2543 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2544 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2545 | context->root_level = 0; |
6aa8b732 | 2546 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2547 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2548 | context->direct_map = true; |
6aa8b732 AK |
2549 | return 0; |
2550 | } | |
2551 | ||
d835dfec | 2552 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2553 | { |
1165f5fe | 2554 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2555 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2556 | } |
2557 | ||
2558 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2559 | { | |
b8688d51 | 2560 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2561 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2562 | } |
2563 | ||
5777ed34 JR |
2564 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2565 | { | |
2566 | return vcpu->arch.cr3; | |
2567 | } | |
2568 | ||
6aa8b732 AK |
2569 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2570 | u64 addr, | |
2571 | u32 err_code) | |
2572 | { | |
cb659db8 | 2573 | vcpu->arch.mmu.inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2574 | } |
2575 | ||
6aa8b732 AK |
2576 | static void paging_free(struct kvm_vcpu *vcpu) |
2577 | { | |
2578 | nonpaging_free(vcpu); | |
2579 | } | |
2580 | ||
82725b20 DE |
2581 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2582 | { | |
2583 | int bit7; | |
2584 | ||
2585 | bit7 = (gpte >> 7) & 1; | |
2586 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2587 | } | |
2588 | ||
6aa8b732 AK |
2589 | #define PTTYPE 64 |
2590 | #include "paging_tmpl.h" | |
2591 | #undef PTTYPE | |
2592 | ||
2593 | #define PTTYPE 32 | |
2594 | #include "paging_tmpl.h" | |
2595 | #undef PTTYPE | |
2596 | ||
52fde8df JR |
2597 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2598 | struct kvm_mmu *context, | |
2599 | int level) | |
82725b20 | 2600 | { |
82725b20 DE |
2601 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2602 | u64 exb_bit_rsvd = 0; | |
2603 | ||
2604 | if (!is_nx(vcpu)) | |
2605 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2606 | switch (level) { | |
2607 | case PT32_ROOT_LEVEL: | |
2608 | /* no rsvd bits for 2 level 4K page table entries */ | |
2609 | context->rsvd_bits_mask[0][1] = 0; | |
2610 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2611 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2612 | ||
2613 | if (!is_pse(vcpu)) { | |
2614 | context->rsvd_bits_mask[1][1] = 0; | |
2615 | break; | |
2616 | } | |
2617 | ||
82725b20 DE |
2618 | if (is_cpuid_PSE36()) |
2619 | /* 36bits PSE 4MB page */ | |
2620 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2621 | else | |
2622 | /* 32 bits PSE 4MB page */ | |
2623 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2624 | break; |
2625 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2626 | context->rsvd_bits_mask[0][2] = |
2627 | rsvd_bits(maxphyaddr, 63) | | |
2628 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2629 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2630 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2631 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2632 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2633 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2634 | rsvd_bits(maxphyaddr, 62) | | |
2635 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2636 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2637 | break; |
2638 | case PT64_ROOT_LEVEL: | |
2639 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2640 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2641 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2642 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2643 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2644 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2645 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2646 | rsvd_bits(maxphyaddr, 51); | |
2647 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2648 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2649 | rsvd_bits(maxphyaddr, 51) | | |
2650 | rsvd_bits(13, 29); | |
82725b20 | 2651 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2652 | rsvd_bits(maxphyaddr, 51) | |
2653 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2654 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2655 | break; |
2656 | } | |
2657 | } | |
2658 | ||
52fde8df JR |
2659 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2660 | struct kvm_mmu *context, | |
2661 | int level) | |
6aa8b732 | 2662 | { |
52fde8df | 2663 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2664 | |
2665 | ASSERT(is_pae(vcpu)); | |
2666 | context->new_cr3 = paging_new_cr3; | |
2667 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2668 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2669 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2670 | context->sync_page = paging64_sync_page; |
a7052897 | 2671 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2672 | context->free = paging_free; |
17ac10ad AK |
2673 | context->root_level = level; |
2674 | context->shadow_root_level = level; | |
17c3ba9d | 2675 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2676 | context->direct_map = false; |
6aa8b732 AK |
2677 | return 0; |
2678 | } | |
2679 | ||
52fde8df JR |
2680 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2681 | struct kvm_mmu *context) | |
17ac10ad | 2682 | { |
52fde8df | 2683 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2684 | } |
2685 | ||
52fde8df JR |
2686 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2687 | struct kvm_mmu *context) | |
6aa8b732 | 2688 | { |
52fde8df | 2689 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2690 | |
2691 | context->new_cr3 = paging_new_cr3; | |
2692 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2693 | context->gva_to_gpa = paging32_gva_to_gpa; |
2694 | context->free = paging_free; | |
c7addb90 | 2695 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2696 | context->sync_page = paging32_sync_page; |
a7052897 | 2697 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2698 | context->root_level = PT32_ROOT_LEVEL; |
2699 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2700 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2701 | context->direct_map = false; |
6aa8b732 AK |
2702 | return 0; |
2703 | } | |
2704 | ||
52fde8df JR |
2705 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2706 | struct kvm_mmu *context) | |
6aa8b732 | 2707 | { |
52fde8df | 2708 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2709 | } |
2710 | ||
fb72d167 JR |
2711 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2712 | { | |
2713 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2714 | ||
2715 | context->new_cr3 = nonpaging_new_cr3; | |
2716 | context->page_fault = tdp_page_fault; | |
2717 | context->free = nonpaging_free; | |
2718 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2719 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2720 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2721 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2722 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2723 | context->direct_map = true; |
1c97f0a0 | 2724 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2725 | context->get_cr3 = get_cr3; |
cb659db8 | 2726 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
2727 | |
2728 | if (!is_paging(vcpu)) { | |
2729 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2730 | context->root_level = 0; | |
2731 | } else if (is_long_mode(vcpu)) { | |
52fde8df | 2732 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
2733 | context->gva_to_gpa = paging64_gva_to_gpa; |
2734 | context->root_level = PT64_ROOT_LEVEL; | |
2735 | } else if (is_pae(vcpu)) { | |
52fde8df | 2736 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2737 | context->gva_to_gpa = paging64_gva_to_gpa; |
2738 | context->root_level = PT32E_ROOT_LEVEL; | |
2739 | } else { | |
52fde8df | 2740 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
2741 | context->gva_to_gpa = paging32_gva_to_gpa; |
2742 | context->root_level = PT32_ROOT_LEVEL; | |
2743 | } | |
2744 | ||
2745 | return 0; | |
2746 | } | |
2747 | ||
52fde8df | 2748 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 2749 | { |
a770f6f2 | 2750 | int r; |
6aa8b732 | 2751 | ASSERT(vcpu); |
ad312c7c | 2752 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2753 | |
2754 | if (!is_paging(vcpu)) | |
52fde8df | 2755 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 2756 | else if (is_long_mode(vcpu)) |
52fde8df | 2757 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 2758 | else if (is_pae(vcpu)) |
52fde8df | 2759 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 2760 | else |
52fde8df | 2761 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 2762 | |
5b7e0102 | 2763 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 2764 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
52fde8df JR |
2765 | |
2766 | return r; | |
2767 | } | |
2768 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
2769 | ||
2770 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
2771 | { | |
2772 | int r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
2773 | ||
f43addd4 | 2774 | vcpu->arch.mmu.set_cr3 = kvm_x86_ops->set_cr3; |
5777ed34 | 2775 | vcpu->arch.mmu.get_cr3 = get_cr3; |
cb659db8 | 2776 | vcpu->arch.mmu.inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
2777 | |
2778 | return r; | |
6aa8b732 AK |
2779 | } |
2780 | ||
fb72d167 JR |
2781 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2782 | { | |
35149e21 AL |
2783 | vcpu->arch.update_pte.pfn = bad_pfn; |
2784 | ||
fb72d167 JR |
2785 | if (tdp_enabled) |
2786 | return init_kvm_tdp_mmu(vcpu); | |
2787 | else | |
2788 | return init_kvm_softmmu(vcpu); | |
2789 | } | |
2790 | ||
6aa8b732 AK |
2791 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2792 | { | |
2793 | ASSERT(vcpu); | |
62ad0755 SY |
2794 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2795 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2796 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2797 | } |
2798 | ||
2799 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2800 | { |
2801 | destroy_kvm_mmu(vcpu); | |
2802 | return init_kvm_mmu(vcpu); | |
2803 | } | |
8668a3c4 | 2804 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2805 | |
2806 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2807 | { |
714b93da AK |
2808 | int r; |
2809 | ||
e2dec939 | 2810 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2811 | if (r) |
2812 | goto out; | |
8986ecc0 | 2813 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2814 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2815 | mmu_sync_roots(vcpu); |
aaee2c94 | 2816 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2817 | if (r) |
2818 | goto out; | |
3662cb1c | 2819 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 2820 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2821 | out: |
2822 | return r; | |
6aa8b732 | 2823 | } |
17c3ba9d AK |
2824 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2825 | ||
2826 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2827 | { | |
2828 | mmu_free_roots(vcpu); | |
2829 | } | |
6aa8b732 | 2830 | |
09072daf | 2831 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2832 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2833 | u64 *spte) |
2834 | { | |
2835 | u64 pte; | |
2836 | struct kvm_mmu_page *child; | |
2837 | ||
2838 | pte = *spte; | |
c7addb90 | 2839 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2840 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 2841 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
2842 | else { |
2843 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2844 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2845 | } |
2846 | } | |
d555c333 | 2847 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2848 | if (is_large_pte(pte)) |
2849 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2850 | } |
2851 | ||
0028425f | 2852 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2853 | struct kvm_mmu_page *sp, |
0028425f | 2854 | u64 *spte, |
489f1d65 | 2855 | const void *new) |
0028425f | 2856 | { |
30945387 | 2857 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2858 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2859 | return; | |
30945387 | 2860 | } |
0028425f | 2861 | |
fa1de2bf XG |
2862 | if (is_rsvd_bits_set(vcpu, *(u64 *)new, PT_PAGE_TABLE_LEVEL)) |
2863 | return; | |
2864 | ||
4cee5764 | 2865 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 2866 | if (!sp->role.cr4_pae) |
489f1d65 | 2867 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2868 | else |
489f1d65 | 2869 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2870 | } |
2871 | ||
79539cec AK |
2872 | static bool need_remote_flush(u64 old, u64 new) |
2873 | { | |
2874 | if (!is_shadow_present_pte(old)) | |
2875 | return false; | |
2876 | if (!is_shadow_present_pte(new)) | |
2877 | return true; | |
2878 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2879 | return true; | |
2880 | old ^= PT64_NX_MASK; | |
2881 | new ^= PT64_NX_MASK; | |
2882 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2883 | } | |
2884 | ||
0671a8e7 XG |
2885 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
2886 | bool remote_flush, bool local_flush) | |
79539cec | 2887 | { |
0671a8e7 XG |
2888 | if (zap_page) |
2889 | return; | |
2890 | ||
2891 | if (remote_flush) | |
79539cec | 2892 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 2893 | else if (local_flush) |
79539cec AK |
2894 | kvm_mmu_flush_tlb(vcpu); |
2895 | } | |
2896 | ||
12b7d28f AK |
2897 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2898 | { | |
ad312c7c | 2899 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2900 | |
7b52345e | 2901 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2902 | } |
2903 | ||
d7824fff | 2904 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2905 | u64 gpte) |
d7824fff AK |
2906 | { |
2907 | gfn_t gfn; | |
35149e21 | 2908 | pfn_t pfn; |
d7824fff | 2909 | |
43a3795a | 2910 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2911 | return; |
2912 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2913 | |
e930bffe | 2914 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2915 | smp_rmb(); |
35149e21 | 2916 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2917 | |
35149e21 AL |
2918 | if (is_error_pfn(pfn)) { |
2919 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2920 | return; |
2921 | } | |
d7824fff | 2922 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2923 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2924 | } |
2925 | ||
1b7fcd32 AK |
2926 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2927 | { | |
2928 | u64 *spte = vcpu->arch.last_pte_updated; | |
2929 | ||
2930 | if (spte | |
2931 | && vcpu->arch.last_pte_gfn == gfn | |
2932 | && shadow_accessed_mask | |
2933 | && !(*spte & shadow_accessed_mask) | |
2934 | && is_shadow_present_pte(*spte)) | |
2935 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2936 | } | |
2937 | ||
09072daf | 2938 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2939 | const u8 *new, int bytes, |
2940 | bool guest_initiated) | |
da4a00f0 | 2941 | { |
9b7a0325 | 2942 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 2943 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 2944 | struct kvm_mmu_page *sp; |
f41d335a | 2945 | struct hlist_node *node; |
d98ba053 | 2946 | LIST_HEAD(invalid_list); |
489f1d65 | 2947 | u64 entry, gentry; |
9b7a0325 | 2948 | u64 *spte; |
9b7a0325 | 2949 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2950 | unsigned pte_size; |
9b7a0325 | 2951 | unsigned page_offset; |
0e7bc4b9 | 2952 | unsigned misaligned; |
fce0657f | 2953 | unsigned quadrant; |
9b7a0325 | 2954 | int level; |
86a5ba02 | 2955 | int flooded = 0; |
ac1b714e | 2956 | int npte; |
489f1d65 | 2957 | int r; |
08e850c6 | 2958 | int invlpg_counter; |
0671a8e7 XG |
2959 | bool remote_flush, local_flush, zap_page; |
2960 | ||
2961 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 2962 | |
b8688d51 | 2963 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2964 | |
08e850c6 | 2965 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2966 | |
2967 | /* | |
2968 | * Assume that the pte write on a page table of the same type | |
2969 | * as the current vcpu paging mode. This is nearly always true | |
2970 | * (might be false while changing modes). Note it is verified later | |
2971 | * by update_pte(). | |
2972 | */ | |
08e850c6 | 2973 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2974 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2975 | if (is_pae(vcpu)) { |
2976 | gpa &= ~(gpa_t)7; | |
2977 | bytes = 8; | |
2978 | } | |
2979 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2980 | if (r) |
2981 | gentry = 0; | |
08e850c6 AK |
2982 | new = (const u8 *)&gentry; |
2983 | } | |
2984 | ||
2985 | switch (bytes) { | |
2986 | case 4: | |
2987 | gentry = *(const u32 *)new; | |
2988 | break; | |
2989 | case 8: | |
2990 | gentry = *(const u64 *)new; | |
2991 | break; | |
2992 | default: | |
2993 | gentry = 0; | |
2994 | break; | |
72016f3a AK |
2995 | } |
2996 | ||
2997 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2998 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2999 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3000 | gentry = 0; | |
1b7fcd32 | 3001 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 3002 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3003 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3004 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 MT |
3005 | if (guest_initiated) { |
3006 | if (gfn == vcpu->arch.last_pt_write_gfn | |
3007 | && !last_updated_pte_accessed(vcpu)) { | |
3008 | ++vcpu->arch.last_pt_write_count; | |
3009 | if (vcpu->arch.last_pt_write_count >= 3) | |
3010 | flooded = 1; | |
3011 | } else { | |
3012 | vcpu->arch.last_pt_write_gfn = gfn; | |
3013 | vcpu->arch.last_pt_write_count = 1; | |
3014 | vcpu->arch.last_pte_updated = NULL; | |
3015 | } | |
86a5ba02 | 3016 | } |
3246af0e | 3017 | |
fa1de2bf | 3018 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3019 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3020 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3021 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3022 | misaligned |= bytes < 4; |
86a5ba02 | 3023 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3024 | /* |
3025 | * Misaligned accesses are too much trouble to fix | |
3026 | * up; also, they usually indicate a page is not used | |
3027 | * as a page table. | |
86a5ba02 AK |
3028 | * |
3029 | * If we're seeing too many writes to a page, | |
3030 | * it may no longer be a page table, or we may be | |
3031 | * forking, in which case it is better to unmap the | |
3032 | * page. | |
0e7bc4b9 AK |
3033 | */ |
3034 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3035 | gpa, bytes, sp->role.word); |
0671a8e7 | 3036 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3037 | &invalid_list); |
4cee5764 | 3038 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3039 | continue; |
3040 | } | |
9b7a0325 | 3041 | page_offset = offset; |
4db35314 | 3042 | level = sp->role.level; |
ac1b714e | 3043 | npte = 1; |
5b7e0102 | 3044 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3045 | page_offset <<= 1; /* 32->64 */ |
3046 | /* | |
3047 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3048 | * only 2MB. So we need to double the offset again | |
3049 | * and zap two pdes instead of one. | |
3050 | */ | |
3051 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3052 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3053 | page_offset <<= 1; |
3054 | npte = 2; | |
3055 | } | |
fce0657f | 3056 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3057 | page_offset &= ~PAGE_MASK; |
4db35314 | 3058 | if (quadrant != sp->role.quadrant) |
fce0657f | 3059 | continue; |
9b7a0325 | 3060 | } |
0671a8e7 | 3061 | local_flush = true; |
4db35314 | 3062 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3063 | while (npte--) { |
79539cec | 3064 | entry = *spte; |
4db35314 | 3065 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3066 | if (gentry && |
3067 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3068 | & mask.word)) | |
72016f3a | 3069 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3070 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3071 | remote_flush = true; | |
ac1b714e | 3072 | ++spte; |
9b7a0325 | 3073 | } |
9b7a0325 | 3074 | } |
0671a8e7 | 3075 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3076 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3077 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3078 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
3079 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
3080 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
3081 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 3082 | } |
da4a00f0 AK |
3083 | } |
3084 | ||
a436036b AK |
3085 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3086 | { | |
10589a46 MT |
3087 | gpa_t gpa; |
3088 | int r; | |
a436036b | 3089 | |
c5a78f2b | 3090 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3091 | return 0; |
3092 | ||
1871c602 | 3093 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3094 | |
aaee2c94 | 3095 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3096 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3097 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3098 | return r; |
a436036b | 3099 | } |
577bdc49 | 3100 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3101 | |
22d95b12 | 3102 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3103 | { |
d98ba053 | 3104 | LIST_HEAD(invalid_list); |
103ad25a | 3105 | |
e0df7b9f | 3106 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3107 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3108 | struct kvm_mmu_page *sp; |
ebeace86 | 3109 | |
f05e70ac | 3110 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3111 | struct kvm_mmu_page, link); |
e0df7b9f | 3112 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3113 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3114 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3115 | } |
3116 | } | |
ebeace86 | 3117 | |
3067714c AK |
3118 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
3119 | { | |
3120 | int r; | |
3121 | enum emulation_result er; | |
3122 | ||
ad312c7c | 3123 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
3124 | if (r < 0) |
3125 | goto out; | |
3126 | ||
3127 | if (!r) { | |
3128 | r = 1; | |
3129 | goto out; | |
3130 | } | |
3131 | ||
b733bfb5 AK |
3132 | r = mmu_topup_memory_caches(vcpu); |
3133 | if (r) | |
3134 | goto out; | |
3135 | ||
851ba692 | 3136 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
3137 | |
3138 | switch (er) { | |
3139 | case EMULATE_DONE: | |
3140 | return 1; | |
3141 | case EMULATE_DO_MMIO: | |
3142 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3143 | /* fall through */ |
3067714c | 3144 | case EMULATE_FAIL: |
3f5d18a9 | 3145 | return 0; |
3067714c AK |
3146 | default: |
3147 | BUG(); | |
3148 | } | |
3149 | out: | |
3067714c AK |
3150 | return r; |
3151 | } | |
3152 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3153 | ||
a7052897 MT |
3154 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3155 | { | |
a7052897 | 3156 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3157 | kvm_mmu_flush_tlb(vcpu); |
3158 | ++vcpu->stat.invlpg; | |
3159 | } | |
3160 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3161 | ||
18552672 JR |
3162 | void kvm_enable_tdp(void) |
3163 | { | |
3164 | tdp_enabled = true; | |
3165 | } | |
3166 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3167 | ||
5f4cb662 JR |
3168 | void kvm_disable_tdp(void) |
3169 | { | |
3170 | tdp_enabled = false; | |
3171 | } | |
3172 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3173 | ||
6aa8b732 AK |
3174 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3175 | { | |
ad312c7c | 3176 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
3177 | } |
3178 | ||
3179 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3180 | { | |
17ac10ad | 3181 | struct page *page; |
6aa8b732 AK |
3182 | int i; |
3183 | ||
3184 | ASSERT(vcpu); | |
3185 | ||
17ac10ad AK |
3186 | /* |
3187 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3188 | * Therefore we need to allocate shadow page tables in the first | |
3189 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3190 | */ | |
3191 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3192 | if (!page) | |
d7fa6ab2 WY |
3193 | return -ENOMEM; |
3194 | ||
ad312c7c | 3195 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3196 | for (i = 0; i < 4; ++i) |
ad312c7c | 3197 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3198 | |
6aa8b732 | 3199 | return 0; |
6aa8b732 AK |
3200 | } |
3201 | ||
8018c27b | 3202 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3203 | { |
6aa8b732 | 3204 | ASSERT(vcpu); |
ad312c7c | 3205 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3206 | |
8018c27b IM |
3207 | return alloc_mmu_pages(vcpu); |
3208 | } | |
6aa8b732 | 3209 | |
8018c27b IM |
3210 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3211 | { | |
3212 | ASSERT(vcpu); | |
ad312c7c | 3213 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3214 | |
8018c27b | 3215 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3216 | } |
3217 | ||
3218 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3219 | { | |
3220 | ASSERT(vcpu); | |
3221 | ||
3222 | destroy_kvm_mmu(vcpu); | |
3223 | free_mmu_pages(vcpu); | |
714b93da | 3224 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
3225 | } |
3226 | ||
90cb0529 | 3227 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3228 | { |
4db35314 | 3229 | struct kvm_mmu_page *sp; |
6aa8b732 | 3230 | |
f05e70ac | 3231 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3232 | int i; |
3233 | u64 *pt; | |
3234 | ||
291f26bc | 3235 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3236 | continue; |
3237 | ||
4db35314 | 3238 | pt = sp->spt; |
6aa8b732 AK |
3239 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3240 | /* avoid RMW */ | |
01c168ac | 3241 | if (is_writable_pte(pt[i])) |
6aa8b732 | 3242 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 3243 | } |
171d595d | 3244 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3245 | } |
37a7d8b0 | 3246 | |
90cb0529 | 3247 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3248 | { |
4db35314 | 3249 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3250 | LIST_HEAD(invalid_list); |
e0fa826f | 3251 | |
aaee2c94 | 3252 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3253 | restart: |
f05e70ac | 3254 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3255 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3256 | goto restart; |
3257 | ||
d98ba053 | 3258 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3259 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3260 | } |
3261 | ||
d98ba053 XG |
3262 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3263 | struct list_head *invalid_list) | |
3ee16c81 IE |
3264 | { |
3265 | struct kvm_mmu_page *page; | |
3266 | ||
3267 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3268 | struct kvm_mmu_page, link); | |
d98ba053 | 3269 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3270 | } |
3271 | ||
7f8275d0 | 3272 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3273 | { |
3274 | struct kvm *kvm; | |
3275 | struct kvm *kvm_freed = NULL; | |
45221ab6 DH |
3276 | |
3277 | if (nr_to_scan == 0) | |
3278 | goto out; | |
3ee16c81 IE |
3279 | |
3280 | spin_lock(&kvm_lock); | |
3281 | ||
3282 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3283 | int idx, freed_pages; |
d98ba053 | 3284 | LIST_HEAD(invalid_list); |
3ee16c81 | 3285 | |
f656ce01 | 3286 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3287 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3288 | if (!kvm_freed && nr_to_scan > 0 && |
3289 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3290 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3291 | &invalid_list); | |
3ee16c81 IE |
3292 | kvm_freed = kvm; |
3293 | } | |
3294 | nr_to_scan--; | |
3295 | ||
d98ba053 | 3296 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3297 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3298 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3299 | } |
3300 | if (kvm_freed) | |
3301 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3302 | ||
3303 | spin_unlock(&kvm_lock); | |
3304 | ||
45221ab6 DH |
3305 | out: |
3306 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3307 | } |
3308 | ||
3309 | static struct shrinker mmu_shrinker = { | |
3310 | .shrink = mmu_shrink, | |
3311 | .seeks = DEFAULT_SEEKS * 10, | |
3312 | }; | |
3313 | ||
2ddfd20e | 3314 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3315 | { |
3316 | if (pte_chain_cache) | |
3317 | kmem_cache_destroy(pte_chain_cache); | |
3318 | if (rmap_desc_cache) | |
3319 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3320 | if (mmu_page_header_cache) |
3321 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3322 | } |
3323 | ||
3ee16c81 IE |
3324 | void kvm_mmu_module_exit(void) |
3325 | { | |
3326 | mmu_destroy_caches(); | |
45bf21a8 | 3327 | percpu_counter_destroy(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
3328 | unregister_shrinker(&mmu_shrinker); |
3329 | } | |
3330 | ||
b5a33a75 AK |
3331 | int kvm_mmu_module_init(void) |
3332 | { | |
3333 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3334 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3335 | 0, 0, NULL); |
b5a33a75 AK |
3336 | if (!pte_chain_cache) |
3337 | goto nomem; | |
3338 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3339 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3340 | 0, 0, NULL); |
b5a33a75 AK |
3341 | if (!rmap_desc_cache) |
3342 | goto nomem; | |
3343 | ||
d3d25b04 AK |
3344 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3345 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3346 | 0, 0, NULL); |
d3d25b04 AK |
3347 | if (!mmu_page_header_cache) |
3348 | goto nomem; | |
3349 | ||
45bf21a8 WY |
3350 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3351 | goto nomem; | |
3352 | ||
3ee16c81 IE |
3353 | register_shrinker(&mmu_shrinker); |
3354 | ||
b5a33a75 AK |
3355 | return 0; |
3356 | ||
3357 | nomem: | |
3ee16c81 | 3358 | mmu_destroy_caches(); |
b5a33a75 AK |
3359 | return -ENOMEM; |
3360 | } | |
3361 | ||
3ad82a7e ZX |
3362 | /* |
3363 | * Caculate mmu pages needed for kvm. | |
3364 | */ | |
3365 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3366 | { | |
3367 | int i; | |
3368 | unsigned int nr_mmu_pages; | |
3369 | unsigned int nr_pages = 0; | |
bc6678a3 | 3370 | struct kvm_memslots *slots; |
3ad82a7e | 3371 | |
90d83dc3 LJ |
3372 | slots = kvm_memslots(kvm); |
3373 | ||
bc6678a3 MT |
3374 | for (i = 0; i < slots->nmemslots; i++) |
3375 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3376 | |
3377 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3378 | nr_mmu_pages = max(nr_mmu_pages, | |
3379 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3380 | ||
3381 | return nr_mmu_pages; | |
3382 | } | |
3383 | ||
2f333bcb MT |
3384 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3385 | unsigned len) | |
3386 | { | |
3387 | if (len > buffer->len) | |
3388 | return NULL; | |
3389 | return buffer->ptr; | |
3390 | } | |
3391 | ||
3392 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3393 | unsigned len) | |
3394 | { | |
3395 | void *ret; | |
3396 | ||
3397 | ret = pv_mmu_peek_buffer(buffer, len); | |
3398 | if (!ret) | |
3399 | return ret; | |
3400 | buffer->ptr += len; | |
3401 | buffer->len -= len; | |
3402 | buffer->processed += len; | |
3403 | return ret; | |
3404 | } | |
3405 | ||
3406 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3407 | gpa_t addr, gpa_t value) | |
3408 | { | |
3409 | int bytes = 8; | |
3410 | int r; | |
3411 | ||
3412 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3413 | bytes = 4; | |
3414 | ||
3415 | r = mmu_topup_memory_caches(vcpu); | |
3416 | if (r) | |
3417 | return r; | |
3418 | ||
3200f405 | 3419 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3420 | return -EFAULT; |
3421 | ||
3422 | return 1; | |
3423 | } | |
3424 | ||
3425 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3426 | { | |
2390218b | 3427 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3428 | return 1; |
3429 | } | |
3430 | ||
3431 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3432 | { | |
3433 | spin_lock(&vcpu->kvm->mmu_lock); | |
3434 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3435 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3436 | return 1; | |
3437 | } | |
3438 | ||
3439 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3440 | struct kvm_pv_mmu_op_buffer *buffer) | |
3441 | { | |
3442 | struct kvm_mmu_op_header *header; | |
3443 | ||
3444 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3445 | if (!header) | |
3446 | return 0; | |
3447 | switch (header->op) { | |
3448 | case KVM_MMU_OP_WRITE_PTE: { | |
3449 | struct kvm_mmu_op_write_pte *wpte; | |
3450 | ||
3451 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3452 | if (!wpte) | |
3453 | return 0; | |
3454 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3455 | wpte->pte_val); | |
3456 | } | |
3457 | case KVM_MMU_OP_FLUSH_TLB: { | |
3458 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3459 | ||
3460 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3461 | if (!ftlb) | |
3462 | return 0; | |
3463 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3464 | } | |
3465 | case KVM_MMU_OP_RELEASE_PT: { | |
3466 | struct kvm_mmu_op_release_pt *rpt; | |
3467 | ||
3468 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3469 | if (!rpt) | |
3470 | return 0; | |
3471 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3472 | } | |
3473 | default: return 0; | |
3474 | } | |
3475 | } | |
3476 | ||
3477 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3478 | gpa_t addr, unsigned long *ret) | |
3479 | { | |
3480 | int r; | |
6ad18fba | 3481 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3482 | |
6ad18fba DH |
3483 | buffer->ptr = buffer->buf; |
3484 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3485 | buffer->processed = 0; | |
2f333bcb | 3486 | |
6ad18fba | 3487 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3488 | if (r) |
3489 | goto out; | |
3490 | ||
6ad18fba DH |
3491 | while (buffer->len) { |
3492 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3493 | if (r < 0) |
3494 | goto out; | |
3495 | if (r == 0) | |
3496 | break; | |
3497 | } | |
3498 | ||
3499 | r = 1; | |
3500 | out: | |
6ad18fba | 3501 | *ret = buffer->processed; |
2f333bcb MT |
3502 | return r; |
3503 | } | |
3504 | ||
94d8b056 MT |
3505 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3506 | { | |
3507 | struct kvm_shadow_walk_iterator iterator; | |
3508 | int nr_sptes = 0; | |
3509 | ||
3510 | spin_lock(&vcpu->kvm->mmu_lock); | |
3511 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3512 | sptes[iterator.level-1] = *iterator.sptep; | |
3513 | nr_sptes++; | |
3514 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3515 | break; | |
3516 | } | |
3517 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3518 | ||
3519 | return nr_sptes; | |
3520 | } | |
3521 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3522 | ||
8b1fe17c | 3523 | #ifdef CONFIG_KVM_MMU_AUDIT |
2f4f3372 | 3524 | #include "mmu_audit.c" |
37a7d8b0 | 3525 | #endif |