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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 113 | |
6aa8b732 AK |
114 | #define PT64_INDEX(address, level)\ |
115 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
118 | #define PT32_LEVEL_BITS 10 | |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
27aba766 | 131 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
132 | #define PT64_DIR_BASE_ADDR_MASK \ |
133 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT64_LVL_ADDR_MASK(level) \ |
135 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT64_LEVEL_BITS))) - 1)) | |
137 | #define PT64_LVL_OFFSET_MASK(level) \ | |
138 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
140 | |
141 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
142 | #define PT32_DIR_BASE_ADDR_MASK \ | |
143 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
144 | #define PT32_LVL_ADDR_MASK(level) \ |
145 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
146 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 147 | |
79539cec AK |
148 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
149 | | PT64_NX_MASK) | |
6aa8b732 | 150 | |
53c07b18 | 151 | #define PTE_LIST_EXT 4 |
cd4a4e53 | 152 | |
fe135d2c AK |
153 | #define ACC_EXEC_MASK 1 |
154 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
155 | #define ACC_USER_MASK PT_USER_MASK | |
156 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
157 | ||
90bb6fc5 AK |
158 | #include <trace/events/kvm.h> |
159 | ||
07420171 AK |
160 | #define CREATE_TRACE_POINTS |
161 | #include "mmutrace.h" | |
162 | ||
1403283a IE |
163 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
164 | ||
135f8c2b AK |
165 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
166 | ||
53c07b18 XG |
167 | struct pte_list_desc { |
168 | u64 *sptes[PTE_LIST_EXT]; | |
169 | struct pte_list_desc *more; | |
cd4a4e53 AK |
170 | }; |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
175 | int level; | |
176 | u64 *sptep; | |
177 | unsigned index; | |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
1047df1f | 185 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 186 | |
b5a33a75 | 187 | static struct kmem_cache *pte_chain_cache; |
53c07b18 | 188 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 189 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 190 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 191 | |
c7addb90 AK |
192 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
193 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
194 | static u64 __read_mostly shadow_nx_mask; |
195 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
196 | static u64 __read_mostly shadow_user_mask; | |
197 | static u64 __read_mostly shadow_accessed_mask; | |
198 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 199 | |
82725b20 DE |
200 | static inline u64 rsvd_bits(int s, int e) |
201 | { | |
202 | return ((1ULL << (e - s + 1)) - 1) << s; | |
203 | } | |
204 | ||
c7addb90 AK |
205 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
206 | { | |
207 | shadow_trap_nonpresent_pte = trap_pte; | |
208 | shadow_notrap_nonpresent_pte = notrap_pte; | |
209 | } | |
210 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
211 | ||
7b52345e | 212 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 213 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
214 | { |
215 | shadow_user_mask = user_mask; | |
216 | shadow_accessed_mask = accessed_mask; | |
217 | shadow_dirty_mask = dirty_mask; | |
218 | shadow_nx_mask = nx_mask; | |
219 | shadow_x_mask = x_mask; | |
220 | } | |
221 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
222 | ||
3dbe1415 | 223 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 224 | { |
4d4ec087 | 225 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
226 | } |
227 | ||
228 | static int is_cpuid_PSE36(void) | |
229 | { | |
230 | return 1; | |
231 | } | |
232 | ||
73b1087e AK |
233 | static int is_nx(struct kvm_vcpu *vcpu) |
234 | { | |
f6801dff | 235 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
236 | } |
237 | ||
c7addb90 AK |
238 | static int is_shadow_present_pte(u64 pte) |
239 | { | |
c7addb90 AK |
240 | return pte != shadow_trap_nonpresent_pte |
241 | && pte != shadow_notrap_nonpresent_pte; | |
242 | } | |
243 | ||
05da4558 MT |
244 | static int is_large_pte(u64 pte) |
245 | { | |
246 | return pte & PT_PAGE_SIZE_MASK; | |
247 | } | |
248 | ||
8dae4445 | 249 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
250 | { |
251 | return pte & PT_WRITABLE_MASK; | |
252 | } | |
253 | ||
43a3795a | 254 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 255 | { |
439e218a | 256 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
257 | } |
258 | ||
43a3795a | 259 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 260 | { |
4b1a80fa | 261 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
262 | } |
263 | ||
776e6633 MT |
264 | static int is_last_spte(u64 pte, int level) |
265 | { | |
266 | if (level == PT_PAGE_TABLE_LEVEL) | |
267 | return 1; | |
852e3c19 | 268 | if (is_large_pte(pte)) |
776e6633 MT |
269 | return 1; |
270 | return 0; | |
271 | } | |
272 | ||
35149e21 | 273 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 274 | { |
35149e21 | 275 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
276 | } |
277 | ||
da928521 AK |
278 | static gfn_t pse36_gfn_delta(u32 gpte) |
279 | { | |
280 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
281 | ||
282 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
283 | } | |
284 | ||
d555c333 | 285 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 286 | { |
7645e432 | 287 | set_64bit(sptep, spte); |
e663ee64 AK |
288 | } |
289 | ||
a9221dd5 AK |
290 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
291 | { | |
292 | #ifdef CONFIG_X86_64 | |
293 | return xchg(sptep, new_spte); | |
294 | #else | |
295 | u64 old_spte; | |
296 | ||
297 | do { | |
298 | old_spte = *sptep; | |
299 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
300 | ||
301 | return old_spte; | |
302 | #endif | |
303 | } | |
304 | ||
8672b721 XG |
305 | static bool spte_has_volatile_bits(u64 spte) |
306 | { | |
307 | if (!shadow_accessed_mask) | |
308 | return false; | |
309 | ||
310 | if (!is_shadow_present_pte(spte)) | |
311 | return false; | |
312 | ||
4132779b XG |
313 | if ((spte & shadow_accessed_mask) && |
314 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
315 | return false; |
316 | ||
317 | return true; | |
318 | } | |
319 | ||
4132779b XG |
320 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
321 | { | |
322 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
323 | } | |
324 | ||
b79b93f9 AK |
325 | static void update_spte(u64 *sptep, u64 new_spte) |
326 | { | |
4132779b XG |
327 | u64 mask, old_spte = *sptep; |
328 | ||
329 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 330 | |
4132779b XG |
331 | new_spte |= old_spte & shadow_dirty_mask; |
332 | ||
333 | mask = shadow_accessed_mask; | |
334 | if (is_writable_pte(old_spte)) | |
335 | mask |= shadow_dirty_mask; | |
336 | ||
337 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 338 | __set_spte(sptep, new_spte); |
4132779b | 339 | else |
b79b93f9 | 340 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
341 | |
342 | if (!shadow_accessed_mask) | |
343 | return; | |
344 | ||
345 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
346 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
347 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
348 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
349 | } |
350 | ||
e2dec939 | 351 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 352 | struct kmem_cache *base_cache, int min) |
714b93da AK |
353 | { |
354 | void *obj; | |
355 | ||
356 | if (cache->nobjs >= min) | |
e2dec939 | 357 | return 0; |
714b93da | 358 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 359 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 360 | if (!obj) |
e2dec939 | 361 | return -ENOMEM; |
714b93da AK |
362 | cache->objects[cache->nobjs++] = obj; |
363 | } | |
e2dec939 | 364 | return 0; |
714b93da AK |
365 | } |
366 | ||
e8ad9a70 XG |
367 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
368 | struct kmem_cache *cache) | |
714b93da AK |
369 | { |
370 | while (mc->nobjs) | |
e8ad9a70 | 371 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
372 | } |
373 | ||
c1158e63 | 374 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 375 | int min) |
c1158e63 | 376 | { |
842f22ed | 377 | void *page; |
c1158e63 AK |
378 | |
379 | if (cache->nobjs >= min) | |
380 | return 0; | |
381 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 382 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
383 | if (!page) |
384 | return -ENOMEM; | |
842f22ed | 385 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
386 | } |
387 | return 0; | |
388 | } | |
389 | ||
390 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
391 | { | |
392 | while (mc->nobjs) | |
c4d198d5 | 393 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
394 | } |
395 | ||
2e3e5882 | 396 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 397 | { |
e2dec939 AK |
398 | int r; |
399 | ||
ad312c7c | 400 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 401 | pte_chain_cache, 4); |
e2dec939 AK |
402 | if (r) |
403 | goto out; | |
53c07b18 XG |
404 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
405 | pte_list_desc_cache, 4 + PTE_PREFETCH_NUM); | |
d3d25b04 AK |
406 | if (r) |
407 | goto out; | |
ad312c7c | 408 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
409 | if (r) |
410 | goto out; | |
ad312c7c | 411 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 412 | mmu_page_header_cache, 4); |
e2dec939 AK |
413 | out: |
414 | return r; | |
714b93da AK |
415 | } |
416 | ||
417 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
418 | { | |
53c07b18 XG |
419 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
420 | pte_chain_cache); | |
421 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, | |
422 | pte_list_desc_cache); | |
ad312c7c | 423 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
424 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
425 | mmu_page_header_cache); | |
714b93da AK |
426 | } |
427 | ||
428 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
429 | size_t size) | |
430 | { | |
431 | void *p; | |
432 | ||
433 | BUG_ON(!mc->nobjs); | |
434 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
435 | return p; |
436 | } | |
437 | ||
714b93da AK |
438 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
439 | { | |
ad312c7c | 440 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
441 | sizeof(struct kvm_pte_chain)); |
442 | } | |
443 | ||
90cb0529 | 444 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 445 | { |
e8ad9a70 | 446 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
447 | } |
448 | ||
53c07b18 | 449 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 450 | { |
53c07b18 XG |
451 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
452 | sizeof(struct pte_list_desc)); | |
714b93da AK |
453 | } |
454 | ||
53c07b18 | 455 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 456 | { |
53c07b18 | 457 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
458 | } |
459 | ||
2032a93d LJ |
460 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
461 | { | |
462 | if (!sp->role.direct) | |
463 | return sp->gfns[index]; | |
464 | ||
465 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
466 | } | |
467 | ||
468 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
469 | { | |
470 | if (sp->role.direct) | |
471 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
472 | else | |
473 | sp->gfns[index] = gfn; | |
474 | } | |
475 | ||
05da4558 | 476 | /* |
d4dbf470 TY |
477 | * Return the pointer to the large page information for a given gfn, |
478 | * handling slots that are not large page aligned. | |
05da4558 | 479 | */ |
d4dbf470 TY |
480 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
481 | struct kvm_memory_slot *slot, | |
482 | int level) | |
05da4558 MT |
483 | { |
484 | unsigned long idx; | |
485 | ||
82855413 JR |
486 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
487 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d4dbf470 | 488 | return &slot->lpage_info[level - 2][idx]; |
05da4558 MT |
489 | } |
490 | ||
491 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
492 | { | |
d25797b2 | 493 | struct kvm_memory_slot *slot; |
d4dbf470 | 494 | struct kvm_lpage_info *linfo; |
d25797b2 | 495 | int i; |
05da4558 | 496 | |
a1f4d395 | 497 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
498 | for (i = PT_DIRECTORY_LEVEL; |
499 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
500 | linfo = lpage_info_slot(gfn, slot, i); |
501 | linfo->write_count += 1; | |
d25797b2 | 502 | } |
332b207d | 503 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
504 | } |
505 | ||
506 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
507 | { | |
d25797b2 | 508 | struct kvm_memory_slot *slot; |
d4dbf470 | 509 | struct kvm_lpage_info *linfo; |
d25797b2 | 510 | int i; |
05da4558 | 511 | |
a1f4d395 | 512 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
513 | for (i = PT_DIRECTORY_LEVEL; |
514 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
515 | linfo = lpage_info_slot(gfn, slot, i); |
516 | linfo->write_count -= 1; | |
517 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 518 | } |
332b207d | 519 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
520 | } |
521 | ||
d25797b2 JR |
522 | static int has_wrprotected_page(struct kvm *kvm, |
523 | gfn_t gfn, | |
524 | int level) | |
05da4558 | 525 | { |
2843099f | 526 | struct kvm_memory_slot *slot; |
d4dbf470 | 527 | struct kvm_lpage_info *linfo; |
05da4558 | 528 | |
a1f4d395 | 529 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 530 | if (slot) { |
d4dbf470 TY |
531 | linfo = lpage_info_slot(gfn, slot, level); |
532 | return linfo->write_count; | |
05da4558 MT |
533 | } |
534 | ||
535 | return 1; | |
536 | } | |
537 | ||
d25797b2 | 538 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 539 | { |
8f0b1ab6 | 540 | unsigned long page_size; |
d25797b2 | 541 | int i, ret = 0; |
05da4558 | 542 | |
8f0b1ab6 | 543 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 544 | |
d25797b2 JR |
545 | for (i = PT_PAGE_TABLE_LEVEL; |
546 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
547 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
548 | ret = i; | |
549 | else | |
550 | break; | |
551 | } | |
552 | ||
4c2155ce | 553 | return ret; |
05da4558 MT |
554 | } |
555 | ||
5d163b1c XG |
556 | static struct kvm_memory_slot * |
557 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
558 | bool no_dirty_log) | |
05da4558 MT |
559 | { |
560 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
561 | |
562 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
563 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
564 | (no_dirty_log && slot->dirty_bitmap)) | |
565 | slot = NULL; | |
566 | ||
567 | return slot; | |
568 | } | |
569 | ||
570 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
571 | { | |
a0a8eaba | 572 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
573 | } |
574 | ||
575 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
576 | { | |
577 | int host_level, level, max_level; | |
05da4558 | 578 | |
d25797b2 JR |
579 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
580 | ||
581 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
582 | return host_level; | |
583 | ||
878403b7 SY |
584 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
585 | kvm_x86_ops->get_lpage_level() : host_level; | |
586 | ||
587 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
588 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
589 | break; | |
d25797b2 JR |
590 | |
591 | return level - 1; | |
05da4558 MT |
592 | } |
593 | ||
290fc38d | 594 | /* |
53c07b18 | 595 | * Pte mapping structures: |
cd4a4e53 | 596 | * |
53c07b18 | 597 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 598 | * |
53c07b18 XG |
599 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
600 | * pte_list_desc containing more mappings. | |
53a27b39 | 601 | * |
53c07b18 | 602 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
603 | * the spte was not added. |
604 | * | |
cd4a4e53 | 605 | */ |
53c07b18 XG |
606 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
607 | unsigned long *pte_list) | |
cd4a4e53 | 608 | { |
53c07b18 | 609 | struct pte_list_desc *desc; |
53a27b39 | 610 | int i, count = 0; |
cd4a4e53 | 611 | |
53c07b18 XG |
612 | if (!*pte_list) { |
613 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
614 | *pte_list = (unsigned long)spte; | |
615 | } else if (!(*pte_list & 1)) { | |
616 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
617 | desc = mmu_alloc_pte_list_desc(vcpu); | |
618 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 619 | desc->sptes[1] = spte; |
53c07b18 | 620 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 621 | ++count; |
cd4a4e53 | 622 | } else { |
53c07b18 XG |
623 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
624 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
625 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 626 | desc = desc->more; |
53c07b18 | 627 | count += PTE_LIST_EXT; |
53a27b39 | 628 | } |
53c07b18 XG |
629 | if (desc->sptes[PTE_LIST_EXT-1]) { |
630 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
631 | desc = desc->more; |
632 | } | |
d555c333 | 633 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 634 | ++count; |
d555c333 | 635 | desc->sptes[i] = spte; |
cd4a4e53 | 636 | } |
53a27b39 | 637 | return count; |
cd4a4e53 AK |
638 | } |
639 | ||
53c07b18 XG |
640 | static u64 *pte_list_next(unsigned long *pte_list, u64 *spte) |
641 | { | |
642 | struct pte_list_desc *desc; | |
643 | u64 *prev_spte; | |
644 | int i; | |
645 | ||
646 | if (!*pte_list) | |
647 | return NULL; | |
648 | else if (!(*pte_list & 1)) { | |
649 | if (!spte) | |
650 | return (u64 *)*pte_list; | |
651 | return NULL; | |
652 | } | |
653 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
654 | prev_spte = NULL; | |
655 | while (desc) { | |
656 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { | |
657 | if (prev_spte == spte) | |
658 | return desc->sptes[i]; | |
659 | prev_spte = desc->sptes[i]; | |
660 | } | |
661 | desc = desc->more; | |
662 | } | |
663 | return NULL; | |
664 | } | |
665 | ||
666 | static void | |
667 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
668 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
669 | { |
670 | int j; | |
671 | ||
53c07b18 | 672 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 673 | ; |
d555c333 AK |
674 | desc->sptes[i] = desc->sptes[j]; |
675 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
676 | if (j != 0) |
677 | return; | |
678 | if (!prev_desc && !desc->more) | |
53c07b18 | 679 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
680 | else |
681 | if (prev_desc) | |
682 | prev_desc->more = desc->more; | |
683 | else | |
53c07b18 XG |
684 | *pte_list = (unsigned long)desc->more | 1; |
685 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
686 | } |
687 | ||
53c07b18 | 688 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 689 | { |
53c07b18 XG |
690 | struct pte_list_desc *desc; |
691 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
692 | int i; |
693 | ||
53c07b18 XG |
694 | if (!*pte_list) { |
695 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 696 | BUG(); |
53c07b18 XG |
697 | } else if (!(*pte_list & 1)) { |
698 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
699 | if ((u64 *)*pte_list != spte) { | |
700 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
701 | BUG(); |
702 | } | |
53c07b18 | 703 | *pte_list = 0; |
cd4a4e53 | 704 | } else { |
53c07b18 XG |
705 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
706 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
707 | prev_desc = NULL; |
708 | while (desc) { | |
53c07b18 | 709 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 710 | if (desc->sptes[i] == spte) { |
53c07b18 | 711 | pte_list_desc_remove_entry(pte_list, |
714b93da | 712 | desc, i, |
cd4a4e53 AK |
713 | prev_desc); |
714 | return; | |
715 | } | |
716 | prev_desc = desc; | |
717 | desc = desc->more; | |
718 | } | |
53c07b18 | 719 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
720 | BUG(); |
721 | } | |
722 | } | |
723 | ||
53c07b18 XG |
724 | /* |
725 | * Take gfn and return the reverse mapping to it. | |
726 | */ | |
727 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
728 | { | |
729 | struct kvm_memory_slot *slot; | |
730 | struct kvm_lpage_info *linfo; | |
731 | ||
732 | slot = gfn_to_memslot(kvm, gfn); | |
733 | if (likely(level == PT_PAGE_TABLE_LEVEL)) | |
734 | return &slot->rmap[gfn - slot->base_gfn]; | |
735 | ||
736 | linfo = lpage_info_slot(gfn, slot, level); | |
737 | ||
738 | return &linfo->rmap_pde; | |
739 | } | |
740 | ||
741 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) | |
742 | { | |
743 | struct kvm_mmu_page *sp; | |
744 | unsigned long *rmapp; | |
745 | ||
746 | if (!is_rmap_spte(*spte)) | |
747 | return 0; | |
748 | ||
749 | sp = page_header(__pa(spte)); | |
750 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
751 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
752 | return pte_list_add(vcpu, spte, rmapp); | |
753 | } | |
754 | ||
755 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) | |
756 | { | |
757 | return pte_list_next(rmapp, spte); | |
758 | } | |
759 | ||
760 | static void rmap_remove(struct kvm *kvm, u64 *spte) | |
761 | { | |
762 | struct kvm_mmu_page *sp; | |
763 | gfn_t gfn; | |
764 | unsigned long *rmapp; | |
765 | ||
766 | sp = page_header(__pa(spte)); | |
767 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
768 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
769 | pte_list_remove(spte, rmapp); | |
770 | } | |
771 | ||
eb45fda4 | 772 | static int set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 773 | { |
ce061867 | 774 | pfn_t pfn; |
9a3aad70 XG |
775 | u64 old_spte = *sptep; |
776 | ||
8672b721 | 777 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 778 | __set_spte(sptep, new_spte); |
8672b721 | 779 | else |
9a3aad70 | 780 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 781 | |
a9221dd5 | 782 | if (!is_rmap_spte(old_spte)) |
eb45fda4 | 783 | return 0; |
8672b721 | 784 | |
a9221dd5 | 785 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 786 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 787 | kvm_set_pfn_accessed(pfn); |
4132779b | 788 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 789 | kvm_set_pfn_dirty(pfn); |
eb45fda4 | 790 | return 1; |
e4b502ea XG |
791 | } |
792 | ||
793 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
794 | { | |
eb45fda4 MT |
795 | if (set_spte_track_bits(sptep, new_spte)) |
796 | rmap_remove(kvm, sptep); | |
be38d276 AK |
797 | } |
798 | ||
b1a36821 | 799 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 800 | { |
290fc38d | 801 | unsigned long *rmapp; |
374cbac0 | 802 | u64 *spte; |
44ad9944 | 803 | int i, write_protected = 0; |
374cbac0 | 804 | |
44ad9944 | 805 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 806 | |
98348e95 IE |
807 | spte = rmap_next(kvm, rmapp, NULL); |
808 | while (spte) { | |
374cbac0 | 809 | BUG_ON(!spte); |
374cbac0 | 810 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 811 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 812 | if (is_writable_pte(*spte)) { |
b79b93f9 | 813 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
814 | write_protected = 1; |
815 | } | |
9647c14c | 816 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 817 | } |
855149aa | 818 | |
05da4558 | 819 | /* check for huge page mappings */ |
44ad9944 JR |
820 | for (i = PT_DIRECTORY_LEVEL; |
821 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
822 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
823 | spte = rmap_next(kvm, rmapp, NULL); | |
824 | while (spte) { | |
825 | BUG_ON(!spte); | |
826 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
827 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
828 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 829 | if (is_writable_pte(*spte)) { |
be38d276 AK |
830 | drop_spte(kvm, spte, |
831 | shadow_trap_nonpresent_pte); | |
44ad9944 | 832 | --kvm->stat.lpages; |
44ad9944 JR |
833 | spte = NULL; |
834 | write_protected = 1; | |
835 | } | |
836 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 837 | } |
05da4558 MT |
838 | } |
839 | ||
b1a36821 | 840 | return write_protected; |
374cbac0 AK |
841 | } |
842 | ||
8a8365c5 FD |
843 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
844 | unsigned long data) | |
e930bffe AA |
845 | { |
846 | u64 *spte; | |
847 | int need_tlb_flush = 0; | |
848 | ||
849 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
850 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
851 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 852 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
853 | need_tlb_flush = 1; |
854 | } | |
855 | return need_tlb_flush; | |
856 | } | |
857 | ||
8a8365c5 FD |
858 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
859 | unsigned long data) | |
3da0dd43 IE |
860 | { |
861 | int need_flush = 0; | |
e4b502ea | 862 | u64 *spte, new_spte; |
3da0dd43 IE |
863 | pte_t *ptep = (pte_t *)data; |
864 | pfn_t new_pfn; | |
865 | ||
866 | WARN_ON(pte_huge(*ptep)); | |
867 | new_pfn = pte_pfn(*ptep); | |
868 | spte = rmap_next(kvm, rmapp, NULL); | |
869 | while (spte) { | |
870 | BUG_ON(!is_shadow_present_pte(*spte)); | |
871 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
872 | need_flush = 1; | |
873 | if (pte_write(*ptep)) { | |
be38d276 | 874 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
875 | spte = rmap_next(kvm, rmapp, NULL); |
876 | } else { | |
877 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
878 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
879 | ||
880 | new_spte &= ~PT_WRITABLE_MASK; | |
881 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 882 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 883 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
884 | spte = rmap_next(kvm, rmapp, spte); |
885 | } | |
886 | } | |
887 | if (need_flush) | |
888 | kvm_flush_remote_tlbs(kvm); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
8a8365c5 FD |
893 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
894 | unsigned long data, | |
3da0dd43 | 895 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 896 | unsigned long data)) |
e930bffe | 897 | { |
852e3c19 | 898 | int i, j; |
90bb6fc5 | 899 | int ret; |
e930bffe | 900 | int retval = 0; |
bc6678a3 MT |
901 | struct kvm_memslots *slots; |
902 | ||
90d83dc3 | 903 | slots = kvm_memslots(kvm); |
e930bffe | 904 | |
46a26bf5 MT |
905 | for (i = 0; i < slots->nmemslots; i++) { |
906 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
907 | unsigned long start = memslot->userspace_addr; |
908 | unsigned long end; | |
909 | ||
e930bffe AA |
910 | end = start + (memslot->npages << PAGE_SHIFT); |
911 | if (hva >= start && hva < end) { | |
912 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 913 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 914 | |
90bb6fc5 | 915 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
916 | |
917 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
918 | struct kvm_lpage_info *linfo; |
919 | ||
920 | linfo = lpage_info_slot(gfn, memslot, | |
921 | PT_DIRECTORY_LEVEL + j); | |
922 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 923 | } |
90bb6fc5 AK |
924 | trace_kvm_age_page(hva, memslot, ret); |
925 | retval |= ret; | |
e930bffe AA |
926 | } |
927 | } | |
928 | ||
929 | return retval; | |
930 | } | |
931 | ||
932 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
933 | { | |
3da0dd43 IE |
934 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
935 | } | |
936 | ||
937 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
938 | { | |
8a8365c5 | 939 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
940 | } |
941 | ||
8a8365c5 FD |
942 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
943 | unsigned long data) | |
e930bffe AA |
944 | { |
945 | u64 *spte; | |
946 | int young = 0; | |
947 | ||
6316e1c8 RR |
948 | /* |
949 | * Emulate the accessed bit for EPT, by checking if this page has | |
950 | * an EPT mapping, and clearing it if it does. On the next access, | |
951 | * a new EPT mapping will be established. | |
952 | * This has some overhead, but not as much as the cost of swapping | |
953 | * out actively used pages or breaking up actively used hugepages. | |
954 | */ | |
534e38b4 | 955 | if (!shadow_accessed_mask) |
6316e1c8 | 956 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 957 | |
e930bffe AA |
958 | spte = rmap_next(kvm, rmapp, NULL); |
959 | while (spte) { | |
960 | int _young; | |
961 | u64 _spte = *spte; | |
962 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
963 | _young = _spte & PT_ACCESSED_MASK; | |
964 | if (_young) { | |
965 | young = 1; | |
966 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
967 | } | |
968 | spte = rmap_next(kvm, rmapp, spte); | |
969 | } | |
970 | return young; | |
971 | } | |
972 | ||
8ee53820 AA |
973 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
974 | unsigned long data) | |
975 | { | |
976 | u64 *spte; | |
977 | int young = 0; | |
978 | ||
979 | /* | |
980 | * If there's no access bit in the secondary pte set by the | |
981 | * hardware it's up to gup-fast/gup to set the access bit in | |
982 | * the primary pte or in the page structure. | |
983 | */ | |
984 | if (!shadow_accessed_mask) | |
985 | goto out; | |
986 | ||
987 | spte = rmap_next(kvm, rmapp, NULL); | |
988 | while (spte) { | |
989 | u64 _spte = *spte; | |
990 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
991 | young = _spte & PT_ACCESSED_MASK; | |
992 | if (young) { | |
993 | young = 1; | |
994 | break; | |
995 | } | |
996 | spte = rmap_next(kvm, rmapp, spte); | |
997 | } | |
998 | out: | |
999 | return young; | |
1000 | } | |
1001 | ||
53a27b39 MT |
1002 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1003 | ||
852e3c19 | 1004 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1005 | { |
1006 | unsigned long *rmapp; | |
852e3c19 JR |
1007 | struct kvm_mmu_page *sp; |
1008 | ||
1009 | sp = page_header(__pa(spte)); | |
53a27b39 | 1010 | |
852e3c19 | 1011 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1012 | |
3da0dd43 | 1013 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1014 | kvm_flush_remote_tlbs(vcpu->kvm); |
1015 | } | |
1016 | ||
e930bffe AA |
1017 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1018 | { | |
3da0dd43 | 1019 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1020 | } |
1021 | ||
8ee53820 AA |
1022 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1023 | { | |
1024 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1025 | } | |
1026 | ||
d6c69ee9 | 1027 | #ifdef MMU_DEBUG |
47ad8e68 | 1028 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1029 | { |
139bdb2d AK |
1030 | u64 *pos; |
1031 | u64 *end; | |
1032 | ||
47ad8e68 | 1033 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1034 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1035 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1036 | pos, *pos); |
6aa8b732 | 1037 | return 0; |
139bdb2d | 1038 | } |
6aa8b732 AK |
1039 | return 1; |
1040 | } | |
d6c69ee9 | 1041 | #endif |
6aa8b732 | 1042 | |
45221ab6 DH |
1043 | /* |
1044 | * This value is the sum of all of the kvm instances's | |
1045 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1046 | * aggregate version in order to make the slab shrinker | |
1047 | * faster | |
1048 | */ | |
1049 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1050 | { | |
1051 | kvm->arch.n_used_mmu_pages += nr; | |
1052 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1053 | } | |
1054 | ||
4db35314 | 1055 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 1056 | { |
4db35314 | 1057 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1058 | hlist_del(&sp->hash_link); |
4db35314 | 1059 | list_del(&sp->link); |
842f22ed | 1060 | free_page((unsigned long)sp->spt); |
2032a93d | 1061 | if (!sp->role.direct) |
842f22ed | 1062 | free_page((unsigned long)sp->gfns); |
e8ad9a70 | 1063 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 1064 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
1065 | } |
1066 | ||
cea0f0e7 AK |
1067 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1068 | { | |
1ae0a13d | 1069 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1070 | } |
1071 | ||
25c0de2c | 1072 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1073 | u64 *parent_pte, int direct) |
6aa8b732 | 1074 | { |
4db35314 | 1075 | struct kvm_mmu_page *sp; |
6aa8b732 | 1076 | |
ad312c7c ZX |
1077 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1078 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1079 | if (!direct) |
1080 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1081 | PAGE_SIZE); | |
4db35314 | 1082 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1083 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1084 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1085 | sp->multimapped = 0; |
1086 | sp->parent_pte = parent_pte; | |
45221ab6 | 1087 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1088 | return sp; |
6aa8b732 AK |
1089 | } |
1090 | ||
714b93da | 1091 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1092 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1093 | { |
1094 | struct kvm_pte_chain *pte_chain; | |
1095 | struct hlist_node *node; | |
1096 | int i; | |
1097 | ||
1098 | if (!parent_pte) | |
1099 | return; | |
4db35314 AK |
1100 | if (!sp->multimapped) { |
1101 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1102 | |
1103 | if (!old) { | |
4db35314 | 1104 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1105 | return; |
1106 | } | |
4db35314 | 1107 | sp->multimapped = 1; |
714b93da | 1108 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1109 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1110 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1111 | pte_chain->parent_ptes[0] = old; |
1112 | } | |
4db35314 | 1113 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1114 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1115 | continue; | |
1116 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1117 | if (!pte_chain->parent_ptes[i]) { | |
1118 | pte_chain->parent_ptes[i] = parent_pte; | |
1119 | return; | |
1120 | } | |
1121 | } | |
714b93da | 1122 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1123 | BUG_ON(!pte_chain); |
4db35314 | 1124 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1125 | pte_chain->parent_ptes[0] = parent_pte; |
1126 | } | |
1127 | ||
4db35314 | 1128 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1129 | u64 *parent_pte) |
1130 | { | |
1131 | struct kvm_pte_chain *pte_chain; | |
1132 | struct hlist_node *node; | |
1133 | int i; | |
1134 | ||
4db35314 AK |
1135 | if (!sp->multimapped) { |
1136 | BUG_ON(sp->parent_pte != parent_pte); | |
1137 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1138 | return; |
1139 | } | |
4db35314 | 1140 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1141 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1142 | if (!pte_chain->parent_ptes[i]) | |
1143 | break; | |
1144 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1145 | continue; | |
697fe2e2 AK |
1146 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1147 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1148 | pte_chain->parent_ptes[i] |
1149 | = pte_chain->parent_ptes[i + 1]; | |
1150 | ++i; | |
1151 | } | |
1152 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1153 | if (i == 0) { |
1154 | hlist_del(&pte_chain->link); | |
90cb0529 | 1155 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1156 | if (hlist_empty(&sp->parent_ptes)) { |
1157 | sp->multimapped = 0; | |
1158 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1159 | } |
1160 | } | |
cea0f0e7 AK |
1161 | return; |
1162 | } | |
1163 | BUG(); | |
1164 | } | |
1165 | ||
6b18493d | 1166 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1167 | { |
1168 | struct kvm_pte_chain *pte_chain; | |
1169 | struct hlist_node *node; | |
1170 | struct kvm_mmu_page *parent_sp; | |
1171 | int i; | |
1172 | ||
1173 | if (!sp->multimapped && sp->parent_pte) { | |
1174 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1175 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1176 | return; |
1177 | } | |
1047df1f | 1178 | |
ad8cfbe3 MT |
1179 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1180 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1181 | u64 *spte = pte_chain->parent_ptes[i]; |
1182 | ||
1183 | if (!spte) | |
ad8cfbe3 | 1184 | break; |
1047df1f XG |
1185 | parent_sp = page_header(__pa(spte)); |
1186 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1187 | } |
1188 | } | |
1189 | ||
1047df1f XG |
1190 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1191 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1192 | { |
1047df1f | 1193 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1194 | } |
1195 | ||
1047df1f | 1196 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1197 | { |
1047df1f | 1198 | unsigned int index; |
0074ff63 | 1199 | |
1047df1f XG |
1200 | index = spte - sp->spt; |
1201 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1202 | return; |
1047df1f | 1203 | if (sp->unsync_children++) |
0074ff63 | 1204 | return; |
1047df1f | 1205 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1206 | } |
1207 | ||
d761a501 AK |
1208 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1209 | struct kvm_mmu_page *sp) | |
1210 | { | |
1211 | int i; | |
1212 | ||
1213 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1214 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1215 | } | |
1216 | ||
e8bc217a | 1217 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1218 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1219 | { |
1220 | return 1; | |
1221 | } | |
1222 | ||
a7052897 MT |
1223 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1224 | { | |
1225 | } | |
1226 | ||
0f53b5b1 XG |
1227 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1228 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1229 | const void *pte) |
0f53b5b1 XG |
1230 | { |
1231 | WARN_ON(1); | |
1232 | } | |
1233 | ||
60c8aec6 MT |
1234 | #define KVM_PAGE_ARRAY_NR 16 |
1235 | ||
1236 | struct kvm_mmu_pages { | |
1237 | struct mmu_page_and_offset { | |
1238 | struct kvm_mmu_page *sp; | |
1239 | unsigned int idx; | |
1240 | } page[KVM_PAGE_ARRAY_NR]; | |
1241 | unsigned int nr; | |
1242 | }; | |
1243 | ||
0074ff63 MT |
1244 | #define for_each_unsync_children(bitmap, idx) \ |
1245 | for (idx = find_first_bit(bitmap, 512); \ | |
1246 | idx < 512; \ | |
1247 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1248 | ||
cded19f3 HE |
1249 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1250 | int idx) | |
4731d4c7 | 1251 | { |
60c8aec6 | 1252 | int i; |
4731d4c7 | 1253 | |
60c8aec6 MT |
1254 | if (sp->unsync) |
1255 | for (i=0; i < pvec->nr; i++) | |
1256 | if (pvec->page[i].sp == sp) | |
1257 | return 0; | |
1258 | ||
1259 | pvec->page[pvec->nr].sp = sp; | |
1260 | pvec->page[pvec->nr].idx = idx; | |
1261 | pvec->nr++; | |
1262 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1263 | } | |
1264 | ||
1265 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1266 | struct kvm_mmu_pages *pvec) | |
1267 | { | |
1268 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1269 | |
0074ff63 | 1270 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1271 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1272 | u64 ent = sp->spt[i]; |
1273 | ||
7a8f1a74 XG |
1274 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1275 | goto clear_child_bitmap; | |
1276 | ||
1277 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1278 | ||
1279 | if (child->unsync_children) { | |
1280 | if (mmu_pages_add(pvec, child, i)) | |
1281 | return -ENOSPC; | |
1282 | ||
1283 | ret = __mmu_unsync_walk(child, pvec); | |
1284 | if (!ret) | |
1285 | goto clear_child_bitmap; | |
1286 | else if (ret > 0) | |
1287 | nr_unsync_leaf += ret; | |
1288 | else | |
1289 | return ret; | |
1290 | } else if (child->unsync) { | |
1291 | nr_unsync_leaf++; | |
1292 | if (mmu_pages_add(pvec, child, i)) | |
1293 | return -ENOSPC; | |
1294 | } else | |
1295 | goto clear_child_bitmap; | |
1296 | ||
1297 | continue; | |
1298 | ||
1299 | clear_child_bitmap: | |
1300 | __clear_bit(i, sp->unsync_child_bitmap); | |
1301 | sp->unsync_children--; | |
1302 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1303 | } |
1304 | ||
4731d4c7 | 1305 | |
60c8aec6 MT |
1306 | return nr_unsync_leaf; |
1307 | } | |
1308 | ||
1309 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1310 | struct kvm_mmu_pages *pvec) | |
1311 | { | |
1312 | if (!sp->unsync_children) | |
1313 | return 0; | |
1314 | ||
1315 | mmu_pages_add(pvec, sp, 0); | |
1316 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1317 | } |
1318 | ||
4731d4c7 MT |
1319 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1320 | { | |
1321 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1322 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1323 | sp->unsync = 0; |
1324 | --kvm->stat.mmu_unsync; | |
1325 | } | |
1326 | ||
7775834a XG |
1327 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1328 | struct list_head *invalid_list); | |
1329 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1330 | struct list_head *invalid_list); | |
4731d4c7 | 1331 | |
f41d335a XG |
1332 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1333 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1334 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1335 | if ((sp)->gfn != (gfn)) {} else | |
1336 | ||
f41d335a XG |
1337 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1338 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1339 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1340 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1341 | (sp)->role.invalid) {} else | |
1342 | ||
f918b443 | 1343 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1344 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1345 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1346 | { |
5b7e0102 | 1347 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1348 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1349 | return 1; |
1350 | } | |
1351 | ||
f918b443 | 1352 | if (clear_unsync) |
1d9dc7e0 | 1353 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1354 | |
a4a8e6f7 | 1355 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1356 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1357 | return 1; |
1358 | } | |
1359 | ||
1360 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1361 | return 0; |
1362 | } | |
1363 | ||
1d9dc7e0 XG |
1364 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1365 | struct kvm_mmu_page *sp) | |
1366 | { | |
d98ba053 | 1367 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1368 | int ret; |
1369 | ||
d98ba053 | 1370 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1371 | if (ret) |
d98ba053 XG |
1372 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1373 | ||
1d9dc7e0 XG |
1374 | return ret; |
1375 | } | |
1376 | ||
d98ba053 XG |
1377 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1378 | struct list_head *invalid_list) | |
1d9dc7e0 | 1379 | { |
d98ba053 | 1380 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1381 | } |
1382 | ||
9f1a122f XG |
1383 | /* @gfn should be write-protected at the call site */ |
1384 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1385 | { | |
9f1a122f | 1386 | struct kvm_mmu_page *s; |
f41d335a | 1387 | struct hlist_node *node; |
d98ba053 | 1388 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1389 | bool flush = false; |
1390 | ||
f41d335a | 1391 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1392 | if (!s->unsync) |
9f1a122f XG |
1393 | continue; |
1394 | ||
1395 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1396 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1397 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1398 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1399 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1400 | continue; |
1401 | } | |
9f1a122f XG |
1402 | flush = true; |
1403 | } | |
1404 | ||
d98ba053 | 1405 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1406 | if (flush) |
1407 | kvm_mmu_flush_tlb(vcpu); | |
1408 | } | |
1409 | ||
60c8aec6 MT |
1410 | struct mmu_page_path { |
1411 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1412 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1413 | }; |
1414 | ||
60c8aec6 MT |
1415 | #define for_each_sp(pvec, sp, parents, i) \ |
1416 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1417 | sp = pvec.page[i].sp; \ | |
1418 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1419 | i = mmu_pages_next(&pvec, &parents, i)) | |
1420 | ||
cded19f3 HE |
1421 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1422 | struct mmu_page_path *parents, | |
1423 | int i) | |
60c8aec6 MT |
1424 | { |
1425 | int n; | |
1426 | ||
1427 | for (n = i+1; n < pvec->nr; n++) { | |
1428 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1429 | ||
1430 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1431 | parents->idx[0] = pvec->page[n].idx; | |
1432 | return n; | |
1433 | } | |
1434 | ||
1435 | parents->parent[sp->role.level-2] = sp; | |
1436 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1437 | } | |
1438 | ||
1439 | return n; | |
1440 | } | |
1441 | ||
cded19f3 | 1442 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1443 | { |
60c8aec6 MT |
1444 | struct kvm_mmu_page *sp; |
1445 | unsigned int level = 0; | |
1446 | ||
1447 | do { | |
1448 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1449 | |
60c8aec6 MT |
1450 | sp = parents->parent[level]; |
1451 | if (!sp) | |
1452 | return; | |
1453 | ||
1454 | --sp->unsync_children; | |
1455 | WARN_ON((int)sp->unsync_children < 0); | |
1456 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1457 | level++; | |
1458 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1459 | } |
1460 | ||
60c8aec6 MT |
1461 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1462 | struct mmu_page_path *parents, | |
1463 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1464 | { |
60c8aec6 MT |
1465 | parents->parent[parent->role.level-1] = NULL; |
1466 | pvec->nr = 0; | |
1467 | } | |
4731d4c7 | 1468 | |
60c8aec6 MT |
1469 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1470 | struct kvm_mmu_page *parent) | |
1471 | { | |
1472 | int i; | |
1473 | struct kvm_mmu_page *sp; | |
1474 | struct mmu_page_path parents; | |
1475 | struct kvm_mmu_pages pages; | |
d98ba053 | 1476 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1477 | |
1478 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1479 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1480 | int protected = 0; |
1481 | ||
1482 | for_each_sp(pages, sp, parents, i) | |
1483 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1484 | ||
1485 | if (protected) | |
1486 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1487 | ||
60c8aec6 | 1488 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1489 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1490 | mmu_pages_clear_parents(&parents); |
1491 | } | |
d98ba053 | 1492 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1493 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1494 | kvm_mmu_pages_init(parent, &parents, &pages); |
1495 | } | |
4731d4c7 MT |
1496 | } |
1497 | ||
cea0f0e7 AK |
1498 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1499 | gfn_t gfn, | |
1500 | gva_t gaddr, | |
1501 | unsigned level, | |
f6e2c02b | 1502 | int direct, |
41074d07 | 1503 | unsigned access, |
f7d9c7b7 | 1504 | u64 *parent_pte) |
cea0f0e7 AK |
1505 | { |
1506 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1507 | unsigned quadrant; |
9f1a122f | 1508 | struct kvm_mmu_page *sp; |
f41d335a | 1509 | struct hlist_node *node; |
9f1a122f | 1510 | bool need_sync = false; |
cea0f0e7 | 1511 | |
a770f6f2 | 1512 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1513 | role.level = level; |
f6e2c02b | 1514 | role.direct = direct; |
84b0c8c6 | 1515 | if (role.direct) |
5b7e0102 | 1516 | role.cr4_pae = 0; |
41074d07 | 1517 | role.access = access; |
c5a78f2b JR |
1518 | if (!vcpu->arch.mmu.direct_map |
1519 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1520 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1521 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1522 | role.quadrant = quadrant; | |
1523 | } | |
f41d335a | 1524 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1525 | if (!need_sync && sp->unsync) |
1526 | need_sync = true; | |
4731d4c7 | 1527 | |
7ae680eb XG |
1528 | if (sp->role.word != role.word) |
1529 | continue; | |
4731d4c7 | 1530 | |
7ae680eb XG |
1531 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1532 | break; | |
e02aa901 | 1533 | |
7ae680eb XG |
1534 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1535 | if (sp->unsync_children) { | |
a8eeb04a | 1536 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1537 | kvm_mmu_mark_parents_unsync(sp); |
1538 | } else if (sp->unsync) | |
1539 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1540 | |
7ae680eb XG |
1541 | trace_kvm_mmu_get_page(sp, false); |
1542 | return sp; | |
1543 | } | |
dfc5aa00 | 1544 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1545 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1546 | if (!sp) |
1547 | return sp; | |
4db35314 AK |
1548 | sp->gfn = gfn; |
1549 | sp->role = role; | |
7ae680eb XG |
1550 | hlist_add_head(&sp->hash_link, |
1551 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1552 | if (!direct) { |
b1a36821 MT |
1553 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1554 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1555 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1556 | kvm_sync_pages(vcpu, gfn); | |
1557 | ||
4731d4c7 MT |
1558 | account_shadowed(vcpu->kvm, gfn); |
1559 | } | |
131d8279 AK |
1560 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1561 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1562 | else | |
1563 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1564 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1565 | return sp; |
cea0f0e7 AK |
1566 | } |
1567 | ||
2d11123a AK |
1568 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1569 | struct kvm_vcpu *vcpu, u64 addr) | |
1570 | { | |
1571 | iterator->addr = addr; | |
1572 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1573 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1574 | |
1575 | if (iterator->level == PT64_ROOT_LEVEL && | |
1576 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1577 | !vcpu->arch.mmu.direct_map) | |
1578 | --iterator->level; | |
1579 | ||
2d11123a AK |
1580 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1581 | iterator->shadow_addr | |
1582 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1583 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1584 | --iterator->level; | |
1585 | if (!iterator->shadow_addr) | |
1586 | iterator->level = 0; | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1591 | { | |
1592 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1593 | return false; | |
4d88954d MT |
1594 | |
1595 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1596 | if (is_large_pte(*iterator->sptep)) | |
1597 | return false; | |
1598 | ||
2d11123a AK |
1599 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1600 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1601 | return true; | |
1602 | } | |
1603 | ||
1604 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1605 | { | |
1606 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1607 | --iterator->level; | |
1608 | } | |
1609 | ||
32ef26a3 AK |
1610 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1611 | { | |
1612 | u64 spte; | |
1613 | ||
1614 | spte = __pa(sp->spt) | |
1615 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1616 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1617 | __set_spte(sptep, spte); |
32ef26a3 AK |
1618 | } |
1619 | ||
a3aa51cf AK |
1620 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1621 | { | |
1622 | if (is_large_pte(*sptep)) { | |
1623 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1624 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1625 | } | |
1626 | } | |
1627 | ||
a357bd22 AK |
1628 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1629 | unsigned direct_access) | |
1630 | { | |
1631 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1632 | struct kvm_mmu_page *child; | |
1633 | ||
1634 | /* | |
1635 | * For the direct sp, if the guest pte's dirty bit | |
1636 | * changed form clean to dirty, it will corrupt the | |
1637 | * sp's access: allow writable in the read-only sp, | |
1638 | * so we should update the spte at this point to get | |
1639 | * a new sp with the correct access. | |
1640 | */ | |
1641 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1642 | if (child->role.access == direct_access) | |
1643 | return; | |
1644 | ||
1645 | mmu_page_remove_parent_pte(child, sptep); | |
1646 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1647 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1648 | } | |
1649 | } | |
1650 | ||
90cb0529 | 1651 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1652 | struct kvm_mmu_page *sp) |
a436036b | 1653 | { |
697fe2e2 AK |
1654 | unsigned i; |
1655 | u64 *pt; | |
1656 | u64 ent; | |
1657 | ||
4db35314 | 1658 | pt = sp->spt; |
697fe2e2 | 1659 | |
697fe2e2 AK |
1660 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1661 | ent = pt[i]; | |
1662 | ||
05da4558 | 1663 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1664 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1665 | ent &= PT64_BASE_ADDR_MASK; |
1666 | mmu_page_remove_parent_pte(page_header(ent), | |
1667 | &pt[i]); | |
1668 | } else { | |
776e6633 MT |
1669 | if (is_large_pte(ent)) |
1670 | --kvm->stat.lpages; | |
be38d276 AK |
1671 | drop_spte(kvm, &pt[i], |
1672 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1673 | } |
1674 | } | |
c7addb90 | 1675 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1676 | } |
a436036b AK |
1677 | } |
1678 | ||
4db35314 | 1679 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1680 | { |
4db35314 | 1681 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1682 | } |
1683 | ||
12b7d28f AK |
1684 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1685 | { | |
1686 | int i; | |
988a2cae | 1687 | struct kvm_vcpu *vcpu; |
12b7d28f | 1688 | |
988a2cae GN |
1689 | kvm_for_each_vcpu(i, vcpu, kvm) |
1690 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1691 | } |
1692 | ||
31aa2b44 | 1693 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1694 | { |
1695 | u64 *parent_pte; | |
1696 | ||
4db35314 AK |
1697 | while (sp->multimapped || sp->parent_pte) { |
1698 | if (!sp->multimapped) | |
1699 | parent_pte = sp->parent_pte; | |
a436036b AK |
1700 | else { |
1701 | struct kvm_pte_chain *chain; | |
1702 | ||
4db35314 | 1703 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1704 | struct kvm_pte_chain, link); |
1705 | parent_pte = chain->parent_ptes[0]; | |
1706 | } | |
697fe2e2 | 1707 | BUG_ON(!parent_pte); |
4db35314 | 1708 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1709 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1710 | } |
31aa2b44 AK |
1711 | } |
1712 | ||
60c8aec6 | 1713 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1714 | struct kvm_mmu_page *parent, |
1715 | struct list_head *invalid_list) | |
4731d4c7 | 1716 | { |
60c8aec6 MT |
1717 | int i, zapped = 0; |
1718 | struct mmu_page_path parents; | |
1719 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1720 | |
60c8aec6 | 1721 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1722 | return 0; |
60c8aec6 MT |
1723 | |
1724 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1725 | while (mmu_unsync_walk(parent, &pages)) { | |
1726 | struct kvm_mmu_page *sp; | |
1727 | ||
1728 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1729 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1730 | mmu_pages_clear_parents(&parents); |
77662e00 | 1731 | zapped++; |
60c8aec6 | 1732 | } |
60c8aec6 MT |
1733 | kvm_mmu_pages_init(parent, &parents, &pages); |
1734 | } | |
1735 | ||
1736 | return zapped; | |
4731d4c7 MT |
1737 | } |
1738 | ||
7775834a XG |
1739 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1740 | struct list_head *invalid_list) | |
31aa2b44 | 1741 | { |
4731d4c7 | 1742 | int ret; |
f691fe1d | 1743 | |
7775834a | 1744 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1745 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1746 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1747 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1748 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1749 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1750 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1751 | if (sp->unsync) |
1752 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1753 | if (!sp->root_count) { |
54a4f023 GJ |
1754 | /* Count self */ |
1755 | ret++; | |
7775834a | 1756 | list_move(&sp->link, invalid_list); |
2e53d63a | 1757 | } else { |
5b5c6a5a | 1758 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1759 | kvm_reload_remote_mmus(kvm); |
1760 | } | |
7775834a XG |
1761 | |
1762 | sp->role.invalid = 1; | |
12b7d28f | 1763 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1764 | return ret; |
a436036b AK |
1765 | } |
1766 | ||
7775834a XG |
1767 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1768 | struct list_head *invalid_list) | |
1769 | { | |
1770 | struct kvm_mmu_page *sp; | |
1771 | ||
1772 | if (list_empty(invalid_list)) | |
1773 | return; | |
1774 | ||
1775 | kvm_flush_remote_tlbs(kvm); | |
1776 | ||
1777 | do { | |
1778 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1779 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1780 | kvm_mmu_free_page(kvm, sp); | |
1781 | } while (!list_empty(invalid_list)); | |
1782 | ||
1783 | } | |
1784 | ||
82ce2c96 IE |
1785 | /* |
1786 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1787 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1788 | */ |
49d5ca26 | 1789 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1790 | { |
d98ba053 | 1791 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1792 | /* |
1793 | * If we set the number of mmu pages to be smaller be than the | |
1794 | * number of actived pages , we must to free some mmu pages before we | |
1795 | * change the value | |
1796 | */ | |
1797 | ||
49d5ca26 DH |
1798 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1799 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1800 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1801 | struct kvm_mmu_page *page; |
1802 | ||
f05e70ac | 1803 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1804 | struct kvm_mmu_page, link); |
80b63faf XF |
1805 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1806 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1807 | } |
49d5ca26 | 1808 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1809 | } |
82ce2c96 | 1810 | |
49d5ca26 | 1811 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1812 | } |
1813 | ||
f67a46f4 | 1814 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1815 | { |
4db35314 | 1816 | struct kvm_mmu_page *sp; |
f41d335a | 1817 | struct hlist_node *node; |
d98ba053 | 1818 | LIST_HEAD(invalid_list); |
a436036b AK |
1819 | int r; |
1820 | ||
9ad17b10 | 1821 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1822 | r = 0; |
f41d335a XG |
1823 | |
1824 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1825 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1826 | sp->role.word); |
1827 | r = 1; | |
f41d335a | 1828 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1829 | } |
d98ba053 | 1830 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1831 | return r; |
cea0f0e7 AK |
1832 | } |
1833 | ||
f67a46f4 | 1834 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1835 | { |
4db35314 | 1836 | struct kvm_mmu_page *sp; |
f41d335a | 1837 | struct hlist_node *node; |
d98ba053 | 1838 | LIST_HEAD(invalid_list); |
97a0a01e | 1839 | |
f41d335a | 1840 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1841 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1842 | __func__, gfn, sp->role.word); |
f41d335a | 1843 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1844 | } |
d98ba053 | 1845 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1846 | } |
1847 | ||
38c335f1 | 1848 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1849 | { |
bc6678a3 | 1850 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1851 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1852 | |
291f26bc | 1853 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1854 | } |
1855 | ||
6844dec6 MT |
1856 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1857 | { | |
1858 | int i; | |
1859 | u64 *pt = sp->spt; | |
1860 | ||
1861 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1862 | return; | |
1863 | ||
1864 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1865 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1866 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1867 | } |
1868 | } | |
1869 | ||
74be52e3 SY |
1870 | /* |
1871 | * The function is based on mtrr_type_lookup() in | |
1872 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1873 | */ | |
1874 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1875 | u64 start, u64 end) | |
1876 | { | |
1877 | int i; | |
1878 | u64 base, mask; | |
1879 | u8 prev_match, curr_match; | |
1880 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1881 | ||
1882 | if (!mtrr_state->enabled) | |
1883 | return 0xFF; | |
1884 | ||
1885 | /* Make end inclusive end, instead of exclusive */ | |
1886 | end--; | |
1887 | ||
1888 | /* Look in fixed ranges. Just return the type as per start */ | |
1889 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1890 | int idx; | |
1891 | ||
1892 | if (start < 0x80000) { | |
1893 | idx = 0; | |
1894 | idx += (start >> 16); | |
1895 | return mtrr_state->fixed_ranges[idx]; | |
1896 | } else if (start < 0xC0000) { | |
1897 | idx = 1 * 8; | |
1898 | idx += ((start - 0x80000) >> 14); | |
1899 | return mtrr_state->fixed_ranges[idx]; | |
1900 | } else if (start < 0x1000000) { | |
1901 | idx = 3 * 8; | |
1902 | idx += ((start - 0xC0000) >> 12); | |
1903 | return mtrr_state->fixed_ranges[idx]; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | /* | |
1908 | * Look in variable ranges | |
1909 | * Look of multiple ranges matching this address and pick type | |
1910 | * as per MTRR precedence | |
1911 | */ | |
1912 | if (!(mtrr_state->enabled & 2)) | |
1913 | return mtrr_state->def_type; | |
1914 | ||
1915 | prev_match = 0xFF; | |
1916 | for (i = 0; i < num_var_ranges; ++i) { | |
1917 | unsigned short start_state, end_state; | |
1918 | ||
1919 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1920 | continue; | |
1921 | ||
1922 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1923 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1924 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1925 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1926 | ||
1927 | start_state = ((start & mask) == (base & mask)); | |
1928 | end_state = ((end & mask) == (base & mask)); | |
1929 | if (start_state != end_state) | |
1930 | return 0xFE; | |
1931 | ||
1932 | if ((start & mask) != (base & mask)) | |
1933 | continue; | |
1934 | ||
1935 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1936 | if (prev_match == 0xFF) { | |
1937 | prev_match = curr_match; | |
1938 | continue; | |
1939 | } | |
1940 | ||
1941 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1942 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1943 | return MTRR_TYPE_UNCACHABLE; | |
1944 | ||
1945 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1946 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1947 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1948 | curr_match == MTRR_TYPE_WRBACK)) { | |
1949 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1950 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1951 | } | |
1952 | ||
1953 | if (prev_match != curr_match) | |
1954 | return MTRR_TYPE_UNCACHABLE; | |
1955 | } | |
1956 | ||
1957 | if (prev_match != 0xFF) | |
1958 | return prev_match; | |
1959 | ||
1960 | return mtrr_state->def_type; | |
1961 | } | |
1962 | ||
4b12f0de | 1963 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1964 | { |
1965 | u8 mtrr; | |
1966 | ||
1967 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1968 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1969 | if (mtrr == 0xfe || mtrr == 0xff) | |
1970 | mtrr = MTRR_TYPE_WRBACK; | |
1971 | return mtrr; | |
1972 | } | |
4b12f0de | 1973 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1974 | |
9cf5cf5a XG |
1975 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1976 | { | |
1977 | trace_kvm_mmu_unsync_page(sp); | |
1978 | ++vcpu->kvm->stat.mmu_unsync; | |
1979 | sp->unsync = 1; | |
1980 | ||
1981 | kvm_mmu_mark_parents_unsync(sp); | |
1982 | mmu_convert_notrap(sp); | |
1983 | } | |
1984 | ||
1985 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1986 | { |
4731d4c7 | 1987 | struct kvm_mmu_page *s; |
f41d335a | 1988 | struct hlist_node *node; |
9cf5cf5a | 1989 | |
f41d335a | 1990 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1991 | if (s->unsync) |
4731d4c7 | 1992 | continue; |
9cf5cf5a XG |
1993 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1994 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1995 | } |
4731d4c7 MT |
1996 | } |
1997 | ||
1998 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1999 | bool can_unsync) | |
2000 | { | |
9cf5cf5a | 2001 | struct kvm_mmu_page *s; |
f41d335a | 2002 | struct hlist_node *node; |
9cf5cf5a XG |
2003 | bool need_unsync = false; |
2004 | ||
f41d335a | 2005 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
2006 | if (!can_unsync) |
2007 | return 1; | |
2008 | ||
9cf5cf5a | 2009 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2010 | return 1; |
9cf5cf5a XG |
2011 | |
2012 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 2013 | if (!oos_shadow) |
9cf5cf5a XG |
2014 | return 1; |
2015 | need_unsync = true; | |
2016 | } | |
4731d4c7 | 2017 | } |
9cf5cf5a XG |
2018 | if (need_unsync) |
2019 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2020 | return 0; |
2021 | } | |
2022 | ||
d555c333 | 2023 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2024 | unsigned pte_access, int user_fault, |
852e3c19 | 2025 | int write_fault, int dirty, int level, |
c2d0ee46 | 2026 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2027 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2028 | { |
b330aa0c | 2029 | u64 spte, entry = *sptep; |
1e73f9dd | 2030 | int ret = 0; |
64d4d521 | 2031 | |
1c4f1fd6 AK |
2032 | /* |
2033 | * We don't set the accessed bit, since we sometimes want to see | |
2034 | * whether the guest actually used the pte (in order to detect | |
2035 | * demand paging). | |
2036 | */ | |
982c2565 | 2037 | spte = PT_PRESENT_MASK; |
947da538 | 2038 | if (!speculative) |
3201b5d9 | 2039 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
2040 | if (!dirty) |
2041 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
2042 | if (pte_access & ACC_EXEC_MASK) |
2043 | spte |= shadow_x_mask; | |
2044 | else | |
2045 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 2046 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2047 | spte |= shadow_user_mask; |
852e3c19 | 2048 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2049 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2050 | if (tdp_enabled) |
4b12f0de SY |
2051 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2052 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2053 | |
9bdbba13 | 2054 | if (host_writable) |
1403283a | 2055 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2056 | else |
2057 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2058 | |
35149e21 | 2059 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
2060 | |
2061 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
2062 | || (!vcpu->arch.mmu.direct_map && write_fault |
2063 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2064 | |
852e3c19 JR |
2065 | if (level > PT_PAGE_TABLE_LEVEL && |
2066 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2067 | ret = 1; |
be38d276 AK |
2068 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
2069 | goto done; | |
38187c83 MT |
2070 | } |
2071 | ||
1c4f1fd6 | 2072 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2073 | |
c5a78f2b JR |
2074 | if (!vcpu->arch.mmu.direct_map |
2075 | && !(pte_access & ACC_WRITE_MASK)) | |
69325a12 AK |
2076 | spte &= ~PT_USER_MASK; |
2077 | ||
ecc5589f MT |
2078 | /* |
2079 | * Optimization: for pte sync, if spte was writable the hash | |
2080 | * lookup is unnecessary (and expensive). Write protection | |
2081 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2082 | * Same reasoning can be applied to dirty page accounting. | |
2083 | */ | |
8dae4445 | 2084 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2085 | goto set_pte; |
2086 | ||
4731d4c7 | 2087 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2088 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2089 | __func__, gfn); |
1e73f9dd | 2090 | ret = 1; |
1c4f1fd6 | 2091 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2092 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2093 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2094 | } |
2095 | } | |
2096 | ||
1c4f1fd6 AK |
2097 | if (pte_access & ACC_WRITE_MASK) |
2098 | mark_page_dirty(vcpu->kvm, gfn); | |
2099 | ||
38187c83 | 2100 | set_pte: |
b79b93f9 | 2101 | update_spte(sptep, spte); |
b330aa0c XG |
2102 | /* |
2103 | * If we overwrite a writable spte with a read-only one we | |
2104 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2105 | * will find a read-only spte, even though the writable spte | |
2106 | * might be cached on a CPU's TLB. | |
2107 | */ | |
2108 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2109 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2110 | done: |
1e73f9dd MT |
2111 | return ret; |
2112 | } | |
2113 | ||
d555c333 | 2114 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2115 | unsigned pt_access, unsigned pte_access, |
2116 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2117 | int *ptwrite, int level, gfn_t gfn, |
1403283a | 2118 | pfn_t pfn, bool speculative, |
9bdbba13 | 2119 | bool host_writable) |
1e73f9dd MT |
2120 | { |
2121 | int was_rmapped = 0; | |
53a27b39 | 2122 | int rmap_count; |
1e73f9dd MT |
2123 | |
2124 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2125 | " user_fault %d gfn %llx\n", |
d555c333 | 2126 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2127 | write_fault, user_fault, gfn); |
2128 | ||
d555c333 | 2129 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2130 | /* |
2131 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2132 | * the parent of the now unreachable PTE. | |
2133 | */ | |
852e3c19 JR |
2134 | if (level > PT_PAGE_TABLE_LEVEL && |
2135 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2136 | struct kvm_mmu_page *child; |
d555c333 | 2137 | u64 pte = *sptep; |
1e73f9dd MT |
2138 | |
2139 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2140 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2141 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2142 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2143 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2144 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2145 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2146 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2147 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2148 | } else |
2149 | was_rmapped = 1; | |
1e73f9dd | 2150 | } |
852e3c19 | 2151 | |
d555c333 | 2152 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a | 2153 | dirty, level, gfn, pfn, speculative, true, |
9bdbba13 | 2154 | host_writable)) { |
1e73f9dd MT |
2155 | if (write_fault) |
2156 | *ptwrite = 1; | |
5304efde | 2157 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2158 | } |
1e73f9dd | 2159 | |
d555c333 | 2160 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2161 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2162 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2163 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2164 | *sptep, sptep); | |
d555c333 | 2165 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2166 | ++vcpu->kvm->stat.lpages; |
2167 | ||
d555c333 | 2168 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2169 | if (!was_rmapped) { |
44ad9944 | 2170 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2171 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2172 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2173 | } |
9ed5520d | 2174 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2175 | if (speculative) { |
d555c333 | 2176 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2177 | vcpu->arch.last_pte_gfn = gfn; |
2178 | } | |
1c4f1fd6 AK |
2179 | } |
2180 | ||
6aa8b732 AK |
2181 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2182 | { | |
2183 | } | |
2184 | ||
957ed9ef XG |
2185 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2186 | bool no_dirty_log) | |
2187 | { | |
2188 | struct kvm_memory_slot *slot; | |
2189 | unsigned long hva; | |
2190 | ||
5d163b1c | 2191 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef XG |
2192 | if (!slot) { |
2193 | get_page(bad_page); | |
2194 | return page_to_pfn(bad_page); | |
2195 | } | |
2196 | ||
2197 | hva = gfn_to_hva_memslot(slot, gfn); | |
2198 | ||
2199 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2200 | } | |
2201 | ||
2202 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2203 | struct kvm_mmu_page *sp, | |
2204 | u64 *start, u64 *end) | |
2205 | { | |
2206 | struct page *pages[PTE_PREFETCH_NUM]; | |
2207 | unsigned access = sp->role.access; | |
2208 | int i, ret; | |
2209 | gfn_t gfn; | |
2210 | ||
2211 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2212 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2213 | return -1; |
2214 | ||
2215 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2216 | if (ret <= 0) | |
2217 | return -1; | |
2218 | ||
2219 | for (i = 0; i < ret; i++, gfn++, start++) | |
2220 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2221 | access, 0, 0, 1, NULL, | |
2222 | sp->role.level, gfn, | |
2223 | page_to_pfn(pages[i]), true, true); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2229 | struct kvm_mmu_page *sp, u64 *sptep) | |
2230 | { | |
2231 | u64 *spte, *start = NULL; | |
2232 | int i; | |
2233 | ||
2234 | WARN_ON(!sp->role.direct); | |
2235 | ||
2236 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2237 | spte = sp->spt + i; | |
2238 | ||
2239 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2240 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2241 | if (!start) | |
2242 | continue; | |
2243 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2244 | break; | |
2245 | start = NULL; | |
2246 | } else if (!start) | |
2247 | start = spte; | |
2248 | } | |
2249 | } | |
2250 | ||
2251 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2252 | { | |
2253 | struct kvm_mmu_page *sp; | |
2254 | ||
2255 | /* | |
2256 | * Since it's no accessed bit on EPT, it's no way to | |
2257 | * distinguish between actually accessed translations | |
2258 | * and prefetched, so disable pte prefetch if EPT is | |
2259 | * enabled. | |
2260 | */ | |
2261 | if (!shadow_accessed_mask) | |
2262 | return; | |
2263 | ||
2264 | sp = page_header(__pa(sptep)); | |
2265 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2266 | return; | |
2267 | ||
2268 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2269 | } | |
2270 | ||
9f652d21 | 2271 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2272 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2273 | bool prefault) | |
140754bc | 2274 | { |
9f652d21 | 2275 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2276 | struct kvm_mmu_page *sp; |
9f652d21 | 2277 | int pt_write = 0; |
140754bc | 2278 | gfn_t pseudo_gfn; |
6aa8b732 | 2279 | |
9f652d21 | 2280 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2281 | if (iterator.level == level) { |
612819c3 MT |
2282 | unsigned pte_access = ACC_ALL; |
2283 | ||
612819c3 | 2284 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
9f652d21 | 2285 | 0, write, 1, &pt_write, |
2ec4739d | 2286 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2287 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2288 | ++vcpu->stat.pf_fixed; |
2289 | break; | |
6aa8b732 AK |
2290 | } |
2291 | ||
9f652d21 | 2292 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2293 | u64 base_addr = iterator.addr; |
2294 | ||
2295 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2296 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2297 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2298 | iterator.level - 1, | |
2299 | 1, ACC_ALL, iterator.sptep); | |
2300 | if (!sp) { | |
2301 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2302 | kvm_release_pfn_clean(pfn); | |
2303 | return -ENOMEM; | |
2304 | } | |
140754bc | 2305 | |
d555c333 AK |
2306 | __set_spte(iterator.sptep, |
2307 | __pa(sp->spt) | |
2308 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
33f91edb XG |
2309 | | shadow_user_mask | shadow_x_mask |
2310 | | shadow_accessed_mask); | |
9f652d21 AK |
2311 | } |
2312 | } | |
2313 | return pt_write; | |
6aa8b732 AK |
2314 | } |
2315 | ||
77db5cbd | 2316 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2317 | { |
77db5cbd HY |
2318 | siginfo_t info; |
2319 | ||
2320 | info.si_signo = SIGBUS; | |
2321 | info.si_errno = 0; | |
2322 | info.si_code = BUS_MCEERR_AR; | |
2323 | info.si_addr = (void __user *)address; | |
2324 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2325 | |
77db5cbd | 2326 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2327 | } |
2328 | ||
2329 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2330 | { | |
2331 | kvm_release_pfn_clean(pfn); | |
2332 | if (is_hwpoison_pfn(pfn)) { | |
77db5cbd | 2333 | kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current); |
bf998156 | 2334 | return 0; |
edba23e5 GN |
2335 | } else if (is_fault_pfn(pfn)) |
2336 | return -EFAULT; | |
2337 | ||
bf998156 HY |
2338 | return 1; |
2339 | } | |
2340 | ||
936a5fe6 AA |
2341 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2342 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2343 | { | |
2344 | pfn_t pfn = *pfnp; | |
2345 | gfn_t gfn = *gfnp; | |
2346 | int level = *levelp; | |
2347 | ||
2348 | /* | |
2349 | * Check if it's a transparent hugepage. If this would be an | |
2350 | * hugetlbfs page, level wouldn't be set to | |
2351 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2352 | * here. | |
2353 | */ | |
2354 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2355 | level == PT_PAGE_TABLE_LEVEL && | |
2356 | PageTransCompound(pfn_to_page(pfn)) && | |
2357 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2358 | unsigned long mask; | |
2359 | /* | |
2360 | * mmu_notifier_retry was successful and we hold the | |
2361 | * mmu_lock here, so the pmd can't become splitting | |
2362 | * from under us, and in turn | |
2363 | * __split_huge_page_refcount() can't run from under | |
2364 | * us and we can safely transfer the refcount from | |
2365 | * PG_tail to PG_head as we switch the pfn to tail to | |
2366 | * head. | |
2367 | */ | |
2368 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2369 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2370 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2371 | if (pfn & mask) { | |
2372 | gfn &= ~mask; | |
2373 | *gfnp = gfn; | |
2374 | kvm_release_pfn_clean(pfn); | |
2375 | pfn &= ~mask; | |
2376 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2377 | BUG(); | |
2378 | *pfnp = pfn; | |
2379 | } | |
2380 | } | |
2381 | } | |
2382 | ||
78b2c54a | 2383 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2384 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2385 | ||
2386 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2387 | bool prefault) |
10589a46 MT |
2388 | { |
2389 | int r; | |
852e3c19 | 2390 | int level; |
936a5fe6 | 2391 | int force_pt_level; |
35149e21 | 2392 | pfn_t pfn; |
e930bffe | 2393 | unsigned long mmu_seq; |
612819c3 | 2394 | bool map_writable; |
aaee2c94 | 2395 | |
936a5fe6 AA |
2396 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2397 | if (likely(!force_pt_level)) { | |
2398 | level = mapping_level(vcpu, gfn); | |
2399 | /* | |
2400 | * This path builds a PAE pagetable - so we can map | |
2401 | * 2mb pages at maximum. Therefore check if the level | |
2402 | * is larger than that. | |
2403 | */ | |
2404 | if (level > PT_DIRECTORY_LEVEL) | |
2405 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2406 | |
936a5fe6 AA |
2407 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2408 | } else | |
2409 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2410 | |
e930bffe | 2411 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2412 | smp_rmb(); |
060c2abe | 2413 | |
78b2c54a | 2414 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2415 | return 0; |
aaee2c94 | 2416 | |
d196e343 | 2417 | /* mmio */ |
bf998156 HY |
2418 | if (is_error_pfn(pfn)) |
2419 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2420 | |
aaee2c94 | 2421 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2422 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2423 | goto out_unlock; | |
eb787d10 | 2424 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2425 | if (likely(!force_pt_level)) |
2426 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2427 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2428 | prefault); | |
aaee2c94 MT |
2429 | spin_unlock(&vcpu->kvm->mmu_lock); |
2430 | ||
aaee2c94 | 2431 | |
10589a46 | 2432 | return r; |
e930bffe AA |
2433 | |
2434 | out_unlock: | |
2435 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2436 | kvm_release_pfn_clean(pfn); | |
2437 | return 0; | |
10589a46 MT |
2438 | } |
2439 | ||
2440 | ||
17ac10ad AK |
2441 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2442 | { | |
2443 | int i; | |
4db35314 | 2444 | struct kvm_mmu_page *sp; |
d98ba053 | 2445 | LIST_HEAD(invalid_list); |
17ac10ad | 2446 | |
ad312c7c | 2447 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2448 | return; |
aaee2c94 | 2449 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2450 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2451 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2452 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2453 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2454 | |
4db35314 AK |
2455 | sp = page_header(root); |
2456 | --sp->root_count; | |
d98ba053 XG |
2457 | if (!sp->root_count && sp->role.invalid) { |
2458 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2459 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2460 | } | |
ad312c7c | 2461 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2462 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2463 | return; |
2464 | } | |
17ac10ad | 2465 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2466 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2467 | |
417726a3 | 2468 | if (root) { |
417726a3 | 2469 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2470 | sp = page_header(root); |
2471 | --sp->root_count; | |
2e53d63a | 2472 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2473 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2474 | &invalid_list); | |
417726a3 | 2475 | } |
ad312c7c | 2476 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2477 | } |
d98ba053 | 2478 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2479 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2480 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2481 | } |
2482 | ||
8986ecc0 MT |
2483 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2484 | { | |
2485 | int ret = 0; | |
2486 | ||
2487 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2488 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2489 | ret = 1; |
2490 | } | |
2491 | ||
2492 | return ret; | |
2493 | } | |
2494 | ||
651dd37a JR |
2495 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2496 | { | |
2497 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2498 | unsigned i; |
651dd37a JR |
2499 | |
2500 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2501 | spin_lock(&vcpu->kvm->mmu_lock); | |
2502 | kvm_mmu_free_some_pages(vcpu); | |
2503 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2504 | 1, ACC_ALL, NULL); | |
2505 | ++sp->root_count; | |
2506 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2507 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2508 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2509 | for (i = 0; i < 4; ++i) { | |
2510 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2511 | ||
2512 | ASSERT(!VALID_PAGE(root)); | |
2513 | spin_lock(&vcpu->kvm->mmu_lock); | |
2514 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2515 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2516 | i << 30, | |
651dd37a JR |
2517 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2518 | NULL); | |
2519 | root = __pa(sp->spt); | |
2520 | ++sp->root_count; | |
2521 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2522 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2523 | } |
6292757f | 2524 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2525 | } else |
2526 | BUG(); | |
2527 | ||
2528 | return 0; | |
2529 | } | |
2530 | ||
2531 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2532 | { |
4db35314 | 2533 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2534 | u64 pdptr, pm_mask; |
2535 | gfn_t root_gfn; | |
2536 | int i; | |
3bb65a22 | 2537 | |
5777ed34 | 2538 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2539 | |
651dd37a JR |
2540 | if (mmu_check_root(vcpu, root_gfn)) |
2541 | return 1; | |
2542 | ||
2543 | /* | |
2544 | * Do we shadow a long mode page table? If so we need to | |
2545 | * write-protect the guests page table root. | |
2546 | */ | |
2547 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2548 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2549 | |
2550 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2551 | |
8facbbff | 2552 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2553 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2554 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2555 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2556 | root = __pa(sp->spt); |
2557 | ++sp->root_count; | |
8facbbff | 2558 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2559 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2560 | return 0; |
17ac10ad | 2561 | } |
f87f9288 | 2562 | |
651dd37a JR |
2563 | /* |
2564 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2565 | * or a PAE 3-level page table. In either case we need to be aware that |
2566 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2567 | */ |
81407ca5 JR |
2568 | pm_mask = PT_PRESENT_MASK; |
2569 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2570 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2571 | ||
17ac10ad | 2572 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2573 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2574 | |
2575 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2576 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2577 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2578 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2579 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2580 | continue; |
2581 | } | |
6de4f3ad | 2582 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2583 | if (mmu_check_root(vcpu, root_gfn)) |
2584 | return 1; | |
5a7388c2 | 2585 | } |
8facbbff | 2586 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2587 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2588 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2589 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2590 | ACC_ALL, NULL); |
4db35314 AK |
2591 | root = __pa(sp->spt); |
2592 | ++sp->root_count; | |
8facbbff AK |
2593 | spin_unlock(&vcpu->kvm->mmu_lock); |
2594 | ||
81407ca5 | 2595 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2596 | } |
6292757f | 2597 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2598 | |
2599 | /* | |
2600 | * If we shadow a 32 bit page table with a long mode page | |
2601 | * table we enter this path. | |
2602 | */ | |
2603 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2604 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2605 | /* | |
2606 | * The additional page necessary for this is only | |
2607 | * allocated on demand. | |
2608 | */ | |
2609 | ||
2610 | u64 *lm_root; | |
2611 | ||
2612 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2613 | if (lm_root == NULL) | |
2614 | return 1; | |
2615 | ||
2616 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2617 | ||
2618 | vcpu->arch.mmu.lm_root = lm_root; | |
2619 | } | |
2620 | ||
2621 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2622 | } | |
2623 | ||
8986ecc0 | 2624 | return 0; |
17ac10ad AK |
2625 | } |
2626 | ||
651dd37a JR |
2627 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2628 | { | |
2629 | if (vcpu->arch.mmu.direct_map) | |
2630 | return mmu_alloc_direct_roots(vcpu); | |
2631 | else | |
2632 | return mmu_alloc_shadow_roots(vcpu); | |
2633 | } | |
2634 | ||
0ba73cda MT |
2635 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2636 | { | |
2637 | int i; | |
2638 | struct kvm_mmu_page *sp; | |
2639 | ||
81407ca5 JR |
2640 | if (vcpu->arch.mmu.direct_map) |
2641 | return; | |
2642 | ||
0ba73cda MT |
2643 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2644 | return; | |
6903074c XG |
2645 | |
2646 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
81407ca5 | 2647 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2648 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2649 | sp = page_header(root); | |
2650 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2651 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2652 | return; |
2653 | } | |
2654 | for (i = 0; i < 4; ++i) { | |
2655 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2656 | ||
8986ecc0 | 2657 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2658 | root &= PT64_BASE_ADDR_MASK; |
2659 | sp = page_header(root); | |
2660 | mmu_sync_children(vcpu, sp); | |
2661 | } | |
2662 | } | |
6903074c | 2663 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2664 | } |
2665 | ||
2666 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2667 | { | |
2668 | spin_lock(&vcpu->kvm->mmu_lock); | |
2669 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2670 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2671 | } |
2672 | ||
1871c602 | 2673 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2674 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2675 | { |
ab9ae313 AK |
2676 | if (exception) |
2677 | exception->error_code = 0; | |
6aa8b732 AK |
2678 | return vaddr; |
2679 | } | |
2680 | ||
6539e738 | 2681 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2682 | u32 access, |
2683 | struct x86_exception *exception) | |
6539e738 | 2684 | { |
ab9ae313 AK |
2685 | if (exception) |
2686 | exception->error_code = 0; | |
6539e738 JR |
2687 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2688 | } | |
2689 | ||
6aa8b732 | 2690 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2691 | u32 error_code, bool prefault) |
6aa8b732 | 2692 | { |
e833240f | 2693 | gfn_t gfn; |
e2dec939 | 2694 | int r; |
6aa8b732 | 2695 | |
b8688d51 | 2696 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2697 | r = mmu_topup_memory_caches(vcpu); |
2698 | if (r) | |
2699 | return r; | |
714b93da | 2700 | |
6aa8b732 | 2701 | ASSERT(vcpu); |
ad312c7c | 2702 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2703 | |
e833240f | 2704 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2705 | |
e833240f | 2706 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2707 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2708 | } |
2709 | ||
7e1fbeac | 2710 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2711 | { |
2712 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2713 | |
7c90705b | 2714 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2715 | arch.gfn = gfn; |
c4806acd | 2716 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2717 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2718 | |
2719 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2720 | } | |
2721 | ||
2722 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2723 | { | |
2724 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2725 | kvm_event_needs_reinjection(vcpu))) | |
2726 | return false; | |
2727 | ||
2728 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2729 | } | |
2730 | ||
78b2c54a | 2731 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2732 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2733 | { |
2734 | bool async; | |
2735 | ||
612819c3 | 2736 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2737 | |
2738 | if (!async) | |
2739 | return false; /* *pfn has correct page already */ | |
2740 | ||
2741 | put_page(pfn_to_page(*pfn)); | |
2742 | ||
78b2c54a | 2743 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2744 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2745 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2746 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2747 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2748 | return true; | |
2749 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2750 | return true; | |
2751 | } | |
2752 | ||
612819c3 | 2753 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2754 | |
2755 | return false; | |
2756 | } | |
2757 | ||
56028d08 | 2758 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2759 | bool prefault) |
fb72d167 | 2760 | { |
35149e21 | 2761 | pfn_t pfn; |
fb72d167 | 2762 | int r; |
852e3c19 | 2763 | int level; |
936a5fe6 | 2764 | int force_pt_level; |
05da4558 | 2765 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2766 | unsigned long mmu_seq; |
612819c3 MT |
2767 | int write = error_code & PFERR_WRITE_MASK; |
2768 | bool map_writable; | |
fb72d167 JR |
2769 | |
2770 | ASSERT(vcpu); | |
2771 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2772 | ||
2773 | r = mmu_topup_memory_caches(vcpu); | |
2774 | if (r) | |
2775 | return r; | |
2776 | ||
936a5fe6 AA |
2777 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2778 | if (likely(!force_pt_level)) { | |
2779 | level = mapping_level(vcpu, gfn); | |
2780 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2781 | } else | |
2782 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 2783 | |
e930bffe | 2784 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2785 | smp_rmb(); |
af585b92 | 2786 | |
78b2c54a | 2787 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2788 | return 0; |
2789 | ||
2790 | /* mmio */ | |
bf998156 HY |
2791 | if (is_error_pfn(pfn)) |
2792 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2793 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2794 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2795 | goto out_unlock; | |
fb72d167 | 2796 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2797 | if (likely(!force_pt_level)) |
2798 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 2799 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2800 | level, gfn, pfn, prefault); |
fb72d167 | 2801 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2802 | |
2803 | return r; | |
e930bffe AA |
2804 | |
2805 | out_unlock: | |
2806 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2807 | kvm_release_pfn_clean(pfn); | |
2808 | return 0; | |
fb72d167 JR |
2809 | } |
2810 | ||
6aa8b732 AK |
2811 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2812 | { | |
17ac10ad | 2813 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2814 | } |
2815 | ||
52fde8df JR |
2816 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2817 | struct kvm_mmu *context) | |
6aa8b732 | 2818 | { |
6aa8b732 AK |
2819 | context->new_cr3 = nonpaging_new_cr3; |
2820 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2821 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2822 | context->free = nonpaging_free; | |
c7addb90 | 2823 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2824 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2825 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2826 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 2827 | context->root_level = 0; |
6aa8b732 | 2828 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2829 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2830 | context->direct_map = true; |
2d48a985 | 2831 | context->nx = false; |
6aa8b732 AK |
2832 | return 0; |
2833 | } | |
2834 | ||
d835dfec | 2835 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2836 | { |
1165f5fe | 2837 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2838 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2839 | } |
2840 | ||
2841 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2842 | { | |
9f8fe504 | 2843 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 2844 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2845 | } |
2846 | ||
5777ed34 JR |
2847 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2848 | { | |
9f8fe504 | 2849 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
2850 | } |
2851 | ||
6389ee94 AK |
2852 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2853 | struct x86_exception *fault) | |
6aa8b732 | 2854 | { |
6389ee94 | 2855 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2856 | } |
2857 | ||
6aa8b732 AK |
2858 | static void paging_free(struct kvm_vcpu *vcpu) |
2859 | { | |
2860 | nonpaging_free(vcpu); | |
2861 | } | |
2862 | ||
3241f22d | 2863 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2864 | { |
2865 | int bit7; | |
2866 | ||
2867 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2868 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2869 | } |
2870 | ||
6aa8b732 AK |
2871 | #define PTTYPE 64 |
2872 | #include "paging_tmpl.h" | |
2873 | #undef PTTYPE | |
2874 | ||
2875 | #define PTTYPE 32 | |
2876 | #include "paging_tmpl.h" | |
2877 | #undef PTTYPE | |
2878 | ||
52fde8df JR |
2879 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2880 | struct kvm_mmu *context, | |
2881 | int level) | |
82725b20 | 2882 | { |
82725b20 DE |
2883 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2884 | u64 exb_bit_rsvd = 0; | |
2885 | ||
2d48a985 | 2886 | if (!context->nx) |
82725b20 DE |
2887 | exb_bit_rsvd = rsvd_bits(63, 63); |
2888 | switch (level) { | |
2889 | case PT32_ROOT_LEVEL: | |
2890 | /* no rsvd bits for 2 level 4K page table entries */ | |
2891 | context->rsvd_bits_mask[0][1] = 0; | |
2892 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2893 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2894 | ||
2895 | if (!is_pse(vcpu)) { | |
2896 | context->rsvd_bits_mask[1][1] = 0; | |
2897 | break; | |
2898 | } | |
2899 | ||
82725b20 DE |
2900 | if (is_cpuid_PSE36()) |
2901 | /* 36bits PSE 4MB page */ | |
2902 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2903 | else | |
2904 | /* 32 bits PSE 4MB page */ | |
2905 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2906 | break; |
2907 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2908 | context->rsvd_bits_mask[0][2] = |
2909 | rsvd_bits(maxphyaddr, 63) | | |
2910 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2911 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2912 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2913 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2914 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2915 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2916 | rsvd_bits(maxphyaddr, 62) | | |
2917 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2918 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2919 | break; |
2920 | case PT64_ROOT_LEVEL: | |
2921 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2922 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2923 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2924 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2925 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2926 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2927 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2928 | rsvd_bits(maxphyaddr, 51); | |
2929 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2930 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2931 | rsvd_bits(maxphyaddr, 51) | | |
2932 | rsvd_bits(13, 29); | |
82725b20 | 2933 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2934 | rsvd_bits(maxphyaddr, 51) | |
2935 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2936 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2937 | break; |
2938 | } | |
2939 | } | |
2940 | ||
52fde8df JR |
2941 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2942 | struct kvm_mmu *context, | |
2943 | int level) | |
6aa8b732 | 2944 | { |
2d48a985 JR |
2945 | context->nx = is_nx(vcpu); |
2946 | ||
52fde8df | 2947 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2948 | |
2949 | ASSERT(is_pae(vcpu)); | |
2950 | context->new_cr3 = paging_new_cr3; | |
2951 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2952 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2953 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2954 | context->sync_page = paging64_sync_page; |
a7052897 | 2955 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 2956 | context->update_pte = paging64_update_pte; |
6aa8b732 | 2957 | context->free = paging_free; |
17ac10ad AK |
2958 | context->root_level = level; |
2959 | context->shadow_root_level = level; | |
17c3ba9d | 2960 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2961 | context->direct_map = false; |
6aa8b732 AK |
2962 | return 0; |
2963 | } | |
2964 | ||
52fde8df JR |
2965 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2966 | struct kvm_mmu *context) | |
17ac10ad | 2967 | { |
52fde8df | 2968 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2969 | } |
2970 | ||
52fde8df JR |
2971 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2972 | struct kvm_mmu *context) | |
6aa8b732 | 2973 | { |
2d48a985 JR |
2974 | context->nx = false; |
2975 | ||
52fde8df | 2976 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2977 | |
2978 | context->new_cr3 = paging_new_cr3; | |
2979 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2980 | context->gva_to_gpa = paging32_gva_to_gpa; |
2981 | context->free = paging_free; | |
c7addb90 | 2982 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2983 | context->sync_page = paging32_sync_page; |
a7052897 | 2984 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 2985 | context->update_pte = paging32_update_pte; |
6aa8b732 AK |
2986 | context->root_level = PT32_ROOT_LEVEL; |
2987 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2988 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2989 | context->direct_map = false; |
6aa8b732 AK |
2990 | return 0; |
2991 | } | |
2992 | ||
52fde8df JR |
2993 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2994 | struct kvm_mmu *context) | |
6aa8b732 | 2995 | { |
52fde8df | 2996 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2997 | } |
2998 | ||
fb72d167 JR |
2999 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3000 | { | |
14dfe855 | 3001 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3002 | |
c445f8ef | 3003 | context->base_role.word = 0; |
fb72d167 JR |
3004 | context->new_cr3 = nonpaging_new_cr3; |
3005 | context->page_fault = tdp_page_fault; | |
3006 | context->free = nonpaging_free; | |
3007 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 3008 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3009 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3010 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3011 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3012 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3013 | context->direct_map = true; |
1c97f0a0 | 3014 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3015 | context->get_cr3 = get_cr3; |
cb659db8 | 3016 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 3017 | context->nx = is_nx(vcpu); |
fb72d167 JR |
3018 | |
3019 | if (!is_paging(vcpu)) { | |
2d48a985 | 3020 | context->nx = false; |
fb72d167 JR |
3021 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3022 | context->root_level = 0; | |
3023 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3024 | context->nx = is_nx(vcpu); |
52fde8df | 3025 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
3026 | context->gva_to_gpa = paging64_gva_to_gpa; |
3027 | context->root_level = PT64_ROOT_LEVEL; | |
3028 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3029 | context->nx = is_nx(vcpu); |
52fde8df | 3030 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
3031 | context->gva_to_gpa = paging64_gva_to_gpa; |
3032 | context->root_level = PT32E_ROOT_LEVEL; | |
3033 | } else { | |
2d48a985 | 3034 | context->nx = false; |
52fde8df | 3035 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
3036 | context->gva_to_gpa = paging32_gva_to_gpa; |
3037 | context->root_level = PT32_ROOT_LEVEL; | |
3038 | } | |
3039 | ||
3040 | return 0; | |
3041 | } | |
3042 | ||
52fde8df | 3043 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3044 | { |
a770f6f2 | 3045 | int r; |
6aa8b732 | 3046 | ASSERT(vcpu); |
ad312c7c | 3047 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3048 | |
3049 | if (!is_paging(vcpu)) | |
52fde8df | 3050 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3051 | else if (is_long_mode(vcpu)) |
52fde8df | 3052 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3053 | else if (is_pae(vcpu)) |
52fde8df | 3054 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3055 | else |
52fde8df | 3056 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3057 | |
5b7e0102 | 3058 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3059 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
52fde8df JR |
3060 | |
3061 | return r; | |
3062 | } | |
3063 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3064 | ||
3065 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3066 | { | |
14dfe855 | 3067 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3068 | |
14dfe855 JR |
3069 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3070 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
3071 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
3072 | |
3073 | return r; | |
6aa8b732 AK |
3074 | } |
3075 | ||
02f59dc9 JR |
3076 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3077 | { | |
3078 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3079 | ||
3080 | g_context->get_cr3 = get_cr3; | |
3081 | g_context->inject_page_fault = kvm_inject_page_fault; | |
3082 | ||
3083 | /* | |
3084 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3085 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3086 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3087 | * functions between mmu and nested_mmu are swapped. | |
3088 | */ | |
3089 | if (!is_paging(vcpu)) { | |
2d48a985 | 3090 | g_context->nx = false; |
02f59dc9 JR |
3091 | g_context->root_level = 0; |
3092 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3093 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3094 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3095 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
3096 | g_context->root_level = PT64_ROOT_LEVEL; | |
3097 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3098 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3099 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3100 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
3101 | g_context->root_level = PT32E_ROOT_LEVEL; | |
3102 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3103 | } else { | |
2d48a985 | 3104 | g_context->nx = false; |
02f59dc9 JR |
3105 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
3106 | g_context->root_level = PT32_ROOT_LEVEL; | |
3107 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
3108 | } | |
3109 | ||
3110 | return 0; | |
3111 | } | |
3112 | ||
fb72d167 JR |
3113 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3114 | { | |
02f59dc9 JR |
3115 | if (mmu_is_nested(vcpu)) |
3116 | return init_kvm_nested_mmu(vcpu); | |
3117 | else if (tdp_enabled) | |
fb72d167 JR |
3118 | return init_kvm_tdp_mmu(vcpu); |
3119 | else | |
3120 | return init_kvm_softmmu(vcpu); | |
3121 | } | |
3122 | ||
6aa8b732 AK |
3123 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3124 | { | |
3125 | ASSERT(vcpu); | |
62ad0755 SY |
3126 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3127 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3128 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3129 | } |
3130 | ||
3131 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3132 | { |
3133 | destroy_kvm_mmu(vcpu); | |
3134 | return init_kvm_mmu(vcpu); | |
3135 | } | |
8668a3c4 | 3136 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3137 | |
3138 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3139 | { |
714b93da AK |
3140 | int r; |
3141 | ||
e2dec939 | 3142 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3143 | if (r) |
3144 | goto out; | |
8986ecc0 | 3145 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3146 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3147 | mmu_sync_roots(vcpu); |
aaee2c94 | 3148 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3149 | if (r) |
3150 | goto out; | |
3662cb1c | 3151 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3152 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3153 | out: |
3154 | return r; | |
6aa8b732 | 3155 | } |
17c3ba9d AK |
3156 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3157 | ||
3158 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3159 | { | |
3160 | mmu_free_roots(vcpu); | |
3161 | } | |
4b16184c | 3162 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3163 | |
09072daf | 3164 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3165 | struct kvm_mmu_page *sp, |
ac1b714e AK |
3166 | u64 *spte) |
3167 | { | |
3168 | u64 pte; | |
3169 | struct kvm_mmu_page *child; | |
3170 | ||
3171 | pte = *spte; | |
c7addb90 | 3172 | if (is_shadow_present_pte(pte)) { |
776e6633 | 3173 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 3174 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
3175 | else { |
3176 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 3177 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
3178 | } |
3179 | } | |
d555c333 | 3180 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
3181 | if (is_large_pte(pte)) |
3182 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
3183 | } |
3184 | ||
0028425f | 3185 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3186 | struct kvm_mmu_page *sp, u64 *spte, |
3187 | const void *new) | |
0028425f | 3188 | { |
30945387 | 3189 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3190 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3191 | return; | |
30945387 | 3192 | } |
0028425f | 3193 | |
4cee5764 | 3194 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3195 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3196 | } |
3197 | ||
79539cec AK |
3198 | static bool need_remote_flush(u64 old, u64 new) |
3199 | { | |
3200 | if (!is_shadow_present_pte(old)) | |
3201 | return false; | |
3202 | if (!is_shadow_present_pte(new)) | |
3203 | return true; | |
3204 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3205 | return true; | |
3206 | old ^= PT64_NX_MASK; | |
3207 | new ^= PT64_NX_MASK; | |
3208 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3209 | } | |
3210 | ||
0671a8e7 XG |
3211 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3212 | bool remote_flush, bool local_flush) | |
79539cec | 3213 | { |
0671a8e7 XG |
3214 | if (zap_page) |
3215 | return; | |
3216 | ||
3217 | if (remote_flush) | |
79539cec | 3218 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3219 | else if (local_flush) |
79539cec AK |
3220 | kvm_mmu_flush_tlb(vcpu); |
3221 | } | |
3222 | ||
12b7d28f AK |
3223 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3224 | { | |
ad312c7c | 3225 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3226 | |
7b52345e | 3227 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3228 | } |
3229 | ||
1b7fcd32 AK |
3230 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3231 | { | |
3232 | u64 *spte = vcpu->arch.last_pte_updated; | |
3233 | ||
3234 | if (spte | |
3235 | && vcpu->arch.last_pte_gfn == gfn | |
3236 | && shadow_accessed_mask | |
3237 | && !(*spte & shadow_accessed_mask) | |
3238 | && is_shadow_present_pte(*spte)) | |
3239 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3240 | } | |
3241 | ||
09072daf | 3242 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3243 | const u8 *new, int bytes, |
3244 | bool guest_initiated) | |
da4a00f0 | 3245 | { |
9b7a0325 | 3246 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3247 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3248 | struct kvm_mmu_page *sp; |
f41d335a | 3249 | struct hlist_node *node; |
d98ba053 | 3250 | LIST_HEAD(invalid_list); |
0f53b5b1 XG |
3251 | u64 entry, gentry, *spte; |
3252 | unsigned pte_size, page_offset, misaligned, quadrant, offset; | |
3253 | int level, npte, invlpg_counter, r, flooded = 0; | |
0671a8e7 XG |
3254 | bool remote_flush, local_flush, zap_page; |
3255 | ||
332b207d XG |
3256 | /* |
3257 | * If we don't have indirect shadow pages, it means no page is | |
3258 | * write-protected, so we can exit simply. | |
3259 | */ | |
3260 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3261 | return; | |
3262 | ||
0671a8e7 | 3263 | zap_page = remote_flush = local_flush = false; |
0f53b5b1 | 3264 | offset = offset_in_page(gpa); |
9b7a0325 | 3265 | |
b8688d51 | 3266 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3267 | |
08e850c6 | 3268 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3269 | |
3270 | /* | |
3271 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3272 | * as the current vcpu paging mode since we update the sptes only |
3273 | * when they have the same mode. | |
72016f3a | 3274 | */ |
08e850c6 | 3275 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3276 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3277 | if (is_pae(vcpu)) { |
3278 | gpa &= ~(gpa_t)7; | |
3279 | bytes = 8; | |
3280 | } | |
3281 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3282 | if (r) |
3283 | gentry = 0; | |
08e850c6 AK |
3284 | new = (const u8 *)&gentry; |
3285 | } | |
3286 | ||
3287 | switch (bytes) { | |
3288 | case 4: | |
3289 | gentry = *(const u32 *)new; | |
3290 | break; | |
3291 | case 8: | |
3292 | gentry = *(const u64 *)new; | |
3293 | break; | |
3294 | default: | |
3295 | gentry = 0; | |
3296 | break; | |
72016f3a AK |
3297 | } |
3298 | ||
aaee2c94 | 3299 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3300 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3301 | gentry = 0; | |
eb787d10 | 3302 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3303 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3304 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 | 3305 | if (guest_initiated) { |
1b7fd45c | 3306 | kvm_mmu_access_page(vcpu, gfn); |
ad218f85 MT |
3307 | if (gfn == vcpu->arch.last_pt_write_gfn |
3308 | && !last_updated_pte_accessed(vcpu)) { | |
3309 | ++vcpu->arch.last_pt_write_count; | |
3310 | if (vcpu->arch.last_pt_write_count >= 3) | |
3311 | flooded = 1; | |
3312 | } else { | |
3313 | vcpu->arch.last_pt_write_gfn = gfn; | |
3314 | vcpu->arch.last_pt_write_count = 1; | |
3315 | vcpu->arch.last_pte_updated = NULL; | |
3316 | } | |
86a5ba02 | 3317 | } |
3246af0e | 3318 | |
fa1de2bf | 3319 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3320 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3321 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3322 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3323 | misaligned |= bytes < 4; |
86a5ba02 | 3324 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3325 | /* |
3326 | * Misaligned accesses are too much trouble to fix | |
3327 | * up; also, they usually indicate a page is not used | |
3328 | * as a page table. | |
86a5ba02 AK |
3329 | * |
3330 | * If we're seeing too many writes to a page, | |
3331 | * it may no longer be a page table, or we may be | |
3332 | * forking, in which case it is better to unmap the | |
3333 | * page. | |
0e7bc4b9 AK |
3334 | */ |
3335 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3336 | gpa, bytes, sp->role.word); |
0671a8e7 | 3337 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3338 | &invalid_list); |
4cee5764 | 3339 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3340 | continue; |
3341 | } | |
9b7a0325 | 3342 | page_offset = offset; |
4db35314 | 3343 | level = sp->role.level; |
ac1b714e | 3344 | npte = 1; |
5b7e0102 | 3345 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3346 | page_offset <<= 1; /* 32->64 */ |
3347 | /* | |
3348 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3349 | * only 2MB. So we need to double the offset again | |
3350 | * and zap two pdes instead of one. | |
3351 | */ | |
3352 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3353 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3354 | page_offset <<= 1; |
3355 | npte = 2; | |
3356 | } | |
fce0657f | 3357 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3358 | page_offset &= ~PAGE_MASK; |
4db35314 | 3359 | if (quadrant != sp->role.quadrant) |
fce0657f | 3360 | continue; |
9b7a0325 | 3361 | } |
0671a8e7 | 3362 | local_flush = true; |
4db35314 | 3363 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3364 | while (npte--) { |
79539cec | 3365 | entry = *spte; |
4db35314 | 3366 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3367 | if (gentry && |
3368 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3369 | & mask.word)) | |
7c562522 | 3370 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3371 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3372 | remote_flush = true; | |
ac1b714e | 3373 | ++spte; |
9b7a0325 | 3374 | } |
9b7a0325 | 3375 | } |
0671a8e7 | 3376 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3377 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3378 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3379 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3380 | } |
3381 | ||
a436036b AK |
3382 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3383 | { | |
10589a46 MT |
3384 | gpa_t gpa; |
3385 | int r; | |
a436036b | 3386 | |
c5a78f2b | 3387 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3388 | return 0; |
3389 | ||
1871c602 | 3390 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3391 | |
aaee2c94 | 3392 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3393 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3394 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3395 | return r; |
a436036b | 3396 | } |
577bdc49 | 3397 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3398 | |
22d95b12 | 3399 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3400 | { |
d98ba053 | 3401 | LIST_HEAD(invalid_list); |
103ad25a | 3402 | |
e0df7b9f | 3403 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3404 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3405 | struct kvm_mmu_page *sp; |
ebeace86 | 3406 | |
f05e70ac | 3407 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3408 | struct kvm_mmu_page, link); |
e0df7b9f | 3409 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3410 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3411 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3412 | } |
3413 | } | |
ebeace86 | 3414 | |
dc25e89e AP |
3415 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3416 | void *insn, int insn_len) | |
3067714c AK |
3417 | { |
3418 | int r; | |
3419 | enum emulation_result er; | |
3420 | ||
56028d08 | 3421 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3422 | if (r < 0) |
3423 | goto out; | |
3424 | ||
3425 | if (!r) { | |
3426 | r = 1; | |
3427 | goto out; | |
3428 | } | |
3429 | ||
b733bfb5 AK |
3430 | r = mmu_topup_memory_caches(vcpu); |
3431 | if (r) | |
3432 | goto out; | |
3433 | ||
dc25e89e | 3434 | er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len); |
3067714c AK |
3435 | |
3436 | switch (er) { | |
3437 | case EMULATE_DONE: | |
3438 | return 1; | |
3439 | case EMULATE_DO_MMIO: | |
3440 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3441 | /* fall through */ |
3067714c | 3442 | case EMULATE_FAIL: |
3f5d18a9 | 3443 | return 0; |
3067714c AK |
3444 | default: |
3445 | BUG(); | |
3446 | } | |
3447 | out: | |
3067714c AK |
3448 | return r; |
3449 | } | |
3450 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3451 | ||
a7052897 MT |
3452 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3453 | { | |
a7052897 | 3454 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3455 | kvm_mmu_flush_tlb(vcpu); |
3456 | ++vcpu->stat.invlpg; | |
3457 | } | |
3458 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3459 | ||
18552672 JR |
3460 | void kvm_enable_tdp(void) |
3461 | { | |
3462 | tdp_enabled = true; | |
3463 | } | |
3464 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3465 | ||
5f4cb662 JR |
3466 | void kvm_disable_tdp(void) |
3467 | { | |
3468 | tdp_enabled = false; | |
3469 | } | |
3470 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3471 | ||
6aa8b732 AK |
3472 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3473 | { | |
ad312c7c | 3474 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3475 | if (vcpu->arch.mmu.lm_root != NULL) |
3476 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3477 | } |
3478 | ||
3479 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3480 | { | |
17ac10ad | 3481 | struct page *page; |
6aa8b732 AK |
3482 | int i; |
3483 | ||
3484 | ASSERT(vcpu); | |
3485 | ||
17ac10ad AK |
3486 | /* |
3487 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3488 | * Therefore we need to allocate shadow page tables in the first | |
3489 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3490 | */ | |
3491 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3492 | if (!page) | |
d7fa6ab2 WY |
3493 | return -ENOMEM; |
3494 | ||
ad312c7c | 3495 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3496 | for (i = 0; i < 4; ++i) |
ad312c7c | 3497 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3498 | |
6aa8b732 | 3499 | return 0; |
6aa8b732 AK |
3500 | } |
3501 | ||
8018c27b | 3502 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3503 | { |
6aa8b732 | 3504 | ASSERT(vcpu); |
ad312c7c | 3505 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3506 | |
8018c27b IM |
3507 | return alloc_mmu_pages(vcpu); |
3508 | } | |
6aa8b732 | 3509 | |
8018c27b IM |
3510 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3511 | { | |
3512 | ASSERT(vcpu); | |
ad312c7c | 3513 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3514 | |
8018c27b | 3515 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3516 | } |
3517 | ||
90cb0529 | 3518 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3519 | { |
4db35314 | 3520 | struct kvm_mmu_page *sp; |
6aa8b732 | 3521 | |
f05e70ac | 3522 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3523 | int i; |
3524 | u64 *pt; | |
3525 | ||
291f26bc | 3526 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3527 | continue; |
3528 | ||
4db35314 | 3529 | pt = sp->spt; |
8234b22e | 3530 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3531 | if (!is_shadow_present_pte(pt[i]) || |
3532 | !is_last_spte(pt[i], sp->role.level)) | |
3533 | continue; | |
3534 | ||
3535 | if (is_large_pte(pt[i])) { | |
8234b22e AK |
3536 | drop_spte(kvm, &pt[i], |
3537 | shadow_trap_nonpresent_pte); | |
3538 | --kvm->stat.lpages; | |
da8dc75f | 3539 | continue; |
8234b22e | 3540 | } |
da8dc75f | 3541 | |
6aa8b732 | 3542 | /* avoid RMW */ |
01c168ac | 3543 | if (is_writable_pte(pt[i])) |
700e1b12 | 3544 | update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK); |
8234b22e | 3545 | } |
6aa8b732 | 3546 | } |
171d595d | 3547 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3548 | } |
37a7d8b0 | 3549 | |
90cb0529 | 3550 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3551 | { |
4db35314 | 3552 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3553 | LIST_HEAD(invalid_list); |
e0fa826f | 3554 | |
aaee2c94 | 3555 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3556 | restart: |
f05e70ac | 3557 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3558 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3559 | goto restart; |
3560 | ||
d98ba053 | 3561 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3562 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3563 | } |
3564 | ||
d98ba053 XG |
3565 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3566 | struct list_head *invalid_list) | |
3ee16c81 IE |
3567 | { |
3568 | struct kvm_mmu_page *page; | |
3569 | ||
3570 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3571 | struct kvm_mmu_page, link); | |
d98ba053 | 3572 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3573 | } |
3574 | ||
1495f230 | 3575 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3576 | { |
3577 | struct kvm *kvm; | |
3578 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3579 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3580 | |
3581 | if (nr_to_scan == 0) | |
3582 | goto out; | |
3ee16c81 | 3583 | |
e935b837 | 3584 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3585 | |
3586 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3587 | int idx, freed_pages; |
d98ba053 | 3588 | LIST_HEAD(invalid_list); |
3ee16c81 | 3589 | |
f656ce01 | 3590 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3591 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3592 | if (!kvm_freed && nr_to_scan > 0 && |
3593 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3594 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3595 | &invalid_list); | |
3ee16c81 IE |
3596 | kvm_freed = kvm; |
3597 | } | |
3598 | nr_to_scan--; | |
3599 | ||
d98ba053 | 3600 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3601 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3602 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3603 | } |
3604 | if (kvm_freed) | |
3605 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3606 | ||
e935b837 | 3607 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3608 | |
45221ab6 DH |
3609 | out: |
3610 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3611 | } |
3612 | ||
3613 | static struct shrinker mmu_shrinker = { | |
3614 | .shrink = mmu_shrink, | |
3615 | .seeks = DEFAULT_SEEKS * 10, | |
3616 | }; | |
3617 | ||
2ddfd20e | 3618 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3619 | { |
3620 | if (pte_chain_cache) | |
3621 | kmem_cache_destroy(pte_chain_cache); | |
53c07b18 XG |
3622 | if (pte_list_desc_cache) |
3623 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
3624 | if (mmu_page_header_cache) |
3625 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3626 | } |
3627 | ||
3628 | int kvm_mmu_module_init(void) | |
3629 | { | |
3630 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3631 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3632 | 0, 0, NULL); |
b5a33a75 AK |
3633 | if (!pte_chain_cache) |
3634 | goto nomem; | |
53c07b18 XG |
3635 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
3636 | sizeof(struct pte_list_desc), | |
20c2df83 | 3637 | 0, 0, NULL); |
53c07b18 | 3638 | if (!pte_list_desc_cache) |
b5a33a75 AK |
3639 | goto nomem; |
3640 | ||
d3d25b04 AK |
3641 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3642 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3643 | 0, 0, NULL); |
d3d25b04 AK |
3644 | if (!mmu_page_header_cache) |
3645 | goto nomem; | |
3646 | ||
45bf21a8 WY |
3647 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3648 | goto nomem; | |
3649 | ||
3ee16c81 IE |
3650 | register_shrinker(&mmu_shrinker); |
3651 | ||
b5a33a75 AK |
3652 | return 0; |
3653 | ||
3654 | nomem: | |
3ee16c81 | 3655 | mmu_destroy_caches(); |
b5a33a75 AK |
3656 | return -ENOMEM; |
3657 | } | |
3658 | ||
3ad82a7e ZX |
3659 | /* |
3660 | * Caculate mmu pages needed for kvm. | |
3661 | */ | |
3662 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3663 | { | |
3664 | int i; | |
3665 | unsigned int nr_mmu_pages; | |
3666 | unsigned int nr_pages = 0; | |
bc6678a3 | 3667 | struct kvm_memslots *slots; |
3ad82a7e | 3668 | |
90d83dc3 LJ |
3669 | slots = kvm_memslots(kvm); |
3670 | ||
bc6678a3 MT |
3671 | for (i = 0; i < slots->nmemslots; i++) |
3672 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3673 | |
3674 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3675 | nr_mmu_pages = max(nr_mmu_pages, | |
3676 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3677 | ||
3678 | return nr_mmu_pages; | |
3679 | } | |
3680 | ||
2f333bcb MT |
3681 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3682 | unsigned len) | |
3683 | { | |
3684 | if (len > buffer->len) | |
3685 | return NULL; | |
3686 | return buffer->ptr; | |
3687 | } | |
3688 | ||
3689 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3690 | unsigned len) | |
3691 | { | |
3692 | void *ret; | |
3693 | ||
3694 | ret = pv_mmu_peek_buffer(buffer, len); | |
3695 | if (!ret) | |
3696 | return ret; | |
3697 | buffer->ptr += len; | |
3698 | buffer->len -= len; | |
3699 | buffer->processed += len; | |
3700 | return ret; | |
3701 | } | |
3702 | ||
3703 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3704 | gpa_t addr, gpa_t value) | |
3705 | { | |
3706 | int bytes = 8; | |
3707 | int r; | |
3708 | ||
3709 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3710 | bytes = 4; | |
3711 | ||
3712 | r = mmu_topup_memory_caches(vcpu); | |
3713 | if (r) | |
3714 | return r; | |
3715 | ||
3200f405 | 3716 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3717 | return -EFAULT; |
3718 | ||
3719 | return 1; | |
3720 | } | |
3721 | ||
3722 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3723 | { | |
9f8fe504 | 3724 | (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu)); |
2f333bcb MT |
3725 | return 1; |
3726 | } | |
3727 | ||
3728 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3729 | { | |
3730 | spin_lock(&vcpu->kvm->mmu_lock); | |
3731 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3732 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3733 | return 1; | |
3734 | } | |
3735 | ||
3736 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3737 | struct kvm_pv_mmu_op_buffer *buffer) | |
3738 | { | |
3739 | struct kvm_mmu_op_header *header; | |
3740 | ||
3741 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3742 | if (!header) | |
3743 | return 0; | |
3744 | switch (header->op) { | |
3745 | case KVM_MMU_OP_WRITE_PTE: { | |
3746 | struct kvm_mmu_op_write_pte *wpte; | |
3747 | ||
3748 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3749 | if (!wpte) | |
3750 | return 0; | |
3751 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3752 | wpte->pte_val); | |
3753 | } | |
3754 | case KVM_MMU_OP_FLUSH_TLB: { | |
3755 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3756 | ||
3757 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3758 | if (!ftlb) | |
3759 | return 0; | |
3760 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3761 | } | |
3762 | case KVM_MMU_OP_RELEASE_PT: { | |
3763 | struct kvm_mmu_op_release_pt *rpt; | |
3764 | ||
3765 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3766 | if (!rpt) | |
3767 | return 0; | |
3768 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3769 | } | |
3770 | default: return 0; | |
3771 | } | |
3772 | } | |
3773 | ||
3774 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3775 | gpa_t addr, unsigned long *ret) | |
3776 | { | |
3777 | int r; | |
6ad18fba | 3778 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3779 | |
6ad18fba DH |
3780 | buffer->ptr = buffer->buf; |
3781 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3782 | buffer->processed = 0; | |
2f333bcb | 3783 | |
6ad18fba | 3784 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3785 | if (r) |
3786 | goto out; | |
3787 | ||
6ad18fba DH |
3788 | while (buffer->len) { |
3789 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3790 | if (r < 0) |
3791 | goto out; | |
3792 | if (r == 0) | |
3793 | break; | |
3794 | } | |
3795 | ||
3796 | r = 1; | |
3797 | out: | |
6ad18fba | 3798 | *ret = buffer->processed; |
2f333bcb MT |
3799 | return r; |
3800 | } | |
3801 | ||
94d8b056 MT |
3802 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3803 | { | |
3804 | struct kvm_shadow_walk_iterator iterator; | |
3805 | int nr_sptes = 0; | |
3806 | ||
3807 | spin_lock(&vcpu->kvm->mmu_lock); | |
3808 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3809 | sptes[iterator.level-1] = *iterator.sptep; | |
3810 | nr_sptes++; | |
3811 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3812 | break; | |
3813 | } | |
3814 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3815 | ||
3816 | return nr_sptes; | |
3817 | } | |
3818 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3819 | ||
c42fffe3 XG |
3820 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
3821 | { | |
3822 | ASSERT(vcpu); | |
3823 | ||
3824 | destroy_kvm_mmu(vcpu); | |
3825 | free_mmu_pages(vcpu); | |
3826 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
3827 | } |
3828 | ||
3829 | #ifdef CONFIG_KVM_MMU_AUDIT | |
3830 | #include "mmu_audit.c" | |
3831 | #else | |
3832 | static void mmu_audit_disable(void) { } | |
3833 | #endif | |
3834 | ||
3835 | void kvm_mmu_module_exit(void) | |
3836 | { | |
3837 | mmu_destroy_caches(); | |
3838 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
3839 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
3840 | mmu_audit_disable(); |
3841 | } |