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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d | 44 | #include <asm/page.h> |
aa2e063a | 45 | #include <asm/pat.h> |
e495606d | 46 | #include <asm/cmpxchg.h> |
4e542370 | 47 | #include <asm/io.h> |
13673a90 | 48 | #include <asm/vmx.h> |
3d0c27ad | 49 | #include <asm/kvm_page_track.h> |
1261bfa3 | 50 | #include "trace.h" |
6aa8b732 | 51 | |
18552672 JR |
52 | /* |
53 | * When setting this variable to true it enables Two-Dimensional-Paging | |
54 | * where the hardware walks 2 page tables: | |
55 | * 1. the guest-virtual to guest-physical | |
56 | * 2. while doing 1. it walks guest-physical to host-physical | |
57 | * If the hardware supports that we don't need to do shadow paging. | |
58 | */ | |
2f333bcb | 59 | bool tdp_enabled = false; |
18552672 | 60 | |
8b1fe17c XG |
61 | enum { |
62 | AUDIT_PRE_PAGE_FAULT, | |
63 | AUDIT_POST_PAGE_FAULT, | |
64 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
65 | AUDIT_POST_PTE_WRITE, |
66 | AUDIT_PRE_SYNC, | |
67 | AUDIT_POST_SYNC | |
8b1fe17c | 68 | }; |
37a7d8b0 | 69 | |
8b1fe17c | 70 | #undef MMU_DEBUG |
37a7d8b0 AK |
71 | |
72 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
73 | static bool dbg = 0; |
74 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
75 | |
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 78 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 79 | #else |
37a7d8b0 AK |
80 | #define pgprintk(x...) do { } while (0) |
81 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 82 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 83 | #endif |
6aa8b732 | 84 | |
957ed9ef XG |
85 | #define PTE_PREFETCH_NUM 8 |
86 | ||
00763e41 | 87 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
88 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
89 | ||
6aa8b732 AK |
90 | #define PT64_LEVEL_BITS 9 |
91 | ||
92 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 93 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 94 | |
6aa8b732 AK |
95 | #define PT64_INDEX(address, level)\ |
96 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
97 | ||
98 | ||
99 | #define PT32_LEVEL_BITS 10 | |
100 | ||
101 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 102 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 103 | |
e04da980 JR |
104 | #define PT32_LVL_OFFSET_MASK(level) \ |
105 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
106 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
107 | |
108 | #define PT32_INDEX(address, level)\ | |
109 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
110 | ||
111 | ||
d0ec49d4 | 112 | #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))) |
6aa8b732 AK |
113 | #define PT64_DIR_BASE_ADDR_MASK \ |
114 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
115 | #define PT64_LVL_ADDR_MASK(level) \ |
116 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
117 | * PT64_LEVEL_BITS))) - 1)) | |
118 | #define PT64_LVL_OFFSET_MASK(level) \ | |
119 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
120 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
121 | |
122 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
123 | #define PT32_DIR_BASE_ADDR_MASK \ | |
124 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT32_LVL_ADDR_MASK(level) \ |
126 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 128 | |
53166229 | 129 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 130 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 131 | |
fe135d2c AK |
132 | #define ACC_EXEC_MASK 1 |
133 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
134 | #define ACC_USER_MASK PT_USER_MASK | |
135 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
136 | ||
f160c7b7 JS |
137 | /* The mask for the R/X bits in EPT PTEs */ |
138 | #define PT64_EPT_READABLE_MASK 0x1ull | |
139 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
140 | ||
90bb6fc5 AK |
141 | #include <trace/events/kvm.h> |
142 | ||
07420171 AK |
143 | #define CREATE_TRACE_POINTS |
144 | #include "mmutrace.h" | |
145 | ||
49fde340 XG |
146 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
147 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 148 | |
135f8c2b AK |
149 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
150 | ||
220f773a TY |
151 | /* make pte_list_desc fit well in cache line */ |
152 | #define PTE_LIST_EXT 3 | |
153 | ||
9b8ebbdb PB |
154 | /* |
155 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
156 | * RET_PF_RETRY: let CPU fault again on the address. | |
157 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
158 | * | |
159 | * For handle_mmio_page_fault only: | |
160 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
161 | */ | |
162 | enum { | |
163 | RET_PF_RETRY = 0, | |
164 | RET_PF_EMULATE = 1, | |
165 | RET_PF_INVALID = 2, | |
166 | }; | |
167 | ||
53c07b18 XG |
168 | struct pte_list_desc { |
169 | u64 *sptes[PTE_LIST_EXT]; | |
170 | struct pte_list_desc *more; | |
cd4a4e53 AK |
171 | }; |
172 | ||
2d11123a AK |
173 | struct kvm_shadow_walk_iterator { |
174 | u64 addr; | |
175 | hpa_t shadow_addr; | |
2d11123a | 176 | u64 *sptep; |
dd3bfd59 | 177 | int level; |
2d11123a AK |
178 | unsigned index; |
179 | }; | |
180 | ||
9fa72119 JS |
181 | static const union kvm_mmu_page_role mmu_base_role_mask = { |
182 | .cr0_wp = 1, | |
183 | .cr4_pae = 1, | |
184 | .nxe = 1, | |
185 | .smep_andnot_wp = 1, | |
186 | .smap_andnot_wp = 1, | |
187 | .smm = 1, | |
188 | .guest_mode = 1, | |
189 | .ad_disabled = 1, | |
190 | }; | |
191 | ||
7eb77e9f JS |
192 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
193 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
194 | (_root), (_addr)); \ | |
195 | shadow_walk_okay(&(_walker)); \ | |
196 | shadow_walk_next(&(_walker))) | |
197 | ||
198 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
199 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
200 | shadow_walk_okay(&(_walker)); \ | |
201 | shadow_walk_next(&(_walker))) | |
202 | ||
c2a2ac2b XG |
203 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
204 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
205 | shadow_walk_okay(&(_walker)) && \ | |
206 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
207 | __shadow_walk_next(&(_walker), spte)) | |
208 | ||
53c07b18 | 209 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 210 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 211 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 212 | |
7b52345e SY |
213 | static u64 __read_mostly shadow_nx_mask; |
214 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
215 | static u64 __read_mostly shadow_user_mask; | |
216 | static u64 __read_mostly shadow_accessed_mask; | |
217 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 218 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 219 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 220 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 221 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 222 | |
f160c7b7 | 223 | /* |
ac8d57e5 PF |
224 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
225 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
226 | * tracking. | |
f160c7b7 JS |
227 | */ |
228 | static u64 __read_mostly shadow_acc_track_mask; | |
229 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
230 | ||
231 | /* | |
232 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
233 | * as not-present for access tracking purposes. We do not save the W bit as the | |
234 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
235 | * restored only when a write is attempted to the page. | |
236 | */ | |
237 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
238 | PT64_EPT_EXECUTABLE_MASK; | |
239 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
240 | ||
28a1f3ac JS |
241 | /* |
242 | * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order | |
243 | * to guard against L1TF attacks. | |
244 | */ | |
245 | static u64 __read_mostly shadow_nonpresent_or_rsvd_mask; | |
246 | ||
247 | /* | |
248 | * The number of high-order 1 bits to use in the mask above. | |
249 | */ | |
250 | static const u64 shadow_nonpresent_or_rsvd_mask_len = 5; | |
251 | ||
daa07cbc SC |
252 | /* |
253 | * In some cases, we need to preserve the GFN of a non-present or reserved | |
254 | * SPTE when we usurp the upper five bits of the physical address space to | |
255 | * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll | |
256 | * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask | |
257 | * left into the reserved bits, i.e. the GFN in the SPTE will be split into | |
258 | * high and low parts. This mask covers the lower bits of the GFN. | |
259 | */ | |
260 | static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; | |
261 | ||
262 | ||
ce88decf | 263 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
264 | static union kvm_mmu_page_role |
265 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 266 | |
40ef75a7 LT |
267 | |
268 | static inline bool kvm_available_flush_tlb_with_range(void) | |
269 | { | |
270 | return kvm_x86_ops->tlb_remote_flush_with_range; | |
271 | } | |
272 | ||
273 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
274 | struct kvm_tlb_range *range) | |
275 | { | |
276 | int ret = -ENOTSUPP; | |
277 | ||
278 | if (range && kvm_x86_ops->tlb_remote_flush_with_range) | |
279 | ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range); | |
280 | ||
281 | if (ret) | |
282 | kvm_flush_remote_tlbs(kvm); | |
283 | } | |
284 | ||
285 | static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, | |
286 | u64 start_gfn, u64 pages) | |
287 | { | |
288 | struct kvm_tlb_range range; | |
289 | ||
290 | range.start_gfn = start_gfn; | |
291 | range.pages = pages; | |
292 | ||
293 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
294 | } | |
295 | ||
dcdca5fe | 296 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 297 | { |
dcdca5fe PF |
298 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
299 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 300 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
301 | } |
302 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
303 | ||
ac8d57e5 PF |
304 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
305 | { | |
306 | return sp->role.ad_disabled; | |
307 | } | |
308 | ||
309 | static inline bool spte_ad_enabled(u64 spte) | |
310 | { | |
311 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
312 | return !(spte & shadow_acc_track_value); | |
313 | } | |
314 | ||
315 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
316 | { | |
317 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
318 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
319 | } | |
320 | ||
321 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
322 | { | |
323 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
324 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
325 | } | |
326 | ||
f160c7b7 JS |
327 | static inline bool is_access_track_spte(u64 spte) |
328 | { | |
ac8d57e5 | 329 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
330 | } |
331 | ||
f2fd125d | 332 | /* |
ee3d1570 DM |
333 | * the low bit of the generation number is always presumed to be zero. |
334 | * This disables mmio caching during memslot updates. The concept is | |
335 | * similar to a seqcount but instead of retrying the access we just punt | |
336 | * and ignore the cache. | |
337 | * | |
338 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
339 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 340 | */ |
ee3d1570 | 341 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
342 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
343 | ||
ee3d1570 DM |
344 | #define MMIO_GEN_SHIFT 20 |
345 | #define MMIO_GEN_LOW_SHIFT 10 | |
346 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 347 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
348 | |
349 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
350 | { | |
351 | u64 mask; | |
352 | ||
842bb26a | 353 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
354 | |
355 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
356 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
357 | return mask; | |
358 | } | |
359 | ||
360 | static unsigned int get_mmio_spte_generation(u64 spte) | |
361 | { | |
362 | unsigned int gen; | |
363 | ||
364 | spte &= ~shadow_mmio_mask; | |
365 | ||
366 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
367 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
368 | return gen; | |
369 | } | |
370 | ||
54bf36aa | 371 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 372 | { |
54bf36aa | 373 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
374 | } |
375 | ||
54bf36aa | 376 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 377 | unsigned access) |
ce88decf | 378 | { |
54bf36aa | 379 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 380 | u64 mask = generation_mmio_spte_mask(gen); |
28a1f3ac | 381 | u64 gpa = gfn << PAGE_SHIFT; |
95b0430d | 382 | |
ce88decf | 383 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
28a1f3ac JS |
384 | mask |= shadow_mmio_value | access; |
385 | mask |= gpa | shadow_nonpresent_or_rsvd_mask; | |
386 | mask |= (gpa & shadow_nonpresent_or_rsvd_mask) | |
387 | << shadow_nonpresent_or_rsvd_mask_len; | |
f2fd125d | 388 | |
f8f55942 | 389 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 390 | mmu_spte_set(sptep, mask); |
ce88decf XG |
391 | } |
392 | ||
393 | static bool is_mmio_spte(u64 spte) | |
394 | { | |
dcdca5fe | 395 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
396 | } |
397 | ||
398 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
399 | { | |
daa07cbc | 400 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac JS |
401 | |
402 | gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len) | |
403 | & shadow_nonpresent_or_rsvd_mask; | |
404 | ||
405 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
406 | } |
407 | ||
408 | static unsigned get_mmio_spte_access(u64 spte) | |
409 | { | |
842bb26a | 410 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 411 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
412 | } |
413 | ||
54bf36aa | 414 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 415 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
416 | { |
417 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 418 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
419 | return true; |
420 | } | |
421 | ||
422 | return false; | |
423 | } | |
c7addb90 | 424 | |
54bf36aa | 425 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 426 | { |
089504c0 XG |
427 | unsigned int kvm_gen, spte_gen; |
428 | ||
54bf36aa | 429 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
430 | spte_gen = get_mmio_spte_generation(spte); |
431 | ||
432 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
433 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
434 | } |
435 | ||
ce00053b PF |
436 | /* |
437 | * Sets the shadow PTE masks used by the MMU. | |
438 | * | |
439 | * Assumptions: | |
440 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
441 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
442 | */ | |
7b52345e | 443 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 444 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 445 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 446 | { |
ce00053b PF |
447 | BUG_ON(!dirty_mask != !accessed_mask); |
448 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 449 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 450 | |
7b52345e SY |
451 | shadow_user_mask = user_mask; |
452 | shadow_accessed_mask = accessed_mask; | |
453 | shadow_dirty_mask = dirty_mask; | |
454 | shadow_nx_mask = nx_mask; | |
455 | shadow_x_mask = x_mask; | |
ffb128c8 | 456 | shadow_present_mask = p_mask; |
f160c7b7 | 457 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 458 | shadow_me_mask = me_mask; |
7b52345e SY |
459 | } |
460 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
461 | ||
28a1f3ac | 462 | static void kvm_mmu_reset_all_pte_masks(void) |
f160c7b7 | 463 | { |
daa07cbc SC |
464 | u8 low_phys_bits; |
465 | ||
f160c7b7 JS |
466 | shadow_user_mask = 0; |
467 | shadow_accessed_mask = 0; | |
468 | shadow_dirty_mask = 0; | |
469 | shadow_nx_mask = 0; | |
470 | shadow_x_mask = 0; | |
471 | shadow_mmio_mask = 0; | |
472 | shadow_present_mask = 0; | |
473 | shadow_acc_track_mask = 0; | |
28a1f3ac JS |
474 | |
475 | /* | |
476 | * If the CPU has 46 or less physical address bits, then set an | |
477 | * appropriate mask to guard against L1TF attacks. Otherwise, it is | |
478 | * assumed that the CPU is not vulnerable to L1TF. | |
479 | */ | |
daa07cbc | 480 | low_phys_bits = boot_cpu_data.x86_phys_bits; |
28a1f3ac | 481 | if (boot_cpu_data.x86_phys_bits < |
daa07cbc | 482 | 52 - shadow_nonpresent_or_rsvd_mask_len) { |
28a1f3ac JS |
483 | shadow_nonpresent_or_rsvd_mask = |
484 | rsvd_bits(boot_cpu_data.x86_phys_bits - | |
485 | shadow_nonpresent_or_rsvd_mask_len, | |
486 | boot_cpu_data.x86_phys_bits - 1); | |
daa07cbc SC |
487 | low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len; |
488 | } | |
489 | shadow_nonpresent_or_rsvd_lower_gfn_mask = | |
490 | GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); | |
f160c7b7 JS |
491 | } |
492 | ||
6aa8b732 AK |
493 | static int is_cpuid_PSE36(void) |
494 | { | |
495 | return 1; | |
496 | } | |
497 | ||
73b1087e AK |
498 | static int is_nx(struct kvm_vcpu *vcpu) |
499 | { | |
f6801dff | 500 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
501 | } |
502 | ||
c7addb90 AK |
503 | static int is_shadow_present_pte(u64 pte) |
504 | { | |
f160c7b7 | 505 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
506 | } |
507 | ||
05da4558 MT |
508 | static int is_large_pte(u64 pte) |
509 | { | |
510 | return pte & PT_PAGE_SIZE_MASK; | |
511 | } | |
512 | ||
776e6633 MT |
513 | static int is_last_spte(u64 pte, int level) |
514 | { | |
515 | if (level == PT_PAGE_TABLE_LEVEL) | |
516 | return 1; | |
852e3c19 | 517 | if (is_large_pte(pte)) |
776e6633 MT |
518 | return 1; |
519 | return 0; | |
520 | } | |
521 | ||
d3e328f2 JS |
522 | static bool is_executable_pte(u64 spte) |
523 | { | |
524 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
525 | } | |
526 | ||
ba049e93 | 527 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 528 | { |
35149e21 | 529 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
530 | } |
531 | ||
da928521 AK |
532 | static gfn_t pse36_gfn_delta(u32 gpte) |
533 | { | |
534 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
535 | ||
536 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
537 | } | |
538 | ||
603e0651 | 539 | #ifdef CONFIG_X86_64 |
d555c333 | 540 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 541 | { |
b19ee2ff | 542 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
543 | } |
544 | ||
603e0651 | 545 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 546 | { |
b19ee2ff | 547 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
548 | } |
549 | ||
550 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
551 | { | |
552 | return xchg(sptep, spte); | |
553 | } | |
c2a2ac2b XG |
554 | |
555 | static u64 __get_spte_lockless(u64 *sptep) | |
556 | { | |
6aa7de05 | 557 | return READ_ONCE(*sptep); |
c2a2ac2b | 558 | } |
a9221dd5 | 559 | #else |
603e0651 XG |
560 | union split_spte { |
561 | struct { | |
562 | u32 spte_low; | |
563 | u32 spte_high; | |
564 | }; | |
565 | u64 spte; | |
566 | }; | |
a9221dd5 | 567 | |
c2a2ac2b XG |
568 | static void count_spte_clear(u64 *sptep, u64 spte) |
569 | { | |
570 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
571 | ||
572 | if (is_shadow_present_pte(spte)) | |
573 | return; | |
574 | ||
575 | /* Ensure the spte is completely set before we increase the count */ | |
576 | smp_wmb(); | |
577 | sp->clear_spte_count++; | |
578 | } | |
579 | ||
603e0651 XG |
580 | static void __set_spte(u64 *sptep, u64 spte) |
581 | { | |
582 | union split_spte *ssptep, sspte; | |
a9221dd5 | 583 | |
603e0651 XG |
584 | ssptep = (union split_spte *)sptep; |
585 | sspte = (union split_spte)spte; | |
586 | ||
587 | ssptep->spte_high = sspte.spte_high; | |
588 | ||
589 | /* | |
590 | * If we map the spte from nonpresent to present, We should store | |
591 | * the high bits firstly, then set present bit, so cpu can not | |
592 | * fetch this spte while we are setting the spte. | |
593 | */ | |
594 | smp_wmb(); | |
595 | ||
b19ee2ff | 596 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
597 | } |
598 | ||
603e0651 XG |
599 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
600 | { | |
601 | union split_spte *ssptep, sspte; | |
602 | ||
603 | ssptep = (union split_spte *)sptep; | |
604 | sspte = (union split_spte)spte; | |
605 | ||
b19ee2ff | 606 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
607 | |
608 | /* | |
609 | * If we map the spte from present to nonpresent, we should clear | |
610 | * present bit firstly to avoid vcpu fetch the old high bits. | |
611 | */ | |
612 | smp_wmb(); | |
613 | ||
614 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 615 | count_spte_clear(sptep, spte); |
603e0651 XG |
616 | } |
617 | ||
618 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
619 | { | |
620 | union split_spte *ssptep, sspte, orig; | |
621 | ||
622 | ssptep = (union split_spte *)sptep; | |
623 | sspte = (union split_spte)spte; | |
624 | ||
625 | /* xchg acts as a barrier before the setting of the high bits */ | |
626 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
627 | orig.spte_high = ssptep->spte_high; |
628 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 629 | count_spte_clear(sptep, spte); |
603e0651 XG |
630 | |
631 | return orig.spte; | |
632 | } | |
c2a2ac2b XG |
633 | |
634 | /* | |
635 | * The idea using the light way get the spte on x86_32 guest is from | |
636 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
637 | * |
638 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
639 | * coalesces them and we are running out of the MMU lock. Therefore | |
640 | * we need to protect against in-progress updates of the spte. | |
641 | * | |
642 | * Reading the spte while an update is in progress may get the old value | |
643 | * for the high part of the spte. The race is fine for a present->non-present | |
644 | * change (because the high part of the spte is ignored for non-present spte), | |
645 | * but for a present->present change we must reread the spte. | |
646 | * | |
647 | * All such changes are done in two steps (present->non-present and | |
648 | * non-present->present), hence it is enough to count the number of | |
649 | * present->non-present updates: if it changed while reading the spte, | |
650 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
651 | */ |
652 | static u64 __get_spte_lockless(u64 *sptep) | |
653 | { | |
654 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
655 | union split_spte spte, *orig = (union split_spte *)sptep; | |
656 | int count; | |
657 | ||
658 | retry: | |
659 | count = sp->clear_spte_count; | |
660 | smp_rmb(); | |
661 | ||
662 | spte.spte_low = orig->spte_low; | |
663 | smp_rmb(); | |
664 | ||
665 | spte.spte_high = orig->spte_high; | |
666 | smp_rmb(); | |
667 | ||
668 | if (unlikely(spte.spte_low != orig->spte_low || | |
669 | count != sp->clear_spte_count)) | |
670 | goto retry; | |
671 | ||
672 | return spte.spte; | |
673 | } | |
603e0651 XG |
674 | #endif |
675 | ||
ea4114bc | 676 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 677 | { |
feb3eb70 GN |
678 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
679 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
680 | } |
681 | ||
8672b721 XG |
682 | static bool spte_has_volatile_bits(u64 spte) |
683 | { | |
f160c7b7 JS |
684 | if (!is_shadow_present_pte(spte)) |
685 | return false; | |
686 | ||
c7ba5b48 | 687 | /* |
6a6256f9 | 688 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
689 | * out of mmu-lock, it can ensure dirty bit is not lost, |
690 | * also, it can help us to get a stable is_writable_pte() | |
691 | * to ensure tlb flush is not missed. | |
692 | */ | |
f160c7b7 JS |
693 | if (spte_can_locklessly_be_made_writable(spte) || |
694 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
695 | return true; |
696 | ||
ac8d57e5 | 697 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
698 | if ((spte & shadow_accessed_mask) == 0 || |
699 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
700 | return true; | |
701 | } | |
8672b721 | 702 | |
f160c7b7 | 703 | return false; |
8672b721 XG |
704 | } |
705 | ||
83ef6c81 | 706 | static bool is_accessed_spte(u64 spte) |
4132779b | 707 | { |
ac8d57e5 PF |
708 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
709 | ||
710 | return accessed_mask ? spte & accessed_mask | |
711 | : !is_access_track_spte(spte); | |
4132779b XG |
712 | } |
713 | ||
83ef6c81 | 714 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 715 | { |
ac8d57e5 PF |
716 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
717 | ||
718 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
719 | } |
720 | ||
1df9f2dc XG |
721 | /* Rules for using mmu_spte_set: |
722 | * Set the sptep from nonpresent to present. | |
723 | * Note: the sptep being assigned *must* be either not present | |
724 | * or in a state where the hardware will not attempt to update | |
725 | * the spte. | |
726 | */ | |
727 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
728 | { | |
729 | WARN_ON(is_shadow_present_pte(*sptep)); | |
730 | __set_spte(sptep, new_spte); | |
731 | } | |
732 | ||
f39a058d JS |
733 | /* |
734 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
735 | * accessed/dirty status. | |
1df9f2dc | 736 | */ |
f39a058d | 737 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 738 | { |
c7ba5b48 | 739 | u64 old_spte = *sptep; |
4132779b | 740 | |
afd28fe1 | 741 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 742 | |
6e7d0354 XG |
743 | if (!is_shadow_present_pte(old_spte)) { |
744 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 745 | return old_spte; |
6e7d0354 | 746 | } |
4132779b | 747 | |
c7ba5b48 | 748 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 749 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 750 | else |
603e0651 | 751 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 752 | |
83ef6c81 JS |
753 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
754 | ||
f39a058d JS |
755 | return old_spte; |
756 | } | |
757 | ||
758 | /* Rules for using mmu_spte_update: | |
759 | * Update the state bits, it means the mapped pfn is not changed. | |
760 | * | |
761 | * Whenever we overwrite a writable spte with a read-only one we | |
762 | * should flush remote TLBs. Otherwise rmap_write_protect | |
763 | * will find a read-only spte, even though the writable spte | |
764 | * might be cached on a CPU's TLB, the return value indicates this | |
765 | * case. | |
766 | * | |
767 | * Returns true if the TLB needs to be flushed | |
768 | */ | |
769 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
770 | { | |
771 | bool flush = false; | |
772 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
773 | ||
774 | if (!is_shadow_present_pte(old_spte)) | |
775 | return false; | |
776 | ||
c7ba5b48 XG |
777 | /* |
778 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 779 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
780 | * spte_has_volatile_bits(). |
781 | */ | |
ea4114bc | 782 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 783 | !is_writable_pte(new_spte)) |
83ef6c81 | 784 | flush = true; |
4132779b | 785 | |
7e71a59b | 786 | /* |
83ef6c81 | 787 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
788 | * to guarantee consistency between TLB and page tables. |
789 | */ | |
7e71a59b | 790 | |
83ef6c81 JS |
791 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
792 | flush = true; | |
4132779b | 793 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
794 | } |
795 | ||
796 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
797 | flush = true; | |
4132779b | 798 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 799 | } |
6e7d0354 | 800 | |
83ef6c81 | 801 | return flush; |
b79b93f9 AK |
802 | } |
803 | ||
1df9f2dc XG |
804 | /* |
805 | * Rules for using mmu_spte_clear_track_bits: | |
806 | * It sets the sptep from present to nonpresent, and track the | |
807 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 808 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
809 | */ |
810 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
811 | { | |
ba049e93 | 812 | kvm_pfn_t pfn; |
1df9f2dc XG |
813 | u64 old_spte = *sptep; |
814 | ||
815 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 816 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 817 | else |
603e0651 | 818 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 819 | |
afd28fe1 | 820 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
821 | return 0; |
822 | ||
823 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
824 | |
825 | /* | |
826 | * KVM does not hold the refcount of the page used by | |
827 | * kvm mmu, before reclaiming the page, we should | |
828 | * unmap it from mmu first. | |
829 | */ | |
bf4bea8e | 830 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 831 | |
83ef6c81 | 832 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 833 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
834 | |
835 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 836 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 837 | |
1df9f2dc XG |
838 | return 1; |
839 | } | |
840 | ||
841 | /* | |
842 | * Rules for using mmu_spte_clear_no_track: | |
843 | * Directly clear spte without caring the state bits of sptep, | |
844 | * it is used to set the upper level spte. | |
845 | */ | |
846 | static void mmu_spte_clear_no_track(u64 *sptep) | |
847 | { | |
603e0651 | 848 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
849 | } |
850 | ||
c2a2ac2b XG |
851 | static u64 mmu_spte_get_lockless(u64 *sptep) |
852 | { | |
853 | return __get_spte_lockless(sptep); | |
854 | } | |
855 | ||
f160c7b7 JS |
856 | static u64 mark_spte_for_access_track(u64 spte) |
857 | { | |
ac8d57e5 | 858 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
859 | return spte & ~shadow_accessed_mask; |
860 | ||
ac8d57e5 | 861 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
862 | return spte; |
863 | ||
864 | /* | |
20d65236 JS |
865 | * Making an Access Tracking PTE will result in removal of write access |
866 | * from the PTE. So, verify that we will be able to restore the write | |
867 | * access in the fast page fault path later on. | |
f160c7b7 JS |
868 | */ |
869 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
870 | !spte_can_locklessly_be_made_writable(spte), | |
871 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
872 | ||
873 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
874 | shadow_acc_track_saved_bits_shift), | |
875 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
876 | ||
877 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
878 | shadow_acc_track_saved_bits_shift; | |
879 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
880 | |
881 | return spte; | |
882 | } | |
883 | ||
d3e328f2 JS |
884 | /* Restore an acc-track PTE back to a regular PTE */ |
885 | static u64 restore_acc_track_spte(u64 spte) | |
886 | { | |
887 | u64 new_spte = spte; | |
888 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
889 | & shadow_acc_track_saved_bits_mask; | |
890 | ||
ac8d57e5 | 891 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
892 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
893 | ||
894 | new_spte &= ~shadow_acc_track_mask; | |
895 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
896 | shadow_acc_track_saved_bits_shift); | |
897 | new_spte |= saved_bits; | |
898 | ||
899 | return new_spte; | |
900 | } | |
901 | ||
f160c7b7 JS |
902 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
903 | static bool mmu_spte_age(u64 *sptep) | |
904 | { | |
905 | u64 spte = mmu_spte_get_lockless(sptep); | |
906 | ||
907 | if (!is_accessed_spte(spte)) | |
908 | return false; | |
909 | ||
ac8d57e5 | 910 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
911 | clear_bit((ffs(shadow_accessed_mask) - 1), |
912 | (unsigned long *)sptep); | |
913 | } else { | |
914 | /* | |
915 | * Capture the dirty status of the page, so that it doesn't get | |
916 | * lost when the SPTE is marked for access tracking. | |
917 | */ | |
918 | if (is_writable_pte(spte)) | |
919 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
920 | ||
921 | spte = mark_spte_for_access_track(spte); | |
922 | mmu_spte_update_no_track(sptep, spte); | |
923 | } | |
924 | ||
925 | return true; | |
926 | } | |
927 | ||
c2a2ac2b XG |
928 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
929 | { | |
c142786c AK |
930 | /* |
931 | * Prevent page table teardown by making any free-er wait during | |
932 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
933 | */ | |
934 | local_irq_disable(); | |
36ca7e0a | 935 | |
c142786c AK |
936 | /* |
937 | * Make sure a following spte read is not reordered ahead of the write | |
938 | * to vcpu->mode. | |
939 | */ | |
36ca7e0a | 940 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
941 | } |
942 | ||
943 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
944 | { | |
c142786c AK |
945 | /* |
946 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 947 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
948 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
949 | */ | |
36ca7e0a | 950 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 951 | local_irq_enable(); |
c2a2ac2b XG |
952 | } |
953 | ||
e2dec939 | 954 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 955 | struct kmem_cache *base_cache, int min) |
714b93da AK |
956 | { |
957 | void *obj; | |
958 | ||
959 | if (cache->nobjs >= min) | |
e2dec939 | 960 | return 0; |
714b93da | 961 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 962 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 963 | if (!obj) |
daefb794 | 964 | return cache->nobjs >= min ? 0 : -ENOMEM; |
714b93da AK |
965 | cache->objects[cache->nobjs++] = obj; |
966 | } | |
e2dec939 | 967 | return 0; |
714b93da AK |
968 | } |
969 | ||
f759e2b4 XG |
970 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
971 | { | |
972 | return cache->nobjs; | |
973 | } | |
974 | ||
e8ad9a70 XG |
975 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
976 | struct kmem_cache *cache) | |
714b93da AK |
977 | { |
978 | while (mc->nobjs) | |
e8ad9a70 | 979 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
980 | } |
981 | ||
c1158e63 | 982 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 983 | int min) |
c1158e63 | 984 | { |
842f22ed | 985 | void *page; |
c1158e63 AK |
986 | |
987 | if (cache->nobjs >= min) | |
988 | return 0; | |
989 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
d97e5e61 | 990 | page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT); |
c1158e63 | 991 | if (!page) |
daefb794 | 992 | return cache->nobjs >= min ? 0 : -ENOMEM; |
842f22ed | 993 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
994 | } |
995 | return 0; | |
996 | } | |
997 | ||
998 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
999 | { | |
1000 | while (mc->nobjs) | |
c4d198d5 | 1001 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
1002 | } |
1003 | ||
2e3e5882 | 1004 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 1005 | { |
e2dec939 AK |
1006 | int r; |
1007 | ||
53c07b18 | 1008 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 1009 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
1010 | if (r) |
1011 | goto out; | |
ad312c7c | 1012 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
1013 | if (r) |
1014 | goto out; | |
ad312c7c | 1015 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 1016 | mmu_page_header_cache, 4); |
e2dec939 AK |
1017 | out: |
1018 | return r; | |
714b93da AK |
1019 | } |
1020 | ||
1021 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
1022 | { | |
53c07b18 XG |
1023 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
1024 | pte_list_desc_cache); | |
ad312c7c | 1025 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
1026 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
1027 | mmu_page_header_cache); | |
714b93da AK |
1028 | } |
1029 | ||
80feb89a | 1030 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
1031 | { |
1032 | void *p; | |
1033 | ||
1034 | BUG_ON(!mc->nobjs); | |
1035 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
1036 | return p; |
1037 | } | |
1038 | ||
53c07b18 | 1039 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 1040 | { |
80feb89a | 1041 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
1042 | } |
1043 | ||
53c07b18 | 1044 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 1045 | { |
53c07b18 | 1046 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
1047 | } |
1048 | ||
2032a93d LJ |
1049 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
1050 | { | |
1051 | if (!sp->role.direct) | |
1052 | return sp->gfns[index]; | |
1053 | ||
1054 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
1055 | } | |
1056 | ||
1057 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
1058 | { | |
1059 | if (sp->role.direct) | |
1060 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
1061 | else | |
1062 | sp->gfns[index] = gfn; | |
1063 | } | |
1064 | ||
05da4558 | 1065 | /* |
d4dbf470 TY |
1066 | * Return the pointer to the large page information for a given gfn, |
1067 | * handling slots that are not large page aligned. | |
05da4558 | 1068 | */ |
d4dbf470 TY |
1069 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
1070 | struct kvm_memory_slot *slot, | |
1071 | int level) | |
05da4558 MT |
1072 | { |
1073 | unsigned long idx; | |
1074 | ||
fb03cb6f | 1075 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 1076 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
1077 | } |
1078 | ||
547ffaed XG |
1079 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
1080 | gfn_t gfn, int count) | |
1081 | { | |
1082 | struct kvm_lpage_info *linfo; | |
1083 | int i; | |
1084 | ||
1085 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
1086 | linfo = lpage_info_slot(gfn, slot, i); | |
1087 | linfo->disallow_lpage += count; | |
1088 | WARN_ON(linfo->disallow_lpage < 0); | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1093 | { | |
1094 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
1095 | } | |
1096 | ||
1097 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1098 | { | |
1099 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1100 | } | |
1101 | ||
3ed1a478 | 1102 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1103 | { |
699023e2 | 1104 | struct kvm_memslots *slots; |
d25797b2 | 1105 | struct kvm_memory_slot *slot; |
3ed1a478 | 1106 | gfn_t gfn; |
05da4558 | 1107 | |
56ca57f9 | 1108 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1109 | gfn = sp->gfn; |
699023e2 PB |
1110 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1111 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1112 | |
1113 | /* the non-leaf shadow pages are keeping readonly. */ | |
1114 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1115 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1116 | KVM_PAGE_TRACK_WRITE); | |
1117 | ||
547ffaed | 1118 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1119 | } |
1120 | ||
3ed1a478 | 1121 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1122 | { |
699023e2 | 1123 | struct kvm_memslots *slots; |
d25797b2 | 1124 | struct kvm_memory_slot *slot; |
3ed1a478 | 1125 | gfn_t gfn; |
05da4558 | 1126 | |
56ca57f9 | 1127 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1128 | gfn = sp->gfn; |
699023e2 PB |
1129 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1130 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1131 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1132 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1133 | KVM_PAGE_TRACK_WRITE); | |
1134 | ||
547ffaed | 1135 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1136 | } |
1137 | ||
92f94f1e XG |
1138 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1139 | struct kvm_memory_slot *slot) | |
05da4558 | 1140 | { |
d4dbf470 | 1141 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1142 | |
1143 | if (slot) { | |
d4dbf470 | 1144 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1145 | return !!linfo->disallow_lpage; |
05da4558 MT |
1146 | } |
1147 | ||
92f94f1e | 1148 | return true; |
05da4558 MT |
1149 | } |
1150 | ||
92f94f1e XG |
1151 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1152 | int level) | |
5225fdf8 TY |
1153 | { |
1154 | struct kvm_memory_slot *slot; | |
1155 | ||
1156 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1157 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1158 | } |
1159 | ||
d25797b2 | 1160 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1161 | { |
8f0b1ab6 | 1162 | unsigned long page_size; |
d25797b2 | 1163 | int i, ret = 0; |
05da4558 | 1164 | |
8f0b1ab6 | 1165 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1166 | |
8a3d08f1 | 1167 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1168 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1169 | ret = i; | |
1170 | else | |
1171 | break; | |
1172 | } | |
1173 | ||
4c2155ce | 1174 | return ret; |
05da4558 MT |
1175 | } |
1176 | ||
d8aacf5d TY |
1177 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1178 | bool no_dirty_log) | |
1179 | { | |
1180 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1181 | return false; | |
1182 | if (no_dirty_log && slot->dirty_bitmap) | |
1183 | return false; | |
1184 | ||
1185 | return true; | |
1186 | } | |
1187 | ||
5d163b1c XG |
1188 | static struct kvm_memory_slot * |
1189 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1190 | bool no_dirty_log) | |
05da4558 MT |
1191 | { |
1192 | struct kvm_memory_slot *slot; | |
5d163b1c | 1193 | |
54bf36aa | 1194 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1195 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1196 | slot = NULL; |
1197 | ||
1198 | return slot; | |
1199 | } | |
1200 | ||
fd136902 TY |
1201 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1202 | bool *force_pt_level) | |
936a5fe6 AA |
1203 | { |
1204 | int host_level, level, max_level; | |
d8aacf5d TY |
1205 | struct kvm_memory_slot *slot; |
1206 | ||
8c85ac1c TY |
1207 | if (unlikely(*force_pt_level)) |
1208 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1209 | |
8c85ac1c TY |
1210 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1211 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1212 | if (unlikely(*force_pt_level)) |
1213 | return PT_PAGE_TABLE_LEVEL; | |
1214 | ||
d25797b2 JR |
1215 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1216 | ||
1217 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1218 | return host_level; | |
1219 | ||
55dd98c3 | 1220 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1221 | |
1222 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1223 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1224 | break; |
d25797b2 JR |
1225 | |
1226 | return level - 1; | |
05da4558 MT |
1227 | } |
1228 | ||
290fc38d | 1229 | /* |
018aabb5 | 1230 | * About rmap_head encoding: |
cd4a4e53 | 1231 | * |
018aabb5 TY |
1232 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1233 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1234 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1235 | */ |
1236 | ||
1237 | /* | |
1238 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1239 | */ |
53c07b18 | 1240 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1241 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1242 | { |
53c07b18 | 1243 | struct pte_list_desc *desc; |
53a27b39 | 1244 | int i, count = 0; |
cd4a4e53 | 1245 | |
018aabb5 | 1246 | if (!rmap_head->val) { |
53c07b18 | 1247 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1248 | rmap_head->val = (unsigned long)spte; |
1249 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1250 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1251 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1252 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1253 | desc->sptes[1] = spte; |
018aabb5 | 1254 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1255 | ++count; |
cd4a4e53 | 1256 | } else { |
53c07b18 | 1257 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1258 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1259 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1260 | desc = desc->more; |
53c07b18 | 1261 | count += PTE_LIST_EXT; |
53a27b39 | 1262 | } |
53c07b18 XG |
1263 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1264 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1265 | desc = desc->more; |
1266 | } | |
d555c333 | 1267 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1268 | ++count; |
d555c333 | 1269 | desc->sptes[i] = spte; |
cd4a4e53 | 1270 | } |
53a27b39 | 1271 | return count; |
cd4a4e53 AK |
1272 | } |
1273 | ||
53c07b18 | 1274 | static void |
018aabb5 TY |
1275 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1276 | struct pte_list_desc *desc, int i, | |
1277 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1278 | { |
1279 | int j; | |
1280 | ||
53c07b18 | 1281 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1282 | ; |
d555c333 AK |
1283 | desc->sptes[i] = desc->sptes[j]; |
1284 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1285 | if (j != 0) |
1286 | return; | |
1287 | if (!prev_desc && !desc->more) | |
018aabb5 | 1288 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1289 | else |
1290 | if (prev_desc) | |
1291 | prev_desc->more = desc->more; | |
1292 | else | |
018aabb5 | 1293 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1294 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1295 | } |
1296 | ||
8daf3462 | 1297 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1298 | { |
53c07b18 XG |
1299 | struct pte_list_desc *desc; |
1300 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1301 | int i; |
1302 | ||
018aabb5 | 1303 | if (!rmap_head->val) { |
8daf3462 | 1304 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 1305 | BUG(); |
018aabb5 | 1306 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 1307 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 1308 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 1309 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
1310 | BUG(); |
1311 | } | |
018aabb5 | 1312 | rmap_head->val = 0; |
cd4a4e53 | 1313 | } else { |
8daf3462 | 1314 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 1315 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1316 | prev_desc = NULL; |
1317 | while (desc) { | |
018aabb5 | 1318 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1319 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1320 | pte_list_desc_remove_entry(rmap_head, |
1321 | desc, i, prev_desc); | |
cd4a4e53 AK |
1322 | return; |
1323 | } | |
018aabb5 | 1324 | } |
cd4a4e53 AK |
1325 | prev_desc = desc; |
1326 | desc = desc->more; | |
1327 | } | |
8daf3462 | 1328 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
1329 | BUG(); |
1330 | } | |
1331 | } | |
1332 | ||
e7912386 WY |
1333 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
1334 | { | |
1335 | mmu_spte_clear_track_bits(sptep); | |
1336 | __pte_list_remove(sptep, rmap_head); | |
1337 | } | |
1338 | ||
018aabb5 TY |
1339 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1340 | struct kvm_memory_slot *slot) | |
53c07b18 | 1341 | { |
77d11309 | 1342 | unsigned long idx; |
53c07b18 | 1343 | |
77d11309 | 1344 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1345 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1346 | } |
1347 | ||
018aabb5 TY |
1348 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1349 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1350 | { |
699023e2 | 1351 | struct kvm_memslots *slots; |
9b9b1492 TY |
1352 | struct kvm_memory_slot *slot; |
1353 | ||
699023e2 PB |
1354 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1355 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1356 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1357 | } |
1358 | ||
f759e2b4 XG |
1359 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1360 | { | |
1361 | struct kvm_mmu_memory_cache *cache; | |
1362 | ||
1363 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1364 | return mmu_memory_cache_free_objects(cache); | |
1365 | } | |
1366 | ||
53c07b18 XG |
1367 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1368 | { | |
1369 | struct kvm_mmu_page *sp; | |
018aabb5 | 1370 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1371 | |
53c07b18 XG |
1372 | sp = page_header(__pa(spte)); |
1373 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1374 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1375 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1376 | } |
1377 | ||
53c07b18 XG |
1378 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1379 | { | |
1380 | struct kvm_mmu_page *sp; | |
1381 | gfn_t gfn; | |
018aabb5 | 1382 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1383 | |
1384 | sp = page_header(__pa(spte)); | |
1385 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 | 1386 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1387 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1388 | } |
1389 | ||
1e3f42f0 TY |
1390 | /* |
1391 | * Used by the following functions to iterate through the sptes linked by a | |
1392 | * rmap. All fields are private and not assumed to be used outside. | |
1393 | */ | |
1394 | struct rmap_iterator { | |
1395 | /* private fields */ | |
1396 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1397 | int pos; /* index of the sptep */ | |
1398 | }; | |
1399 | ||
1400 | /* | |
1401 | * Iteration must be started by this function. This should also be used after | |
1402 | * removing/dropping sptes from the rmap link because in such cases the | |
1403 | * information in the itererator may not be valid. | |
1404 | * | |
1405 | * Returns sptep if found, NULL otherwise. | |
1406 | */ | |
018aabb5 TY |
1407 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1408 | struct rmap_iterator *iter) | |
1e3f42f0 | 1409 | { |
77fbbbd2 TY |
1410 | u64 *sptep; |
1411 | ||
018aabb5 | 1412 | if (!rmap_head->val) |
1e3f42f0 TY |
1413 | return NULL; |
1414 | ||
018aabb5 | 1415 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1416 | iter->desc = NULL; |
77fbbbd2 TY |
1417 | sptep = (u64 *)rmap_head->val; |
1418 | goto out; | |
1e3f42f0 TY |
1419 | } |
1420 | ||
018aabb5 | 1421 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1422 | iter->pos = 0; |
77fbbbd2 TY |
1423 | sptep = iter->desc->sptes[iter->pos]; |
1424 | out: | |
1425 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1426 | return sptep; | |
1e3f42f0 TY |
1427 | } |
1428 | ||
1429 | /* | |
1430 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1431 | * | |
1432 | * Returns sptep if found, NULL otherwise. | |
1433 | */ | |
1434 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1435 | { | |
77fbbbd2 TY |
1436 | u64 *sptep; |
1437 | ||
1e3f42f0 TY |
1438 | if (iter->desc) { |
1439 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1440 | ++iter->pos; |
1441 | sptep = iter->desc->sptes[iter->pos]; | |
1442 | if (sptep) | |
77fbbbd2 | 1443 | goto out; |
1e3f42f0 TY |
1444 | } |
1445 | ||
1446 | iter->desc = iter->desc->more; | |
1447 | ||
1448 | if (iter->desc) { | |
1449 | iter->pos = 0; | |
1450 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1451 | sptep = iter->desc->sptes[iter->pos]; |
1452 | goto out; | |
1e3f42f0 TY |
1453 | } |
1454 | } | |
1455 | ||
1456 | return NULL; | |
77fbbbd2 TY |
1457 | out: |
1458 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1459 | return sptep; | |
1e3f42f0 TY |
1460 | } |
1461 | ||
018aabb5 TY |
1462 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1463 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1464 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1465 | |
c3707958 | 1466 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1467 | { |
1df9f2dc | 1468 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1469 | rmap_remove(kvm, sptep); |
be38d276 AK |
1470 | } |
1471 | ||
8e22f955 XG |
1472 | |
1473 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1474 | { | |
1475 | if (is_large_pte(*sptep)) { | |
1476 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1477 | PT_PAGE_TABLE_LEVEL); | |
1478 | drop_spte(kvm, sptep); | |
1479 | --kvm->stat.lpages; | |
1480 | return true; | |
1481 | } | |
1482 | ||
1483 | return false; | |
1484 | } | |
1485 | ||
1486 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1487 | { | |
c3134ce2 LT |
1488 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
1489 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
1490 | ||
1491 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1492 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1493 | } | |
8e22f955 XG |
1494 | } |
1495 | ||
1496 | /* | |
49fde340 | 1497 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1498 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1499 | * |
b4619660 | 1500 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1501 | * protection: |
1502 | * - for dirty logging, the spte can be set to writable at anytime if | |
1503 | * its dirty bitmap is properly set. | |
1504 | * - for spte protection, the spte can be writable only after unsync-ing | |
1505 | * shadow page. | |
8e22f955 | 1506 | * |
c126d94f | 1507 | * Return true if tlb need be flushed. |
8e22f955 | 1508 | */ |
c4f138b4 | 1509 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1510 | { |
1511 | u64 spte = *sptep; | |
1512 | ||
49fde340 | 1513 | if (!is_writable_pte(spte) && |
ea4114bc | 1514 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1515 | return false; |
1516 | ||
1517 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1518 | ||
49fde340 XG |
1519 | if (pt_protect) |
1520 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1521 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1522 | |
c126d94f | 1523 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1524 | } |
1525 | ||
018aabb5 TY |
1526 | static bool __rmap_write_protect(struct kvm *kvm, |
1527 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1528 | bool pt_protect) |
98348e95 | 1529 | { |
1e3f42f0 TY |
1530 | u64 *sptep; |
1531 | struct rmap_iterator iter; | |
d13bc5b5 | 1532 | bool flush = false; |
374cbac0 | 1533 | |
018aabb5 | 1534 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1535 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1536 | |
d13bc5b5 | 1537 | return flush; |
a0ed4607 TY |
1538 | } |
1539 | ||
c4f138b4 | 1540 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1541 | { |
1542 | u64 spte = *sptep; | |
1543 | ||
1544 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1545 | ||
1546 | spte &= ~shadow_dirty_mask; | |
1547 | ||
1548 | return mmu_spte_update(sptep, spte); | |
1549 | } | |
1550 | ||
ac8d57e5 PF |
1551 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1552 | { | |
1553 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1554 | (unsigned long *)sptep); | |
1555 | if (was_writable) | |
1556 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1557 | ||
1558 | return was_writable; | |
1559 | } | |
1560 | ||
1561 | /* | |
1562 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1563 | * - D bit on ad-enabled SPTEs, and | |
1564 | * - W bit on ad-disabled SPTEs. | |
1565 | * Returns true iff any D or W bits were cleared. | |
1566 | */ | |
018aabb5 | 1567 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1568 | { |
1569 | u64 *sptep; | |
1570 | struct rmap_iterator iter; | |
1571 | bool flush = false; | |
1572 | ||
018aabb5 | 1573 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1574 | if (spte_ad_enabled(*sptep)) |
1575 | flush |= spte_clear_dirty(sptep); | |
1576 | else | |
1577 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1578 | |
1579 | return flush; | |
1580 | } | |
1581 | ||
c4f138b4 | 1582 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1583 | { |
1584 | u64 spte = *sptep; | |
1585 | ||
1586 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1587 | ||
1588 | spte |= shadow_dirty_mask; | |
1589 | ||
1590 | return mmu_spte_update(sptep, spte); | |
1591 | } | |
1592 | ||
018aabb5 | 1593 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1594 | { |
1595 | u64 *sptep; | |
1596 | struct rmap_iterator iter; | |
1597 | bool flush = false; | |
1598 | ||
018aabb5 | 1599 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1600 | if (spte_ad_enabled(*sptep)) |
1601 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1602 | |
1603 | return flush; | |
1604 | } | |
1605 | ||
5dc99b23 | 1606 | /** |
3b0f1d01 | 1607 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1608 | * @kvm: kvm instance |
1609 | * @slot: slot to protect | |
1610 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1611 | * @mask: indicates which pages we should protect | |
1612 | * | |
1613 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1614 | * logging we do not have any such mappings. | |
1615 | */ | |
3b0f1d01 | 1616 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1617 | struct kvm_memory_slot *slot, |
1618 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1619 | { |
018aabb5 | 1620 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1621 | |
5dc99b23 | 1622 | while (mask) { |
018aabb5 TY |
1623 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1624 | PT_PAGE_TABLE_LEVEL, slot); | |
1625 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1626 | |
5dc99b23 TY |
1627 | /* clear the first set bit */ |
1628 | mask &= mask - 1; | |
1629 | } | |
374cbac0 AK |
1630 | } |
1631 | ||
f4b4b180 | 1632 | /** |
ac8d57e5 PF |
1633 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1634 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1635 | * @kvm: kvm instance |
1636 | * @slot: slot to clear D-bit | |
1637 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1638 | * @mask: indicates which pages we should clear D-bit | |
1639 | * | |
1640 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1641 | */ | |
1642 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1643 | struct kvm_memory_slot *slot, | |
1644 | gfn_t gfn_offset, unsigned long mask) | |
1645 | { | |
018aabb5 | 1646 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1647 | |
1648 | while (mask) { | |
018aabb5 TY |
1649 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1650 | PT_PAGE_TABLE_LEVEL, slot); | |
1651 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1652 | |
1653 | /* clear the first set bit */ | |
1654 | mask &= mask - 1; | |
1655 | } | |
1656 | } | |
1657 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1658 | ||
3b0f1d01 KH |
1659 | /** |
1660 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1661 | * PT level pages. | |
1662 | * | |
1663 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1664 | * enable dirty logging for them. | |
1665 | * | |
1666 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1667 | * logging we do not have any such mappings. | |
1668 | */ | |
1669 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1670 | struct kvm_memory_slot *slot, | |
1671 | gfn_t gfn_offset, unsigned long mask) | |
1672 | { | |
88178fd4 KH |
1673 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1674 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1675 | mask); | |
1676 | else | |
1677 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1678 | } |
1679 | ||
bab4165e BD |
1680 | /** |
1681 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1682 | * @vcpu: Guest mode vcpu | |
1683 | * | |
1684 | * Emulate arch specific page modification logging for the | |
1685 | * nested hypervisor | |
1686 | */ | |
1687 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1688 | { | |
1689 | if (kvm_x86_ops->write_log_dirty) | |
1690 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
aeecee2e XG |
1695 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1696 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1697 | { |
018aabb5 | 1698 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1699 | int i; |
2f84569f | 1700 | bool write_protected = false; |
95d4c16c | 1701 | |
8a3d08f1 | 1702 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1703 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1704 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1705 | } |
1706 | ||
1707 | return write_protected; | |
95d4c16c TY |
1708 | } |
1709 | ||
aeecee2e XG |
1710 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1711 | { | |
1712 | struct kvm_memory_slot *slot; | |
1713 | ||
1714 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1715 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1716 | } | |
1717 | ||
018aabb5 | 1718 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1719 | { |
1e3f42f0 TY |
1720 | u64 *sptep; |
1721 | struct rmap_iterator iter; | |
6a49f85c | 1722 | bool flush = false; |
e930bffe | 1723 | |
018aabb5 | 1724 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1725 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1726 | |
e7912386 | 1727 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1728 | flush = true; |
e930bffe | 1729 | } |
1e3f42f0 | 1730 | |
6a49f85c XG |
1731 | return flush; |
1732 | } | |
1733 | ||
018aabb5 | 1734 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1735 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1736 | unsigned long data) | |
1737 | { | |
018aabb5 | 1738 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1739 | } |
1740 | ||
018aabb5 | 1741 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1742 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1743 | unsigned long data) | |
3da0dd43 | 1744 | { |
1e3f42f0 TY |
1745 | u64 *sptep; |
1746 | struct rmap_iterator iter; | |
3da0dd43 | 1747 | int need_flush = 0; |
1e3f42f0 | 1748 | u64 new_spte; |
3da0dd43 | 1749 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1750 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1751 | |
1752 | WARN_ON(pte_huge(*ptep)); | |
1753 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1754 | |
0d536790 | 1755 | restart: |
018aabb5 | 1756 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1757 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1758 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1759 | |
3da0dd43 | 1760 | need_flush = 1; |
1e3f42f0 | 1761 | |
3da0dd43 | 1762 | if (pte_write(*ptep)) { |
e7912386 | 1763 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1764 | goto restart; |
3da0dd43 | 1765 | } else { |
1e3f42f0 | 1766 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1767 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1768 | ||
1769 | new_spte &= ~PT_WRITABLE_MASK; | |
1770 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1771 | |
1772 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1773 | |
1774 | mmu_spte_clear_track_bits(sptep); | |
1775 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1776 | } |
1777 | } | |
1e3f42f0 | 1778 | |
3cc5ea94 LT |
1779 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1780 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1781 | return 0; | |
1782 | } | |
1783 | ||
0cf853c5 | 1784 | return need_flush; |
3da0dd43 IE |
1785 | } |
1786 | ||
6ce1f4e2 XG |
1787 | struct slot_rmap_walk_iterator { |
1788 | /* input fields. */ | |
1789 | struct kvm_memory_slot *slot; | |
1790 | gfn_t start_gfn; | |
1791 | gfn_t end_gfn; | |
1792 | int start_level; | |
1793 | int end_level; | |
1794 | ||
1795 | /* output fields. */ | |
1796 | gfn_t gfn; | |
018aabb5 | 1797 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1798 | int level; |
1799 | ||
1800 | /* private field. */ | |
018aabb5 | 1801 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1802 | }; |
1803 | ||
1804 | static void | |
1805 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1806 | { | |
1807 | iterator->level = level; | |
1808 | iterator->gfn = iterator->start_gfn; | |
1809 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1810 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1811 | iterator->slot); | |
1812 | } | |
1813 | ||
1814 | static void | |
1815 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1816 | struct kvm_memory_slot *slot, int start_level, | |
1817 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1818 | { | |
1819 | iterator->slot = slot; | |
1820 | iterator->start_level = start_level; | |
1821 | iterator->end_level = end_level; | |
1822 | iterator->start_gfn = start_gfn; | |
1823 | iterator->end_gfn = end_gfn; | |
1824 | ||
1825 | rmap_walk_init_level(iterator, iterator->start_level); | |
1826 | } | |
1827 | ||
1828 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1829 | { | |
1830 | return !!iterator->rmap; | |
1831 | } | |
1832 | ||
1833 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1834 | { | |
1835 | if (++iterator->rmap <= iterator->end_rmap) { | |
1836 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1837 | return; | |
1838 | } | |
1839 | ||
1840 | if (++iterator->level > iterator->end_level) { | |
1841 | iterator->rmap = NULL; | |
1842 | return; | |
1843 | } | |
1844 | ||
1845 | rmap_walk_init_level(iterator, iterator->level); | |
1846 | } | |
1847 | ||
1848 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1849 | _start_gfn, _end_gfn, _iter_) \ | |
1850 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1851 | _end_level_, _start_gfn, _end_gfn); \ | |
1852 | slot_rmap_walk_okay(_iter_); \ | |
1853 | slot_rmap_walk_next(_iter_)) | |
1854 | ||
84504ef3 TY |
1855 | static int kvm_handle_hva_range(struct kvm *kvm, |
1856 | unsigned long start, | |
1857 | unsigned long end, | |
1858 | unsigned long data, | |
1859 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1860 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1861 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1862 | gfn_t gfn, |
1863 | int level, | |
84504ef3 | 1864 | unsigned long data)) |
e930bffe | 1865 | { |
bc6678a3 | 1866 | struct kvm_memslots *slots; |
be6ba0f0 | 1867 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1868 | struct slot_rmap_walk_iterator iterator; |
1869 | int ret = 0; | |
9da0e4d5 | 1870 | int i; |
bc6678a3 | 1871 | |
9da0e4d5 PB |
1872 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1873 | slots = __kvm_memslots(kvm, i); | |
1874 | kvm_for_each_memslot(memslot, slots) { | |
1875 | unsigned long hva_start, hva_end; | |
1876 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1877 | |
9da0e4d5 PB |
1878 | hva_start = max(start, memslot->userspace_addr); |
1879 | hva_end = min(end, memslot->userspace_addr + | |
1880 | (memslot->npages << PAGE_SHIFT)); | |
1881 | if (hva_start >= hva_end) | |
1882 | continue; | |
1883 | /* | |
1884 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1885 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1886 | */ | |
1887 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1888 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1889 | ||
1890 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1891 | PT_MAX_HUGEPAGE_LEVEL, | |
1892 | gfn_start, gfn_end - 1, | |
1893 | &iterator) | |
1894 | ret |= handler(kvm, iterator.rmap, memslot, | |
1895 | iterator.gfn, iterator.level, data); | |
1896 | } | |
e930bffe AA |
1897 | } |
1898 | ||
f395302e | 1899 | return ret; |
e930bffe AA |
1900 | } |
1901 | ||
84504ef3 TY |
1902 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1903 | unsigned long data, | |
018aabb5 TY |
1904 | int (*handler)(struct kvm *kvm, |
1905 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1906 | struct kvm_memory_slot *slot, |
8a9522d2 | 1907 | gfn_t gfn, int level, |
84504ef3 TY |
1908 | unsigned long data)) |
1909 | { | |
1910 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1911 | } |
1912 | ||
b3ae2096 TY |
1913 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1914 | { | |
1915 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1916 | } | |
1917 | ||
748c0e31 | 1918 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1919 | { |
0cf853c5 | 1920 | return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1921 | } |
1922 | ||
018aabb5 | 1923 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1924 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1925 | unsigned long data) | |
e930bffe | 1926 | { |
1e3f42f0 | 1927 | u64 *sptep; |
79f702a6 | 1928 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1929 | int young = 0; |
1930 | ||
f160c7b7 JS |
1931 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1932 | young |= mmu_spte_age(sptep); | |
0d536790 | 1933 | |
8a9522d2 | 1934 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1935 | return young; |
1936 | } | |
1937 | ||
018aabb5 | 1938 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1939 | struct kvm_memory_slot *slot, gfn_t gfn, |
1940 | int level, unsigned long data) | |
8ee53820 | 1941 | { |
1e3f42f0 TY |
1942 | u64 *sptep; |
1943 | struct rmap_iterator iter; | |
8ee53820 | 1944 | |
83ef6c81 JS |
1945 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1946 | if (is_accessed_spte(*sptep)) | |
1947 | return 1; | |
83ef6c81 | 1948 | return 0; |
8ee53820 AA |
1949 | } |
1950 | ||
53a27b39 MT |
1951 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1952 | ||
852e3c19 | 1953 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1954 | { |
018aabb5 | 1955 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1956 | struct kvm_mmu_page *sp; |
1957 | ||
1958 | sp = page_header(__pa(spte)); | |
53a27b39 | 1959 | |
018aabb5 | 1960 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1961 | |
018aabb5 | 1962 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
1963 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1964 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1965 | } |
1966 | ||
57128468 | 1967 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1968 | { |
57128468 | 1969 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1970 | } |
1971 | ||
8ee53820 AA |
1972 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1973 | { | |
1974 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1975 | } | |
1976 | ||
d6c69ee9 | 1977 | #ifdef MMU_DEBUG |
47ad8e68 | 1978 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1979 | { |
139bdb2d AK |
1980 | u64 *pos; |
1981 | u64 *end; | |
1982 | ||
47ad8e68 | 1983 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1984 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1985 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1986 | pos, *pos); |
6aa8b732 | 1987 | return 0; |
139bdb2d | 1988 | } |
6aa8b732 AK |
1989 | return 1; |
1990 | } | |
d6c69ee9 | 1991 | #endif |
6aa8b732 | 1992 | |
45221ab6 DH |
1993 | /* |
1994 | * This value is the sum of all of the kvm instances's | |
1995 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1996 | * aggregate version in order to make the slab shrinker | |
1997 | * faster | |
1998 | */ | |
1999 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
2000 | { | |
2001 | kvm->arch.n_used_mmu_pages += nr; | |
2002 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
2003 | } | |
2004 | ||
834be0d8 | 2005 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 2006 | { |
fa4a2c08 | 2007 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 2008 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
2009 | list_del(&sp->link); |
2010 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
2011 | if (!sp->role.direct) |
2012 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 2013 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
2014 | } |
2015 | ||
cea0f0e7 AK |
2016 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
2017 | { | |
114df303 | 2018 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
2019 | } |
2020 | ||
714b93da | 2021 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2022 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2023 | { |
cea0f0e7 AK |
2024 | if (!parent_pte) |
2025 | return; | |
cea0f0e7 | 2026 | |
67052b35 | 2027 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2028 | } |
2029 | ||
4db35314 | 2030 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
2031 | u64 *parent_pte) |
2032 | { | |
8daf3462 | 2033 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2034 | } |
2035 | ||
bcdd9a93 XG |
2036 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
2037 | u64 *parent_pte) | |
2038 | { | |
2039 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 2040 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
2041 | } |
2042 | ||
47005792 | 2043 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 2044 | { |
67052b35 | 2045 | struct kvm_mmu_page *sp; |
7ddca7e4 | 2046 | |
80feb89a TY |
2047 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
2048 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 2049 | if (!direct) |
80feb89a | 2050 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 2051 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
2052 | |
2053 | /* | |
2054 | * The active_mmu_pages list is the FIFO list, do not move the | |
2055 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
2056 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
2057 | */ | |
67052b35 | 2058 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
2059 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
2060 | return sp; | |
ad8cfbe3 MT |
2061 | } |
2062 | ||
67052b35 | 2063 | static void mark_unsync(u64 *spte); |
1047df1f | 2064 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 2065 | { |
74c4e63a TY |
2066 | u64 *sptep; |
2067 | struct rmap_iterator iter; | |
2068 | ||
2069 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
2070 | mark_unsync(sptep); | |
2071 | } | |
0074ff63 MT |
2072 | } |
2073 | ||
67052b35 | 2074 | static void mark_unsync(u64 *spte) |
0074ff63 | 2075 | { |
67052b35 | 2076 | struct kvm_mmu_page *sp; |
1047df1f | 2077 | unsigned int index; |
0074ff63 | 2078 | |
67052b35 | 2079 | sp = page_header(__pa(spte)); |
1047df1f XG |
2080 | index = spte - sp->spt; |
2081 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 2082 | return; |
1047df1f | 2083 | if (sp->unsync_children++) |
0074ff63 | 2084 | return; |
1047df1f | 2085 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
2086 | } |
2087 | ||
e8bc217a | 2088 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 2089 | struct kvm_mmu_page *sp) |
e8bc217a | 2090 | { |
1f50f1b3 | 2091 | return 0; |
e8bc217a MT |
2092 | } |
2093 | ||
7eb77e9f | 2094 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root) |
a7052897 MT |
2095 | { |
2096 | } | |
2097 | ||
0f53b5b1 XG |
2098 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
2099 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 2100 | const void *pte) |
0f53b5b1 XG |
2101 | { |
2102 | WARN_ON(1); | |
2103 | } | |
2104 | ||
60c8aec6 MT |
2105 | #define KVM_PAGE_ARRAY_NR 16 |
2106 | ||
2107 | struct kvm_mmu_pages { | |
2108 | struct mmu_page_and_offset { | |
2109 | struct kvm_mmu_page *sp; | |
2110 | unsigned int idx; | |
2111 | } page[KVM_PAGE_ARRAY_NR]; | |
2112 | unsigned int nr; | |
2113 | }; | |
2114 | ||
cded19f3 HE |
2115 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2116 | int idx) | |
4731d4c7 | 2117 | { |
60c8aec6 | 2118 | int i; |
4731d4c7 | 2119 | |
60c8aec6 MT |
2120 | if (sp->unsync) |
2121 | for (i=0; i < pvec->nr; i++) | |
2122 | if (pvec->page[i].sp == sp) | |
2123 | return 0; | |
2124 | ||
2125 | pvec->page[pvec->nr].sp = sp; | |
2126 | pvec->page[pvec->nr].idx = idx; | |
2127 | pvec->nr++; | |
2128 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2129 | } | |
2130 | ||
fd951457 TY |
2131 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2132 | { | |
2133 | --sp->unsync_children; | |
2134 | WARN_ON((int)sp->unsync_children < 0); | |
2135 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2136 | } | |
2137 | ||
60c8aec6 MT |
2138 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2139 | struct kvm_mmu_pages *pvec) | |
2140 | { | |
2141 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2142 | |
37178b8b | 2143 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2144 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2145 | u64 ent = sp->spt[i]; |
2146 | ||
fd951457 TY |
2147 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2148 | clear_unsync_child_bit(sp, i); | |
2149 | continue; | |
2150 | } | |
7a8f1a74 XG |
2151 | |
2152 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2153 | ||
2154 | if (child->unsync_children) { | |
2155 | if (mmu_pages_add(pvec, child, i)) | |
2156 | return -ENOSPC; | |
2157 | ||
2158 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2159 | if (!ret) { |
2160 | clear_unsync_child_bit(sp, i); | |
2161 | continue; | |
2162 | } else if (ret > 0) { | |
7a8f1a74 | 2163 | nr_unsync_leaf += ret; |
fd951457 | 2164 | } else |
7a8f1a74 XG |
2165 | return ret; |
2166 | } else if (child->unsync) { | |
2167 | nr_unsync_leaf++; | |
2168 | if (mmu_pages_add(pvec, child, i)) | |
2169 | return -ENOSPC; | |
2170 | } else | |
fd951457 | 2171 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2172 | } |
2173 | ||
60c8aec6 MT |
2174 | return nr_unsync_leaf; |
2175 | } | |
2176 | ||
e23d3fef XG |
2177 | #define INVALID_INDEX (-1) |
2178 | ||
60c8aec6 MT |
2179 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2180 | struct kvm_mmu_pages *pvec) | |
2181 | { | |
0a47cd85 | 2182 | pvec->nr = 0; |
60c8aec6 MT |
2183 | if (!sp->unsync_children) |
2184 | return 0; | |
2185 | ||
e23d3fef | 2186 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2187 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2188 | } |
2189 | ||
4731d4c7 MT |
2190 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2191 | { | |
2192 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2193 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2194 | sp->unsync = 0; |
2195 | --kvm->stat.mmu_unsync; | |
2196 | } | |
2197 | ||
7775834a XG |
2198 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2199 | struct list_head *invalid_list); | |
2200 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2201 | struct list_head *invalid_list); | |
4731d4c7 | 2202 | |
f34d251d XG |
2203 | /* |
2204 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2205 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2206 | * since it has been deleted from active_mmu_pages but still can be found | |
2207 | * at hast list. | |
2208 | * | |
f3414bc7 | 2209 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2210 | */ |
f3414bc7 | 2211 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2212 | hlist_for_each_entry(_sp, \ |
2213 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2214 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2215 | } else | |
1044b030 TY |
2216 | |
2217 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2218 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2219 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2220 | |
f918b443 | 2221 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2222 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2223 | struct list_head *invalid_list) | |
4731d4c7 | 2224 | { |
450917b6 | 2225 | if (sp->role.cr4_pae != !!is_pae(vcpu) |
44dd3ffa | 2226 | || vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 2227 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2228 | return false; |
4731d4c7 MT |
2229 | } |
2230 | ||
1f50f1b3 | 2231 | return true; |
4731d4c7 MT |
2232 | } |
2233 | ||
35a70510 PB |
2234 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2235 | struct list_head *invalid_list, | |
2236 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2237 | { |
35a70510 PB |
2238 | if (!list_empty(invalid_list)) { |
2239 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2240 | return; | |
2241 | } | |
d98ba053 | 2242 | |
35a70510 PB |
2243 | if (remote_flush) |
2244 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2245 | else if (local_flush) | |
2246 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2247 | } |
2248 | ||
e37fa785 XG |
2249 | #ifdef CONFIG_KVM_MMU_AUDIT |
2250 | #include "mmu_audit.c" | |
2251 | #else | |
2252 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2253 | static void mmu_audit_disable(void) { } | |
2254 | #endif | |
2255 | ||
46971a2f XG |
2256 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2257 | { | |
2258 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2259 | } | |
2260 | ||
1f50f1b3 | 2261 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2262 | struct list_head *invalid_list) |
1d9dc7e0 | 2263 | { |
9a43c5d9 PB |
2264 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2265 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2266 | } |
2267 | ||
9f1a122f | 2268 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2269 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2270 | struct list_head *invalid_list) | |
9f1a122f | 2271 | { |
9f1a122f | 2272 | struct kvm_mmu_page *s; |
2a74003a | 2273 | bool ret = false; |
9f1a122f | 2274 | |
b67bfe0d | 2275 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2276 | if (!s->unsync) |
9f1a122f XG |
2277 | continue; |
2278 | ||
2279 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2280 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2281 | } |
2282 | ||
2a74003a | 2283 | return ret; |
9f1a122f XG |
2284 | } |
2285 | ||
60c8aec6 | 2286 | struct mmu_page_path { |
2a7266a8 YZ |
2287 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2288 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2289 | }; |
2290 | ||
60c8aec6 | 2291 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2292 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2293 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2294 | i = mmu_pages_next(&pvec, &parents, i)) | |
2295 | ||
cded19f3 HE |
2296 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2297 | struct mmu_page_path *parents, | |
2298 | int i) | |
60c8aec6 MT |
2299 | { |
2300 | int n; | |
2301 | ||
2302 | for (n = i+1; n < pvec->nr; n++) { | |
2303 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2304 | unsigned idx = pvec->page[n].idx; |
2305 | int level = sp->role.level; | |
60c8aec6 | 2306 | |
0a47cd85 PB |
2307 | parents->idx[level-1] = idx; |
2308 | if (level == PT_PAGE_TABLE_LEVEL) | |
2309 | break; | |
60c8aec6 | 2310 | |
0a47cd85 | 2311 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2312 | } |
2313 | ||
2314 | return n; | |
2315 | } | |
2316 | ||
0a47cd85 PB |
2317 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2318 | struct mmu_page_path *parents) | |
2319 | { | |
2320 | struct kvm_mmu_page *sp; | |
2321 | int level; | |
2322 | ||
2323 | if (pvec->nr == 0) | |
2324 | return 0; | |
2325 | ||
e23d3fef XG |
2326 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2327 | ||
0a47cd85 PB |
2328 | sp = pvec->page[0].sp; |
2329 | level = sp->role.level; | |
2330 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2331 | ||
2332 | parents->parent[level-2] = sp; | |
2333 | ||
2334 | /* Also set up a sentinel. Further entries in pvec are all | |
2335 | * children of sp, so this element is never overwritten. | |
2336 | */ | |
2337 | parents->parent[level-1] = NULL; | |
2338 | return mmu_pages_next(pvec, parents, 0); | |
2339 | } | |
2340 | ||
cded19f3 | 2341 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2342 | { |
60c8aec6 MT |
2343 | struct kvm_mmu_page *sp; |
2344 | unsigned int level = 0; | |
2345 | ||
2346 | do { | |
2347 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2348 | sp = parents->parent[level]; |
2349 | if (!sp) | |
2350 | return; | |
2351 | ||
e23d3fef | 2352 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2353 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2354 | level++; |
0a47cd85 | 2355 | } while (!sp->unsync_children); |
60c8aec6 | 2356 | } |
4731d4c7 | 2357 | |
60c8aec6 MT |
2358 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2359 | struct kvm_mmu_page *parent) | |
2360 | { | |
2361 | int i; | |
2362 | struct kvm_mmu_page *sp; | |
2363 | struct mmu_page_path parents; | |
2364 | struct kvm_mmu_pages pages; | |
d98ba053 | 2365 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2366 | bool flush = false; |
60c8aec6 | 2367 | |
60c8aec6 | 2368 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2369 | bool protected = false; |
b1a36821 MT |
2370 | |
2371 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2372 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2373 | |
50c9e6f3 | 2374 | if (protected) { |
b1a36821 | 2375 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2376 | flush = false; |
2377 | } | |
b1a36821 | 2378 | |
60c8aec6 | 2379 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2380 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2381 | mmu_pages_clear_parents(&parents); |
2382 | } | |
50c9e6f3 PB |
2383 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2384 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2385 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2386 | flush = false; | |
2387 | } | |
60c8aec6 | 2388 | } |
50c9e6f3 PB |
2389 | |
2390 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2391 | } |
2392 | ||
a30f47cb XG |
2393 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2394 | { | |
e5691a81 | 2395 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2396 | } |
2397 | ||
2398 | static void clear_sp_write_flooding_count(u64 *spte) | |
2399 | { | |
2400 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2401 | ||
2402 | __clear_sp_write_flooding_count(sp); | |
2403 | } | |
2404 | ||
cea0f0e7 AK |
2405 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2406 | gfn_t gfn, | |
2407 | gva_t gaddr, | |
2408 | unsigned level, | |
f6e2c02b | 2409 | int direct, |
bb11c6c9 | 2410 | unsigned access) |
cea0f0e7 AK |
2411 | { |
2412 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2413 | unsigned quadrant; |
9f1a122f | 2414 | struct kvm_mmu_page *sp; |
9f1a122f | 2415 | bool need_sync = false; |
2a74003a | 2416 | bool flush = false; |
f3414bc7 | 2417 | int collisions = 0; |
2a74003a | 2418 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2419 | |
36d9594d | 2420 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2421 | role.level = level; |
f6e2c02b | 2422 | role.direct = direct; |
84b0c8c6 | 2423 | if (role.direct) |
5b7e0102 | 2424 | role.cr4_pae = 0; |
41074d07 | 2425 | role.access = access; |
44dd3ffa VK |
2426 | if (!vcpu->arch.mmu->direct_map |
2427 | && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2428 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2429 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2430 | role.quadrant = quadrant; | |
2431 | } | |
f3414bc7 DM |
2432 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2433 | if (sp->gfn != gfn) { | |
2434 | collisions++; | |
2435 | continue; | |
2436 | } | |
2437 | ||
7ae680eb XG |
2438 | if (!need_sync && sp->unsync) |
2439 | need_sync = true; | |
4731d4c7 | 2440 | |
7ae680eb XG |
2441 | if (sp->role.word != role.word) |
2442 | continue; | |
4731d4c7 | 2443 | |
2a74003a PB |
2444 | if (sp->unsync) { |
2445 | /* The page is good, but __kvm_sync_page might still end | |
2446 | * up zapping it. If so, break in order to rebuild it. | |
2447 | */ | |
2448 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2449 | break; | |
2450 | ||
2451 | WARN_ON(!list_empty(&invalid_list)); | |
2452 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2453 | } | |
e02aa901 | 2454 | |
98bba238 | 2455 | if (sp->unsync_children) |
a8eeb04a | 2456 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2457 | |
a30f47cb | 2458 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2459 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2460 | goto out; |
7ae680eb | 2461 | } |
47005792 | 2462 | |
dfc5aa00 | 2463 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2464 | |
2465 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2466 | ||
4db35314 AK |
2467 | sp->gfn = gfn; |
2468 | sp->role = role; | |
7ae680eb XG |
2469 | hlist_add_head(&sp->hash_link, |
2470 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2471 | if (!direct) { |
56ca57f9 XG |
2472 | /* |
2473 | * we should do write protection before syncing pages | |
2474 | * otherwise the content of the synced shadow page may | |
2475 | * be inconsistent with guest page table. | |
2476 | */ | |
2477 | account_shadowed(vcpu->kvm, sp); | |
2478 | if (level == PT_PAGE_TABLE_LEVEL && | |
2479 | rmap_write_protect(vcpu, gfn)) | |
c3134ce2 | 2480 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2481 | |
9f1a122f | 2482 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2483 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2484 | } |
5304b8d3 | 2485 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2486 | clear_page(sp->spt); |
f691fe1d | 2487 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2488 | |
2489 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2490 | out: |
2491 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2492 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2493 | return sp; |
cea0f0e7 AK |
2494 | } |
2495 | ||
7eb77e9f JS |
2496 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2497 | struct kvm_vcpu *vcpu, hpa_t root, | |
2498 | u64 addr) | |
2d11123a AK |
2499 | { |
2500 | iterator->addr = addr; | |
7eb77e9f | 2501 | iterator->shadow_addr = root; |
44dd3ffa | 2502 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2503 | |
2a7266a8 | 2504 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2505 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2506 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2507 | --iterator->level; |
2508 | ||
2d11123a | 2509 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2510 | /* |
2511 | * prev_root is currently only used for 64-bit hosts. So only | |
2512 | * the active root_hpa is valid here. | |
2513 | */ | |
44dd3ffa | 2514 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2515 | |
2d11123a | 2516 | iterator->shadow_addr |
44dd3ffa | 2517 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2518 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2519 | --iterator->level; | |
2520 | if (!iterator->shadow_addr) | |
2521 | iterator->level = 0; | |
2522 | } | |
2523 | } | |
2524 | ||
7eb77e9f JS |
2525 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2526 | struct kvm_vcpu *vcpu, u64 addr) | |
2527 | { | |
44dd3ffa | 2528 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2529 | addr); |
2530 | } | |
2531 | ||
2d11123a AK |
2532 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2533 | { | |
2534 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2535 | return false; | |
4d88954d | 2536 | |
2d11123a AK |
2537 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2538 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2539 | return true; | |
2540 | } | |
2541 | ||
c2a2ac2b XG |
2542 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2543 | u64 spte) | |
2d11123a | 2544 | { |
c2a2ac2b | 2545 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2546 | iterator->level = 0; |
2547 | return; | |
2548 | } | |
2549 | ||
c2a2ac2b | 2550 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2551 | --iterator->level; |
2552 | } | |
2553 | ||
c2a2ac2b XG |
2554 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2555 | { | |
bb606a9b | 2556 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2557 | } |
2558 | ||
98bba238 TY |
2559 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2560 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2561 | { |
2562 | u64 spte; | |
2563 | ||
ffb128c8 | 2564 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2565 | |
ffb128c8 | 2566 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2567 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2568 | |
2569 | if (sp_ad_disabled(sp)) | |
2570 | spte |= shadow_acc_track_value; | |
2571 | else | |
2572 | spte |= shadow_accessed_mask; | |
24db2734 | 2573 | |
1df9f2dc | 2574 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2575 | |
2576 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2577 | ||
2578 | if (sp->unsync_children || sp->unsync) | |
2579 | mark_unsync(sptep); | |
32ef26a3 AK |
2580 | } |
2581 | ||
a357bd22 AK |
2582 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2583 | unsigned direct_access) | |
2584 | { | |
2585 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2586 | struct kvm_mmu_page *child; | |
2587 | ||
2588 | /* | |
2589 | * For the direct sp, if the guest pte's dirty bit | |
2590 | * changed form clean to dirty, it will corrupt the | |
2591 | * sp's access: allow writable in the read-only sp, | |
2592 | * so we should update the spte at this point to get | |
2593 | * a new sp with the correct access. | |
2594 | */ | |
2595 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2596 | if (child->role.access == direct_access) | |
2597 | return; | |
2598 | ||
bcdd9a93 | 2599 | drop_parent_pte(child, sptep); |
c3134ce2 | 2600 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2601 | } |
2602 | } | |
2603 | ||
505aef8f | 2604 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2605 | u64 *spte) |
2606 | { | |
2607 | u64 pte; | |
2608 | struct kvm_mmu_page *child; | |
2609 | ||
2610 | pte = *spte; | |
2611 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2612 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2613 | drop_spte(kvm, spte); |
505aef8f XG |
2614 | if (is_large_pte(pte)) |
2615 | --kvm->stat.lpages; | |
2616 | } else { | |
38e3b2b2 | 2617 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2618 | drop_parent_pte(child, spte); |
38e3b2b2 | 2619 | } |
505aef8f XG |
2620 | return true; |
2621 | } | |
2622 | ||
2623 | if (is_mmio_spte(pte)) | |
ce88decf | 2624 | mmu_spte_clear_no_track(spte); |
c3707958 | 2625 | |
505aef8f | 2626 | return false; |
38e3b2b2 XG |
2627 | } |
2628 | ||
90cb0529 | 2629 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2630 | struct kvm_mmu_page *sp) |
a436036b | 2631 | { |
697fe2e2 | 2632 | unsigned i; |
697fe2e2 | 2633 | |
38e3b2b2 XG |
2634 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2635 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2636 | } |
2637 | ||
31aa2b44 | 2638 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2639 | { |
1e3f42f0 TY |
2640 | u64 *sptep; |
2641 | struct rmap_iterator iter; | |
a436036b | 2642 | |
018aabb5 | 2643 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2644 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2645 | } |
2646 | ||
60c8aec6 | 2647 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2648 | struct kvm_mmu_page *parent, |
2649 | struct list_head *invalid_list) | |
4731d4c7 | 2650 | { |
60c8aec6 MT |
2651 | int i, zapped = 0; |
2652 | struct mmu_page_path parents; | |
2653 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2654 | |
60c8aec6 | 2655 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2656 | return 0; |
60c8aec6 | 2657 | |
60c8aec6 MT |
2658 | while (mmu_unsync_walk(parent, &pages)) { |
2659 | struct kvm_mmu_page *sp; | |
2660 | ||
2661 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2662 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2663 | mmu_pages_clear_parents(&parents); |
77662e00 | 2664 | zapped++; |
60c8aec6 | 2665 | } |
60c8aec6 MT |
2666 | } |
2667 | ||
2668 | return zapped; | |
4731d4c7 MT |
2669 | } |
2670 | ||
7775834a XG |
2671 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2672 | struct list_head *invalid_list) | |
31aa2b44 | 2673 | { |
4731d4c7 | 2674 | int ret; |
f691fe1d | 2675 | |
7775834a | 2676 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2677 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2678 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2679 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2680 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2681 | |
f6e2c02b | 2682 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2683 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2684 | |
4731d4c7 MT |
2685 | if (sp->unsync) |
2686 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2687 | if (!sp->root_count) { |
54a4f023 GJ |
2688 | /* Count self */ |
2689 | ret++; | |
7775834a | 2690 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2691 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2692 | } else { |
5b5c6a5a | 2693 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2694 | |
2695 | /* | |
2696 | * The obsolete pages can not be used on any vcpus. | |
2697 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2698 | */ | |
2699 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2700 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2701 | } |
7775834a XG |
2702 | |
2703 | sp->role.invalid = 1; | |
4731d4c7 | 2704 | return ret; |
a436036b AK |
2705 | } |
2706 | ||
7775834a XG |
2707 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2708 | struct list_head *invalid_list) | |
2709 | { | |
945315b9 | 2710 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2711 | |
2712 | if (list_empty(invalid_list)) | |
2713 | return; | |
2714 | ||
c142786c | 2715 | /* |
9753f529 LT |
2716 | * We need to make sure everyone sees our modifications to |
2717 | * the page tables and see changes to vcpu->mode here. The barrier | |
2718 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2719 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2720 | * | |
2721 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2722 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2723 | */ |
2724 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2725 | |
945315b9 | 2726 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2727 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2728 | kvm_mmu_free_page(sp); |
945315b9 | 2729 | } |
7775834a XG |
2730 | } |
2731 | ||
5da59607 TY |
2732 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2733 | struct list_head *invalid_list) | |
2734 | { | |
2735 | struct kvm_mmu_page *sp; | |
2736 | ||
2737 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2738 | return false; | |
2739 | ||
d74c0e6b GT |
2740 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2741 | struct kvm_mmu_page, link); | |
42bcbebf | 2742 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2743 | } |
2744 | ||
82ce2c96 IE |
2745 | /* |
2746 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2747 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2748 | */ |
49d5ca26 | 2749 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2750 | { |
d98ba053 | 2751 | LIST_HEAD(invalid_list); |
82ce2c96 | 2752 | |
b34cb590 TY |
2753 | spin_lock(&kvm->mmu_lock); |
2754 | ||
49d5ca26 | 2755 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2756 | /* Need to free some mmu pages to achieve the goal. */ |
2757 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2758 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2759 | break; | |
82ce2c96 | 2760 | |
aa6bd187 | 2761 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2762 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2763 | } |
82ce2c96 | 2764 | |
49d5ca26 | 2765 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2766 | |
2767 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2768 | } |
2769 | ||
1cb3f3ae | 2770 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2771 | { |
4db35314 | 2772 | struct kvm_mmu_page *sp; |
d98ba053 | 2773 | LIST_HEAD(invalid_list); |
a436036b AK |
2774 | int r; |
2775 | ||
9ad17b10 | 2776 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2777 | r = 0; |
1cb3f3ae | 2778 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2779 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2780 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2781 | sp->role.word); |
2782 | r = 1; | |
f41d335a | 2783 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2784 | } |
d98ba053 | 2785 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2786 | spin_unlock(&kvm->mmu_lock); |
2787 | ||
a436036b | 2788 | return r; |
cea0f0e7 | 2789 | } |
1cb3f3ae | 2790 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2791 | |
5c520e90 | 2792 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2793 | { |
2794 | trace_kvm_mmu_unsync_page(sp); | |
2795 | ++vcpu->kvm->stat.mmu_unsync; | |
2796 | sp->unsync = 1; | |
2797 | ||
2798 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2799 | } |
2800 | ||
3d0c27ad XG |
2801 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2802 | bool can_unsync) | |
4731d4c7 | 2803 | { |
5c520e90 | 2804 | struct kvm_mmu_page *sp; |
4731d4c7 | 2805 | |
3d0c27ad XG |
2806 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2807 | return true; | |
9cf5cf5a | 2808 | |
5c520e90 | 2809 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2810 | if (!can_unsync) |
3d0c27ad | 2811 | return true; |
36a2e677 | 2812 | |
5c520e90 XG |
2813 | if (sp->unsync) |
2814 | continue; | |
9cf5cf5a | 2815 | |
5c520e90 XG |
2816 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2817 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2818 | } |
3d0c27ad | 2819 | |
578e1c4d JS |
2820 | /* |
2821 | * We need to ensure that the marking of unsync pages is visible | |
2822 | * before the SPTE is updated to allow writes because | |
2823 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2824 | * the MMU lock and so can race with this. If the SPTE was updated | |
2825 | * before the page had been marked as unsync-ed, something like the | |
2826 | * following could happen: | |
2827 | * | |
2828 | * CPU 1 CPU 2 | |
2829 | * --------------------------------------------------------------------- | |
2830 | * 1.2 Host updates SPTE | |
2831 | * to be writable | |
2832 | * 2.1 Guest writes a GPTE for GVA X. | |
2833 | * (GPTE being in the guest page table shadowed | |
2834 | * by the SP from CPU 1.) | |
2835 | * This reads SPTE during the page table walk. | |
2836 | * Since SPTE.W is read as 1, there is no | |
2837 | * fault. | |
2838 | * | |
2839 | * 2.2 Guest issues TLB flush. | |
2840 | * That causes a VM Exit. | |
2841 | * | |
2842 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2843 | * Since it is false, so it just returns. | |
2844 | * | |
2845 | * 2.4 Guest accesses GVA X. | |
2846 | * Since the mapping in the SP was not updated, | |
2847 | * so the old mapping for GVA X incorrectly | |
2848 | * gets used. | |
2849 | * 1.1 Host marks SP | |
2850 | * as unsync | |
2851 | * (sp->unsync = true) | |
2852 | * | |
2853 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2854 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2855 | * pairs with this write barrier. | |
2856 | */ | |
2857 | smp_wmb(); | |
2858 | ||
3d0c27ad | 2859 | return false; |
4731d4c7 MT |
2860 | } |
2861 | ||
ba049e93 | 2862 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2863 | { |
2864 | if (pfn_valid(pfn)) | |
aa2e063a HZ |
2865 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && |
2866 | /* | |
2867 | * Some reserved pages, such as those from NVDIMM | |
2868 | * DAX devices, are not for MMIO, and can be mapped | |
2869 | * with cached memory type for better performance. | |
2870 | * However, the above check misconceives those pages | |
2871 | * as MMIO, and results in KVM mapping them with UC | |
2872 | * memory type, which would hurt the performance. | |
2873 | * Therefore, we check the host memory type in addition | |
2874 | * and only treat UC/UC-/WC pages as MMIO. | |
2875 | */ | |
2876 | (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); | |
d1fe9219 PB |
2877 | |
2878 | return true; | |
2879 | } | |
2880 | ||
5ce4786f JS |
2881 | /* Bits which may be returned by set_spte() */ |
2882 | #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) | |
2883 | #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) | |
2884 | ||
d555c333 | 2885 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2886 | unsigned pte_access, int level, |
ba049e93 | 2887 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2888 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2889 | { |
ffb128c8 | 2890 | u64 spte = 0; |
1e73f9dd | 2891 | int ret = 0; |
ac8d57e5 | 2892 | struct kvm_mmu_page *sp; |
64d4d521 | 2893 | |
54bf36aa | 2894 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2895 | return 0; |
2896 | ||
ac8d57e5 PF |
2897 | sp = page_header(__pa(sptep)); |
2898 | if (sp_ad_disabled(sp)) | |
2899 | spte |= shadow_acc_track_value; | |
2900 | ||
d95c5568 BD |
2901 | /* |
2902 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2903 | * supports exec-only page table entries. In that case, | |
2904 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2905 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2906 | */ | |
ffb128c8 | 2907 | spte |= shadow_present_mask; |
947da538 | 2908 | if (!speculative) |
ac8d57e5 | 2909 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2910 | |
7b52345e SY |
2911 | if (pte_access & ACC_EXEC_MASK) |
2912 | spte |= shadow_x_mask; | |
2913 | else | |
2914 | spte |= shadow_nx_mask; | |
49fde340 | 2915 | |
1c4f1fd6 | 2916 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2917 | spte |= shadow_user_mask; |
49fde340 | 2918 | |
852e3c19 | 2919 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2920 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2921 | if (tdp_enabled) |
4b12f0de | 2922 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2923 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2924 | |
9bdbba13 | 2925 | if (host_writable) |
1403283a | 2926 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2927 | else |
2928 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2929 | |
daaf216c TL |
2930 | if (!kvm_is_mmio_pfn(pfn)) |
2931 | spte |= shadow_me_mask; | |
2932 | ||
35149e21 | 2933 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2934 | |
c2288505 | 2935 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2936 | |
c2193463 | 2937 | /* |
7751babd XG |
2938 | * Other vcpu creates new sp in the window between |
2939 | * mapping_level() and acquiring mmu-lock. We can | |
2940 | * allow guest to retry the access, the mapping can | |
2941 | * be fixed if guest refault. | |
c2193463 | 2942 | */ |
852e3c19 | 2943 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2944 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2945 | goto done; |
38187c83 | 2946 | |
49fde340 | 2947 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2948 | |
ecc5589f MT |
2949 | /* |
2950 | * Optimization: for pte sync, if spte was writable the hash | |
2951 | * lookup is unnecessary (and expensive). Write protection | |
2952 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2953 | * Same reasoning can be applied to dirty page accounting. | |
2954 | */ | |
8dae4445 | 2955 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2956 | goto set_pte; |
2957 | ||
4731d4c7 | 2958 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2959 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2960 | __func__, gfn); |
5ce4786f | 2961 | ret |= SET_SPTE_WRITE_PROTECTED_PT; |
1c4f1fd6 | 2962 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2963 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2964 | } |
2965 | } | |
2966 | ||
9b51a630 | 2967 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2968 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2969 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2970 | } |
1c4f1fd6 | 2971 | |
f160c7b7 JS |
2972 | if (speculative) |
2973 | spte = mark_spte_for_access_track(spte); | |
2974 | ||
38187c83 | 2975 | set_pte: |
6e7d0354 | 2976 | if (mmu_spte_update(sptep, spte)) |
5ce4786f | 2977 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
be38d276 | 2978 | done: |
1e73f9dd MT |
2979 | return ret; |
2980 | } | |
2981 | ||
9b8ebbdb PB |
2982 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
2983 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, | |
2984 | bool speculative, bool host_writable) | |
1e73f9dd MT |
2985 | { |
2986 | int was_rmapped = 0; | |
53a27b39 | 2987 | int rmap_count; |
5ce4786f | 2988 | int set_spte_ret; |
9b8ebbdb | 2989 | int ret = RET_PF_RETRY; |
c2a4eadf | 2990 | bool flush = false; |
1e73f9dd | 2991 | |
f7616203 XG |
2992 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2993 | *sptep, write_fault, gfn); | |
1e73f9dd | 2994 | |
afd28fe1 | 2995 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2996 | /* |
2997 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2998 | * the parent of the now unreachable PTE. | |
2999 | */ | |
852e3c19 JR |
3000 | if (level > PT_PAGE_TABLE_LEVEL && |
3001 | !is_large_pte(*sptep)) { | |
1e73f9dd | 3002 | struct kvm_mmu_page *child; |
d555c333 | 3003 | u64 pte = *sptep; |
1e73f9dd MT |
3004 | |
3005 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 3006 | drop_parent_pte(child, sptep); |
c2a4eadf | 3007 | flush = true; |
d555c333 | 3008 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 3009 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 3010 | spte_to_pfn(*sptep), pfn); |
c3707958 | 3011 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 3012 | flush = true; |
6bed6b9e JR |
3013 | } else |
3014 | was_rmapped = 1; | |
1e73f9dd | 3015 | } |
852e3c19 | 3016 | |
5ce4786f JS |
3017 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
3018 | speculative, true, host_writable); | |
3019 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 3020 | if (write_fault) |
9b8ebbdb | 3021 | ret = RET_PF_EMULATE; |
77c3913b | 3022 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 3023 | } |
c3134ce2 | 3024 | |
c2a4eadf | 3025 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
3026 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
3027 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 3028 | |
029499b4 | 3029 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 3030 | ret = RET_PF_EMULATE; |
ce88decf | 3031 | |
d555c333 | 3032 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 3033 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 3034 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 3035 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 3036 | *sptep, sptep); |
d555c333 | 3037 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
3038 | ++vcpu->kvm->stat.lpages; |
3039 | ||
ffb61bb3 | 3040 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
3041 | if (!was_rmapped) { |
3042 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
3043 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
3044 | rmap_recycle(vcpu, sptep, gfn); | |
3045 | } | |
1c4f1fd6 | 3046 | } |
cb9aaa30 | 3047 | |
f3ac1a4b | 3048 | kvm_release_pfn_clean(pfn); |
029499b4 | 3049 | |
9b8ebbdb | 3050 | return ret; |
1c4f1fd6 AK |
3051 | } |
3052 | ||
ba049e93 | 3053 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
3054 | bool no_dirty_log) |
3055 | { | |
3056 | struct kvm_memory_slot *slot; | |
957ed9ef | 3057 | |
5d163b1c | 3058 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 3059 | if (!slot) |
6c8ee57b | 3060 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 3061 | |
037d92dc | 3062 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
3063 | } |
3064 | ||
3065 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
3066 | struct kvm_mmu_page *sp, | |
3067 | u64 *start, u64 *end) | |
3068 | { | |
3069 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 3070 | struct kvm_memory_slot *slot; |
957ed9ef XG |
3071 | unsigned access = sp->role.access; |
3072 | int i, ret; | |
3073 | gfn_t gfn; | |
3074 | ||
3075 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
3076 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
3077 | if (!slot) | |
957ed9ef XG |
3078 | return -1; |
3079 | ||
d9ef13c2 | 3080 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
3081 | if (ret <= 0) |
3082 | return -1; | |
3083 | ||
3084 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
3085 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
3086 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
3087 | |
3088 | return 0; | |
3089 | } | |
3090 | ||
3091 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
3092 | struct kvm_mmu_page *sp, u64 *sptep) | |
3093 | { | |
3094 | u64 *spte, *start = NULL; | |
3095 | int i; | |
3096 | ||
3097 | WARN_ON(!sp->role.direct); | |
3098 | ||
3099 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
3100 | spte = sp->spt + i; | |
3101 | ||
3102 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 3103 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
3104 | if (!start) |
3105 | continue; | |
3106 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
3107 | break; | |
3108 | start = NULL; | |
3109 | } else if (!start) | |
3110 | start = spte; | |
3111 | } | |
3112 | } | |
3113 | ||
3114 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
3115 | { | |
3116 | struct kvm_mmu_page *sp; | |
3117 | ||
ac8d57e5 PF |
3118 | sp = page_header(__pa(sptep)); |
3119 | ||
957ed9ef | 3120 | /* |
ac8d57e5 PF |
3121 | * Without accessed bits, there's no way to distinguish between |
3122 | * actually accessed translations and prefetched, so disable pte | |
3123 | * prefetch if accessed bits aren't available. | |
957ed9ef | 3124 | */ |
ac8d57e5 | 3125 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
3126 | return; |
3127 | ||
957ed9ef XG |
3128 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
3129 | return; | |
3130 | ||
3131 | __direct_pte_prefetch(vcpu, sp, sptep); | |
3132 | } | |
3133 | ||
7ee0e5b2 | 3134 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 3135 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 3136 | { |
9f652d21 | 3137 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 3138 | struct kvm_mmu_page *sp; |
b90a0e6c | 3139 | int emulate = 0; |
140754bc | 3140 | gfn_t pseudo_gfn; |
6aa8b732 | 3141 | |
44dd3ffa | 3142 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
989c6b34 MT |
3143 | return 0; |
3144 | ||
9f652d21 | 3145 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 3146 | if (iterator.level == level) { |
029499b4 TY |
3147 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
3148 | write, level, gfn, pfn, prefault, | |
3149 | map_writable); | |
957ed9ef | 3150 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
3151 | ++vcpu->stat.pf_fixed; |
3152 | break; | |
6aa8b732 AK |
3153 | } |
3154 | ||
404381c5 | 3155 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 3156 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
3157 | u64 base_addr = iterator.addr; |
3158 | ||
3159 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
3160 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 3161 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 3162 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 3163 | |
98bba238 | 3164 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
3165 | } |
3166 | } | |
b90a0e6c | 3167 | return emulate; |
6aa8b732 AK |
3168 | } |
3169 | ||
77db5cbd | 3170 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3171 | { |
585a8b9b | 3172 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
3173 | } |
3174 | ||
ba049e93 | 3175 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3176 | { |
4d8b81ab XG |
3177 | /* |
3178 | * Do not cache the mmio info caused by writing the readonly gfn | |
3179 | * into the spte otherwise read access on readonly gfn also can | |
3180 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3181 | */ |
3182 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3183 | return RET_PF_EMULATE; |
4d8b81ab | 3184 | |
e6c1502b | 3185 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3186 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3187 | return RET_PF_RETRY; |
d7c55201 | 3188 | } |
edba23e5 | 3189 | |
2c151b25 | 3190 | return -EFAULT; |
bf998156 HY |
3191 | } |
3192 | ||
936a5fe6 | 3193 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3194 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3195 | int *levelp) | |
936a5fe6 | 3196 | { |
ba049e93 | 3197 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3198 | gfn_t gfn = *gfnp; |
3199 | int level = *levelp; | |
3200 | ||
3201 | /* | |
3202 | * Check if it's a transparent hugepage. If this would be an | |
3203 | * hugetlbfs page, level wouldn't be set to | |
3204 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3205 | * here. | |
3206 | */ | |
bf4bea8e | 3207 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3208 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3209 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3210 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3211 | unsigned long mask; |
3212 | /* | |
3213 | * mmu_notifier_retry was successful and we hold the | |
3214 | * mmu_lock here, so the pmd can't become splitting | |
3215 | * from under us, and in turn | |
3216 | * __split_huge_page_refcount() can't run from under | |
3217 | * us and we can safely transfer the refcount from | |
3218 | * PG_tail to PG_head as we switch the pfn to tail to | |
3219 | * head. | |
3220 | */ | |
3221 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3222 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3223 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3224 | if (pfn & mask) { | |
3225 | gfn &= ~mask; | |
3226 | *gfnp = gfn; | |
3227 | kvm_release_pfn_clean(pfn); | |
3228 | pfn &= ~mask; | |
c3586667 | 3229 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3230 | *pfnp = pfn; |
3231 | } | |
3232 | } | |
3233 | } | |
3234 | ||
d7c55201 | 3235 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3236 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3237 | { |
d7c55201 | 3238 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3239 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3240 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3241 | return true; |
d7c55201 XG |
3242 | } |
3243 | ||
ce88decf | 3244 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3245 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3246 | |
798e88b3 | 3247 | return false; |
d7c55201 XG |
3248 | } |
3249 | ||
e5552fd2 | 3250 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3251 | { |
1c118b82 XG |
3252 | /* |
3253 | * Do not fix the mmio spte with invalid generation number which | |
3254 | * need to be updated by slow page fault path. | |
3255 | */ | |
3256 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3257 | return false; | |
3258 | ||
f160c7b7 JS |
3259 | /* See if the page fault is due to an NX violation */ |
3260 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3261 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3262 | return false; | |
3263 | ||
c7ba5b48 | 3264 | /* |
f160c7b7 JS |
3265 | * #PF can be fast if: |
3266 | * 1. The shadow page table entry is not present, which could mean that | |
3267 | * the fault is potentially caused by access tracking (if enabled). | |
3268 | * 2. The shadow page table entry is present and the fault | |
3269 | * is caused by write-protect, that means we just need change the W | |
3270 | * bit of the spte which can be done out of mmu-lock. | |
3271 | * | |
3272 | * However, if access tracking is disabled we know that a non-present | |
3273 | * page must be a genuine page fault where we have to create a new SPTE. | |
3274 | * So, if access tracking is disabled, we return true only for write | |
3275 | * accesses to a present page. | |
c7ba5b48 | 3276 | */ |
c7ba5b48 | 3277 | |
f160c7b7 JS |
3278 | return shadow_acc_track_mask != 0 || |
3279 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3280 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3281 | } |
3282 | ||
97dceba2 JS |
3283 | /* |
3284 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3285 | * someone else modified the SPTE from its original value. | |
3286 | */ | |
c7ba5b48 | 3287 | static bool |
92a476cb | 3288 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3289 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3290 | { |
c7ba5b48 XG |
3291 | gfn_t gfn; |
3292 | ||
3293 | WARN_ON(!sp->role.direct); | |
3294 | ||
9b51a630 KH |
3295 | /* |
3296 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3297 | * order to eliminate unnecessary PML logging. See comments in | |
3298 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3299 | * enabled, so we do not do this. This might result in the same GPA | |
3300 | * to be logged in PML buffer again when the write really happens, and | |
3301 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3302 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3303 | * so non-PML cases won't be impacted. | |
3304 | * | |
3305 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3306 | */ | |
f160c7b7 | 3307 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3308 | return false; |
3309 | ||
d3e328f2 | 3310 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3311 | /* |
3312 | * The gfn of direct spte is stable since it is | |
3313 | * calculated by sp->gfn. | |
3314 | */ | |
3315 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3316 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3317 | } | |
c7ba5b48 XG |
3318 | |
3319 | return true; | |
3320 | } | |
3321 | ||
d3e328f2 JS |
3322 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3323 | { | |
3324 | if (fault_err_code & PFERR_FETCH_MASK) | |
3325 | return is_executable_pte(spte); | |
3326 | ||
3327 | if (fault_err_code & PFERR_WRITE_MASK) | |
3328 | return is_writable_pte(spte); | |
3329 | ||
3330 | /* Fault was on Read access */ | |
3331 | return spte & PT_PRESENT_MASK; | |
3332 | } | |
3333 | ||
c7ba5b48 XG |
3334 | /* |
3335 | * Return value: | |
3336 | * - true: let the vcpu to access on the same address again. | |
3337 | * - false: let the real page fault path to fix it. | |
3338 | */ | |
3339 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3340 | u32 error_code) | |
3341 | { | |
3342 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3343 | struct kvm_mmu_page *sp; |
97dceba2 | 3344 | bool fault_handled = false; |
c7ba5b48 | 3345 | u64 spte = 0ull; |
97dceba2 | 3346 | uint retry_count = 0; |
c7ba5b48 | 3347 | |
44dd3ffa | 3348 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
3349 | return false; |
3350 | ||
e5552fd2 | 3351 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3352 | return false; |
3353 | ||
3354 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3355 | |
97dceba2 | 3356 | do { |
d3e328f2 | 3357 | u64 new_spte; |
c7ba5b48 | 3358 | |
d162f30a JS |
3359 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3360 | if (!is_shadow_present_pte(spte) || | |
3361 | iterator.level < level) | |
3362 | break; | |
3363 | ||
97dceba2 JS |
3364 | sp = page_header(__pa(iterator.sptep)); |
3365 | if (!is_last_spte(spte, sp->role.level)) | |
3366 | break; | |
c7ba5b48 | 3367 | |
97dceba2 | 3368 | /* |
f160c7b7 JS |
3369 | * Check whether the memory access that caused the fault would |
3370 | * still cause it if it were to be performed right now. If not, | |
3371 | * then this is a spurious fault caused by TLB lazily flushed, | |
3372 | * or some other CPU has already fixed the PTE after the | |
3373 | * current CPU took the fault. | |
97dceba2 JS |
3374 | * |
3375 | * Need not check the access of upper level table entries since | |
3376 | * they are always ACC_ALL. | |
3377 | */ | |
d3e328f2 JS |
3378 | if (is_access_allowed(error_code, spte)) { |
3379 | fault_handled = true; | |
3380 | break; | |
3381 | } | |
f160c7b7 | 3382 | |
d3e328f2 JS |
3383 | new_spte = spte; |
3384 | ||
3385 | if (is_access_track_spte(spte)) | |
3386 | new_spte = restore_acc_track_spte(new_spte); | |
3387 | ||
3388 | /* | |
3389 | * Currently, to simplify the code, write-protection can | |
3390 | * be removed in the fast path only if the SPTE was | |
3391 | * write-protected for dirty-logging or access tracking. | |
3392 | */ | |
3393 | if ((error_code & PFERR_WRITE_MASK) && | |
3394 | spte_can_locklessly_be_made_writable(spte)) | |
3395 | { | |
3396 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3397 | |
3398 | /* | |
d3e328f2 JS |
3399 | * Do not fix write-permission on the large spte. Since |
3400 | * we only dirty the first page into the dirty-bitmap in | |
3401 | * fast_pf_fix_direct_spte(), other pages are missed | |
3402 | * if its slot has dirty logging enabled. | |
3403 | * | |
3404 | * Instead, we let the slow page fault path create a | |
3405 | * normal spte to fix the access. | |
3406 | * | |
3407 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3408 | */ |
d3e328f2 | 3409 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3410 | break; |
97dceba2 | 3411 | } |
c7ba5b48 | 3412 | |
f160c7b7 | 3413 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3414 | if (new_spte == spte || |
3415 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3416 | break; |
3417 | ||
3418 | /* | |
3419 | * Currently, fast page fault only works for direct mapping | |
3420 | * since the gfn is not stable for indirect shadow page. See | |
3421 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3422 | */ | |
3423 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3424 | iterator.sptep, spte, |
d3e328f2 | 3425 | new_spte); |
97dceba2 JS |
3426 | if (fault_handled) |
3427 | break; | |
3428 | ||
3429 | if (++retry_count > 4) { | |
3430 | printk_once(KERN_WARNING | |
3431 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3432 | break; | |
3433 | } | |
3434 | ||
97dceba2 | 3435 | } while (true); |
c126d94f | 3436 | |
a72faf25 | 3437 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3438 | spte, fault_handled); |
c7ba5b48 XG |
3439 | walk_shadow_page_lockless_end(vcpu); |
3440 | ||
97dceba2 | 3441 | return fault_handled; |
c7ba5b48 XG |
3442 | } |
3443 | ||
78b2c54a | 3444 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3445 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3446 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3447 | |
c7ba5b48 XG |
3448 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3449 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3450 | { |
3451 | int r; | |
852e3c19 | 3452 | int level; |
fd136902 | 3453 | bool force_pt_level = false; |
ba049e93 | 3454 | kvm_pfn_t pfn; |
e930bffe | 3455 | unsigned long mmu_seq; |
c7ba5b48 | 3456 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3457 | |
fd136902 | 3458 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3459 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3460 | /* |
3461 | * This path builds a PAE pagetable - so we can map | |
3462 | * 2mb pages at maximum. Therefore check if the level | |
3463 | * is larger than that. | |
3464 | */ | |
3465 | if (level > PT_DIRECTORY_LEVEL) | |
3466 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3467 | |
936a5fe6 | 3468 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3469 | } |
05da4558 | 3470 | |
c7ba5b48 | 3471 | if (fast_page_fault(vcpu, v, level, error_code)) |
9b8ebbdb | 3472 | return RET_PF_RETRY; |
c7ba5b48 | 3473 | |
e930bffe | 3474 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3475 | smp_rmb(); |
060c2abe | 3476 | |
78b2c54a | 3477 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
9b8ebbdb | 3478 | return RET_PF_RETRY; |
aaee2c94 | 3479 | |
d7c55201 XG |
3480 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3481 | return r; | |
d196e343 | 3482 | |
aaee2c94 | 3483 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3484 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3485 | goto out_unlock; |
26eeb53c WL |
3486 | if (make_mmu_pages_available(vcpu) < 0) |
3487 | goto out_unlock; | |
936a5fe6 AA |
3488 | if (likely(!force_pt_level)) |
3489 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3490 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3491 | spin_unlock(&vcpu->kvm->mmu_lock); |
3492 | ||
10589a46 | 3493 | return r; |
e930bffe AA |
3494 | |
3495 | out_unlock: | |
3496 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3497 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 3498 | return RET_PF_RETRY; |
10589a46 MT |
3499 | } |
3500 | ||
74b566e6 JS |
3501 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3502 | struct list_head *invalid_list) | |
17ac10ad | 3503 | { |
4db35314 | 3504 | struct kvm_mmu_page *sp; |
17ac10ad | 3505 | |
74b566e6 | 3506 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3507 | return; |
35af577a | 3508 | |
74b566e6 JS |
3509 | sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK); |
3510 | --sp->root_count; | |
3511 | if (!sp->root_count && sp->role.invalid) | |
3512 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3513 | |
74b566e6 JS |
3514 | *root_hpa = INVALID_PAGE; |
3515 | } | |
3516 | ||
08fb59d8 | 3517 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3518 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3519 | ulong roots_to_free) | |
74b566e6 JS |
3520 | { |
3521 | int i; | |
3522 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3523 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3524 | |
b94742c9 | 3525 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3526 | |
08fb59d8 | 3527 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3528 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3529 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3530 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3531 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3532 | break; | |
3533 | ||
3534 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3535 | return; | |
3536 | } | |
35af577a GN |
3537 | |
3538 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3539 | |
b94742c9 JS |
3540 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3541 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
3542 | mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa, | |
3543 | &invalid_list); | |
7c390d35 | 3544 | |
08fb59d8 JS |
3545 | if (free_active_root) { |
3546 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3547 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
3548 | mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, | |
3549 | &invalid_list); | |
3550 | } else { | |
3551 | for (i = 0; i < 4; ++i) | |
3552 | if (mmu->pae_root[i] != 0) | |
3553 | mmu_free_root_page(vcpu->kvm, | |
3554 | &mmu->pae_root[i], | |
3555 | &invalid_list); | |
3556 | mmu->root_hpa = INVALID_PAGE; | |
3557 | } | |
ad7dc69a | 3558 | mmu->root_cr3 = 0; |
17ac10ad | 3559 | } |
74b566e6 | 3560 | |
d98ba053 | 3561 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3562 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad | 3563 | } |
74b566e6 | 3564 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3565 | |
8986ecc0 MT |
3566 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3567 | { | |
3568 | int ret = 0; | |
3569 | ||
3570 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3571 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3572 | ret = 1; |
3573 | } | |
3574 | ||
3575 | return ret; | |
3576 | } | |
3577 | ||
651dd37a JR |
3578 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3579 | { | |
3580 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3581 | unsigned i; |
651dd37a | 3582 | |
44dd3ffa | 3583 | if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3584 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3585 | if(make_mmu_pages_available(vcpu) < 0) { |
3586 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3587 | return -ENOSPC; |
26eeb53c | 3588 | } |
855feb67 | 3589 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
44dd3ffa | 3590 | vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL); |
651dd37a JR |
3591 | ++sp->root_count; |
3592 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa VK |
3593 | vcpu->arch.mmu->root_hpa = __pa(sp->spt); |
3594 | } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3595 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3596 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
651dd37a | 3597 | |
fa4a2c08 | 3598 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3599 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3600 | if (make_mmu_pages_available(vcpu) < 0) { |
3601 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3602 | return -ENOSPC; |
26eeb53c | 3603 | } |
649497d1 | 3604 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3605 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3606 | root = __pa(sp->spt); |
3607 | ++sp->root_count; | |
3608 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa | 3609 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3610 | } |
44dd3ffa | 3611 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3612 | } else |
3613 | BUG(); | |
ad7dc69a | 3614 | vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu); |
651dd37a JR |
3615 | |
3616 | return 0; | |
3617 | } | |
3618 | ||
3619 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3620 | { |
4db35314 | 3621 | struct kvm_mmu_page *sp; |
81407ca5 | 3622 | u64 pdptr, pm_mask; |
ad7dc69a | 3623 | gfn_t root_gfn, root_cr3; |
81407ca5 | 3624 | int i; |
3bb65a22 | 3625 | |
ad7dc69a VK |
3626 | root_cr3 = vcpu->arch.mmu->get_cr3(vcpu); |
3627 | root_gfn = root_cr3 >> PAGE_SHIFT; | |
17ac10ad | 3628 | |
651dd37a JR |
3629 | if (mmu_check_root(vcpu, root_gfn)) |
3630 | return 1; | |
3631 | ||
3632 | /* | |
3633 | * Do we shadow a long mode page table? If so we need to | |
3634 | * write-protect the guests page table root. | |
3635 | */ | |
44dd3ffa VK |
3636 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3637 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
17ac10ad | 3638 | |
fa4a2c08 | 3639 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3640 | |
8facbbff | 3641 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3642 | if (make_mmu_pages_available(vcpu) < 0) { |
3643 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3644 | return -ENOSPC; |
26eeb53c | 3645 | } |
855feb67 | 3646 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
44dd3ffa | 3647 | vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL); |
4db35314 AK |
3648 | root = __pa(sp->spt); |
3649 | ++sp->root_count; | |
8facbbff | 3650 | spin_unlock(&vcpu->kvm->mmu_lock); |
44dd3ffa | 3651 | vcpu->arch.mmu->root_hpa = root; |
ad7dc69a | 3652 | goto set_root_cr3; |
17ac10ad | 3653 | } |
f87f9288 | 3654 | |
651dd37a JR |
3655 | /* |
3656 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3657 | * or a PAE 3-level page table. In either case we need to be aware that |
3658 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3659 | */ |
81407ca5 | 3660 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3661 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3662 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3663 | ||
17ac10ad | 3664 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3665 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
17ac10ad | 3666 | |
fa4a2c08 | 3667 | MMU_WARN_ON(VALID_PAGE(root)); |
44dd3ffa VK |
3668 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3669 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3670 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3671 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3672 | continue; |
3673 | } | |
6de4f3ad | 3674 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3675 | if (mmu_check_root(vcpu, root_gfn)) |
3676 | return 1; | |
5a7388c2 | 3677 | } |
8facbbff | 3678 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3679 | if (make_mmu_pages_available(vcpu) < 0) { |
3680 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3681 | return -ENOSPC; |
26eeb53c | 3682 | } |
bb11c6c9 TY |
3683 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3684 | 0, ACC_ALL); | |
4db35314 AK |
3685 | root = __pa(sp->spt); |
3686 | ++sp->root_count; | |
8facbbff AK |
3687 | spin_unlock(&vcpu->kvm->mmu_lock); |
3688 | ||
44dd3ffa | 3689 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3690 | } |
44dd3ffa | 3691 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3692 | |
3693 | /* | |
3694 | * If we shadow a 32 bit page table with a long mode page | |
3695 | * table we enter this path. | |
3696 | */ | |
44dd3ffa VK |
3697 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3698 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3699 | /* |
3700 | * The additional page necessary for this is only | |
3701 | * allocated on demand. | |
3702 | */ | |
3703 | ||
3704 | u64 *lm_root; | |
3705 | ||
3706 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3707 | if (lm_root == NULL) | |
3708 | return 1; | |
3709 | ||
44dd3ffa | 3710 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3711 | |
44dd3ffa | 3712 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3713 | } |
3714 | ||
44dd3ffa | 3715 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3716 | } |
3717 | ||
ad7dc69a VK |
3718 | set_root_cr3: |
3719 | vcpu->arch.mmu->root_cr3 = root_cr3; | |
3720 | ||
8986ecc0 | 3721 | return 0; |
17ac10ad AK |
3722 | } |
3723 | ||
651dd37a JR |
3724 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3725 | { | |
44dd3ffa | 3726 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3727 | return mmu_alloc_direct_roots(vcpu); |
3728 | else | |
3729 | return mmu_alloc_shadow_roots(vcpu); | |
3730 | } | |
3731 | ||
578e1c4d | 3732 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3733 | { |
3734 | int i; | |
3735 | struct kvm_mmu_page *sp; | |
3736 | ||
44dd3ffa | 3737 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3738 | return; |
3739 | ||
44dd3ffa | 3740 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3741 | return; |
6903074c | 3742 | |
56f17dd3 | 3743 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3744 | |
44dd3ffa VK |
3745 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3746 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
0ba73cda | 3747 | sp = page_header(root); |
578e1c4d JS |
3748 | |
3749 | /* | |
3750 | * Even if another CPU was marking the SP as unsync-ed | |
3751 | * simultaneously, any guest page table changes are not | |
3752 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3753 | * flush strictly after those changes are made. We only need to | |
3754 | * ensure that the other CPU sets these flags before any actual | |
3755 | * changes to the page tables are made. The comments in | |
3756 | * mmu_need_write_protect() describe what could go wrong if this | |
3757 | * requirement isn't satisfied. | |
3758 | */ | |
3759 | if (!smp_load_acquire(&sp->unsync) && | |
3760 | !smp_load_acquire(&sp->unsync_children)) | |
3761 | return; | |
3762 | ||
3763 | spin_lock(&vcpu->kvm->mmu_lock); | |
3764 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3765 | ||
0ba73cda | 3766 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3767 | |
0375f7fa | 3768 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3769 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3770 | return; |
3771 | } | |
578e1c4d JS |
3772 | |
3773 | spin_lock(&vcpu->kvm->mmu_lock); | |
3774 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3775 | ||
0ba73cda | 3776 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3777 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3778 | |
8986ecc0 | 3779 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3780 | root &= PT64_BASE_ADDR_MASK; |
3781 | sp = page_header(root); | |
3782 | mmu_sync_children(vcpu, sp); | |
3783 | } | |
3784 | } | |
0ba73cda | 3785 | |
578e1c4d | 3786 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3787 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3788 | } |
bfd0a56b | 3789 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3790 | |
1871c602 | 3791 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3792 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3793 | { |
ab9ae313 AK |
3794 | if (exception) |
3795 | exception->error_code = 0; | |
6aa8b732 AK |
3796 | return vaddr; |
3797 | } | |
3798 | ||
6539e738 | 3799 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3800 | u32 access, |
3801 | struct x86_exception *exception) | |
6539e738 | 3802 | { |
ab9ae313 AK |
3803 | if (exception) |
3804 | exception->error_code = 0; | |
54987b7a | 3805 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3806 | } |
3807 | ||
d625b155 XG |
3808 | static bool |
3809 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3810 | { | |
3811 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3812 | ||
3813 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3814 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3815 | } | |
3816 | ||
3817 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3818 | { | |
3819 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3820 | } | |
3821 | ||
3822 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3823 | { | |
3824 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3825 | } | |
3826 | ||
ded58749 | 3827 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3828 | { |
9034e6e8 PB |
3829 | /* |
3830 | * A nested guest cannot use the MMIO cache if it is using nested | |
3831 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3832 | */ | |
3833 | if (mmu_is_nested(vcpu)) | |
3834 | return false; | |
3835 | ||
ce88decf XG |
3836 | if (direct) |
3837 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3838 | ||
3839 | return vcpu_match_mmio_gva(vcpu, addr); | |
3840 | } | |
3841 | ||
47ab8751 XG |
3842 | /* return true if reserved bit is detected on spte. */ |
3843 | static bool | |
3844 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3845 | { |
3846 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3847 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
47ab8751 XG |
3848 | int root, leaf; |
3849 | bool reserved = false; | |
ce88decf | 3850 | |
44dd3ffa | 3851 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
47ab8751 | 3852 | goto exit; |
37f6a4e2 | 3853 | |
ce88decf | 3854 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3855 | |
29ecd660 PB |
3856 | for (shadow_walk_init(&iterator, vcpu, addr), |
3857 | leaf = root = iterator.level; | |
47ab8751 XG |
3858 | shadow_walk_okay(&iterator); |
3859 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3860 | spte = mmu_spte_get_lockless(iterator.sptep); |
3861 | ||
3862 | sptes[leaf - 1] = spte; | |
29ecd660 | 3863 | leaf--; |
47ab8751 | 3864 | |
ce88decf XG |
3865 | if (!is_shadow_present_pte(spte)) |
3866 | break; | |
47ab8751 | 3867 | |
44dd3ffa | 3868 | reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte, |
58c95070 | 3869 | iterator.level); |
47ab8751 XG |
3870 | } |
3871 | ||
ce88decf XG |
3872 | walk_shadow_page_lockless_end(vcpu); |
3873 | ||
47ab8751 XG |
3874 | if (reserved) { |
3875 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3876 | __func__, addr); | |
29ecd660 | 3877 | while (root > leaf) { |
47ab8751 XG |
3878 | pr_err("------ spte 0x%llx level %d.\n", |
3879 | sptes[root - 1], root); | |
3880 | root--; | |
3881 | } | |
3882 | } | |
3883 | exit: | |
3884 | *sptep = spte; | |
3885 | return reserved; | |
ce88decf XG |
3886 | } |
3887 | ||
e08d26f0 | 3888 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3889 | { |
3890 | u64 spte; | |
47ab8751 | 3891 | bool reserved; |
ce88decf | 3892 | |
ded58749 | 3893 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3894 | return RET_PF_EMULATE; |
ce88decf | 3895 | |
47ab8751 | 3896 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3897 | if (WARN_ON(reserved)) |
9b8ebbdb | 3898 | return -EINVAL; |
ce88decf XG |
3899 | |
3900 | if (is_mmio_spte(spte)) { | |
3901 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3902 | unsigned access = get_mmio_spte_access(spte); | |
3903 | ||
54bf36aa | 3904 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3905 | return RET_PF_INVALID; |
f8f55942 | 3906 | |
ce88decf XG |
3907 | if (direct) |
3908 | addr = 0; | |
4f022648 XG |
3909 | |
3910 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3911 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3912 | return RET_PF_EMULATE; |
ce88decf XG |
3913 | } |
3914 | ||
ce88decf XG |
3915 | /* |
3916 | * If the page table is zapped by other cpus, let CPU fault again on | |
3917 | * the address. | |
3918 | */ | |
9b8ebbdb | 3919 | return RET_PF_RETRY; |
ce88decf | 3920 | } |
ce88decf | 3921 | |
3d0c27ad XG |
3922 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3923 | u32 error_code, gfn_t gfn) | |
3924 | { | |
3925 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3926 | return false; | |
3927 | ||
3928 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3929 | !(error_code & PFERR_WRITE_MASK)) | |
3930 | return false; | |
3931 | ||
3932 | /* | |
3933 | * guest is writing the page which is write tracked which can | |
3934 | * not be fixed by page fault handler. | |
3935 | */ | |
3936 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3937 | return true; | |
3938 | ||
3939 | return false; | |
3940 | } | |
3941 | ||
e5691a81 XG |
3942 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3943 | { | |
3944 | struct kvm_shadow_walk_iterator iterator; | |
3945 | u64 spte; | |
3946 | ||
44dd3ffa | 3947 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
e5691a81 XG |
3948 | return; |
3949 | ||
3950 | walk_shadow_page_lockless_begin(vcpu); | |
3951 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3952 | clear_sp_write_flooding_count(iterator.sptep); | |
3953 | if (!is_shadow_present_pte(spte)) | |
3954 | break; | |
3955 | } | |
3956 | walk_shadow_page_lockless_end(vcpu); | |
3957 | } | |
3958 | ||
6aa8b732 | 3959 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3960 | u32 error_code, bool prefault) |
6aa8b732 | 3961 | { |
3d0c27ad | 3962 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3963 | int r; |
6aa8b732 | 3964 | |
b8688d51 | 3965 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3966 | |
3d0c27ad | 3967 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3968 | return RET_PF_EMULATE; |
ce88decf | 3969 | |
e2dec939 AK |
3970 | r = mmu_topup_memory_caches(vcpu); |
3971 | if (r) | |
3972 | return r; | |
714b93da | 3973 | |
44dd3ffa | 3974 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
6aa8b732 | 3975 | |
6aa8b732 | 3976 | |
e833240f | 3977 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3978 | error_code, gfn, prefault); |
6aa8b732 AK |
3979 | } |
3980 | ||
7e1fbeac | 3981 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3982 | { |
3983 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3984 | |
7c90705b | 3985 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3986 | arch.gfn = gfn; |
44dd3ffa VK |
3987 | arch.direct_map = vcpu->arch.mmu->direct_map; |
3988 | arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu); | |
af585b92 | 3989 | |
54bf36aa | 3990 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3991 | } |
3992 | ||
9bc1f09f | 3993 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3994 | { |
35754c98 | 3995 | if (unlikely(!lapic_in_kernel(vcpu) || |
2a266f23 HZ |
3996 | kvm_event_needs_reinjection(vcpu) || |
3997 | vcpu->arch.exception.pending)) | |
af585b92 GN |
3998 | return false; |
3999 | ||
52a5c155 | 4000 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) |
9bc1f09f WL |
4001 | return false; |
4002 | ||
af585b92 GN |
4003 | return kvm_x86_ops->interrupt_allowed(vcpu); |
4004 | } | |
4005 | ||
78b2c54a | 4006 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 4007 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 4008 | { |
3520469d | 4009 | struct kvm_memory_slot *slot; |
af585b92 GN |
4010 | bool async; |
4011 | ||
3a2936de JM |
4012 | /* |
4013 | * Don't expose private memslots to L2. | |
4014 | */ | |
4015 | if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
4016 | *pfn = KVM_PFN_NOSLOT; | |
4017 | return false; | |
4018 | } | |
4019 | ||
54bf36aa | 4020 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
4021 | async = false; |
4022 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
4023 | if (!async) |
4024 | return false; /* *pfn has correct page already */ | |
4025 | ||
9bc1f09f | 4026 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 4027 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
4028 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
4029 | trace_kvm_async_pf_doublefault(gva, gfn); | |
4030 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
4031 | return true; | |
4032 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
4033 | return true; | |
4034 | } | |
4035 | ||
3520469d | 4036 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
4037 | return false; |
4038 | } | |
4039 | ||
1261bfa3 | 4040 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 4041 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
4042 | { |
4043 | int r = 1; | |
4044 | ||
c595ceee | 4045 | vcpu->arch.l1tf_flush_l1d = true; |
1261bfa3 WL |
4046 | switch (vcpu->arch.apf.host_apf_reason) { |
4047 | default: | |
4048 | trace_kvm_page_fault(fault_address, error_code); | |
4049 | ||
d0006530 | 4050 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
4051 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
4052 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
4053 | insn_len); | |
4054 | break; | |
4055 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
4056 | vcpu->arch.apf.host_apf_reason = 0; | |
4057 | local_irq_disable(); | |
a2b7861b | 4058 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
4059 | local_irq_enable(); |
4060 | break; | |
4061 | case KVM_PV_REASON_PAGE_READY: | |
4062 | vcpu->arch.apf.host_apf_reason = 0; | |
4063 | local_irq_disable(); | |
4064 | kvm_async_pf_task_wake(fault_address); | |
4065 | local_irq_enable(); | |
4066 | break; | |
4067 | } | |
4068 | return r; | |
4069 | } | |
4070 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
4071 | ||
6a39bbc5 XG |
4072 | static bool |
4073 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
4074 | { | |
4075 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
4076 | ||
4077 | gfn &= ~(page_num - 1); | |
4078 | ||
4079 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
4080 | } | |
4081 | ||
56028d08 | 4082 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 4083 | bool prefault) |
fb72d167 | 4084 | { |
ba049e93 | 4085 | kvm_pfn_t pfn; |
fb72d167 | 4086 | int r; |
852e3c19 | 4087 | int level; |
cd1872f0 | 4088 | bool force_pt_level; |
05da4558 | 4089 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 4090 | unsigned long mmu_seq; |
612819c3 MT |
4091 | int write = error_code & PFERR_WRITE_MASK; |
4092 | bool map_writable; | |
fb72d167 | 4093 | |
44dd3ffa | 4094 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
fb72d167 | 4095 | |
3d0c27ad | 4096 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 4097 | return RET_PF_EMULATE; |
ce88decf | 4098 | |
fb72d167 JR |
4099 | r = mmu_topup_memory_caches(vcpu); |
4100 | if (r) | |
4101 | return r; | |
4102 | ||
fd136902 TY |
4103 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
4104 | PT_DIRECTORY_LEVEL); | |
4105 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 4106 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
4107 | if (level > PT_DIRECTORY_LEVEL && |
4108 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
4109 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 4110 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 4111 | } |
852e3c19 | 4112 | |
c7ba5b48 | 4113 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
9b8ebbdb | 4114 | return RET_PF_RETRY; |
c7ba5b48 | 4115 | |
e930bffe | 4116 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 4117 | smp_rmb(); |
af585b92 | 4118 | |
78b2c54a | 4119 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
9b8ebbdb | 4120 | return RET_PF_RETRY; |
af585b92 | 4121 | |
d7c55201 XG |
4122 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
4123 | return r; | |
4124 | ||
fb72d167 | 4125 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 4126 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 4127 | goto out_unlock; |
26eeb53c WL |
4128 | if (make_mmu_pages_available(vcpu) < 0) |
4129 | goto out_unlock; | |
936a5fe6 AA |
4130 | if (likely(!force_pt_level)) |
4131 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 4132 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 4133 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
4134 | |
4135 | return r; | |
e930bffe AA |
4136 | |
4137 | out_unlock: | |
4138 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4139 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 4140 | return RET_PF_RETRY; |
fb72d167 JR |
4141 | } |
4142 | ||
8a3c1a33 PB |
4143 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
4144 | struct kvm_mmu *context) | |
6aa8b732 | 4145 | { |
6aa8b732 | 4146 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4147 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4148 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4149 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4150 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 4151 | context->root_level = 0; |
6aa8b732 | 4152 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4153 | context->direct_map = true; |
2d48a985 | 4154 | context->nx = false; |
6aa8b732 AK |
4155 | } |
4156 | ||
b94742c9 JS |
4157 | /* |
4158 | * Find out if a previously cached root matching the new CR3/role is available. | |
4159 | * The current root is also inserted into the cache. | |
4160 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
4161 | * returned. | |
4162 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
4163 | * false is returned. This root should now be freed by the caller. | |
4164 | */ | |
4165 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3, | |
4166 | union kvm_mmu_page_role new_role) | |
4167 | { | |
4168 | uint i; | |
4169 | struct kvm_mmu_root_info root; | |
44dd3ffa | 4170 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 4171 | |
ad7dc69a | 4172 | root.cr3 = mmu->root_cr3; |
b94742c9 JS |
4173 | root.hpa = mmu->root_hpa; |
4174 | ||
4175 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
4176 | swap(root, mmu->prev_roots[i]); | |
4177 | ||
4178 | if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) && | |
4179 | page_header(root.hpa) != NULL && | |
4180 | new_role.word == page_header(root.hpa)->role.word) | |
4181 | break; | |
4182 | } | |
4183 | ||
4184 | mmu->root_hpa = root.hpa; | |
ad7dc69a | 4185 | mmu->root_cr3 = root.cr3; |
b94742c9 JS |
4186 | |
4187 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4188 | } | |
4189 | ||
0aab33e4 | 4190 | static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4191 | union kvm_mmu_page_role new_role, |
4192 | bool skip_tlb_flush) | |
6aa8b732 | 4193 | { |
44dd3ffa | 4194 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4195 | |
4196 | /* | |
4197 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4198 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4199 | * later if necessary. | |
4200 | */ | |
4201 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
4202 | mmu->root_level >= PT64_ROOT_4LEVEL) { | |
7c390d35 JS |
4203 | if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT)) |
4204 | return false; | |
4205 | ||
b94742c9 | 4206 | if (cached_root_available(vcpu, new_cr3, new_role)) { |
7c390d35 JS |
4207 | /* |
4208 | * It is possible that the cached previous root page is | |
4209 | * obsolete because of a change in the MMU | |
4210 | * generation number. However, that is accompanied by | |
4211 | * KVM_REQ_MMU_RELOAD, which will free the root that we | |
4212 | * have set here and allocate a new one. | |
4213 | */ | |
4214 | ||
0aab33e4 | 4215 | kvm_make_request(KVM_REQ_LOAD_CR3, vcpu); |
956bf353 JS |
4216 | if (!skip_tlb_flush) { |
4217 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); | |
ade61e28 | 4218 | kvm_x86_ops->tlb_flush(vcpu, true); |
956bf353 JS |
4219 | } |
4220 | ||
4221 | /* | |
4222 | * The last MMIO access's GVA and GPA are cached in the | |
4223 | * VCPU. When switching to a new CR3, that GVA->GPA | |
4224 | * mapping may no longer be valid. So clear any cached | |
4225 | * MMIO info even when we don't need to sync the shadow | |
4226 | * page tables. | |
4227 | */ | |
4228 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
ade61e28 | 4229 | |
7c390d35 JS |
4230 | __clear_sp_write_flooding_count( |
4231 | page_header(mmu->root_hpa)); | |
4232 | ||
7c390d35 JS |
4233 | return true; |
4234 | } | |
4235 | } | |
4236 | ||
4237 | return false; | |
6aa8b732 AK |
4238 | } |
4239 | ||
0aab33e4 | 4240 | static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4241 | union kvm_mmu_page_role new_role, |
4242 | bool skip_tlb_flush) | |
6aa8b732 | 4243 | { |
ade61e28 | 4244 | if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush)) |
6a82cd1c VK |
4245 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, |
4246 | KVM_MMU_ROOT_CURRENT); | |
6aa8b732 AK |
4247 | } |
4248 | ||
ade61e28 | 4249 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush) |
0aab33e4 | 4250 | { |
ade61e28 JS |
4251 | __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu), |
4252 | skip_tlb_flush); | |
0aab33e4 | 4253 | } |
50c28f21 | 4254 | EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3); |
0aab33e4 | 4255 | |
5777ed34 JR |
4256 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4257 | { | |
9f8fe504 | 4258 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4259 | } |
4260 | ||
6389ee94 AK |
4261 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
4262 | struct x86_exception *fault) | |
6aa8b732 | 4263 | { |
44dd3ffa | 4264 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
6aa8b732 AK |
4265 | } |
4266 | ||
54bf36aa | 4267 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 4268 | unsigned access, int *nr_present) |
ce88decf XG |
4269 | { |
4270 | if (unlikely(is_mmio_spte(*sptep))) { | |
4271 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4272 | mmu_spte_clear_no_track(sptep); | |
4273 | return true; | |
4274 | } | |
4275 | ||
4276 | (*nr_present)++; | |
54bf36aa | 4277 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4278 | return true; |
4279 | } | |
4280 | ||
4281 | return false; | |
4282 | } | |
4283 | ||
6bb69c9b PB |
4284 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4285 | unsigned level, unsigned gpte) | |
6fd01b71 | 4286 | { |
6bb69c9b PB |
4287 | /* |
4288 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4289 | * If it is clear, there are no large pages at this level, so clear | |
4290 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4291 | */ | |
4292 | gpte &= level - mmu->last_nonleaf_level; | |
4293 | ||
829ee279 LP |
4294 | /* |
4295 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
4296 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
4297 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
4298 | */ | |
4299 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
4300 | ||
6bb69c9b | 4301 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4302 | } |
4303 | ||
37406aaa NHE |
4304 | #define PTTYPE_EPT 18 /* arbitrary */ |
4305 | #define PTTYPE PTTYPE_EPT | |
4306 | #include "paging_tmpl.h" | |
4307 | #undef PTTYPE | |
4308 | ||
6aa8b732 AK |
4309 | #define PTTYPE 64 |
4310 | #include "paging_tmpl.h" | |
4311 | #undef PTTYPE | |
4312 | ||
4313 | #define PTTYPE 32 | |
4314 | #include "paging_tmpl.h" | |
4315 | #undef PTTYPE | |
4316 | ||
6dc98b86 XG |
4317 | static void |
4318 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4319 | struct rsvd_bits_validate *rsvd_check, | |
4320 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4321 | bool pse, bool amd) |
82725b20 | 4322 | { |
82725b20 | 4323 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4324 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4325 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4326 | |
a0a64f50 | 4327 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4328 | |
6dc98b86 | 4329 | if (!nx) |
82725b20 | 4330 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4331 | if (!gbpages) |
5f7dde7b | 4332 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4333 | |
4334 | /* | |
4335 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4336 | * leaf entries) on AMD CPUs only. | |
4337 | */ | |
6fec2144 | 4338 | if (amd) |
a0c0feb5 PB |
4339 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4340 | ||
6dc98b86 | 4341 | switch (level) { |
82725b20 DE |
4342 | case PT32_ROOT_LEVEL: |
4343 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4344 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4345 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4346 | rsvd_check->rsvd_bits_mask[1][0] = | |
4347 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4348 | |
6dc98b86 | 4349 | if (!pse) { |
a0a64f50 | 4350 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4351 | break; |
4352 | } | |
4353 | ||
82725b20 DE |
4354 | if (is_cpuid_PSE36()) |
4355 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4356 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4357 | else |
4358 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4359 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4360 | break; |
4361 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4362 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4363 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4364 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4365 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4366 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4367 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4368 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4369 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4370 | rsvd_bits(maxphyaddr, 62) | |
4371 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4372 | rsvd_check->rsvd_bits_mask[1][0] = |
4373 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4374 | break; |
855feb67 YZ |
4375 | case PT64_ROOT_5LEVEL: |
4376 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4377 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4378 | rsvd_bits(maxphyaddr, 51); | |
4379 | rsvd_check->rsvd_bits_mask[1][4] = | |
4380 | rsvd_check->rsvd_bits_mask[0][4]; | |
b2869f28 | 4381 | /* fall through */ |
2a7266a8 | 4382 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4383 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4384 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4385 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4386 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4387 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4388 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4389 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4390 | rsvd_bits(maxphyaddr, 51); | |
4391 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4392 | rsvd_bits(maxphyaddr, 51); | |
4393 | rsvd_check->rsvd_bits_mask[1][3] = | |
4394 | rsvd_check->rsvd_bits_mask[0][3]; | |
4395 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4396 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4397 | rsvd_bits(13, 29); |
a0a64f50 | 4398 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4399 | rsvd_bits(maxphyaddr, 51) | |
4400 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4401 | rsvd_check->rsvd_bits_mask[1][0] = |
4402 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4403 | break; |
4404 | } | |
4405 | } | |
4406 | ||
6dc98b86 XG |
4407 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4408 | struct kvm_mmu *context) | |
4409 | { | |
4410 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4411 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4412 | context->nx, |
4413 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4414 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4415 | } |
4416 | ||
81b8eebb XG |
4417 | static void |
4418 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4419 | int maxphyaddr, bool execonly) | |
25d92081 | 4420 | { |
951f9fd7 | 4421 | u64 bad_mt_xwr; |
25d92081 | 4422 | |
855feb67 YZ |
4423 | rsvd_check->rsvd_bits_mask[0][4] = |
4424 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4425 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4426 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4427 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4428 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4429 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4430 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4431 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4432 | |
4433 | /* large page */ | |
855feb67 | 4434 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4435 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4436 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4437 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4438 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4439 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4440 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4441 | |
951f9fd7 PB |
4442 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4443 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4444 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4445 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4446 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4447 | if (!execonly) { | |
4448 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4449 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4450 | } |
951f9fd7 | 4451 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4452 | } |
4453 | ||
81b8eebb XG |
4454 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4455 | struct kvm_mmu *context, bool execonly) | |
4456 | { | |
4457 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4458 | cpuid_maxphyaddr(vcpu), execonly); | |
4459 | } | |
4460 | ||
c258b62b XG |
4461 | /* |
4462 | * the page table on host is the shadow page table for the page | |
4463 | * table in guest or amd nested guest, its mmu features completely | |
4464 | * follow the features in guest. | |
4465 | */ | |
4466 | void | |
4467 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4468 | { | |
36d9594d VK |
4469 | bool uses_nx = context->nx || |
4470 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4471 | struct rsvd_bits_validate *shadow_zero_check; |
4472 | int i; | |
5f0b8199 | 4473 | |
6fec2144 PB |
4474 | /* |
4475 | * Passing "true" to the last argument is okay; it adds a check | |
4476 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4477 | */ | |
ea2800dd BS |
4478 | shadow_zero_check = &context->shadow_zero_check; |
4479 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
c258b62b | 4480 | boot_cpu_data.x86_phys_bits, |
5f0b8199 | 4481 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4482 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4483 | is_pse(vcpu), true); | |
ea2800dd BS |
4484 | |
4485 | if (!shadow_me_mask) | |
4486 | return; | |
4487 | ||
4488 | for (i = context->shadow_root_level; --i >= 0;) { | |
4489 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4490 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4491 | } | |
4492 | ||
c258b62b XG |
4493 | } |
4494 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4495 | ||
6fec2144 PB |
4496 | static inline bool boot_cpu_is_amd(void) |
4497 | { | |
4498 | WARN_ON_ONCE(!tdp_enabled); | |
4499 | return shadow_x_mask == 0; | |
4500 | } | |
4501 | ||
c258b62b XG |
4502 | /* |
4503 | * the direct page table on host, use as much mmu features as | |
4504 | * possible, however, kvm currently does not do execution-protection. | |
4505 | */ | |
4506 | static void | |
4507 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4508 | struct kvm_mmu *context) | |
4509 | { | |
ea2800dd BS |
4510 | struct rsvd_bits_validate *shadow_zero_check; |
4511 | int i; | |
4512 | ||
4513 | shadow_zero_check = &context->shadow_zero_check; | |
4514 | ||
6fec2144 | 4515 | if (boot_cpu_is_amd()) |
ea2800dd | 4516 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
c258b62b XG |
4517 | boot_cpu_data.x86_phys_bits, |
4518 | context->shadow_root_level, false, | |
b8291adc BP |
4519 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4520 | true, true); | |
c258b62b | 4521 | else |
ea2800dd | 4522 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
c258b62b XG |
4523 | boot_cpu_data.x86_phys_bits, |
4524 | false); | |
4525 | ||
ea2800dd BS |
4526 | if (!shadow_me_mask) |
4527 | return; | |
4528 | ||
4529 | for (i = context->shadow_root_level; --i >= 0;) { | |
4530 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4531 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4532 | } | |
c258b62b XG |
4533 | } |
4534 | ||
4535 | /* | |
4536 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4537 | * is the shadow page table for intel nested guest. | |
4538 | */ | |
4539 | static void | |
4540 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4541 | struct kvm_mmu *context, bool execonly) | |
4542 | { | |
4543 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4544 | boot_cpu_data.x86_phys_bits, execonly); | |
4545 | } | |
4546 | ||
09f037aa PB |
4547 | #define BYTE_MASK(access) \ |
4548 | ((1 & (access) ? 2 : 0) | \ | |
4549 | (2 & (access) ? 4 : 0) | \ | |
4550 | (3 & (access) ? 8 : 0) | \ | |
4551 | (4 & (access) ? 16 : 0) | \ | |
4552 | (5 & (access) ? 32 : 0) | \ | |
4553 | (6 & (access) ? 64 : 0) | \ | |
4554 | (7 & (access) ? 128 : 0)) | |
4555 | ||
4556 | ||
edc90b7d XG |
4557 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4558 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4559 | { |
09f037aa PB |
4560 | unsigned byte; |
4561 | ||
4562 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4563 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4564 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4565 | ||
4566 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4567 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4568 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4569 | |
97d64b78 | 4570 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4571 | unsigned pfec = byte << 1; |
4572 | ||
97ec8c06 | 4573 | /* |
09f037aa PB |
4574 | * Each "*f" variable has a 1 bit for each UWX value |
4575 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4576 | */ |
97d64b78 | 4577 | |
09f037aa PB |
4578 | /* Faults from writes to non-writable pages */ |
4579 | u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; | |
4580 | /* Faults from user mode accesses to supervisor pages */ | |
4581 | u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; | |
4582 | /* Faults from fetches of non-executable pages*/ | |
4583 | u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; | |
4584 | /* Faults from kernel mode fetches of user pages */ | |
4585 | u8 smepf = 0; | |
4586 | /* Faults from kernel mode accesses of user pages */ | |
4587 | u8 smapf = 0; | |
4588 | ||
4589 | if (!ept) { | |
4590 | /* Faults from kernel mode accesses to user pages */ | |
4591 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4592 | ||
4593 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4594 | if (!mmu->nx) | |
4595 | ff = 0; | |
4596 | ||
4597 | /* Allow supervisor writes if !cr0.wp */ | |
4598 | if (!cr0_wp) | |
4599 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4600 | ||
4601 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4602 | if (cr4_smep) | |
4603 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4604 | ||
4605 | /* | |
4606 | * SMAP:kernel-mode data accesses from user-mode | |
4607 | * mappings should fault. A fault is considered | |
4608 | * as a SMAP violation if all of the following | |
39337ad1 | 4609 | * conditions are true: |
09f037aa PB |
4610 | * - X86_CR4_SMAP is set in CR4 |
4611 | * - A user page is accessed | |
4612 | * - The access is not a fetch | |
4613 | * - Page fault in kernel mode | |
4614 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4615 | * | |
4616 | * Here, we cover the first three conditions. | |
4617 | * The fourth is computed dynamically in permission_fault(); | |
4618 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4619 | * *not* subject to SMAP restrictions. | |
4620 | */ | |
4621 | if (cr4_smap) | |
4622 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4623 | } |
09f037aa PB |
4624 | |
4625 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4626 | } |
4627 | } | |
4628 | ||
2d344105 HH |
4629 | /* |
4630 | * PKU is an additional mechanism by which the paging controls access to | |
4631 | * user-mode addresses based on the value in the PKRU register. Protection | |
4632 | * key violations are reported through a bit in the page fault error code. | |
4633 | * Unlike other bits of the error code, the PK bit is not known at the | |
4634 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4635 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4636 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4637 | * | |
4638 | * In particular the following conditions come from the error code, the | |
4639 | * page tables and the machine state: | |
4640 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4641 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4642 | * - PK is always zero if U=0 in the page tables | |
4643 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4644 | * | |
4645 | * The PKRU bitmask caches the result of these four conditions. The error | |
4646 | * code (minus the P bit) and the page table's U bit form an index into the | |
4647 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4648 | * with the two bits of the PKRU register corresponding to the protection key. | |
4649 | * For the first three conditions above the bits will be 00, thus masking | |
4650 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4651 | * only will be masked away. | |
4652 | */ | |
4653 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4654 | bool ept) | |
4655 | { | |
4656 | unsigned bit; | |
4657 | bool wp; | |
4658 | ||
4659 | if (ept) { | |
4660 | mmu->pkru_mask = 0; | |
4661 | return; | |
4662 | } | |
4663 | ||
4664 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4665 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4666 | mmu->pkru_mask = 0; | |
4667 | return; | |
4668 | } | |
4669 | ||
4670 | wp = is_write_protection(vcpu); | |
4671 | ||
4672 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4673 | unsigned pfec, pkey_bits; | |
4674 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4675 | ||
4676 | pfec = bit << 1; | |
4677 | ff = pfec & PFERR_FETCH_MASK; | |
4678 | uf = pfec & PFERR_USER_MASK; | |
4679 | wf = pfec & PFERR_WRITE_MASK; | |
4680 | ||
4681 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4682 | pte_user = pfec & PFERR_RSVD_MASK; | |
4683 | ||
4684 | /* | |
4685 | * Only need to check the access which is not an | |
4686 | * instruction fetch and is to a user page. | |
4687 | */ | |
4688 | check_pkey = (!ff && pte_user); | |
4689 | /* | |
4690 | * write access is controlled by PKRU if it is a | |
4691 | * user access or CR0.WP = 1. | |
4692 | */ | |
4693 | check_write = check_pkey && wf && (uf || wp); | |
4694 | ||
4695 | /* PKRU.AD stops both read and write access. */ | |
4696 | pkey_bits = !!check_pkey; | |
4697 | /* PKRU.WD stops write access. */ | |
4698 | pkey_bits |= (!!check_write) << 1; | |
4699 | ||
4700 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4701 | } | |
4702 | } | |
4703 | ||
6bb69c9b | 4704 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4705 | { |
6bb69c9b PB |
4706 | unsigned root_level = mmu->root_level; |
4707 | ||
4708 | mmu->last_nonleaf_level = root_level; | |
4709 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4710 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4711 | } |
4712 | ||
8a3c1a33 PB |
4713 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4714 | struct kvm_mmu *context, | |
4715 | int level) | |
6aa8b732 | 4716 | { |
2d48a985 | 4717 | context->nx = is_nx(vcpu); |
4d6931c3 | 4718 | context->root_level = level; |
2d48a985 | 4719 | |
4d6931c3 | 4720 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4721 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4722 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4723 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4724 | |
fa4a2c08 | 4725 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4726 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4727 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4728 | context->sync_page = paging64_sync_page; |
a7052897 | 4729 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4730 | context->update_pte = paging64_update_pte; |
17ac10ad | 4731 | context->shadow_root_level = level; |
c5a78f2b | 4732 | context->direct_map = false; |
6aa8b732 AK |
4733 | } |
4734 | ||
8a3c1a33 PB |
4735 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4736 | struct kvm_mmu *context) | |
17ac10ad | 4737 | { |
855feb67 YZ |
4738 | int root_level = is_la57_mode(vcpu) ? |
4739 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4740 | ||
4741 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4742 | } |
4743 | ||
8a3c1a33 PB |
4744 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4745 | struct kvm_mmu *context) | |
6aa8b732 | 4746 | { |
2d48a985 | 4747 | context->nx = false; |
4d6931c3 | 4748 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4749 | |
4d6931c3 | 4750 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4751 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4752 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4753 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4754 | |
6aa8b732 | 4755 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4756 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4757 | context->sync_page = paging32_sync_page; |
a7052897 | 4758 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4759 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4760 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4761 | context->direct_map = false; |
6aa8b732 AK |
4762 | } |
4763 | ||
8a3c1a33 PB |
4764 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4765 | struct kvm_mmu *context) | |
6aa8b732 | 4766 | { |
8a3c1a33 | 4767 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4768 | } |
4769 | ||
a336282d VK |
4770 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4771 | { | |
4772 | union kvm_mmu_extended_role ext = {0}; | |
4773 | ||
7dcd5755 | 4774 | ext.cr0_pg = !!is_paging(vcpu); |
a336282d VK |
4775 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4776 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4777 | ext.cr4_pse = !!is_pse(vcpu); | |
4778 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
7dcd5755 | 4779 | ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57); |
de3ccd26 | 4780 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4781 | |
4782 | ext.valid = 1; | |
4783 | ||
4784 | return ext; | |
4785 | } | |
4786 | ||
7dcd5755 VK |
4787 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4788 | bool base_only) | |
4789 | { | |
4790 | union kvm_mmu_role role = {0}; | |
4791 | ||
4792 | role.base.access = ACC_ALL; | |
4793 | role.base.nxe = !!is_nx(vcpu); | |
4794 | role.base.cr4_pae = !!is_pae(vcpu); | |
4795 | role.base.cr0_wp = is_write_protection(vcpu); | |
4796 | role.base.smm = is_smm(vcpu); | |
4797 | role.base.guest_mode = is_guest_mode(vcpu); | |
4798 | ||
4799 | if (base_only) | |
4800 | return role; | |
4801 | ||
4802 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4803 | ||
4804 | return role; | |
4805 | } | |
4806 | ||
4807 | static union kvm_mmu_role | |
4808 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4809 | { |
7dcd5755 | 4810 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4811 | |
7dcd5755 VK |
4812 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
4813 | role.base.level = kvm_x86_ops->get_tdp_level(vcpu); | |
4814 | role.base.direct = true; | |
9fa72119 JS |
4815 | |
4816 | return role; | |
4817 | } | |
4818 | ||
8a3c1a33 | 4819 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4820 | { |
44dd3ffa | 4821 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4822 | union kvm_mmu_role new_role = |
4823 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4824 | |
7dcd5755 VK |
4825 | new_role.base.word &= mmu_base_role_mask.word; |
4826 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4827 | return; | |
4828 | ||
4829 | context->mmu_role.as_u64 = new_role.as_u64; | |
fb72d167 | 4830 | context->page_fault = tdp_page_fault; |
e8bc217a | 4831 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4832 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4833 | context->update_pte = nonpaging_update_pte; |
855feb67 | 4834 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu); |
c5a78f2b | 4835 | context->direct_map = true; |
1c97f0a0 | 4836 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4837 | context->get_cr3 = get_cr3; |
e4e517b4 | 4838 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4839 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4840 | |
4841 | if (!is_paging(vcpu)) { | |
2d48a985 | 4842 | context->nx = false; |
fb72d167 JR |
4843 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4844 | context->root_level = 0; | |
4845 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4846 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4847 | context->root_level = is_la57_mode(vcpu) ? |
4848 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4849 | reset_rsvds_bits_mask(vcpu, context); |
4850 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4851 | } else if (is_pae(vcpu)) { |
2d48a985 | 4852 | context->nx = is_nx(vcpu); |
fb72d167 | 4853 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4854 | reset_rsvds_bits_mask(vcpu, context); |
4855 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4856 | } else { |
2d48a985 | 4857 | context->nx = false; |
fb72d167 | 4858 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4859 | reset_rsvds_bits_mask(vcpu, context); |
4860 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4861 | } |
4862 | ||
25d92081 | 4863 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4864 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4865 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4866 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4867 | } |
4868 | ||
7dcd5755 VK |
4869 | static union kvm_mmu_role |
4870 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4871 | { | |
4872 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4873 | ||
4874 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4875 | !is_write_protection(vcpu); | |
4876 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4877 | !is_write_protection(vcpu); | |
4878 | role.base.direct = !is_paging(vcpu); | |
9fa72119 JS |
4879 | |
4880 | if (!is_long_mode(vcpu)) | |
7dcd5755 | 4881 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4882 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4883 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4884 | else |
7dcd5755 | 4885 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4886 | |
4887 | return role; | |
4888 | } | |
4889 | ||
4890 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) | |
4891 | { | |
44dd3ffa | 4892 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4893 | union kvm_mmu_role new_role = |
4894 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4895 | ||
4896 | new_role.base.word &= mmu_base_role_mask.word; | |
4897 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4898 | return; | |
6aa8b732 AK |
4899 | |
4900 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4901 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4902 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4903 | paging64_init_context(vcpu, context); |
6aa8b732 | 4904 | else if (is_pae(vcpu)) |
8a3c1a33 | 4905 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4906 | else |
8a3c1a33 | 4907 | paging32_init_context(vcpu, context); |
a770f6f2 | 4908 | |
7dcd5755 | 4909 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4910 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4911 | } |
4912 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4913 | ||
a336282d VK |
4914 | static union kvm_mmu_role |
4915 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
4916 | bool execonly) | |
9fa72119 | 4917 | { |
a336282d | 4918 | union kvm_mmu_role role; |
14c07ad8 | 4919 | |
a336282d VK |
4920 | /* Base role is inherited from root_mmu */ |
4921 | role.base.word = vcpu->arch.root_mmu.mmu_role.base.word; | |
4922 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
9fa72119 | 4923 | |
a336282d VK |
4924 | role.base.level = PT64_ROOT_4LEVEL; |
4925 | role.base.direct = false; | |
4926 | role.base.ad_disabled = !accessed_dirty; | |
4927 | role.base.guest_mode = true; | |
4928 | role.base.access = ACC_ALL; | |
9fa72119 | 4929 | |
a336282d | 4930 | role.ext.execonly = execonly; |
9fa72119 JS |
4931 | |
4932 | return role; | |
4933 | } | |
4934 | ||
ae1e2d10 | 4935 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4936 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4937 | { |
44dd3ffa | 4938 | struct kvm_mmu *context = vcpu->arch.mmu; |
a336282d VK |
4939 | union kvm_mmu_role new_role = |
4940 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
4941 | execonly); | |
4942 | ||
4943 | __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false); | |
4944 | ||
4945 | new_role.base.word &= mmu_base_role_mask.word; | |
4946 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4947 | return; | |
ad896af0 | 4948 | |
855feb67 | 4949 | context->shadow_root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4950 | |
4951 | context->nx = true; | |
ae1e2d10 | 4952 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4953 | context->page_fault = ept_page_fault; |
4954 | context->gva_to_gpa = ept_gva_to_gpa; | |
4955 | context->sync_page = ept_sync_page; | |
4956 | context->invlpg = ept_invlpg; | |
4957 | context->update_pte = ept_update_pte; | |
855feb67 | 4958 | context->root_level = PT64_ROOT_4LEVEL; |
155a97a3 | 4959 | context->direct_map = false; |
a336282d | 4960 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4961 | |
155a97a3 | 4962 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4963 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4964 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4965 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4966 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4967 | } |
4968 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4969 | ||
8a3c1a33 | 4970 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4971 | { |
44dd3ffa | 4972 | struct kvm_mmu *context = vcpu->arch.mmu; |
ad896af0 PB |
4973 | |
4974 | kvm_init_shadow_mmu(vcpu); | |
4975 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4976 | context->get_cr3 = get_cr3; | |
4977 | context->get_pdptr = kvm_pdptr_read; | |
4978 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4979 | } |
4980 | ||
8a3c1a33 | 4981 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4982 | { |
bf627a92 | 4983 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
4984 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4985 | ||
bf627a92 VK |
4986 | new_role.base.word &= mmu_base_role_mask.word; |
4987 | if (new_role.as_u64 == g_context->mmu_role.as_u64) | |
4988 | return; | |
4989 | ||
4990 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
02f59dc9 | 4991 | g_context->get_cr3 = get_cr3; |
e4e517b4 | 4992 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4993 | g_context->inject_page_fault = kvm_inject_page_fault; |
4994 | ||
4995 | /* | |
44dd3ffa | 4996 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4997 | * L1's nested page tables (e.g. EPT12). The nested translation |
4998 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4999 | * L2's page tables as the first level of translation and L1's | |
5000 | * nested page tables as the second level of translation. Basically | |
5001 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
5002 | */ |
5003 | if (!is_paging(vcpu)) { | |
2d48a985 | 5004 | g_context->nx = false; |
02f59dc9 JR |
5005 | g_context->root_level = 0; |
5006 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
5007 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 5008 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
5009 | g_context->root_level = is_la57_mode(vcpu) ? |
5010 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 5011 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5012 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5013 | } else if (is_pae(vcpu)) { | |
2d48a985 | 5014 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 5015 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 5016 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5017 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5018 | } else { | |
2d48a985 | 5019 | g_context->nx = false; |
02f59dc9 | 5020 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 5021 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5022 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
5023 | } | |
5024 | ||
25d92081 | 5025 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 5026 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 5027 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
5028 | } |
5029 | ||
1c53da3f | 5030 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 5031 | { |
1c53da3f | 5032 | if (reset_roots) { |
b94742c9 JS |
5033 | uint i; |
5034 | ||
44dd3ffa | 5035 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
5036 | |
5037 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 5038 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
5039 | } |
5040 | ||
02f59dc9 | 5041 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 5042 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 5043 | else if (tdp_enabled) |
e0c6db3e | 5044 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 5045 | else |
e0c6db3e | 5046 | init_kvm_softmmu(vcpu); |
fb72d167 | 5047 | } |
1c53da3f | 5048 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 5049 | |
9fa72119 JS |
5050 | static union kvm_mmu_page_role |
5051 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
5052 | { | |
7dcd5755 VK |
5053 | union kvm_mmu_role role; |
5054 | ||
9fa72119 | 5055 | if (tdp_enabled) |
7dcd5755 | 5056 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 5057 | else |
7dcd5755 VK |
5058 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
5059 | ||
5060 | return role.base; | |
9fa72119 | 5061 | } |
fb72d167 | 5062 | |
8a3c1a33 | 5063 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 5064 | { |
95f93af4 | 5065 | kvm_mmu_unload(vcpu); |
1c53da3f | 5066 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 5067 | } |
8668a3c4 | 5068 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
5069 | |
5070 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 5071 | { |
714b93da AK |
5072 | int r; |
5073 | ||
e2dec939 | 5074 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
5075 | if (r) |
5076 | goto out; | |
8986ecc0 | 5077 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 5078 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
5079 | if (r) |
5080 | goto out; | |
6e42782f | 5081 | kvm_mmu_load_cr3(vcpu); |
afe828d1 | 5082 | kvm_x86_ops->tlb_flush(vcpu, true); |
714b93da AK |
5083 | out: |
5084 | return r; | |
6aa8b732 | 5085 | } |
17c3ba9d AK |
5086 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
5087 | ||
5088 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5089 | { | |
14c07ad8 VK |
5090 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5091 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5092 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5093 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5094 | } |
4b16184c | 5095 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 5096 | |
0028425f | 5097 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
5098 | struct kvm_mmu_page *sp, u64 *spte, |
5099 | const void *new) | |
0028425f | 5100 | { |
30945387 | 5101 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
5102 | ++vcpu->kvm->stat.mmu_pde_zapped; |
5103 | return; | |
30945387 | 5104 | } |
0028425f | 5105 | |
4cee5764 | 5106 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 5107 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
5108 | } |
5109 | ||
79539cec AK |
5110 | static bool need_remote_flush(u64 old, u64 new) |
5111 | { | |
5112 | if (!is_shadow_present_pte(old)) | |
5113 | return false; | |
5114 | if (!is_shadow_present_pte(new)) | |
5115 | return true; | |
5116 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5117 | return true; | |
53166229 GN |
5118 | old ^= shadow_nx_mask; |
5119 | new ^= shadow_nx_mask; | |
79539cec AK |
5120 | return (old & ~new & PT64_PERM_MASK) != 0; |
5121 | } | |
5122 | ||
889e5cbc | 5123 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5124 | int *bytes) |
da4a00f0 | 5125 | { |
0e0fee5c | 5126 | u64 gentry = 0; |
889e5cbc | 5127 | int r; |
72016f3a | 5128 | |
72016f3a AK |
5129 | /* |
5130 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5131 | * as the current vcpu paging mode since we update the sptes only |
5132 | * when they have the same mode. | |
72016f3a | 5133 | */ |
889e5cbc | 5134 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5135 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5136 | *gpa &= ~(gpa_t)7; |
5137 | *bytes = 8; | |
08e850c6 AK |
5138 | } |
5139 | ||
0e0fee5c JS |
5140 | if (*bytes == 4 || *bytes == 8) { |
5141 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5142 | if (r) | |
5143 | gentry = 0; | |
72016f3a AK |
5144 | } |
5145 | ||
889e5cbc XG |
5146 | return gentry; |
5147 | } | |
5148 | ||
5149 | /* | |
5150 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5151 | * or we may be forking, in which case it is better to unmap the page. | |
5152 | */ | |
a138fe75 | 5153 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5154 | { |
a30f47cb XG |
5155 | /* |
5156 | * Skip write-flooding detected for the sp whose level is 1, because | |
5157 | * it can become unsync, then the guest page is not write-protected. | |
5158 | */ | |
f71fa31f | 5159 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 5160 | return false; |
3246af0e | 5161 | |
e5691a81 XG |
5162 | atomic_inc(&sp->write_flooding_count); |
5163 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5164 | } |
5165 | ||
5166 | /* | |
5167 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5168 | * indicate a page is not used as a page table. | |
5169 | */ | |
5170 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5171 | int bytes) | |
5172 | { | |
5173 | unsigned offset, pte_size, misaligned; | |
5174 | ||
5175 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5176 | gpa, bytes, sp->role.word); | |
5177 | ||
5178 | offset = offset_in_page(gpa); | |
5179 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
5180 | |
5181 | /* | |
5182 | * Sometimes, the OS only writes the last one bytes to update status | |
5183 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5184 | */ | |
5185 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5186 | return false; | |
5187 | ||
889e5cbc XG |
5188 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5189 | misaligned |= bytes < 4; | |
5190 | ||
5191 | return misaligned; | |
5192 | } | |
5193 | ||
5194 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5195 | { | |
5196 | unsigned page_offset, quadrant; | |
5197 | u64 *spte; | |
5198 | int level; | |
5199 | ||
5200 | page_offset = offset_in_page(gpa); | |
5201 | level = sp->role.level; | |
5202 | *nspte = 1; | |
5203 | if (!sp->role.cr4_pae) { | |
5204 | page_offset <<= 1; /* 32->64 */ | |
5205 | /* | |
5206 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5207 | * only 2MB. So we need to double the offset again | |
5208 | * and zap two pdes instead of one. | |
5209 | */ | |
5210 | if (level == PT32_ROOT_LEVEL) { | |
5211 | page_offset &= ~7; /* kill rounding error */ | |
5212 | page_offset <<= 1; | |
5213 | *nspte = 2; | |
5214 | } | |
5215 | quadrant = page_offset >> PAGE_SHIFT; | |
5216 | page_offset &= ~PAGE_MASK; | |
5217 | if (quadrant != sp->role.quadrant) | |
5218 | return NULL; | |
5219 | } | |
5220 | ||
5221 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5222 | return spte; | |
5223 | } | |
5224 | ||
13d268ca | 5225 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5226 | const u8 *new, int bytes, |
5227 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5228 | { |
5229 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5230 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5231 | LIST_HEAD(invalid_list); |
5232 | u64 entry, gentry, *spte; | |
5233 | int npte; | |
b8c67b7a | 5234 | bool remote_flush, local_flush; |
889e5cbc XG |
5235 | |
5236 | /* | |
5237 | * If we don't have indirect shadow pages, it means no page is | |
5238 | * write-protected, so we can exit simply. | |
5239 | */ | |
6aa7de05 | 5240 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5241 | return; |
5242 | ||
b8c67b7a | 5243 | remote_flush = local_flush = false; |
889e5cbc XG |
5244 | |
5245 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5246 | ||
889e5cbc XG |
5247 | /* |
5248 | * No need to care whether allocation memory is successful | |
5249 | * or not since pte prefetch is skiped if it does not have | |
5250 | * enough objects in the cache. | |
5251 | */ | |
5252 | mmu_topup_memory_caches(vcpu); | |
5253 | ||
5254 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
5255 | |
5256 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5257 | ||
889e5cbc | 5258 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5259 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5260 | |
b67bfe0d | 5261 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5262 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5263 | detect_write_flooding(sp)) { |
b8c67b7a | 5264 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5265 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5266 | continue; |
5267 | } | |
889e5cbc XG |
5268 | |
5269 | spte = get_written_sptes(sp, gpa, &npte); | |
5270 | if (!spte) | |
5271 | continue; | |
5272 | ||
0671a8e7 | 5273 | local_flush = true; |
ac1b714e | 5274 | while (npte--) { |
36d9594d VK |
5275 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
5276 | ||
79539cec | 5277 | entry = *spte; |
38e3b2b2 | 5278 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf | 5279 | if (gentry && |
36d9594d | 5280 | !((sp->role.word ^ base_role) |
9fa72119 | 5281 | & mmu_base_role_mask.word) && rmap_can_add(vcpu)) |
7c562522 | 5282 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5283 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5284 | remote_flush = true; |
ac1b714e | 5285 | ++spte; |
9b7a0325 | 5286 | } |
9b7a0325 | 5287 | } |
b8c67b7a | 5288 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5289 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5290 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5291 | } |
5292 | ||
a436036b AK |
5293 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5294 | { | |
10589a46 MT |
5295 | gpa_t gpa; |
5296 | int r; | |
a436036b | 5297 | |
44dd3ffa | 5298 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
5299 | return 0; |
5300 | ||
1871c602 | 5301 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5302 | |
10589a46 | 5303 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5304 | |
10589a46 | 5305 | return r; |
a436036b | 5306 | } |
577bdc49 | 5307 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5308 | |
26eeb53c | 5309 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 5310 | { |
d98ba053 | 5311 | LIST_HEAD(invalid_list); |
103ad25a | 5312 | |
81f4f76b | 5313 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 5314 | return 0; |
81f4f76b | 5315 | |
5da59607 TY |
5316 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
5317 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
5318 | break; | |
ebeace86 | 5319 | |
4cee5764 | 5320 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 5321 | } |
aa6bd187 | 5322 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
5323 | |
5324 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
5325 | return -ENOSPC; | |
5326 | return 0; | |
ebeace86 | 5327 | } |
ebeace86 | 5328 | |
14727754 | 5329 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 5330 | void *insn, int insn_len) |
3067714c | 5331 | { |
472faffa | 5332 | int r, emulation_type = 0; |
3067714c | 5333 | enum emulation_result er; |
44dd3ffa | 5334 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5335 | |
618232e2 | 5336 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
44dd3ffa | 5337 | if (vcpu->arch.mmu->direct_map) { |
618232e2 BS |
5338 | vcpu->arch.gpa_available = true; |
5339 | vcpu->arch.gpa_val = cr2; | |
5340 | } | |
3067714c | 5341 | |
9b8ebbdb | 5342 | r = RET_PF_INVALID; |
e9ee956e TY |
5343 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
5344 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
472faffa | 5345 | if (r == RET_PF_EMULATE) |
e9ee956e | 5346 | goto emulate; |
e9ee956e | 5347 | } |
3067714c | 5348 | |
9b8ebbdb | 5349 | if (r == RET_PF_INVALID) { |
44dd3ffa VK |
5350 | r = vcpu->arch.mmu->page_fault(vcpu, cr2, |
5351 | lower_32_bits(error_code), | |
5352 | false); | |
9b8ebbdb PB |
5353 | WARN_ON(r == RET_PF_INVALID); |
5354 | } | |
5355 | ||
5356 | if (r == RET_PF_RETRY) | |
5357 | return 1; | |
3067714c | 5358 | if (r < 0) |
e9ee956e | 5359 | return r; |
3067714c | 5360 | |
14727754 TL |
5361 | /* |
5362 | * Before emulating the instruction, check if the error code | |
5363 | * was due to a RO violation while translating the guest page. | |
5364 | * This can occur when using nested virtualization with nested | |
5365 | * paging in both guests. If true, we simply unprotect the page | |
5366 | * and resume the guest. | |
14727754 | 5367 | */ |
44dd3ffa | 5368 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5369 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
5370 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
5371 | return 1; | |
5372 | } | |
5373 | ||
472faffa SC |
5374 | /* |
5375 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5376 | * optimistically try to just unprotect the page and let the processor | |
5377 | * re-execute the instruction that caused the page fault. Do not allow | |
5378 | * retrying MMIO emulation, as it's not only pointless but could also | |
5379 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5380 | * faulting on the non-existent MMIO address. Retrying an instruction |
5381 | * from a nested guest is also pointless and dangerous as we are only | |
5382 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5383 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5384 | */ |
6c3dfeb6 | 5385 | if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu)) |
472faffa | 5386 | emulation_type = EMULTYPE_ALLOW_RETRY; |
e9ee956e | 5387 | emulate: |
00b10fe1 BS |
5388 | /* |
5389 | * On AMD platforms, under certain conditions insn_len may be zero on #NPF. | |
5390 | * This can happen if a guest gets a page-fault on data access but the HW | |
5391 | * table walker is not able to read the instruction page (e.g instruction | |
5392 | * page is not present in memory). In those cases we simply restart the | |
5393 | * guest. | |
5394 | */ | |
5395 | if (unlikely(insn && !insn_len)) | |
5396 | return 1; | |
5397 | ||
1cb3f3ae | 5398 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
5399 | |
5400 | switch (er) { | |
5401 | case EMULATE_DONE: | |
5402 | return 1; | |
ac0a48c3 | 5403 | case EMULATE_USER_EXIT: |
3067714c | 5404 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 5405 | /* fall through */ |
3067714c | 5406 | case EMULATE_FAIL: |
3f5d18a9 | 5407 | return 0; |
3067714c AK |
5408 | default: |
5409 | BUG(); | |
5410 | } | |
3067714c AK |
5411 | } |
5412 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5413 | ||
a7052897 MT |
5414 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5415 | { | |
44dd3ffa | 5416 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 5417 | int i; |
7eb77e9f | 5418 | |
faff8758 JS |
5419 | /* INVLPG on a * non-canonical address is a NOP according to the SDM. */ |
5420 | if (is_noncanonical_address(gva, vcpu)) | |
5421 | return; | |
5422 | ||
7eb77e9f | 5423 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
956bf353 JS |
5424 | |
5425 | /* | |
5426 | * INVLPG is required to invalidate any global mappings for the VA, | |
5427 | * irrespective of PCID. Since it would take us roughly similar amount | |
b94742c9 JS |
5428 | * of work to determine whether any of the prev_root mappings of the VA |
5429 | * is marked global, or to just sync it blindly, so we might as well | |
5430 | * just always sync it. | |
956bf353 | 5431 | * |
b94742c9 JS |
5432 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5433 | * synced when switching to that cr3, so nothing needs to be done here | |
5434 | * for them. | |
956bf353 | 5435 | */ |
b94742c9 JS |
5436 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
5437 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5438 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
956bf353 | 5439 | |
faff8758 | 5440 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); |
a7052897 MT |
5441 | ++vcpu->stat.invlpg; |
5442 | } | |
5443 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5444 | ||
eb4b248e JS |
5445 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5446 | { | |
44dd3ffa | 5447 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5448 | bool tlb_flush = false; |
b94742c9 | 5449 | uint i; |
eb4b248e JS |
5450 | |
5451 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5452 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5453 | tlb_flush = true; |
eb4b248e JS |
5454 | } |
5455 | ||
b94742c9 JS |
5456 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5457 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
5458 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) { | |
5459 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5460 | tlb_flush = true; | |
5461 | } | |
956bf353 | 5462 | } |
ade61e28 | 5463 | |
faff8758 JS |
5464 | if (tlb_flush) |
5465 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); | |
5466 | ||
eb4b248e JS |
5467 | ++vcpu->stat.invlpg; |
5468 | ||
5469 | /* | |
b94742c9 JS |
5470 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5471 | * synced when switching to that cr3, so nothing needs to be done here | |
5472 | * for them. | |
eb4b248e JS |
5473 | */ |
5474 | } | |
5475 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5476 | ||
18552672 JR |
5477 | void kvm_enable_tdp(void) |
5478 | { | |
5479 | tdp_enabled = true; | |
5480 | } | |
5481 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
5482 | ||
5f4cb662 JR |
5483 | void kvm_disable_tdp(void) |
5484 | { | |
5485 | tdp_enabled = false; | |
5486 | } | |
5487 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
5488 | ||
6aa8b732 AK |
5489 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
5490 | { | |
44dd3ffa VK |
5491 | free_page((unsigned long)vcpu->arch.mmu->pae_root); |
5492 | free_page((unsigned long)vcpu->arch.mmu->lm_root); | |
6aa8b732 AK |
5493 | } |
5494 | ||
5495 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
5496 | { | |
17ac10ad | 5497 | struct page *page; |
6aa8b732 AK |
5498 | int i; |
5499 | ||
ee6268ba LC |
5500 | if (tdp_enabled) |
5501 | return 0; | |
5502 | ||
17ac10ad AK |
5503 | /* |
5504 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
5505 | * Therefore we need to allocate shadow page tables in the first | |
5506 | * 4GB of memory, which happens to fit the DMA32 zone. | |
5507 | */ | |
5508 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
5509 | if (!page) | |
d7fa6ab2 WY |
5510 | return -ENOMEM; |
5511 | ||
44dd3ffa | 5512 | vcpu->arch.mmu->pae_root = page_address(page); |
17ac10ad | 5513 | for (i = 0; i < 4; ++i) |
44dd3ffa | 5514 | vcpu->arch.mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5515 | |
6aa8b732 | 5516 | return 0; |
6aa8b732 AK |
5517 | } |
5518 | ||
8018c27b | 5519 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5520 | { |
b94742c9 JS |
5521 | uint i; |
5522 | ||
44dd3ffa VK |
5523 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5524 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5525 | |
44dd3ffa | 5526 | vcpu->arch.root_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5527 | vcpu->arch.root_mmu.root_cr3 = 0; |
44dd3ffa | 5528 | vcpu->arch.root_mmu.translate_gpa = translate_gpa; |
b94742c9 | 5529 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
44dd3ffa | 5530 | vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
6aa8b732 | 5531 | |
14c07ad8 | 5532 | vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE; |
ad7dc69a | 5533 | vcpu->arch.guest_mmu.root_cr3 = 0; |
14c07ad8 VK |
5534 | vcpu->arch.guest_mmu.translate_gpa = translate_gpa; |
5535 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5536 | vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
2c264957 | 5537 | |
14c07ad8 | 5538 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
8018c27b | 5539 | return alloc_mmu_pages(vcpu); |
6aa8b732 AK |
5540 | } |
5541 | ||
b5f5fdca | 5542 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5543 | struct kvm_memory_slot *slot, |
5544 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
5545 | { |
5546 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
5547 | } | |
5548 | ||
13d268ca XG |
5549 | void kvm_mmu_init_vm(struct kvm *kvm) |
5550 | { | |
5551 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5552 | ||
5553 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 5554 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
5555 | kvm_page_track_register_notifier(kvm, node); |
5556 | } | |
5557 | ||
5558 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
5559 | { | |
5560 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5561 | ||
5562 | kvm_page_track_unregister_notifier(kvm, node); | |
5563 | } | |
5564 | ||
1bad2b2a | 5565 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 5566 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
5567 | |
5568 | /* The caller should hold mmu-lock before calling this function. */ | |
928a4c39 | 5569 | static __always_inline bool |
1bad2b2a XG |
5570 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5571 | slot_level_handler fn, int start_level, int end_level, | |
5572 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5573 | { | |
5574 | struct slot_rmap_walk_iterator iterator; | |
5575 | bool flush = false; | |
5576 | ||
5577 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5578 | end_gfn, &iterator) { | |
5579 | if (iterator.rmap) | |
5580 | flush |= fn(kvm, iterator.rmap); | |
5581 | ||
5582 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5583 | if (flush && lock_flush_tlb) { | |
5584 | kvm_flush_remote_tlbs(kvm); | |
5585 | flush = false; | |
5586 | } | |
5587 | cond_resched_lock(&kvm->mmu_lock); | |
5588 | } | |
5589 | } | |
5590 | ||
5591 | if (flush && lock_flush_tlb) { | |
5592 | kvm_flush_remote_tlbs(kvm); | |
5593 | flush = false; | |
5594 | } | |
5595 | ||
5596 | return flush; | |
5597 | } | |
5598 | ||
928a4c39 | 5599 | static __always_inline bool |
1bad2b2a XG |
5600 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5601 | slot_level_handler fn, int start_level, int end_level, | |
5602 | bool lock_flush_tlb) | |
5603 | { | |
5604 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5605 | end_level, memslot->base_gfn, | |
5606 | memslot->base_gfn + memslot->npages - 1, | |
5607 | lock_flush_tlb); | |
5608 | } | |
5609 | ||
928a4c39 | 5610 | static __always_inline bool |
1bad2b2a XG |
5611 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5612 | slot_level_handler fn, bool lock_flush_tlb) | |
5613 | { | |
5614 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5615 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5616 | } | |
5617 | ||
928a4c39 | 5618 | static __always_inline bool |
1bad2b2a XG |
5619 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5620 | slot_level_handler fn, bool lock_flush_tlb) | |
5621 | { | |
5622 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5623 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5624 | } | |
5625 | ||
928a4c39 | 5626 | static __always_inline bool |
1bad2b2a XG |
5627 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5628 | slot_level_handler fn, bool lock_flush_tlb) | |
5629 | { | |
5630 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5631 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5632 | } | |
5633 | ||
efdfe536 XG |
5634 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5635 | { | |
5636 | struct kvm_memslots *slots; | |
5637 | struct kvm_memory_slot *memslot; | |
71883a62 LT |
5638 | bool flush_tlb = true; |
5639 | bool flush = false; | |
9da0e4d5 | 5640 | int i; |
efdfe536 | 5641 | |
71883a62 LT |
5642 | if (kvm_available_flush_tlb_with_range()) |
5643 | flush_tlb = false; | |
5644 | ||
efdfe536 | 5645 | spin_lock(&kvm->mmu_lock); |
9da0e4d5 PB |
5646 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5647 | slots = __kvm_memslots(kvm, i); | |
5648 | kvm_for_each_memslot(memslot, slots) { | |
5649 | gfn_t start, end; | |
5650 | ||
5651 | start = max(gfn_start, memslot->base_gfn); | |
5652 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5653 | if (start >= end) | |
5654 | continue; | |
efdfe536 | 5655 | |
71883a62 LT |
5656 | flush |= slot_handle_level_range(kvm, memslot, |
5657 | kvm_zap_rmapp, PT_PAGE_TABLE_LEVEL, | |
5658 | PT_MAX_HUGEPAGE_LEVEL, start, | |
5659 | end - 1, flush_tlb); | |
9da0e4d5 | 5660 | } |
efdfe536 XG |
5661 | } |
5662 | ||
71883a62 LT |
5663 | if (flush) |
5664 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, | |
5665 | gfn_end - gfn_start + 1); | |
5666 | ||
efdfe536 XG |
5667 | spin_unlock(&kvm->mmu_lock); |
5668 | } | |
5669 | ||
018aabb5 TY |
5670 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5671 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5672 | { |
018aabb5 | 5673 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5674 | } |
5675 | ||
1c91cad4 KH |
5676 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5677 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5678 | { |
d77aa73c | 5679 | bool flush; |
6aa8b732 | 5680 | |
9d1beefb | 5681 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5682 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5683 | false); | |
9d1beefb | 5684 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5685 | |
5686 | /* | |
5687 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5688 | * which do tlb flush out of mmu-lock should be serialized by | |
5689 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5690 | */ | |
5691 | lockdep_assert_held(&kvm->slots_lock); | |
5692 | ||
5693 | /* | |
5694 | * We can flush all the TLBs out of the mmu lock without TLB | |
5695 | * corruption since we just change the spte from writable to | |
5696 | * readonly so that we only need to care the case of changing | |
5697 | * spte from present to present (changing the spte from present | |
5698 | * to nonpresent will flush all the TLBs immediately), in other | |
5699 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5700 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5701 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5702 | * on PT_WRITABLE_MASK anymore. | |
5703 | */ | |
d91ffee9 | 5704 | if (flush) |
c3134ce2 LT |
5705 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5706 | memslot->npages); | |
6aa8b732 | 5707 | } |
37a7d8b0 | 5708 | |
3ea3b7fa | 5709 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5710 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5711 | { |
5712 | u64 *sptep; | |
5713 | struct rmap_iterator iter; | |
5714 | int need_tlb_flush = 0; | |
ba049e93 | 5715 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5716 | struct kvm_mmu_page *sp; |
5717 | ||
0d536790 | 5718 | restart: |
018aabb5 | 5719 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5720 | sp = page_header(__pa(sptep)); |
5721 | pfn = spte_to_pfn(*sptep); | |
5722 | ||
5723 | /* | |
decf6333 XG |
5724 | * We cannot do huge page mapping for indirect shadow pages, |
5725 | * which are found on the last rmap (level = 1) when not using | |
5726 | * tdp; such shadow pages are synced with the page table in | |
5727 | * the guest, and the guest page table is using 4K page size | |
5728 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5729 | */ |
5730 | if (sp->role.direct && | |
5731 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5732 | PageTransCompoundMap(pfn_to_page(pfn))) { |
e7912386 | 5733 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5734 | |
5735 | if (kvm_available_flush_tlb_with_range()) | |
5736 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5737 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5738 | else | |
5739 | need_tlb_flush = 1; | |
5740 | ||
0d536790 XG |
5741 | goto restart; |
5742 | } | |
3ea3b7fa WL |
5743 | } |
5744 | ||
5745 | return need_tlb_flush; | |
5746 | } | |
5747 | ||
5748 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5749 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5750 | { |
f36f3f28 | 5751 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5752 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5753 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5754 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5755 | spin_unlock(&kvm->mmu_lock); |
5756 | } | |
5757 | ||
f4b4b180 KH |
5758 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5759 | struct kvm_memory_slot *memslot) | |
5760 | { | |
d77aa73c | 5761 | bool flush; |
f4b4b180 KH |
5762 | |
5763 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5764 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5765 | spin_unlock(&kvm->mmu_lock); |
5766 | ||
5767 | lockdep_assert_held(&kvm->slots_lock); | |
5768 | ||
5769 | /* | |
5770 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5771 | * function is only used for dirty logging, in which case flushing TLB | |
5772 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5773 | * dirty_bitmap. | |
5774 | */ | |
5775 | if (flush) | |
c3134ce2 LT |
5776 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5777 | memslot->npages); | |
f4b4b180 KH |
5778 | } |
5779 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5780 | ||
5781 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5782 | struct kvm_memory_slot *memslot) | |
5783 | { | |
d77aa73c | 5784 | bool flush; |
f4b4b180 KH |
5785 | |
5786 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5787 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5788 | false); | |
f4b4b180 KH |
5789 | spin_unlock(&kvm->mmu_lock); |
5790 | ||
5791 | /* see kvm_mmu_slot_remove_write_access */ | |
5792 | lockdep_assert_held(&kvm->slots_lock); | |
5793 | ||
5794 | if (flush) | |
c3134ce2 LT |
5795 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5796 | memslot->npages); | |
f4b4b180 KH |
5797 | } |
5798 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5799 | ||
5800 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5801 | struct kvm_memory_slot *memslot) | |
5802 | { | |
d77aa73c | 5803 | bool flush; |
f4b4b180 KH |
5804 | |
5805 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5806 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5807 | spin_unlock(&kvm->mmu_lock); |
5808 | ||
5809 | lockdep_assert_held(&kvm->slots_lock); | |
5810 | ||
5811 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5812 | if (flush) | |
c3134ce2 LT |
5813 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5814 | memslot->npages); | |
f4b4b180 KH |
5815 | } |
5816 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5817 | ||
e7d11c7a | 5818 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5819 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5820 | { | |
5821 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5822 | int batch = 0; |
5304b8d3 XG |
5823 | |
5824 | restart: | |
5825 | list_for_each_entry_safe_reverse(sp, node, | |
5826 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5827 | int ret; |
5828 | ||
5304b8d3 XG |
5829 | /* |
5830 | * No obsolete page exists before new created page since | |
5831 | * active_mmu_pages is the FIFO list. | |
5832 | */ | |
5833 | if (!is_obsolete_sp(kvm, sp)) | |
5834 | break; | |
5835 | ||
5836 | /* | |
5304b8d3 XG |
5837 | * Since we are reversely walking the list and the invalid |
5838 | * list will be moved to the head, skip the invalid page | |
5839 | * can help us to avoid the infinity list walking. | |
5840 | */ | |
5841 | if (sp->role.invalid) | |
5842 | continue; | |
5843 | ||
f34d251d XG |
5844 | /* |
5845 | * Need not flush tlb since we only zap the sp with invalid | |
5846 | * generation number. | |
5847 | */ | |
e7d11c7a | 5848 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5849 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5850 | batch = 0; |
5304b8d3 XG |
5851 | goto restart; |
5852 | } | |
5853 | ||
365c8868 XG |
5854 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5855 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5856 | batch += ret; |
5857 | ||
5858 | if (ret) | |
5304b8d3 XG |
5859 | goto restart; |
5860 | } | |
5861 | ||
f34d251d XG |
5862 | /* |
5863 | * Should flush tlb before free page tables since lockless-walking | |
5864 | * may use the pages. | |
5865 | */ | |
365c8868 | 5866 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5867 | } |
5868 | ||
5869 | /* | |
5870 | * Fast invalidate all shadow pages and use lock-break technique | |
5871 | * to zap obsolete pages. | |
5872 | * | |
5873 | * It's required when memslot is being deleted or VM is being | |
5874 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5875 | * not use any resource of the being-deleted slot or all slots | |
5876 | * after calling the function. | |
5877 | */ | |
5878 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5879 | { | |
5880 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5881 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5882 | kvm->arch.mmu_valid_gen++; |
5883 | ||
f34d251d XG |
5884 | /* |
5885 | * Notify all vcpus to reload its shadow page table | |
5886 | * and flush TLB. Then all vcpus will switch to new | |
5887 | * shadow page table with the new mmu_valid_gen. | |
5888 | * | |
5889 | * Note: we should do this under the protection of | |
5890 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5891 | * but miss tlb flush. | |
5892 | */ | |
5893 | kvm_reload_remote_mmus(kvm); | |
5894 | ||
5304b8d3 XG |
5895 | kvm_zap_obsolete_pages(kvm); |
5896 | spin_unlock(&kvm->mmu_lock); | |
5897 | } | |
5898 | ||
365c8868 XG |
5899 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5900 | { | |
5901 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5902 | } | |
5903 | ||
54bf36aa | 5904 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5905 | { |
5906 | /* | |
5907 | * The very rare case: if the generation-number is round, | |
5908 | * zap all shadow pages. | |
f8f55942 | 5909 | */ |
54bf36aa | 5910 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5911 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5912 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5913 | } |
f8f55942 XG |
5914 | } |
5915 | ||
70534a73 DC |
5916 | static unsigned long |
5917 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5918 | { |
5919 | struct kvm *kvm; | |
1495f230 | 5920 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5921 | unsigned long freed = 0; |
3ee16c81 | 5922 | |
2f303b74 | 5923 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5924 | |
5925 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5926 | int idx; |
d98ba053 | 5927 | LIST_HEAD(invalid_list); |
3ee16c81 | 5928 | |
35f2d16b TY |
5929 | /* |
5930 | * Never scan more than sc->nr_to_scan VM instances. | |
5931 | * Will not hit this condition practically since we do not try | |
5932 | * to shrink more than one VM and it is very unlikely to see | |
5933 | * !n_used_mmu_pages so many times. | |
5934 | */ | |
5935 | if (!nr_to_scan--) | |
5936 | break; | |
19526396 GN |
5937 | /* |
5938 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5939 | * here. We may skip a VM instance errorneosly, but we do not | |
5940 | * want to shrink a VM that only started to populate its MMU | |
5941 | * anyway. | |
5942 | */ | |
365c8868 XG |
5943 | if (!kvm->arch.n_used_mmu_pages && |
5944 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5945 | continue; |
19526396 | 5946 | |
f656ce01 | 5947 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5948 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5949 | |
365c8868 XG |
5950 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5951 | kvm_mmu_commit_zap_page(kvm, | |
5952 | &kvm->arch.zapped_obsolete_pages); | |
5953 | goto unlock; | |
5954 | } | |
5955 | ||
70534a73 DC |
5956 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5957 | freed++; | |
d98ba053 | 5958 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5959 | |
365c8868 | 5960 | unlock: |
3ee16c81 | 5961 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5962 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5963 | |
70534a73 DC |
5964 | /* |
5965 | * unfair on small ones | |
5966 | * per-vm shrinkers cry out | |
5967 | * sadness comes quickly | |
5968 | */ | |
19526396 GN |
5969 | list_move_tail(&kvm->vm_list, &vm_list); |
5970 | break; | |
3ee16c81 | 5971 | } |
3ee16c81 | 5972 | |
2f303b74 | 5973 | spin_unlock(&kvm_lock); |
70534a73 | 5974 | return freed; |
70534a73 DC |
5975 | } |
5976 | ||
5977 | static unsigned long | |
5978 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5979 | { | |
45221ab6 | 5980 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5981 | } |
5982 | ||
5983 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5984 | .count_objects = mmu_shrink_count, |
5985 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5986 | .seeks = DEFAULT_SEEKS * 10, |
5987 | }; | |
5988 | ||
2ddfd20e | 5989 | static void mmu_destroy_caches(void) |
b5a33a75 | 5990 | { |
c1bd743e TH |
5991 | kmem_cache_destroy(pte_list_desc_cache); |
5992 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5993 | } |
5994 | ||
5995 | int kvm_mmu_module_init(void) | |
5996 | { | |
ab271bd4 AB |
5997 | int ret = -ENOMEM; |
5998 | ||
36d9594d VK |
5999 | /* |
6000 | * MMU roles use union aliasing which is, generally speaking, an | |
6001 | * undefined behavior. However, we supposedly know how compilers behave | |
6002 | * and the current status quo is unlikely to change. Guardians below are | |
6003 | * supposed to let us know if the assumption becomes false. | |
6004 | */ | |
6005 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6006 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6007 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6008 | ||
28a1f3ac | 6009 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6010 | |
53c07b18 XG |
6011 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6012 | sizeof(struct pte_list_desc), | |
46bea48a | 6013 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6014 | if (!pte_list_desc_cache) |
ab271bd4 | 6015 | goto out; |
b5a33a75 | 6016 | |
d3d25b04 AK |
6017 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6018 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6019 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6020 | if (!mmu_page_header_cache) |
ab271bd4 | 6021 | goto out; |
d3d25b04 | 6022 | |
908c7f19 | 6023 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6024 | goto out; |
45bf21a8 | 6025 | |
ab271bd4 AB |
6026 | ret = register_shrinker(&mmu_shrinker); |
6027 | if (ret) | |
6028 | goto out; | |
3ee16c81 | 6029 | |
b5a33a75 AK |
6030 | return 0; |
6031 | ||
ab271bd4 | 6032 | out: |
3ee16c81 | 6033 | mmu_destroy_caches(); |
ab271bd4 | 6034 | return ret; |
b5a33a75 AK |
6035 | } |
6036 | ||
3ad82a7e | 6037 | /* |
39337ad1 | 6038 | * Calculate mmu pages needed for kvm. |
3ad82a7e ZX |
6039 | */ |
6040 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
6041 | { | |
3ad82a7e ZX |
6042 | unsigned int nr_mmu_pages; |
6043 | unsigned int nr_pages = 0; | |
bc6678a3 | 6044 | struct kvm_memslots *slots; |
be6ba0f0 | 6045 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6046 | int i; |
3ad82a7e | 6047 | |
9da0e4d5 PB |
6048 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6049 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6050 | |
9da0e4d5 PB |
6051 | kvm_for_each_memslot(memslot, slots) |
6052 | nr_pages += memslot->npages; | |
6053 | } | |
3ad82a7e ZX |
6054 | |
6055 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
6056 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 6057 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6058 | |
6059 | return nr_mmu_pages; | |
6060 | } | |
6061 | ||
c42fffe3 XG |
6062 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6063 | { | |
95f93af4 | 6064 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
6065 | free_mmu_pages(vcpu); |
6066 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
6067 | } |
6068 | ||
b034cf01 XG |
6069 | void kvm_mmu_module_exit(void) |
6070 | { | |
6071 | mmu_destroy_caches(); | |
6072 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6073 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6074 | mmu_audit_disable(); |
6075 | } |