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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d AK |
44 | #include <asm/page.h> |
45 | #include <asm/cmpxchg.h> | |
4e542370 | 46 | #include <asm/io.h> |
13673a90 | 47 | #include <asm/vmx.h> |
3d0c27ad | 48 | #include <asm/kvm_page_track.h> |
1261bfa3 | 49 | #include "trace.h" |
6aa8b732 | 50 | |
18552672 JR |
51 | /* |
52 | * When setting this variable to true it enables Two-Dimensional-Paging | |
53 | * where the hardware walks 2 page tables: | |
54 | * 1. the guest-virtual to guest-physical | |
55 | * 2. while doing 1. it walks guest-physical to host-physical | |
56 | * If the hardware supports that we don't need to do shadow paging. | |
57 | */ | |
2f333bcb | 58 | bool tdp_enabled = false; |
18552672 | 59 | |
8b1fe17c XG |
60 | enum { |
61 | AUDIT_PRE_PAGE_FAULT, | |
62 | AUDIT_POST_PAGE_FAULT, | |
63 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
64 | AUDIT_POST_PTE_WRITE, |
65 | AUDIT_PRE_SYNC, | |
66 | AUDIT_POST_SYNC | |
8b1fe17c | 67 | }; |
37a7d8b0 | 68 | |
8b1fe17c | 69 | #undef MMU_DEBUG |
37a7d8b0 AK |
70 | |
71 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
72 | static bool dbg = 0; |
73 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
74 | |
75 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
76 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 77 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 78 | #else |
37a7d8b0 AK |
79 | #define pgprintk(x...) do { } while (0) |
80 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 81 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 82 | #endif |
6aa8b732 | 83 | |
957ed9ef XG |
84 | #define PTE_PREFETCH_NUM 8 |
85 | ||
00763e41 | 86 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
87 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
88 | ||
6aa8b732 AK |
89 | #define PT64_LEVEL_BITS 9 |
90 | ||
91 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 92 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 93 | |
6aa8b732 AK |
94 | #define PT64_INDEX(address, level)\ |
95 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
96 | ||
97 | ||
98 | #define PT32_LEVEL_BITS 10 | |
99 | ||
100 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 101 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 102 | |
e04da980 JR |
103 | #define PT32_LVL_OFFSET_MASK(level) \ |
104 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
105 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
106 | |
107 | #define PT32_INDEX(address, level)\ | |
108 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
109 | ||
110 | ||
d0ec49d4 | 111 | #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))) |
6aa8b732 AK |
112 | #define PT64_DIR_BASE_ADDR_MASK \ |
113 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
114 | #define PT64_LVL_ADDR_MASK(level) \ |
115 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT64_LEVEL_BITS))) - 1)) | |
117 | #define PT64_LVL_OFFSET_MASK(level) \ | |
118 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
119 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
120 | |
121 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
122 | #define PT32_DIR_BASE_ADDR_MASK \ | |
123 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
124 | #define PT32_LVL_ADDR_MASK(level) \ |
125 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 127 | |
53166229 | 128 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 129 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 130 | |
fe135d2c AK |
131 | #define ACC_EXEC_MASK 1 |
132 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
133 | #define ACC_USER_MASK PT_USER_MASK | |
134 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
135 | ||
f160c7b7 JS |
136 | /* The mask for the R/X bits in EPT PTEs */ |
137 | #define PT64_EPT_READABLE_MASK 0x1ull | |
138 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
139 | ||
90bb6fc5 AK |
140 | #include <trace/events/kvm.h> |
141 | ||
07420171 AK |
142 | #define CREATE_TRACE_POINTS |
143 | #include "mmutrace.h" | |
144 | ||
49fde340 XG |
145 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
146 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 147 | |
135f8c2b AK |
148 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
149 | ||
220f773a TY |
150 | /* make pte_list_desc fit well in cache line */ |
151 | #define PTE_LIST_EXT 3 | |
152 | ||
9b8ebbdb PB |
153 | /* |
154 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
155 | * RET_PF_RETRY: let CPU fault again on the address. | |
156 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
157 | * | |
158 | * For handle_mmio_page_fault only: | |
159 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
160 | */ | |
161 | enum { | |
162 | RET_PF_RETRY = 0, | |
163 | RET_PF_EMULATE = 1, | |
164 | RET_PF_INVALID = 2, | |
165 | }; | |
166 | ||
53c07b18 XG |
167 | struct pte_list_desc { |
168 | u64 *sptes[PTE_LIST_EXT]; | |
169 | struct pte_list_desc *more; | |
cd4a4e53 AK |
170 | }; |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
2d11123a | 175 | u64 *sptep; |
dd3bfd59 | 176 | int level; |
2d11123a AK |
177 | unsigned index; |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
c2a2ac2b XG |
185 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
186 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
187 | shadow_walk_okay(&(_walker)) && \ | |
188 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
189 | __shadow_walk_next(&(_walker), spte)) | |
190 | ||
53c07b18 | 191 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 192 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 193 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 194 | |
7b52345e SY |
195 | static u64 __read_mostly shadow_nx_mask; |
196 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
197 | static u64 __read_mostly shadow_user_mask; | |
198 | static u64 __read_mostly shadow_accessed_mask; | |
199 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 200 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 201 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 202 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 203 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 204 | |
f160c7b7 | 205 | /* |
ac8d57e5 PF |
206 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
207 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
208 | * tracking. | |
f160c7b7 JS |
209 | */ |
210 | static u64 __read_mostly shadow_acc_track_mask; | |
211 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
212 | ||
213 | /* | |
214 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
215 | * as not-present for access tracking purposes. We do not save the W bit as the | |
216 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
217 | * restored only when a write is attempted to the page. | |
218 | */ | |
219 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
220 | PT64_EPT_EXECUTABLE_MASK; | |
221 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
222 | ||
ce88decf | 223 | static void mmu_spte_set(u64 *sptep, u64 spte); |
e676505a | 224 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf | 225 | |
dcdca5fe | 226 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 227 | { |
dcdca5fe PF |
228 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
229 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 230 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
231 | } |
232 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
233 | ||
ac8d57e5 PF |
234 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
235 | { | |
236 | return sp->role.ad_disabled; | |
237 | } | |
238 | ||
239 | static inline bool spte_ad_enabled(u64 spte) | |
240 | { | |
241 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
242 | return !(spte & shadow_acc_track_value); | |
243 | } | |
244 | ||
245 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
246 | { | |
247 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
248 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
249 | } | |
250 | ||
251 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
252 | { | |
253 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
254 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
255 | } | |
256 | ||
f160c7b7 JS |
257 | static inline bool is_access_track_spte(u64 spte) |
258 | { | |
ac8d57e5 | 259 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
260 | } |
261 | ||
f2fd125d | 262 | /* |
ee3d1570 DM |
263 | * the low bit of the generation number is always presumed to be zero. |
264 | * This disables mmio caching during memslot updates. The concept is | |
265 | * similar to a seqcount but instead of retrying the access we just punt | |
266 | * and ignore the cache. | |
267 | * | |
268 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
269 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 270 | */ |
ee3d1570 | 271 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
272 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
273 | ||
ee3d1570 DM |
274 | #define MMIO_GEN_SHIFT 20 |
275 | #define MMIO_GEN_LOW_SHIFT 10 | |
276 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 277 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
278 | |
279 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
280 | { | |
281 | u64 mask; | |
282 | ||
842bb26a | 283 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
284 | |
285 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
286 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
287 | return mask; | |
288 | } | |
289 | ||
290 | static unsigned int get_mmio_spte_generation(u64 spte) | |
291 | { | |
292 | unsigned int gen; | |
293 | ||
294 | spte &= ~shadow_mmio_mask; | |
295 | ||
296 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
297 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
298 | return gen; | |
299 | } | |
300 | ||
54bf36aa | 301 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 302 | { |
54bf36aa | 303 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
304 | } |
305 | ||
54bf36aa | 306 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 307 | unsigned access) |
ce88decf | 308 | { |
54bf36aa | 309 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 310 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 311 | |
ce88decf | 312 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
dcdca5fe | 313 | mask |= shadow_mmio_value | access | gfn << PAGE_SHIFT; |
f2fd125d | 314 | |
f8f55942 | 315 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 316 | mmu_spte_set(sptep, mask); |
ce88decf XG |
317 | } |
318 | ||
319 | static bool is_mmio_spte(u64 spte) | |
320 | { | |
dcdca5fe | 321 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
322 | } |
323 | ||
324 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
325 | { | |
842bb26a | 326 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 327 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
328 | } |
329 | ||
330 | static unsigned get_mmio_spte_access(u64 spte) | |
331 | { | |
842bb26a | 332 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 333 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
334 | } |
335 | ||
54bf36aa | 336 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 337 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
338 | { |
339 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 340 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
341 | return true; |
342 | } | |
343 | ||
344 | return false; | |
345 | } | |
c7addb90 | 346 | |
54bf36aa | 347 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 348 | { |
089504c0 XG |
349 | unsigned int kvm_gen, spte_gen; |
350 | ||
54bf36aa | 351 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
352 | spte_gen = get_mmio_spte_generation(spte); |
353 | ||
354 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
355 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
356 | } |
357 | ||
ce00053b PF |
358 | /* |
359 | * Sets the shadow PTE masks used by the MMU. | |
360 | * | |
361 | * Assumptions: | |
362 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
363 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
364 | */ | |
7b52345e | 365 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 366 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 367 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 368 | { |
ce00053b PF |
369 | BUG_ON(!dirty_mask != !accessed_mask); |
370 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 371 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 372 | |
7b52345e SY |
373 | shadow_user_mask = user_mask; |
374 | shadow_accessed_mask = accessed_mask; | |
375 | shadow_dirty_mask = dirty_mask; | |
376 | shadow_nx_mask = nx_mask; | |
377 | shadow_x_mask = x_mask; | |
ffb128c8 | 378 | shadow_present_mask = p_mask; |
f160c7b7 | 379 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 380 | shadow_me_mask = me_mask; |
7b52345e SY |
381 | } |
382 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
383 | ||
f160c7b7 JS |
384 | void kvm_mmu_clear_all_pte_masks(void) |
385 | { | |
386 | shadow_user_mask = 0; | |
387 | shadow_accessed_mask = 0; | |
388 | shadow_dirty_mask = 0; | |
389 | shadow_nx_mask = 0; | |
390 | shadow_x_mask = 0; | |
391 | shadow_mmio_mask = 0; | |
392 | shadow_present_mask = 0; | |
393 | shadow_acc_track_mask = 0; | |
394 | } | |
395 | ||
6aa8b732 AK |
396 | static int is_cpuid_PSE36(void) |
397 | { | |
398 | return 1; | |
399 | } | |
400 | ||
73b1087e AK |
401 | static int is_nx(struct kvm_vcpu *vcpu) |
402 | { | |
f6801dff | 403 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
404 | } |
405 | ||
c7addb90 AK |
406 | static int is_shadow_present_pte(u64 pte) |
407 | { | |
f160c7b7 | 408 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
409 | } |
410 | ||
05da4558 MT |
411 | static int is_large_pte(u64 pte) |
412 | { | |
413 | return pte & PT_PAGE_SIZE_MASK; | |
414 | } | |
415 | ||
776e6633 MT |
416 | static int is_last_spte(u64 pte, int level) |
417 | { | |
418 | if (level == PT_PAGE_TABLE_LEVEL) | |
419 | return 1; | |
852e3c19 | 420 | if (is_large_pte(pte)) |
776e6633 MT |
421 | return 1; |
422 | return 0; | |
423 | } | |
424 | ||
d3e328f2 JS |
425 | static bool is_executable_pte(u64 spte) |
426 | { | |
427 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
428 | } | |
429 | ||
ba049e93 | 430 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 431 | { |
35149e21 | 432 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
433 | } |
434 | ||
da928521 AK |
435 | static gfn_t pse36_gfn_delta(u32 gpte) |
436 | { | |
437 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
438 | ||
439 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
440 | } | |
441 | ||
603e0651 | 442 | #ifdef CONFIG_X86_64 |
d555c333 | 443 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 444 | { |
b19ee2ff | 445 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
446 | } |
447 | ||
603e0651 | 448 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 449 | { |
b19ee2ff | 450 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
451 | } |
452 | ||
453 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
454 | { | |
455 | return xchg(sptep, spte); | |
456 | } | |
c2a2ac2b XG |
457 | |
458 | static u64 __get_spte_lockless(u64 *sptep) | |
459 | { | |
6aa7de05 | 460 | return READ_ONCE(*sptep); |
c2a2ac2b | 461 | } |
a9221dd5 | 462 | #else |
603e0651 XG |
463 | union split_spte { |
464 | struct { | |
465 | u32 spte_low; | |
466 | u32 spte_high; | |
467 | }; | |
468 | u64 spte; | |
469 | }; | |
a9221dd5 | 470 | |
c2a2ac2b XG |
471 | static void count_spte_clear(u64 *sptep, u64 spte) |
472 | { | |
473 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
474 | ||
475 | if (is_shadow_present_pte(spte)) | |
476 | return; | |
477 | ||
478 | /* Ensure the spte is completely set before we increase the count */ | |
479 | smp_wmb(); | |
480 | sp->clear_spte_count++; | |
481 | } | |
482 | ||
603e0651 XG |
483 | static void __set_spte(u64 *sptep, u64 spte) |
484 | { | |
485 | union split_spte *ssptep, sspte; | |
a9221dd5 | 486 | |
603e0651 XG |
487 | ssptep = (union split_spte *)sptep; |
488 | sspte = (union split_spte)spte; | |
489 | ||
490 | ssptep->spte_high = sspte.spte_high; | |
491 | ||
492 | /* | |
493 | * If we map the spte from nonpresent to present, We should store | |
494 | * the high bits firstly, then set present bit, so cpu can not | |
495 | * fetch this spte while we are setting the spte. | |
496 | */ | |
497 | smp_wmb(); | |
498 | ||
b19ee2ff | 499 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
500 | } |
501 | ||
603e0651 XG |
502 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
503 | { | |
504 | union split_spte *ssptep, sspte; | |
505 | ||
506 | ssptep = (union split_spte *)sptep; | |
507 | sspte = (union split_spte)spte; | |
508 | ||
b19ee2ff | 509 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
510 | |
511 | /* | |
512 | * If we map the spte from present to nonpresent, we should clear | |
513 | * present bit firstly to avoid vcpu fetch the old high bits. | |
514 | */ | |
515 | smp_wmb(); | |
516 | ||
517 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 518 | count_spte_clear(sptep, spte); |
603e0651 XG |
519 | } |
520 | ||
521 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
522 | { | |
523 | union split_spte *ssptep, sspte, orig; | |
524 | ||
525 | ssptep = (union split_spte *)sptep; | |
526 | sspte = (union split_spte)spte; | |
527 | ||
528 | /* xchg acts as a barrier before the setting of the high bits */ | |
529 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
530 | orig.spte_high = ssptep->spte_high; |
531 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 532 | count_spte_clear(sptep, spte); |
603e0651 XG |
533 | |
534 | return orig.spte; | |
535 | } | |
c2a2ac2b XG |
536 | |
537 | /* | |
538 | * The idea using the light way get the spte on x86_32 guest is from | |
539 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
540 | * |
541 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
542 | * coalesces them and we are running out of the MMU lock. Therefore | |
543 | * we need to protect against in-progress updates of the spte. | |
544 | * | |
545 | * Reading the spte while an update is in progress may get the old value | |
546 | * for the high part of the spte. The race is fine for a present->non-present | |
547 | * change (because the high part of the spte is ignored for non-present spte), | |
548 | * but for a present->present change we must reread the spte. | |
549 | * | |
550 | * All such changes are done in two steps (present->non-present and | |
551 | * non-present->present), hence it is enough to count the number of | |
552 | * present->non-present updates: if it changed while reading the spte, | |
553 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
554 | */ |
555 | static u64 __get_spte_lockless(u64 *sptep) | |
556 | { | |
557 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
558 | union split_spte spte, *orig = (union split_spte *)sptep; | |
559 | int count; | |
560 | ||
561 | retry: | |
562 | count = sp->clear_spte_count; | |
563 | smp_rmb(); | |
564 | ||
565 | spte.spte_low = orig->spte_low; | |
566 | smp_rmb(); | |
567 | ||
568 | spte.spte_high = orig->spte_high; | |
569 | smp_rmb(); | |
570 | ||
571 | if (unlikely(spte.spte_low != orig->spte_low || | |
572 | count != sp->clear_spte_count)) | |
573 | goto retry; | |
574 | ||
575 | return spte.spte; | |
576 | } | |
603e0651 XG |
577 | #endif |
578 | ||
ea4114bc | 579 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 580 | { |
feb3eb70 GN |
581 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
582 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
583 | } |
584 | ||
8672b721 XG |
585 | static bool spte_has_volatile_bits(u64 spte) |
586 | { | |
f160c7b7 JS |
587 | if (!is_shadow_present_pte(spte)) |
588 | return false; | |
589 | ||
c7ba5b48 | 590 | /* |
6a6256f9 | 591 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
592 | * out of mmu-lock, it can ensure dirty bit is not lost, |
593 | * also, it can help us to get a stable is_writable_pte() | |
594 | * to ensure tlb flush is not missed. | |
595 | */ | |
f160c7b7 JS |
596 | if (spte_can_locklessly_be_made_writable(spte) || |
597 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
598 | return true; |
599 | ||
ac8d57e5 | 600 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
601 | if ((spte & shadow_accessed_mask) == 0 || |
602 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
603 | return true; | |
604 | } | |
8672b721 | 605 | |
f160c7b7 | 606 | return false; |
8672b721 XG |
607 | } |
608 | ||
83ef6c81 | 609 | static bool is_accessed_spte(u64 spte) |
4132779b | 610 | { |
ac8d57e5 PF |
611 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
612 | ||
613 | return accessed_mask ? spte & accessed_mask | |
614 | : !is_access_track_spte(spte); | |
4132779b XG |
615 | } |
616 | ||
83ef6c81 | 617 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 618 | { |
ac8d57e5 PF |
619 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
620 | ||
621 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
622 | } |
623 | ||
1df9f2dc XG |
624 | /* Rules for using mmu_spte_set: |
625 | * Set the sptep from nonpresent to present. | |
626 | * Note: the sptep being assigned *must* be either not present | |
627 | * or in a state where the hardware will not attempt to update | |
628 | * the spte. | |
629 | */ | |
630 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
631 | { | |
632 | WARN_ON(is_shadow_present_pte(*sptep)); | |
633 | __set_spte(sptep, new_spte); | |
634 | } | |
635 | ||
f39a058d JS |
636 | /* |
637 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
638 | * accessed/dirty status. | |
1df9f2dc | 639 | */ |
f39a058d | 640 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 641 | { |
c7ba5b48 | 642 | u64 old_spte = *sptep; |
4132779b | 643 | |
afd28fe1 | 644 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 645 | |
6e7d0354 XG |
646 | if (!is_shadow_present_pte(old_spte)) { |
647 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 648 | return old_spte; |
6e7d0354 | 649 | } |
4132779b | 650 | |
c7ba5b48 | 651 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 652 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 653 | else |
603e0651 | 654 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 655 | |
83ef6c81 JS |
656 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
657 | ||
f39a058d JS |
658 | return old_spte; |
659 | } | |
660 | ||
661 | /* Rules for using mmu_spte_update: | |
662 | * Update the state bits, it means the mapped pfn is not changed. | |
663 | * | |
664 | * Whenever we overwrite a writable spte with a read-only one we | |
665 | * should flush remote TLBs. Otherwise rmap_write_protect | |
666 | * will find a read-only spte, even though the writable spte | |
667 | * might be cached on a CPU's TLB, the return value indicates this | |
668 | * case. | |
669 | * | |
670 | * Returns true if the TLB needs to be flushed | |
671 | */ | |
672 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
673 | { | |
674 | bool flush = false; | |
675 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
676 | ||
677 | if (!is_shadow_present_pte(old_spte)) | |
678 | return false; | |
679 | ||
c7ba5b48 XG |
680 | /* |
681 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 682 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
683 | * spte_has_volatile_bits(). |
684 | */ | |
ea4114bc | 685 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 686 | !is_writable_pte(new_spte)) |
83ef6c81 | 687 | flush = true; |
4132779b | 688 | |
7e71a59b | 689 | /* |
83ef6c81 | 690 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
691 | * to guarantee consistency between TLB and page tables. |
692 | */ | |
7e71a59b | 693 | |
83ef6c81 JS |
694 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
695 | flush = true; | |
4132779b | 696 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
697 | } |
698 | ||
699 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
700 | flush = true; | |
4132779b | 701 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 702 | } |
6e7d0354 | 703 | |
83ef6c81 | 704 | return flush; |
b79b93f9 AK |
705 | } |
706 | ||
1df9f2dc XG |
707 | /* |
708 | * Rules for using mmu_spte_clear_track_bits: | |
709 | * It sets the sptep from present to nonpresent, and track the | |
710 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 711 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
712 | */ |
713 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
714 | { | |
ba049e93 | 715 | kvm_pfn_t pfn; |
1df9f2dc XG |
716 | u64 old_spte = *sptep; |
717 | ||
718 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 719 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 720 | else |
603e0651 | 721 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 722 | |
afd28fe1 | 723 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
724 | return 0; |
725 | ||
726 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
727 | |
728 | /* | |
729 | * KVM does not hold the refcount of the page used by | |
730 | * kvm mmu, before reclaiming the page, we should | |
731 | * unmap it from mmu first. | |
732 | */ | |
bf4bea8e | 733 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 734 | |
83ef6c81 | 735 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 736 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
737 | |
738 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 739 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 740 | |
1df9f2dc XG |
741 | return 1; |
742 | } | |
743 | ||
744 | /* | |
745 | * Rules for using mmu_spte_clear_no_track: | |
746 | * Directly clear spte without caring the state bits of sptep, | |
747 | * it is used to set the upper level spte. | |
748 | */ | |
749 | static void mmu_spte_clear_no_track(u64 *sptep) | |
750 | { | |
603e0651 | 751 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
752 | } |
753 | ||
c2a2ac2b XG |
754 | static u64 mmu_spte_get_lockless(u64 *sptep) |
755 | { | |
756 | return __get_spte_lockless(sptep); | |
757 | } | |
758 | ||
f160c7b7 JS |
759 | static u64 mark_spte_for_access_track(u64 spte) |
760 | { | |
ac8d57e5 | 761 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
762 | return spte & ~shadow_accessed_mask; |
763 | ||
ac8d57e5 | 764 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
765 | return spte; |
766 | ||
767 | /* | |
20d65236 JS |
768 | * Making an Access Tracking PTE will result in removal of write access |
769 | * from the PTE. So, verify that we will be able to restore the write | |
770 | * access in the fast page fault path later on. | |
f160c7b7 JS |
771 | */ |
772 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
773 | !spte_can_locklessly_be_made_writable(spte), | |
774 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
775 | ||
776 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
777 | shadow_acc_track_saved_bits_shift), | |
778 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
779 | ||
780 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
781 | shadow_acc_track_saved_bits_shift; | |
782 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
783 | |
784 | return spte; | |
785 | } | |
786 | ||
d3e328f2 JS |
787 | /* Restore an acc-track PTE back to a regular PTE */ |
788 | static u64 restore_acc_track_spte(u64 spte) | |
789 | { | |
790 | u64 new_spte = spte; | |
791 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
792 | & shadow_acc_track_saved_bits_mask; | |
793 | ||
ac8d57e5 | 794 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
795 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
796 | ||
797 | new_spte &= ~shadow_acc_track_mask; | |
798 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
799 | shadow_acc_track_saved_bits_shift); | |
800 | new_spte |= saved_bits; | |
801 | ||
802 | return new_spte; | |
803 | } | |
804 | ||
f160c7b7 JS |
805 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
806 | static bool mmu_spte_age(u64 *sptep) | |
807 | { | |
808 | u64 spte = mmu_spte_get_lockless(sptep); | |
809 | ||
810 | if (!is_accessed_spte(spte)) | |
811 | return false; | |
812 | ||
ac8d57e5 | 813 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
814 | clear_bit((ffs(shadow_accessed_mask) - 1), |
815 | (unsigned long *)sptep); | |
816 | } else { | |
817 | /* | |
818 | * Capture the dirty status of the page, so that it doesn't get | |
819 | * lost when the SPTE is marked for access tracking. | |
820 | */ | |
821 | if (is_writable_pte(spte)) | |
822 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
823 | ||
824 | spte = mark_spte_for_access_track(spte); | |
825 | mmu_spte_update_no_track(sptep, spte); | |
826 | } | |
827 | ||
828 | return true; | |
829 | } | |
830 | ||
c2a2ac2b XG |
831 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
832 | { | |
c142786c AK |
833 | /* |
834 | * Prevent page table teardown by making any free-er wait during | |
835 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
836 | */ | |
837 | local_irq_disable(); | |
36ca7e0a | 838 | |
c142786c AK |
839 | /* |
840 | * Make sure a following spte read is not reordered ahead of the write | |
841 | * to vcpu->mode. | |
842 | */ | |
36ca7e0a | 843 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
844 | } |
845 | ||
846 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
847 | { | |
c142786c AK |
848 | /* |
849 | * Make sure the write to vcpu->mode is not reordered in front of | |
850 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
851 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
852 | */ | |
36ca7e0a | 853 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 854 | local_irq_enable(); |
c2a2ac2b XG |
855 | } |
856 | ||
e2dec939 | 857 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 858 | struct kmem_cache *base_cache, int min) |
714b93da AK |
859 | { |
860 | void *obj; | |
861 | ||
862 | if (cache->nobjs >= min) | |
e2dec939 | 863 | return 0; |
714b93da | 864 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 865 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 866 | if (!obj) |
e2dec939 | 867 | return -ENOMEM; |
714b93da AK |
868 | cache->objects[cache->nobjs++] = obj; |
869 | } | |
e2dec939 | 870 | return 0; |
714b93da AK |
871 | } |
872 | ||
f759e2b4 XG |
873 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
874 | { | |
875 | return cache->nobjs; | |
876 | } | |
877 | ||
e8ad9a70 XG |
878 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
879 | struct kmem_cache *cache) | |
714b93da AK |
880 | { |
881 | while (mc->nobjs) | |
e8ad9a70 | 882 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
883 | } |
884 | ||
c1158e63 | 885 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 886 | int min) |
c1158e63 | 887 | { |
842f22ed | 888 | void *page; |
c1158e63 AK |
889 | |
890 | if (cache->nobjs >= min) | |
891 | return 0; | |
892 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 893 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
894 | if (!page) |
895 | return -ENOMEM; | |
842f22ed | 896 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
897 | } |
898 | return 0; | |
899 | } | |
900 | ||
901 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
902 | { | |
903 | while (mc->nobjs) | |
c4d198d5 | 904 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
905 | } |
906 | ||
2e3e5882 | 907 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 908 | { |
e2dec939 AK |
909 | int r; |
910 | ||
53c07b18 | 911 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 912 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
913 | if (r) |
914 | goto out; | |
ad312c7c | 915 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
916 | if (r) |
917 | goto out; | |
ad312c7c | 918 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 919 | mmu_page_header_cache, 4); |
e2dec939 AK |
920 | out: |
921 | return r; | |
714b93da AK |
922 | } |
923 | ||
924 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
925 | { | |
53c07b18 XG |
926 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
927 | pte_list_desc_cache); | |
ad312c7c | 928 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
929 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
930 | mmu_page_header_cache); | |
714b93da AK |
931 | } |
932 | ||
80feb89a | 933 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
934 | { |
935 | void *p; | |
936 | ||
937 | BUG_ON(!mc->nobjs); | |
938 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
939 | return p; |
940 | } | |
941 | ||
53c07b18 | 942 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 943 | { |
80feb89a | 944 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
945 | } |
946 | ||
53c07b18 | 947 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 948 | { |
53c07b18 | 949 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
950 | } |
951 | ||
2032a93d LJ |
952 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
953 | { | |
954 | if (!sp->role.direct) | |
955 | return sp->gfns[index]; | |
956 | ||
957 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
958 | } | |
959 | ||
960 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
961 | { | |
962 | if (sp->role.direct) | |
963 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
964 | else | |
965 | sp->gfns[index] = gfn; | |
966 | } | |
967 | ||
05da4558 | 968 | /* |
d4dbf470 TY |
969 | * Return the pointer to the large page information for a given gfn, |
970 | * handling slots that are not large page aligned. | |
05da4558 | 971 | */ |
d4dbf470 TY |
972 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
973 | struct kvm_memory_slot *slot, | |
974 | int level) | |
05da4558 MT |
975 | { |
976 | unsigned long idx; | |
977 | ||
fb03cb6f | 978 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 979 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
980 | } |
981 | ||
547ffaed XG |
982 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
983 | gfn_t gfn, int count) | |
984 | { | |
985 | struct kvm_lpage_info *linfo; | |
986 | int i; | |
987 | ||
988 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
989 | linfo = lpage_info_slot(gfn, slot, i); | |
990 | linfo->disallow_lpage += count; | |
991 | WARN_ON(linfo->disallow_lpage < 0); | |
992 | } | |
993 | } | |
994 | ||
995 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
996 | { | |
997 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
998 | } | |
999 | ||
1000 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1001 | { | |
1002 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1003 | } | |
1004 | ||
3ed1a478 | 1005 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1006 | { |
699023e2 | 1007 | struct kvm_memslots *slots; |
d25797b2 | 1008 | struct kvm_memory_slot *slot; |
3ed1a478 | 1009 | gfn_t gfn; |
05da4558 | 1010 | |
56ca57f9 | 1011 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1012 | gfn = sp->gfn; |
699023e2 PB |
1013 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1014 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1015 | |
1016 | /* the non-leaf shadow pages are keeping readonly. */ | |
1017 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1018 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1019 | KVM_PAGE_TRACK_WRITE); | |
1020 | ||
547ffaed | 1021 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1022 | } |
1023 | ||
3ed1a478 | 1024 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1025 | { |
699023e2 | 1026 | struct kvm_memslots *slots; |
d25797b2 | 1027 | struct kvm_memory_slot *slot; |
3ed1a478 | 1028 | gfn_t gfn; |
05da4558 | 1029 | |
56ca57f9 | 1030 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1031 | gfn = sp->gfn; |
699023e2 PB |
1032 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1033 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1034 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1035 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1036 | KVM_PAGE_TRACK_WRITE); | |
1037 | ||
547ffaed | 1038 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1039 | } |
1040 | ||
92f94f1e XG |
1041 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1042 | struct kvm_memory_slot *slot) | |
05da4558 | 1043 | { |
d4dbf470 | 1044 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1045 | |
1046 | if (slot) { | |
d4dbf470 | 1047 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1048 | return !!linfo->disallow_lpage; |
05da4558 MT |
1049 | } |
1050 | ||
92f94f1e | 1051 | return true; |
05da4558 MT |
1052 | } |
1053 | ||
92f94f1e XG |
1054 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1055 | int level) | |
5225fdf8 TY |
1056 | { |
1057 | struct kvm_memory_slot *slot; | |
1058 | ||
1059 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1060 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1061 | } |
1062 | ||
d25797b2 | 1063 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1064 | { |
8f0b1ab6 | 1065 | unsigned long page_size; |
d25797b2 | 1066 | int i, ret = 0; |
05da4558 | 1067 | |
8f0b1ab6 | 1068 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1069 | |
8a3d08f1 | 1070 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1071 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1072 | ret = i; | |
1073 | else | |
1074 | break; | |
1075 | } | |
1076 | ||
4c2155ce | 1077 | return ret; |
05da4558 MT |
1078 | } |
1079 | ||
d8aacf5d TY |
1080 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1081 | bool no_dirty_log) | |
1082 | { | |
1083 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1084 | return false; | |
1085 | if (no_dirty_log && slot->dirty_bitmap) | |
1086 | return false; | |
1087 | ||
1088 | return true; | |
1089 | } | |
1090 | ||
5d163b1c XG |
1091 | static struct kvm_memory_slot * |
1092 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1093 | bool no_dirty_log) | |
05da4558 MT |
1094 | { |
1095 | struct kvm_memory_slot *slot; | |
5d163b1c | 1096 | |
54bf36aa | 1097 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1098 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1099 | slot = NULL; |
1100 | ||
1101 | return slot; | |
1102 | } | |
1103 | ||
fd136902 TY |
1104 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1105 | bool *force_pt_level) | |
936a5fe6 AA |
1106 | { |
1107 | int host_level, level, max_level; | |
d8aacf5d TY |
1108 | struct kvm_memory_slot *slot; |
1109 | ||
8c85ac1c TY |
1110 | if (unlikely(*force_pt_level)) |
1111 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1112 | |
8c85ac1c TY |
1113 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1114 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1115 | if (unlikely(*force_pt_level)) |
1116 | return PT_PAGE_TABLE_LEVEL; | |
1117 | ||
d25797b2 JR |
1118 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1119 | ||
1120 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1121 | return host_level; | |
1122 | ||
55dd98c3 | 1123 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1124 | |
1125 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1126 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1127 | break; |
d25797b2 JR |
1128 | |
1129 | return level - 1; | |
05da4558 MT |
1130 | } |
1131 | ||
290fc38d | 1132 | /* |
018aabb5 | 1133 | * About rmap_head encoding: |
cd4a4e53 | 1134 | * |
018aabb5 TY |
1135 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1136 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1137 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1138 | */ |
1139 | ||
1140 | /* | |
1141 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1142 | */ |
53c07b18 | 1143 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1144 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1145 | { |
53c07b18 | 1146 | struct pte_list_desc *desc; |
53a27b39 | 1147 | int i, count = 0; |
cd4a4e53 | 1148 | |
018aabb5 | 1149 | if (!rmap_head->val) { |
53c07b18 | 1150 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1151 | rmap_head->val = (unsigned long)spte; |
1152 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1153 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1154 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1155 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1156 | desc->sptes[1] = spte; |
018aabb5 | 1157 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1158 | ++count; |
cd4a4e53 | 1159 | } else { |
53c07b18 | 1160 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1161 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1162 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1163 | desc = desc->more; |
53c07b18 | 1164 | count += PTE_LIST_EXT; |
53a27b39 | 1165 | } |
53c07b18 XG |
1166 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1167 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1168 | desc = desc->more; |
1169 | } | |
d555c333 | 1170 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1171 | ++count; |
d555c333 | 1172 | desc->sptes[i] = spte; |
cd4a4e53 | 1173 | } |
53a27b39 | 1174 | return count; |
cd4a4e53 AK |
1175 | } |
1176 | ||
53c07b18 | 1177 | static void |
018aabb5 TY |
1178 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1179 | struct pte_list_desc *desc, int i, | |
1180 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1181 | { |
1182 | int j; | |
1183 | ||
53c07b18 | 1184 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1185 | ; |
d555c333 AK |
1186 | desc->sptes[i] = desc->sptes[j]; |
1187 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1188 | if (j != 0) |
1189 | return; | |
1190 | if (!prev_desc && !desc->more) | |
018aabb5 | 1191 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1192 | else |
1193 | if (prev_desc) | |
1194 | prev_desc->more = desc->more; | |
1195 | else | |
018aabb5 | 1196 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1197 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1198 | } |
1199 | ||
018aabb5 | 1200 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1201 | { |
53c07b18 XG |
1202 | struct pte_list_desc *desc; |
1203 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1204 | int i; |
1205 | ||
018aabb5 | 1206 | if (!rmap_head->val) { |
53c07b18 | 1207 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1208 | BUG(); |
018aabb5 | 1209 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1210 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1211 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1212 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1213 | BUG(); |
1214 | } | |
018aabb5 | 1215 | rmap_head->val = 0; |
cd4a4e53 | 1216 | } else { |
53c07b18 | 1217 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1218 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1219 | prev_desc = NULL; |
1220 | while (desc) { | |
018aabb5 | 1221 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1222 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1223 | pte_list_desc_remove_entry(rmap_head, |
1224 | desc, i, prev_desc); | |
cd4a4e53 AK |
1225 | return; |
1226 | } | |
018aabb5 | 1227 | } |
cd4a4e53 AK |
1228 | prev_desc = desc; |
1229 | desc = desc->more; | |
1230 | } | |
53c07b18 | 1231 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1232 | BUG(); |
1233 | } | |
1234 | } | |
1235 | ||
018aabb5 TY |
1236 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1237 | struct kvm_memory_slot *slot) | |
53c07b18 | 1238 | { |
77d11309 | 1239 | unsigned long idx; |
53c07b18 | 1240 | |
77d11309 | 1241 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1242 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1243 | } |
1244 | ||
018aabb5 TY |
1245 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1246 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1247 | { |
699023e2 | 1248 | struct kvm_memslots *slots; |
9b9b1492 TY |
1249 | struct kvm_memory_slot *slot; |
1250 | ||
699023e2 PB |
1251 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1252 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1253 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1254 | } |
1255 | ||
f759e2b4 XG |
1256 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1257 | { | |
1258 | struct kvm_mmu_memory_cache *cache; | |
1259 | ||
1260 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1261 | return mmu_memory_cache_free_objects(cache); | |
1262 | } | |
1263 | ||
53c07b18 XG |
1264 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1265 | { | |
1266 | struct kvm_mmu_page *sp; | |
018aabb5 | 1267 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1268 | |
53c07b18 XG |
1269 | sp = page_header(__pa(spte)); |
1270 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1271 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1272 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1273 | } |
1274 | ||
53c07b18 XG |
1275 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1276 | { | |
1277 | struct kvm_mmu_page *sp; | |
1278 | gfn_t gfn; | |
018aabb5 | 1279 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1280 | |
1281 | sp = page_header(__pa(spte)); | |
1282 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1283 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1284 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1285 | } |
1286 | ||
1e3f42f0 TY |
1287 | /* |
1288 | * Used by the following functions to iterate through the sptes linked by a | |
1289 | * rmap. All fields are private and not assumed to be used outside. | |
1290 | */ | |
1291 | struct rmap_iterator { | |
1292 | /* private fields */ | |
1293 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1294 | int pos; /* index of the sptep */ | |
1295 | }; | |
1296 | ||
1297 | /* | |
1298 | * Iteration must be started by this function. This should also be used after | |
1299 | * removing/dropping sptes from the rmap link because in such cases the | |
1300 | * information in the itererator may not be valid. | |
1301 | * | |
1302 | * Returns sptep if found, NULL otherwise. | |
1303 | */ | |
018aabb5 TY |
1304 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1305 | struct rmap_iterator *iter) | |
1e3f42f0 | 1306 | { |
77fbbbd2 TY |
1307 | u64 *sptep; |
1308 | ||
018aabb5 | 1309 | if (!rmap_head->val) |
1e3f42f0 TY |
1310 | return NULL; |
1311 | ||
018aabb5 | 1312 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1313 | iter->desc = NULL; |
77fbbbd2 TY |
1314 | sptep = (u64 *)rmap_head->val; |
1315 | goto out; | |
1e3f42f0 TY |
1316 | } |
1317 | ||
018aabb5 | 1318 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1319 | iter->pos = 0; |
77fbbbd2 TY |
1320 | sptep = iter->desc->sptes[iter->pos]; |
1321 | out: | |
1322 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1323 | return sptep; | |
1e3f42f0 TY |
1324 | } |
1325 | ||
1326 | /* | |
1327 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1328 | * | |
1329 | * Returns sptep if found, NULL otherwise. | |
1330 | */ | |
1331 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1332 | { | |
77fbbbd2 TY |
1333 | u64 *sptep; |
1334 | ||
1e3f42f0 TY |
1335 | if (iter->desc) { |
1336 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1337 | ++iter->pos; |
1338 | sptep = iter->desc->sptes[iter->pos]; | |
1339 | if (sptep) | |
77fbbbd2 | 1340 | goto out; |
1e3f42f0 TY |
1341 | } |
1342 | ||
1343 | iter->desc = iter->desc->more; | |
1344 | ||
1345 | if (iter->desc) { | |
1346 | iter->pos = 0; | |
1347 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1348 | sptep = iter->desc->sptes[iter->pos]; |
1349 | goto out; | |
1e3f42f0 TY |
1350 | } |
1351 | } | |
1352 | ||
1353 | return NULL; | |
77fbbbd2 TY |
1354 | out: |
1355 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1356 | return sptep; | |
1e3f42f0 TY |
1357 | } |
1358 | ||
018aabb5 TY |
1359 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1360 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1361 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1362 | |
c3707958 | 1363 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1364 | { |
1df9f2dc | 1365 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1366 | rmap_remove(kvm, sptep); |
be38d276 AK |
1367 | } |
1368 | ||
8e22f955 XG |
1369 | |
1370 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1371 | { | |
1372 | if (is_large_pte(*sptep)) { | |
1373 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1374 | PT_PAGE_TABLE_LEVEL); | |
1375 | drop_spte(kvm, sptep); | |
1376 | --kvm->stat.lpages; | |
1377 | return true; | |
1378 | } | |
1379 | ||
1380 | return false; | |
1381 | } | |
1382 | ||
1383 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1384 | { | |
1385 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1386 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1387 | } | |
1388 | ||
1389 | /* | |
49fde340 | 1390 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1391 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1392 | * |
b4619660 | 1393 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1394 | * protection: |
1395 | * - for dirty logging, the spte can be set to writable at anytime if | |
1396 | * its dirty bitmap is properly set. | |
1397 | * - for spte protection, the spte can be writable only after unsync-ing | |
1398 | * shadow page. | |
8e22f955 | 1399 | * |
c126d94f | 1400 | * Return true if tlb need be flushed. |
8e22f955 | 1401 | */ |
c4f138b4 | 1402 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1403 | { |
1404 | u64 spte = *sptep; | |
1405 | ||
49fde340 | 1406 | if (!is_writable_pte(spte) && |
ea4114bc | 1407 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1408 | return false; |
1409 | ||
1410 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1411 | ||
49fde340 XG |
1412 | if (pt_protect) |
1413 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1414 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1415 | |
c126d94f | 1416 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1417 | } |
1418 | ||
018aabb5 TY |
1419 | static bool __rmap_write_protect(struct kvm *kvm, |
1420 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1421 | bool pt_protect) |
98348e95 | 1422 | { |
1e3f42f0 TY |
1423 | u64 *sptep; |
1424 | struct rmap_iterator iter; | |
d13bc5b5 | 1425 | bool flush = false; |
374cbac0 | 1426 | |
018aabb5 | 1427 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1428 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1429 | |
d13bc5b5 | 1430 | return flush; |
a0ed4607 TY |
1431 | } |
1432 | ||
c4f138b4 | 1433 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1434 | { |
1435 | u64 spte = *sptep; | |
1436 | ||
1437 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1438 | ||
1439 | spte &= ~shadow_dirty_mask; | |
1440 | ||
1441 | return mmu_spte_update(sptep, spte); | |
1442 | } | |
1443 | ||
ac8d57e5 PF |
1444 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1445 | { | |
1446 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1447 | (unsigned long *)sptep); | |
1448 | if (was_writable) | |
1449 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1450 | ||
1451 | return was_writable; | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1456 | * - D bit on ad-enabled SPTEs, and | |
1457 | * - W bit on ad-disabled SPTEs. | |
1458 | * Returns true iff any D or W bits were cleared. | |
1459 | */ | |
018aabb5 | 1460 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1461 | { |
1462 | u64 *sptep; | |
1463 | struct rmap_iterator iter; | |
1464 | bool flush = false; | |
1465 | ||
018aabb5 | 1466 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1467 | if (spte_ad_enabled(*sptep)) |
1468 | flush |= spte_clear_dirty(sptep); | |
1469 | else | |
1470 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1471 | |
1472 | return flush; | |
1473 | } | |
1474 | ||
c4f138b4 | 1475 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1476 | { |
1477 | u64 spte = *sptep; | |
1478 | ||
1479 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1480 | ||
1481 | spte |= shadow_dirty_mask; | |
1482 | ||
1483 | return mmu_spte_update(sptep, spte); | |
1484 | } | |
1485 | ||
018aabb5 | 1486 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1487 | { |
1488 | u64 *sptep; | |
1489 | struct rmap_iterator iter; | |
1490 | bool flush = false; | |
1491 | ||
018aabb5 | 1492 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1493 | if (spte_ad_enabled(*sptep)) |
1494 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1495 | |
1496 | return flush; | |
1497 | } | |
1498 | ||
5dc99b23 | 1499 | /** |
3b0f1d01 | 1500 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1501 | * @kvm: kvm instance |
1502 | * @slot: slot to protect | |
1503 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1504 | * @mask: indicates which pages we should protect | |
1505 | * | |
1506 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1507 | * logging we do not have any such mappings. | |
1508 | */ | |
3b0f1d01 | 1509 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1510 | struct kvm_memory_slot *slot, |
1511 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1512 | { |
018aabb5 | 1513 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1514 | |
5dc99b23 | 1515 | while (mask) { |
018aabb5 TY |
1516 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1517 | PT_PAGE_TABLE_LEVEL, slot); | |
1518 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1519 | |
5dc99b23 TY |
1520 | /* clear the first set bit */ |
1521 | mask &= mask - 1; | |
1522 | } | |
374cbac0 AK |
1523 | } |
1524 | ||
f4b4b180 | 1525 | /** |
ac8d57e5 PF |
1526 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1527 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1528 | * @kvm: kvm instance |
1529 | * @slot: slot to clear D-bit | |
1530 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1531 | * @mask: indicates which pages we should clear D-bit | |
1532 | * | |
1533 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1534 | */ | |
1535 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1536 | struct kvm_memory_slot *slot, | |
1537 | gfn_t gfn_offset, unsigned long mask) | |
1538 | { | |
018aabb5 | 1539 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1540 | |
1541 | while (mask) { | |
018aabb5 TY |
1542 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1543 | PT_PAGE_TABLE_LEVEL, slot); | |
1544 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1545 | |
1546 | /* clear the first set bit */ | |
1547 | mask &= mask - 1; | |
1548 | } | |
1549 | } | |
1550 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1551 | ||
3b0f1d01 KH |
1552 | /** |
1553 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1554 | * PT level pages. | |
1555 | * | |
1556 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1557 | * enable dirty logging for them. | |
1558 | * | |
1559 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1560 | * logging we do not have any such mappings. | |
1561 | */ | |
1562 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1563 | struct kvm_memory_slot *slot, | |
1564 | gfn_t gfn_offset, unsigned long mask) | |
1565 | { | |
88178fd4 KH |
1566 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1567 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1568 | mask); | |
1569 | else | |
1570 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1571 | } |
1572 | ||
bab4165e BD |
1573 | /** |
1574 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1575 | * @vcpu: Guest mode vcpu | |
1576 | * | |
1577 | * Emulate arch specific page modification logging for the | |
1578 | * nested hypervisor | |
1579 | */ | |
1580 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1581 | { | |
1582 | if (kvm_x86_ops->write_log_dirty) | |
1583 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
aeecee2e XG |
1588 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1589 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1590 | { |
018aabb5 | 1591 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1592 | int i; |
2f84569f | 1593 | bool write_protected = false; |
95d4c16c | 1594 | |
8a3d08f1 | 1595 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1596 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1597 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1598 | } |
1599 | ||
1600 | return write_protected; | |
95d4c16c TY |
1601 | } |
1602 | ||
aeecee2e XG |
1603 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1604 | { | |
1605 | struct kvm_memory_slot *slot; | |
1606 | ||
1607 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1608 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1609 | } | |
1610 | ||
018aabb5 | 1611 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1612 | { |
1e3f42f0 TY |
1613 | u64 *sptep; |
1614 | struct rmap_iterator iter; | |
6a49f85c | 1615 | bool flush = false; |
e930bffe | 1616 | |
018aabb5 | 1617 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1618 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1619 | |
1620 | drop_spte(kvm, sptep); | |
6a49f85c | 1621 | flush = true; |
e930bffe | 1622 | } |
1e3f42f0 | 1623 | |
6a49f85c XG |
1624 | return flush; |
1625 | } | |
1626 | ||
018aabb5 | 1627 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1628 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1629 | unsigned long data) | |
1630 | { | |
018aabb5 | 1631 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1632 | } |
1633 | ||
018aabb5 | 1634 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1635 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1636 | unsigned long data) | |
3da0dd43 | 1637 | { |
1e3f42f0 TY |
1638 | u64 *sptep; |
1639 | struct rmap_iterator iter; | |
3da0dd43 | 1640 | int need_flush = 0; |
1e3f42f0 | 1641 | u64 new_spte; |
3da0dd43 | 1642 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1643 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1644 | |
1645 | WARN_ON(pte_huge(*ptep)); | |
1646 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1647 | |
0d536790 | 1648 | restart: |
018aabb5 | 1649 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1650 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1651 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1652 | |
3da0dd43 | 1653 | need_flush = 1; |
1e3f42f0 | 1654 | |
3da0dd43 | 1655 | if (pte_write(*ptep)) { |
1e3f42f0 | 1656 | drop_spte(kvm, sptep); |
0d536790 | 1657 | goto restart; |
3da0dd43 | 1658 | } else { |
1e3f42f0 | 1659 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1660 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1661 | ||
1662 | new_spte &= ~PT_WRITABLE_MASK; | |
1663 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1664 | |
1665 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1666 | |
1667 | mmu_spte_clear_track_bits(sptep); | |
1668 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1669 | } |
1670 | } | |
1e3f42f0 | 1671 | |
3da0dd43 IE |
1672 | if (need_flush) |
1673 | kvm_flush_remote_tlbs(kvm); | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
6ce1f4e2 XG |
1678 | struct slot_rmap_walk_iterator { |
1679 | /* input fields. */ | |
1680 | struct kvm_memory_slot *slot; | |
1681 | gfn_t start_gfn; | |
1682 | gfn_t end_gfn; | |
1683 | int start_level; | |
1684 | int end_level; | |
1685 | ||
1686 | /* output fields. */ | |
1687 | gfn_t gfn; | |
018aabb5 | 1688 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1689 | int level; |
1690 | ||
1691 | /* private field. */ | |
018aabb5 | 1692 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1693 | }; |
1694 | ||
1695 | static void | |
1696 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1697 | { | |
1698 | iterator->level = level; | |
1699 | iterator->gfn = iterator->start_gfn; | |
1700 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1701 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1702 | iterator->slot); | |
1703 | } | |
1704 | ||
1705 | static void | |
1706 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1707 | struct kvm_memory_slot *slot, int start_level, | |
1708 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1709 | { | |
1710 | iterator->slot = slot; | |
1711 | iterator->start_level = start_level; | |
1712 | iterator->end_level = end_level; | |
1713 | iterator->start_gfn = start_gfn; | |
1714 | iterator->end_gfn = end_gfn; | |
1715 | ||
1716 | rmap_walk_init_level(iterator, iterator->start_level); | |
1717 | } | |
1718 | ||
1719 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1720 | { | |
1721 | return !!iterator->rmap; | |
1722 | } | |
1723 | ||
1724 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1725 | { | |
1726 | if (++iterator->rmap <= iterator->end_rmap) { | |
1727 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1728 | return; | |
1729 | } | |
1730 | ||
1731 | if (++iterator->level > iterator->end_level) { | |
1732 | iterator->rmap = NULL; | |
1733 | return; | |
1734 | } | |
1735 | ||
1736 | rmap_walk_init_level(iterator, iterator->level); | |
1737 | } | |
1738 | ||
1739 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1740 | _start_gfn, _end_gfn, _iter_) \ | |
1741 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1742 | _end_level_, _start_gfn, _end_gfn); \ | |
1743 | slot_rmap_walk_okay(_iter_); \ | |
1744 | slot_rmap_walk_next(_iter_)) | |
1745 | ||
84504ef3 TY |
1746 | static int kvm_handle_hva_range(struct kvm *kvm, |
1747 | unsigned long start, | |
1748 | unsigned long end, | |
1749 | unsigned long data, | |
1750 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1751 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1752 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1753 | gfn_t gfn, |
1754 | int level, | |
84504ef3 | 1755 | unsigned long data)) |
e930bffe | 1756 | { |
bc6678a3 | 1757 | struct kvm_memslots *slots; |
be6ba0f0 | 1758 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1759 | struct slot_rmap_walk_iterator iterator; |
1760 | int ret = 0; | |
9da0e4d5 | 1761 | int i; |
bc6678a3 | 1762 | |
9da0e4d5 PB |
1763 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1764 | slots = __kvm_memslots(kvm, i); | |
1765 | kvm_for_each_memslot(memslot, slots) { | |
1766 | unsigned long hva_start, hva_end; | |
1767 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1768 | |
9da0e4d5 PB |
1769 | hva_start = max(start, memslot->userspace_addr); |
1770 | hva_end = min(end, memslot->userspace_addr + | |
1771 | (memslot->npages << PAGE_SHIFT)); | |
1772 | if (hva_start >= hva_end) | |
1773 | continue; | |
1774 | /* | |
1775 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1776 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1777 | */ | |
1778 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1779 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1780 | ||
1781 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1782 | PT_MAX_HUGEPAGE_LEVEL, | |
1783 | gfn_start, gfn_end - 1, | |
1784 | &iterator) | |
1785 | ret |= handler(kvm, iterator.rmap, memslot, | |
1786 | iterator.gfn, iterator.level, data); | |
1787 | } | |
e930bffe AA |
1788 | } |
1789 | ||
f395302e | 1790 | return ret; |
e930bffe AA |
1791 | } |
1792 | ||
84504ef3 TY |
1793 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1794 | unsigned long data, | |
018aabb5 TY |
1795 | int (*handler)(struct kvm *kvm, |
1796 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1797 | struct kvm_memory_slot *slot, |
8a9522d2 | 1798 | gfn_t gfn, int level, |
84504ef3 TY |
1799 | unsigned long data)) |
1800 | { | |
1801 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1802 | } |
1803 | ||
1804 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1805 | { | |
3da0dd43 IE |
1806 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1807 | } | |
1808 | ||
b3ae2096 TY |
1809 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1810 | { | |
1811 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1812 | } | |
1813 | ||
3da0dd43 IE |
1814 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1815 | { | |
8a8365c5 | 1816 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1817 | } |
1818 | ||
018aabb5 | 1819 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1820 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1821 | unsigned long data) | |
e930bffe | 1822 | { |
1e3f42f0 | 1823 | u64 *sptep; |
79f702a6 | 1824 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1825 | int young = 0; |
1826 | ||
f160c7b7 JS |
1827 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1828 | young |= mmu_spte_age(sptep); | |
0d536790 | 1829 | |
8a9522d2 | 1830 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1831 | return young; |
1832 | } | |
1833 | ||
018aabb5 | 1834 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1835 | struct kvm_memory_slot *slot, gfn_t gfn, |
1836 | int level, unsigned long data) | |
8ee53820 | 1837 | { |
1e3f42f0 TY |
1838 | u64 *sptep; |
1839 | struct rmap_iterator iter; | |
8ee53820 | 1840 | |
83ef6c81 JS |
1841 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1842 | if (is_accessed_spte(*sptep)) | |
1843 | return 1; | |
83ef6c81 | 1844 | return 0; |
8ee53820 AA |
1845 | } |
1846 | ||
53a27b39 MT |
1847 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1848 | ||
852e3c19 | 1849 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1850 | { |
018aabb5 | 1851 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1852 | struct kvm_mmu_page *sp; |
1853 | ||
1854 | sp = page_header(__pa(spte)); | |
53a27b39 | 1855 | |
018aabb5 | 1856 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1857 | |
018aabb5 | 1858 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1859 | kvm_flush_remote_tlbs(vcpu->kvm); |
1860 | } | |
1861 | ||
57128468 | 1862 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1863 | { |
57128468 | 1864 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1865 | } |
1866 | ||
8ee53820 AA |
1867 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1868 | { | |
1869 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1870 | } | |
1871 | ||
d6c69ee9 | 1872 | #ifdef MMU_DEBUG |
47ad8e68 | 1873 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1874 | { |
139bdb2d AK |
1875 | u64 *pos; |
1876 | u64 *end; | |
1877 | ||
47ad8e68 | 1878 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1879 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1880 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1881 | pos, *pos); |
6aa8b732 | 1882 | return 0; |
139bdb2d | 1883 | } |
6aa8b732 AK |
1884 | return 1; |
1885 | } | |
d6c69ee9 | 1886 | #endif |
6aa8b732 | 1887 | |
45221ab6 DH |
1888 | /* |
1889 | * This value is the sum of all of the kvm instances's | |
1890 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1891 | * aggregate version in order to make the slab shrinker | |
1892 | * faster | |
1893 | */ | |
1894 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1895 | { | |
1896 | kvm->arch.n_used_mmu_pages += nr; | |
1897 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1898 | } | |
1899 | ||
834be0d8 | 1900 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1901 | { |
fa4a2c08 | 1902 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1903 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1904 | list_del(&sp->link); |
1905 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1906 | if (!sp->role.direct) |
1907 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1908 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1909 | } |
1910 | ||
cea0f0e7 AK |
1911 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1912 | { | |
114df303 | 1913 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1914 | } |
1915 | ||
714b93da | 1916 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1917 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1918 | { |
cea0f0e7 AK |
1919 | if (!parent_pte) |
1920 | return; | |
cea0f0e7 | 1921 | |
67052b35 | 1922 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1923 | } |
1924 | ||
4db35314 | 1925 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1926 | u64 *parent_pte) |
1927 | { | |
67052b35 | 1928 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1929 | } |
1930 | ||
bcdd9a93 XG |
1931 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1932 | u64 *parent_pte) | |
1933 | { | |
1934 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1935 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1936 | } |
1937 | ||
47005792 | 1938 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1939 | { |
67052b35 | 1940 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1941 | |
80feb89a TY |
1942 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1943 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1944 | if (!direct) |
80feb89a | 1945 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1946 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1947 | |
1948 | /* | |
1949 | * The active_mmu_pages list is the FIFO list, do not move the | |
1950 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1951 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1952 | */ | |
67052b35 | 1953 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1954 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1955 | return sp; | |
ad8cfbe3 MT |
1956 | } |
1957 | ||
67052b35 | 1958 | static void mark_unsync(u64 *spte); |
1047df1f | 1959 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1960 | { |
74c4e63a TY |
1961 | u64 *sptep; |
1962 | struct rmap_iterator iter; | |
1963 | ||
1964 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1965 | mark_unsync(sptep); | |
1966 | } | |
0074ff63 MT |
1967 | } |
1968 | ||
67052b35 | 1969 | static void mark_unsync(u64 *spte) |
0074ff63 | 1970 | { |
67052b35 | 1971 | struct kvm_mmu_page *sp; |
1047df1f | 1972 | unsigned int index; |
0074ff63 | 1973 | |
67052b35 | 1974 | sp = page_header(__pa(spte)); |
1047df1f XG |
1975 | index = spte - sp->spt; |
1976 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1977 | return; |
1047df1f | 1978 | if (sp->unsync_children++) |
0074ff63 | 1979 | return; |
1047df1f | 1980 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1981 | } |
1982 | ||
e8bc217a | 1983 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1984 | struct kvm_mmu_page *sp) |
e8bc217a | 1985 | { |
1f50f1b3 | 1986 | return 0; |
e8bc217a MT |
1987 | } |
1988 | ||
a7052897 MT |
1989 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1990 | { | |
1991 | } | |
1992 | ||
0f53b5b1 XG |
1993 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1994 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1995 | const void *pte) |
0f53b5b1 XG |
1996 | { |
1997 | WARN_ON(1); | |
1998 | } | |
1999 | ||
60c8aec6 MT |
2000 | #define KVM_PAGE_ARRAY_NR 16 |
2001 | ||
2002 | struct kvm_mmu_pages { | |
2003 | struct mmu_page_and_offset { | |
2004 | struct kvm_mmu_page *sp; | |
2005 | unsigned int idx; | |
2006 | } page[KVM_PAGE_ARRAY_NR]; | |
2007 | unsigned int nr; | |
2008 | }; | |
2009 | ||
cded19f3 HE |
2010 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2011 | int idx) | |
4731d4c7 | 2012 | { |
60c8aec6 | 2013 | int i; |
4731d4c7 | 2014 | |
60c8aec6 MT |
2015 | if (sp->unsync) |
2016 | for (i=0; i < pvec->nr; i++) | |
2017 | if (pvec->page[i].sp == sp) | |
2018 | return 0; | |
2019 | ||
2020 | pvec->page[pvec->nr].sp = sp; | |
2021 | pvec->page[pvec->nr].idx = idx; | |
2022 | pvec->nr++; | |
2023 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2024 | } | |
2025 | ||
fd951457 TY |
2026 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2027 | { | |
2028 | --sp->unsync_children; | |
2029 | WARN_ON((int)sp->unsync_children < 0); | |
2030 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2031 | } | |
2032 | ||
60c8aec6 MT |
2033 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2034 | struct kvm_mmu_pages *pvec) | |
2035 | { | |
2036 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2037 | |
37178b8b | 2038 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2039 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2040 | u64 ent = sp->spt[i]; |
2041 | ||
fd951457 TY |
2042 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2043 | clear_unsync_child_bit(sp, i); | |
2044 | continue; | |
2045 | } | |
7a8f1a74 XG |
2046 | |
2047 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2048 | ||
2049 | if (child->unsync_children) { | |
2050 | if (mmu_pages_add(pvec, child, i)) | |
2051 | return -ENOSPC; | |
2052 | ||
2053 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2054 | if (!ret) { |
2055 | clear_unsync_child_bit(sp, i); | |
2056 | continue; | |
2057 | } else if (ret > 0) { | |
7a8f1a74 | 2058 | nr_unsync_leaf += ret; |
fd951457 | 2059 | } else |
7a8f1a74 XG |
2060 | return ret; |
2061 | } else if (child->unsync) { | |
2062 | nr_unsync_leaf++; | |
2063 | if (mmu_pages_add(pvec, child, i)) | |
2064 | return -ENOSPC; | |
2065 | } else | |
fd951457 | 2066 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2067 | } |
2068 | ||
60c8aec6 MT |
2069 | return nr_unsync_leaf; |
2070 | } | |
2071 | ||
e23d3fef XG |
2072 | #define INVALID_INDEX (-1) |
2073 | ||
60c8aec6 MT |
2074 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2075 | struct kvm_mmu_pages *pvec) | |
2076 | { | |
0a47cd85 | 2077 | pvec->nr = 0; |
60c8aec6 MT |
2078 | if (!sp->unsync_children) |
2079 | return 0; | |
2080 | ||
e23d3fef | 2081 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2082 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2083 | } |
2084 | ||
4731d4c7 MT |
2085 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2086 | { | |
2087 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2088 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2089 | sp->unsync = 0; |
2090 | --kvm->stat.mmu_unsync; | |
2091 | } | |
2092 | ||
7775834a XG |
2093 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2094 | struct list_head *invalid_list); | |
2095 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2096 | struct list_head *invalid_list); | |
4731d4c7 | 2097 | |
f34d251d XG |
2098 | /* |
2099 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2100 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2101 | * since it has been deleted from active_mmu_pages but still can be found | |
2102 | * at hast list. | |
2103 | * | |
f3414bc7 | 2104 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2105 | */ |
f3414bc7 | 2106 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2107 | hlist_for_each_entry(_sp, \ |
2108 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2109 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2110 | } else | |
1044b030 TY |
2111 | |
2112 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2113 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2114 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2115 | |
f918b443 | 2116 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2117 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2118 | struct list_head *invalid_list) | |
4731d4c7 | 2119 | { |
5b7e0102 | 2120 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 2121 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2122 | return false; |
4731d4c7 MT |
2123 | } |
2124 | ||
1f50f1b3 | 2125 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 2126 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2127 | return false; |
4731d4c7 MT |
2128 | } |
2129 | ||
1f50f1b3 | 2130 | return true; |
4731d4c7 MT |
2131 | } |
2132 | ||
35a70510 PB |
2133 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2134 | struct list_head *invalid_list, | |
2135 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2136 | { |
35a70510 PB |
2137 | if (!list_empty(invalid_list)) { |
2138 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2139 | return; | |
2140 | } | |
d98ba053 | 2141 | |
35a70510 PB |
2142 | if (remote_flush) |
2143 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2144 | else if (local_flush) | |
2145 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2146 | } |
2147 | ||
e37fa785 XG |
2148 | #ifdef CONFIG_KVM_MMU_AUDIT |
2149 | #include "mmu_audit.c" | |
2150 | #else | |
2151 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2152 | static void mmu_audit_disable(void) { } | |
2153 | #endif | |
2154 | ||
46971a2f XG |
2155 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2156 | { | |
2157 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2158 | } | |
2159 | ||
1f50f1b3 | 2160 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2161 | struct list_head *invalid_list) |
1d9dc7e0 | 2162 | { |
9a43c5d9 PB |
2163 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2164 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2165 | } |
2166 | ||
9f1a122f | 2167 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2168 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2169 | struct list_head *invalid_list) | |
9f1a122f | 2170 | { |
9f1a122f | 2171 | struct kvm_mmu_page *s; |
2a74003a | 2172 | bool ret = false; |
9f1a122f | 2173 | |
b67bfe0d | 2174 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2175 | if (!s->unsync) |
9f1a122f XG |
2176 | continue; |
2177 | ||
2178 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2179 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2180 | } |
2181 | ||
2a74003a | 2182 | return ret; |
9f1a122f XG |
2183 | } |
2184 | ||
60c8aec6 | 2185 | struct mmu_page_path { |
2a7266a8 YZ |
2186 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2187 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2188 | }; |
2189 | ||
60c8aec6 | 2190 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2191 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2192 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2193 | i = mmu_pages_next(&pvec, &parents, i)) | |
2194 | ||
cded19f3 HE |
2195 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2196 | struct mmu_page_path *parents, | |
2197 | int i) | |
60c8aec6 MT |
2198 | { |
2199 | int n; | |
2200 | ||
2201 | for (n = i+1; n < pvec->nr; n++) { | |
2202 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2203 | unsigned idx = pvec->page[n].idx; |
2204 | int level = sp->role.level; | |
60c8aec6 | 2205 | |
0a47cd85 PB |
2206 | parents->idx[level-1] = idx; |
2207 | if (level == PT_PAGE_TABLE_LEVEL) | |
2208 | break; | |
60c8aec6 | 2209 | |
0a47cd85 | 2210 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2211 | } |
2212 | ||
2213 | return n; | |
2214 | } | |
2215 | ||
0a47cd85 PB |
2216 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2217 | struct mmu_page_path *parents) | |
2218 | { | |
2219 | struct kvm_mmu_page *sp; | |
2220 | int level; | |
2221 | ||
2222 | if (pvec->nr == 0) | |
2223 | return 0; | |
2224 | ||
e23d3fef XG |
2225 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2226 | ||
0a47cd85 PB |
2227 | sp = pvec->page[0].sp; |
2228 | level = sp->role.level; | |
2229 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2230 | ||
2231 | parents->parent[level-2] = sp; | |
2232 | ||
2233 | /* Also set up a sentinel. Further entries in pvec are all | |
2234 | * children of sp, so this element is never overwritten. | |
2235 | */ | |
2236 | parents->parent[level-1] = NULL; | |
2237 | return mmu_pages_next(pvec, parents, 0); | |
2238 | } | |
2239 | ||
cded19f3 | 2240 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2241 | { |
60c8aec6 MT |
2242 | struct kvm_mmu_page *sp; |
2243 | unsigned int level = 0; | |
2244 | ||
2245 | do { | |
2246 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2247 | sp = parents->parent[level]; |
2248 | if (!sp) | |
2249 | return; | |
2250 | ||
e23d3fef | 2251 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2252 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2253 | level++; |
0a47cd85 | 2254 | } while (!sp->unsync_children); |
60c8aec6 | 2255 | } |
4731d4c7 | 2256 | |
60c8aec6 MT |
2257 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2258 | struct kvm_mmu_page *parent) | |
2259 | { | |
2260 | int i; | |
2261 | struct kvm_mmu_page *sp; | |
2262 | struct mmu_page_path parents; | |
2263 | struct kvm_mmu_pages pages; | |
d98ba053 | 2264 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2265 | bool flush = false; |
60c8aec6 | 2266 | |
60c8aec6 | 2267 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2268 | bool protected = false; |
b1a36821 MT |
2269 | |
2270 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2271 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2272 | |
50c9e6f3 | 2273 | if (protected) { |
b1a36821 | 2274 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2275 | flush = false; |
2276 | } | |
b1a36821 | 2277 | |
60c8aec6 | 2278 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2279 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2280 | mmu_pages_clear_parents(&parents); |
2281 | } | |
50c9e6f3 PB |
2282 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2283 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2284 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2285 | flush = false; | |
2286 | } | |
60c8aec6 | 2287 | } |
50c9e6f3 PB |
2288 | |
2289 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2290 | } |
2291 | ||
a30f47cb XG |
2292 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2293 | { | |
e5691a81 | 2294 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2295 | } |
2296 | ||
2297 | static void clear_sp_write_flooding_count(u64 *spte) | |
2298 | { | |
2299 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2300 | ||
2301 | __clear_sp_write_flooding_count(sp); | |
2302 | } | |
2303 | ||
cea0f0e7 AK |
2304 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2305 | gfn_t gfn, | |
2306 | gva_t gaddr, | |
2307 | unsigned level, | |
f6e2c02b | 2308 | int direct, |
bb11c6c9 | 2309 | unsigned access) |
cea0f0e7 AK |
2310 | { |
2311 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2312 | unsigned quadrant; |
9f1a122f | 2313 | struct kvm_mmu_page *sp; |
9f1a122f | 2314 | bool need_sync = false; |
2a74003a | 2315 | bool flush = false; |
f3414bc7 | 2316 | int collisions = 0; |
2a74003a | 2317 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2318 | |
a770f6f2 | 2319 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2320 | role.level = level; |
f6e2c02b | 2321 | role.direct = direct; |
84b0c8c6 | 2322 | if (role.direct) |
5b7e0102 | 2323 | role.cr4_pae = 0; |
41074d07 | 2324 | role.access = access; |
c5a78f2b JR |
2325 | if (!vcpu->arch.mmu.direct_map |
2326 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2327 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2328 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2329 | role.quadrant = quadrant; | |
2330 | } | |
f3414bc7 DM |
2331 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2332 | if (sp->gfn != gfn) { | |
2333 | collisions++; | |
2334 | continue; | |
2335 | } | |
2336 | ||
7ae680eb XG |
2337 | if (!need_sync && sp->unsync) |
2338 | need_sync = true; | |
4731d4c7 | 2339 | |
7ae680eb XG |
2340 | if (sp->role.word != role.word) |
2341 | continue; | |
4731d4c7 | 2342 | |
2a74003a PB |
2343 | if (sp->unsync) { |
2344 | /* The page is good, but __kvm_sync_page might still end | |
2345 | * up zapping it. If so, break in order to rebuild it. | |
2346 | */ | |
2347 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2348 | break; | |
2349 | ||
2350 | WARN_ON(!list_empty(&invalid_list)); | |
2351 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2352 | } | |
e02aa901 | 2353 | |
98bba238 | 2354 | if (sp->unsync_children) |
a8eeb04a | 2355 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2356 | |
a30f47cb | 2357 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2358 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2359 | goto out; |
7ae680eb | 2360 | } |
47005792 | 2361 | |
dfc5aa00 | 2362 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2363 | |
2364 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2365 | ||
4db35314 AK |
2366 | sp->gfn = gfn; |
2367 | sp->role = role; | |
7ae680eb XG |
2368 | hlist_add_head(&sp->hash_link, |
2369 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2370 | if (!direct) { |
56ca57f9 XG |
2371 | /* |
2372 | * we should do write protection before syncing pages | |
2373 | * otherwise the content of the synced shadow page may | |
2374 | * be inconsistent with guest page table. | |
2375 | */ | |
2376 | account_shadowed(vcpu->kvm, sp); | |
2377 | if (level == PT_PAGE_TABLE_LEVEL && | |
2378 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2379 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2380 | |
9f1a122f | 2381 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2382 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2383 | } |
5304b8d3 | 2384 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2385 | clear_page(sp->spt); |
f691fe1d | 2386 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2387 | |
2388 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2389 | out: |
2390 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2391 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2392 | return sp; |
cea0f0e7 AK |
2393 | } |
2394 | ||
2d11123a AK |
2395 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2396 | struct kvm_vcpu *vcpu, u64 addr) | |
2397 | { | |
2398 | iterator->addr = addr; | |
2399 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2400 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 | 2401 | |
2a7266a8 YZ |
2402 | if (iterator->level == PT64_ROOT_4LEVEL && |
2403 | vcpu->arch.mmu.root_level < PT64_ROOT_4LEVEL && | |
81407ca5 JR |
2404 | !vcpu->arch.mmu.direct_map) |
2405 | --iterator->level; | |
2406 | ||
2d11123a AK |
2407 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2408 | iterator->shadow_addr | |
2409 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2410 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2411 | --iterator->level; | |
2412 | if (!iterator->shadow_addr) | |
2413 | iterator->level = 0; | |
2414 | } | |
2415 | } | |
2416 | ||
2417 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2418 | { | |
2419 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2420 | return false; | |
4d88954d | 2421 | |
2d11123a AK |
2422 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2423 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2424 | return true; | |
2425 | } | |
2426 | ||
c2a2ac2b XG |
2427 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2428 | u64 spte) | |
2d11123a | 2429 | { |
c2a2ac2b | 2430 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2431 | iterator->level = 0; |
2432 | return; | |
2433 | } | |
2434 | ||
c2a2ac2b | 2435 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2436 | --iterator->level; |
2437 | } | |
2438 | ||
c2a2ac2b XG |
2439 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2440 | { | |
bb606a9b | 2441 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2442 | } |
2443 | ||
98bba238 TY |
2444 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2445 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2446 | { |
2447 | u64 spte; | |
2448 | ||
ffb128c8 | 2449 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2450 | |
ffb128c8 | 2451 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2452 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2453 | |
2454 | if (sp_ad_disabled(sp)) | |
2455 | spte |= shadow_acc_track_value; | |
2456 | else | |
2457 | spte |= shadow_accessed_mask; | |
24db2734 | 2458 | |
1df9f2dc | 2459 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2460 | |
2461 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2462 | ||
2463 | if (sp->unsync_children || sp->unsync) | |
2464 | mark_unsync(sptep); | |
32ef26a3 AK |
2465 | } |
2466 | ||
a357bd22 AK |
2467 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2468 | unsigned direct_access) | |
2469 | { | |
2470 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2471 | struct kvm_mmu_page *child; | |
2472 | ||
2473 | /* | |
2474 | * For the direct sp, if the guest pte's dirty bit | |
2475 | * changed form clean to dirty, it will corrupt the | |
2476 | * sp's access: allow writable in the read-only sp, | |
2477 | * so we should update the spte at this point to get | |
2478 | * a new sp with the correct access. | |
2479 | */ | |
2480 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2481 | if (child->role.access == direct_access) | |
2482 | return; | |
2483 | ||
bcdd9a93 | 2484 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2485 | kvm_flush_remote_tlbs(vcpu->kvm); |
2486 | } | |
2487 | } | |
2488 | ||
505aef8f | 2489 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2490 | u64 *spte) |
2491 | { | |
2492 | u64 pte; | |
2493 | struct kvm_mmu_page *child; | |
2494 | ||
2495 | pte = *spte; | |
2496 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2497 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2498 | drop_spte(kvm, spte); |
505aef8f XG |
2499 | if (is_large_pte(pte)) |
2500 | --kvm->stat.lpages; | |
2501 | } else { | |
38e3b2b2 | 2502 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2503 | drop_parent_pte(child, spte); |
38e3b2b2 | 2504 | } |
505aef8f XG |
2505 | return true; |
2506 | } | |
2507 | ||
2508 | if (is_mmio_spte(pte)) | |
ce88decf | 2509 | mmu_spte_clear_no_track(spte); |
c3707958 | 2510 | |
505aef8f | 2511 | return false; |
38e3b2b2 XG |
2512 | } |
2513 | ||
90cb0529 | 2514 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2515 | struct kvm_mmu_page *sp) |
a436036b | 2516 | { |
697fe2e2 | 2517 | unsigned i; |
697fe2e2 | 2518 | |
38e3b2b2 XG |
2519 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2520 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2521 | } |
2522 | ||
31aa2b44 | 2523 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2524 | { |
1e3f42f0 TY |
2525 | u64 *sptep; |
2526 | struct rmap_iterator iter; | |
a436036b | 2527 | |
018aabb5 | 2528 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2529 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2530 | } |
2531 | ||
60c8aec6 | 2532 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2533 | struct kvm_mmu_page *parent, |
2534 | struct list_head *invalid_list) | |
4731d4c7 | 2535 | { |
60c8aec6 MT |
2536 | int i, zapped = 0; |
2537 | struct mmu_page_path parents; | |
2538 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2539 | |
60c8aec6 | 2540 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2541 | return 0; |
60c8aec6 | 2542 | |
60c8aec6 MT |
2543 | while (mmu_unsync_walk(parent, &pages)) { |
2544 | struct kvm_mmu_page *sp; | |
2545 | ||
2546 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2547 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2548 | mmu_pages_clear_parents(&parents); |
77662e00 | 2549 | zapped++; |
60c8aec6 | 2550 | } |
60c8aec6 MT |
2551 | } |
2552 | ||
2553 | return zapped; | |
4731d4c7 MT |
2554 | } |
2555 | ||
7775834a XG |
2556 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2557 | struct list_head *invalid_list) | |
31aa2b44 | 2558 | { |
4731d4c7 | 2559 | int ret; |
f691fe1d | 2560 | |
7775834a | 2561 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2562 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2563 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2564 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2565 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2566 | |
f6e2c02b | 2567 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2568 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2569 | |
4731d4c7 MT |
2570 | if (sp->unsync) |
2571 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2572 | if (!sp->root_count) { |
54a4f023 GJ |
2573 | /* Count self */ |
2574 | ret++; | |
7775834a | 2575 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2576 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2577 | } else { |
5b5c6a5a | 2578 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2579 | |
2580 | /* | |
2581 | * The obsolete pages can not be used on any vcpus. | |
2582 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2583 | */ | |
2584 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2585 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2586 | } |
7775834a XG |
2587 | |
2588 | sp->role.invalid = 1; | |
4731d4c7 | 2589 | return ret; |
a436036b AK |
2590 | } |
2591 | ||
7775834a XG |
2592 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2593 | struct list_head *invalid_list) | |
2594 | { | |
945315b9 | 2595 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2596 | |
2597 | if (list_empty(invalid_list)) | |
2598 | return; | |
2599 | ||
c142786c | 2600 | /* |
9753f529 LT |
2601 | * We need to make sure everyone sees our modifications to |
2602 | * the page tables and see changes to vcpu->mode here. The barrier | |
2603 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2604 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2605 | * | |
2606 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2607 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2608 | */ |
2609 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2610 | |
945315b9 | 2611 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2612 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2613 | kvm_mmu_free_page(sp); |
945315b9 | 2614 | } |
7775834a XG |
2615 | } |
2616 | ||
5da59607 TY |
2617 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2618 | struct list_head *invalid_list) | |
2619 | { | |
2620 | struct kvm_mmu_page *sp; | |
2621 | ||
2622 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2623 | return false; | |
2624 | ||
d74c0e6b GT |
2625 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2626 | struct kvm_mmu_page, link); | |
42bcbebf | 2627 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2628 | } |
2629 | ||
82ce2c96 IE |
2630 | /* |
2631 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2632 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2633 | */ |
49d5ca26 | 2634 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2635 | { |
d98ba053 | 2636 | LIST_HEAD(invalid_list); |
82ce2c96 | 2637 | |
b34cb590 TY |
2638 | spin_lock(&kvm->mmu_lock); |
2639 | ||
49d5ca26 | 2640 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2641 | /* Need to free some mmu pages to achieve the goal. */ |
2642 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2643 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2644 | break; | |
82ce2c96 | 2645 | |
aa6bd187 | 2646 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2647 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2648 | } |
82ce2c96 | 2649 | |
49d5ca26 | 2650 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2651 | |
2652 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2653 | } |
2654 | ||
1cb3f3ae | 2655 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2656 | { |
4db35314 | 2657 | struct kvm_mmu_page *sp; |
d98ba053 | 2658 | LIST_HEAD(invalid_list); |
a436036b AK |
2659 | int r; |
2660 | ||
9ad17b10 | 2661 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2662 | r = 0; |
1cb3f3ae | 2663 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2664 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2665 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2666 | sp->role.word); |
2667 | r = 1; | |
f41d335a | 2668 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2669 | } |
d98ba053 | 2670 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2671 | spin_unlock(&kvm->mmu_lock); |
2672 | ||
a436036b | 2673 | return r; |
cea0f0e7 | 2674 | } |
1cb3f3ae | 2675 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2676 | |
5c520e90 | 2677 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2678 | { |
2679 | trace_kvm_mmu_unsync_page(sp); | |
2680 | ++vcpu->kvm->stat.mmu_unsync; | |
2681 | sp->unsync = 1; | |
2682 | ||
2683 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2684 | } |
2685 | ||
3d0c27ad XG |
2686 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2687 | bool can_unsync) | |
4731d4c7 | 2688 | { |
5c520e90 | 2689 | struct kvm_mmu_page *sp; |
4731d4c7 | 2690 | |
3d0c27ad XG |
2691 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2692 | return true; | |
9cf5cf5a | 2693 | |
5c520e90 | 2694 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2695 | if (!can_unsync) |
3d0c27ad | 2696 | return true; |
36a2e677 | 2697 | |
5c520e90 XG |
2698 | if (sp->unsync) |
2699 | continue; | |
9cf5cf5a | 2700 | |
5c520e90 XG |
2701 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2702 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2703 | } |
3d0c27ad XG |
2704 | |
2705 | return false; | |
4731d4c7 MT |
2706 | } |
2707 | ||
ba049e93 | 2708 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2709 | { |
2710 | if (pfn_valid(pfn)) | |
2711 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2712 | ||
2713 | return true; | |
2714 | } | |
2715 | ||
d555c333 | 2716 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2717 | unsigned pte_access, int level, |
ba049e93 | 2718 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2719 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2720 | { |
ffb128c8 | 2721 | u64 spte = 0; |
1e73f9dd | 2722 | int ret = 0; |
ac8d57e5 | 2723 | struct kvm_mmu_page *sp; |
64d4d521 | 2724 | |
54bf36aa | 2725 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2726 | return 0; |
2727 | ||
ac8d57e5 PF |
2728 | sp = page_header(__pa(sptep)); |
2729 | if (sp_ad_disabled(sp)) | |
2730 | spte |= shadow_acc_track_value; | |
2731 | ||
d95c5568 BD |
2732 | /* |
2733 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2734 | * supports exec-only page table entries. In that case, | |
2735 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2736 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2737 | */ | |
ffb128c8 | 2738 | spte |= shadow_present_mask; |
947da538 | 2739 | if (!speculative) |
ac8d57e5 | 2740 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2741 | |
7b52345e SY |
2742 | if (pte_access & ACC_EXEC_MASK) |
2743 | spte |= shadow_x_mask; | |
2744 | else | |
2745 | spte |= shadow_nx_mask; | |
49fde340 | 2746 | |
1c4f1fd6 | 2747 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2748 | spte |= shadow_user_mask; |
49fde340 | 2749 | |
852e3c19 | 2750 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2751 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2752 | if (tdp_enabled) |
4b12f0de | 2753 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2754 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2755 | |
9bdbba13 | 2756 | if (host_writable) |
1403283a | 2757 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2758 | else |
2759 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2760 | |
35149e21 | 2761 | spte |= (u64)pfn << PAGE_SHIFT; |
d0ec49d4 | 2762 | spte |= shadow_me_mask; |
1c4f1fd6 | 2763 | |
c2288505 | 2764 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2765 | |
c2193463 | 2766 | /* |
7751babd XG |
2767 | * Other vcpu creates new sp in the window between |
2768 | * mapping_level() and acquiring mmu-lock. We can | |
2769 | * allow guest to retry the access, the mapping can | |
2770 | * be fixed if guest refault. | |
c2193463 | 2771 | */ |
852e3c19 | 2772 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2773 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2774 | goto done; |
38187c83 | 2775 | |
49fde340 | 2776 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2777 | |
ecc5589f MT |
2778 | /* |
2779 | * Optimization: for pte sync, if spte was writable the hash | |
2780 | * lookup is unnecessary (and expensive). Write protection | |
2781 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2782 | * Same reasoning can be applied to dirty page accounting. | |
2783 | */ | |
8dae4445 | 2784 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2785 | goto set_pte; |
2786 | ||
4731d4c7 | 2787 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2788 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2789 | __func__, gfn); |
1e73f9dd | 2790 | ret = 1; |
1c4f1fd6 | 2791 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2792 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2793 | } |
2794 | } | |
2795 | ||
9b51a630 | 2796 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2797 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2798 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2799 | } |
1c4f1fd6 | 2800 | |
f160c7b7 JS |
2801 | if (speculative) |
2802 | spte = mark_spte_for_access_track(spte); | |
2803 | ||
38187c83 | 2804 | set_pte: |
6e7d0354 | 2805 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2806 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2807 | done: |
1e73f9dd MT |
2808 | return ret; |
2809 | } | |
2810 | ||
9b8ebbdb PB |
2811 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
2812 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, | |
2813 | bool speculative, bool host_writable) | |
1e73f9dd MT |
2814 | { |
2815 | int was_rmapped = 0; | |
53a27b39 | 2816 | int rmap_count; |
9b8ebbdb | 2817 | int ret = RET_PF_RETRY; |
1e73f9dd | 2818 | |
f7616203 XG |
2819 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2820 | *sptep, write_fault, gfn); | |
1e73f9dd | 2821 | |
afd28fe1 | 2822 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2823 | /* |
2824 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2825 | * the parent of the now unreachable PTE. | |
2826 | */ | |
852e3c19 JR |
2827 | if (level > PT_PAGE_TABLE_LEVEL && |
2828 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2829 | struct kvm_mmu_page *child; |
d555c333 | 2830 | u64 pte = *sptep; |
1e73f9dd MT |
2831 | |
2832 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2833 | drop_parent_pte(child, sptep); |
3be2264b | 2834 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2835 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2836 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2837 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2838 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2839 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2840 | } else |
2841 | was_rmapped = 1; | |
1e73f9dd | 2842 | } |
852e3c19 | 2843 | |
c2288505 XG |
2844 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2845 | true, host_writable)) { | |
1e73f9dd | 2846 | if (write_fault) |
9b8ebbdb | 2847 | ret = RET_PF_EMULATE; |
77c3913b | 2848 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2849 | } |
1e73f9dd | 2850 | |
029499b4 | 2851 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 2852 | ret = RET_PF_EMULATE; |
ce88decf | 2853 | |
d555c333 | 2854 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2855 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2856 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 2857 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 2858 | *sptep, sptep); |
d555c333 | 2859 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2860 | ++vcpu->kvm->stat.lpages; |
2861 | ||
ffb61bb3 | 2862 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2863 | if (!was_rmapped) { |
2864 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2865 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2866 | rmap_recycle(vcpu, sptep, gfn); | |
2867 | } | |
1c4f1fd6 | 2868 | } |
cb9aaa30 | 2869 | |
f3ac1a4b | 2870 | kvm_release_pfn_clean(pfn); |
029499b4 | 2871 | |
9b8ebbdb | 2872 | return ret; |
1c4f1fd6 AK |
2873 | } |
2874 | ||
ba049e93 | 2875 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2876 | bool no_dirty_log) |
2877 | { | |
2878 | struct kvm_memory_slot *slot; | |
957ed9ef | 2879 | |
5d163b1c | 2880 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2881 | if (!slot) |
6c8ee57b | 2882 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2883 | |
037d92dc | 2884 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2885 | } |
2886 | ||
2887 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2888 | struct kvm_mmu_page *sp, | |
2889 | u64 *start, u64 *end) | |
2890 | { | |
2891 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2892 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2893 | unsigned access = sp->role.access; |
2894 | int i, ret; | |
2895 | gfn_t gfn; | |
2896 | ||
2897 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2898 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2899 | if (!slot) | |
957ed9ef XG |
2900 | return -1; |
2901 | ||
d9ef13c2 | 2902 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2903 | if (ret <= 0) |
2904 | return -1; | |
2905 | ||
2906 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2907 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2908 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2909 | |
2910 | return 0; | |
2911 | } | |
2912 | ||
2913 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2914 | struct kvm_mmu_page *sp, u64 *sptep) | |
2915 | { | |
2916 | u64 *spte, *start = NULL; | |
2917 | int i; | |
2918 | ||
2919 | WARN_ON(!sp->role.direct); | |
2920 | ||
2921 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2922 | spte = sp->spt + i; | |
2923 | ||
2924 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2925 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2926 | if (!start) |
2927 | continue; | |
2928 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2929 | break; | |
2930 | start = NULL; | |
2931 | } else if (!start) | |
2932 | start = spte; | |
2933 | } | |
2934 | } | |
2935 | ||
2936 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2937 | { | |
2938 | struct kvm_mmu_page *sp; | |
2939 | ||
ac8d57e5 PF |
2940 | sp = page_header(__pa(sptep)); |
2941 | ||
957ed9ef | 2942 | /* |
ac8d57e5 PF |
2943 | * Without accessed bits, there's no way to distinguish between |
2944 | * actually accessed translations and prefetched, so disable pte | |
2945 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2946 | */ |
ac8d57e5 | 2947 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2948 | return; |
2949 | ||
957ed9ef XG |
2950 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
2951 | return; | |
2952 | ||
2953 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2954 | } | |
2955 | ||
7ee0e5b2 | 2956 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2957 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2958 | { |
9f652d21 | 2959 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2960 | struct kvm_mmu_page *sp; |
b90a0e6c | 2961 | int emulate = 0; |
140754bc | 2962 | gfn_t pseudo_gfn; |
6aa8b732 | 2963 | |
989c6b34 MT |
2964 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2965 | return 0; | |
2966 | ||
9f652d21 | 2967 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2968 | if (iterator.level == level) { |
029499b4 TY |
2969 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2970 | write, level, gfn, pfn, prefault, | |
2971 | map_writable); | |
957ed9ef | 2972 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2973 | ++vcpu->stat.pf_fixed; |
2974 | break; | |
6aa8b732 AK |
2975 | } |
2976 | ||
404381c5 | 2977 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2978 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2979 | u64 base_addr = iterator.addr; |
2980 | ||
2981 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2982 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2983 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2984 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2985 | |
98bba238 | 2986 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2987 | } |
2988 | } | |
b90a0e6c | 2989 | return emulate; |
6aa8b732 AK |
2990 | } |
2991 | ||
77db5cbd | 2992 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2993 | { |
77db5cbd HY |
2994 | siginfo_t info; |
2995 | ||
2996 | info.si_signo = SIGBUS; | |
2997 | info.si_errno = 0; | |
2998 | info.si_code = BUS_MCEERR_AR; | |
2999 | info.si_addr = (void __user *)address; | |
3000 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 3001 | |
77db5cbd | 3002 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
3003 | } |
3004 | ||
ba049e93 | 3005 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3006 | { |
4d8b81ab XG |
3007 | /* |
3008 | * Do not cache the mmio info caused by writing the readonly gfn | |
3009 | * into the spte otherwise read access on readonly gfn also can | |
3010 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3011 | */ |
3012 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3013 | return RET_PF_EMULATE; |
4d8b81ab | 3014 | |
e6c1502b | 3015 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3016 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3017 | return RET_PF_RETRY; |
d7c55201 | 3018 | } |
edba23e5 | 3019 | |
d7c55201 | 3020 | return -EFAULT; |
bf998156 HY |
3021 | } |
3022 | ||
936a5fe6 | 3023 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3024 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3025 | int *levelp) | |
936a5fe6 | 3026 | { |
ba049e93 | 3027 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3028 | gfn_t gfn = *gfnp; |
3029 | int level = *levelp; | |
3030 | ||
3031 | /* | |
3032 | * Check if it's a transparent hugepage. If this would be an | |
3033 | * hugetlbfs page, level wouldn't be set to | |
3034 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3035 | * here. | |
3036 | */ | |
bf4bea8e | 3037 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3038 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3039 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3040 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3041 | unsigned long mask; |
3042 | /* | |
3043 | * mmu_notifier_retry was successful and we hold the | |
3044 | * mmu_lock here, so the pmd can't become splitting | |
3045 | * from under us, and in turn | |
3046 | * __split_huge_page_refcount() can't run from under | |
3047 | * us and we can safely transfer the refcount from | |
3048 | * PG_tail to PG_head as we switch the pfn to tail to | |
3049 | * head. | |
3050 | */ | |
3051 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3052 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3053 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3054 | if (pfn & mask) { | |
3055 | gfn &= ~mask; | |
3056 | *gfnp = gfn; | |
3057 | kvm_release_pfn_clean(pfn); | |
3058 | pfn &= ~mask; | |
c3586667 | 3059 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3060 | *pfnp = pfn; |
3061 | } | |
3062 | } | |
3063 | } | |
3064 | ||
d7c55201 | 3065 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3066 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3067 | { |
d7c55201 | 3068 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3069 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3070 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3071 | return true; |
d7c55201 XG |
3072 | } |
3073 | ||
ce88decf | 3074 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3075 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3076 | |
798e88b3 | 3077 | return false; |
d7c55201 XG |
3078 | } |
3079 | ||
e5552fd2 | 3080 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3081 | { |
1c118b82 XG |
3082 | /* |
3083 | * Do not fix the mmio spte with invalid generation number which | |
3084 | * need to be updated by slow page fault path. | |
3085 | */ | |
3086 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3087 | return false; | |
3088 | ||
f160c7b7 JS |
3089 | /* See if the page fault is due to an NX violation */ |
3090 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3091 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3092 | return false; | |
3093 | ||
c7ba5b48 | 3094 | /* |
f160c7b7 JS |
3095 | * #PF can be fast if: |
3096 | * 1. The shadow page table entry is not present, which could mean that | |
3097 | * the fault is potentially caused by access tracking (if enabled). | |
3098 | * 2. The shadow page table entry is present and the fault | |
3099 | * is caused by write-protect, that means we just need change the W | |
3100 | * bit of the spte which can be done out of mmu-lock. | |
3101 | * | |
3102 | * However, if access tracking is disabled we know that a non-present | |
3103 | * page must be a genuine page fault where we have to create a new SPTE. | |
3104 | * So, if access tracking is disabled, we return true only for write | |
3105 | * accesses to a present page. | |
c7ba5b48 | 3106 | */ |
c7ba5b48 | 3107 | |
f160c7b7 JS |
3108 | return shadow_acc_track_mask != 0 || |
3109 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3110 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3111 | } |
3112 | ||
97dceba2 JS |
3113 | /* |
3114 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3115 | * someone else modified the SPTE from its original value. | |
3116 | */ | |
c7ba5b48 | 3117 | static bool |
92a476cb | 3118 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3119 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3120 | { |
c7ba5b48 XG |
3121 | gfn_t gfn; |
3122 | ||
3123 | WARN_ON(!sp->role.direct); | |
3124 | ||
9b51a630 KH |
3125 | /* |
3126 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3127 | * order to eliminate unnecessary PML logging. See comments in | |
3128 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3129 | * enabled, so we do not do this. This might result in the same GPA | |
3130 | * to be logged in PML buffer again when the write really happens, and | |
3131 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3132 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3133 | * so non-PML cases won't be impacted. | |
3134 | * | |
3135 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3136 | */ | |
f160c7b7 | 3137 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3138 | return false; |
3139 | ||
d3e328f2 | 3140 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3141 | /* |
3142 | * The gfn of direct spte is stable since it is | |
3143 | * calculated by sp->gfn. | |
3144 | */ | |
3145 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3146 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3147 | } | |
c7ba5b48 XG |
3148 | |
3149 | return true; | |
3150 | } | |
3151 | ||
d3e328f2 JS |
3152 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3153 | { | |
3154 | if (fault_err_code & PFERR_FETCH_MASK) | |
3155 | return is_executable_pte(spte); | |
3156 | ||
3157 | if (fault_err_code & PFERR_WRITE_MASK) | |
3158 | return is_writable_pte(spte); | |
3159 | ||
3160 | /* Fault was on Read access */ | |
3161 | return spte & PT_PRESENT_MASK; | |
3162 | } | |
3163 | ||
c7ba5b48 XG |
3164 | /* |
3165 | * Return value: | |
3166 | * - true: let the vcpu to access on the same address again. | |
3167 | * - false: let the real page fault path to fix it. | |
3168 | */ | |
3169 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3170 | u32 error_code) | |
3171 | { | |
3172 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3173 | struct kvm_mmu_page *sp; |
97dceba2 | 3174 | bool fault_handled = false; |
c7ba5b48 | 3175 | u64 spte = 0ull; |
97dceba2 | 3176 | uint retry_count = 0; |
c7ba5b48 | 3177 | |
37f6a4e2 MT |
3178 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3179 | return false; | |
3180 | ||
e5552fd2 | 3181 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3182 | return false; |
3183 | ||
3184 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3185 | |
97dceba2 | 3186 | do { |
d3e328f2 | 3187 | u64 new_spte; |
c7ba5b48 | 3188 | |
d162f30a JS |
3189 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3190 | if (!is_shadow_present_pte(spte) || | |
3191 | iterator.level < level) | |
3192 | break; | |
3193 | ||
97dceba2 JS |
3194 | sp = page_header(__pa(iterator.sptep)); |
3195 | if (!is_last_spte(spte, sp->role.level)) | |
3196 | break; | |
c7ba5b48 | 3197 | |
97dceba2 | 3198 | /* |
f160c7b7 JS |
3199 | * Check whether the memory access that caused the fault would |
3200 | * still cause it if it were to be performed right now. If not, | |
3201 | * then this is a spurious fault caused by TLB lazily flushed, | |
3202 | * or some other CPU has already fixed the PTE after the | |
3203 | * current CPU took the fault. | |
97dceba2 JS |
3204 | * |
3205 | * Need not check the access of upper level table entries since | |
3206 | * they are always ACC_ALL. | |
3207 | */ | |
d3e328f2 JS |
3208 | if (is_access_allowed(error_code, spte)) { |
3209 | fault_handled = true; | |
3210 | break; | |
3211 | } | |
f160c7b7 | 3212 | |
d3e328f2 JS |
3213 | new_spte = spte; |
3214 | ||
3215 | if (is_access_track_spte(spte)) | |
3216 | new_spte = restore_acc_track_spte(new_spte); | |
3217 | ||
3218 | /* | |
3219 | * Currently, to simplify the code, write-protection can | |
3220 | * be removed in the fast path only if the SPTE was | |
3221 | * write-protected for dirty-logging or access tracking. | |
3222 | */ | |
3223 | if ((error_code & PFERR_WRITE_MASK) && | |
3224 | spte_can_locklessly_be_made_writable(spte)) | |
3225 | { | |
3226 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3227 | |
3228 | /* | |
d3e328f2 JS |
3229 | * Do not fix write-permission on the large spte. Since |
3230 | * we only dirty the first page into the dirty-bitmap in | |
3231 | * fast_pf_fix_direct_spte(), other pages are missed | |
3232 | * if its slot has dirty logging enabled. | |
3233 | * | |
3234 | * Instead, we let the slow page fault path create a | |
3235 | * normal spte to fix the access. | |
3236 | * | |
3237 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3238 | */ |
d3e328f2 | 3239 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3240 | break; |
97dceba2 | 3241 | } |
c7ba5b48 | 3242 | |
f160c7b7 | 3243 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3244 | if (new_spte == spte || |
3245 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3246 | break; |
3247 | ||
3248 | /* | |
3249 | * Currently, fast page fault only works for direct mapping | |
3250 | * since the gfn is not stable for indirect shadow page. See | |
3251 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3252 | */ | |
3253 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3254 | iterator.sptep, spte, |
d3e328f2 | 3255 | new_spte); |
97dceba2 JS |
3256 | if (fault_handled) |
3257 | break; | |
3258 | ||
3259 | if (++retry_count > 4) { | |
3260 | printk_once(KERN_WARNING | |
3261 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3262 | break; | |
3263 | } | |
3264 | ||
97dceba2 | 3265 | } while (true); |
c126d94f | 3266 | |
a72faf25 | 3267 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3268 | spte, fault_handled); |
c7ba5b48 XG |
3269 | walk_shadow_page_lockless_end(vcpu); |
3270 | ||
97dceba2 | 3271 | return fault_handled; |
c7ba5b48 XG |
3272 | } |
3273 | ||
78b2c54a | 3274 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3275 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3276 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3277 | |
c7ba5b48 XG |
3278 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3279 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3280 | { |
3281 | int r; | |
852e3c19 | 3282 | int level; |
fd136902 | 3283 | bool force_pt_level = false; |
ba049e93 | 3284 | kvm_pfn_t pfn; |
e930bffe | 3285 | unsigned long mmu_seq; |
c7ba5b48 | 3286 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3287 | |
fd136902 | 3288 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3289 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3290 | /* |
3291 | * This path builds a PAE pagetable - so we can map | |
3292 | * 2mb pages at maximum. Therefore check if the level | |
3293 | * is larger than that. | |
3294 | */ | |
3295 | if (level > PT_DIRECTORY_LEVEL) | |
3296 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3297 | |
936a5fe6 | 3298 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3299 | } |
05da4558 | 3300 | |
c7ba5b48 | 3301 | if (fast_page_fault(vcpu, v, level, error_code)) |
9b8ebbdb | 3302 | return RET_PF_RETRY; |
c7ba5b48 | 3303 | |
e930bffe | 3304 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3305 | smp_rmb(); |
060c2abe | 3306 | |
78b2c54a | 3307 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
9b8ebbdb | 3308 | return RET_PF_RETRY; |
aaee2c94 | 3309 | |
d7c55201 XG |
3310 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3311 | return r; | |
d196e343 | 3312 | |
aaee2c94 | 3313 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3314 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3315 | goto out_unlock; |
26eeb53c WL |
3316 | if (make_mmu_pages_available(vcpu) < 0) |
3317 | goto out_unlock; | |
936a5fe6 AA |
3318 | if (likely(!force_pt_level)) |
3319 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3320 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3321 | spin_unlock(&vcpu->kvm->mmu_lock); |
3322 | ||
10589a46 | 3323 | return r; |
e930bffe AA |
3324 | |
3325 | out_unlock: | |
3326 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3327 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 3328 | return RET_PF_RETRY; |
10589a46 MT |
3329 | } |
3330 | ||
3331 | ||
17ac10ad AK |
3332 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3333 | { | |
3334 | int i; | |
4db35314 | 3335 | struct kvm_mmu_page *sp; |
d98ba053 | 3336 | LIST_HEAD(invalid_list); |
17ac10ad | 3337 | |
ad312c7c | 3338 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3339 | return; |
35af577a | 3340 | |
855feb67 YZ |
3341 | if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL && |
3342 | (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL || | |
81407ca5 | 3343 | vcpu->arch.mmu.direct_map)) { |
ad312c7c | 3344 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3345 | |
35af577a | 3346 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3347 | sp = page_header(root); |
3348 | --sp->root_count; | |
d98ba053 XG |
3349 | if (!sp->root_count && sp->role.invalid) { |
3350 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3351 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3352 | } | |
aaee2c94 | 3353 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3354 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3355 | return; |
3356 | } | |
35af577a GN |
3357 | |
3358 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3359 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3360 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3361 | |
417726a3 | 3362 | if (root) { |
417726a3 | 3363 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3364 | sp = page_header(root); |
3365 | --sp->root_count; | |
2e53d63a | 3366 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3367 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3368 | &invalid_list); | |
417726a3 | 3369 | } |
ad312c7c | 3370 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3371 | } |
d98ba053 | 3372 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3373 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3374 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3375 | } |
3376 | ||
8986ecc0 MT |
3377 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3378 | { | |
3379 | int ret = 0; | |
3380 | ||
3381 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3382 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3383 | ret = 1; |
3384 | } | |
3385 | ||
3386 | return ret; | |
3387 | } | |
3388 | ||
651dd37a JR |
3389 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3390 | { | |
3391 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3392 | unsigned i; |
651dd37a | 3393 | |
855feb67 | 3394 | if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3395 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3396 | if(make_mmu_pages_available(vcpu) < 0) { |
3397 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3398 | return -ENOSPC; |
26eeb53c | 3399 | } |
855feb67 YZ |
3400 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
3401 | vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL); | |
651dd37a JR |
3402 | ++sp->root_count; |
3403 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3404 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3405 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3406 | for (i = 0; i < 4; ++i) { | |
3407 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3408 | ||
fa4a2c08 | 3409 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3410 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3411 | if (make_mmu_pages_available(vcpu) < 0) { |
3412 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3413 | return -ENOSPC; |
26eeb53c | 3414 | } |
649497d1 | 3415 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3416 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3417 | root = __pa(sp->spt); |
3418 | ++sp->root_count; | |
3419 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3420 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3421 | } |
6292757f | 3422 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3423 | } else |
3424 | BUG(); | |
3425 | ||
3426 | return 0; | |
3427 | } | |
3428 | ||
3429 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3430 | { |
4db35314 | 3431 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3432 | u64 pdptr, pm_mask; |
3433 | gfn_t root_gfn; | |
3434 | int i; | |
3bb65a22 | 3435 | |
5777ed34 | 3436 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3437 | |
651dd37a JR |
3438 | if (mmu_check_root(vcpu, root_gfn)) |
3439 | return 1; | |
3440 | ||
3441 | /* | |
3442 | * Do we shadow a long mode page table? If so we need to | |
3443 | * write-protect the guests page table root. | |
3444 | */ | |
855feb67 | 3445 | if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) { |
ad312c7c | 3446 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3447 | |
fa4a2c08 | 3448 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3449 | |
8facbbff | 3450 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3451 | if (make_mmu_pages_available(vcpu) < 0) { |
3452 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3453 | return -ENOSPC; |
26eeb53c | 3454 | } |
855feb67 YZ |
3455 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
3456 | vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL); | |
4db35314 AK |
3457 | root = __pa(sp->spt); |
3458 | ++sp->root_count; | |
8facbbff | 3459 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3460 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3461 | return 0; |
17ac10ad | 3462 | } |
f87f9288 | 3463 | |
651dd37a JR |
3464 | /* |
3465 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3466 | * or a PAE 3-level page table. In either case we need to be aware that |
3467 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3468 | */ |
81407ca5 | 3469 | pm_mask = PT_PRESENT_MASK; |
2a7266a8 | 3470 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3471 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3472 | ||
17ac10ad | 3473 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3474 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3475 | |
fa4a2c08 | 3476 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3477 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3478 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
812f30b2 | 3479 | if (!(pdptr & PT_PRESENT_MASK)) { |
ad312c7c | 3480 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3481 | continue; |
3482 | } | |
6de4f3ad | 3483 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3484 | if (mmu_check_root(vcpu, root_gfn)) |
3485 | return 1; | |
5a7388c2 | 3486 | } |
8facbbff | 3487 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3488 | if (make_mmu_pages_available(vcpu) < 0) { |
3489 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3490 | return -ENOSPC; |
26eeb53c | 3491 | } |
bb11c6c9 TY |
3492 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3493 | 0, ACC_ALL); | |
4db35314 AK |
3494 | root = __pa(sp->spt); |
3495 | ++sp->root_count; | |
8facbbff AK |
3496 | spin_unlock(&vcpu->kvm->mmu_lock); |
3497 | ||
81407ca5 | 3498 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3499 | } |
6292757f | 3500 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3501 | |
3502 | /* | |
3503 | * If we shadow a 32 bit page table with a long mode page | |
3504 | * table we enter this path. | |
3505 | */ | |
2a7266a8 | 3506 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3507 | if (vcpu->arch.mmu.lm_root == NULL) { |
3508 | /* | |
3509 | * The additional page necessary for this is only | |
3510 | * allocated on demand. | |
3511 | */ | |
3512 | ||
3513 | u64 *lm_root; | |
3514 | ||
3515 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3516 | if (lm_root == NULL) | |
3517 | return 1; | |
3518 | ||
3519 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3520 | ||
3521 | vcpu->arch.mmu.lm_root = lm_root; | |
3522 | } | |
3523 | ||
3524 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3525 | } | |
3526 | ||
8986ecc0 | 3527 | return 0; |
17ac10ad AK |
3528 | } |
3529 | ||
651dd37a JR |
3530 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3531 | { | |
3532 | if (vcpu->arch.mmu.direct_map) | |
3533 | return mmu_alloc_direct_roots(vcpu); | |
3534 | else | |
3535 | return mmu_alloc_shadow_roots(vcpu); | |
3536 | } | |
3537 | ||
0ba73cda MT |
3538 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3539 | { | |
3540 | int i; | |
3541 | struct kvm_mmu_page *sp; | |
3542 | ||
81407ca5 JR |
3543 | if (vcpu->arch.mmu.direct_map) |
3544 | return; | |
3545 | ||
0ba73cda MT |
3546 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3547 | return; | |
6903074c | 3548 | |
56f17dd3 | 3549 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3550 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
855feb67 | 3551 | if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) { |
0ba73cda MT |
3552 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3553 | sp = page_header(root); | |
3554 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3555 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3556 | return; |
3557 | } | |
3558 | for (i = 0; i < 4; ++i) { | |
3559 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3560 | ||
8986ecc0 | 3561 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3562 | root &= PT64_BASE_ADDR_MASK; |
3563 | sp = page_header(root); | |
3564 | mmu_sync_children(vcpu, sp); | |
3565 | } | |
3566 | } | |
0375f7fa | 3567 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3568 | } |
3569 | ||
3570 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3571 | { | |
3572 | spin_lock(&vcpu->kvm->mmu_lock); | |
3573 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3574 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3575 | } |
bfd0a56b | 3576 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3577 | |
1871c602 | 3578 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3579 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3580 | { |
ab9ae313 AK |
3581 | if (exception) |
3582 | exception->error_code = 0; | |
6aa8b732 AK |
3583 | return vaddr; |
3584 | } | |
3585 | ||
6539e738 | 3586 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3587 | u32 access, |
3588 | struct x86_exception *exception) | |
6539e738 | 3589 | { |
ab9ae313 AK |
3590 | if (exception) |
3591 | exception->error_code = 0; | |
54987b7a | 3592 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3593 | } |
3594 | ||
d625b155 XG |
3595 | static bool |
3596 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3597 | { | |
3598 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3599 | ||
3600 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3601 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3602 | } | |
3603 | ||
3604 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3605 | { | |
3606 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3607 | } | |
3608 | ||
3609 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3610 | { | |
3611 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3612 | } | |
3613 | ||
ded58749 | 3614 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3615 | { |
9034e6e8 PB |
3616 | /* |
3617 | * A nested guest cannot use the MMIO cache if it is using nested | |
3618 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3619 | */ | |
3620 | if (mmu_is_nested(vcpu)) | |
3621 | return false; | |
3622 | ||
ce88decf XG |
3623 | if (direct) |
3624 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3625 | ||
3626 | return vcpu_match_mmio_gva(vcpu, addr); | |
3627 | } | |
3628 | ||
47ab8751 XG |
3629 | /* return true if reserved bit is detected on spte. */ |
3630 | static bool | |
3631 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3632 | { |
3633 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3634 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
47ab8751 XG |
3635 | int root, leaf; |
3636 | bool reserved = false; | |
ce88decf | 3637 | |
37f6a4e2 | 3638 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3639 | goto exit; |
37f6a4e2 | 3640 | |
ce88decf | 3641 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3642 | |
29ecd660 PB |
3643 | for (shadow_walk_init(&iterator, vcpu, addr), |
3644 | leaf = root = iterator.level; | |
47ab8751 XG |
3645 | shadow_walk_okay(&iterator); |
3646 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3647 | spte = mmu_spte_get_lockless(iterator.sptep); |
3648 | ||
3649 | sptes[leaf - 1] = spte; | |
29ecd660 | 3650 | leaf--; |
47ab8751 | 3651 | |
ce88decf XG |
3652 | if (!is_shadow_present_pte(spte)) |
3653 | break; | |
47ab8751 XG |
3654 | |
3655 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3656 | iterator.level); |
47ab8751 XG |
3657 | } |
3658 | ||
ce88decf XG |
3659 | walk_shadow_page_lockless_end(vcpu); |
3660 | ||
47ab8751 XG |
3661 | if (reserved) { |
3662 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3663 | __func__, addr); | |
29ecd660 | 3664 | while (root > leaf) { |
47ab8751 XG |
3665 | pr_err("------ spte 0x%llx level %d.\n", |
3666 | sptes[root - 1], root); | |
3667 | root--; | |
3668 | } | |
3669 | } | |
3670 | exit: | |
3671 | *sptep = spte; | |
3672 | return reserved; | |
ce88decf XG |
3673 | } |
3674 | ||
e08d26f0 | 3675 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3676 | { |
3677 | u64 spte; | |
47ab8751 | 3678 | bool reserved; |
ce88decf | 3679 | |
ded58749 | 3680 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3681 | return RET_PF_EMULATE; |
ce88decf | 3682 | |
47ab8751 | 3683 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3684 | if (WARN_ON(reserved)) |
9b8ebbdb | 3685 | return -EINVAL; |
ce88decf XG |
3686 | |
3687 | if (is_mmio_spte(spte)) { | |
3688 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3689 | unsigned access = get_mmio_spte_access(spte); | |
3690 | ||
54bf36aa | 3691 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3692 | return RET_PF_INVALID; |
f8f55942 | 3693 | |
ce88decf XG |
3694 | if (direct) |
3695 | addr = 0; | |
4f022648 XG |
3696 | |
3697 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3698 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3699 | return RET_PF_EMULATE; |
ce88decf XG |
3700 | } |
3701 | ||
ce88decf XG |
3702 | /* |
3703 | * If the page table is zapped by other cpus, let CPU fault again on | |
3704 | * the address. | |
3705 | */ | |
9b8ebbdb | 3706 | return RET_PF_RETRY; |
ce88decf | 3707 | } |
450869d6 | 3708 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3709 | |
3d0c27ad XG |
3710 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3711 | u32 error_code, gfn_t gfn) | |
3712 | { | |
3713 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3714 | return false; | |
3715 | ||
3716 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3717 | !(error_code & PFERR_WRITE_MASK)) | |
3718 | return false; | |
3719 | ||
3720 | /* | |
3721 | * guest is writing the page which is write tracked which can | |
3722 | * not be fixed by page fault handler. | |
3723 | */ | |
3724 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3725 | return true; | |
3726 | ||
3727 | return false; | |
3728 | } | |
3729 | ||
e5691a81 XG |
3730 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3731 | { | |
3732 | struct kvm_shadow_walk_iterator iterator; | |
3733 | u64 spte; | |
3734 | ||
3735 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3736 | return; | |
3737 | ||
3738 | walk_shadow_page_lockless_begin(vcpu); | |
3739 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3740 | clear_sp_write_flooding_count(iterator.sptep); | |
3741 | if (!is_shadow_present_pte(spte)) | |
3742 | break; | |
3743 | } | |
3744 | walk_shadow_page_lockless_end(vcpu); | |
3745 | } | |
3746 | ||
6aa8b732 | 3747 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3748 | u32 error_code, bool prefault) |
6aa8b732 | 3749 | { |
3d0c27ad | 3750 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3751 | int r; |
6aa8b732 | 3752 | |
b8688d51 | 3753 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3754 | |
3d0c27ad | 3755 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3756 | return RET_PF_EMULATE; |
ce88decf | 3757 | |
e2dec939 AK |
3758 | r = mmu_topup_memory_caches(vcpu); |
3759 | if (r) | |
3760 | return r; | |
714b93da | 3761 | |
fa4a2c08 | 3762 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3763 | |
6aa8b732 | 3764 | |
e833240f | 3765 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3766 | error_code, gfn, prefault); |
6aa8b732 AK |
3767 | } |
3768 | ||
7e1fbeac | 3769 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3770 | { |
3771 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3772 | |
7c90705b | 3773 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3774 | arch.gfn = gfn; |
c4806acd | 3775 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3776 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3777 | |
54bf36aa | 3778 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3779 | } |
3780 | ||
9bc1f09f | 3781 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3782 | { |
35754c98 | 3783 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3784 | kvm_event_needs_reinjection(vcpu))) |
3785 | return false; | |
3786 | ||
52a5c155 | 3787 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) |
9bc1f09f WL |
3788 | return false; |
3789 | ||
af585b92 GN |
3790 | return kvm_x86_ops->interrupt_allowed(vcpu); |
3791 | } | |
3792 | ||
78b2c54a | 3793 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3794 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3795 | { |
3520469d | 3796 | struct kvm_memory_slot *slot; |
af585b92 GN |
3797 | bool async; |
3798 | ||
54bf36aa | 3799 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3800 | async = false; |
3801 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3802 | if (!async) |
3803 | return false; /* *pfn has correct page already */ | |
3804 | ||
9bc1f09f | 3805 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 3806 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3807 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3808 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3809 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3810 | return true; | |
3811 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3812 | return true; | |
3813 | } | |
3814 | ||
3520469d | 3815 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3816 | return false; |
3817 | } | |
3818 | ||
1261bfa3 | 3819 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3820 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3821 | { |
3822 | int r = 1; | |
3823 | ||
3824 | switch (vcpu->arch.apf.host_apf_reason) { | |
3825 | default: | |
3826 | trace_kvm_page_fault(fault_address, error_code); | |
3827 | ||
d0006530 | 3828 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3829 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3830 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3831 | insn_len); | |
3832 | break; | |
3833 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
3834 | vcpu->arch.apf.host_apf_reason = 0; | |
3835 | local_irq_disable(); | |
a2b7861b | 3836 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
3837 | local_irq_enable(); |
3838 | break; | |
3839 | case KVM_PV_REASON_PAGE_READY: | |
3840 | vcpu->arch.apf.host_apf_reason = 0; | |
3841 | local_irq_disable(); | |
3842 | kvm_async_pf_task_wake(fault_address); | |
3843 | local_irq_enable(); | |
3844 | break; | |
3845 | } | |
3846 | return r; | |
3847 | } | |
3848 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3849 | ||
6a39bbc5 XG |
3850 | static bool |
3851 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3852 | { | |
3853 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3854 | ||
3855 | gfn &= ~(page_num - 1); | |
3856 | ||
3857 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3858 | } | |
3859 | ||
56028d08 | 3860 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3861 | bool prefault) |
fb72d167 | 3862 | { |
ba049e93 | 3863 | kvm_pfn_t pfn; |
fb72d167 | 3864 | int r; |
852e3c19 | 3865 | int level; |
cd1872f0 | 3866 | bool force_pt_level; |
05da4558 | 3867 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3868 | unsigned long mmu_seq; |
612819c3 MT |
3869 | int write = error_code & PFERR_WRITE_MASK; |
3870 | bool map_writable; | |
fb72d167 | 3871 | |
fa4a2c08 | 3872 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3873 | |
3d0c27ad | 3874 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3875 | return RET_PF_EMULATE; |
ce88decf | 3876 | |
fb72d167 JR |
3877 | r = mmu_topup_memory_caches(vcpu); |
3878 | if (r) | |
3879 | return r; | |
3880 | ||
fd136902 TY |
3881 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3882 | PT_DIRECTORY_LEVEL); | |
3883 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3884 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3885 | if (level > PT_DIRECTORY_LEVEL && |
3886 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3887 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3888 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3889 | } |
852e3c19 | 3890 | |
c7ba5b48 | 3891 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
9b8ebbdb | 3892 | return RET_PF_RETRY; |
c7ba5b48 | 3893 | |
e930bffe | 3894 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3895 | smp_rmb(); |
af585b92 | 3896 | |
78b2c54a | 3897 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
9b8ebbdb | 3898 | return RET_PF_RETRY; |
af585b92 | 3899 | |
d7c55201 XG |
3900 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3901 | return r; | |
3902 | ||
fb72d167 | 3903 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3904 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3905 | goto out_unlock; |
26eeb53c WL |
3906 | if (make_mmu_pages_available(vcpu) < 0) |
3907 | goto out_unlock; | |
936a5fe6 AA |
3908 | if (likely(!force_pt_level)) |
3909 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3910 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3911 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3912 | |
3913 | return r; | |
e930bffe AA |
3914 | |
3915 | out_unlock: | |
3916 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3917 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 3918 | return RET_PF_RETRY; |
fb72d167 JR |
3919 | } |
3920 | ||
8a3c1a33 PB |
3921 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3922 | struct kvm_mmu *context) | |
6aa8b732 | 3923 | { |
6aa8b732 | 3924 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3925 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3926 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3927 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3928 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3929 | context->root_level = 0; |
6aa8b732 | 3930 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3931 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3932 | context->direct_map = true; |
2d48a985 | 3933 | context->nx = false; |
6aa8b732 AK |
3934 | } |
3935 | ||
d8d173da | 3936 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3937 | { |
cea0f0e7 | 3938 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3939 | } |
3940 | ||
5777ed34 JR |
3941 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3942 | { | |
9f8fe504 | 3943 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3944 | } |
3945 | ||
6389ee94 AK |
3946 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3947 | struct x86_exception *fault) | |
6aa8b732 | 3948 | { |
6389ee94 | 3949 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3950 | } |
3951 | ||
54bf36aa | 3952 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3953 | unsigned access, int *nr_present) |
ce88decf XG |
3954 | { |
3955 | if (unlikely(is_mmio_spte(*sptep))) { | |
3956 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3957 | mmu_spte_clear_no_track(sptep); | |
3958 | return true; | |
3959 | } | |
3960 | ||
3961 | (*nr_present)++; | |
54bf36aa | 3962 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3963 | return true; |
3964 | } | |
3965 | ||
3966 | return false; | |
3967 | } | |
3968 | ||
6bb69c9b PB |
3969 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3970 | unsigned level, unsigned gpte) | |
6fd01b71 | 3971 | { |
6bb69c9b PB |
3972 | /* |
3973 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3974 | * If it is clear, there are no large pages at this level, so clear | |
3975 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3976 | */ | |
3977 | gpte &= level - mmu->last_nonleaf_level; | |
3978 | ||
829ee279 LP |
3979 | /* |
3980 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
3981 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
3982 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
3983 | */ | |
3984 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
3985 | ||
6bb69c9b | 3986 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
3987 | } |
3988 | ||
37406aaa NHE |
3989 | #define PTTYPE_EPT 18 /* arbitrary */ |
3990 | #define PTTYPE PTTYPE_EPT | |
3991 | #include "paging_tmpl.h" | |
3992 | #undef PTTYPE | |
3993 | ||
6aa8b732 AK |
3994 | #define PTTYPE 64 |
3995 | #include "paging_tmpl.h" | |
3996 | #undef PTTYPE | |
3997 | ||
3998 | #define PTTYPE 32 | |
3999 | #include "paging_tmpl.h" | |
4000 | #undef PTTYPE | |
4001 | ||
6dc98b86 XG |
4002 | static void |
4003 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4004 | struct rsvd_bits_validate *rsvd_check, | |
4005 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4006 | bool pse, bool amd) |
82725b20 | 4007 | { |
82725b20 | 4008 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4009 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4010 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4011 | |
a0a64f50 | 4012 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4013 | |
6dc98b86 | 4014 | if (!nx) |
82725b20 | 4015 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4016 | if (!gbpages) |
5f7dde7b | 4017 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4018 | |
4019 | /* | |
4020 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4021 | * leaf entries) on AMD CPUs only. | |
4022 | */ | |
6fec2144 | 4023 | if (amd) |
a0c0feb5 PB |
4024 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4025 | ||
6dc98b86 | 4026 | switch (level) { |
82725b20 DE |
4027 | case PT32_ROOT_LEVEL: |
4028 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4029 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4030 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4031 | rsvd_check->rsvd_bits_mask[1][0] = | |
4032 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4033 | |
6dc98b86 | 4034 | if (!pse) { |
a0a64f50 | 4035 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4036 | break; |
4037 | } | |
4038 | ||
82725b20 DE |
4039 | if (is_cpuid_PSE36()) |
4040 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4041 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4042 | else |
4043 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4044 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4045 | break; |
4046 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4047 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4048 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4049 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4050 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4051 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4052 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4053 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4054 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4055 | rsvd_bits(maxphyaddr, 62) | |
4056 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4057 | rsvd_check->rsvd_bits_mask[1][0] = |
4058 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4059 | break; |
855feb67 YZ |
4060 | case PT64_ROOT_5LEVEL: |
4061 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4062 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4063 | rsvd_bits(maxphyaddr, 51); | |
4064 | rsvd_check->rsvd_bits_mask[1][4] = | |
4065 | rsvd_check->rsvd_bits_mask[0][4]; | |
2a7266a8 | 4066 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4067 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4068 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4069 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4070 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4071 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4072 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4073 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4074 | rsvd_bits(maxphyaddr, 51); | |
4075 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4076 | rsvd_bits(maxphyaddr, 51); | |
4077 | rsvd_check->rsvd_bits_mask[1][3] = | |
4078 | rsvd_check->rsvd_bits_mask[0][3]; | |
4079 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4080 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4081 | rsvd_bits(13, 29); |
a0a64f50 | 4082 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4083 | rsvd_bits(maxphyaddr, 51) | |
4084 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4085 | rsvd_check->rsvd_bits_mask[1][0] = |
4086 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4087 | break; |
4088 | } | |
4089 | } | |
4090 | ||
6dc98b86 XG |
4091 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4092 | struct kvm_mmu *context) | |
4093 | { | |
4094 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4095 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4096 | context->nx, |
4097 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4098 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4099 | } |
4100 | ||
81b8eebb XG |
4101 | static void |
4102 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4103 | int maxphyaddr, bool execonly) | |
25d92081 | 4104 | { |
951f9fd7 | 4105 | u64 bad_mt_xwr; |
25d92081 | 4106 | |
855feb67 YZ |
4107 | rsvd_check->rsvd_bits_mask[0][4] = |
4108 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4109 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4110 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4111 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4112 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4113 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4114 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4115 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4116 | |
4117 | /* large page */ | |
855feb67 | 4118 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4119 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4120 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4121 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4122 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4123 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4124 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4125 | |
951f9fd7 PB |
4126 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4127 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4128 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4129 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4130 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4131 | if (!execonly) { | |
4132 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4133 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4134 | } |
951f9fd7 | 4135 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4136 | } |
4137 | ||
81b8eebb XG |
4138 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4139 | struct kvm_mmu *context, bool execonly) | |
4140 | { | |
4141 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4142 | cpuid_maxphyaddr(vcpu), execonly); | |
4143 | } | |
4144 | ||
c258b62b XG |
4145 | /* |
4146 | * the page table on host is the shadow page table for the page | |
4147 | * table in guest or amd nested guest, its mmu features completely | |
4148 | * follow the features in guest. | |
4149 | */ | |
4150 | void | |
4151 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4152 | { | |
5f0b8199 | 4153 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
ea2800dd BS |
4154 | struct rsvd_bits_validate *shadow_zero_check; |
4155 | int i; | |
5f0b8199 | 4156 | |
6fec2144 PB |
4157 | /* |
4158 | * Passing "true" to the last argument is okay; it adds a check | |
4159 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4160 | */ | |
ea2800dd BS |
4161 | shadow_zero_check = &context->shadow_zero_check; |
4162 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
c258b62b | 4163 | boot_cpu_data.x86_phys_bits, |
5f0b8199 | 4164 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4165 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4166 | is_pse(vcpu), true); | |
ea2800dd BS |
4167 | |
4168 | if (!shadow_me_mask) | |
4169 | return; | |
4170 | ||
4171 | for (i = context->shadow_root_level; --i >= 0;) { | |
4172 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4173 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4174 | } | |
4175 | ||
c258b62b XG |
4176 | } |
4177 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4178 | ||
6fec2144 PB |
4179 | static inline bool boot_cpu_is_amd(void) |
4180 | { | |
4181 | WARN_ON_ONCE(!tdp_enabled); | |
4182 | return shadow_x_mask == 0; | |
4183 | } | |
4184 | ||
c258b62b XG |
4185 | /* |
4186 | * the direct page table on host, use as much mmu features as | |
4187 | * possible, however, kvm currently does not do execution-protection. | |
4188 | */ | |
4189 | static void | |
4190 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4191 | struct kvm_mmu *context) | |
4192 | { | |
ea2800dd BS |
4193 | struct rsvd_bits_validate *shadow_zero_check; |
4194 | int i; | |
4195 | ||
4196 | shadow_zero_check = &context->shadow_zero_check; | |
4197 | ||
6fec2144 | 4198 | if (boot_cpu_is_amd()) |
ea2800dd | 4199 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
c258b62b XG |
4200 | boot_cpu_data.x86_phys_bits, |
4201 | context->shadow_root_level, false, | |
b8291adc BP |
4202 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4203 | true, true); | |
c258b62b | 4204 | else |
ea2800dd | 4205 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
c258b62b XG |
4206 | boot_cpu_data.x86_phys_bits, |
4207 | false); | |
4208 | ||
ea2800dd BS |
4209 | if (!shadow_me_mask) |
4210 | return; | |
4211 | ||
4212 | for (i = context->shadow_root_level; --i >= 0;) { | |
4213 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4214 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4215 | } | |
c258b62b XG |
4216 | } |
4217 | ||
4218 | /* | |
4219 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4220 | * is the shadow page table for intel nested guest. | |
4221 | */ | |
4222 | static void | |
4223 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4224 | struct kvm_mmu *context, bool execonly) | |
4225 | { | |
4226 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4227 | boot_cpu_data.x86_phys_bits, execonly); | |
4228 | } | |
4229 | ||
09f037aa PB |
4230 | #define BYTE_MASK(access) \ |
4231 | ((1 & (access) ? 2 : 0) | \ | |
4232 | (2 & (access) ? 4 : 0) | \ | |
4233 | (3 & (access) ? 8 : 0) | \ | |
4234 | (4 & (access) ? 16 : 0) | \ | |
4235 | (5 & (access) ? 32 : 0) | \ | |
4236 | (6 & (access) ? 64 : 0) | \ | |
4237 | (7 & (access) ? 128 : 0)) | |
4238 | ||
4239 | ||
edc90b7d XG |
4240 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4241 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4242 | { |
09f037aa PB |
4243 | unsigned byte; |
4244 | ||
4245 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4246 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4247 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4248 | ||
4249 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4250 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4251 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4252 | |
97d64b78 | 4253 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4254 | unsigned pfec = byte << 1; |
4255 | ||
97ec8c06 | 4256 | /* |
09f037aa PB |
4257 | * Each "*f" variable has a 1 bit for each UWX value |
4258 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4259 | */ |
97d64b78 | 4260 | |
09f037aa PB |
4261 | /* Faults from writes to non-writable pages */ |
4262 | u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; | |
4263 | /* Faults from user mode accesses to supervisor pages */ | |
4264 | u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; | |
4265 | /* Faults from fetches of non-executable pages*/ | |
4266 | u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; | |
4267 | /* Faults from kernel mode fetches of user pages */ | |
4268 | u8 smepf = 0; | |
4269 | /* Faults from kernel mode accesses of user pages */ | |
4270 | u8 smapf = 0; | |
4271 | ||
4272 | if (!ept) { | |
4273 | /* Faults from kernel mode accesses to user pages */ | |
4274 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4275 | ||
4276 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4277 | if (!mmu->nx) | |
4278 | ff = 0; | |
4279 | ||
4280 | /* Allow supervisor writes if !cr0.wp */ | |
4281 | if (!cr0_wp) | |
4282 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4283 | ||
4284 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4285 | if (cr4_smep) | |
4286 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4287 | ||
4288 | /* | |
4289 | * SMAP:kernel-mode data accesses from user-mode | |
4290 | * mappings should fault. A fault is considered | |
4291 | * as a SMAP violation if all of the following | |
4292 | * conditions are ture: | |
4293 | * - X86_CR4_SMAP is set in CR4 | |
4294 | * - A user page is accessed | |
4295 | * - The access is not a fetch | |
4296 | * - Page fault in kernel mode | |
4297 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4298 | * | |
4299 | * Here, we cover the first three conditions. | |
4300 | * The fourth is computed dynamically in permission_fault(); | |
4301 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4302 | * *not* subject to SMAP restrictions. | |
4303 | */ | |
4304 | if (cr4_smap) | |
4305 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4306 | } |
09f037aa PB |
4307 | |
4308 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4309 | } |
4310 | } | |
4311 | ||
2d344105 HH |
4312 | /* |
4313 | * PKU is an additional mechanism by which the paging controls access to | |
4314 | * user-mode addresses based on the value in the PKRU register. Protection | |
4315 | * key violations are reported through a bit in the page fault error code. | |
4316 | * Unlike other bits of the error code, the PK bit is not known at the | |
4317 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4318 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4319 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4320 | * | |
4321 | * In particular the following conditions come from the error code, the | |
4322 | * page tables and the machine state: | |
4323 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4324 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4325 | * - PK is always zero if U=0 in the page tables | |
4326 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4327 | * | |
4328 | * The PKRU bitmask caches the result of these four conditions. The error | |
4329 | * code (minus the P bit) and the page table's U bit form an index into the | |
4330 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4331 | * with the two bits of the PKRU register corresponding to the protection key. | |
4332 | * For the first three conditions above the bits will be 00, thus masking | |
4333 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4334 | * only will be masked away. | |
4335 | */ | |
4336 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4337 | bool ept) | |
4338 | { | |
4339 | unsigned bit; | |
4340 | bool wp; | |
4341 | ||
4342 | if (ept) { | |
4343 | mmu->pkru_mask = 0; | |
4344 | return; | |
4345 | } | |
4346 | ||
4347 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4348 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4349 | mmu->pkru_mask = 0; | |
4350 | return; | |
4351 | } | |
4352 | ||
4353 | wp = is_write_protection(vcpu); | |
4354 | ||
4355 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4356 | unsigned pfec, pkey_bits; | |
4357 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4358 | ||
4359 | pfec = bit << 1; | |
4360 | ff = pfec & PFERR_FETCH_MASK; | |
4361 | uf = pfec & PFERR_USER_MASK; | |
4362 | wf = pfec & PFERR_WRITE_MASK; | |
4363 | ||
4364 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4365 | pte_user = pfec & PFERR_RSVD_MASK; | |
4366 | ||
4367 | /* | |
4368 | * Only need to check the access which is not an | |
4369 | * instruction fetch and is to a user page. | |
4370 | */ | |
4371 | check_pkey = (!ff && pte_user); | |
4372 | /* | |
4373 | * write access is controlled by PKRU if it is a | |
4374 | * user access or CR0.WP = 1. | |
4375 | */ | |
4376 | check_write = check_pkey && wf && (uf || wp); | |
4377 | ||
4378 | /* PKRU.AD stops both read and write access. */ | |
4379 | pkey_bits = !!check_pkey; | |
4380 | /* PKRU.WD stops write access. */ | |
4381 | pkey_bits |= (!!check_write) << 1; | |
4382 | ||
4383 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4384 | } | |
4385 | } | |
4386 | ||
6bb69c9b | 4387 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4388 | { |
6bb69c9b PB |
4389 | unsigned root_level = mmu->root_level; |
4390 | ||
4391 | mmu->last_nonleaf_level = root_level; | |
4392 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4393 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4394 | } |
4395 | ||
8a3c1a33 PB |
4396 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4397 | struct kvm_mmu *context, | |
4398 | int level) | |
6aa8b732 | 4399 | { |
2d48a985 | 4400 | context->nx = is_nx(vcpu); |
4d6931c3 | 4401 | context->root_level = level; |
2d48a985 | 4402 | |
4d6931c3 | 4403 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4404 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4405 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4406 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4407 | |
fa4a2c08 | 4408 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4409 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4410 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4411 | context->sync_page = paging64_sync_page; |
a7052897 | 4412 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4413 | context->update_pte = paging64_update_pte; |
17ac10ad | 4414 | context->shadow_root_level = level; |
17c3ba9d | 4415 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4416 | context->direct_map = false; |
6aa8b732 AK |
4417 | } |
4418 | ||
8a3c1a33 PB |
4419 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4420 | struct kvm_mmu *context) | |
17ac10ad | 4421 | { |
855feb67 YZ |
4422 | int root_level = is_la57_mode(vcpu) ? |
4423 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4424 | ||
4425 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4426 | } |
4427 | ||
8a3c1a33 PB |
4428 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4429 | struct kvm_mmu *context) | |
6aa8b732 | 4430 | { |
2d48a985 | 4431 | context->nx = false; |
4d6931c3 | 4432 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4433 | |
4d6931c3 | 4434 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4435 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4436 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4437 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4438 | |
6aa8b732 | 4439 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4440 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4441 | context->sync_page = paging32_sync_page; |
a7052897 | 4442 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4443 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4444 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 4445 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4446 | context->direct_map = false; |
6aa8b732 AK |
4447 | } |
4448 | ||
8a3c1a33 PB |
4449 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4450 | struct kvm_mmu *context) | |
6aa8b732 | 4451 | { |
8a3c1a33 | 4452 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4453 | } |
4454 | ||
8a3c1a33 | 4455 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4456 | { |
ad896af0 | 4457 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4458 | |
c445f8ef | 4459 | context->base_role.word = 0; |
699023e2 | 4460 | context->base_role.smm = is_smm(vcpu); |
ac8d57e5 | 4461 | context->base_role.ad_disabled = (shadow_accessed_mask == 0); |
fb72d167 | 4462 | context->page_fault = tdp_page_fault; |
e8bc217a | 4463 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4464 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4465 | context->update_pte = nonpaging_update_pte; |
855feb67 | 4466 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu); |
fb72d167 | 4467 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4468 | context->direct_map = true; |
1c97f0a0 | 4469 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4470 | context->get_cr3 = get_cr3; |
e4e517b4 | 4471 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4472 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4473 | |
4474 | if (!is_paging(vcpu)) { | |
2d48a985 | 4475 | context->nx = false; |
fb72d167 JR |
4476 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4477 | context->root_level = 0; | |
4478 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4479 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4480 | context->root_level = is_la57_mode(vcpu) ? |
4481 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4482 | reset_rsvds_bits_mask(vcpu, context); |
4483 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4484 | } else if (is_pae(vcpu)) { |
2d48a985 | 4485 | context->nx = is_nx(vcpu); |
fb72d167 | 4486 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4487 | reset_rsvds_bits_mask(vcpu, context); |
4488 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4489 | } else { |
2d48a985 | 4490 | context->nx = false; |
fb72d167 | 4491 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4492 | reset_rsvds_bits_mask(vcpu, context); |
4493 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4494 | } |
4495 | ||
25d92081 | 4496 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4497 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4498 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4499 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4500 | } |
4501 | ||
ad896af0 | 4502 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4503 | { |
411c588d | 4504 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4505 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4506 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4507 | ||
fa4a2c08 | 4508 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4509 | |
4510 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4511 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4512 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4513 | paging64_init_context(vcpu, context); |
6aa8b732 | 4514 | else if (is_pae(vcpu)) |
8a3c1a33 | 4515 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4516 | else |
8a3c1a33 | 4517 | paging32_init_context(vcpu, context); |
a770f6f2 | 4518 | |
ad896af0 PB |
4519 | context->base_role.nxe = is_nx(vcpu); |
4520 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4521 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4522 | context->base_role.smep_andnot_wp | |
411c588d | 4523 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4524 | context->base_role.smap_andnot_wp |
4525 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4526 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4527 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4528 | } |
4529 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4530 | ||
ae1e2d10 PB |
4531 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
4532 | bool accessed_dirty) | |
155a97a3 | 4533 | { |
ad896af0 PB |
4534 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4535 | ||
fa4a2c08 | 4536 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 | 4537 | |
855feb67 | 4538 | context->shadow_root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4539 | |
4540 | context->nx = true; | |
ae1e2d10 | 4541 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4542 | context->page_fault = ept_page_fault; |
4543 | context->gva_to_gpa = ept_gva_to_gpa; | |
4544 | context->sync_page = ept_sync_page; | |
4545 | context->invlpg = ept_invlpg; | |
4546 | context->update_pte = ept_update_pte; | |
855feb67 | 4547 | context->root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4548 | context->root_hpa = INVALID_PAGE; |
4549 | context->direct_map = false; | |
995f00a6 | 4550 | context->base_role.ad_disabled = !accessed_dirty; |
155a97a3 NHE |
4551 | |
4552 | update_permission_bitmask(vcpu, context, true); | |
2d344105 | 4553 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4554 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4555 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4556 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4557 | } |
4558 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4559 | ||
8a3c1a33 | 4560 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4561 | { |
ad896af0 PB |
4562 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4563 | ||
4564 | kvm_init_shadow_mmu(vcpu); | |
4565 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4566 | context->get_cr3 = get_cr3; | |
4567 | context->get_pdptr = kvm_pdptr_read; | |
4568 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4569 | } |
4570 | ||
8a3c1a33 | 4571 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4572 | { |
4573 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4574 | ||
4575 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4576 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4577 | g_context->inject_page_fault = kvm_inject_page_fault; |
4578 | ||
4579 | /* | |
0af2593b DM |
4580 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4581 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4582 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4583 | * L2's page tables as the first level of translation and L1's | |
4584 | * nested page tables as the second level of translation. Basically | |
4585 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4586 | */ |
4587 | if (!is_paging(vcpu)) { | |
2d48a985 | 4588 | g_context->nx = false; |
02f59dc9 JR |
4589 | g_context->root_level = 0; |
4590 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4591 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4592 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4593 | g_context->root_level = is_la57_mode(vcpu) ? |
4594 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4595 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4596 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4597 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4598 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4599 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4600 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4601 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4602 | } else { | |
2d48a985 | 4603 | g_context->nx = false; |
02f59dc9 | 4604 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4605 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4606 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4607 | } | |
4608 | ||
25d92081 | 4609 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4610 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4611 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4612 | } |
4613 | ||
8a3c1a33 | 4614 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4615 | { |
02f59dc9 | 4616 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4617 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4618 | else if (tdp_enabled) |
e0c6db3e | 4619 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4620 | else |
e0c6db3e | 4621 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4622 | } |
4623 | ||
8a3c1a33 | 4624 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4625 | { |
95f93af4 | 4626 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4627 | init_kvm_mmu(vcpu); |
17c3ba9d | 4628 | } |
8668a3c4 | 4629 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4630 | |
4631 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4632 | { |
714b93da AK |
4633 | int r; |
4634 | ||
e2dec939 | 4635 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4636 | if (r) |
4637 | goto out; | |
8986ecc0 | 4638 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4639 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4640 | if (r) |
4641 | goto out; | |
3662cb1c | 4642 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4643 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4644 | out: |
4645 | return r; | |
6aa8b732 | 4646 | } |
17c3ba9d AK |
4647 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4648 | ||
4649 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4650 | { | |
4651 | mmu_free_roots(vcpu); | |
95f93af4 | 4652 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4653 | } |
4b16184c | 4654 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4655 | |
0028425f | 4656 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4657 | struct kvm_mmu_page *sp, u64 *spte, |
4658 | const void *new) | |
0028425f | 4659 | { |
30945387 | 4660 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4661 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4662 | return; | |
30945387 | 4663 | } |
0028425f | 4664 | |
4cee5764 | 4665 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4666 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4667 | } |
4668 | ||
79539cec AK |
4669 | static bool need_remote_flush(u64 old, u64 new) |
4670 | { | |
4671 | if (!is_shadow_present_pte(old)) | |
4672 | return false; | |
4673 | if (!is_shadow_present_pte(new)) | |
4674 | return true; | |
4675 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4676 | return true; | |
53166229 GN |
4677 | old ^= shadow_nx_mask; |
4678 | new ^= shadow_nx_mask; | |
79539cec AK |
4679 | return (old & ~new & PT64_PERM_MASK) != 0; |
4680 | } | |
4681 | ||
889e5cbc XG |
4682 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4683 | const u8 *new, int *bytes) | |
da4a00f0 | 4684 | { |
889e5cbc XG |
4685 | u64 gentry; |
4686 | int r; | |
72016f3a | 4687 | |
72016f3a AK |
4688 | /* |
4689 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4690 | * as the current vcpu paging mode since we update the sptes only |
4691 | * when they have the same mode. | |
72016f3a | 4692 | */ |
889e5cbc | 4693 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4694 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4695 | *gpa &= ~(gpa_t)7; |
4696 | *bytes = 8; | |
54bf36aa | 4697 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4698 | if (r) |
4699 | gentry = 0; | |
08e850c6 AK |
4700 | new = (const u8 *)&gentry; |
4701 | } | |
4702 | ||
889e5cbc | 4703 | switch (*bytes) { |
08e850c6 AK |
4704 | case 4: |
4705 | gentry = *(const u32 *)new; | |
4706 | break; | |
4707 | case 8: | |
4708 | gentry = *(const u64 *)new; | |
4709 | break; | |
4710 | default: | |
4711 | gentry = 0; | |
4712 | break; | |
72016f3a AK |
4713 | } |
4714 | ||
889e5cbc XG |
4715 | return gentry; |
4716 | } | |
4717 | ||
4718 | /* | |
4719 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4720 | * or we may be forking, in which case it is better to unmap the page. | |
4721 | */ | |
a138fe75 | 4722 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4723 | { |
a30f47cb XG |
4724 | /* |
4725 | * Skip write-flooding detected for the sp whose level is 1, because | |
4726 | * it can become unsync, then the guest page is not write-protected. | |
4727 | */ | |
f71fa31f | 4728 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4729 | return false; |
3246af0e | 4730 | |
e5691a81 XG |
4731 | atomic_inc(&sp->write_flooding_count); |
4732 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4733 | } |
4734 | ||
4735 | /* | |
4736 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4737 | * indicate a page is not used as a page table. | |
4738 | */ | |
4739 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4740 | int bytes) | |
4741 | { | |
4742 | unsigned offset, pte_size, misaligned; | |
4743 | ||
4744 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4745 | gpa, bytes, sp->role.word); | |
4746 | ||
4747 | offset = offset_in_page(gpa); | |
4748 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4749 | |
4750 | /* | |
4751 | * Sometimes, the OS only writes the last one bytes to update status | |
4752 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4753 | */ | |
4754 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4755 | return false; | |
4756 | ||
889e5cbc XG |
4757 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4758 | misaligned |= bytes < 4; | |
4759 | ||
4760 | return misaligned; | |
4761 | } | |
4762 | ||
4763 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4764 | { | |
4765 | unsigned page_offset, quadrant; | |
4766 | u64 *spte; | |
4767 | int level; | |
4768 | ||
4769 | page_offset = offset_in_page(gpa); | |
4770 | level = sp->role.level; | |
4771 | *nspte = 1; | |
4772 | if (!sp->role.cr4_pae) { | |
4773 | page_offset <<= 1; /* 32->64 */ | |
4774 | /* | |
4775 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4776 | * only 2MB. So we need to double the offset again | |
4777 | * and zap two pdes instead of one. | |
4778 | */ | |
4779 | if (level == PT32_ROOT_LEVEL) { | |
4780 | page_offset &= ~7; /* kill rounding error */ | |
4781 | page_offset <<= 1; | |
4782 | *nspte = 2; | |
4783 | } | |
4784 | quadrant = page_offset >> PAGE_SHIFT; | |
4785 | page_offset &= ~PAGE_MASK; | |
4786 | if (quadrant != sp->role.quadrant) | |
4787 | return NULL; | |
4788 | } | |
4789 | ||
4790 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4791 | return spte; | |
4792 | } | |
4793 | ||
13d268ca | 4794 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4795 | const u8 *new, int bytes, |
4796 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4797 | { |
4798 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4799 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4800 | LIST_HEAD(invalid_list); |
4801 | u64 entry, gentry, *spte; | |
4802 | int npte; | |
b8c67b7a | 4803 | bool remote_flush, local_flush; |
4141259b AM |
4804 | union kvm_mmu_page_role mask = { }; |
4805 | ||
4806 | mask.cr0_wp = 1; | |
4807 | mask.cr4_pae = 1; | |
4808 | mask.nxe = 1; | |
4809 | mask.smep_andnot_wp = 1; | |
4810 | mask.smap_andnot_wp = 1; | |
699023e2 | 4811 | mask.smm = 1; |
ac8d57e5 | 4812 | mask.ad_disabled = 1; |
889e5cbc XG |
4813 | |
4814 | /* | |
4815 | * If we don't have indirect shadow pages, it means no page is | |
4816 | * write-protected, so we can exit simply. | |
4817 | */ | |
6aa7de05 | 4818 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
4819 | return; |
4820 | ||
b8c67b7a | 4821 | remote_flush = local_flush = false; |
889e5cbc XG |
4822 | |
4823 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4824 | ||
4825 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4826 | ||
4827 | /* | |
4828 | * No need to care whether allocation memory is successful | |
4829 | * or not since pte prefetch is skiped if it does not have | |
4830 | * enough objects in the cache. | |
4831 | */ | |
4832 | mmu_topup_memory_caches(vcpu); | |
4833 | ||
4834 | spin_lock(&vcpu->kvm->mmu_lock); | |
4835 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4836 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4837 | |
b67bfe0d | 4838 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4839 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4840 | detect_write_flooding(sp)) { |
b8c67b7a | 4841 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4842 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4843 | continue; |
4844 | } | |
889e5cbc XG |
4845 | |
4846 | spte = get_written_sptes(sp, gpa, &npte); | |
4847 | if (!spte) | |
4848 | continue; | |
4849 | ||
0671a8e7 | 4850 | local_flush = true; |
ac1b714e | 4851 | while (npte--) { |
79539cec | 4852 | entry = *spte; |
38e3b2b2 | 4853 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4854 | if (gentry && |
4855 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4856 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4857 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4858 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4859 | remote_flush = true; |
ac1b714e | 4860 | ++spte; |
9b7a0325 | 4861 | } |
9b7a0325 | 4862 | } |
b8c67b7a | 4863 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4864 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4865 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4866 | } |
4867 | ||
a436036b AK |
4868 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4869 | { | |
10589a46 MT |
4870 | gpa_t gpa; |
4871 | int r; | |
a436036b | 4872 | |
c5a78f2b | 4873 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4874 | return 0; |
4875 | ||
1871c602 | 4876 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4877 | |
10589a46 | 4878 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4879 | |
10589a46 | 4880 | return r; |
a436036b | 4881 | } |
577bdc49 | 4882 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4883 | |
26eeb53c | 4884 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4885 | { |
d98ba053 | 4886 | LIST_HEAD(invalid_list); |
103ad25a | 4887 | |
81f4f76b | 4888 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 4889 | return 0; |
81f4f76b | 4890 | |
5da59607 TY |
4891 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4892 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4893 | break; | |
ebeace86 | 4894 | |
4cee5764 | 4895 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4896 | } |
aa6bd187 | 4897 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
4898 | |
4899 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
4900 | return -ENOSPC; | |
4901 | return 0; | |
ebeace86 | 4902 | } |
ebeace86 | 4903 | |
14727754 | 4904 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 4905 | void *insn, int insn_len) |
3067714c | 4906 | { |
1cb3f3ae | 4907 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4908 | enum emulation_result er; |
9034e6e8 | 4909 | bool direct = vcpu->arch.mmu.direct_map; |
3067714c | 4910 | |
618232e2 BS |
4911 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
4912 | if (vcpu->arch.mmu.direct_map) { | |
4913 | vcpu->arch.gpa_available = true; | |
4914 | vcpu->arch.gpa_val = cr2; | |
4915 | } | |
3067714c | 4916 | |
9b8ebbdb | 4917 | r = RET_PF_INVALID; |
e9ee956e TY |
4918 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4919 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
9b8ebbdb | 4920 | if (r == RET_PF_EMULATE) { |
e9ee956e TY |
4921 | emulation_type = 0; |
4922 | goto emulate; | |
4923 | } | |
e9ee956e | 4924 | } |
3067714c | 4925 | |
9b8ebbdb PB |
4926 | if (r == RET_PF_INVALID) { |
4927 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code), | |
4928 | false); | |
4929 | WARN_ON(r == RET_PF_INVALID); | |
4930 | } | |
4931 | ||
4932 | if (r == RET_PF_RETRY) | |
4933 | return 1; | |
3067714c | 4934 | if (r < 0) |
e9ee956e | 4935 | return r; |
3067714c | 4936 | |
14727754 TL |
4937 | /* |
4938 | * Before emulating the instruction, check if the error code | |
4939 | * was due to a RO violation while translating the guest page. | |
4940 | * This can occur when using nested virtualization with nested | |
4941 | * paging in both guests. If true, we simply unprotect the page | |
4942 | * and resume the guest. | |
14727754 | 4943 | */ |
64531a3b | 4944 | if (vcpu->arch.mmu.direct_map && |
eebed243 | 4945 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
4946 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
4947 | return 1; | |
4948 | } | |
4949 | ||
ded58749 | 4950 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4951 | emulation_type = 0; |
e9ee956e | 4952 | emulate: |
1cb3f3ae | 4953 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4954 | |
4955 | switch (er) { | |
4956 | case EMULATE_DONE: | |
4957 | return 1; | |
ac0a48c3 | 4958 | case EMULATE_USER_EXIT: |
3067714c | 4959 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4960 | /* fall through */ |
3067714c | 4961 | case EMULATE_FAIL: |
3f5d18a9 | 4962 | return 0; |
3067714c AK |
4963 | default: |
4964 | BUG(); | |
4965 | } | |
3067714c AK |
4966 | } |
4967 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4968 | ||
a7052897 MT |
4969 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4970 | { | |
a7052897 | 4971 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4972 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4973 | ++vcpu->stat.invlpg; |
4974 | } | |
4975 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4976 | ||
18552672 JR |
4977 | void kvm_enable_tdp(void) |
4978 | { | |
4979 | tdp_enabled = true; | |
4980 | } | |
4981 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4982 | ||
5f4cb662 JR |
4983 | void kvm_disable_tdp(void) |
4984 | { | |
4985 | tdp_enabled = false; | |
4986 | } | |
4987 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4988 | ||
6aa8b732 AK |
4989 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4990 | { | |
ad312c7c | 4991 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
87ca74ad | 4992 | free_page((unsigned long)vcpu->arch.mmu.lm_root); |
6aa8b732 AK |
4993 | } |
4994 | ||
4995 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4996 | { | |
17ac10ad | 4997 | struct page *page; |
6aa8b732 AK |
4998 | int i; |
4999 | ||
17ac10ad AK |
5000 | /* |
5001 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
5002 | * Therefore we need to allocate shadow page tables in the first | |
5003 | * 4GB of memory, which happens to fit the DMA32 zone. | |
5004 | */ | |
5005 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
5006 | if (!page) | |
d7fa6ab2 WY |
5007 | return -ENOMEM; |
5008 | ||
ad312c7c | 5009 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 5010 | for (i = 0; i < 4; ++i) |
ad312c7c | 5011 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 5012 | |
6aa8b732 | 5013 | return 0; |
6aa8b732 AK |
5014 | } |
5015 | ||
8018c27b | 5016 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5017 | { |
e459e322 XG |
5018 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
5019 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
5020 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
5021 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 5022 | |
8018c27b IM |
5023 | return alloc_mmu_pages(vcpu); |
5024 | } | |
6aa8b732 | 5025 | |
8a3c1a33 | 5026 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 5027 | { |
fa4a2c08 | 5028 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 5029 | |
8a3c1a33 | 5030 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
5031 | } |
5032 | ||
b5f5fdca | 5033 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5034 | struct kvm_memory_slot *slot, |
5035 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
5036 | { |
5037 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
5038 | } | |
5039 | ||
13d268ca XG |
5040 | void kvm_mmu_init_vm(struct kvm *kvm) |
5041 | { | |
5042 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5043 | ||
5044 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 5045 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
5046 | kvm_page_track_register_notifier(kvm, node); |
5047 | } | |
5048 | ||
5049 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
5050 | { | |
5051 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5052 | ||
5053 | kvm_page_track_unregister_notifier(kvm, node); | |
5054 | } | |
5055 | ||
1bad2b2a | 5056 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 5057 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
5058 | |
5059 | /* The caller should hold mmu-lock before calling this function. */ | |
5060 | static bool | |
5061 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5062 | slot_level_handler fn, int start_level, int end_level, | |
5063 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5064 | { | |
5065 | struct slot_rmap_walk_iterator iterator; | |
5066 | bool flush = false; | |
5067 | ||
5068 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5069 | end_gfn, &iterator) { | |
5070 | if (iterator.rmap) | |
5071 | flush |= fn(kvm, iterator.rmap); | |
5072 | ||
5073 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5074 | if (flush && lock_flush_tlb) { | |
5075 | kvm_flush_remote_tlbs(kvm); | |
5076 | flush = false; | |
5077 | } | |
5078 | cond_resched_lock(&kvm->mmu_lock); | |
5079 | } | |
5080 | } | |
5081 | ||
5082 | if (flush && lock_flush_tlb) { | |
5083 | kvm_flush_remote_tlbs(kvm); | |
5084 | flush = false; | |
5085 | } | |
5086 | ||
5087 | return flush; | |
5088 | } | |
5089 | ||
5090 | static bool | |
5091 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5092 | slot_level_handler fn, int start_level, int end_level, | |
5093 | bool lock_flush_tlb) | |
5094 | { | |
5095 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5096 | end_level, memslot->base_gfn, | |
5097 | memslot->base_gfn + memslot->npages - 1, | |
5098 | lock_flush_tlb); | |
5099 | } | |
5100 | ||
5101 | static bool | |
5102 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5103 | slot_level_handler fn, bool lock_flush_tlb) | |
5104 | { | |
5105 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5106 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5107 | } | |
5108 | ||
5109 | static bool | |
5110 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5111 | slot_level_handler fn, bool lock_flush_tlb) | |
5112 | { | |
5113 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5114 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5115 | } | |
5116 | ||
5117 | static bool | |
5118 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5119 | slot_level_handler fn, bool lock_flush_tlb) | |
5120 | { | |
5121 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5122 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5123 | } | |
5124 | ||
efdfe536 XG |
5125 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5126 | { | |
5127 | struct kvm_memslots *slots; | |
5128 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5129 | int i; |
efdfe536 XG |
5130 | |
5131 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5132 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5133 | slots = __kvm_memslots(kvm, i); | |
5134 | kvm_for_each_memslot(memslot, slots) { | |
5135 | gfn_t start, end; | |
5136 | ||
5137 | start = max(gfn_start, memslot->base_gfn); | |
5138 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5139 | if (start >= end) | |
5140 | continue; | |
efdfe536 | 5141 | |
9da0e4d5 PB |
5142 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
5143 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
5144 | start, end - 1, true); | |
5145 | } | |
efdfe536 XG |
5146 | } |
5147 | ||
5148 | spin_unlock(&kvm->mmu_lock); | |
5149 | } | |
5150 | ||
018aabb5 TY |
5151 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5152 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5153 | { |
018aabb5 | 5154 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5155 | } |
5156 | ||
1c91cad4 KH |
5157 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5158 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5159 | { |
d77aa73c | 5160 | bool flush; |
6aa8b732 | 5161 | |
9d1beefb | 5162 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5163 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5164 | false); | |
9d1beefb | 5165 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5166 | |
5167 | /* | |
5168 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5169 | * which do tlb flush out of mmu-lock should be serialized by | |
5170 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5171 | */ | |
5172 | lockdep_assert_held(&kvm->slots_lock); | |
5173 | ||
5174 | /* | |
5175 | * We can flush all the TLBs out of the mmu lock without TLB | |
5176 | * corruption since we just change the spte from writable to | |
5177 | * readonly so that we only need to care the case of changing | |
5178 | * spte from present to present (changing the spte from present | |
5179 | * to nonpresent will flush all the TLBs immediately), in other | |
5180 | * words, the only case we care is mmu_spte_update() where we | |
5181 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
5182 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
5183 | * on PT_WRITABLE_MASK anymore. | |
5184 | */ | |
d91ffee9 KH |
5185 | if (flush) |
5186 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 5187 | } |
37a7d8b0 | 5188 | |
3ea3b7fa | 5189 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5190 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5191 | { |
5192 | u64 *sptep; | |
5193 | struct rmap_iterator iter; | |
5194 | int need_tlb_flush = 0; | |
ba049e93 | 5195 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5196 | struct kvm_mmu_page *sp; |
5197 | ||
0d536790 | 5198 | restart: |
018aabb5 | 5199 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5200 | sp = page_header(__pa(sptep)); |
5201 | pfn = spte_to_pfn(*sptep); | |
5202 | ||
5203 | /* | |
decf6333 XG |
5204 | * We cannot do huge page mapping for indirect shadow pages, |
5205 | * which are found on the last rmap (level = 1) when not using | |
5206 | * tdp; such shadow pages are synced with the page table in | |
5207 | * the guest, and the guest page table is using 4K page size | |
5208 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5209 | */ |
5210 | if (sp->role.direct && | |
5211 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5212 | PageTransCompoundMap(pfn_to_page(pfn))) { |
3ea3b7fa | 5213 | drop_spte(kvm, sptep); |
3ea3b7fa | 5214 | need_tlb_flush = 1; |
0d536790 XG |
5215 | goto restart; |
5216 | } | |
3ea3b7fa WL |
5217 | } |
5218 | ||
5219 | return need_tlb_flush; | |
5220 | } | |
5221 | ||
5222 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5223 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5224 | { |
f36f3f28 | 5225 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5226 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5227 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5228 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5229 | spin_unlock(&kvm->mmu_lock); |
5230 | } | |
5231 | ||
f4b4b180 KH |
5232 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5233 | struct kvm_memory_slot *memslot) | |
5234 | { | |
d77aa73c | 5235 | bool flush; |
f4b4b180 KH |
5236 | |
5237 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5238 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5239 | spin_unlock(&kvm->mmu_lock); |
5240 | ||
5241 | lockdep_assert_held(&kvm->slots_lock); | |
5242 | ||
5243 | /* | |
5244 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5245 | * function is only used for dirty logging, in which case flushing TLB | |
5246 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5247 | * dirty_bitmap. | |
5248 | */ | |
5249 | if (flush) | |
5250 | kvm_flush_remote_tlbs(kvm); | |
5251 | } | |
5252 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5253 | ||
5254 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5255 | struct kvm_memory_slot *memslot) | |
5256 | { | |
d77aa73c | 5257 | bool flush; |
f4b4b180 KH |
5258 | |
5259 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5260 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5261 | false); | |
f4b4b180 KH |
5262 | spin_unlock(&kvm->mmu_lock); |
5263 | ||
5264 | /* see kvm_mmu_slot_remove_write_access */ | |
5265 | lockdep_assert_held(&kvm->slots_lock); | |
5266 | ||
5267 | if (flush) | |
5268 | kvm_flush_remote_tlbs(kvm); | |
5269 | } | |
5270 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5271 | ||
5272 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5273 | struct kvm_memory_slot *memslot) | |
5274 | { | |
d77aa73c | 5275 | bool flush; |
f4b4b180 KH |
5276 | |
5277 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5278 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5279 | spin_unlock(&kvm->mmu_lock); |
5280 | ||
5281 | lockdep_assert_held(&kvm->slots_lock); | |
5282 | ||
5283 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5284 | if (flush) | |
5285 | kvm_flush_remote_tlbs(kvm); | |
5286 | } | |
5287 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5288 | ||
e7d11c7a | 5289 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5290 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5291 | { | |
5292 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5293 | int batch = 0; |
5304b8d3 XG |
5294 | |
5295 | restart: | |
5296 | list_for_each_entry_safe_reverse(sp, node, | |
5297 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5298 | int ret; |
5299 | ||
5304b8d3 XG |
5300 | /* |
5301 | * No obsolete page exists before new created page since | |
5302 | * active_mmu_pages is the FIFO list. | |
5303 | */ | |
5304 | if (!is_obsolete_sp(kvm, sp)) | |
5305 | break; | |
5306 | ||
5307 | /* | |
5304b8d3 XG |
5308 | * Since we are reversely walking the list and the invalid |
5309 | * list will be moved to the head, skip the invalid page | |
5310 | * can help us to avoid the infinity list walking. | |
5311 | */ | |
5312 | if (sp->role.invalid) | |
5313 | continue; | |
5314 | ||
f34d251d XG |
5315 | /* |
5316 | * Need not flush tlb since we only zap the sp with invalid | |
5317 | * generation number. | |
5318 | */ | |
e7d11c7a | 5319 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5320 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5321 | batch = 0; |
5304b8d3 XG |
5322 | goto restart; |
5323 | } | |
5324 | ||
365c8868 XG |
5325 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5326 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5327 | batch += ret; |
5328 | ||
5329 | if (ret) | |
5304b8d3 XG |
5330 | goto restart; |
5331 | } | |
5332 | ||
f34d251d XG |
5333 | /* |
5334 | * Should flush tlb before free page tables since lockless-walking | |
5335 | * may use the pages. | |
5336 | */ | |
365c8868 | 5337 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5338 | } |
5339 | ||
5340 | /* | |
5341 | * Fast invalidate all shadow pages and use lock-break technique | |
5342 | * to zap obsolete pages. | |
5343 | * | |
5344 | * It's required when memslot is being deleted or VM is being | |
5345 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5346 | * not use any resource of the being-deleted slot or all slots | |
5347 | * after calling the function. | |
5348 | */ | |
5349 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5350 | { | |
5351 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5352 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5353 | kvm->arch.mmu_valid_gen++; |
5354 | ||
f34d251d XG |
5355 | /* |
5356 | * Notify all vcpus to reload its shadow page table | |
5357 | * and flush TLB. Then all vcpus will switch to new | |
5358 | * shadow page table with the new mmu_valid_gen. | |
5359 | * | |
5360 | * Note: we should do this under the protection of | |
5361 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5362 | * but miss tlb flush. | |
5363 | */ | |
5364 | kvm_reload_remote_mmus(kvm); | |
5365 | ||
5304b8d3 XG |
5366 | kvm_zap_obsolete_pages(kvm); |
5367 | spin_unlock(&kvm->mmu_lock); | |
5368 | } | |
5369 | ||
365c8868 XG |
5370 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5371 | { | |
5372 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5373 | } | |
5374 | ||
54bf36aa | 5375 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5376 | { |
5377 | /* | |
5378 | * The very rare case: if the generation-number is round, | |
5379 | * zap all shadow pages. | |
f8f55942 | 5380 | */ |
54bf36aa | 5381 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5382 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5383 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5384 | } |
f8f55942 XG |
5385 | } |
5386 | ||
70534a73 DC |
5387 | static unsigned long |
5388 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5389 | { |
5390 | struct kvm *kvm; | |
1495f230 | 5391 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5392 | unsigned long freed = 0; |
3ee16c81 | 5393 | |
2f303b74 | 5394 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5395 | |
5396 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5397 | int idx; |
d98ba053 | 5398 | LIST_HEAD(invalid_list); |
3ee16c81 | 5399 | |
35f2d16b TY |
5400 | /* |
5401 | * Never scan more than sc->nr_to_scan VM instances. | |
5402 | * Will not hit this condition practically since we do not try | |
5403 | * to shrink more than one VM and it is very unlikely to see | |
5404 | * !n_used_mmu_pages so many times. | |
5405 | */ | |
5406 | if (!nr_to_scan--) | |
5407 | break; | |
19526396 GN |
5408 | /* |
5409 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5410 | * here. We may skip a VM instance errorneosly, but we do not | |
5411 | * want to shrink a VM that only started to populate its MMU | |
5412 | * anyway. | |
5413 | */ | |
365c8868 XG |
5414 | if (!kvm->arch.n_used_mmu_pages && |
5415 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5416 | continue; |
19526396 | 5417 | |
f656ce01 | 5418 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5419 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5420 | |
365c8868 XG |
5421 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5422 | kvm_mmu_commit_zap_page(kvm, | |
5423 | &kvm->arch.zapped_obsolete_pages); | |
5424 | goto unlock; | |
5425 | } | |
5426 | ||
70534a73 DC |
5427 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5428 | freed++; | |
d98ba053 | 5429 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5430 | |
365c8868 | 5431 | unlock: |
3ee16c81 | 5432 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5433 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5434 | |
70534a73 DC |
5435 | /* |
5436 | * unfair on small ones | |
5437 | * per-vm shrinkers cry out | |
5438 | * sadness comes quickly | |
5439 | */ | |
19526396 GN |
5440 | list_move_tail(&kvm->vm_list, &vm_list); |
5441 | break; | |
3ee16c81 | 5442 | } |
3ee16c81 | 5443 | |
2f303b74 | 5444 | spin_unlock(&kvm_lock); |
70534a73 | 5445 | return freed; |
70534a73 DC |
5446 | } |
5447 | ||
5448 | static unsigned long | |
5449 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5450 | { | |
45221ab6 | 5451 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5452 | } |
5453 | ||
5454 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5455 | .count_objects = mmu_shrink_count, |
5456 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5457 | .seeks = DEFAULT_SEEKS * 10, |
5458 | }; | |
5459 | ||
2ddfd20e | 5460 | static void mmu_destroy_caches(void) |
b5a33a75 | 5461 | { |
c1bd743e TH |
5462 | kmem_cache_destroy(pte_list_desc_cache); |
5463 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5464 | } |
5465 | ||
5466 | int kvm_mmu_module_init(void) | |
5467 | { | |
f160c7b7 JS |
5468 | kvm_mmu_clear_all_pte_masks(); |
5469 | ||
53c07b18 XG |
5470 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5471 | sizeof(struct pte_list_desc), | |
46bea48a | 5472 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5473 | if (!pte_list_desc_cache) |
b5a33a75 AK |
5474 | goto nomem; |
5475 | ||
d3d25b04 AK |
5476 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5477 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5478 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 AK |
5479 | if (!mmu_page_header_cache) |
5480 | goto nomem; | |
5481 | ||
908c7f19 | 5482 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
5483 | goto nomem; |
5484 | ||
3ee16c81 IE |
5485 | register_shrinker(&mmu_shrinker); |
5486 | ||
b5a33a75 AK |
5487 | return 0; |
5488 | ||
5489 | nomem: | |
3ee16c81 | 5490 | mmu_destroy_caches(); |
b5a33a75 AK |
5491 | return -ENOMEM; |
5492 | } | |
5493 | ||
3ad82a7e ZX |
5494 | /* |
5495 | * Caculate mmu pages needed for kvm. | |
5496 | */ | |
5497 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5498 | { | |
3ad82a7e ZX |
5499 | unsigned int nr_mmu_pages; |
5500 | unsigned int nr_pages = 0; | |
bc6678a3 | 5501 | struct kvm_memslots *slots; |
be6ba0f0 | 5502 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5503 | int i; |
3ad82a7e | 5504 | |
9da0e4d5 PB |
5505 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5506 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5507 | |
9da0e4d5 PB |
5508 | kvm_for_each_memslot(memslot, slots) |
5509 | nr_pages += memslot->npages; | |
5510 | } | |
3ad82a7e ZX |
5511 | |
5512 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5513 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5514 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5515 | |
5516 | return nr_mmu_pages; | |
5517 | } | |
5518 | ||
c42fffe3 XG |
5519 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5520 | { | |
95f93af4 | 5521 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5522 | free_mmu_pages(vcpu); |
5523 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5524 | } |
5525 | ||
b034cf01 XG |
5526 | void kvm_mmu_module_exit(void) |
5527 | { | |
5528 | mmu_destroy_caches(); | |
5529 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5530 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5531 | mmu_audit_disable(); |
5532 | } |