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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 113 | |
6aa8b732 AK |
114 | #define PT64_INDEX(address, level)\ |
115 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
118 | #define PT32_LEVEL_BITS 10 | |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
27aba766 | 131 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
132 | #define PT64_DIR_BASE_ADDR_MASK \ |
133 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT64_LVL_ADDR_MASK(level) \ |
135 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT64_LEVEL_BITS))) - 1)) | |
137 | #define PT64_LVL_OFFSET_MASK(level) \ | |
138 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
140 | |
141 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
142 | #define PT32_DIR_BASE_ADDR_MASK \ | |
143 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
144 | #define PT32_LVL_ADDR_MASK(level) \ |
145 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
146 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 147 | |
79539cec AK |
148 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
149 | | PT64_NX_MASK) | |
6aa8b732 | 150 | |
cd4a4e53 AK |
151 | #define RMAP_EXT 4 |
152 | ||
fe135d2c AK |
153 | #define ACC_EXEC_MASK 1 |
154 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
155 | #define ACC_USER_MASK PT_USER_MASK | |
156 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
157 | ||
90bb6fc5 AK |
158 | #include <trace/events/kvm.h> |
159 | ||
07420171 AK |
160 | #define CREATE_TRACE_POINTS |
161 | #include "mmutrace.h" | |
162 | ||
1403283a IE |
163 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
164 | ||
135f8c2b AK |
165 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
166 | ||
cd4a4e53 | 167 | struct kvm_rmap_desc { |
d555c333 | 168 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
169 | struct kvm_rmap_desc *more; |
170 | }; | |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
175 | int level; | |
176 | u64 *sptep; | |
177 | unsigned index; | |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
1047df1f | 185 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 186 | |
b5a33a75 AK |
187 | static struct kmem_cache *pte_chain_cache; |
188 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 189 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 190 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 191 | |
c7addb90 AK |
192 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
193 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
194 | static u64 __read_mostly shadow_nx_mask; |
195 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
196 | static u64 __read_mostly shadow_user_mask; | |
197 | static u64 __read_mostly shadow_accessed_mask; | |
198 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 199 | |
82725b20 DE |
200 | static inline u64 rsvd_bits(int s, int e) |
201 | { | |
202 | return ((1ULL << (e - s + 1)) - 1) << s; | |
203 | } | |
204 | ||
c7addb90 AK |
205 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
206 | { | |
207 | shadow_trap_nonpresent_pte = trap_pte; | |
208 | shadow_notrap_nonpresent_pte = notrap_pte; | |
209 | } | |
210 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
211 | ||
7b52345e | 212 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 213 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
214 | { |
215 | shadow_user_mask = user_mask; | |
216 | shadow_accessed_mask = accessed_mask; | |
217 | shadow_dirty_mask = dirty_mask; | |
218 | shadow_nx_mask = nx_mask; | |
219 | shadow_x_mask = x_mask; | |
220 | } | |
221 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
222 | ||
3dbe1415 | 223 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 224 | { |
4d4ec087 | 225 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
226 | } |
227 | ||
228 | static int is_cpuid_PSE36(void) | |
229 | { | |
230 | return 1; | |
231 | } | |
232 | ||
73b1087e AK |
233 | static int is_nx(struct kvm_vcpu *vcpu) |
234 | { | |
f6801dff | 235 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
236 | } |
237 | ||
c7addb90 AK |
238 | static int is_shadow_present_pte(u64 pte) |
239 | { | |
c7addb90 AK |
240 | return pte != shadow_trap_nonpresent_pte |
241 | && pte != shadow_notrap_nonpresent_pte; | |
242 | } | |
243 | ||
05da4558 MT |
244 | static int is_large_pte(u64 pte) |
245 | { | |
246 | return pte & PT_PAGE_SIZE_MASK; | |
247 | } | |
248 | ||
8dae4445 | 249 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
250 | { |
251 | return pte & PT_WRITABLE_MASK; | |
252 | } | |
253 | ||
43a3795a | 254 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 255 | { |
439e218a | 256 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
257 | } |
258 | ||
43a3795a | 259 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 260 | { |
4b1a80fa | 261 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
262 | } |
263 | ||
776e6633 MT |
264 | static int is_last_spte(u64 pte, int level) |
265 | { | |
266 | if (level == PT_PAGE_TABLE_LEVEL) | |
267 | return 1; | |
852e3c19 | 268 | if (is_large_pte(pte)) |
776e6633 MT |
269 | return 1; |
270 | return 0; | |
271 | } | |
272 | ||
35149e21 | 273 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 274 | { |
35149e21 | 275 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
276 | } |
277 | ||
da928521 AK |
278 | static gfn_t pse36_gfn_delta(u32 gpte) |
279 | { | |
280 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
281 | ||
282 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
283 | } | |
284 | ||
d555c333 | 285 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 286 | { |
7645e432 | 287 | set_64bit(sptep, spte); |
e663ee64 AK |
288 | } |
289 | ||
a9221dd5 AK |
290 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
291 | { | |
292 | #ifdef CONFIG_X86_64 | |
293 | return xchg(sptep, new_spte); | |
294 | #else | |
295 | u64 old_spte; | |
296 | ||
297 | do { | |
298 | old_spte = *sptep; | |
299 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
300 | ||
301 | return old_spte; | |
302 | #endif | |
303 | } | |
304 | ||
8672b721 XG |
305 | static bool spte_has_volatile_bits(u64 spte) |
306 | { | |
307 | if (!shadow_accessed_mask) | |
308 | return false; | |
309 | ||
310 | if (!is_shadow_present_pte(spte)) | |
311 | return false; | |
312 | ||
4132779b XG |
313 | if ((spte & shadow_accessed_mask) && |
314 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
315 | return false; |
316 | ||
317 | return true; | |
318 | } | |
319 | ||
4132779b XG |
320 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
321 | { | |
322 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
323 | } | |
324 | ||
b79b93f9 AK |
325 | static void update_spte(u64 *sptep, u64 new_spte) |
326 | { | |
4132779b XG |
327 | u64 mask, old_spte = *sptep; |
328 | ||
329 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 330 | |
4132779b XG |
331 | new_spte |= old_spte & shadow_dirty_mask; |
332 | ||
333 | mask = shadow_accessed_mask; | |
334 | if (is_writable_pte(old_spte)) | |
335 | mask |= shadow_dirty_mask; | |
336 | ||
337 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 338 | __set_spte(sptep, new_spte); |
4132779b | 339 | else |
b79b93f9 | 340 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
341 | |
342 | if (!shadow_accessed_mask) | |
343 | return; | |
344 | ||
345 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
346 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
347 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
348 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
349 | } |
350 | ||
e2dec939 | 351 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 352 | struct kmem_cache *base_cache, int min) |
714b93da AK |
353 | { |
354 | void *obj; | |
355 | ||
356 | if (cache->nobjs >= min) | |
e2dec939 | 357 | return 0; |
714b93da | 358 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 359 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 360 | if (!obj) |
e2dec939 | 361 | return -ENOMEM; |
714b93da AK |
362 | cache->objects[cache->nobjs++] = obj; |
363 | } | |
e2dec939 | 364 | return 0; |
714b93da AK |
365 | } |
366 | ||
e8ad9a70 XG |
367 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
368 | struct kmem_cache *cache) | |
714b93da AK |
369 | { |
370 | while (mc->nobjs) | |
e8ad9a70 | 371 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
372 | } |
373 | ||
c1158e63 | 374 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 375 | int min) |
c1158e63 | 376 | { |
842f22ed | 377 | void *page; |
c1158e63 AK |
378 | |
379 | if (cache->nobjs >= min) | |
380 | return 0; | |
381 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 382 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
383 | if (!page) |
384 | return -ENOMEM; | |
842f22ed | 385 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
386 | } |
387 | return 0; | |
388 | } | |
389 | ||
390 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
391 | { | |
392 | while (mc->nobjs) | |
c4d198d5 | 393 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
394 | } |
395 | ||
2e3e5882 | 396 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 397 | { |
e2dec939 AK |
398 | int r; |
399 | ||
ad312c7c | 400 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 401 | pte_chain_cache, 4); |
e2dec939 AK |
402 | if (r) |
403 | goto out; | |
ad312c7c | 404 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
957ed9ef | 405 | rmap_desc_cache, 4 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
406 | if (r) |
407 | goto out; | |
ad312c7c | 408 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
409 | if (r) |
410 | goto out; | |
ad312c7c | 411 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 412 | mmu_page_header_cache, 4); |
e2dec939 AK |
413 | out: |
414 | return r; | |
714b93da AK |
415 | } |
416 | ||
417 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
418 | { | |
e8ad9a70 XG |
419 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
420 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 421 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
422 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
423 | mmu_page_header_cache); | |
714b93da AK |
424 | } |
425 | ||
426 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
427 | size_t size) | |
428 | { | |
429 | void *p; | |
430 | ||
431 | BUG_ON(!mc->nobjs); | |
432 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
433 | return p; |
434 | } | |
435 | ||
714b93da AK |
436 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
437 | { | |
ad312c7c | 438 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
439 | sizeof(struct kvm_pte_chain)); |
440 | } | |
441 | ||
90cb0529 | 442 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 443 | { |
e8ad9a70 | 444 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
445 | } |
446 | ||
447 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
448 | { | |
ad312c7c | 449 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
450 | sizeof(struct kvm_rmap_desc)); |
451 | } | |
452 | ||
90cb0529 | 453 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 454 | { |
e8ad9a70 | 455 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
456 | } |
457 | ||
2032a93d LJ |
458 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
459 | { | |
460 | if (!sp->role.direct) | |
461 | return sp->gfns[index]; | |
462 | ||
463 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
464 | } | |
465 | ||
466 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
467 | { | |
468 | if (sp->role.direct) | |
469 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
470 | else | |
471 | sp->gfns[index] = gfn; | |
472 | } | |
473 | ||
05da4558 | 474 | /* |
d4dbf470 TY |
475 | * Return the pointer to the large page information for a given gfn, |
476 | * handling slots that are not large page aligned. | |
05da4558 | 477 | */ |
d4dbf470 TY |
478 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
479 | struct kvm_memory_slot *slot, | |
480 | int level) | |
05da4558 MT |
481 | { |
482 | unsigned long idx; | |
483 | ||
82855413 JR |
484 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
485 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d4dbf470 | 486 | return &slot->lpage_info[level - 2][idx]; |
05da4558 MT |
487 | } |
488 | ||
489 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
490 | { | |
d25797b2 | 491 | struct kvm_memory_slot *slot; |
d4dbf470 | 492 | struct kvm_lpage_info *linfo; |
d25797b2 | 493 | int i; |
05da4558 | 494 | |
a1f4d395 | 495 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
496 | for (i = PT_DIRECTORY_LEVEL; |
497 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
498 | linfo = lpage_info_slot(gfn, slot, i); |
499 | linfo->write_count += 1; | |
d25797b2 | 500 | } |
05da4558 MT |
501 | } |
502 | ||
503 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
504 | { | |
d25797b2 | 505 | struct kvm_memory_slot *slot; |
d4dbf470 | 506 | struct kvm_lpage_info *linfo; |
d25797b2 | 507 | int i; |
05da4558 | 508 | |
a1f4d395 | 509 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
510 | for (i = PT_DIRECTORY_LEVEL; |
511 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
512 | linfo = lpage_info_slot(gfn, slot, i); |
513 | linfo->write_count -= 1; | |
514 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 515 | } |
05da4558 MT |
516 | } |
517 | ||
d25797b2 JR |
518 | static int has_wrprotected_page(struct kvm *kvm, |
519 | gfn_t gfn, | |
520 | int level) | |
05da4558 | 521 | { |
2843099f | 522 | struct kvm_memory_slot *slot; |
d4dbf470 | 523 | struct kvm_lpage_info *linfo; |
05da4558 | 524 | |
a1f4d395 | 525 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 526 | if (slot) { |
d4dbf470 TY |
527 | linfo = lpage_info_slot(gfn, slot, level); |
528 | return linfo->write_count; | |
05da4558 MT |
529 | } |
530 | ||
531 | return 1; | |
532 | } | |
533 | ||
d25797b2 | 534 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 535 | { |
8f0b1ab6 | 536 | unsigned long page_size; |
d25797b2 | 537 | int i, ret = 0; |
05da4558 | 538 | |
8f0b1ab6 | 539 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 540 | |
d25797b2 JR |
541 | for (i = PT_PAGE_TABLE_LEVEL; |
542 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
543 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
544 | ret = i; | |
545 | else | |
546 | break; | |
547 | } | |
548 | ||
4c2155ce | 549 | return ret; |
05da4558 MT |
550 | } |
551 | ||
5d163b1c XG |
552 | static struct kvm_memory_slot * |
553 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
554 | bool no_dirty_log) | |
05da4558 MT |
555 | { |
556 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
557 | |
558 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
559 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
560 | (no_dirty_log && slot->dirty_bitmap)) | |
561 | slot = NULL; | |
562 | ||
563 | return slot; | |
564 | } | |
565 | ||
566 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
567 | { | |
568 | return gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); | |
936a5fe6 AA |
569 | } |
570 | ||
571 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
572 | { | |
573 | int host_level, level, max_level; | |
05da4558 | 574 | |
d25797b2 JR |
575 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
576 | ||
577 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
578 | return host_level; | |
579 | ||
878403b7 SY |
580 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
581 | kvm_x86_ops->get_lpage_level() : host_level; | |
582 | ||
583 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
584 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
585 | break; | |
d25797b2 JR |
586 | |
587 | return level - 1; | |
05da4558 MT |
588 | } |
589 | ||
290fc38d IE |
590 | /* |
591 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
592 | */ |
593 | ||
44ad9944 | 594 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
595 | { |
596 | struct kvm_memory_slot *slot; | |
d4dbf470 | 597 | struct kvm_lpage_info *linfo; |
290fc38d IE |
598 | |
599 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 600 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
601 | return &slot->rmap[gfn - slot->base_gfn]; |
602 | ||
d4dbf470 | 603 | linfo = lpage_info_slot(gfn, slot, level); |
05da4558 | 604 | |
d4dbf470 | 605 | return &linfo->rmap_pde; |
290fc38d IE |
606 | } |
607 | ||
cd4a4e53 AK |
608 | /* |
609 | * Reverse mapping data structures: | |
610 | * | |
290fc38d IE |
611 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
612 | * that points to page_address(page). | |
cd4a4e53 | 613 | * |
290fc38d IE |
614 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
615 | * containing more mappings. | |
53a27b39 MT |
616 | * |
617 | * Returns the number of rmap entries before the spte was added or zero if | |
618 | * the spte was not added. | |
619 | * | |
cd4a4e53 | 620 | */ |
44ad9944 | 621 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 622 | { |
4db35314 | 623 | struct kvm_mmu_page *sp; |
cd4a4e53 | 624 | struct kvm_rmap_desc *desc; |
290fc38d | 625 | unsigned long *rmapp; |
53a27b39 | 626 | int i, count = 0; |
cd4a4e53 | 627 | |
43a3795a | 628 | if (!is_rmap_spte(*spte)) |
53a27b39 | 629 | return count; |
4db35314 | 630 | sp = page_header(__pa(spte)); |
2032a93d | 631 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 632 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 633 | if (!*rmapp) { |
cd4a4e53 | 634 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
635 | *rmapp = (unsigned long)spte; |
636 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 637 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 638 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
639 | desc->sptes[0] = (u64 *)*rmapp; |
640 | desc->sptes[1] = spte; | |
290fc38d | 641 | *rmapp = (unsigned long)desc | 1; |
cb16a7b3 | 642 | ++count; |
cd4a4e53 AK |
643 | } else { |
644 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 645 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 646 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 647 | desc = desc->more; |
53a27b39 MT |
648 | count += RMAP_EXT; |
649 | } | |
d555c333 | 650 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 651 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
652 | desc = desc->more; |
653 | } | |
d555c333 | 654 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 655 | ++count; |
d555c333 | 656 | desc->sptes[i] = spte; |
cd4a4e53 | 657 | } |
53a27b39 | 658 | return count; |
cd4a4e53 AK |
659 | } |
660 | ||
290fc38d | 661 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
662 | struct kvm_rmap_desc *desc, |
663 | int i, | |
664 | struct kvm_rmap_desc *prev_desc) | |
665 | { | |
666 | int j; | |
667 | ||
d555c333 | 668 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 669 | ; |
d555c333 AK |
670 | desc->sptes[i] = desc->sptes[j]; |
671 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
672 | if (j != 0) |
673 | return; | |
674 | if (!prev_desc && !desc->more) | |
d555c333 | 675 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
676 | else |
677 | if (prev_desc) | |
678 | prev_desc->more = desc->more; | |
679 | else | |
290fc38d | 680 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 681 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
682 | } |
683 | ||
290fc38d | 684 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 685 | { |
cd4a4e53 AK |
686 | struct kvm_rmap_desc *desc; |
687 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 688 | struct kvm_mmu_page *sp; |
2032a93d | 689 | gfn_t gfn; |
290fc38d | 690 | unsigned long *rmapp; |
cd4a4e53 AK |
691 | int i; |
692 | ||
4db35314 | 693 | sp = page_header(__pa(spte)); |
2032a93d LJ |
694 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
695 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 696 | if (!*rmapp) { |
19ada5c4 | 697 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 698 | BUG(); |
290fc38d | 699 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 700 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 701 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 702 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
703 | BUG(); |
704 | } | |
290fc38d | 705 | *rmapp = 0; |
cd4a4e53 | 706 | } else { |
19ada5c4 | 707 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 708 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
709 | prev_desc = NULL; |
710 | while (desc) { | |
d555c333 AK |
711 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
712 | if (desc->sptes[i] == spte) { | |
290fc38d | 713 | rmap_desc_remove_entry(rmapp, |
714b93da | 714 | desc, i, |
cd4a4e53 AK |
715 | prev_desc); |
716 | return; | |
717 | } | |
718 | prev_desc = desc; | |
719 | desc = desc->more; | |
720 | } | |
19ada5c4 | 721 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
722 | BUG(); |
723 | } | |
724 | } | |
725 | ||
eb45fda4 | 726 | static int set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 727 | { |
ce061867 | 728 | pfn_t pfn; |
9a3aad70 XG |
729 | u64 old_spte = *sptep; |
730 | ||
8672b721 | 731 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 732 | __set_spte(sptep, new_spte); |
8672b721 | 733 | else |
9a3aad70 | 734 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 735 | |
a9221dd5 | 736 | if (!is_rmap_spte(old_spte)) |
eb45fda4 | 737 | return 0; |
8672b721 | 738 | |
a9221dd5 | 739 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 740 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 741 | kvm_set_pfn_accessed(pfn); |
4132779b | 742 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 743 | kvm_set_pfn_dirty(pfn); |
eb45fda4 | 744 | return 1; |
e4b502ea XG |
745 | } |
746 | ||
747 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
748 | { | |
eb45fda4 MT |
749 | if (set_spte_track_bits(sptep, new_spte)) |
750 | rmap_remove(kvm, sptep); | |
be38d276 AK |
751 | } |
752 | ||
98348e95 | 753 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 754 | { |
374cbac0 | 755 | struct kvm_rmap_desc *desc; |
98348e95 IE |
756 | u64 *prev_spte; |
757 | int i; | |
758 | ||
759 | if (!*rmapp) | |
760 | return NULL; | |
761 | else if (!(*rmapp & 1)) { | |
762 | if (!spte) | |
763 | return (u64 *)*rmapp; | |
764 | return NULL; | |
765 | } | |
766 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
767 | prev_spte = NULL; |
768 | while (desc) { | |
d555c333 | 769 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 770 | if (prev_spte == spte) |
d555c333 AK |
771 | return desc->sptes[i]; |
772 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
773 | } |
774 | desc = desc->more; | |
775 | } | |
776 | return NULL; | |
777 | } | |
778 | ||
b1a36821 | 779 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 780 | { |
290fc38d | 781 | unsigned long *rmapp; |
374cbac0 | 782 | u64 *spte; |
44ad9944 | 783 | int i, write_protected = 0; |
374cbac0 | 784 | |
44ad9944 | 785 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 786 | |
98348e95 IE |
787 | spte = rmap_next(kvm, rmapp, NULL); |
788 | while (spte) { | |
374cbac0 | 789 | BUG_ON(!spte); |
374cbac0 | 790 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 791 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 792 | if (is_writable_pte(*spte)) { |
b79b93f9 | 793 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
794 | write_protected = 1; |
795 | } | |
9647c14c | 796 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 797 | } |
855149aa | 798 | |
05da4558 | 799 | /* check for huge page mappings */ |
44ad9944 JR |
800 | for (i = PT_DIRECTORY_LEVEL; |
801 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
802 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
803 | spte = rmap_next(kvm, rmapp, NULL); | |
804 | while (spte) { | |
805 | BUG_ON(!spte); | |
806 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
807 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
808 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 809 | if (is_writable_pte(*spte)) { |
be38d276 AK |
810 | drop_spte(kvm, spte, |
811 | shadow_trap_nonpresent_pte); | |
44ad9944 | 812 | --kvm->stat.lpages; |
44ad9944 JR |
813 | spte = NULL; |
814 | write_protected = 1; | |
815 | } | |
816 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 817 | } |
05da4558 MT |
818 | } |
819 | ||
b1a36821 | 820 | return write_protected; |
374cbac0 AK |
821 | } |
822 | ||
8a8365c5 FD |
823 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
824 | unsigned long data) | |
e930bffe AA |
825 | { |
826 | u64 *spte; | |
827 | int need_tlb_flush = 0; | |
828 | ||
829 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
830 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
831 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 832 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
833 | need_tlb_flush = 1; |
834 | } | |
835 | return need_tlb_flush; | |
836 | } | |
837 | ||
8a8365c5 FD |
838 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
839 | unsigned long data) | |
3da0dd43 IE |
840 | { |
841 | int need_flush = 0; | |
e4b502ea | 842 | u64 *spte, new_spte; |
3da0dd43 IE |
843 | pte_t *ptep = (pte_t *)data; |
844 | pfn_t new_pfn; | |
845 | ||
846 | WARN_ON(pte_huge(*ptep)); | |
847 | new_pfn = pte_pfn(*ptep); | |
848 | spte = rmap_next(kvm, rmapp, NULL); | |
849 | while (spte) { | |
850 | BUG_ON(!is_shadow_present_pte(*spte)); | |
851 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
852 | need_flush = 1; | |
853 | if (pte_write(*ptep)) { | |
be38d276 | 854 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
855 | spte = rmap_next(kvm, rmapp, NULL); |
856 | } else { | |
857 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
858 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
859 | ||
860 | new_spte &= ~PT_WRITABLE_MASK; | |
861 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 862 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 863 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
864 | spte = rmap_next(kvm, rmapp, spte); |
865 | } | |
866 | } | |
867 | if (need_flush) | |
868 | kvm_flush_remote_tlbs(kvm); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
8a8365c5 FD |
873 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
874 | unsigned long data, | |
3da0dd43 | 875 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 876 | unsigned long data)) |
e930bffe | 877 | { |
852e3c19 | 878 | int i, j; |
90bb6fc5 | 879 | int ret; |
e930bffe | 880 | int retval = 0; |
bc6678a3 MT |
881 | struct kvm_memslots *slots; |
882 | ||
90d83dc3 | 883 | slots = kvm_memslots(kvm); |
e930bffe | 884 | |
46a26bf5 MT |
885 | for (i = 0; i < slots->nmemslots; i++) { |
886 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
887 | unsigned long start = memslot->userspace_addr; |
888 | unsigned long end; | |
889 | ||
e930bffe AA |
890 | end = start + (memslot->npages << PAGE_SHIFT); |
891 | if (hva >= start && hva < end) { | |
892 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 893 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 894 | |
90bb6fc5 | 895 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
896 | |
897 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
898 | struct kvm_lpage_info *linfo; |
899 | ||
900 | linfo = lpage_info_slot(gfn, memslot, | |
901 | PT_DIRECTORY_LEVEL + j); | |
902 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 903 | } |
90bb6fc5 AK |
904 | trace_kvm_age_page(hva, memslot, ret); |
905 | retval |= ret; | |
e930bffe AA |
906 | } |
907 | } | |
908 | ||
909 | return retval; | |
910 | } | |
911 | ||
912 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
913 | { | |
3da0dd43 IE |
914 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
915 | } | |
916 | ||
917 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
918 | { | |
8a8365c5 | 919 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
920 | } |
921 | ||
8a8365c5 FD |
922 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
923 | unsigned long data) | |
e930bffe AA |
924 | { |
925 | u64 *spte; | |
926 | int young = 0; | |
927 | ||
6316e1c8 RR |
928 | /* |
929 | * Emulate the accessed bit for EPT, by checking if this page has | |
930 | * an EPT mapping, and clearing it if it does. On the next access, | |
931 | * a new EPT mapping will be established. | |
932 | * This has some overhead, but not as much as the cost of swapping | |
933 | * out actively used pages or breaking up actively used hugepages. | |
934 | */ | |
534e38b4 | 935 | if (!shadow_accessed_mask) |
6316e1c8 | 936 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 937 | |
e930bffe AA |
938 | spte = rmap_next(kvm, rmapp, NULL); |
939 | while (spte) { | |
940 | int _young; | |
941 | u64 _spte = *spte; | |
942 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
943 | _young = _spte & PT_ACCESSED_MASK; | |
944 | if (_young) { | |
945 | young = 1; | |
946 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
947 | } | |
948 | spte = rmap_next(kvm, rmapp, spte); | |
949 | } | |
950 | return young; | |
951 | } | |
952 | ||
8ee53820 AA |
953 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
954 | unsigned long data) | |
955 | { | |
956 | u64 *spte; | |
957 | int young = 0; | |
958 | ||
959 | /* | |
960 | * If there's no access bit in the secondary pte set by the | |
961 | * hardware it's up to gup-fast/gup to set the access bit in | |
962 | * the primary pte or in the page structure. | |
963 | */ | |
964 | if (!shadow_accessed_mask) | |
965 | goto out; | |
966 | ||
967 | spte = rmap_next(kvm, rmapp, NULL); | |
968 | while (spte) { | |
969 | u64 _spte = *spte; | |
970 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
971 | young = _spte & PT_ACCESSED_MASK; | |
972 | if (young) { | |
973 | young = 1; | |
974 | break; | |
975 | } | |
976 | spte = rmap_next(kvm, rmapp, spte); | |
977 | } | |
978 | out: | |
979 | return young; | |
980 | } | |
981 | ||
53a27b39 MT |
982 | #define RMAP_RECYCLE_THRESHOLD 1000 |
983 | ||
852e3c19 | 984 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
985 | { |
986 | unsigned long *rmapp; | |
852e3c19 JR |
987 | struct kvm_mmu_page *sp; |
988 | ||
989 | sp = page_header(__pa(spte)); | |
53a27b39 | 990 | |
852e3c19 | 991 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 992 | |
3da0dd43 | 993 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
994 | kvm_flush_remote_tlbs(vcpu->kvm); |
995 | } | |
996 | ||
e930bffe AA |
997 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
998 | { | |
3da0dd43 | 999 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1000 | } |
1001 | ||
8ee53820 AA |
1002 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1003 | { | |
1004 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1005 | } | |
1006 | ||
d6c69ee9 | 1007 | #ifdef MMU_DEBUG |
47ad8e68 | 1008 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1009 | { |
139bdb2d AK |
1010 | u64 *pos; |
1011 | u64 *end; | |
1012 | ||
47ad8e68 | 1013 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1014 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1015 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1016 | pos, *pos); |
6aa8b732 | 1017 | return 0; |
139bdb2d | 1018 | } |
6aa8b732 AK |
1019 | return 1; |
1020 | } | |
d6c69ee9 | 1021 | #endif |
6aa8b732 | 1022 | |
45221ab6 DH |
1023 | /* |
1024 | * This value is the sum of all of the kvm instances's | |
1025 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1026 | * aggregate version in order to make the slab shrinker | |
1027 | * faster | |
1028 | */ | |
1029 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1030 | { | |
1031 | kvm->arch.n_used_mmu_pages += nr; | |
1032 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1033 | } | |
1034 | ||
4db35314 | 1035 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 1036 | { |
4db35314 | 1037 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1038 | hlist_del(&sp->hash_link); |
4db35314 | 1039 | list_del(&sp->link); |
842f22ed | 1040 | free_page((unsigned long)sp->spt); |
2032a93d | 1041 | if (!sp->role.direct) |
842f22ed | 1042 | free_page((unsigned long)sp->gfns); |
e8ad9a70 | 1043 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 1044 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
1045 | } |
1046 | ||
cea0f0e7 AK |
1047 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1048 | { | |
1ae0a13d | 1049 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1050 | } |
1051 | ||
25c0de2c | 1052 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1053 | u64 *parent_pte, int direct) |
6aa8b732 | 1054 | { |
4db35314 | 1055 | struct kvm_mmu_page *sp; |
6aa8b732 | 1056 | |
ad312c7c ZX |
1057 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1058 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1059 | if (!direct) |
1060 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1061 | PAGE_SIZE); | |
4db35314 | 1062 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1063 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1064 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1065 | sp->multimapped = 0; |
1066 | sp->parent_pte = parent_pte; | |
45221ab6 | 1067 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1068 | return sp; |
6aa8b732 AK |
1069 | } |
1070 | ||
714b93da | 1071 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1072 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1073 | { |
1074 | struct kvm_pte_chain *pte_chain; | |
1075 | struct hlist_node *node; | |
1076 | int i; | |
1077 | ||
1078 | if (!parent_pte) | |
1079 | return; | |
4db35314 AK |
1080 | if (!sp->multimapped) { |
1081 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1082 | |
1083 | if (!old) { | |
4db35314 | 1084 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1085 | return; |
1086 | } | |
4db35314 | 1087 | sp->multimapped = 1; |
714b93da | 1088 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1089 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1090 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1091 | pte_chain->parent_ptes[0] = old; |
1092 | } | |
4db35314 | 1093 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1094 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1095 | continue; | |
1096 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1097 | if (!pte_chain->parent_ptes[i]) { | |
1098 | pte_chain->parent_ptes[i] = parent_pte; | |
1099 | return; | |
1100 | } | |
1101 | } | |
714b93da | 1102 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1103 | BUG_ON(!pte_chain); |
4db35314 | 1104 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1105 | pte_chain->parent_ptes[0] = parent_pte; |
1106 | } | |
1107 | ||
4db35314 | 1108 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1109 | u64 *parent_pte) |
1110 | { | |
1111 | struct kvm_pte_chain *pte_chain; | |
1112 | struct hlist_node *node; | |
1113 | int i; | |
1114 | ||
4db35314 AK |
1115 | if (!sp->multimapped) { |
1116 | BUG_ON(sp->parent_pte != parent_pte); | |
1117 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1118 | return; |
1119 | } | |
4db35314 | 1120 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1121 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1122 | if (!pte_chain->parent_ptes[i]) | |
1123 | break; | |
1124 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1125 | continue; | |
697fe2e2 AK |
1126 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1127 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1128 | pte_chain->parent_ptes[i] |
1129 | = pte_chain->parent_ptes[i + 1]; | |
1130 | ++i; | |
1131 | } | |
1132 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1133 | if (i == 0) { |
1134 | hlist_del(&pte_chain->link); | |
90cb0529 | 1135 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1136 | if (hlist_empty(&sp->parent_ptes)) { |
1137 | sp->multimapped = 0; | |
1138 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1139 | } |
1140 | } | |
cea0f0e7 AK |
1141 | return; |
1142 | } | |
1143 | BUG(); | |
1144 | } | |
1145 | ||
6b18493d | 1146 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1147 | { |
1148 | struct kvm_pte_chain *pte_chain; | |
1149 | struct hlist_node *node; | |
1150 | struct kvm_mmu_page *parent_sp; | |
1151 | int i; | |
1152 | ||
1153 | if (!sp->multimapped && sp->parent_pte) { | |
1154 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1155 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1156 | return; |
1157 | } | |
1047df1f | 1158 | |
ad8cfbe3 MT |
1159 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1160 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1161 | u64 *spte = pte_chain->parent_ptes[i]; |
1162 | ||
1163 | if (!spte) | |
ad8cfbe3 | 1164 | break; |
1047df1f XG |
1165 | parent_sp = page_header(__pa(spte)); |
1166 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1167 | } |
1168 | } | |
1169 | ||
1047df1f XG |
1170 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1171 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1172 | { |
1047df1f | 1173 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1174 | } |
1175 | ||
1047df1f | 1176 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1177 | { |
1047df1f | 1178 | unsigned int index; |
0074ff63 | 1179 | |
1047df1f XG |
1180 | index = spte - sp->spt; |
1181 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1182 | return; |
1047df1f | 1183 | if (sp->unsync_children++) |
0074ff63 | 1184 | return; |
1047df1f | 1185 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1186 | } |
1187 | ||
d761a501 AK |
1188 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1189 | struct kvm_mmu_page *sp) | |
1190 | { | |
1191 | int i; | |
1192 | ||
1193 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1194 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1195 | } | |
1196 | ||
e8bc217a | 1197 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1198 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1199 | { |
1200 | return 1; | |
1201 | } | |
1202 | ||
a7052897 MT |
1203 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1204 | { | |
1205 | } | |
1206 | ||
0f53b5b1 XG |
1207 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1208 | struct kvm_mmu_page *sp, u64 *spte, | |
1209 | const void *pte, unsigned long mmu_seq) | |
1210 | { | |
1211 | WARN_ON(1); | |
1212 | } | |
1213 | ||
60c8aec6 MT |
1214 | #define KVM_PAGE_ARRAY_NR 16 |
1215 | ||
1216 | struct kvm_mmu_pages { | |
1217 | struct mmu_page_and_offset { | |
1218 | struct kvm_mmu_page *sp; | |
1219 | unsigned int idx; | |
1220 | } page[KVM_PAGE_ARRAY_NR]; | |
1221 | unsigned int nr; | |
1222 | }; | |
1223 | ||
0074ff63 MT |
1224 | #define for_each_unsync_children(bitmap, idx) \ |
1225 | for (idx = find_first_bit(bitmap, 512); \ | |
1226 | idx < 512; \ | |
1227 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1228 | ||
cded19f3 HE |
1229 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1230 | int idx) | |
4731d4c7 | 1231 | { |
60c8aec6 | 1232 | int i; |
4731d4c7 | 1233 | |
60c8aec6 MT |
1234 | if (sp->unsync) |
1235 | for (i=0; i < pvec->nr; i++) | |
1236 | if (pvec->page[i].sp == sp) | |
1237 | return 0; | |
1238 | ||
1239 | pvec->page[pvec->nr].sp = sp; | |
1240 | pvec->page[pvec->nr].idx = idx; | |
1241 | pvec->nr++; | |
1242 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1243 | } | |
1244 | ||
1245 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1246 | struct kvm_mmu_pages *pvec) | |
1247 | { | |
1248 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1249 | |
0074ff63 | 1250 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1251 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1252 | u64 ent = sp->spt[i]; |
1253 | ||
7a8f1a74 XG |
1254 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1255 | goto clear_child_bitmap; | |
1256 | ||
1257 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1258 | ||
1259 | if (child->unsync_children) { | |
1260 | if (mmu_pages_add(pvec, child, i)) | |
1261 | return -ENOSPC; | |
1262 | ||
1263 | ret = __mmu_unsync_walk(child, pvec); | |
1264 | if (!ret) | |
1265 | goto clear_child_bitmap; | |
1266 | else if (ret > 0) | |
1267 | nr_unsync_leaf += ret; | |
1268 | else | |
1269 | return ret; | |
1270 | } else if (child->unsync) { | |
1271 | nr_unsync_leaf++; | |
1272 | if (mmu_pages_add(pvec, child, i)) | |
1273 | return -ENOSPC; | |
1274 | } else | |
1275 | goto clear_child_bitmap; | |
1276 | ||
1277 | continue; | |
1278 | ||
1279 | clear_child_bitmap: | |
1280 | __clear_bit(i, sp->unsync_child_bitmap); | |
1281 | sp->unsync_children--; | |
1282 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1283 | } |
1284 | ||
4731d4c7 | 1285 | |
60c8aec6 MT |
1286 | return nr_unsync_leaf; |
1287 | } | |
1288 | ||
1289 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1290 | struct kvm_mmu_pages *pvec) | |
1291 | { | |
1292 | if (!sp->unsync_children) | |
1293 | return 0; | |
1294 | ||
1295 | mmu_pages_add(pvec, sp, 0); | |
1296 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1297 | } |
1298 | ||
4731d4c7 MT |
1299 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1300 | { | |
1301 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1302 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1303 | sp->unsync = 0; |
1304 | --kvm->stat.mmu_unsync; | |
1305 | } | |
1306 | ||
7775834a XG |
1307 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1308 | struct list_head *invalid_list); | |
1309 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1310 | struct list_head *invalid_list); | |
4731d4c7 | 1311 | |
f41d335a XG |
1312 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1313 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1314 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1315 | if ((sp)->gfn != (gfn)) {} else | |
1316 | ||
f41d335a XG |
1317 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1318 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1319 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1320 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1321 | (sp)->role.invalid) {} else | |
1322 | ||
f918b443 | 1323 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1324 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1325 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1326 | { |
5b7e0102 | 1327 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1328 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1329 | return 1; |
1330 | } | |
1331 | ||
f918b443 | 1332 | if (clear_unsync) |
1d9dc7e0 | 1333 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1334 | |
a4a8e6f7 | 1335 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1336 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1337 | return 1; |
1338 | } | |
1339 | ||
1340 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1341 | return 0; |
1342 | } | |
1343 | ||
1d9dc7e0 XG |
1344 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1345 | struct kvm_mmu_page *sp) | |
1346 | { | |
d98ba053 | 1347 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1348 | int ret; |
1349 | ||
d98ba053 | 1350 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1351 | if (ret) |
d98ba053 XG |
1352 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1353 | ||
1d9dc7e0 XG |
1354 | return ret; |
1355 | } | |
1356 | ||
d98ba053 XG |
1357 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1358 | struct list_head *invalid_list) | |
1d9dc7e0 | 1359 | { |
d98ba053 | 1360 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1361 | } |
1362 | ||
9f1a122f XG |
1363 | /* @gfn should be write-protected at the call site */ |
1364 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1365 | { | |
9f1a122f | 1366 | struct kvm_mmu_page *s; |
f41d335a | 1367 | struct hlist_node *node; |
d98ba053 | 1368 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1369 | bool flush = false; |
1370 | ||
f41d335a | 1371 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1372 | if (!s->unsync) |
9f1a122f XG |
1373 | continue; |
1374 | ||
1375 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1376 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1377 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1378 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1379 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1380 | continue; |
1381 | } | |
9f1a122f XG |
1382 | flush = true; |
1383 | } | |
1384 | ||
d98ba053 | 1385 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1386 | if (flush) |
1387 | kvm_mmu_flush_tlb(vcpu); | |
1388 | } | |
1389 | ||
60c8aec6 MT |
1390 | struct mmu_page_path { |
1391 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1392 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1393 | }; |
1394 | ||
60c8aec6 MT |
1395 | #define for_each_sp(pvec, sp, parents, i) \ |
1396 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1397 | sp = pvec.page[i].sp; \ | |
1398 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1399 | i = mmu_pages_next(&pvec, &parents, i)) | |
1400 | ||
cded19f3 HE |
1401 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1402 | struct mmu_page_path *parents, | |
1403 | int i) | |
60c8aec6 MT |
1404 | { |
1405 | int n; | |
1406 | ||
1407 | for (n = i+1; n < pvec->nr; n++) { | |
1408 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1409 | ||
1410 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1411 | parents->idx[0] = pvec->page[n].idx; | |
1412 | return n; | |
1413 | } | |
1414 | ||
1415 | parents->parent[sp->role.level-2] = sp; | |
1416 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1417 | } | |
1418 | ||
1419 | return n; | |
1420 | } | |
1421 | ||
cded19f3 | 1422 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1423 | { |
60c8aec6 MT |
1424 | struct kvm_mmu_page *sp; |
1425 | unsigned int level = 0; | |
1426 | ||
1427 | do { | |
1428 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1429 | |
60c8aec6 MT |
1430 | sp = parents->parent[level]; |
1431 | if (!sp) | |
1432 | return; | |
1433 | ||
1434 | --sp->unsync_children; | |
1435 | WARN_ON((int)sp->unsync_children < 0); | |
1436 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1437 | level++; | |
1438 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1439 | } |
1440 | ||
60c8aec6 MT |
1441 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1442 | struct mmu_page_path *parents, | |
1443 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1444 | { |
60c8aec6 MT |
1445 | parents->parent[parent->role.level-1] = NULL; |
1446 | pvec->nr = 0; | |
1447 | } | |
4731d4c7 | 1448 | |
60c8aec6 MT |
1449 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1450 | struct kvm_mmu_page *parent) | |
1451 | { | |
1452 | int i; | |
1453 | struct kvm_mmu_page *sp; | |
1454 | struct mmu_page_path parents; | |
1455 | struct kvm_mmu_pages pages; | |
d98ba053 | 1456 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1457 | |
1458 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1459 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1460 | int protected = 0; |
1461 | ||
1462 | for_each_sp(pages, sp, parents, i) | |
1463 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1464 | ||
1465 | if (protected) | |
1466 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1467 | ||
60c8aec6 | 1468 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1469 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1470 | mmu_pages_clear_parents(&parents); |
1471 | } | |
d98ba053 | 1472 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1473 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1474 | kvm_mmu_pages_init(parent, &parents, &pages); |
1475 | } | |
4731d4c7 MT |
1476 | } |
1477 | ||
cea0f0e7 AK |
1478 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1479 | gfn_t gfn, | |
1480 | gva_t gaddr, | |
1481 | unsigned level, | |
f6e2c02b | 1482 | int direct, |
41074d07 | 1483 | unsigned access, |
f7d9c7b7 | 1484 | u64 *parent_pte) |
cea0f0e7 AK |
1485 | { |
1486 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1487 | unsigned quadrant; |
9f1a122f | 1488 | struct kvm_mmu_page *sp; |
f41d335a | 1489 | struct hlist_node *node; |
9f1a122f | 1490 | bool need_sync = false; |
cea0f0e7 | 1491 | |
a770f6f2 | 1492 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1493 | role.level = level; |
f6e2c02b | 1494 | role.direct = direct; |
84b0c8c6 | 1495 | if (role.direct) |
5b7e0102 | 1496 | role.cr4_pae = 0; |
41074d07 | 1497 | role.access = access; |
c5a78f2b JR |
1498 | if (!vcpu->arch.mmu.direct_map |
1499 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1500 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1501 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1502 | role.quadrant = quadrant; | |
1503 | } | |
f41d335a | 1504 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1505 | if (!need_sync && sp->unsync) |
1506 | need_sync = true; | |
4731d4c7 | 1507 | |
7ae680eb XG |
1508 | if (sp->role.word != role.word) |
1509 | continue; | |
4731d4c7 | 1510 | |
7ae680eb XG |
1511 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1512 | break; | |
e02aa901 | 1513 | |
7ae680eb XG |
1514 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1515 | if (sp->unsync_children) { | |
a8eeb04a | 1516 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1517 | kvm_mmu_mark_parents_unsync(sp); |
1518 | } else if (sp->unsync) | |
1519 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1520 | |
7ae680eb XG |
1521 | trace_kvm_mmu_get_page(sp, false); |
1522 | return sp; | |
1523 | } | |
dfc5aa00 | 1524 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1525 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1526 | if (!sp) |
1527 | return sp; | |
4db35314 AK |
1528 | sp->gfn = gfn; |
1529 | sp->role = role; | |
7ae680eb XG |
1530 | hlist_add_head(&sp->hash_link, |
1531 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1532 | if (!direct) { |
b1a36821 MT |
1533 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1534 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1535 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1536 | kvm_sync_pages(vcpu, gfn); | |
1537 | ||
4731d4c7 MT |
1538 | account_shadowed(vcpu->kvm, gfn); |
1539 | } | |
131d8279 AK |
1540 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1541 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1542 | else | |
1543 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1544 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1545 | return sp; |
cea0f0e7 AK |
1546 | } |
1547 | ||
2d11123a AK |
1548 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1549 | struct kvm_vcpu *vcpu, u64 addr) | |
1550 | { | |
1551 | iterator->addr = addr; | |
1552 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1553 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1554 | |
1555 | if (iterator->level == PT64_ROOT_LEVEL && | |
1556 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1557 | !vcpu->arch.mmu.direct_map) | |
1558 | --iterator->level; | |
1559 | ||
2d11123a AK |
1560 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1561 | iterator->shadow_addr | |
1562 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1563 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1564 | --iterator->level; | |
1565 | if (!iterator->shadow_addr) | |
1566 | iterator->level = 0; | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1571 | { | |
1572 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1573 | return false; | |
4d88954d MT |
1574 | |
1575 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1576 | if (is_large_pte(*iterator->sptep)) | |
1577 | return false; | |
1578 | ||
2d11123a AK |
1579 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1580 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1581 | return true; | |
1582 | } | |
1583 | ||
1584 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1585 | { | |
1586 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1587 | --iterator->level; | |
1588 | } | |
1589 | ||
32ef26a3 AK |
1590 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1591 | { | |
1592 | u64 spte; | |
1593 | ||
1594 | spte = __pa(sp->spt) | |
1595 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1596 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1597 | __set_spte(sptep, spte); |
32ef26a3 AK |
1598 | } |
1599 | ||
a3aa51cf AK |
1600 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1601 | { | |
1602 | if (is_large_pte(*sptep)) { | |
1603 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1604 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1605 | } | |
1606 | } | |
1607 | ||
a357bd22 AK |
1608 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1609 | unsigned direct_access) | |
1610 | { | |
1611 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1612 | struct kvm_mmu_page *child; | |
1613 | ||
1614 | /* | |
1615 | * For the direct sp, if the guest pte's dirty bit | |
1616 | * changed form clean to dirty, it will corrupt the | |
1617 | * sp's access: allow writable in the read-only sp, | |
1618 | * so we should update the spte at this point to get | |
1619 | * a new sp with the correct access. | |
1620 | */ | |
1621 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1622 | if (child->role.access == direct_access) | |
1623 | return; | |
1624 | ||
1625 | mmu_page_remove_parent_pte(child, sptep); | |
1626 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1627 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1628 | } | |
1629 | } | |
1630 | ||
90cb0529 | 1631 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1632 | struct kvm_mmu_page *sp) |
a436036b | 1633 | { |
697fe2e2 AK |
1634 | unsigned i; |
1635 | u64 *pt; | |
1636 | u64 ent; | |
1637 | ||
4db35314 | 1638 | pt = sp->spt; |
697fe2e2 | 1639 | |
697fe2e2 AK |
1640 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1641 | ent = pt[i]; | |
1642 | ||
05da4558 | 1643 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1644 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1645 | ent &= PT64_BASE_ADDR_MASK; |
1646 | mmu_page_remove_parent_pte(page_header(ent), | |
1647 | &pt[i]); | |
1648 | } else { | |
776e6633 MT |
1649 | if (is_large_pte(ent)) |
1650 | --kvm->stat.lpages; | |
be38d276 AK |
1651 | drop_spte(kvm, &pt[i], |
1652 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1653 | } |
1654 | } | |
c7addb90 | 1655 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1656 | } |
a436036b AK |
1657 | } |
1658 | ||
4db35314 | 1659 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1660 | { |
4db35314 | 1661 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1662 | } |
1663 | ||
12b7d28f AK |
1664 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1665 | { | |
1666 | int i; | |
988a2cae | 1667 | struct kvm_vcpu *vcpu; |
12b7d28f | 1668 | |
988a2cae GN |
1669 | kvm_for_each_vcpu(i, vcpu, kvm) |
1670 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1671 | } |
1672 | ||
31aa2b44 | 1673 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1674 | { |
1675 | u64 *parent_pte; | |
1676 | ||
4db35314 AK |
1677 | while (sp->multimapped || sp->parent_pte) { |
1678 | if (!sp->multimapped) | |
1679 | parent_pte = sp->parent_pte; | |
a436036b AK |
1680 | else { |
1681 | struct kvm_pte_chain *chain; | |
1682 | ||
4db35314 | 1683 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1684 | struct kvm_pte_chain, link); |
1685 | parent_pte = chain->parent_ptes[0]; | |
1686 | } | |
697fe2e2 | 1687 | BUG_ON(!parent_pte); |
4db35314 | 1688 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1689 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1690 | } |
31aa2b44 AK |
1691 | } |
1692 | ||
60c8aec6 | 1693 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1694 | struct kvm_mmu_page *parent, |
1695 | struct list_head *invalid_list) | |
4731d4c7 | 1696 | { |
60c8aec6 MT |
1697 | int i, zapped = 0; |
1698 | struct mmu_page_path parents; | |
1699 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1700 | |
60c8aec6 | 1701 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1702 | return 0; |
60c8aec6 MT |
1703 | |
1704 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1705 | while (mmu_unsync_walk(parent, &pages)) { | |
1706 | struct kvm_mmu_page *sp; | |
1707 | ||
1708 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1709 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1710 | mmu_pages_clear_parents(&parents); |
77662e00 | 1711 | zapped++; |
60c8aec6 | 1712 | } |
60c8aec6 MT |
1713 | kvm_mmu_pages_init(parent, &parents, &pages); |
1714 | } | |
1715 | ||
1716 | return zapped; | |
4731d4c7 MT |
1717 | } |
1718 | ||
7775834a XG |
1719 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1720 | struct list_head *invalid_list) | |
31aa2b44 | 1721 | { |
4731d4c7 | 1722 | int ret; |
f691fe1d | 1723 | |
7775834a | 1724 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1725 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1726 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1727 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1728 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1729 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1730 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1731 | if (sp->unsync) |
1732 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1733 | if (!sp->root_count) { |
54a4f023 GJ |
1734 | /* Count self */ |
1735 | ret++; | |
7775834a | 1736 | list_move(&sp->link, invalid_list); |
2e53d63a | 1737 | } else { |
5b5c6a5a | 1738 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1739 | kvm_reload_remote_mmus(kvm); |
1740 | } | |
7775834a XG |
1741 | |
1742 | sp->role.invalid = 1; | |
12b7d28f | 1743 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1744 | return ret; |
a436036b AK |
1745 | } |
1746 | ||
7775834a XG |
1747 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1748 | struct list_head *invalid_list) | |
1749 | { | |
1750 | struct kvm_mmu_page *sp; | |
1751 | ||
1752 | if (list_empty(invalid_list)) | |
1753 | return; | |
1754 | ||
1755 | kvm_flush_remote_tlbs(kvm); | |
1756 | ||
1757 | do { | |
1758 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1759 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1760 | kvm_mmu_free_page(kvm, sp); | |
1761 | } while (!list_empty(invalid_list)); | |
1762 | ||
1763 | } | |
1764 | ||
82ce2c96 IE |
1765 | /* |
1766 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1767 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1768 | */ |
49d5ca26 | 1769 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1770 | { |
d98ba053 | 1771 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1772 | /* |
1773 | * If we set the number of mmu pages to be smaller be than the | |
1774 | * number of actived pages , we must to free some mmu pages before we | |
1775 | * change the value | |
1776 | */ | |
1777 | ||
49d5ca26 DH |
1778 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1779 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1780 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1781 | struct kvm_mmu_page *page; |
1782 | ||
f05e70ac | 1783 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1784 | struct kvm_mmu_page, link); |
80b63faf XF |
1785 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1786 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1787 | } |
49d5ca26 | 1788 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1789 | } |
82ce2c96 | 1790 | |
49d5ca26 | 1791 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1792 | } |
1793 | ||
f67a46f4 | 1794 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1795 | { |
4db35314 | 1796 | struct kvm_mmu_page *sp; |
f41d335a | 1797 | struct hlist_node *node; |
d98ba053 | 1798 | LIST_HEAD(invalid_list); |
a436036b AK |
1799 | int r; |
1800 | ||
9ad17b10 | 1801 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1802 | r = 0; |
f41d335a XG |
1803 | |
1804 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1805 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1806 | sp->role.word); |
1807 | r = 1; | |
f41d335a | 1808 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1809 | } |
d98ba053 | 1810 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1811 | return r; |
cea0f0e7 AK |
1812 | } |
1813 | ||
f67a46f4 | 1814 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1815 | { |
4db35314 | 1816 | struct kvm_mmu_page *sp; |
f41d335a | 1817 | struct hlist_node *node; |
d98ba053 | 1818 | LIST_HEAD(invalid_list); |
97a0a01e | 1819 | |
f41d335a | 1820 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1821 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1822 | __func__, gfn, sp->role.word); |
f41d335a | 1823 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1824 | } |
d98ba053 | 1825 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1826 | } |
1827 | ||
38c335f1 | 1828 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1829 | { |
bc6678a3 | 1830 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1831 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1832 | |
291f26bc | 1833 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1834 | } |
1835 | ||
6844dec6 MT |
1836 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1837 | { | |
1838 | int i; | |
1839 | u64 *pt = sp->spt; | |
1840 | ||
1841 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1842 | return; | |
1843 | ||
1844 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1845 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1846 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1847 | } |
1848 | } | |
1849 | ||
74be52e3 SY |
1850 | /* |
1851 | * The function is based on mtrr_type_lookup() in | |
1852 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1853 | */ | |
1854 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1855 | u64 start, u64 end) | |
1856 | { | |
1857 | int i; | |
1858 | u64 base, mask; | |
1859 | u8 prev_match, curr_match; | |
1860 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1861 | ||
1862 | if (!mtrr_state->enabled) | |
1863 | return 0xFF; | |
1864 | ||
1865 | /* Make end inclusive end, instead of exclusive */ | |
1866 | end--; | |
1867 | ||
1868 | /* Look in fixed ranges. Just return the type as per start */ | |
1869 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1870 | int idx; | |
1871 | ||
1872 | if (start < 0x80000) { | |
1873 | idx = 0; | |
1874 | idx += (start >> 16); | |
1875 | return mtrr_state->fixed_ranges[idx]; | |
1876 | } else if (start < 0xC0000) { | |
1877 | idx = 1 * 8; | |
1878 | idx += ((start - 0x80000) >> 14); | |
1879 | return mtrr_state->fixed_ranges[idx]; | |
1880 | } else if (start < 0x1000000) { | |
1881 | idx = 3 * 8; | |
1882 | idx += ((start - 0xC0000) >> 12); | |
1883 | return mtrr_state->fixed_ranges[idx]; | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | /* | |
1888 | * Look in variable ranges | |
1889 | * Look of multiple ranges matching this address and pick type | |
1890 | * as per MTRR precedence | |
1891 | */ | |
1892 | if (!(mtrr_state->enabled & 2)) | |
1893 | return mtrr_state->def_type; | |
1894 | ||
1895 | prev_match = 0xFF; | |
1896 | for (i = 0; i < num_var_ranges; ++i) { | |
1897 | unsigned short start_state, end_state; | |
1898 | ||
1899 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1900 | continue; | |
1901 | ||
1902 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1903 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1904 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1905 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1906 | ||
1907 | start_state = ((start & mask) == (base & mask)); | |
1908 | end_state = ((end & mask) == (base & mask)); | |
1909 | if (start_state != end_state) | |
1910 | return 0xFE; | |
1911 | ||
1912 | if ((start & mask) != (base & mask)) | |
1913 | continue; | |
1914 | ||
1915 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1916 | if (prev_match == 0xFF) { | |
1917 | prev_match = curr_match; | |
1918 | continue; | |
1919 | } | |
1920 | ||
1921 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1922 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1923 | return MTRR_TYPE_UNCACHABLE; | |
1924 | ||
1925 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1926 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1927 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1928 | curr_match == MTRR_TYPE_WRBACK)) { | |
1929 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1930 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1931 | } | |
1932 | ||
1933 | if (prev_match != curr_match) | |
1934 | return MTRR_TYPE_UNCACHABLE; | |
1935 | } | |
1936 | ||
1937 | if (prev_match != 0xFF) | |
1938 | return prev_match; | |
1939 | ||
1940 | return mtrr_state->def_type; | |
1941 | } | |
1942 | ||
4b12f0de | 1943 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1944 | { |
1945 | u8 mtrr; | |
1946 | ||
1947 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1948 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1949 | if (mtrr == 0xfe || mtrr == 0xff) | |
1950 | mtrr = MTRR_TYPE_WRBACK; | |
1951 | return mtrr; | |
1952 | } | |
4b12f0de | 1953 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1954 | |
9cf5cf5a XG |
1955 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1956 | { | |
1957 | trace_kvm_mmu_unsync_page(sp); | |
1958 | ++vcpu->kvm->stat.mmu_unsync; | |
1959 | sp->unsync = 1; | |
1960 | ||
1961 | kvm_mmu_mark_parents_unsync(sp); | |
1962 | mmu_convert_notrap(sp); | |
1963 | } | |
1964 | ||
1965 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1966 | { |
4731d4c7 | 1967 | struct kvm_mmu_page *s; |
f41d335a | 1968 | struct hlist_node *node; |
9cf5cf5a | 1969 | |
f41d335a | 1970 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1971 | if (s->unsync) |
4731d4c7 | 1972 | continue; |
9cf5cf5a XG |
1973 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1974 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1975 | } |
4731d4c7 MT |
1976 | } |
1977 | ||
1978 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1979 | bool can_unsync) | |
1980 | { | |
9cf5cf5a | 1981 | struct kvm_mmu_page *s; |
f41d335a | 1982 | struct hlist_node *node; |
9cf5cf5a XG |
1983 | bool need_unsync = false; |
1984 | ||
f41d335a | 1985 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1986 | if (!can_unsync) |
1987 | return 1; | |
1988 | ||
9cf5cf5a | 1989 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1990 | return 1; |
9cf5cf5a XG |
1991 | |
1992 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1993 | if (!oos_shadow) |
9cf5cf5a XG |
1994 | return 1; |
1995 | need_unsync = true; | |
1996 | } | |
4731d4c7 | 1997 | } |
9cf5cf5a XG |
1998 | if (need_unsync) |
1999 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2000 | return 0; |
2001 | } | |
2002 | ||
d555c333 | 2003 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2004 | unsigned pte_access, int user_fault, |
852e3c19 | 2005 | int write_fault, int dirty, int level, |
c2d0ee46 | 2006 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2007 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2008 | { |
b330aa0c | 2009 | u64 spte, entry = *sptep; |
1e73f9dd | 2010 | int ret = 0; |
64d4d521 | 2011 | |
1c4f1fd6 AK |
2012 | /* |
2013 | * We don't set the accessed bit, since we sometimes want to see | |
2014 | * whether the guest actually used the pte (in order to detect | |
2015 | * demand paging). | |
2016 | */ | |
982c2565 | 2017 | spte = PT_PRESENT_MASK; |
947da538 | 2018 | if (!speculative) |
3201b5d9 | 2019 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
2020 | if (!dirty) |
2021 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
2022 | if (pte_access & ACC_EXEC_MASK) |
2023 | spte |= shadow_x_mask; | |
2024 | else | |
2025 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 2026 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2027 | spte |= shadow_user_mask; |
852e3c19 | 2028 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2029 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2030 | if (tdp_enabled) |
4b12f0de SY |
2031 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2032 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2033 | |
9bdbba13 | 2034 | if (host_writable) |
1403283a | 2035 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2036 | else |
2037 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2038 | |
35149e21 | 2039 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
2040 | |
2041 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
2042 | || (!vcpu->arch.mmu.direct_map && write_fault |
2043 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2044 | |
852e3c19 JR |
2045 | if (level > PT_PAGE_TABLE_LEVEL && |
2046 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2047 | ret = 1; |
be38d276 AK |
2048 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
2049 | goto done; | |
38187c83 MT |
2050 | } |
2051 | ||
1c4f1fd6 | 2052 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2053 | |
c5a78f2b JR |
2054 | if (!vcpu->arch.mmu.direct_map |
2055 | && !(pte_access & ACC_WRITE_MASK)) | |
69325a12 AK |
2056 | spte &= ~PT_USER_MASK; |
2057 | ||
ecc5589f MT |
2058 | /* |
2059 | * Optimization: for pte sync, if spte was writable the hash | |
2060 | * lookup is unnecessary (and expensive). Write protection | |
2061 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2062 | * Same reasoning can be applied to dirty page accounting. | |
2063 | */ | |
8dae4445 | 2064 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2065 | goto set_pte; |
2066 | ||
4731d4c7 | 2067 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2068 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2069 | __func__, gfn); |
1e73f9dd | 2070 | ret = 1; |
1c4f1fd6 | 2071 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2072 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2073 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2074 | } |
2075 | } | |
2076 | ||
1c4f1fd6 AK |
2077 | if (pte_access & ACC_WRITE_MASK) |
2078 | mark_page_dirty(vcpu->kvm, gfn); | |
2079 | ||
38187c83 | 2080 | set_pte: |
b79b93f9 | 2081 | update_spte(sptep, spte); |
b330aa0c XG |
2082 | /* |
2083 | * If we overwrite a writable spte with a read-only one we | |
2084 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2085 | * will find a read-only spte, even though the writable spte | |
2086 | * might be cached on a CPU's TLB. | |
2087 | */ | |
2088 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2089 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2090 | done: |
1e73f9dd MT |
2091 | return ret; |
2092 | } | |
2093 | ||
d555c333 | 2094 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2095 | unsigned pt_access, unsigned pte_access, |
2096 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2097 | int *ptwrite, int level, gfn_t gfn, |
1403283a | 2098 | pfn_t pfn, bool speculative, |
9bdbba13 | 2099 | bool host_writable) |
1e73f9dd MT |
2100 | { |
2101 | int was_rmapped = 0; | |
53a27b39 | 2102 | int rmap_count; |
1e73f9dd MT |
2103 | |
2104 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2105 | " user_fault %d gfn %llx\n", |
d555c333 | 2106 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2107 | write_fault, user_fault, gfn); |
2108 | ||
d555c333 | 2109 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2110 | /* |
2111 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2112 | * the parent of the now unreachable PTE. | |
2113 | */ | |
852e3c19 JR |
2114 | if (level > PT_PAGE_TABLE_LEVEL && |
2115 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2116 | struct kvm_mmu_page *child; |
d555c333 | 2117 | u64 pte = *sptep; |
1e73f9dd MT |
2118 | |
2119 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2120 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2121 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2122 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2123 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2124 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2125 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2126 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2127 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2128 | } else |
2129 | was_rmapped = 1; | |
1e73f9dd | 2130 | } |
852e3c19 | 2131 | |
d555c333 | 2132 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a | 2133 | dirty, level, gfn, pfn, speculative, true, |
9bdbba13 | 2134 | host_writable)) { |
1e73f9dd MT |
2135 | if (write_fault) |
2136 | *ptwrite = 1; | |
5304efde | 2137 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2138 | } |
1e73f9dd | 2139 | |
d555c333 | 2140 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2141 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2142 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2143 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2144 | *sptep, sptep); | |
d555c333 | 2145 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2146 | ++vcpu->kvm->stat.lpages; |
2147 | ||
d555c333 | 2148 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2149 | if (!was_rmapped) { |
44ad9944 | 2150 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2151 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2152 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2153 | } |
9ed5520d | 2154 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2155 | if (speculative) { |
d555c333 | 2156 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2157 | vcpu->arch.last_pte_gfn = gfn; |
2158 | } | |
1c4f1fd6 AK |
2159 | } |
2160 | ||
6aa8b732 AK |
2161 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2162 | { | |
2163 | } | |
2164 | ||
957ed9ef XG |
2165 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2166 | bool no_dirty_log) | |
2167 | { | |
2168 | struct kvm_memory_slot *slot; | |
2169 | unsigned long hva; | |
2170 | ||
5d163b1c | 2171 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef XG |
2172 | if (!slot) { |
2173 | get_page(bad_page); | |
2174 | return page_to_pfn(bad_page); | |
2175 | } | |
2176 | ||
2177 | hva = gfn_to_hva_memslot(slot, gfn); | |
2178 | ||
2179 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2180 | } | |
2181 | ||
2182 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2183 | struct kvm_mmu_page *sp, | |
2184 | u64 *start, u64 *end) | |
2185 | { | |
2186 | struct page *pages[PTE_PREFETCH_NUM]; | |
2187 | unsigned access = sp->role.access; | |
2188 | int i, ret; | |
2189 | gfn_t gfn; | |
2190 | ||
2191 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2192 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2193 | return -1; |
2194 | ||
2195 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2196 | if (ret <= 0) | |
2197 | return -1; | |
2198 | ||
2199 | for (i = 0; i < ret; i++, gfn++, start++) | |
2200 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2201 | access, 0, 0, 1, NULL, | |
2202 | sp->role.level, gfn, | |
2203 | page_to_pfn(pages[i]), true, true); | |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2209 | struct kvm_mmu_page *sp, u64 *sptep) | |
2210 | { | |
2211 | u64 *spte, *start = NULL; | |
2212 | int i; | |
2213 | ||
2214 | WARN_ON(!sp->role.direct); | |
2215 | ||
2216 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2217 | spte = sp->spt + i; | |
2218 | ||
2219 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2220 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2221 | if (!start) | |
2222 | continue; | |
2223 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2224 | break; | |
2225 | start = NULL; | |
2226 | } else if (!start) | |
2227 | start = spte; | |
2228 | } | |
2229 | } | |
2230 | ||
2231 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2232 | { | |
2233 | struct kvm_mmu_page *sp; | |
2234 | ||
2235 | /* | |
2236 | * Since it's no accessed bit on EPT, it's no way to | |
2237 | * distinguish between actually accessed translations | |
2238 | * and prefetched, so disable pte prefetch if EPT is | |
2239 | * enabled. | |
2240 | */ | |
2241 | if (!shadow_accessed_mask) | |
2242 | return; | |
2243 | ||
2244 | sp = page_header(__pa(sptep)); | |
2245 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2246 | return; | |
2247 | ||
2248 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2249 | } | |
2250 | ||
9f652d21 | 2251 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2252 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2253 | bool prefault) | |
140754bc | 2254 | { |
9f652d21 | 2255 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2256 | struct kvm_mmu_page *sp; |
9f652d21 | 2257 | int pt_write = 0; |
140754bc | 2258 | gfn_t pseudo_gfn; |
6aa8b732 | 2259 | |
9f652d21 | 2260 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2261 | if (iterator.level == level) { |
612819c3 MT |
2262 | unsigned pte_access = ACC_ALL; |
2263 | ||
612819c3 | 2264 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
9f652d21 | 2265 | 0, write, 1, &pt_write, |
2ec4739d | 2266 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2267 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2268 | ++vcpu->stat.pf_fixed; |
2269 | break; | |
6aa8b732 AK |
2270 | } |
2271 | ||
9f652d21 | 2272 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2273 | u64 base_addr = iterator.addr; |
2274 | ||
2275 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2276 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2277 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2278 | iterator.level - 1, | |
2279 | 1, ACC_ALL, iterator.sptep); | |
2280 | if (!sp) { | |
2281 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2282 | kvm_release_pfn_clean(pfn); | |
2283 | return -ENOMEM; | |
2284 | } | |
140754bc | 2285 | |
d555c333 AK |
2286 | __set_spte(iterator.sptep, |
2287 | __pa(sp->spt) | |
2288 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
33f91edb XG |
2289 | | shadow_user_mask | shadow_x_mask |
2290 | | shadow_accessed_mask); | |
9f652d21 AK |
2291 | } |
2292 | } | |
2293 | return pt_write; | |
6aa8b732 AK |
2294 | } |
2295 | ||
77db5cbd | 2296 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2297 | { |
77db5cbd HY |
2298 | siginfo_t info; |
2299 | ||
2300 | info.si_signo = SIGBUS; | |
2301 | info.si_errno = 0; | |
2302 | info.si_code = BUS_MCEERR_AR; | |
2303 | info.si_addr = (void __user *)address; | |
2304 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2305 | |
77db5cbd | 2306 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2307 | } |
2308 | ||
2309 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2310 | { | |
2311 | kvm_release_pfn_clean(pfn); | |
2312 | if (is_hwpoison_pfn(pfn)) { | |
77db5cbd | 2313 | kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current); |
bf998156 | 2314 | return 0; |
edba23e5 GN |
2315 | } else if (is_fault_pfn(pfn)) |
2316 | return -EFAULT; | |
2317 | ||
bf998156 HY |
2318 | return 1; |
2319 | } | |
2320 | ||
936a5fe6 AA |
2321 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2322 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2323 | { | |
2324 | pfn_t pfn = *pfnp; | |
2325 | gfn_t gfn = *gfnp; | |
2326 | int level = *levelp; | |
2327 | ||
2328 | /* | |
2329 | * Check if it's a transparent hugepage. If this would be an | |
2330 | * hugetlbfs page, level wouldn't be set to | |
2331 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2332 | * here. | |
2333 | */ | |
2334 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2335 | level == PT_PAGE_TABLE_LEVEL && | |
2336 | PageTransCompound(pfn_to_page(pfn)) && | |
2337 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2338 | unsigned long mask; | |
2339 | /* | |
2340 | * mmu_notifier_retry was successful and we hold the | |
2341 | * mmu_lock here, so the pmd can't become splitting | |
2342 | * from under us, and in turn | |
2343 | * __split_huge_page_refcount() can't run from under | |
2344 | * us and we can safely transfer the refcount from | |
2345 | * PG_tail to PG_head as we switch the pfn to tail to | |
2346 | * head. | |
2347 | */ | |
2348 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2349 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2350 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2351 | if (pfn & mask) { | |
2352 | gfn &= ~mask; | |
2353 | *gfnp = gfn; | |
2354 | kvm_release_pfn_clean(pfn); | |
2355 | pfn &= ~mask; | |
2356 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2357 | BUG(); | |
2358 | *pfnp = pfn; | |
2359 | } | |
2360 | } | |
2361 | } | |
2362 | ||
78b2c54a | 2363 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2364 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2365 | ||
2366 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2367 | bool prefault) |
10589a46 MT |
2368 | { |
2369 | int r; | |
852e3c19 | 2370 | int level; |
936a5fe6 | 2371 | int force_pt_level; |
35149e21 | 2372 | pfn_t pfn; |
e930bffe | 2373 | unsigned long mmu_seq; |
612819c3 | 2374 | bool map_writable; |
aaee2c94 | 2375 | |
936a5fe6 AA |
2376 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2377 | if (likely(!force_pt_level)) { | |
2378 | level = mapping_level(vcpu, gfn); | |
2379 | /* | |
2380 | * This path builds a PAE pagetable - so we can map | |
2381 | * 2mb pages at maximum. Therefore check if the level | |
2382 | * is larger than that. | |
2383 | */ | |
2384 | if (level > PT_DIRECTORY_LEVEL) | |
2385 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2386 | |
936a5fe6 AA |
2387 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2388 | } else | |
2389 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2390 | |
e930bffe | 2391 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2392 | smp_rmb(); |
060c2abe | 2393 | |
78b2c54a | 2394 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2395 | return 0; |
aaee2c94 | 2396 | |
d196e343 | 2397 | /* mmio */ |
bf998156 HY |
2398 | if (is_error_pfn(pfn)) |
2399 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2400 | |
aaee2c94 | 2401 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2402 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2403 | goto out_unlock; | |
eb787d10 | 2404 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2405 | if (likely(!force_pt_level)) |
2406 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2407 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2408 | prefault); | |
aaee2c94 MT |
2409 | spin_unlock(&vcpu->kvm->mmu_lock); |
2410 | ||
aaee2c94 | 2411 | |
10589a46 | 2412 | return r; |
e930bffe AA |
2413 | |
2414 | out_unlock: | |
2415 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2416 | kvm_release_pfn_clean(pfn); | |
2417 | return 0; | |
10589a46 MT |
2418 | } |
2419 | ||
2420 | ||
17ac10ad AK |
2421 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2422 | { | |
2423 | int i; | |
4db35314 | 2424 | struct kvm_mmu_page *sp; |
d98ba053 | 2425 | LIST_HEAD(invalid_list); |
17ac10ad | 2426 | |
ad312c7c | 2427 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2428 | return; |
aaee2c94 | 2429 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2430 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2431 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2432 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2433 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2434 | |
4db35314 AK |
2435 | sp = page_header(root); |
2436 | --sp->root_count; | |
d98ba053 XG |
2437 | if (!sp->root_count && sp->role.invalid) { |
2438 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2439 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2440 | } | |
ad312c7c | 2441 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2442 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2443 | return; |
2444 | } | |
17ac10ad | 2445 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2446 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2447 | |
417726a3 | 2448 | if (root) { |
417726a3 | 2449 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2450 | sp = page_header(root); |
2451 | --sp->root_count; | |
2e53d63a | 2452 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2453 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2454 | &invalid_list); | |
417726a3 | 2455 | } |
ad312c7c | 2456 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2457 | } |
d98ba053 | 2458 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2459 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2460 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2461 | } |
2462 | ||
8986ecc0 MT |
2463 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2464 | { | |
2465 | int ret = 0; | |
2466 | ||
2467 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2468 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2469 | ret = 1; |
2470 | } | |
2471 | ||
2472 | return ret; | |
2473 | } | |
2474 | ||
651dd37a JR |
2475 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2476 | { | |
2477 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2478 | unsigned i; |
651dd37a JR |
2479 | |
2480 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2481 | spin_lock(&vcpu->kvm->mmu_lock); | |
2482 | kvm_mmu_free_some_pages(vcpu); | |
2483 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2484 | 1, ACC_ALL, NULL); | |
2485 | ++sp->root_count; | |
2486 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2487 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2488 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2489 | for (i = 0; i < 4; ++i) { | |
2490 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2491 | ||
2492 | ASSERT(!VALID_PAGE(root)); | |
2493 | spin_lock(&vcpu->kvm->mmu_lock); | |
2494 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2495 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2496 | i << 30, | |
651dd37a JR |
2497 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2498 | NULL); | |
2499 | root = __pa(sp->spt); | |
2500 | ++sp->root_count; | |
2501 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2502 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2503 | } |
6292757f | 2504 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2505 | } else |
2506 | BUG(); | |
2507 | ||
2508 | return 0; | |
2509 | } | |
2510 | ||
2511 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2512 | { |
4db35314 | 2513 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2514 | u64 pdptr, pm_mask; |
2515 | gfn_t root_gfn; | |
2516 | int i; | |
3bb65a22 | 2517 | |
5777ed34 | 2518 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2519 | |
651dd37a JR |
2520 | if (mmu_check_root(vcpu, root_gfn)) |
2521 | return 1; | |
2522 | ||
2523 | /* | |
2524 | * Do we shadow a long mode page table? If so we need to | |
2525 | * write-protect the guests page table root. | |
2526 | */ | |
2527 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2528 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2529 | |
2530 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2531 | |
8facbbff | 2532 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2533 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2534 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2535 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2536 | root = __pa(sp->spt); |
2537 | ++sp->root_count; | |
8facbbff | 2538 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2539 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2540 | return 0; |
17ac10ad | 2541 | } |
f87f9288 | 2542 | |
651dd37a JR |
2543 | /* |
2544 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2545 | * or a PAE 3-level page table. In either case we need to be aware that |
2546 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2547 | */ |
81407ca5 JR |
2548 | pm_mask = PT_PRESENT_MASK; |
2549 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2550 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2551 | ||
17ac10ad | 2552 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2553 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2554 | |
2555 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2556 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2557 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2558 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2559 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2560 | continue; |
2561 | } | |
6de4f3ad | 2562 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2563 | if (mmu_check_root(vcpu, root_gfn)) |
2564 | return 1; | |
5a7388c2 | 2565 | } |
8facbbff | 2566 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2567 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2568 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2569 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2570 | ACC_ALL, NULL); |
4db35314 AK |
2571 | root = __pa(sp->spt); |
2572 | ++sp->root_count; | |
8facbbff AK |
2573 | spin_unlock(&vcpu->kvm->mmu_lock); |
2574 | ||
81407ca5 | 2575 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2576 | } |
6292757f | 2577 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2578 | |
2579 | /* | |
2580 | * If we shadow a 32 bit page table with a long mode page | |
2581 | * table we enter this path. | |
2582 | */ | |
2583 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2584 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2585 | /* | |
2586 | * The additional page necessary for this is only | |
2587 | * allocated on demand. | |
2588 | */ | |
2589 | ||
2590 | u64 *lm_root; | |
2591 | ||
2592 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2593 | if (lm_root == NULL) | |
2594 | return 1; | |
2595 | ||
2596 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2597 | ||
2598 | vcpu->arch.mmu.lm_root = lm_root; | |
2599 | } | |
2600 | ||
2601 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2602 | } | |
2603 | ||
8986ecc0 | 2604 | return 0; |
17ac10ad AK |
2605 | } |
2606 | ||
651dd37a JR |
2607 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2608 | { | |
2609 | if (vcpu->arch.mmu.direct_map) | |
2610 | return mmu_alloc_direct_roots(vcpu); | |
2611 | else | |
2612 | return mmu_alloc_shadow_roots(vcpu); | |
2613 | } | |
2614 | ||
0ba73cda MT |
2615 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2616 | { | |
2617 | int i; | |
2618 | struct kvm_mmu_page *sp; | |
2619 | ||
81407ca5 JR |
2620 | if (vcpu->arch.mmu.direct_map) |
2621 | return; | |
2622 | ||
0ba73cda MT |
2623 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2624 | return; | |
6903074c XG |
2625 | |
2626 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
81407ca5 | 2627 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2628 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2629 | sp = page_header(root); | |
2630 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2631 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2632 | return; |
2633 | } | |
2634 | for (i = 0; i < 4; ++i) { | |
2635 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2636 | ||
8986ecc0 | 2637 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2638 | root &= PT64_BASE_ADDR_MASK; |
2639 | sp = page_header(root); | |
2640 | mmu_sync_children(vcpu, sp); | |
2641 | } | |
2642 | } | |
6903074c | 2643 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2644 | } |
2645 | ||
2646 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2647 | { | |
2648 | spin_lock(&vcpu->kvm->mmu_lock); | |
2649 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2650 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2651 | } |
2652 | ||
1871c602 | 2653 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2654 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2655 | { |
ab9ae313 AK |
2656 | if (exception) |
2657 | exception->error_code = 0; | |
6aa8b732 AK |
2658 | return vaddr; |
2659 | } | |
2660 | ||
6539e738 | 2661 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2662 | u32 access, |
2663 | struct x86_exception *exception) | |
6539e738 | 2664 | { |
ab9ae313 AK |
2665 | if (exception) |
2666 | exception->error_code = 0; | |
6539e738 JR |
2667 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2668 | } | |
2669 | ||
6aa8b732 | 2670 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2671 | u32 error_code, bool prefault) |
6aa8b732 | 2672 | { |
e833240f | 2673 | gfn_t gfn; |
e2dec939 | 2674 | int r; |
6aa8b732 | 2675 | |
b8688d51 | 2676 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2677 | r = mmu_topup_memory_caches(vcpu); |
2678 | if (r) | |
2679 | return r; | |
714b93da | 2680 | |
6aa8b732 | 2681 | ASSERT(vcpu); |
ad312c7c | 2682 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2683 | |
e833240f | 2684 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2685 | |
e833240f | 2686 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2687 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2688 | } |
2689 | ||
7e1fbeac | 2690 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2691 | { |
2692 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2693 | |
7c90705b | 2694 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2695 | arch.gfn = gfn; |
c4806acd | 2696 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2697 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2698 | |
2699 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2700 | } | |
2701 | ||
2702 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2703 | { | |
2704 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2705 | kvm_event_needs_reinjection(vcpu))) | |
2706 | return false; | |
2707 | ||
2708 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2709 | } | |
2710 | ||
78b2c54a | 2711 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2712 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2713 | { |
2714 | bool async; | |
2715 | ||
612819c3 | 2716 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2717 | |
2718 | if (!async) | |
2719 | return false; /* *pfn has correct page already */ | |
2720 | ||
2721 | put_page(pfn_to_page(*pfn)); | |
2722 | ||
78b2c54a | 2723 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2724 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2725 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2726 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2727 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2728 | return true; | |
2729 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2730 | return true; | |
2731 | } | |
2732 | ||
612819c3 | 2733 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2734 | |
2735 | return false; | |
2736 | } | |
2737 | ||
56028d08 | 2738 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2739 | bool prefault) |
fb72d167 | 2740 | { |
35149e21 | 2741 | pfn_t pfn; |
fb72d167 | 2742 | int r; |
852e3c19 | 2743 | int level; |
936a5fe6 | 2744 | int force_pt_level; |
05da4558 | 2745 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2746 | unsigned long mmu_seq; |
612819c3 MT |
2747 | int write = error_code & PFERR_WRITE_MASK; |
2748 | bool map_writable; | |
fb72d167 JR |
2749 | |
2750 | ASSERT(vcpu); | |
2751 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2752 | ||
2753 | r = mmu_topup_memory_caches(vcpu); | |
2754 | if (r) | |
2755 | return r; | |
2756 | ||
936a5fe6 AA |
2757 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2758 | if (likely(!force_pt_level)) { | |
2759 | level = mapping_level(vcpu, gfn); | |
2760 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2761 | } else | |
2762 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 2763 | |
e930bffe | 2764 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2765 | smp_rmb(); |
af585b92 | 2766 | |
78b2c54a | 2767 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2768 | return 0; |
2769 | ||
2770 | /* mmio */ | |
bf998156 HY |
2771 | if (is_error_pfn(pfn)) |
2772 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2773 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2774 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2775 | goto out_unlock; | |
fb72d167 | 2776 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2777 | if (likely(!force_pt_level)) |
2778 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 2779 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2780 | level, gfn, pfn, prefault); |
fb72d167 | 2781 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2782 | |
2783 | return r; | |
e930bffe AA |
2784 | |
2785 | out_unlock: | |
2786 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2787 | kvm_release_pfn_clean(pfn); | |
2788 | return 0; | |
fb72d167 JR |
2789 | } |
2790 | ||
6aa8b732 AK |
2791 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2792 | { | |
17ac10ad | 2793 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2794 | } |
2795 | ||
52fde8df JR |
2796 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2797 | struct kvm_mmu *context) | |
6aa8b732 | 2798 | { |
6aa8b732 AK |
2799 | context->new_cr3 = nonpaging_new_cr3; |
2800 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2801 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2802 | context->free = nonpaging_free; | |
c7addb90 | 2803 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2804 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2805 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2806 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 2807 | context->root_level = 0; |
6aa8b732 | 2808 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2809 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2810 | context->direct_map = true; |
2d48a985 | 2811 | context->nx = false; |
6aa8b732 AK |
2812 | return 0; |
2813 | } | |
2814 | ||
d835dfec | 2815 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2816 | { |
1165f5fe | 2817 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2818 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2819 | } |
2820 | ||
2821 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2822 | { | |
9f8fe504 | 2823 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 2824 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2825 | } |
2826 | ||
5777ed34 JR |
2827 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2828 | { | |
9f8fe504 | 2829 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
2830 | } |
2831 | ||
6389ee94 AK |
2832 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2833 | struct x86_exception *fault) | |
6aa8b732 | 2834 | { |
6389ee94 | 2835 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2836 | } |
2837 | ||
6aa8b732 AK |
2838 | static void paging_free(struct kvm_vcpu *vcpu) |
2839 | { | |
2840 | nonpaging_free(vcpu); | |
2841 | } | |
2842 | ||
3241f22d | 2843 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2844 | { |
2845 | int bit7; | |
2846 | ||
2847 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2848 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2849 | } |
2850 | ||
6aa8b732 AK |
2851 | #define PTTYPE 64 |
2852 | #include "paging_tmpl.h" | |
2853 | #undef PTTYPE | |
2854 | ||
2855 | #define PTTYPE 32 | |
2856 | #include "paging_tmpl.h" | |
2857 | #undef PTTYPE | |
2858 | ||
52fde8df JR |
2859 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2860 | struct kvm_mmu *context, | |
2861 | int level) | |
82725b20 | 2862 | { |
82725b20 DE |
2863 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2864 | u64 exb_bit_rsvd = 0; | |
2865 | ||
2d48a985 | 2866 | if (!context->nx) |
82725b20 DE |
2867 | exb_bit_rsvd = rsvd_bits(63, 63); |
2868 | switch (level) { | |
2869 | case PT32_ROOT_LEVEL: | |
2870 | /* no rsvd bits for 2 level 4K page table entries */ | |
2871 | context->rsvd_bits_mask[0][1] = 0; | |
2872 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2873 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2874 | ||
2875 | if (!is_pse(vcpu)) { | |
2876 | context->rsvd_bits_mask[1][1] = 0; | |
2877 | break; | |
2878 | } | |
2879 | ||
82725b20 DE |
2880 | if (is_cpuid_PSE36()) |
2881 | /* 36bits PSE 4MB page */ | |
2882 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2883 | else | |
2884 | /* 32 bits PSE 4MB page */ | |
2885 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2886 | break; |
2887 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2888 | context->rsvd_bits_mask[0][2] = |
2889 | rsvd_bits(maxphyaddr, 63) | | |
2890 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2891 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2892 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2893 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2894 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2895 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2896 | rsvd_bits(maxphyaddr, 62) | | |
2897 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2898 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2899 | break; |
2900 | case PT64_ROOT_LEVEL: | |
2901 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2902 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2903 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2904 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2905 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2906 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2907 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2908 | rsvd_bits(maxphyaddr, 51); | |
2909 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2910 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2911 | rsvd_bits(maxphyaddr, 51) | | |
2912 | rsvd_bits(13, 29); | |
82725b20 | 2913 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2914 | rsvd_bits(maxphyaddr, 51) | |
2915 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2916 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2917 | break; |
2918 | } | |
2919 | } | |
2920 | ||
52fde8df JR |
2921 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2922 | struct kvm_mmu *context, | |
2923 | int level) | |
6aa8b732 | 2924 | { |
2d48a985 JR |
2925 | context->nx = is_nx(vcpu); |
2926 | ||
52fde8df | 2927 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2928 | |
2929 | ASSERT(is_pae(vcpu)); | |
2930 | context->new_cr3 = paging_new_cr3; | |
2931 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2932 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2933 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2934 | context->sync_page = paging64_sync_page; |
a7052897 | 2935 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 2936 | context->update_pte = paging64_update_pte; |
6aa8b732 | 2937 | context->free = paging_free; |
17ac10ad AK |
2938 | context->root_level = level; |
2939 | context->shadow_root_level = level; | |
17c3ba9d | 2940 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2941 | context->direct_map = false; |
6aa8b732 AK |
2942 | return 0; |
2943 | } | |
2944 | ||
52fde8df JR |
2945 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2946 | struct kvm_mmu *context) | |
17ac10ad | 2947 | { |
52fde8df | 2948 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2949 | } |
2950 | ||
52fde8df JR |
2951 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2952 | struct kvm_mmu *context) | |
6aa8b732 | 2953 | { |
2d48a985 JR |
2954 | context->nx = false; |
2955 | ||
52fde8df | 2956 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2957 | |
2958 | context->new_cr3 = paging_new_cr3; | |
2959 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2960 | context->gva_to_gpa = paging32_gva_to_gpa; |
2961 | context->free = paging_free; | |
c7addb90 | 2962 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2963 | context->sync_page = paging32_sync_page; |
a7052897 | 2964 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 2965 | context->update_pte = paging32_update_pte; |
6aa8b732 AK |
2966 | context->root_level = PT32_ROOT_LEVEL; |
2967 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2968 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2969 | context->direct_map = false; |
6aa8b732 AK |
2970 | return 0; |
2971 | } | |
2972 | ||
52fde8df JR |
2973 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2974 | struct kvm_mmu *context) | |
6aa8b732 | 2975 | { |
52fde8df | 2976 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2977 | } |
2978 | ||
fb72d167 JR |
2979 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2980 | { | |
14dfe855 | 2981 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 2982 | |
c445f8ef | 2983 | context->base_role.word = 0; |
fb72d167 JR |
2984 | context->new_cr3 = nonpaging_new_cr3; |
2985 | context->page_fault = tdp_page_fault; | |
2986 | context->free = nonpaging_free; | |
2987 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2988 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2989 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2990 | context->update_pte = nonpaging_update_pte; |
67253af5 | 2991 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2992 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2993 | context->direct_map = true; |
1c97f0a0 | 2994 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2995 | context->get_cr3 = get_cr3; |
cb659db8 | 2996 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 2997 | context->nx = is_nx(vcpu); |
fb72d167 JR |
2998 | |
2999 | if (!is_paging(vcpu)) { | |
2d48a985 | 3000 | context->nx = false; |
fb72d167 JR |
3001 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3002 | context->root_level = 0; | |
3003 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3004 | context->nx = is_nx(vcpu); |
52fde8df | 3005 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
3006 | context->gva_to_gpa = paging64_gva_to_gpa; |
3007 | context->root_level = PT64_ROOT_LEVEL; | |
3008 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3009 | context->nx = is_nx(vcpu); |
52fde8df | 3010 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
3011 | context->gva_to_gpa = paging64_gva_to_gpa; |
3012 | context->root_level = PT32E_ROOT_LEVEL; | |
3013 | } else { | |
2d48a985 | 3014 | context->nx = false; |
52fde8df | 3015 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
3016 | context->gva_to_gpa = paging32_gva_to_gpa; |
3017 | context->root_level = PT32_ROOT_LEVEL; | |
3018 | } | |
3019 | ||
3020 | return 0; | |
3021 | } | |
3022 | ||
52fde8df | 3023 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3024 | { |
a770f6f2 | 3025 | int r; |
6aa8b732 | 3026 | ASSERT(vcpu); |
ad312c7c | 3027 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3028 | |
3029 | if (!is_paging(vcpu)) | |
52fde8df | 3030 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3031 | else if (is_long_mode(vcpu)) |
52fde8df | 3032 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3033 | else if (is_pae(vcpu)) |
52fde8df | 3034 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3035 | else |
52fde8df | 3036 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3037 | |
5b7e0102 | 3038 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3039 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
52fde8df JR |
3040 | |
3041 | return r; | |
3042 | } | |
3043 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3044 | ||
3045 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3046 | { | |
14dfe855 | 3047 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3048 | |
14dfe855 JR |
3049 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3050 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
3051 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
3052 | |
3053 | return r; | |
6aa8b732 AK |
3054 | } |
3055 | ||
02f59dc9 JR |
3056 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3057 | { | |
3058 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3059 | ||
3060 | g_context->get_cr3 = get_cr3; | |
3061 | g_context->inject_page_fault = kvm_inject_page_fault; | |
3062 | ||
3063 | /* | |
3064 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3065 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3066 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3067 | * functions between mmu and nested_mmu are swapped. | |
3068 | */ | |
3069 | if (!is_paging(vcpu)) { | |
2d48a985 | 3070 | g_context->nx = false; |
02f59dc9 JR |
3071 | g_context->root_level = 0; |
3072 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3073 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3074 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3075 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
3076 | g_context->root_level = PT64_ROOT_LEVEL; | |
3077 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3078 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3079 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3080 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
3081 | g_context->root_level = PT32E_ROOT_LEVEL; | |
3082 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3083 | } else { | |
2d48a985 | 3084 | g_context->nx = false; |
02f59dc9 JR |
3085 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
3086 | g_context->root_level = PT32_ROOT_LEVEL; | |
3087 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
3088 | } | |
3089 | ||
3090 | return 0; | |
3091 | } | |
3092 | ||
fb72d167 JR |
3093 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3094 | { | |
02f59dc9 JR |
3095 | if (mmu_is_nested(vcpu)) |
3096 | return init_kvm_nested_mmu(vcpu); | |
3097 | else if (tdp_enabled) | |
fb72d167 JR |
3098 | return init_kvm_tdp_mmu(vcpu); |
3099 | else | |
3100 | return init_kvm_softmmu(vcpu); | |
3101 | } | |
3102 | ||
6aa8b732 AK |
3103 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3104 | { | |
3105 | ASSERT(vcpu); | |
62ad0755 SY |
3106 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3107 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3108 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3109 | } |
3110 | ||
3111 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3112 | { |
3113 | destroy_kvm_mmu(vcpu); | |
3114 | return init_kvm_mmu(vcpu); | |
3115 | } | |
8668a3c4 | 3116 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3117 | |
3118 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3119 | { |
714b93da AK |
3120 | int r; |
3121 | ||
e2dec939 | 3122 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3123 | if (r) |
3124 | goto out; | |
8986ecc0 | 3125 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3126 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3127 | mmu_sync_roots(vcpu); |
aaee2c94 | 3128 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3129 | if (r) |
3130 | goto out; | |
3662cb1c | 3131 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3132 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3133 | out: |
3134 | return r; | |
6aa8b732 | 3135 | } |
17c3ba9d AK |
3136 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3137 | ||
3138 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3139 | { | |
3140 | mmu_free_roots(vcpu); | |
3141 | } | |
4b16184c | 3142 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3143 | |
09072daf | 3144 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3145 | struct kvm_mmu_page *sp, |
ac1b714e AK |
3146 | u64 *spte) |
3147 | { | |
3148 | u64 pte; | |
3149 | struct kvm_mmu_page *child; | |
3150 | ||
3151 | pte = *spte; | |
c7addb90 | 3152 | if (is_shadow_present_pte(pte)) { |
776e6633 | 3153 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 3154 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
3155 | else { |
3156 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 3157 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
3158 | } |
3159 | } | |
d555c333 | 3160 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
3161 | if (is_large_pte(pte)) |
3162 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
3163 | } |
3164 | ||
0028425f | 3165 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3166 | struct kvm_mmu_page *sp, |
0028425f | 3167 | u64 *spte, |
0f53b5b1 | 3168 | const void *new, unsigned long mmu_seq) |
0028425f | 3169 | { |
30945387 | 3170 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3171 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3172 | return; | |
30945387 | 3173 | } |
0028425f | 3174 | |
4cee5764 | 3175 | ++vcpu->kvm->stat.mmu_pte_updated; |
0f53b5b1 | 3176 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new, mmu_seq); |
0028425f AK |
3177 | } |
3178 | ||
79539cec AK |
3179 | static bool need_remote_flush(u64 old, u64 new) |
3180 | { | |
3181 | if (!is_shadow_present_pte(old)) | |
3182 | return false; | |
3183 | if (!is_shadow_present_pte(new)) | |
3184 | return true; | |
3185 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3186 | return true; | |
3187 | old ^= PT64_NX_MASK; | |
3188 | new ^= PT64_NX_MASK; | |
3189 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3190 | } | |
3191 | ||
0671a8e7 XG |
3192 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3193 | bool remote_flush, bool local_flush) | |
79539cec | 3194 | { |
0671a8e7 XG |
3195 | if (zap_page) |
3196 | return; | |
3197 | ||
3198 | if (remote_flush) | |
79539cec | 3199 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3200 | else if (local_flush) |
79539cec AK |
3201 | kvm_mmu_flush_tlb(vcpu); |
3202 | } | |
3203 | ||
12b7d28f AK |
3204 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3205 | { | |
ad312c7c | 3206 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3207 | |
7b52345e | 3208 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3209 | } |
3210 | ||
1b7fcd32 AK |
3211 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3212 | { | |
3213 | u64 *spte = vcpu->arch.last_pte_updated; | |
3214 | ||
3215 | if (spte | |
3216 | && vcpu->arch.last_pte_gfn == gfn | |
3217 | && shadow_accessed_mask | |
3218 | && !(*spte & shadow_accessed_mask) | |
3219 | && is_shadow_present_pte(*spte)) | |
3220 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3221 | } | |
3222 | ||
09072daf | 3223 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3224 | const u8 *new, int bytes, |
3225 | bool guest_initiated) | |
da4a00f0 | 3226 | { |
9b7a0325 | 3227 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3228 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3229 | struct kvm_mmu_page *sp; |
f41d335a | 3230 | struct hlist_node *node; |
d98ba053 | 3231 | LIST_HEAD(invalid_list); |
0f53b5b1 XG |
3232 | unsigned long mmu_seq; |
3233 | u64 entry, gentry, *spte; | |
3234 | unsigned pte_size, page_offset, misaligned, quadrant, offset; | |
3235 | int level, npte, invlpg_counter, r, flooded = 0; | |
0671a8e7 XG |
3236 | bool remote_flush, local_flush, zap_page; |
3237 | ||
3238 | zap_page = remote_flush = local_flush = false; | |
0f53b5b1 | 3239 | offset = offset_in_page(gpa); |
9b7a0325 | 3240 | |
b8688d51 | 3241 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3242 | |
08e850c6 | 3243 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3244 | |
3245 | /* | |
3246 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3247 | * as the current vcpu paging mode since we update the sptes only |
3248 | * when they have the same mode. | |
72016f3a | 3249 | */ |
08e850c6 | 3250 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3251 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3252 | if (is_pae(vcpu)) { |
3253 | gpa &= ~(gpa_t)7; | |
3254 | bytes = 8; | |
3255 | } | |
3256 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3257 | if (r) |
3258 | gentry = 0; | |
08e850c6 AK |
3259 | new = (const u8 *)&gentry; |
3260 | } | |
3261 | ||
3262 | switch (bytes) { | |
3263 | case 4: | |
3264 | gentry = *(const u32 *)new; | |
3265 | break; | |
3266 | case 8: | |
3267 | gentry = *(const u64 *)new; | |
3268 | break; | |
3269 | default: | |
3270 | gentry = 0; | |
3271 | break; | |
72016f3a AK |
3272 | } |
3273 | ||
0f53b5b1 XG |
3274 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3275 | smp_rmb(); | |
3276 | ||
aaee2c94 | 3277 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3278 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3279 | gentry = 0; | |
eb787d10 | 3280 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3281 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3282 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 | 3283 | if (guest_initiated) { |
1b7fd45c | 3284 | kvm_mmu_access_page(vcpu, gfn); |
ad218f85 MT |
3285 | if (gfn == vcpu->arch.last_pt_write_gfn |
3286 | && !last_updated_pte_accessed(vcpu)) { | |
3287 | ++vcpu->arch.last_pt_write_count; | |
3288 | if (vcpu->arch.last_pt_write_count >= 3) | |
3289 | flooded = 1; | |
3290 | } else { | |
3291 | vcpu->arch.last_pt_write_gfn = gfn; | |
3292 | vcpu->arch.last_pt_write_count = 1; | |
3293 | vcpu->arch.last_pte_updated = NULL; | |
3294 | } | |
86a5ba02 | 3295 | } |
3246af0e | 3296 | |
fa1de2bf | 3297 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3298 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3299 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3300 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3301 | misaligned |= bytes < 4; |
86a5ba02 | 3302 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3303 | /* |
3304 | * Misaligned accesses are too much trouble to fix | |
3305 | * up; also, they usually indicate a page is not used | |
3306 | * as a page table. | |
86a5ba02 AK |
3307 | * |
3308 | * If we're seeing too many writes to a page, | |
3309 | * it may no longer be a page table, or we may be | |
3310 | * forking, in which case it is better to unmap the | |
3311 | * page. | |
0e7bc4b9 AK |
3312 | */ |
3313 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3314 | gpa, bytes, sp->role.word); |
0671a8e7 | 3315 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3316 | &invalid_list); |
4cee5764 | 3317 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3318 | continue; |
3319 | } | |
9b7a0325 | 3320 | page_offset = offset; |
4db35314 | 3321 | level = sp->role.level; |
ac1b714e | 3322 | npte = 1; |
5b7e0102 | 3323 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3324 | page_offset <<= 1; /* 32->64 */ |
3325 | /* | |
3326 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3327 | * only 2MB. So we need to double the offset again | |
3328 | * and zap two pdes instead of one. | |
3329 | */ | |
3330 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3331 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3332 | page_offset <<= 1; |
3333 | npte = 2; | |
3334 | } | |
fce0657f | 3335 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3336 | page_offset &= ~PAGE_MASK; |
4db35314 | 3337 | if (quadrant != sp->role.quadrant) |
fce0657f | 3338 | continue; |
9b7a0325 | 3339 | } |
0671a8e7 | 3340 | local_flush = true; |
4db35314 | 3341 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3342 | while (npte--) { |
79539cec | 3343 | entry = *spte; |
4db35314 | 3344 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3345 | if (gentry && |
3346 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3347 | & mask.word)) | |
0f53b5b1 XG |
3348 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry, |
3349 | mmu_seq); | |
0671a8e7 XG |
3350 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3351 | remote_flush = true; | |
ac1b714e | 3352 | ++spte; |
9b7a0325 | 3353 | } |
9b7a0325 | 3354 | } |
0671a8e7 | 3355 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3356 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3357 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3358 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3359 | } |
3360 | ||
a436036b AK |
3361 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3362 | { | |
10589a46 MT |
3363 | gpa_t gpa; |
3364 | int r; | |
a436036b | 3365 | |
c5a78f2b | 3366 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3367 | return 0; |
3368 | ||
1871c602 | 3369 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3370 | |
aaee2c94 | 3371 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3372 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3373 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3374 | return r; |
a436036b | 3375 | } |
577bdc49 | 3376 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3377 | |
22d95b12 | 3378 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3379 | { |
d98ba053 | 3380 | LIST_HEAD(invalid_list); |
103ad25a | 3381 | |
e0df7b9f | 3382 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3383 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3384 | struct kvm_mmu_page *sp; |
ebeace86 | 3385 | |
f05e70ac | 3386 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3387 | struct kvm_mmu_page, link); |
e0df7b9f | 3388 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3389 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3390 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3391 | } |
3392 | } | |
ebeace86 | 3393 | |
dc25e89e AP |
3394 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3395 | void *insn, int insn_len) | |
3067714c AK |
3396 | { |
3397 | int r; | |
3398 | enum emulation_result er; | |
3399 | ||
56028d08 | 3400 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3401 | if (r < 0) |
3402 | goto out; | |
3403 | ||
3404 | if (!r) { | |
3405 | r = 1; | |
3406 | goto out; | |
3407 | } | |
3408 | ||
b733bfb5 AK |
3409 | r = mmu_topup_memory_caches(vcpu); |
3410 | if (r) | |
3411 | goto out; | |
3412 | ||
dc25e89e | 3413 | er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len); |
3067714c AK |
3414 | |
3415 | switch (er) { | |
3416 | case EMULATE_DONE: | |
3417 | return 1; | |
3418 | case EMULATE_DO_MMIO: | |
3419 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3420 | /* fall through */ |
3067714c | 3421 | case EMULATE_FAIL: |
3f5d18a9 | 3422 | return 0; |
3067714c AK |
3423 | default: |
3424 | BUG(); | |
3425 | } | |
3426 | out: | |
3067714c AK |
3427 | return r; |
3428 | } | |
3429 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3430 | ||
a7052897 MT |
3431 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3432 | { | |
a7052897 | 3433 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3434 | kvm_mmu_flush_tlb(vcpu); |
3435 | ++vcpu->stat.invlpg; | |
3436 | } | |
3437 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3438 | ||
18552672 JR |
3439 | void kvm_enable_tdp(void) |
3440 | { | |
3441 | tdp_enabled = true; | |
3442 | } | |
3443 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3444 | ||
5f4cb662 JR |
3445 | void kvm_disable_tdp(void) |
3446 | { | |
3447 | tdp_enabled = false; | |
3448 | } | |
3449 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3450 | ||
6aa8b732 AK |
3451 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3452 | { | |
ad312c7c | 3453 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3454 | if (vcpu->arch.mmu.lm_root != NULL) |
3455 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3456 | } |
3457 | ||
3458 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3459 | { | |
17ac10ad | 3460 | struct page *page; |
6aa8b732 AK |
3461 | int i; |
3462 | ||
3463 | ASSERT(vcpu); | |
3464 | ||
17ac10ad AK |
3465 | /* |
3466 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3467 | * Therefore we need to allocate shadow page tables in the first | |
3468 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3469 | */ | |
3470 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3471 | if (!page) | |
d7fa6ab2 WY |
3472 | return -ENOMEM; |
3473 | ||
ad312c7c | 3474 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3475 | for (i = 0; i < 4; ++i) |
ad312c7c | 3476 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3477 | |
6aa8b732 | 3478 | return 0; |
6aa8b732 AK |
3479 | } |
3480 | ||
8018c27b | 3481 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3482 | { |
6aa8b732 | 3483 | ASSERT(vcpu); |
ad312c7c | 3484 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3485 | |
8018c27b IM |
3486 | return alloc_mmu_pages(vcpu); |
3487 | } | |
6aa8b732 | 3488 | |
8018c27b IM |
3489 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3490 | { | |
3491 | ASSERT(vcpu); | |
ad312c7c | 3492 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3493 | |
8018c27b | 3494 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3495 | } |
3496 | ||
90cb0529 | 3497 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3498 | { |
4db35314 | 3499 | struct kvm_mmu_page *sp; |
6aa8b732 | 3500 | |
f05e70ac | 3501 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3502 | int i; |
3503 | u64 *pt; | |
3504 | ||
291f26bc | 3505 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3506 | continue; |
3507 | ||
4db35314 | 3508 | pt = sp->spt; |
8234b22e | 3509 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3510 | if (!is_shadow_present_pte(pt[i]) || |
3511 | !is_last_spte(pt[i], sp->role.level)) | |
3512 | continue; | |
3513 | ||
3514 | if (is_large_pte(pt[i])) { | |
8234b22e AK |
3515 | drop_spte(kvm, &pt[i], |
3516 | shadow_trap_nonpresent_pte); | |
3517 | --kvm->stat.lpages; | |
da8dc75f | 3518 | continue; |
8234b22e | 3519 | } |
da8dc75f | 3520 | |
6aa8b732 | 3521 | /* avoid RMW */ |
01c168ac | 3522 | if (is_writable_pte(pt[i])) |
700e1b12 | 3523 | update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK); |
8234b22e | 3524 | } |
6aa8b732 | 3525 | } |
171d595d | 3526 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3527 | } |
37a7d8b0 | 3528 | |
90cb0529 | 3529 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3530 | { |
4db35314 | 3531 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3532 | LIST_HEAD(invalid_list); |
e0fa826f | 3533 | |
aaee2c94 | 3534 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3535 | restart: |
f05e70ac | 3536 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3537 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3538 | goto restart; |
3539 | ||
d98ba053 | 3540 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3541 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3542 | } |
3543 | ||
d98ba053 XG |
3544 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3545 | struct list_head *invalid_list) | |
3ee16c81 IE |
3546 | { |
3547 | struct kvm_mmu_page *page; | |
3548 | ||
3549 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3550 | struct kvm_mmu_page, link); | |
d98ba053 | 3551 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3552 | } |
3553 | ||
7f8275d0 | 3554 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3555 | { |
3556 | struct kvm *kvm; | |
3557 | struct kvm *kvm_freed = NULL; | |
45221ab6 DH |
3558 | |
3559 | if (nr_to_scan == 0) | |
3560 | goto out; | |
3ee16c81 | 3561 | |
e935b837 | 3562 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3563 | |
3564 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3565 | int idx, freed_pages; |
d98ba053 | 3566 | LIST_HEAD(invalid_list); |
3ee16c81 | 3567 | |
f656ce01 | 3568 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3569 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3570 | if (!kvm_freed && nr_to_scan > 0 && |
3571 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3572 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3573 | &invalid_list); | |
3ee16c81 IE |
3574 | kvm_freed = kvm; |
3575 | } | |
3576 | nr_to_scan--; | |
3577 | ||
d98ba053 | 3578 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3579 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3580 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3581 | } |
3582 | if (kvm_freed) | |
3583 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3584 | ||
e935b837 | 3585 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3586 | |
45221ab6 DH |
3587 | out: |
3588 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3589 | } |
3590 | ||
3591 | static struct shrinker mmu_shrinker = { | |
3592 | .shrink = mmu_shrink, | |
3593 | .seeks = DEFAULT_SEEKS * 10, | |
3594 | }; | |
3595 | ||
2ddfd20e | 3596 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3597 | { |
3598 | if (pte_chain_cache) | |
3599 | kmem_cache_destroy(pte_chain_cache); | |
3600 | if (rmap_desc_cache) | |
3601 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3602 | if (mmu_page_header_cache) |
3603 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3604 | } |
3605 | ||
3606 | int kvm_mmu_module_init(void) | |
3607 | { | |
3608 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3609 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3610 | 0, 0, NULL); |
b5a33a75 AK |
3611 | if (!pte_chain_cache) |
3612 | goto nomem; | |
3613 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3614 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3615 | 0, 0, NULL); |
b5a33a75 AK |
3616 | if (!rmap_desc_cache) |
3617 | goto nomem; | |
3618 | ||
d3d25b04 AK |
3619 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3620 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3621 | 0, 0, NULL); |
d3d25b04 AK |
3622 | if (!mmu_page_header_cache) |
3623 | goto nomem; | |
3624 | ||
45bf21a8 WY |
3625 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3626 | goto nomem; | |
3627 | ||
3ee16c81 IE |
3628 | register_shrinker(&mmu_shrinker); |
3629 | ||
b5a33a75 AK |
3630 | return 0; |
3631 | ||
3632 | nomem: | |
3ee16c81 | 3633 | mmu_destroy_caches(); |
b5a33a75 AK |
3634 | return -ENOMEM; |
3635 | } | |
3636 | ||
3ad82a7e ZX |
3637 | /* |
3638 | * Caculate mmu pages needed for kvm. | |
3639 | */ | |
3640 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3641 | { | |
3642 | int i; | |
3643 | unsigned int nr_mmu_pages; | |
3644 | unsigned int nr_pages = 0; | |
bc6678a3 | 3645 | struct kvm_memslots *slots; |
3ad82a7e | 3646 | |
90d83dc3 LJ |
3647 | slots = kvm_memslots(kvm); |
3648 | ||
bc6678a3 MT |
3649 | for (i = 0; i < slots->nmemslots; i++) |
3650 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3651 | |
3652 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3653 | nr_mmu_pages = max(nr_mmu_pages, | |
3654 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3655 | ||
3656 | return nr_mmu_pages; | |
3657 | } | |
3658 | ||
2f333bcb MT |
3659 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3660 | unsigned len) | |
3661 | { | |
3662 | if (len > buffer->len) | |
3663 | return NULL; | |
3664 | return buffer->ptr; | |
3665 | } | |
3666 | ||
3667 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3668 | unsigned len) | |
3669 | { | |
3670 | void *ret; | |
3671 | ||
3672 | ret = pv_mmu_peek_buffer(buffer, len); | |
3673 | if (!ret) | |
3674 | return ret; | |
3675 | buffer->ptr += len; | |
3676 | buffer->len -= len; | |
3677 | buffer->processed += len; | |
3678 | return ret; | |
3679 | } | |
3680 | ||
3681 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3682 | gpa_t addr, gpa_t value) | |
3683 | { | |
3684 | int bytes = 8; | |
3685 | int r; | |
3686 | ||
3687 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3688 | bytes = 4; | |
3689 | ||
3690 | r = mmu_topup_memory_caches(vcpu); | |
3691 | if (r) | |
3692 | return r; | |
3693 | ||
3200f405 | 3694 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3695 | return -EFAULT; |
3696 | ||
3697 | return 1; | |
3698 | } | |
3699 | ||
3700 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3701 | { | |
9f8fe504 | 3702 | (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu)); |
2f333bcb MT |
3703 | return 1; |
3704 | } | |
3705 | ||
3706 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3707 | { | |
3708 | spin_lock(&vcpu->kvm->mmu_lock); | |
3709 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3710 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3711 | return 1; | |
3712 | } | |
3713 | ||
3714 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3715 | struct kvm_pv_mmu_op_buffer *buffer) | |
3716 | { | |
3717 | struct kvm_mmu_op_header *header; | |
3718 | ||
3719 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3720 | if (!header) | |
3721 | return 0; | |
3722 | switch (header->op) { | |
3723 | case KVM_MMU_OP_WRITE_PTE: { | |
3724 | struct kvm_mmu_op_write_pte *wpte; | |
3725 | ||
3726 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3727 | if (!wpte) | |
3728 | return 0; | |
3729 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3730 | wpte->pte_val); | |
3731 | } | |
3732 | case KVM_MMU_OP_FLUSH_TLB: { | |
3733 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3734 | ||
3735 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3736 | if (!ftlb) | |
3737 | return 0; | |
3738 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3739 | } | |
3740 | case KVM_MMU_OP_RELEASE_PT: { | |
3741 | struct kvm_mmu_op_release_pt *rpt; | |
3742 | ||
3743 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3744 | if (!rpt) | |
3745 | return 0; | |
3746 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3747 | } | |
3748 | default: return 0; | |
3749 | } | |
3750 | } | |
3751 | ||
3752 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3753 | gpa_t addr, unsigned long *ret) | |
3754 | { | |
3755 | int r; | |
6ad18fba | 3756 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3757 | |
6ad18fba DH |
3758 | buffer->ptr = buffer->buf; |
3759 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3760 | buffer->processed = 0; | |
2f333bcb | 3761 | |
6ad18fba | 3762 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3763 | if (r) |
3764 | goto out; | |
3765 | ||
6ad18fba DH |
3766 | while (buffer->len) { |
3767 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3768 | if (r < 0) |
3769 | goto out; | |
3770 | if (r == 0) | |
3771 | break; | |
3772 | } | |
3773 | ||
3774 | r = 1; | |
3775 | out: | |
6ad18fba | 3776 | *ret = buffer->processed; |
2f333bcb MT |
3777 | return r; |
3778 | } | |
3779 | ||
94d8b056 MT |
3780 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3781 | { | |
3782 | struct kvm_shadow_walk_iterator iterator; | |
3783 | int nr_sptes = 0; | |
3784 | ||
3785 | spin_lock(&vcpu->kvm->mmu_lock); | |
3786 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3787 | sptes[iterator.level-1] = *iterator.sptep; | |
3788 | nr_sptes++; | |
3789 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3790 | break; | |
3791 | } | |
3792 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3793 | ||
3794 | return nr_sptes; | |
3795 | } | |
3796 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3797 | ||
c42fffe3 XG |
3798 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
3799 | { | |
3800 | ASSERT(vcpu); | |
3801 | ||
3802 | destroy_kvm_mmu(vcpu); | |
3803 | free_mmu_pages(vcpu); | |
3804 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
3805 | } |
3806 | ||
3807 | #ifdef CONFIG_KVM_MMU_AUDIT | |
3808 | #include "mmu_audit.c" | |
3809 | #else | |
3810 | static void mmu_audit_disable(void) { } | |
3811 | #endif | |
3812 | ||
3813 | void kvm_mmu_module_exit(void) | |
3814 | { | |
3815 | mmu_destroy_caches(); | |
3816 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
3817 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
3818 | mmu_audit_disable(); |
3819 | } |