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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c | 63 | #undef MMU_DEBUG |
37a7d8b0 AK |
64 | |
65 | #ifdef MMU_DEBUG | |
66 | ||
67 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
68 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
69 | ||
70 | #else | |
71 | ||
72 | #define pgprintk(x...) do { } while (0) | |
73 | #define rmap_printk(x...) do { } while (0) | |
74 | ||
75 | #endif | |
76 | ||
8b1fe17c | 77 | #ifdef MMU_DEBUG |
476bc001 | 78 | static bool dbg = 0; |
6ada8cca | 79 | module_param(dbg, bool, 0644); |
37a7d8b0 | 80 | #endif |
6aa8b732 | 81 | |
d6c69ee9 YD |
82 | #ifndef MMU_DEBUG |
83 | #define ASSERT(x) do { } while (0) | |
84 | #else | |
6aa8b732 AK |
85 | #define ASSERT(x) \ |
86 | if (!(x)) { \ | |
87 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
88 | __FILE__, __LINE__, #x); \ | |
89 | } | |
d6c69ee9 | 90 | #endif |
6aa8b732 | 91 | |
957ed9ef XG |
92 | #define PTE_PREFETCH_NUM 8 |
93 | ||
00763e41 | 94 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
95 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
96 | ||
6aa8b732 AK |
97 | #define PT64_LEVEL_BITS 9 |
98 | ||
99 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 100 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 101 | |
6aa8b732 AK |
102 | #define PT64_INDEX(address, level)\ |
103 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
104 | ||
105 | ||
106 | #define PT32_LEVEL_BITS 10 | |
107 | ||
108 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 109 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 110 | |
e04da980 JR |
111 | #define PT32_LVL_OFFSET_MASK(level) \ |
112 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
113 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
114 | |
115 | #define PT32_INDEX(address, level)\ | |
116 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
117 | ||
118 | ||
27aba766 | 119 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
120 | #define PT64_DIR_BASE_ADDR_MASK \ |
121 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
122 | #define PT64_LVL_ADDR_MASK(level) \ |
123 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
124 | * PT64_LEVEL_BITS))) - 1)) | |
125 | #define PT64_LVL_OFFSET_MASK(level) \ | |
126 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
128 | |
129 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
130 | #define PT32_DIR_BASE_ADDR_MASK \ | |
131 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
132 | #define PT32_LVL_ADDR_MASK(level) \ |
133 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
134 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 135 | |
53166229 GN |
136 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
137 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 138 | |
fe135d2c AK |
139 | #define ACC_EXEC_MASK 1 |
140 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
141 | #define ACC_USER_MASK PT_USER_MASK | |
142 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
143 | ||
90bb6fc5 AK |
144 | #include <trace/events/kvm.h> |
145 | ||
07420171 AK |
146 | #define CREATE_TRACE_POINTS |
147 | #include "mmutrace.h" | |
148 | ||
49fde340 XG |
149 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
150 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 151 | |
135f8c2b AK |
152 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
153 | ||
220f773a TY |
154 | /* make pte_list_desc fit well in cache line */ |
155 | #define PTE_LIST_EXT 3 | |
156 | ||
53c07b18 XG |
157 | struct pte_list_desc { |
158 | u64 *sptes[PTE_LIST_EXT]; | |
159 | struct pte_list_desc *more; | |
cd4a4e53 AK |
160 | }; |
161 | ||
2d11123a AK |
162 | struct kvm_shadow_walk_iterator { |
163 | u64 addr; | |
164 | hpa_t shadow_addr; | |
2d11123a | 165 | u64 *sptep; |
dd3bfd59 | 166 | int level; |
2d11123a AK |
167 | unsigned index; |
168 | }; | |
169 | ||
170 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
171 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
172 | shadow_walk_okay(&(_walker)); \ | |
173 | shadow_walk_next(&(_walker))) | |
174 | ||
c2a2ac2b XG |
175 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
176 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
177 | shadow_walk_okay(&(_walker)) && \ | |
178 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
179 | __shadow_walk_next(&(_walker), spte)) | |
180 | ||
53c07b18 | 181 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 182 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 183 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 184 | |
7b52345e SY |
185 | static u64 __read_mostly shadow_nx_mask; |
186 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
187 | static u64 __read_mostly shadow_user_mask; | |
188 | static u64 __read_mostly shadow_accessed_mask; | |
189 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
190 | static u64 __read_mostly shadow_mmio_mask; |
191 | ||
192 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 193 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
194 | |
195 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
196 | { | |
197 | shadow_mmio_mask = mmio_mask; | |
198 | } | |
199 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
200 | ||
f2fd125d | 201 | /* |
ee3d1570 DM |
202 | * the low bit of the generation number is always presumed to be zero. |
203 | * This disables mmio caching during memslot updates. The concept is | |
204 | * similar to a seqcount but instead of retrying the access we just punt | |
205 | * and ignore the cache. | |
206 | * | |
207 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
208 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 209 | */ |
ee3d1570 | 210 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
211 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
212 | ||
ee3d1570 DM |
213 | #define MMIO_GEN_SHIFT 20 |
214 | #define MMIO_GEN_LOW_SHIFT 10 | |
215 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 XG |
216 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
217 | #define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1) | |
f2fd125d XG |
218 | |
219 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
220 | { | |
221 | u64 mask; | |
222 | ||
223 | WARN_ON(gen > MMIO_MAX_GEN); | |
224 | ||
225 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
226 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
227 | return mask; | |
228 | } | |
229 | ||
230 | static unsigned int get_mmio_spte_generation(u64 spte) | |
231 | { | |
232 | unsigned int gen; | |
233 | ||
234 | spte &= ~shadow_mmio_mask; | |
235 | ||
236 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
237 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
238 | return gen; | |
239 | } | |
240 | ||
f8f55942 XG |
241 | static unsigned int kvm_current_mmio_generation(struct kvm *kvm) |
242 | { | |
00f034a1 | 243 | return kvm_memslots(kvm)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
244 | } |
245 | ||
f2fd125d XG |
246 | static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn, |
247 | unsigned access) | |
ce88decf | 248 | { |
f8f55942 XG |
249 | unsigned int gen = kvm_current_mmio_generation(kvm); |
250 | u64 mask = generation_mmio_spte_mask(gen); | |
95b0430d | 251 | |
ce88decf | 252 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 253 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
f2fd125d | 254 | |
f8f55942 | 255 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 256 | mmu_spte_set(sptep, mask); |
ce88decf XG |
257 | } |
258 | ||
259 | static bool is_mmio_spte(u64 spte) | |
260 | { | |
261 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
262 | } | |
263 | ||
264 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
265 | { | |
f2fd125d XG |
266 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
267 | return (spte & ~mask) >> PAGE_SHIFT; | |
ce88decf XG |
268 | } |
269 | ||
270 | static unsigned get_mmio_spte_access(u64 spte) | |
271 | { | |
f2fd125d XG |
272 | u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask; |
273 | return (spte & ~mask) & ~PAGE_MASK; | |
ce88decf XG |
274 | } |
275 | ||
f2fd125d XG |
276 | static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
277 | pfn_t pfn, unsigned access) | |
ce88decf XG |
278 | { |
279 | if (unlikely(is_noslot_pfn(pfn))) { | |
f2fd125d | 280 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
281 | return true; |
282 | } | |
283 | ||
284 | return false; | |
285 | } | |
c7addb90 | 286 | |
f8f55942 XG |
287 | static bool check_mmio_spte(struct kvm *kvm, u64 spte) |
288 | { | |
089504c0 XG |
289 | unsigned int kvm_gen, spte_gen; |
290 | ||
291 | kvm_gen = kvm_current_mmio_generation(kvm); | |
292 | spte_gen = get_mmio_spte_generation(spte); | |
293 | ||
294 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
295 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
296 | } |
297 | ||
7b52345e | 298 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 299 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
300 | { |
301 | shadow_user_mask = user_mask; | |
302 | shadow_accessed_mask = accessed_mask; | |
303 | shadow_dirty_mask = dirty_mask; | |
304 | shadow_nx_mask = nx_mask; | |
305 | shadow_x_mask = x_mask; | |
306 | } | |
307 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
308 | ||
6aa8b732 AK |
309 | static int is_cpuid_PSE36(void) |
310 | { | |
311 | return 1; | |
312 | } | |
313 | ||
73b1087e AK |
314 | static int is_nx(struct kvm_vcpu *vcpu) |
315 | { | |
f6801dff | 316 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
317 | } |
318 | ||
c7addb90 AK |
319 | static int is_shadow_present_pte(u64 pte) |
320 | { | |
ce88decf | 321 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
322 | } |
323 | ||
05da4558 MT |
324 | static int is_large_pte(u64 pte) |
325 | { | |
326 | return pte & PT_PAGE_SIZE_MASK; | |
327 | } | |
328 | ||
43a3795a | 329 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 330 | { |
4b1a80fa | 331 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
332 | } |
333 | ||
776e6633 MT |
334 | static int is_last_spte(u64 pte, int level) |
335 | { | |
336 | if (level == PT_PAGE_TABLE_LEVEL) | |
337 | return 1; | |
852e3c19 | 338 | if (is_large_pte(pte)) |
776e6633 MT |
339 | return 1; |
340 | return 0; | |
341 | } | |
342 | ||
35149e21 | 343 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 344 | { |
35149e21 | 345 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
346 | } |
347 | ||
da928521 AK |
348 | static gfn_t pse36_gfn_delta(u32 gpte) |
349 | { | |
350 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
351 | ||
352 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
353 | } | |
354 | ||
603e0651 | 355 | #ifdef CONFIG_X86_64 |
d555c333 | 356 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 357 | { |
603e0651 | 358 | *sptep = spte; |
e663ee64 AK |
359 | } |
360 | ||
603e0651 | 361 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 362 | { |
603e0651 XG |
363 | *sptep = spte; |
364 | } | |
365 | ||
366 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
367 | { | |
368 | return xchg(sptep, spte); | |
369 | } | |
c2a2ac2b XG |
370 | |
371 | static u64 __get_spte_lockless(u64 *sptep) | |
372 | { | |
373 | return ACCESS_ONCE(*sptep); | |
374 | } | |
ce88decf XG |
375 | |
376 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
377 | { | |
378 | /* It is valid if the spte is zapped. */ | |
379 | return spte == 0ull; | |
380 | } | |
a9221dd5 | 381 | #else |
603e0651 XG |
382 | union split_spte { |
383 | struct { | |
384 | u32 spte_low; | |
385 | u32 spte_high; | |
386 | }; | |
387 | u64 spte; | |
388 | }; | |
a9221dd5 | 389 | |
c2a2ac2b XG |
390 | static void count_spte_clear(u64 *sptep, u64 spte) |
391 | { | |
392 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
393 | ||
394 | if (is_shadow_present_pte(spte)) | |
395 | return; | |
396 | ||
397 | /* Ensure the spte is completely set before we increase the count */ | |
398 | smp_wmb(); | |
399 | sp->clear_spte_count++; | |
400 | } | |
401 | ||
603e0651 XG |
402 | static void __set_spte(u64 *sptep, u64 spte) |
403 | { | |
404 | union split_spte *ssptep, sspte; | |
a9221dd5 | 405 | |
603e0651 XG |
406 | ssptep = (union split_spte *)sptep; |
407 | sspte = (union split_spte)spte; | |
408 | ||
409 | ssptep->spte_high = sspte.spte_high; | |
410 | ||
411 | /* | |
412 | * If we map the spte from nonpresent to present, We should store | |
413 | * the high bits firstly, then set present bit, so cpu can not | |
414 | * fetch this spte while we are setting the spte. | |
415 | */ | |
416 | smp_wmb(); | |
417 | ||
418 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
419 | } |
420 | ||
603e0651 XG |
421 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
422 | { | |
423 | union split_spte *ssptep, sspte; | |
424 | ||
425 | ssptep = (union split_spte *)sptep; | |
426 | sspte = (union split_spte)spte; | |
427 | ||
428 | ssptep->spte_low = sspte.spte_low; | |
429 | ||
430 | /* | |
431 | * If we map the spte from present to nonpresent, we should clear | |
432 | * present bit firstly to avoid vcpu fetch the old high bits. | |
433 | */ | |
434 | smp_wmb(); | |
435 | ||
436 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 437 | count_spte_clear(sptep, spte); |
603e0651 XG |
438 | } |
439 | ||
440 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
441 | { | |
442 | union split_spte *ssptep, sspte, orig; | |
443 | ||
444 | ssptep = (union split_spte *)sptep; | |
445 | sspte = (union split_spte)spte; | |
446 | ||
447 | /* xchg acts as a barrier before the setting of the high bits */ | |
448 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
449 | orig.spte_high = ssptep->spte_high; |
450 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 451 | count_spte_clear(sptep, spte); |
603e0651 XG |
452 | |
453 | return orig.spte; | |
454 | } | |
c2a2ac2b XG |
455 | |
456 | /* | |
457 | * The idea using the light way get the spte on x86_32 guest is from | |
458 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
459 | * |
460 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
461 | * coalesces them and we are running out of the MMU lock. Therefore | |
462 | * we need to protect against in-progress updates of the spte. | |
463 | * | |
464 | * Reading the spte while an update is in progress may get the old value | |
465 | * for the high part of the spte. The race is fine for a present->non-present | |
466 | * change (because the high part of the spte is ignored for non-present spte), | |
467 | * but for a present->present change we must reread the spte. | |
468 | * | |
469 | * All such changes are done in two steps (present->non-present and | |
470 | * non-present->present), hence it is enough to count the number of | |
471 | * present->non-present updates: if it changed while reading the spte, | |
472 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
473 | */ |
474 | static u64 __get_spte_lockless(u64 *sptep) | |
475 | { | |
476 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
477 | union split_spte spte, *orig = (union split_spte *)sptep; | |
478 | int count; | |
479 | ||
480 | retry: | |
481 | count = sp->clear_spte_count; | |
482 | smp_rmb(); | |
483 | ||
484 | spte.spte_low = orig->spte_low; | |
485 | smp_rmb(); | |
486 | ||
487 | spte.spte_high = orig->spte_high; | |
488 | smp_rmb(); | |
489 | ||
490 | if (unlikely(spte.spte_low != orig->spte_low || | |
491 | count != sp->clear_spte_count)) | |
492 | goto retry; | |
493 | ||
494 | return spte.spte; | |
495 | } | |
ce88decf XG |
496 | |
497 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
498 | { | |
499 | union split_spte sspte = (union split_spte)spte; | |
500 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
501 | ||
502 | /* It is valid if the spte is zapped. */ | |
503 | if (spte == 0ull) | |
504 | return true; | |
505 | ||
506 | /* It is valid if the spte is being zapped. */ | |
507 | if (sspte.spte_low == 0ull && | |
508 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
509 | return true; | |
510 | ||
511 | return false; | |
512 | } | |
603e0651 XG |
513 | #endif |
514 | ||
c7ba5b48 XG |
515 | static bool spte_is_locklessly_modifiable(u64 spte) |
516 | { | |
feb3eb70 GN |
517 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
518 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
519 | } |
520 | ||
8672b721 XG |
521 | static bool spte_has_volatile_bits(u64 spte) |
522 | { | |
c7ba5b48 XG |
523 | /* |
524 | * Always atomicly update spte if it can be updated | |
525 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
526 | * also, it can help us to get a stable is_writable_pte() | |
527 | * to ensure tlb flush is not missed. | |
528 | */ | |
529 | if (spte_is_locklessly_modifiable(spte)) | |
530 | return true; | |
531 | ||
8672b721 XG |
532 | if (!shadow_accessed_mask) |
533 | return false; | |
534 | ||
535 | if (!is_shadow_present_pte(spte)) | |
536 | return false; | |
537 | ||
4132779b XG |
538 | if ((spte & shadow_accessed_mask) && |
539 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
540 | return false; |
541 | ||
542 | return true; | |
543 | } | |
544 | ||
4132779b XG |
545 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
546 | { | |
547 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
548 | } | |
549 | ||
1df9f2dc XG |
550 | /* Rules for using mmu_spte_set: |
551 | * Set the sptep from nonpresent to present. | |
552 | * Note: the sptep being assigned *must* be either not present | |
553 | * or in a state where the hardware will not attempt to update | |
554 | * the spte. | |
555 | */ | |
556 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
557 | { | |
558 | WARN_ON(is_shadow_present_pte(*sptep)); | |
559 | __set_spte(sptep, new_spte); | |
560 | } | |
561 | ||
562 | /* Rules for using mmu_spte_update: | |
563 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
564 | * |
565 | * Whenever we overwrite a writable spte with a read-only one we | |
566 | * should flush remote TLBs. Otherwise rmap_write_protect | |
567 | * will find a read-only spte, even though the writable spte | |
568 | * might be cached on a CPU's TLB, the return value indicates this | |
569 | * case. | |
1df9f2dc | 570 | */ |
6e7d0354 | 571 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 572 | { |
c7ba5b48 | 573 | u64 old_spte = *sptep; |
6e7d0354 | 574 | bool ret = false; |
4132779b XG |
575 | |
576 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 577 | |
6e7d0354 XG |
578 | if (!is_shadow_present_pte(old_spte)) { |
579 | mmu_spte_set(sptep, new_spte); | |
580 | return ret; | |
581 | } | |
4132779b | 582 | |
c7ba5b48 | 583 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 584 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 585 | else |
603e0651 | 586 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 587 | |
c7ba5b48 XG |
588 | /* |
589 | * For the spte updated out of mmu-lock is safe, since | |
590 | * we always atomicly update it, see the comments in | |
591 | * spte_has_volatile_bits(). | |
592 | */ | |
7f31c959 XG |
593 | if (spte_is_locklessly_modifiable(old_spte) && |
594 | !is_writable_pte(new_spte)) | |
6e7d0354 XG |
595 | ret = true; |
596 | ||
4132779b | 597 | if (!shadow_accessed_mask) |
6e7d0354 | 598 | return ret; |
4132779b XG |
599 | |
600 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
601 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
602 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
603 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
604 | |
605 | return ret; | |
b79b93f9 AK |
606 | } |
607 | ||
1df9f2dc XG |
608 | /* |
609 | * Rules for using mmu_spte_clear_track_bits: | |
610 | * It sets the sptep from present to nonpresent, and track the | |
611 | * state bits, it is used to clear the last level sptep. | |
612 | */ | |
613 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
614 | { | |
615 | pfn_t pfn; | |
616 | u64 old_spte = *sptep; | |
617 | ||
618 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 619 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 620 | else |
603e0651 | 621 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
622 | |
623 | if (!is_rmap_spte(old_spte)) | |
624 | return 0; | |
625 | ||
626 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
627 | |
628 | /* | |
629 | * KVM does not hold the refcount of the page used by | |
630 | * kvm mmu, before reclaiming the page, we should | |
631 | * unmap it from mmu first. | |
632 | */ | |
633 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
634 | ||
1df9f2dc XG |
635 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
636 | kvm_set_pfn_accessed(pfn); | |
637 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
638 | kvm_set_pfn_dirty(pfn); | |
639 | return 1; | |
640 | } | |
641 | ||
642 | /* | |
643 | * Rules for using mmu_spte_clear_no_track: | |
644 | * Directly clear spte without caring the state bits of sptep, | |
645 | * it is used to set the upper level spte. | |
646 | */ | |
647 | static void mmu_spte_clear_no_track(u64 *sptep) | |
648 | { | |
603e0651 | 649 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
650 | } |
651 | ||
c2a2ac2b XG |
652 | static u64 mmu_spte_get_lockless(u64 *sptep) |
653 | { | |
654 | return __get_spte_lockless(sptep); | |
655 | } | |
656 | ||
657 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
658 | { | |
c142786c AK |
659 | /* |
660 | * Prevent page table teardown by making any free-er wait during | |
661 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
662 | */ | |
663 | local_irq_disable(); | |
664 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
665 | /* | |
666 | * Make sure a following spte read is not reordered ahead of the write | |
667 | * to vcpu->mode. | |
668 | */ | |
669 | smp_mb(); | |
c2a2ac2b XG |
670 | } |
671 | ||
672 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
673 | { | |
c142786c AK |
674 | /* |
675 | * Make sure the write to vcpu->mode is not reordered in front of | |
676 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
677 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
678 | */ | |
679 | smp_mb(); | |
680 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
681 | local_irq_enable(); | |
c2a2ac2b XG |
682 | } |
683 | ||
e2dec939 | 684 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 685 | struct kmem_cache *base_cache, int min) |
714b93da AK |
686 | { |
687 | void *obj; | |
688 | ||
689 | if (cache->nobjs >= min) | |
e2dec939 | 690 | return 0; |
714b93da | 691 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 692 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 693 | if (!obj) |
e2dec939 | 694 | return -ENOMEM; |
714b93da AK |
695 | cache->objects[cache->nobjs++] = obj; |
696 | } | |
e2dec939 | 697 | return 0; |
714b93da AK |
698 | } |
699 | ||
f759e2b4 XG |
700 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
701 | { | |
702 | return cache->nobjs; | |
703 | } | |
704 | ||
e8ad9a70 XG |
705 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
706 | struct kmem_cache *cache) | |
714b93da AK |
707 | { |
708 | while (mc->nobjs) | |
e8ad9a70 | 709 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
710 | } |
711 | ||
c1158e63 | 712 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 713 | int min) |
c1158e63 | 714 | { |
842f22ed | 715 | void *page; |
c1158e63 AK |
716 | |
717 | if (cache->nobjs >= min) | |
718 | return 0; | |
719 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 720 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
721 | if (!page) |
722 | return -ENOMEM; | |
842f22ed | 723 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
724 | } |
725 | return 0; | |
726 | } | |
727 | ||
728 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
729 | { | |
730 | while (mc->nobjs) | |
c4d198d5 | 731 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
732 | } |
733 | ||
2e3e5882 | 734 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 735 | { |
e2dec939 AK |
736 | int r; |
737 | ||
53c07b18 | 738 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 739 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
740 | if (r) |
741 | goto out; | |
ad312c7c | 742 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
743 | if (r) |
744 | goto out; | |
ad312c7c | 745 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 746 | mmu_page_header_cache, 4); |
e2dec939 AK |
747 | out: |
748 | return r; | |
714b93da AK |
749 | } |
750 | ||
751 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
752 | { | |
53c07b18 XG |
753 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
754 | pte_list_desc_cache); | |
ad312c7c | 755 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
756 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
757 | mmu_page_header_cache); | |
714b93da AK |
758 | } |
759 | ||
80feb89a | 760 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
761 | { |
762 | void *p; | |
763 | ||
764 | BUG_ON(!mc->nobjs); | |
765 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
766 | return p; |
767 | } | |
768 | ||
53c07b18 | 769 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 770 | { |
80feb89a | 771 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
772 | } |
773 | ||
53c07b18 | 774 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 775 | { |
53c07b18 | 776 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
777 | } |
778 | ||
2032a93d LJ |
779 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
780 | { | |
781 | if (!sp->role.direct) | |
782 | return sp->gfns[index]; | |
783 | ||
784 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
785 | } | |
786 | ||
787 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
788 | { | |
789 | if (sp->role.direct) | |
790 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
791 | else | |
792 | sp->gfns[index] = gfn; | |
793 | } | |
794 | ||
05da4558 | 795 | /* |
d4dbf470 TY |
796 | * Return the pointer to the large page information for a given gfn, |
797 | * handling slots that are not large page aligned. | |
05da4558 | 798 | */ |
d4dbf470 TY |
799 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
800 | struct kvm_memory_slot *slot, | |
801 | int level) | |
05da4558 MT |
802 | { |
803 | unsigned long idx; | |
804 | ||
fb03cb6f | 805 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 806 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
807 | } |
808 | ||
809 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
810 | { | |
d25797b2 | 811 | struct kvm_memory_slot *slot; |
d4dbf470 | 812 | struct kvm_lpage_info *linfo; |
d25797b2 | 813 | int i; |
05da4558 | 814 | |
a1f4d395 | 815 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
816 | for (i = PT_DIRECTORY_LEVEL; |
817 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
818 | linfo = lpage_info_slot(gfn, slot, i); |
819 | linfo->write_count += 1; | |
d25797b2 | 820 | } |
332b207d | 821 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
822 | } |
823 | ||
824 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
825 | { | |
d25797b2 | 826 | struct kvm_memory_slot *slot; |
d4dbf470 | 827 | struct kvm_lpage_info *linfo; |
d25797b2 | 828 | int i; |
05da4558 | 829 | |
a1f4d395 | 830 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
831 | for (i = PT_DIRECTORY_LEVEL; |
832 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
833 | linfo = lpage_info_slot(gfn, slot, i); |
834 | linfo->write_count -= 1; | |
835 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 836 | } |
332b207d | 837 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
838 | } |
839 | ||
d25797b2 JR |
840 | static int has_wrprotected_page(struct kvm *kvm, |
841 | gfn_t gfn, | |
842 | int level) | |
05da4558 | 843 | { |
2843099f | 844 | struct kvm_memory_slot *slot; |
d4dbf470 | 845 | struct kvm_lpage_info *linfo; |
05da4558 | 846 | |
a1f4d395 | 847 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 848 | if (slot) { |
d4dbf470 TY |
849 | linfo = lpage_info_slot(gfn, slot, level); |
850 | return linfo->write_count; | |
05da4558 MT |
851 | } |
852 | ||
853 | return 1; | |
854 | } | |
855 | ||
d25797b2 | 856 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 857 | { |
8f0b1ab6 | 858 | unsigned long page_size; |
d25797b2 | 859 | int i, ret = 0; |
05da4558 | 860 | |
8f0b1ab6 | 861 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 862 | |
d25797b2 JR |
863 | for (i = PT_PAGE_TABLE_LEVEL; |
864 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
865 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
866 | ret = i; | |
867 | else | |
868 | break; | |
869 | } | |
870 | ||
4c2155ce | 871 | return ret; |
05da4558 MT |
872 | } |
873 | ||
5d163b1c XG |
874 | static struct kvm_memory_slot * |
875 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
876 | bool no_dirty_log) | |
05da4558 MT |
877 | { |
878 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
879 | |
880 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
881 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
882 | (no_dirty_log && slot->dirty_bitmap)) | |
883 | slot = NULL; | |
884 | ||
885 | return slot; | |
886 | } | |
887 | ||
888 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
889 | { | |
a0a8eaba | 890 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
891 | } |
892 | ||
893 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
894 | { | |
895 | int host_level, level, max_level; | |
05da4558 | 896 | |
d25797b2 JR |
897 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
898 | ||
899 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
900 | return host_level; | |
901 | ||
55dd98c3 | 902 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
903 | |
904 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
905 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
906 | break; | |
d25797b2 JR |
907 | |
908 | return level - 1; | |
05da4558 MT |
909 | } |
910 | ||
290fc38d | 911 | /* |
53c07b18 | 912 | * Pte mapping structures: |
cd4a4e53 | 913 | * |
53c07b18 | 914 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 915 | * |
53c07b18 XG |
916 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
917 | * pte_list_desc containing more mappings. | |
53a27b39 | 918 | * |
53c07b18 | 919 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
920 | * the spte was not added. |
921 | * | |
cd4a4e53 | 922 | */ |
53c07b18 XG |
923 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
924 | unsigned long *pte_list) | |
cd4a4e53 | 925 | { |
53c07b18 | 926 | struct pte_list_desc *desc; |
53a27b39 | 927 | int i, count = 0; |
cd4a4e53 | 928 | |
53c07b18 XG |
929 | if (!*pte_list) { |
930 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
931 | *pte_list = (unsigned long)spte; | |
932 | } else if (!(*pte_list & 1)) { | |
933 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
934 | desc = mmu_alloc_pte_list_desc(vcpu); | |
935 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 936 | desc->sptes[1] = spte; |
53c07b18 | 937 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 938 | ++count; |
cd4a4e53 | 939 | } else { |
53c07b18 XG |
940 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
941 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
942 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 943 | desc = desc->more; |
53c07b18 | 944 | count += PTE_LIST_EXT; |
53a27b39 | 945 | } |
53c07b18 XG |
946 | if (desc->sptes[PTE_LIST_EXT-1]) { |
947 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
948 | desc = desc->more; |
949 | } | |
d555c333 | 950 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 951 | ++count; |
d555c333 | 952 | desc->sptes[i] = spte; |
cd4a4e53 | 953 | } |
53a27b39 | 954 | return count; |
cd4a4e53 AK |
955 | } |
956 | ||
53c07b18 XG |
957 | static void |
958 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
959 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
960 | { |
961 | int j; | |
962 | ||
53c07b18 | 963 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 964 | ; |
d555c333 AK |
965 | desc->sptes[i] = desc->sptes[j]; |
966 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
967 | if (j != 0) |
968 | return; | |
969 | if (!prev_desc && !desc->more) | |
53c07b18 | 970 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
971 | else |
972 | if (prev_desc) | |
973 | prev_desc->more = desc->more; | |
974 | else | |
53c07b18 XG |
975 | *pte_list = (unsigned long)desc->more | 1; |
976 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
977 | } |
978 | ||
53c07b18 | 979 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 980 | { |
53c07b18 XG |
981 | struct pte_list_desc *desc; |
982 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
983 | int i; |
984 | ||
53c07b18 XG |
985 | if (!*pte_list) { |
986 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 987 | BUG(); |
53c07b18 XG |
988 | } else if (!(*pte_list & 1)) { |
989 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
990 | if ((u64 *)*pte_list != spte) { | |
991 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
992 | BUG(); |
993 | } | |
53c07b18 | 994 | *pte_list = 0; |
cd4a4e53 | 995 | } else { |
53c07b18 XG |
996 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
997 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
998 | prev_desc = NULL; |
999 | while (desc) { | |
53c07b18 | 1000 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 1001 | if (desc->sptes[i] == spte) { |
53c07b18 | 1002 | pte_list_desc_remove_entry(pte_list, |
714b93da | 1003 | desc, i, |
cd4a4e53 AK |
1004 | prev_desc); |
1005 | return; | |
1006 | } | |
1007 | prev_desc = desc; | |
1008 | desc = desc->more; | |
1009 | } | |
53c07b18 | 1010 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1011 | BUG(); |
1012 | } | |
1013 | } | |
1014 | ||
67052b35 XG |
1015 | typedef void (*pte_list_walk_fn) (u64 *spte); |
1016 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
1017 | { | |
1018 | struct pte_list_desc *desc; | |
1019 | int i; | |
1020 | ||
1021 | if (!*pte_list) | |
1022 | return; | |
1023 | ||
1024 | if (!(*pte_list & 1)) | |
1025 | return fn((u64 *)*pte_list); | |
1026 | ||
1027 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
1028 | while (desc) { | |
1029 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
1030 | fn(desc->sptes[i]); | |
1031 | desc = desc->more; | |
1032 | } | |
1033 | } | |
1034 | ||
9373e2c0 | 1035 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 1036 | struct kvm_memory_slot *slot) |
53c07b18 | 1037 | { |
77d11309 | 1038 | unsigned long idx; |
53c07b18 | 1039 | |
77d11309 | 1040 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1041 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1042 | } |
1043 | ||
9b9b1492 TY |
1044 | /* |
1045 | * Take gfn and return the reverse mapping to it. | |
1046 | */ | |
1047 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
1048 | { | |
1049 | struct kvm_memory_slot *slot; | |
1050 | ||
1051 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 1052 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
1053 | } |
1054 | ||
f759e2b4 XG |
1055 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1056 | { | |
1057 | struct kvm_mmu_memory_cache *cache; | |
1058 | ||
1059 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1060 | return mmu_memory_cache_free_objects(cache); | |
1061 | } | |
1062 | ||
53c07b18 XG |
1063 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1064 | { | |
1065 | struct kvm_mmu_page *sp; | |
1066 | unsigned long *rmapp; | |
1067 | ||
53c07b18 XG |
1068 | sp = page_header(__pa(spte)); |
1069 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1070 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1071 | return pte_list_add(vcpu, spte, rmapp); | |
1072 | } | |
1073 | ||
53c07b18 XG |
1074 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1075 | { | |
1076 | struct kvm_mmu_page *sp; | |
1077 | gfn_t gfn; | |
1078 | unsigned long *rmapp; | |
1079 | ||
1080 | sp = page_header(__pa(spte)); | |
1081 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1082 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1083 | pte_list_remove(spte, rmapp); | |
1084 | } | |
1085 | ||
1e3f42f0 TY |
1086 | /* |
1087 | * Used by the following functions to iterate through the sptes linked by a | |
1088 | * rmap. All fields are private and not assumed to be used outside. | |
1089 | */ | |
1090 | struct rmap_iterator { | |
1091 | /* private fields */ | |
1092 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1093 | int pos; /* index of the sptep */ | |
1094 | }; | |
1095 | ||
1096 | /* | |
1097 | * Iteration must be started by this function. This should also be used after | |
1098 | * removing/dropping sptes from the rmap link because in such cases the | |
1099 | * information in the itererator may not be valid. | |
1100 | * | |
1101 | * Returns sptep if found, NULL otherwise. | |
1102 | */ | |
1103 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1104 | { | |
1105 | if (!rmap) | |
1106 | return NULL; | |
1107 | ||
1108 | if (!(rmap & 1)) { | |
1109 | iter->desc = NULL; | |
1110 | return (u64 *)rmap; | |
1111 | } | |
1112 | ||
1113 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1114 | iter->pos = 0; | |
1115 | return iter->desc->sptes[iter->pos]; | |
1116 | } | |
1117 | ||
1118 | /* | |
1119 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1120 | * | |
1121 | * Returns sptep if found, NULL otherwise. | |
1122 | */ | |
1123 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1124 | { | |
1125 | if (iter->desc) { | |
1126 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1127 | u64 *sptep; | |
1128 | ||
1129 | ++iter->pos; | |
1130 | sptep = iter->desc->sptes[iter->pos]; | |
1131 | if (sptep) | |
1132 | return sptep; | |
1133 | } | |
1134 | ||
1135 | iter->desc = iter->desc->more; | |
1136 | ||
1137 | if (iter->desc) { | |
1138 | iter->pos = 0; | |
1139 | /* desc->sptes[0] cannot be NULL */ | |
1140 | return iter->desc->sptes[iter->pos]; | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | return NULL; | |
1145 | } | |
1146 | ||
c3707958 | 1147 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1148 | { |
1df9f2dc | 1149 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1150 | rmap_remove(kvm, sptep); |
be38d276 AK |
1151 | } |
1152 | ||
8e22f955 XG |
1153 | |
1154 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1155 | { | |
1156 | if (is_large_pte(*sptep)) { | |
1157 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1158 | PT_PAGE_TABLE_LEVEL); | |
1159 | drop_spte(kvm, sptep); | |
1160 | --kvm->stat.lpages; | |
1161 | return true; | |
1162 | } | |
1163 | ||
1164 | return false; | |
1165 | } | |
1166 | ||
1167 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1168 | { | |
1169 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1170 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1171 | } | |
1172 | ||
1173 | /* | |
49fde340 | 1174 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1175 | * spte write-protection is caused by protecting shadow page table. |
49fde340 XG |
1176 | * |
1177 | * Note: write protection is difference between drity logging and spte | |
1178 | * protection: | |
1179 | * - for dirty logging, the spte can be set to writable at anytime if | |
1180 | * its dirty bitmap is properly set. | |
1181 | * - for spte protection, the spte can be writable only after unsync-ing | |
1182 | * shadow page. | |
8e22f955 | 1183 | * |
c126d94f | 1184 | * Return true if tlb need be flushed. |
8e22f955 | 1185 | */ |
c126d94f | 1186 | static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1187 | { |
1188 | u64 spte = *sptep; | |
1189 | ||
49fde340 XG |
1190 | if (!is_writable_pte(spte) && |
1191 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1192 | return false; |
1193 | ||
1194 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1195 | ||
49fde340 XG |
1196 | if (pt_protect) |
1197 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1198 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1199 | |
c126d94f | 1200 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1201 | } |
1202 | ||
49fde340 | 1203 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1204 | bool pt_protect) |
98348e95 | 1205 | { |
1e3f42f0 TY |
1206 | u64 *sptep; |
1207 | struct rmap_iterator iter; | |
d13bc5b5 | 1208 | bool flush = false; |
374cbac0 | 1209 | |
1e3f42f0 TY |
1210 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1211 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
a0ed4607 | 1212 | |
c126d94f | 1213 | flush |= spte_write_protect(kvm, sptep, pt_protect); |
d13bc5b5 | 1214 | sptep = rmap_get_next(&iter); |
374cbac0 | 1215 | } |
855149aa | 1216 | |
d13bc5b5 | 1217 | return flush; |
a0ed4607 TY |
1218 | } |
1219 | ||
5dc99b23 TY |
1220 | /** |
1221 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1222 | * @kvm: kvm instance | |
1223 | * @slot: slot to protect | |
1224 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1225 | * @mask: indicates which pages we should protect | |
1226 | * | |
1227 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1228 | * logging we do not have any such mappings. | |
1229 | */ | |
1230 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1231 | struct kvm_memory_slot *slot, | |
1232 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1233 | { |
1234 | unsigned long *rmapp; | |
a0ed4607 | 1235 | |
5dc99b23 | 1236 | while (mask) { |
65fbe37c TY |
1237 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1238 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1239 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1240 | |
5dc99b23 TY |
1241 | /* clear the first set bit */ |
1242 | mask &= mask - 1; | |
1243 | } | |
374cbac0 AK |
1244 | } |
1245 | ||
2f84569f | 1246 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1247 | { |
1248 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1249 | unsigned long *rmapp; |
1250 | int i; | |
2f84569f | 1251 | bool write_protected = false; |
95d4c16c TY |
1252 | |
1253 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1254 | |
1255 | for (i = PT_PAGE_TABLE_LEVEL; | |
1256 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1257 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1258 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1259 | } |
1260 | ||
1261 | return write_protected; | |
95d4c16c TY |
1262 | } |
1263 | ||
8a8365c5 | 1264 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1265 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1266 | { |
1e3f42f0 TY |
1267 | u64 *sptep; |
1268 | struct rmap_iterator iter; | |
e930bffe AA |
1269 | int need_tlb_flush = 0; |
1270 | ||
1e3f42f0 TY |
1271 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1272 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1273 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1274 | ||
1275 | drop_spte(kvm, sptep); | |
e930bffe AA |
1276 | need_tlb_flush = 1; |
1277 | } | |
1e3f42f0 | 1278 | |
e930bffe AA |
1279 | return need_tlb_flush; |
1280 | } | |
1281 | ||
8a8365c5 | 1282 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1283 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1284 | { |
1e3f42f0 TY |
1285 | u64 *sptep; |
1286 | struct rmap_iterator iter; | |
3da0dd43 | 1287 | int need_flush = 0; |
1e3f42f0 | 1288 | u64 new_spte; |
3da0dd43 IE |
1289 | pte_t *ptep = (pte_t *)data; |
1290 | pfn_t new_pfn; | |
1291 | ||
1292 | WARN_ON(pte_huge(*ptep)); | |
1293 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1294 | |
1295 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1296 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1297 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1298 | ||
3da0dd43 | 1299 | need_flush = 1; |
1e3f42f0 | 1300 | |
3da0dd43 | 1301 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1302 | drop_spte(kvm, sptep); |
1303 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1304 | } else { |
1e3f42f0 | 1305 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1306 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1307 | ||
1308 | new_spte &= ~PT_WRITABLE_MASK; | |
1309 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1310 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1311 | |
1312 | mmu_spte_clear_track_bits(sptep); | |
1313 | mmu_spte_set(sptep, new_spte); | |
1314 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1315 | } |
1316 | } | |
1e3f42f0 | 1317 | |
3da0dd43 IE |
1318 | if (need_flush) |
1319 | kvm_flush_remote_tlbs(kvm); | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
84504ef3 TY |
1324 | static int kvm_handle_hva_range(struct kvm *kvm, |
1325 | unsigned long start, | |
1326 | unsigned long end, | |
1327 | unsigned long data, | |
1328 | int (*handler)(struct kvm *kvm, | |
1329 | unsigned long *rmapp, | |
048212d0 | 1330 | struct kvm_memory_slot *slot, |
84504ef3 | 1331 | unsigned long data)) |
e930bffe | 1332 | { |
be6ba0f0 | 1333 | int j; |
f395302e | 1334 | int ret = 0; |
bc6678a3 | 1335 | struct kvm_memslots *slots; |
be6ba0f0 | 1336 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1337 | |
90d83dc3 | 1338 | slots = kvm_memslots(kvm); |
e930bffe | 1339 | |
be6ba0f0 | 1340 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1341 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1342 | gfn_t gfn_start, gfn_end; |
e930bffe | 1343 | |
84504ef3 TY |
1344 | hva_start = max(start, memslot->userspace_addr); |
1345 | hva_end = min(end, memslot->userspace_addr + | |
1346 | (memslot->npages << PAGE_SHIFT)); | |
1347 | if (hva_start >= hva_end) | |
1348 | continue; | |
1349 | /* | |
1350 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1351 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1352 | */ |
bcd3ef58 | 1353 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1354 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1355 | |
bcd3ef58 TY |
1356 | for (j = PT_PAGE_TABLE_LEVEL; |
1357 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1358 | unsigned long idx, idx_end; | |
1359 | unsigned long *rmapp; | |
d4dbf470 | 1360 | |
bcd3ef58 TY |
1361 | /* |
1362 | * {idx(page_j) | page_j intersects with | |
1363 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1364 | */ | |
1365 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1366 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1367 | |
bcd3ef58 | 1368 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1369 | |
bcd3ef58 TY |
1370 | for (; idx <= idx_end; ++idx) |
1371 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1372 | } |
1373 | } | |
1374 | ||
f395302e | 1375 | return ret; |
e930bffe AA |
1376 | } |
1377 | ||
84504ef3 TY |
1378 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1379 | unsigned long data, | |
1380 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1381 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1382 | unsigned long data)) |
1383 | { | |
1384 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1385 | } |
1386 | ||
1387 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1388 | { | |
3da0dd43 IE |
1389 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1390 | } | |
1391 | ||
b3ae2096 TY |
1392 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1393 | { | |
1394 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1395 | } | |
1396 | ||
3da0dd43 IE |
1397 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1398 | { | |
8a8365c5 | 1399 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1400 | } |
1401 | ||
8a8365c5 | 1402 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1403 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1404 | { |
1e3f42f0 | 1405 | u64 *sptep; |
79f702a6 | 1406 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1407 | int young = 0; |
1408 | ||
6316e1c8 | 1409 | /* |
3f6d8c8a XH |
1410 | * In case of absence of EPT Access and Dirty Bits supports, |
1411 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1412 | * an EPT mapping, and clearing it if it does. On the next access, |
1413 | * a new EPT mapping will be established. | |
1414 | * This has some overhead, but not as much as the cost of swapping | |
1415 | * out actively used pages or breaking up actively used hugepages. | |
1416 | */ | |
f395302e TY |
1417 | if (!shadow_accessed_mask) { |
1418 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1419 | goto out; | |
1420 | } | |
534e38b4 | 1421 | |
1e3f42f0 TY |
1422 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1423 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1424 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1425 | |
3f6d8c8a | 1426 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1427 | young = 1; |
3f6d8c8a XH |
1428 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1429 | (unsigned long *)sptep); | |
e930bffe | 1430 | } |
e930bffe | 1431 | } |
f395302e TY |
1432 | out: |
1433 | /* @data has hva passed to kvm_age_hva(). */ | |
1434 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1435 | return young; |
1436 | } | |
1437 | ||
8ee53820 | 1438 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1439 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1440 | { |
1e3f42f0 TY |
1441 | u64 *sptep; |
1442 | struct rmap_iterator iter; | |
8ee53820 AA |
1443 | int young = 0; |
1444 | ||
1445 | /* | |
1446 | * If there's no access bit in the secondary pte set by the | |
1447 | * hardware it's up to gup-fast/gup to set the access bit in | |
1448 | * the primary pte or in the page structure. | |
1449 | */ | |
1450 | if (!shadow_accessed_mask) | |
1451 | goto out; | |
1452 | ||
1e3f42f0 TY |
1453 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1454 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1455 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1456 | |
3f6d8c8a | 1457 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1458 | young = 1; |
1459 | break; | |
1460 | } | |
8ee53820 AA |
1461 | } |
1462 | out: | |
1463 | return young; | |
1464 | } | |
1465 | ||
53a27b39 MT |
1466 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1467 | ||
852e3c19 | 1468 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1469 | { |
1470 | unsigned long *rmapp; | |
852e3c19 JR |
1471 | struct kvm_mmu_page *sp; |
1472 | ||
1473 | sp = page_header(__pa(spte)); | |
53a27b39 | 1474 | |
852e3c19 | 1475 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1476 | |
048212d0 | 1477 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1478 | kvm_flush_remote_tlbs(vcpu->kvm); |
1479 | } | |
1480 | ||
e930bffe AA |
1481 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1482 | { | |
f395302e | 1483 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1484 | } |
1485 | ||
8ee53820 AA |
1486 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1487 | { | |
1488 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1489 | } | |
1490 | ||
d6c69ee9 | 1491 | #ifdef MMU_DEBUG |
47ad8e68 | 1492 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1493 | { |
139bdb2d AK |
1494 | u64 *pos; |
1495 | u64 *end; | |
1496 | ||
47ad8e68 | 1497 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1498 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1499 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1500 | pos, *pos); |
6aa8b732 | 1501 | return 0; |
139bdb2d | 1502 | } |
6aa8b732 AK |
1503 | return 1; |
1504 | } | |
d6c69ee9 | 1505 | #endif |
6aa8b732 | 1506 | |
45221ab6 DH |
1507 | /* |
1508 | * This value is the sum of all of the kvm instances's | |
1509 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1510 | * aggregate version in order to make the slab shrinker | |
1511 | * faster | |
1512 | */ | |
1513 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1514 | { | |
1515 | kvm->arch.n_used_mmu_pages += nr; | |
1516 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1517 | } | |
1518 | ||
834be0d8 | 1519 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1520 | { |
4db35314 | 1521 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1522 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1523 | list_del(&sp->link); |
1524 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1525 | if (!sp->role.direct) |
1526 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1527 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1528 | } |
1529 | ||
cea0f0e7 AK |
1530 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1531 | { | |
1ae0a13d | 1532 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1533 | } |
1534 | ||
714b93da | 1535 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1536 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1537 | { |
cea0f0e7 AK |
1538 | if (!parent_pte) |
1539 | return; | |
cea0f0e7 | 1540 | |
67052b35 | 1541 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1542 | } |
1543 | ||
4db35314 | 1544 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1545 | u64 *parent_pte) |
1546 | { | |
67052b35 | 1547 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1548 | } |
1549 | ||
bcdd9a93 XG |
1550 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1551 | u64 *parent_pte) | |
1552 | { | |
1553 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1554 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1555 | } |
1556 | ||
67052b35 XG |
1557 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1558 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1559 | { |
67052b35 | 1560 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1561 | |
80feb89a TY |
1562 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1563 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1564 | if (!direct) |
80feb89a | 1565 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1566 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1567 | |
1568 | /* | |
1569 | * The active_mmu_pages list is the FIFO list, do not move the | |
1570 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1571 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1572 | */ | |
67052b35 | 1573 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1574 | sp->parent_ptes = 0; |
1575 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1576 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1577 | return sp; | |
ad8cfbe3 MT |
1578 | } |
1579 | ||
67052b35 | 1580 | static void mark_unsync(u64 *spte); |
1047df1f | 1581 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1582 | { |
67052b35 | 1583 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1584 | } |
1585 | ||
67052b35 | 1586 | static void mark_unsync(u64 *spte) |
0074ff63 | 1587 | { |
67052b35 | 1588 | struct kvm_mmu_page *sp; |
1047df1f | 1589 | unsigned int index; |
0074ff63 | 1590 | |
67052b35 | 1591 | sp = page_header(__pa(spte)); |
1047df1f XG |
1592 | index = spte - sp->spt; |
1593 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1594 | return; |
1047df1f | 1595 | if (sp->unsync_children++) |
0074ff63 | 1596 | return; |
1047df1f | 1597 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1598 | } |
1599 | ||
e8bc217a | 1600 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1601 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1602 | { |
1603 | return 1; | |
1604 | } | |
1605 | ||
a7052897 MT |
1606 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1607 | { | |
1608 | } | |
1609 | ||
0f53b5b1 XG |
1610 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1611 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1612 | const void *pte) |
0f53b5b1 XG |
1613 | { |
1614 | WARN_ON(1); | |
1615 | } | |
1616 | ||
60c8aec6 MT |
1617 | #define KVM_PAGE_ARRAY_NR 16 |
1618 | ||
1619 | struct kvm_mmu_pages { | |
1620 | struct mmu_page_and_offset { | |
1621 | struct kvm_mmu_page *sp; | |
1622 | unsigned int idx; | |
1623 | } page[KVM_PAGE_ARRAY_NR]; | |
1624 | unsigned int nr; | |
1625 | }; | |
1626 | ||
cded19f3 HE |
1627 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1628 | int idx) | |
4731d4c7 | 1629 | { |
60c8aec6 | 1630 | int i; |
4731d4c7 | 1631 | |
60c8aec6 MT |
1632 | if (sp->unsync) |
1633 | for (i=0; i < pvec->nr; i++) | |
1634 | if (pvec->page[i].sp == sp) | |
1635 | return 0; | |
1636 | ||
1637 | pvec->page[pvec->nr].sp = sp; | |
1638 | pvec->page[pvec->nr].idx = idx; | |
1639 | pvec->nr++; | |
1640 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1641 | } | |
1642 | ||
1643 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1644 | struct kvm_mmu_pages *pvec) | |
1645 | { | |
1646 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1647 | |
37178b8b | 1648 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1649 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1650 | u64 ent = sp->spt[i]; |
1651 | ||
7a8f1a74 XG |
1652 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1653 | goto clear_child_bitmap; | |
1654 | ||
1655 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1656 | ||
1657 | if (child->unsync_children) { | |
1658 | if (mmu_pages_add(pvec, child, i)) | |
1659 | return -ENOSPC; | |
1660 | ||
1661 | ret = __mmu_unsync_walk(child, pvec); | |
1662 | if (!ret) | |
1663 | goto clear_child_bitmap; | |
1664 | else if (ret > 0) | |
1665 | nr_unsync_leaf += ret; | |
1666 | else | |
1667 | return ret; | |
1668 | } else if (child->unsync) { | |
1669 | nr_unsync_leaf++; | |
1670 | if (mmu_pages_add(pvec, child, i)) | |
1671 | return -ENOSPC; | |
1672 | } else | |
1673 | goto clear_child_bitmap; | |
1674 | ||
1675 | continue; | |
1676 | ||
1677 | clear_child_bitmap: | |
1678 | __clear_bit(i, sp->unsync_child_bitmap); | |
1679 | sp->unsync_children--; | |
1680 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1681 | } |
1682 | ||
4731d4c7 | 1683 | |
60c8aec6 MT |
1684 | return nr_unsync_leaf; |
1685 | } | |
1686 | ||
1687 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1688 | struct kvm_mmu_pages *pvec) | |
1689 | { | |
1690 | if (!sp->unsync_children) | |
1691 | return 0; | |
1692 | ||
1693 | mmu_pages_add(pvec, sp, 0); | |
1694 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1695 | } |
1696 | ||
4731d4c7 MT |
1697 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1698 | { | |
1699 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1700 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1701 | sp->unsync = 0; |
1702 | --kvm->stat.mmu_unsync; | |
1703 | } | |
1704 | ||
7775834a XG |
1705 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1706 | struct list_head *invalid_list); | |
1707 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1708 | struct list_head *invalid_list); | |
4731d4c7 | 1709 | |
f34d251d XG |
1710 | /* |
1711 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1712 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1713 | * since it has been deleted from active_mmu_pages but still can be found | |
1714 | * at hast list. | |
1715 | * | |
1716 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1717 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1718 | * all the obsolete pages. | |
1719 | */ | |
1044b030 TY |
1720 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1721 | hlist_for_each_entry(_sp, \ | |
1722 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1723 | if ((_sp)->gfn != (_gfn)) {} else | |
1724 | ||
1725 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1726 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1727 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1728 | |
f918b443 | 1729 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1730 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1731 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1732 | { |
5b7e0102 | 1733 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1734 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1735 | return 1; |
1736 | } | |
1737 | ||
f918b443 | 1738 | if (clear_unsync) |
1d9dc7e0 | 1739 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1740 | |
a4a8e6f7 | 1741 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1742 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1743 | return 1; |
1744 | } | |
1745 | ||
1746 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1747 | return 0; |
1748 | } | |
1749 | ||
1d9dc7e0 XG |
1750 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1751 | struct kvm_mmu_page *sp) | |
1752 | { | |
d98ba053 | 1753 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1754 | int ret; |
1755 | ||
d98ba053 | 1756 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1757 | if (ret) |
d98ba053 XG |
1758 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1759 | ||
1d9dc7e0 XG |
1760 | return ret; |
1761 | } | |
1762 | ||
e37fa785 XG |
1763 | #ifdef CONFIG_KVM_MMU_AUDIT |
1764 | #include "mmu_audit.c" | |
1765 | #else | |
1766 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1767 | static void mmu_audit_disable(void) { } | |
1768 | #endif | |
1769 | ||
d98ba053 XG |
1770 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1771 | struct list_head *invalid_list) | |
1d9dc7e0 | 1772 | { |
d98ba053 | 1773 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1774 | } |
1775 | ||
9f1a122f XG |
1776 | /* @gfn should be write-protected at the call site */ |
1777 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1778 | { | |
9f1a122f | 1779 | struct kvm_mmu_page *s; |
d98ba053 | 1780 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1781 | bool flush = false; |
1782 | ||
b67bfe0d | 1783 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1784 | if (!s->unsync) |
9f1a122f XG |
1785 | continue; |
1786 | ||
1787 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1788 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1789 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1790 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1791 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1792 | continue; |
1793 | } | |
9f1a122f XG |
1794 | flush = true; |
1795 | } | |
1796 | ||
d98ba053 | 1797 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1798 | if (flush) |
1799 | kvm_mmu_flush_tlb(vcpu); | |
1800 | } | |
1801 | ||
60c8aec6 MT |
1802 | struct mmu_page_path { |
1803 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1804 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1805 | }; |
1806 | ||
60c8aec6 MT |
1807 | #define for_each_sp(pvec, sp, parents, i) \ |
1808 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1809 | sp = pvec.page[i].sp; \ | |
1810 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1811 | i = mmu_pages_next(&pvec, &parents, i)) | |
1812 | ||
cded19f3 HE |
1813 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1814 | struct mmu_page_path *parents, | |
1815 | int i) | |
60c8aec6 MT |
1816 | { |
1817 | int n; | |
1818 | ||
1819 | for (n = i+1; n < pvec->nr; n++) { | |
1820 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1821 | ||
1822 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1823 | parents->idx[0] = pvec->page[n].idx; | |
1824 | return n; | |
1825 | } | |
1826 | ||
1827 | parents->parent[sp->role.level-2] = sp; | |
1828 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1829 | } | |
1830 | ||
1831 | return n; | |
1832 | } | |
1833 | ||
cded19f3 | 1834 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1835 | { |
60c8aec6 MT |
1836 | struct kvm_mmu_page *sp; |
1837 | unsigned int level = 0; | |
1838 | ||
1839 | do { | |
1840 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1841 | |
60c8aec6 MT |
1842 | sp = parents->parent[level]; |
1843 | if (!sp) | |
1844 | return; | |
1845 | ||
1846 | --sp->unsync_children; | |
1847 | WARN_ON((int)sp->unsync_children < 0); | |
1848 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1849 | level++; | |
1850 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1851 | } |
1852 | ||
60c8aec6 MT |
1853 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1854 | struct mmu_page_path *parents, | |
1855 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1856 | { |
60c8aec6 MT |
1857 | parents->parent[parent->role.level-1] = NULL; |
1858 | pvec->nr = 0; | |
1859 | } | |
4731d4c7 | 1860 | |
60c8aec6 MT |
1861 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1862 | struct kvm_mmu_page *parent) | |
1863 | { | |
1864 | int i; | |
1865 | struct kvm_mmu_page *sp; | |
1866 | struct mmu_page_path parents; | |
1867 | struct kvm_mmu_pages pages; | |
d98ba053 | 1868 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1869 | |
1870 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1871 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1872 | bool protected = false; |
b1a36821 MT |
1873 | |
1874 | for_each_sp(pages, sp, parents, i) | |
1875 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1876 | ||
1877 | if (protected) | |
1878 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1879 | ||
60c8aec6 | 1880 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1881 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1882 | mmu_pages_clear_parents(&parents); |
1883 | } | |
d98ba053 | 1884 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1885 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1886 | kvm_mmu_pages_init(parent, &parents, &pages); |
1887 | } | |
4731d4c7 MT |
1888 | } |
1889 | ||
c3707958 XG |
1890 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1891 | { | |
1892 | int i; | |
1893 | ||
1894 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1895 | sp->spt[i] = 0ull; | |
1896 | } | |
1897 | ||
a30f47cb XG |
1898 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1899 | { | |
1900 | sp->write_flooding_count = 0; | |
1901 | } | |
1902 | ||
1903 | static void clear_sp_write_flooding_count(u64 *spte) | |
1904 | { | |
1905 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1906 | ||
1907 | __clear_sp_write_flooding_count(sp); | |
1908 | } | |
1909 | ||
5304b8d3 XG |
1910 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1911 | { | |
1912 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
1913 | } | |
1914 | ||
cea0f0e7 AK |
1915 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1916 | gfn_t gfn, | |
1917 | gva_t gaddr, | |
1918 | unsigned level, | |
f6e2c02b | 1919 | int direct, |
41074d07 | 1920 | unsigned access, |
f7d9c7b7 | 1921 | u64 *parent_pte) |
cea0f0e7 AK |
1922 | { |
1923 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1924 | unsigned quadrant; |
9f1a122f | 1925 | struct kvm_mmu_page *sp; |
9f1a122f | 1926 | bool need_sync = false; |
cea0f0e7 | 1927 | |
a770f6f2 | 1928 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1929 | role.level = level; |
f6e2c02b | 1930 | role.direct = direct; |
84b0c8c6 | 1931 | if (role.direct) |
5b7e0102 | 1932 | role.cr4_pae = 0; |
41074d07 | 1933 | role.access = access; |
c5a78f2b JR |
1934 | if (!vcpu->arch.mmu.direct_map |
1935 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1936 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1937 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1938 | role.quadrant = quadrant; | |
1939 | } | |
b67bfe0d | 1940 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
1941 | if (is_obsolete_sp(vcpu->kvm, sp)) |
1942 | continue; | |
1943 | ||
7ae680eb XG |
1944 | if (!need_sync && sp->unsync) |
1945 | need_sync = true; | |
4731d4c7 | 1946 | |
7ae680eb XG |
1947 | if (sp->role.word != role.word) |
1948 | continue; | |
4731d4c7 | 1949 | |
7ae680eb XG |
1950 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1951 | break; | |
e02aa901 | 1952 | |
7ae680eb XG |
1953 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1954 | if (sp->unsync_children) { | |
a8eeb04a | 1955 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1956 | kvm_mmu_mark_parents_unsync(sp); |
1957 | } else if (sp->unsync) | |
1958 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1959 | |
a30f47cb | 1960 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1961 | trace_kvm_mmu_get_page(sp, false); |
1962 | return sp; | |
1963 | } | |
dfc5aa00 | 1964 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1965 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1966 | if (!sp) |
1967 | return sp; | |
4db35314 AK |
1968 | sp->gfn = gfn; |
1969 | sp->role = role; | |
7ae680eb XG |
1970 | hlist_add_head(&sp->hash_link, |
1971 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1972 | if (!direct) { |
b1a36821 MT |
1973 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1974 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1975 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1976 | kvm_sync_pages(vcpu, gfn); | |
1977 | ||
4731d4c7 MT |
1978 | account_shadowed(vcpu->kvm, gfn); |
1979 | } | |
5304b8d3 | 1980 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
c3707958 | 1981 | init_shadow_page_table(sp); |
f691fe1d | 1982 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1983 | return sp; |
cea0f0e7 AK |
1984 | } |
1985 | ||
2d11123a AK |
1986 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1987 | struct kvm_vcpu *vcpu, u64 addr) | |
1988 | { | |
1989 | iterator->addr = addr; | |
1990 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1991 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1992 | |
1993 | if (iterator->level == PT64_ROOT_LEVEL && | |
1994 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1995 | !vcpu->arch.mmu.direct_map) | |
1996 | --iterator->level; | |
1997 | ||
2d11123a AK |
1998 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1999 | iterator->shadow_addr | |
2000 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2001 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2002 | --iterator->level; | |
2003 | if (!iterator->shadow_addr) | |
2004 | iterator->level = 0; | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2009 | { | |
2010 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2011 | return false; | |
4d88954d | 2012 | |
2d11123a AK |
2013 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2014 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2015 | return true; | |
2016 | } | |
2017 | ||
c2a2ac2b XG |
2018 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2019 | u64 spte) | |
2d11123a | 2020 | { |
c2a2ac2b | 2021 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2022 | iterator->level = 0; |
2023 | return; | |
2024 | } | |
2025 | ||
c2a2ac2b | 2026 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2027 | --iterator->level; |
2028 | } | |
2029 | ||
c2a2ac2b XG |
2030 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2031 | { | |
2032 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2033 | } | |
2034 | ||
7a1638ce | 2035 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed) |
32ef26a3 AK |
2036 | { |
2037 | u64 spte; | |
2038 | ||
7a1638ce YZ |
2039 | BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK || |
2040 | VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2041 | ||
24db2734 | 2042 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
7a1638ce YZ |
2043 | shadow_user_mask | shadow_x_mask; |
2044 | ||
2045 | if (accessed) | |
2046 | spte |= shadow_accessed_mask; | |
24db2734 | 2047 | |
1df9f2dc | 2048 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
2049 | } |
2050 | ||
a357bd22 AK |
2051 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2052 | unsigned direct_access) | |
2053 | { | |
2054 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2055 | struct kvm_mmu_page *child; | |
2056 | ||
2057 | /* | |
2058 | * For the direct sp, if the guest pte's dirty bit | |
2059 | * changed form clean to dirty, it will corrupt the | |
2060 | * sp's access: allow writable in the read-only sp, | |
2061 | * so we should update the spte at this point to get | |
2062 | * a new sp with the correct access. | |
2063 | */ | |
2064 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2065 | if (child->role.access == direct_access) | |
2066 | return; | |
2067 | ||
bcdd9a93 | 2068 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2069 | kvm_flush_remote_tlbs(vcpu->kvm); |
2070 | } | |
2071 | } | |
2072 | ||
505aef8f | 2073 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2074 | u64 *spte) |
2075 | { | |
2076 | u64 pte; | |
2077 | struct kvm_mmu_page *child; | |
2078 | ||
2079 | pte = *spte; | |
2080 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2081 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2082 | drop_spte(kvm, spte); |
505aef8f XG |
2083 | if (is_large_pte(pte)) |
2084 | --kvm->stat.lpages; | |
2085 | } else { | |
38e3b2b2 | 2086 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2087 | drop_parent_pte(child, spte); |
38e3b2b2 | 2088 | } |
505aef8f XG |
2089 | return true; |
2090 | } | |
2091 | ||
2092 | if (is_mmio_spte(pte)) | |
ce88decf | 2093 | mmu_spte_clear_no_track(spte); |
c3707958 | 2094 | |
505aef8f | 2095 | return false; |
38e3b2b2 XG |
2096 | } |
2097 | ||
90cb0529 | 2098 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2099 | struct kvm_mmu_page *sp) |
a436036b | 2100 | { |
697fe2e2 | 2101 | unsigned i; |
697fe2e2 | 2102 | |
38e3b2b2 XG |
2103 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2104 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2105 | } |
2106 | ||
4db35314 | 2107 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2108 | { |
4db35314 | 2109 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2110 | } |
2111 | ||
31aa2b44 | 2112 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2113 | { |
1e3f42f0 TY |
2114 | u64 *sptep; |
2115 | struct rmap_iterator iter; | |
a436036b | 2116 | |
1e3f42f0 TY |
2117 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2118 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2119 | } |
2120 | ||
60c8aec6 | 2121 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2122 | struct kvm_mmu_page *parent, |
2123 | struct list_head *invalid_list) | |
4731d4c7 | 2124 | { |
60c8aec6 MT |
2125 | int i, zapped = 0; |
2126 | struct mmu_page_path parents; | |
2127 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2128 | |
60c8aec6 | 2129 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2130 | return 0; |
60c8aec6 MT |
2131 | |
2132 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2133 | while (mmu_unsync_walk(parent, &pages)) { | |
2134 | struct kvm_mmu_page *sp; | |
2135 | ||
2136 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2137 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2138 | mmu_pages_clear_parents(&parents); |
77662e00 | 2139 | zapped++; |
60c8aec6 | 2140 | } |
60c8aec6 MT |
2141 | kvm_mmu_pages_init(parent, &parents, &pages); |
2142 | } | |
2143 | ||
2144 | return zapped; | |
4731d4c7 MT |
2145 | } |
2146 | ||
7775834a XG |
2147 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2148 | struct list_head *invalid_list) | |
31aa2b44 | 2149 | { |
4731d4c7 | 2150 | int ret; |
f691fe1d | 2151 | |
7775834a | 2152 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2153 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2154 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2155 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2156 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2157 | |
f6e2c02b | 2158 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2159 | unaccount_shadowed(kvm, sp->gfn); |
5304b8d3 | 2160 | |
4731d4c7 MT |
2161 | if (sp->unsync) |
2162 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2163 | if (!sp->root_count) { |
54a4f023 GJ |
2164 | /* Count self */ |
2165 | ret++; | |
7775834a | 2166 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2167 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2168 | } else { |
5b5c6a5a | 2169 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2170 | |
2171 | /* | |
2172 | * The obsolete pages can not be used on any vcpus. | |
2173 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2174 | */ | |
2175 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2176 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2177 | } |
7775834a XG |
2178 | |
2179 | sp->role.invalid = 1; | |
4731d4c7 | 2180 | return ret; |
a436036b AK |
2181 | } |
2182 | ||
7775834a XG |
2183 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2184 | struct list_head *invalid_list) | |
2185 | { | |
945315b9 | 2186 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2187 | |
2188 | if (list_empty(invalid_list)) | |
2189 | return; | |
2190 | ||
c142786c AK |
2191 | /* |
2192 | * wmb: make sure everyone sees our modifications to the page tables | |
2193 | * rmb: make sure we see changes to vcpu->mode | |
2194 | */ | |
2195 | smp_mb(); | |
4f022648 | 2196 | |
c142786c AK |
2197 | /* |
2198 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2199 | * page table walks. | |
2200 | */ | |
2201 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2202 | |
945315b9 | 2203 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2204 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2205 | kvm_mmu_free_page(sp); |
945315b9 | 2206 | } |
7775834a XG |
2207 | } |
2208 | ||
5da59607 TY |
2209 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2210 | struct list_head *invalid_list) | |
2211 | { | |
2212 | struct kvm_mmu_page *sp; | |
2213 | ||
2214 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2215 | return false; | |
2216 | ||
2217 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2218 | struct kvm_mmu_page, link); | |
2219 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2220 | ||
2221 | return true; | |
2222 | } | |
2223 | ||
82ce2c96 IE |
2224 | /* |
2225 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2226 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2227 | */ |
49d5ca26 | 2228 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2229 | { |
d98ba053 | 2230 | LIST_HEAD(invalid_list); |
82ce2c96 | 2231 | |
b34cb590 TY |
2232 | spin_lock(&kvm->mmu_lock); |
2233 | ||
49d5ca26 | 2234 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2235 | /* Need to free some mmu pages to achieve the goal. */ |
2236 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2237 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2238 | break; | |
82ce2c96 | 2239 | |
aa6bd187 | 2240 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2241 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2242 | } |
82ce2c96 | 2243 | |
49d5ca26 | 2244 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2245 | |
2246 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2247 | } |
2248 | ||
1cb3f3ae | 2249 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2250 | { |
4db35314 | 2251 | struct kvm_mmu_page *sp; |
d98ba053 | 2252 | LIST_HEAD(invalid_list); |
a436036b AK |
2253 | int r; |
2254 | ||
9ad17b10 | 2255 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2256 | r = 0; |
1cb3f3ae | 2257 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2258 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2259 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2260 | sp->role.word); |
2261 | r = 1; | |
f41d335a | 2262 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2263 | } |
d98ba053 | 2264 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2265 | spin_unlock(&kvm->mmu_lock); |
2266 | ||
a436036b | 2267 | return r; |
cea0f0e7 | 2268 | } |
1cb3f3ae | 2269 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2270 | |
74be52e3 SY |
2271 | /* |
2272 | * The function is based on mtrr_type_lookup() in | |
2273 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2274 | */ | |
2275 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2276 | u64 start, u64 end) | |
2277 | { | |
2278 | int i; | |
2279 | u64 base, mask; | |
2280 | u8 prev_match, curr_match; | |
2281 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2282 | ||
2283 | if (!mtrr_state->enabled) | |
2284 | return 0xFF; | |
2285 | ||
2286 | /* Make end inclusive end, instead of exclusive */ | |
2287 | end--; | |
2288 | ||
2289 | /* Look in fixed ranges. Just return the type as per start */ | |
2290 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2291 | int idx; | |
2292 | ||
2293 | if (start < 0x80000) { | |
2294 | idx = 0; | |
2295 | idx += (start >> 16); | |
2296 | return mtrr_state->fixed_ranges[idx]; | |
2297 | } else if (start < 0xC0000) { | |
2298 | idx = 1 * 8; | |
2299 | idx += ((start - 0x80000) >> 14); | |
2300 | return mtrr_state->fixed_ranges[idx]; | |
2301 | } else if (start < 0x1000000) { | |
2302 | idx = 3 * 8; | |
2303 | idx += ((start - 0xC0000) >> 12); | |
2304 | return mtrr_state->fixed_ranges[idx]; | |
2305 | } | |
2306 | } | |
2307 | ||
2308 | /* | |
2309 | * Look in variable ranges | |
2310 | * Look of multiple ranges matching this address and pick type | |
2311 | * as per MTRR precedence | |
2312 | */ | |
2313 | if (!(mtrr_state->enabled & 2)) | |
2314 | return mtrr_state->def_type; | |
2315 | ||
2316 | prev_match = 0xFF; | |
2317 | for (i = 0; i < num_var_ranges; ++i) { | |
2318 | unsigned short start_state, end_state; | |
2319 | ||
2320 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2321 | continue; | |
2322 | ||
2323 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2324 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2325 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2326 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2327 | ||
2328 | start_state = ((start & mask) == (base & mask)); | |
2329 | end_state = ((end & mask) == (base & mask)); | |
2330 | if (start_state != end_state) | |
2331 | return 0xFE; | |
2332 | ||
2333 | if ((start & mask) != (base & mask)) | |
2334 | continue; | |
2335 | ||
2336 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2337 | if (prev_match == 0xFF) { | |
2338 | prev_match = curr_match; | |
2339 | continue; | |
2340 | } | |
2341 | ||
2342 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2343 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2344 | return MTRR_TYPE_UNCACHABLE; | |
2345 | ||
2346 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2347 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2348 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2349 | curr_match == MTRR_TYPE_WRBACK)) { | |
2350 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2351 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2352 | } | |
2353 | ||
2354 | if (prev_match != curr_match) | |
2355 | return MTRR_TYPE_UNCACHABLE; | |
2356 | } | |
2357 | ||
2358 | if (prev_match != 0xFF) | |
2359 | return prev_match; | |
2360 | ||
2361 | return mtrr_state->def_type; | |
2362 | } | |
2363 | ||
4b12f0de | 2364 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2365 | { |
2366 | u8 mtrr; | |
2367 | ||
2368 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2369 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2370 | if (mtrr == 0xfe || mtrr == 0xff) | |
2371 | mtrr = MTRR_TYPE_WRBACK; | |
2372 | return mtrr; | |
2373 | } | |
4b12f0de | 2374 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2375 | |
9cf5cf5a XG |
2376 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2377 | { | |
2378 | trace_kvm_mmu_unsync_page(sp); | |
2379 | ++vcpu->kvm->stat.mmu_unsync; | |
2380 | sp->unsync = 1; | |
2381 | ||
2382 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2383 | } |
2384 | ||
2385 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2386 | { |
4731d4c7 | 2387 | struct kvm_mmu_page *s; |
9cf5cf5a | 2388 | |
b67bfe0d | 2389 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2390 | if (s->unsync) |
4731d4c7 | 2391 | continue; |
9cf5cf5a XG |
2392 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2393 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2394 | } |
4731d4c7 MT |
2395 | } |
2396 | ||
2397 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2398 | bool can_unsync) | |
2399 | { | |
9cf5cf5a | 2400 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2401 | bool need_unsync = false; |
2402 | ||
b67bfe0d | 2403 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2404 | if (!can_unsync) |
2405 | return 1; | |
2406 | ||
9cf5cf5a | 2407 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2408 | return 1; |
9cf5cf5a | 2409 | |
9bb4f6b1 | 2410 | if (!s->unsync) |
9cf5cf5a | 2411 | need_unsync = true; |
4731d4c7 | 2412 | } |
9cf5cf5a XG |
2413 | if (need_unsync) |
2414 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2415 | return 0; |
2416 | } | |
2417 | ||
d555c333 | 2418 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2419 | unsigned pte_access, int level, |
c2d0ee46 | 2420 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2421 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2422 | { |
6e7d0354 | 2423 | u64 spte; |
1e73f9dd | 2424 | int ret = 0; |
64d4d521 | 2425 | |
f2fd125d | 2426 | if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2427 | return 0; |
2428 | ||
982c2565 | 2429 | spte = PT_PRESENT_MASK; |
947da538 | 2430 | if (!speculative) |
3201b5d9 | 2431 | spte |= shadow_accessed_mask; |
640d9b0d | 2432 | |
7b52345e SY |
2433 | if (pte_access & ACC_EXEC_MASK) |
2434 | spte |= shadow_x_mask; | |
2435 | else | |
2436 | spte |= shadow_nx_mask; | |
49fde340 | 2437 | |
1c4f1fd6 | 2438 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2439 | spte |= shadow_user_mask; |
49fde340 | 2440 | |
852e3c19 | 2441 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2442 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2443 | if (tdp_enabled) |
4b12f0de SY |
2444 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2445 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2446 | |
9bdbba13 | 2447 | if (host_writable) |
1403283a | 2448 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2449 | else |
2450 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2451 | |
35149e21 | 2452 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2453 | |
c2288505 | 2454 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2455 | |
c2193463 | 2456 | /* |
7751babd XG |
2457 | * Other vcpu creates new sp in the window between |
2458 | * mapping_level() and acquiring mmu-lock. We can | |
2459 | * allow guest to retry the access, the mapping can | |
2460 | * be fixed if guest refault. | |
c2193463 | 2461 | */ |
852e3c19 | 2462 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2463 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2464 | goto done; |
38187c83 | 2465 | |
49fde340 | 2466 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2467 | |
ecc5589f MT |
2468 | /* |
2469 | * Optimization: for pte sync, if spte was writable the hash | |
2470 | * lookup is unnecessary (and expensive). Write protection | |
2471 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2472 | * Same reasoning can be applied to dirty page accounting. | |
2473 | */ | |
8dae4445 | 2474 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2475 | goto set_pte; |
2476 | ||
4731d4c7 | 2477 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2478 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2479 | __func__, gfn); |
1e73f9dd | 2480 | ret = 1; |
1c4f1fd6 | 2481 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2482 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2483 | } |
2484 | } | |
2485 | ||
1c4f1fd6 AK |
2486 | if (pte_access & ACC_WRITE_MASK) |
2487 | mark_page_dirty(vcpu->kvm, gfn); | |
2488 | ||
38187c83 | 2489 | set_pte: |
6e7d0354 | 2490 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2491 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2492 | done: |
1e73f9dd MT |
2493 | return ret; |
2494 | } | |
2495 | ||
d555c333 | 2496 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2497 | unsigned pte_access, int write_fault, int *emulate, |
2498 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2499 | bool host_writable) | |
1e73f9dd MT |
2500 | { |
2501 | int was_rmapped = 0; | |
53a27b39 | 2502 | int rmap_count; |
1e73f9dd | 2503 | |
f7616203 XG |
2504 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2505 | *sptep, write_fault, gfn); | |
1e73f9dd | 2506 | |
d555c333 | 2507 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2508 | /* |
2509 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2510 | * the parent of the now unreachable PTE. | |
2511 | */ | |
852e3c19 JR |
2512 | if (level > PT_PAGE_TABLE_LEVEL && |
2513 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2514 | struct kvm_mmu_page *child; |
d555c333 | 2515 | u64 pte = *sptep; |
1e73f9dd MT |
2516 | |
2517 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2518 | drop_parent_pte(child, sptep); |
3be2264b | 2519 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2520 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2521 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2522 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2523 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2524 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2525 | } else |
2526 | was_rmapped = 1; | |
1e73f9dd | 2527 | } |
852e3c19 | 2528 | |
c2288505 XG |
2529 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2530 | true, host_writable)) { | |
1e73f9dd | 2531 | if (write_fault) |
b90a0e6c | 2532 | *emulate = 1; |
5304efde | 2533 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2534 | } |
1e73f9dd | 2535 | |
ce88decf XG |
2536 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2537 | *emulate = 1; | |
2538 | ||
d555c333 | 2539 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2540 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2541 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2542 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2543 | *sptep, sptep); | |
d555c333 | 2544 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2545 | ++vcpu->kvm->stat.lpages; |
2546 | ||
ffb61bb3 | 2547 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2548 | if (!was_rmapped) { |
2549 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2550 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2551 | rmap_recycle(vcpu, sptep, gfn); | |
2552 | } | |
1c4f1fd6 | 2553 | } |
cb9aaa30 | 2554 | |
f3ac1a4b | 2555 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2556 | } |
2557 | ||
957ed9ef XG |
2558 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2559 | bool no_dirty_log) | |
2560 | { | |
2561 | struct kvm_memory_slot *slot; | |
957ed9ef | 2562 | |
5d163b1c | 2563 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2564 | if (!slot) |
6c8ee57b | 2565 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2566 | |
037d92dc | 2567 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2568 | } |
2569 | ||
2570 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2571 | struct kvm_mmu_page *sp, | |
2572 | u64 *start, u64 *end) | |
2573 | { | |
2574 | struct page *pages[PTE_PREFETCH_NUM]; | |
2575 | unsigned access = sp->role.access; | |
2576 | int i, ret; | |
2577 | gfn_t gfn; | |
2578 | ||
2579 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2580 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2581 | return -1; |
2582 | ||
2583 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2584 | if (ret <= 0) | |
2585 | return -1; | |
2586 | ||
2587 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2588 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2589 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2590 | true, true); | |
957ed9ef XG |
2591 | |
2592 | return 0; | |
2593 | } | |
2594 | ||
2595 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2596 | struct kvm_mmu_page *sp, u64 *sptep) | |
2597 | { | |
2598 | u64 *spte, *start = NULL; | |
2599 | int i; | |
2600 | ||
2601 | WARN_ON(!sp->role.direct); | |
2602 | ||
2603 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2604 | spte = sp->spt + i; | |
2605 | ||
2606 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2607 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2608 | if (!start) |
2609 | continue; | |
2610 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2611 | break; | |
2612 | start = NULL; | |
2613 | } else if (!start) | |
2614 | start = spte; | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2619 | { | |
2620 | struct kvm_mmu_page *sp; | |
2621 | ||
2622 | /* | |
2623 | * Since it's no accessed bit on EPT, it's no way to | |
2624 | * distinguish between actually accessed translations | |
2625 | * and prefetched, so disable pte prefetch if EPT is | |
2626 | * enabled. | |
2627 | */ | |
2628 | if (!shadow_accessed_mask) | |
2629 | return; | |
2630 | ||
2631 | sp = page_header(__pa(sptep)); | |
2632 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2633 | return; | |
2634 | ||
2635 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2636 | } | |
2637 | ||
9f652d21 | 2638 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2639 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2640 | bool prefault) | |
140754bc | 2641 | { |
9f652d21 | 2642 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2643 | struct kvm_mmu_page *sp; |
b90a0e6c | 2644 | int emulate = 0; |
140754bc | 2645 | gfn_t pseudo_gfn; |
6aa8b732 | 2646 | |
989c6b34 MT |
2647 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2648 | return 0; | |
2649 | ||
9f652d21 | 2650 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2651 | if (iterator.level == level) { |
f7616203 | 2652 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2653 | write, &emulate, level, gfn, pfn, |
2654 | prefault, map_writable); | |
957ed9ef | 2655 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2656 | ++vcpu->stat.pf_fixed; |
2657 | break; | |
6aa8b732 AK |
2658 | } |
2659 | ||
404381c5 | 2660 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2661 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2662 | u64 base_addr = iterator.addr; |
2663 | ||
2664 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2665 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2666 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2667 | iterator.level - 1, | |
2668 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2669 | |
7a1638ce | 2670 | link_shadow_page(iterator.sptep, sp, true); |
9f652d21 AK |
2671 | } |
2672 | } | |
b90a0e6c | 2673 | return emulate; |
6aa8b732 AK |
2674 | } |
2675 | ||
77db5cbd | 2676 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2677 | { |
77db5cbd HY |
2678 | siginfo_t info; |
2679 | ||
2680 | info.si_signo = SIGBUS; | |
2681 | info.si_errno = 0; | |
2682 | info.si_code = BUS_MCEERR_AR; | |
2683 | info.si_addr = (void __user *)address; | |
2684 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2685 | |
77db5cbd | 2686 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2687 | } |
2688 | ||
d7c55201 | 2689 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2690 | { |
4d8b81ab XG |
2691 | /* |
2692 | * Do not cache the mmio info caused by writing the readonly gfn | |
2693 | * into the spte otherwise read access on readonly gfn also can | |
2694 | * caused mmio page fault and treat it as mmio access. | |
2695 | * Return 1 to tell kvm to emulate it. | |
2696 | */ | |
2697 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2698 | return 1; | |
2699 | ||
e6c1502b | 2700 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2701 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2702 | return 0; |
d7c55201 | 2703 | } |
edba23e5 | 2704 | |
d7c55201 | 2705 | return -EFAULT; |
bf998156 HY |
2706 | } |
2707 | ||
936a5fe6 AA |
2708 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2709 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2710 | { | |
2711 | pfn_t pfn = *pfnp; | |
2712 | gfn_t gfn = *gfnp; | |
2713 | int level = *levelp; | |
2714 | ||
2715 | /* | |
2716 | * Check if it's a transparent hugepage. If this would be an | |
2717 | * hugetlbfs page, level wouldn't be set to | |
2718 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2719 | * here. | |
2720 | */ | |
81c52c56 | 2721 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2722 | level == PT_PAGE_TABLE_LEVEL && |
2723 | PageTransCompound(pfn_to_page(pfn)) && | |
2724 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2725 | unsigned long mask; | |
2726 | /* | |
2727 | * mmu_notifier_retry was successful and we hold the | |
2728 | * mmu_lock here, so the pmd can't become splitting | |
2729 | * from under us, and in turn | |
2730 | * __split_huge_page_refcount() can't run from under | |
2731 | * us and we can safely transfer the refcount from | |
2732 | * PG_tail to PG_head as we switch the pfn to tail to | |
2733 | * head. | |
2734 | */ | |
2735 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2736 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2737 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2738 | if (pfn & mask) { | |
2739 | gfn &= ~mask; | |
2740 | *gfnp = gfn; | |
2741 | kvm_release_pfn_clean(pfn); | |
2742 | pfn &= ~mask; | |
c3586667 | 2743 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2744 | *pfnp = pfn; |
2745 | } | |
2746 | } | |
2747 | } | |
2748 | ||
d7c55201 XG |
2749 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2750 | pfn_t pfn, unsigned access, int *ret_val) | |
2751 | { | |
2752 | bool ret = true; | |
2753 | ||
2754 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2755 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2756 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2757 | goto exit; | |
2758 | } | |
2759 | ||
ce88decf | 2760 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2761 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2762 | |
2763 | ret = false; | |
2764 | exit: | |
2765 | return ret; | |
2766 | } | |
2767 | ||
e5552fd2 | 2768 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2769 | { |
1c118b82 XG |
2770 | /* |
2771 | * Do not fix the mmio spte with invalid generation number which | |
2772 | * need to be updated by slow page fault path. | |
2773 | */ | |
2774 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2775 | return false; | |
2776 | ||
c7ba5b48 XG |
2777 | /* |
2778 | * #PF can be fast only if the shadow page table is present and it | |
2779 | * is caused by write-protect, that means we just need change the | |
2780 | * W bit of the spte which can be done out of mmu-lock. | |
2781 | */ | |
2782 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2783 | !(error_code & PFERR_WRITE_MASK)) | |
2784 | return false; | |
2785 | ||
2786 | return true; | |
2787 | } | |
2788 | ||
2789 | static bool | |
92a476cb XG |
2790 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2791 | u64 *sptep, u64 spte) | |
c7ba5b48 | 2792 | { |
c7ba5b48 XG |
2793 | gfn_t gfn; |
2794 | ||
2795 | WARN_ON(!sp->role.direct); | |
2796 | ||
2797 | /* | |
2798 | * The gfn of direct spte is stable since it is calculated | |
2799 | * by sp->gfn. | |
2800 | */ | |
2801 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2802 | ||
2803 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2804 | mark_page_dirty(vcpu->kvm, gfn); | |
2805 | ||
2806 | return true; | |
2807 | } | |
2808 | ||
2809 | /* | |
2810 | * Return value: | |
2811 | * - true: let the vcpu to access on the same address again. | |
2812 | * - false: let the real page fault path to fix it. | |
2813 | */ | |
2814 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2815 | u32 error_code) | |
2816 | { | |
2817 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 2818 | struct kvm_mmu_page *sp; |
c7ba5b48 XG |
2819 | bool ret = false; |
2820 | u64 spte = 0ull; | |
2821 | ||
37f6a4e2 MT |
2822 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2823 | return false; | |
2824 | ||
e5552fd2 | 2825 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
2826 | return false; |
2827 | ||
2828 | walk_shadow_page_lockless_begin(vcpu); | |
2829 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2830 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2831 | break; | |
2832 | ||
2833 | /* | |
2834 | * If the mapping has been changed, let the vcpu fault on the | |
2835 | * same address again. | |
2836 | */ | |
2837 | if (!is_rmap_spte(spte)) { | |
2838 | ret = true; | |
2839 | goto exit; | |
2840 | } | |
2841 | ||
92a476cb XG |
2842 | sp = page_header(__pa(iterator.sptep)); |
2843 | if (!is_last_spte(spte, sp->role.level)) | |
c7ba5b48 XG |
2844 | goto exit; |
2845 | ||
2846 | /* | |
2847 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2848 | * | |
2849 | * Need not check the access of upper level table entries since | |
2850 | * they are always ACC_ALL. | |
2851 | */ | |
2852 | if (is_writable_pte(spte)) { | |
2853 | ret = true; | |
2854 | goto exit; | |
2855 | } | |
2856 | ||
2857 | /* | |
2858 | * Currently, to simplify the code, only the spte write-protected | |
2859 | * by dirty-log can be fast fixed. | |
2860 | */ | |
2861 | if (!spte_is_locklessly_modifiable(spte)) | |
2862 | goto exit; | |
2863 | ||
c126d94f XG |
2864 | /* |
2865 | * Do not fix write-permission on the large spte since we only dirty | |
2866 | * the first page into the dirty-bitmap in fast_pf_fix_direct_spte() | |
2867 | * that means other pages are missed if its slot is dirty-logged. | |
2868 | * | |
2869 | * Instead, we let the slow page fault path create a normal spte to | |
2870 | * fix the access. | |
2871 | * | |
2872 | * See the comments in kvm_arch_commit_memory_region(). | |
2873 | */ | |
2874 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2875 | goto exit; | |
2876 | ||
c7ba5b48 XG |
2877 | /* |
2878 | * Currently, fast page fault only works for direct mapping since | |
2879 | * the gfn is not stable for indirect shadow page. | |
2880 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2881 | */ | |
92a476cb | 2882 | ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte); |
c7ba5b48 | 2883 | exit: |
a72faf25 XG |
2884 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2885 | spte, ret); | |
c7ba5b48 XG |
2886 | walk_shadow_page_lockless_end(vcpu); |
2887 | ||
2888 | return ret; | |
2889 | } | |
2890 | ||
78b2c54a | 2891 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 2892 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2893 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2894 | |
c7ba5b48 XG |
2895 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2896 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2897 | { |
2898 | int r; | |
852e3c19 | 2899 | int level; |
936a5fe6 | 2900 | int force_pt_level; |
35149e21 | 2901 | pfn_t pfn; |
e930bffe | 2902 | unsigned long mmu_seq; |
c7ba5b48 | 2903 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2904 | |
936a5fe6 AA |
2905 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2906 | if (likely(!force_pt_level)) { | |
2907 | level = mapping_level(vcpu, gfn); | |
2908 | /* | |
2909 | * This path builds a PAE pagetable - so we can map | |
2910 | * 2mb pages at maximum. Therefore check if the level | |
2911 | * is larger than that. | |
2912 | */ | |
2913 | if (level > PT_DIRECTORY_LEVEL) | |
2914 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2915 | |
936a5fe6 AA |
2916 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2917 | } else | |
2918 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2919 | |
c7ba5b48 XG |
2920 | if (fast_page_fault(vcpu, v, level, error_code)) |
2921 | return 0; | |
2922 | ||
e930bffe | 2923 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2924 | smp_rmb(); |
060c2abe | 2925 | |
78b2c54a | 2926 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2927 | return 0; |
aaee2c94 | 2928 | |
d7c55201 XG |
2929 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2930 | return r; | |
d196e343 | 2931 | |
aaee2c94 | 2932 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2933 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2934 | goto out_unlock; |
450e0b41 | 2935 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
2936 | if (likely(!force_pt_level)) |
2937 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2938 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2939 | prefault); | |
aaee2c94 MT |
2940 | spin_unlock(&vcpu->kvm->mmu_lock); |
2941 | ||
aaee2c94 | 2942 | |
10589a46 | 2943 | return r; |
e930bffe AA |
2944 | |
2945 | out_unlock: | |
2946 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2947 | kvm_release_pfn_clean(pfn); | |
2948 | return 0; | |
10589a46 MT |
2949 | } |
2950 | ||
2951 | ||
17ac10ad AK |
2952 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2953 | { | |
2954 | int i; | |
4db35314 | 2955 | struct kvm_mmu_page *sp; |
d98ba053 | 2956 | LIST_HEAD(invalid_list); |
17ac10ad | 2957 | |
ad312c7c | 2958 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2959 | return; |
35af577a | 2960 | |
81407ca5 JR |
2961 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2962 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2963 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2964 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2965 | |
35af577a | 2966 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
2967 | sp = page_header(root); |
2968 | --sp->root_count; | |
d98ba053 XG |
2969 | if (!sp->root_count && sp->role.invalid) { |
2970 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2971 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2972 | } | |
aaee2c94 | 2973 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 2974 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2975 | return; |
2976 | } | |
35af577a GN |
2977 | |
2978 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 2979 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2980 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2981 | |
417726a3 | 2982 | if (root) { |
417726a3 | 2983 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2984 | sp = page_header(root); |
2985 | --sp->root_count; | |
2e53d63a | 2986 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2987 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2988 | &invalid_list); | |
417726a3 | 2989 | } |
ad312c7c | 2990 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2991 | } |
d98ba053 | 2992 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2993 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2994 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2995 | } |
2996 | ||
8986ecc0 MT |
2997 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2998 | { | |
2999 | int ret = 0; | |
3000 | ||
3001 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3002 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3003 | ret = 1; |
3004 | } | |
3005 | ||
3006 | return ret; | |
3007 | } | |
3008 | ||
651dd37a JR |
3009 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3010 | { | |
3011 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3012 | unsigned i; |
651dd37a JR |
3013 | |
3014 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3015 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3016 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3017 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
3018 | 1, ACC_ALL, NULL); | |
3019 | ++sp->root_count; | |
3020 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3021 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3022 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3023 | for (i = 0; i < 4; ++i) { | |
3024 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3025 | ||
3026 | ASSERT(!VALID_PAGE(root)); | |
3027 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3028 | make_mmu_pages_available(vcpu); |
649497d1 AK |
3029 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
3030 | i << 30, | |
651dd37a JR |
3031 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
3032 | NULL); | |
3033 | root = __pa(sp->spt); | |
3034 | ++sp->root_count; | |
3035 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3036 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3037 | } |
6292757f | 3038 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3039 | } else |
3040 | BUG(); | |
3041 | ||
3042 | return 0; | |
3043 | } | |
3044 | ||
3045 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3046 | { |
4db35314 | 3047 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3048 | u64 pdptr, pm_mask; |
3049 | gfn_t root_gfn; | |
3050 | int i; | |
3bb65a22 | 3051 | |
5777ed34 | 3052 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3053 | |
651dd37a JR |
3054 | if (mmu_check_root(vcpu, root_gfn)) |
3055 | return 1; | |
3056 | ||
3057 | /* | |
3058 | * Do we shadow a long mode page table? If so we need to | |
3059 | * write-protect the guests page table root. | |
3060 | */ | |
3061 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3062 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
3063 | |
3064 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 3065 | |
8facbbff | 3066 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3067 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3068 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
3069 | 0, ACC_ALL, NULL); | |
4db35314 AK |
3070 | root = __pa(sp->spt); |
3071 | ++sp->root_count; | |
8facbbff | 3072 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3073 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3074 | return 0; |
17ac10ad | 3075 | } |
f87f9288 | 3076 | |
651dd37a JR |
3077 | /* |
3078 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3079 | * or a PAE 3-level page table. In either case we need to be aware that |
3080 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3081 | */ |
81407ca5 JR |
3082 | pm_mask = PT_PRESENT_MASK; |
3083 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3084 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3085 | ||
17ac10ad | 3086 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3087 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
3088 | |
3089 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 3090 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3091 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3092 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3093 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3094 | continue; |
3095 | } | |
6de4f3ad | 3096 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3097 | if (mmu_check_root(vcpu, root_gfn)) |
3098 | return 1; | |
5a7388c2 | 3099 | } |
8facbbff | 3100 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3101 | make_mmu_pages_available(vcpu); |
4db35314 | 3102 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3103 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3104 | ACC_ALL, NULL); |
4db35314 AK |
3105 | root = __pa(sp->spt); |
3106 | ++sp->root_count; | |
8facbbff AK |
3107 | spin_unlock(&vcpu->kvm->mmu_lock); |
3108 | ||
81407ca5 | 3109 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3110 | } |
6292757f | 3111 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3112 | |
3113 | /* | |
3114 | * If we shadow a 32 bit page table with a long mode page | |
3115 | * table we enter this path. | |
3116 | */ | |
3117 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3118 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3119 | /* | |
3120 | * The additional page necessary for this is only | |
3121 | * allocated on demand. | |
3122 | */ | |
3123 | ||
3124 | u64 *lm_root; | |
3125 | ||
3126 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3127 | if (lm_root == NULL) | |
3128 | return 1; | |
3129 | ||
3130 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3131 | ||
3132 | vcpu->arch.mmu.lm_root = lm_root; | |
3133 | } | |
3134 | ||
3135 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3136 | } | |
3137 | ||
8986ecc0 | 3138 | return 0; |
17ac10ad AK |
3139 | } |
3140 | ||
651dd37a JR |
3141 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3142 | { | |
3143 | if (vcpu->arch.mmu.direct_map) | |
3144 | return mmu_alloc_direct_roots(vcpu); | |
3145 | else | |
3146 | return mmu_alloc_shadow_roots(vcpu); | |
3147 | } | |
3148 | ||
0ba73cda MT |
3149 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3150 | { | |
3151 | int i; | |
3152 | struct kvm_mmu_page *sp; | |
3153 | ||
81407ca5 JR |
3154 | if (vcpu->arch.mmu.direct_map) |
3155 | return; | |
3156 | ||
0ba73cda MT |
3157 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3158 | return; | |
6903074c | 3159 | |
56f17dd3 | 3160 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3161 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3162 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3163 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3164 | sp = page_header(root); | |
3165 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3166 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3167 | return; |
3168 | } | |
3169 | for (i = 0; i < 4; ++i) { | |
3170 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3171 | ||
8986ecc0 | 3172 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3173 | root &= PT64_BASE_ADDR_MASK; |
3174 | sp = page_header(root); | |
3175 | mmu_sync_children(vcpu, sp); | |
3176 | } | |
3177 | } | |
0375f7fa | 3178 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3179 | } |
3180 | ||
3181 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3182 | { | |
3183 | spin_lock(&vcpu->kvm->mmu_lock); | |
3184 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3185 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3186 | } |
bfd0a56b | 3187 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3188 | |
1871c602 | 3189 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3190 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3191 | { |
ab9ae313 AK |
3192 | if (exception) |
3193 | exception->error_code = 0; | |
6aa8b732 AK |
3194 | return vaddr; |
3195 | } | |
3196 | ||
6539e738 | 3197 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3198 | u32 access, |
3199 | struct x86_exception *exception) | |
6539e738 | 3200 | { |
ab9ae313 AK |
3201 | if (exception) |
3202 | exception->error_code = 0; | |
54987b7a | 3203 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3204 | } |
3205 | ||
ce88decf XG |
3206 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3207 | { | |
3208 | if (direct) | |
3209 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3210 | ||
3211 | return vcpu_match_mmio_gva(vcpu, addr); | |
3212 | } | |
3213 | ||
3214 | ||
3215 | /* | |
3216 | * On direct hosts, the last spte is only allows two states | |
3217 | * for mmio page fault: | |
3218 | * - It is the mmio spte | |
3219 | * - It is zapped or it is being zapped. | |
3220 | * | |
3221 | * This function completely checks the spte when the last spte | |
3222 | * is not the mmio spte. | |
3223 | */ | |
3224 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3225 | { | |
3226 | return __check_direct_spte_mmio_pf(spte); | |
3227 | } | |
3228 | ||
3229 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3230 | { | |
3231 | struct kvm_shadow_walk_iterator iterator; | |
3232 | u64 spte = 0ull; | |
3233 | ||
37f6a4e2 MT |
3234 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3235 | return spte; | |
3236 | ||
ce88decf XG |
3237 | walk_shadow_page_lockless_begin(vcpu); |
3238 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3239 | if (!is_shadow_present_pte(spte)) | |
3240 | break; | |
3241 | walk_shadow_page_lockless_end(vcpu); | |
3242 | ||
3243 | return spte; | |
3244 | } | |
3245 | ||
ce88decf XG |
3246 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3247 | { | |
3248 | u64 spte; | |
3249 | ||
3250 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
b37fbea6 | 3251 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3252 | |
3253 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3254 | ||
3255 | if (is_mmio_spte(spte)) { | |
3256 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3257 | unsigned access = get_mmio_spte_access(spte); | |
3258 | ||
f8f55942 XG |
3259 | if (!check_mmio_spte(vcpu->kvm, spte)) |
3260 | return RET_MMIO_PF_INVALID; | |
3261 | ||
ce88decf XG |
3262 | if (direct) |
3263 | addr = 0; | |
4f022648 XG |
3264 | |
3265 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3266 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3267 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3268 | } |
3269 | ||
3270 | /* | |
3271 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3272 | * it's a BUG if the gfn is not a mmio page. | |
3273 | */ | |
3274 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
b37fbea6 | 3275 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3276 | |
3277 | /* | |
3278 | * If the page table is zapped by other cpus, let CPU fault again on | |
3279 | * the address. | |
3280 | */ | |
b37fbea6 | 3281 | return RET_MMIO_PF_RETRY; |
ce88decf XG |
3282 | } |
3283 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3284 | ||
3285 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3286 | u32 error_code, bool direct) | |
3287 | { | |
3288 | int ret; | |
3289 | ||
3290 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
b37fbea6 | 3291 | WARN_ON(ret == RET_MMIO_PF_BUG); |
ce88decf XG |
3292 | return ret; |
3293 | } | |
3294 | ||
6aa8b732 | 3295 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3296 | u32 error_code, bool prefault) |
6aa8b732 | 3297 | { |
e833240f | 3298 | gfn_t gfn; |
e2dec939 | 3299 | int r; |
6aa8b732 | 3300 | |
b8688d51 | 3301 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3302 | |
f8f55942 XG |
3303 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3304 | r = handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3305 | ||
3306 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3307 | return r; | |
3308 | } | |
ce88decf | 3309 | |
e2dec939 AK |
3310 | r = mmu_topup_memory_caches(vcpu); |
3311 | if (r) | |
3312 | return r; | |
714b93da | 3313 | |
6aa8b732 | 3314 | ASSERT(vcpu); |
ad312c7c | 3315 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3316 | |
e833240f | 3317 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3318 | |
e833240f | 3319 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3320 | error_code, gfn, prefault); |
6aa8b732 AK |
3321 | } |
3322 | ||
7e1fbeac | 3323 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3324 | { |
3325 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3326 | |
7c90705b | 3327 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3328 | arch.gfn = gfn; |
c4806acd | 3329 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3330 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3331 | |
e0ead41a | 3332 | return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch); |
af585b92 GN |
3333 | } |
3334 | ||
3335 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3336 | { | |
3337 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3338 | kvm_event_needs_reinjection(vcpu))) | |
3339 | return false; | |
3340 | ||
3341 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3342 | } | |
3343 | ||
78b2c54a | 3344 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3345 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3346 | { |
3347 | bool async; | |
3348 | ||
612819c3 | 3349 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3350 | |
3351 | if (!async) | |
3352 | return false; /* *pfn has correct page already */ | |
3353 | ||
78b2c54a | 3354 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3355 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3356 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3357 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3358 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3359 | return true; | |
3360 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3361 | return true; | |
3362 | } | |
3363 | ||
612819c3 | 3364 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3365 | |
3366 | return false; | |
3367 | } | |
3368 | ||
56028d08 | 3369 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3370 | bool prefault) |
fb72d167 | 3371 | { |
35149e21 | 3372 | pfn_t pfn; |
fb72d167 | 3373 | int r; |
852e3c19 | 3374 | int level; |
936a5fe6 | 3375 | int force_pt_level; |
05da4558 | 3376 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3377 | unsigned long mmu_seq; |
612819c3 MT |
3378 | int write = error_code & PFERR_WRITE_MASK; |
3379 | bool map_writable; | |
fb72d167 JR |
3380 | |
3381 | ASSERT(vcpu); | |
3382 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3383 | ||
f8f55942 XG |
3384 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
3385 | r = handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3386 | ||
3387 | if (likely(r != RET_MMIO_PF_INVALID)) | |
3388 | return r; | |
3389 | } | |
ce88decf | 3390 | |
fb72d167 JR |
3391 | r = mmu_topup_memory_caches(vcpu); |
3392 | if (r) | |
3393 | return r; | |
3394 | ||
936a5fe6 AA |
3395 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3396 | if (likely(!force_pt_level)) { | |
3397 | level = mapping_level(vcpu, gfn); | |
3398 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3399 | } else | |
3400 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3401 | |
c7ba5b48 XG |
3402 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3403 | return 0; | |
3404 | ||
e930bffe | 3405 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3406 | smp_rmb(); |
af585b92 | 3407 | |
78b2c54a | 3408 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3409 | return 0; |
3410 | ||
d7c55201 XG |
3411 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3412 | return r; | |
3413 | ||
fb72d167 | 3414 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3415 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3416 | goto out_unlock; |
450e0b41 | 3417 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3418 | if (likely(!force_pt_level)) |
3419 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3420 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3421 | level, gfn, pfn, prefault); |
fb72d167 | 3422 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3423 | |
3424 | return r; | |
e930bffe AA |
3425 | |
3426 | out_unlock: | |
3427 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3428 | kvm_release_pfn_clean(pfn); | |
3429 | return 0; | |
fb72d167 JR |
3430 | } |
3431 | ||
8a3c1a33 PB |
3432 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3433 | struct kvm_mmu *context) | |
6aa8b732 | 3434 | { |
6aa8b732 | 3435 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3436 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3437 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3438 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3439 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3440 | context->root_level = 0; |
6aa8b732 | 3441 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3442 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3443 | context->direct_map = true; |
2d48a985 | 3444 | context->nx = false; |
6aa8b732 AK |
3445 | } |
3446 | ||
d835dfec | 3447 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3448 | { |
a8eeb04a | 3449 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 | 3450 | } |
bfd0a56b | 3451 | EXPORT_SYMBOL_GPL(kvm_mmu_flush_tlb); |
6aa8b732 | 3452 | |
d8d173da | 3453 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3454 | { |
cea0f0e7 | 3455 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3456 | } |
3457 | ||
5777ed34 JR |
3458 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3459 | { | |
9f8fe504 | 3460 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3461 | } |
3462 | ||
6389ee94 AK |
3463 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3464 | struct x86_exception *fault) | |
6aa8b732 | 3465 | { |
6389ee94 | 3466 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3467 | } |
3468 | ||
f2fd125d XG |
3469 | static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn, |
3470 | unsigned access, int *nr_present) | |
ce88decf XG |
3471 | { |
3472 | if (unlikely(is_mmio_spte(*sptep))) { | |
3473 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3474 | mmu_spte_clear_no_track(sptep); | |
3475 | return true; | |
3476 | } | |
3477 | ||
3478 | (*nr_present)++; | |
f2fd125d | 3479 | mark_mmio_spte(kvm, sptep, gfn, access); |
ce88decf XG |
3480 | return true; |
3481 | } | |
3482 | ||
3483 | return false; | |
3484 | } | |
3485 | ||
6fd01b71 AK |
3486 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3487 | { | |
3488 | unsigned index; | |
3489 | ||
3490 | index = level - 1; | |
3491 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3492 | return mmu->last_pte_bitmap & (1 << index); | |
3493 | } | |
3494 | ||
37406aaa NHE |
3495 | #define PTTYPE_EPT 18 /* arbitrary */ |
3496 | #define PTTYPE PTTYPE_EPT | |
3497 | #include "paging_tmpl.h" | |
3498 | #undef PTTYPE | |
3499 | ||
6aa8b732 AK |
3500 | #define PTTYPE 64 |
3501 | #include "paging_tmpl.h" | |
3502 | #undef PTTYPE | |
3503 | ||
3504 | #define PTTYPE 32 | |
3505 | #include "paging_tmpl.h" | |
3506 | #undef PTTYPE | |
3507 | ||
52fde8df | 3508 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3509 | struct kvm_mmu *context) |
82725b20 | 3510 | { |
82725b20 DE |
3511 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3512 | u64 exb_bit_rsvd = 0; | |
5f7dde7b | 3513 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3514 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3515 | |
25d92081 YZ |
3516 | context->bad_mt_xwr = 0; |
3517 | ||
2d48a985 | 3518 | if (!context->nx) |
82725b20 | 3519 | exb_bit_rsvd = rsvd_bits(63, 63); |
5f7dde7b NA |
3520 | if (!guest_cpuid_has_gbpages(vcpu)) |
3521 | gbpages_bit_rsvd = rsvd_bits(7, 7); | |
a0c0feb5 PB |
3522 | |
3523 | /* | |
3524 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3525 | * leaf entries) on AMD CPUs only. | |
3526 | */ | |
3527 | if (guest_cpuid_is_amd(vcpu)) | |
3528 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); | |
3529 | ||
4d6931c3 | 3530 | switch (context->root_level) { |
82725b20 DE |
3531 | case PT32_ROOT_LEVEL: |
3532 | /* no rsvd bits for 2 level 4K page table entries */ | |
3533 | context->rsvd_bits_mask[0][1] = 0; | |
3534 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3535 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3536 | ||
3537 | if (!is_pse(vcpu)) { | |
3538 | context->rsvd_bits_mask[1][1] = 0; | |
3539 | break; | |
3540 | } | |
3541 | ||
82725b20 DE |
3542 | if (is_cpuid_PSE36()) |
3543 | /* 36bits PSE 4MB page */ | |
3544 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3545 | else | |
3546 | /* 32 bits PSE 4MB page */ | |
3547 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3548 | break; |
3549 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3550 | context->rsvd_bits_mask[0][2] = |
3551 | rsvd_bits(maxphyaddr, 63) | | |
cd9ae5fe | 3552 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
82725b20 | 3553 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3554 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3555 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3556 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3557 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3558 | rsvd_bits(maxphyaddr, 62) | | |
3559 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3560 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3561 | break; |
3562 | case PT64_ROOT_LEVEL: | |
3563 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
a0c0feb5 | 3564 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | rsvd_bits(maxphyaddr, 51); |
82725b20 | 3565 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
a0c0feb5 | 3566 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51); |
82725b20 | 3567 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3568 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3569 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3570 | rsvd_bits(maxphyaddr, 51); | |
3571 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 | 3572 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
5f7dde7b | 3573 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3574 | rsvd_bits(13, 29); |
82725b20 | 3575 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3576 | rsvd_bits(maxphyaddr, 51) | |
3577 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3578 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3579 | break; |
3580 | } | |
3581 | } | |
3582 | ||
25d92081 YZ |
3583 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
3584 | struct kvm_mmu *context, bool execonly) | |
3585 | { | |
3586 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
3587 | int pte; | |
3588 | ||
3589 | context->rsvd_bits_mask[0][3] = | |
3590 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
3591 | context->rsvd_bits_mask[0][2] = | |
3592 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); | |
3593 | context->rsvd_bits_mask[0][1] = | |
3594 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); | |
3595 | context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); | |
3596 | ||
3597 | /* large page */ | |
3598 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
3599 | context->rsvd_bits_mask[1][2] = | |
3600 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); | |
3601 | context->rsvd_bits_mask[1][1] = | |
3602 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); | |
3603 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; | |
3604 | ||
3605 | for (pte = 0; pte < 64; pte++) { | |
3606 | int rwx_bits = pte & 7; | |
3607 | int mt = pte >> 3; | |
3608 | if (mt == 0x2 || mt == 0x3 || mt == 0x7 || | |
3609 | rwx_bits == 0x2 || rwx_bits == 0x6 || | |
3610 | (rwx_bits == 0x4 && !execonly)) | |
3611 | context->bad_mt_xwr |= (1ull << pte); | |
3612 | } | |
3613 | } | |
3614 | ||
97ec8c06 | 3615 | void update_permission_bitmask(struct kvm_vcpu *vcpu, |
25d92081 | 3616 | struct kvm_mmu *mmu, bool ept) |
97d64b78 AK |
3617 | { |
3618 | unsigned bit, byte, pfec; | |
3619 | u8 map; | |
66386ade | 3620 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 3621 | |
66386ade | 3622 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 3623 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
3624 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
3625 | pfec = byte << 1; | |
3626 | map = 0; | |
3627 | wf = pfec & PFERR_WRITE_MASK; | |
3628 | uf = pfec & PFERR_USER_MASK; | |
3629 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
3630 | /* |
3631 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
3632 | * subject to SMAP restrictions, and cleared otherwise. The | |
3633 | * bit is only meaningful if the SMAP bit is set in CR4. | |
3634 | */ | |
3635 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
3636 | for (bit = 0; bit < 8; ++bit) { |
3637 | x = bit & ACC_EXEC_MASK; | |
3638 | w = bit & ACC_WRITE_MASK; | |
3639 | u = bit & ACC_USER_MASK; | |
3640 | ||
25d92081 YZ |
3641 | if (!ept) { |
3642 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3643 | x |= !mmu->nx; | |
3644 | /* Allow supervisor writes if !cr0.wp */ | |
3645 | w |= !is_write_protection(vcpu) && !uf; | |
3646 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 3647 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
3648 | |
3649 | /* | |
3650 | * SMAP:kernel-mode data accesses from user-mode | |
3651 | * mappings should fault. A fault is considered | |
3652 | * as a SMAP violation if all of the following | |
3653 | * conditions are ture: | |
3654 | * - X86_CR4_SMAP is set in CR4 | |
3655 | * - An user page is accessed | |
3656 | * - Page fault in kernel mode | |
3657 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
3658 | * | |
3659 | * Here, we cover the first three conditions. | |
3660 | * The fourth is computed dynamically in | |
3661 | * permission_fault() and is in smapf. | |
3662 | * | |
3663 | * Also, SMAP does not affect instruction | |
3664 | * fetches, add the !ff check here to make it | |
3665 | * clearer. | |
3666 | */ | |
3667 | smap = cr4_smap && u && !uf && !ff; | |
25d92081 YZ |
3668 | } else |
3669 | /* Not really needed: no U/S accesses on ept */ | |
3670 | u = 1; | |
97d64b78 | 3671 | |
97ec8c06 FW |
3672 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
3673 | (smapf && smap); | |
97d64b78 AK |
3674 | map |= fault << bit; |
3675 | } | |
3676 | mmu->permissions[byte] = map; | |
3677 | } | |
3678 | } | |
3679 | ||
6fd01b71 AK |
3680 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3681 | { | |
3682 | u8 map; | |
3683 | unsigned level, root_level = mmu->root_level; | |
3684 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3685 | ||
3686 | if (root_level == PT32E_ROOT_LEVEL) | |
3687 | --root_level; | |
3688 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3689 | map = 1 | (1 << ps_set_index); | |
3690 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3691 | if (level <= PT_PDPE_LEVEL | |
3692 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3693 | map |= 1 << (ps_set_index | (level - 1)); | |
3694 | } | |
3695 | mmu->last_pte_bitmap = map; | |
3696 | } | |
3697 | ||
8a3c1a33 PB |
3698 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
3699 | struct kvm_mmu *context, | |
3700 | int level) | |
6aa8b732 | 3701 | { |
2d48a985 | 3702 | context->nx = is_nx(vcpu); |
4d6931c3 | 3703 | context->root_level = level; |
2d48a985 | 3704 | |
4d6931c3 | 3705 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3706 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3707 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3708 | |
3709 | ASSERT(is_pae(vcpu)); | |
6aa8b732 | 3710 | context->page_fault = paging64_page_fault; |
6aa8b732 | 3711 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3712 | context->sync_page = paging64_sync_page; |
a7052897 | 3713 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3714 | context->update_pte = paging64_update_pte; |
17ac10ad | 3715 | context->shadow_root_level = level; |
17c3ba9d | 3716 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3717 | context->direct_map = false; |
6aa8b732 AK |
3718 | } |
3719 | ||
8a3c1a33 PB |
3720 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
3721 | struct kvm_mmu *context) | |
17ac10ad | 3722 | { |
8a3c1a33 | 3723 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3724 | } |
3725 | ||
8a3c1a33 PB |
3726 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
3727 | struct kvm_mmu *context) | |
6aa8b732 | 3728 | { |
2d48a985 | 3729 | context->nx = false; |
4d6931c3 | 3730 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3731 | |
4d6931c3 | 3732 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 3733 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3734 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 | 3735 | |
6aa8b732 | 3736 | context->page_fault = paging32_page_fault; |
6aa8b732 | 3737 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 3738 | context->sync_page = paging32_sync_page; |
a7052897 | 3739 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3740 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3741 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3742 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3743 | context->direct_map = false; |
6aa8b732 AK |
3744 | } |
3745 | ||
8a3c1a33 PB |
3746 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
3747 | struct kvm_mmu *context) | |
6aa8b732 | 3748 | { |
8a3c1a33 | 3749 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3750 | } |
3751 | ||
8a3c1a33 | 3752 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 3753 | { |
14dfe855 | 3754 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3755 | |
c445f8ef | 3756 | context->base_role.word = 0; |
fb72d167 | 3757 | context->page_fault = tdp_page_fault; |
e8bc217a | 3758 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3759 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3760 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3761 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3762 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3763 | context->direct_map = true; |
1c97f0a0 | 3764 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3765 | context->get_cr3 = get_cr3; |
e4e517b4 | 3766 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3767 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3768 | |
3769 | if (!is_paging(vcpu)) { | |
2d48a985 | 3770 | context->nx = false; |
fb72d167 JR |
3771 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3772 | context->root_level = 0; | |
3773 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3774 | context->nx = is_nx(vcpu); |
fb72d167 | 3775 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3776 | reset_rsvds_bits_mask(vcpu, context); |
3777 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3778 | } else if (is_pae(vcpu)) { |
2d48a985 | 3779 | context->nx = is_nx(vcpu); |
fb72d167 | 3780 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3781 | reset_rsvds_bits_mask(vcpu, context); |
3782 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3783 | } else { |
2d48a985 | 3784 | context->nx = false; |
fb72d167 | 3785 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3786 | reset_rsvds_bits_mask(vcpu, context); |
3787 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3788 | } |
3789 | ||
25d92081 | 3790 | update_permission_bitmask(vcpu, context, false); |
6fd01b71 | 3791 | update_last_pte_bitmap(vcpu, context); |
fb72d167 JR |
3792 | } |
3793 | ||
8a3c1a33 | 3794 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3795 | { |
411c588d | 3796 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3797 | ASSERT(vcpu); |
ad312c7c | 3798 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3799 | |
3800 | if (!is_paging(vcpu)) | |
8a3c1a33 | 3801 | nonpaging_init_context(vcpu, context); |
a9058ecd | 3802 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 3803 | paging64_init_context(vcpu, context); |
6aa8b732 | 3804 | else if (is_pae(vcpu)) |
8a3c1a33 | 3805 | paging32E_init_context(vcpu, context); |
6aa8b732 | 3806 | else |
8a3c1a33 | 3807 | paging32_init_context(vcpu, context); |
a770f6f2 | 3808 | |
2c9afa52 | 3809 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3810 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3811 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3812 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3813 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3814 | } |
3815 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3816 | ||
8a3c1a33 | 3817 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
155a97a3 NHE |
3818 | bool execonly) |
3819 | { | |
3820 | ASSERT(vcpu); | |
3821 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3822 | ||
3823 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
3824 | ||
3825 | context->nx = true; | |
155a97a3 NHE |
3826 | context->page_fault = ept_page_fault; |
3827 | context->gva_to_gpa = ept_gva_to_gpa; | |
3828 | context->sync_page = ept_sync_page; | |
3829 | context->invlpg = ept_invlpg; | |
3830 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
3831 | context->root_level = context->shadow_root_level; |
3832 | context->root_hpa = INVALID_PAGE; | |
3833 | context->direct_map = false; | |
3834 | ||
3835 | update_permission_bitmask(vcpu, context, true); | |
3836 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); | |
155a97a3 NHE |
3837 | } |
3838 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
3839 | ||
8a3c1a33 | 3840 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 3841 | { |
8a3c1a33 | 3842 | kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
14dfe855 JR |
3843 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3844 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3845 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3846 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
6aa8b732 AK |
3847 | } |
3848 | ||
8a3c1a33 | 3849 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
3850 | { |
3851 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3852 | ||
3853 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3854 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3855 | g_context->inject_page_fault = kvm_inject_page_fault; |
3856 | ||
3857 | /* | |
3858 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3859 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3860 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3861 | * functions between mmu and nested_mmu are swapped. | |
3862 | */ | |
3863 | if (!is_paging(vcpu)) { | |
2d48a985 | 3864 | g_context->nx = false; |
02f59dc9 JR |
3865 | g_context->root_level = 0; |
3866 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3867 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3868 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3869 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3870 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3871 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3872 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3873 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3874 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3875 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3876 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3877 | } else { | |
2d48a985 | 3878 | g_context->nx = false; |
02f59dc9 | 3879 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3880 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3881 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3882 | } | |
3883 | ||
25d92081 | 3884 | update_permission_bitmask(vcpu, g_context, false); |
6fd01b71 | 3885 | update_last_pte_bitmap(vcpu, g_context); |
02f59dc9 JR |
3886 | } |
3887 | ||
8a3c1a33 | 3888 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 3889 | { |
02f59dc9 JR |
3890 | if (mmu_is_nested(vcpu)) |
3891 | return init_kvm_nested_mmu(vcpu); | |
3892 | else if (tdp_enabled) | |
fb72d167 JR |
3893 | return init_kvm_tdp_mmu(vcpu); |
3894 | else | |
3895 | return init_kvm_softmmu(vcpu); | |
3896 | } | |
3897 | ||
8a3c1a33 | 3898 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
3899 | { |
3900 | ASSERT(vcpu); | |
6aa8b732 | 3901 | |
95f93af4 | 3902 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 3903 | init_kvm_mmu(vcpu); |
17c3ba9d | 3904 | } |
8668a3c4 | 3905 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3906 | |
3907 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3908 | { |
714b93da AK |
3909 | int r; |
3910 | ||
e2dec939 | 3911 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3912 | if (r) |
3913 | goto out; | |
8986ecc0 | 3914 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 3915 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
3916 | if (r) |
3917 | goto out; | |
3662cb1c | 3918 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3919 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3920 | out: |
3921 | return r; | |
6aa8b732 | 3922 | } |
17c3ba9d AK |
3923 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3924 | ||
3925 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3926 | { | |
3927 | mmu_free_roots(vcpu); | |
95f93af4 | 3928 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 3929 | } |
4b16184c | 3930 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3931 | |
0028425f | 3932 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3933 | struct kvm_mmu_page *sp, u64 *spte, |
3934 | const void *new) | |
0028425f | 3935 | { |
30945387 | 3936 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3937 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3938 | return; | |
30945387 | 3939 | } |
0028425f | 3940 | |
4cee5764 | 3941 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3942 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3943 | } |
3944 | ||
79539cec AK |
3945 | static bool need_remote_flush(u64 old, u64 new) |
3946 | { | |
3947 | if (!is_shadow_present_pte(old)) | |
3948 | return false; | |
3949 | if (!is_shadow_present_pte(new)) | |
3950 | return true; | |
3951 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3952 | return true; | |
53166229 GN |
3953 | old ^= shadow_nx_mask; |
3954 | new ^= shadow_nx_mask; | |
79539cec AK |
3955 | return (old & ~new & PT64_PERM_MASK) != 0; |
3956 | } | |
3957 | ||
0671a8e7 XG |
3958 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3959 | bool remote_flush, bool local_flush) | |
79539cec | 3960 | { |
0671a8e7 XG |
3961 | if (zap_page) |
3962 | return; | |
3963 | ||
3964 | if (remote_flush) | |
79539cec | 3965 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3966 | else if (local_flush) |
79539cec AK |
3967 | kvm_mmu_flush_tlb(vcpu); |
3968 | } | |
3969 | ||
889e5cbc XG |
3970 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3971 | const u8 *new, int *bytes) | |
da4a00f0 | 3972 | { |
889e5cbc XG |
3973 | u64 gentry; |
3974 | int r; | |
72016f3a | 3975 | |
72016f3a AK |
3976 | /* |
3977 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3978 | * as the current vcpu paging mode since we update the sptes only |
3979 | * when they have the same mode. | |
72016f3a | 3980 | */ |
889e5cbc | 3981 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3982 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3983 | *gpa &= ~(gpa_t)7; |
3984 | *bytes = 8; | |
116eb3d3 | 3985 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3986 | if (r) |
3987 | gentry = 0; | |
08e850c6 AK |
3988 | new = (const u8 *)&gentry; |
3989 | } | |
3990 | ||
889e5cbc | 3991 | switch (*bytes) { |
08e850c6 AK |
3992 | case 4: |
3993 | gentry = *(const u32 *)new; | |
3994 | break; | |
3995 | case 8: | |
3996 | gentry = *(const u64 *)new; | |
3997 | break; | |
3998 | default: | |
3999 | gentry = 0; | |
4000 | break; | |
72016f3a AK |
4001 | } |
4002 | ||
889e5cbc XG |
4003 | return gentry; |
4004 | } | |
4005 | ||
4006 | /* | |
4007 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4008 | * or we may be forking, in which case it is better to unmap the page. | |
4009 | */ | |
a138fe75 | 4010 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4011 | { |
a30f47cb XG |
4012 | /* |
4013 | * Skip write-flooding detected for the sp whose level is 1, because | |
4014 | * it can become unsync, then the guest page is not write-protected. | |
4015 | */ | |
f71fa31f | 4016 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4017 | return false; |
3246af0e | 4018 | |
a30f47cb | 4019 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
4020 | } |
4021 | ||
4022 | /* | |
4023 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4024 | * indicate a page is not used as a page table. | |
4025 | */ | |
4026 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4027 | int bytes) | |
4028 | { | |
4029 | unsigned offset, pte_size, misaligned; | |
4030 | ||
4031 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4032 | gpa, bytes, sp->role.word); | |
4033 | ||
4034 | offset = offset_in_page(gpa); | |
4035 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4036 | |
4037 | /* | |
4038 | * Sometimes, the OS only writes the last one bytes to update status | |
4039 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4040 | */ | |
4041 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4042 | return false; | |
4043 | ||
889e5cbc XG |
4044 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4045 | misaligned |= bytes < 4; | |
4046 | ||
4047 | return misaligned; | |
4048 | } | |
4049 | ||
4050 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4051 | { | |
4052 | unsigned page_offset, quadrant; | |
4053 | u64 *spte; | |
4054 | int level; | |
4055 | ||
4056 | page_offset = offset_in_page(gpa); | |
4057 | level = sp->role.level; | |
4058 | *nspte = 1; | |
4059 | if (!sp->role.cr4_pae) { | |
4060 | page_offset <<= 1; /* 32->64 */ | |
4061 | /* | |
4062 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4063 | * only 2MB. So we need to double the offset again | |
4064 | * and zap two pdes instead of one. | |
4065 | */ | |
4066 | if (level == PT32_ROOT_LEVEL) { | |
4067 | page_offset &= ~7; /* kill rounding error */ | |
4068 | page_offset <<= 1; | |
4069 | *nspte = 2; | |
4070 | } | |
4071 | quadrant = page_offset >> PAGE_SHIFT; | |
4072 | page_offset &= ~PAGE_MASK; | |
4073 | if (quadrant != sp->role.quadrant) | |
4074 | return NULL; | |
4075 | } | |
4076 | ||
4077 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4078 | return spte; | |
4079 | } | |
4080 | ||
4081 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4082 | const u8 *new, int bytes) | |
4083 | { | |
4084 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
4085 | union kvm_mmu_page_role mask = { .word = 0 }; | |
4086 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
4087 | LIST_HEAD(invalid_list); |
4088 | u64 entry, gentry, *spte; | |
4089 | int npte; | |
a30f47cb | 4090 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
4091 | |
4092 | /* | |
4093 | * If we don't have indirect shadow pages, it means no page is | |
4094 | * write-protected, so we can exit simply. | |
4095 | */ | |
4096 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4097 | return; | |
4098 | ||
4099 | zap_page = remote_flush = local_flush = false; | |
4100 | ||
4101 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4102 | ||
4103 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4104 | ||
4105 | /* | |
4106 | * No need to care whether allocation memory is successful | |
4107 | * or not since pte prefetch is skiped if it does not have | |
4108 | * enough objects in the cache. | |
4109 | */ | |
4110 | mmu_topup_memory_caches(vcpu); | |
4111 | ||
4112 | spin_lock(&vcpu->kvm->mmu_lock); | |
4113 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4114 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4115 | |
fa1de2bf | 4116 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 4117 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4118 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4119 | detect_write_flooding(sp)) { |
0671a8e7 | 4120 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4121 | &invalid_list); |
4cee5764 | 4122 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4123 | continue; |
4124 | } | |
889e5cbc XG |
4125 | |
4126 | spte = get_written_sptes(sp, gpa, &npte); | |
4127 | if (!spte) | |
4128 | continue; | |
4129 | ||
0671a8e7 | 4130 | local_flush = true; |
ac1b714e | 4131 | while (npte--) { |
79539cec | 4132 | entry = *spte; |
38e3b2b2 | 4133 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4134 | if (gentry && |
4135 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4136 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4137 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4138 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4139 | remote_flush = true; |
ac1b714e | 4140 | ++spte; |
9b7a0325 | 4141 | } |
9b7a0325 | 4142 | } |
0671a8e7 | 4143 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4144 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4145 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4146 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4147 | } |
4148 | ||
a436036b AK |
4149 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4150 | { | |
10589a46 MT |
4151 | gpa_t gpa; |
4152 | int r; | |
a436036b | 4153 | |
c5a78f2b | 4154 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4155 | return 0; |
4156 | ||
1871c602 | 4157 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4158 | |
10589a46 | 4159 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4160 | |
10589a46 | 4161 | return r; |
a436036b | 4162 | } |
577bdc49 | 4163 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4164 | |
81f4f76b | 4165 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4166 | { |
d98ba053 | 4167 | LIST_HEAD(invalid_list); |
103ad25a | 4168 | |
81f4f76b TY |
4169 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4170 | return; | |
4171 | ||
5da59607 TY |
4172 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4173 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4174 | break; | |
ebeace86 | 4175 | |
4cee5764 | 4176 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4177 | } |
aa6bd187 | 4178 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4179 | } |
ebeace86 | 4180 | |
1cb3f3ae XG |
4181 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4182 | { | |
4183 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4184 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4185 | ||
4186 | return vcpu_match_mmio_gva(vcpu, addr); | |
4187 | } | |
4188 | ||
dc25e89e AP |
4189 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4190 | void *insn, int insn_len) | |
3067714c | 4191 | { |
1cb3f3ae | 4192 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4193 | enum emulation_result er; |
4194 | ||
56028d08 | 4195 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4196 | if (r < 0) |
4197 | goto out; | |
4198 | ||
4199 | if (!r) { | |
4200 | r = 1; | |
4201 | goto out; | |
4202 | } | |
4203 | ||
1cb3f3ae XG |
4204 | if (is_mmio_page_fault(vcpu, cr2)) |
4205 | emulation_type = 0; | |
4206 | ||
4207 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4208 | |
4209 | switch (er) { | |
4210 | case EMULATE_DONE: | |
4211 | return 1; | |
ac0a48c3 | 4212 | case EMULATE_USER_EXIT: |
3067714c | 4213 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4214 | /* fall through */ |
3067714c | 4215 | case EMULATE_FAIL: |
3f5d18a9 | 4216 | return 0; |
3067714c AK |
4217 | default: |
4218 | BUG(); | |
4219 | } | |
4220 | out: | |
3067714c AK |
4221 | return r; |
4222 | } | |
4223 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4224 | ||
a7052897 MT |
4225 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4226 | { | |
a7052897 | 4227 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4228 | kvm_mmu_flush_tlb(vcpu); |
4229 | ++vcpu->stat.invlpg; | |
4230 | } | |
4231 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4232 | ||
18552672 JR |
4233 | void kvm_enable_tdp(void) |
4234 | { | |
4235 | tdp_enabled = true; | |
4236 | } | |
4237 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4238 | ||
5f4cb662 JR |
4239 | void kvm_disable_tdp(void) |
4240 | { | |
4241 | tdp_enabled = false; | |
4242 | } | |
4243 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4244 | ||
6aa8b732 AK |
4245 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4246 | { | |
ad312c7c | 4247 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4248 | if (vcpu->arch.mmu.lm_root != NULL) |
4249 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4250 | } |
4251 | ||
4252 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4253 | { | |
17ac10ad | 4254 | struct page *page; |
6aa8b732 AK |
4255 | int i; |
4256 | ||
4257 | ASSERT(vcpu); | |
4258 | ||
17ac10ad AK |
4259 | /* |
4260 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4261 | * Therefore we need to allocate shadow page tables in the first | |
4262 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4263 | */ | |
4264 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4265 | if (!page) | |
d7fa6ab2 WY |
4266 | return -ENOMEM; |
4267 | ||
ad312c7c | 4268 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4269 | for (i = 0; i < 4; ++i) |
ad312c7c | 4270 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4271 | |
6aa8b732 | 4272 | return 0; |
6aa8b732 AK |
4273 | } |
4274 | ||
8018c27b | 4275 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4276 | { |
6aa8b732 | 4277 | ASSERT(vcpu); |
e459e322 XG |
4278 | |
4279 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4280 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4281 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4282 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4283 | |
8018c27b IM |
4284 | return alloc_mmu_pages(vcpu); |
4285 | } | |
6aa8b732 | 4286 | |
8a3c1a33 | 4287 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b IM |
4288 | { |
4289 | ASSERT(vcpu); | |
ad312c7c | 4290 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4291 | |
8a3c1a33 | 4292 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4293 | } |
4294 | ||
90cb0529 | 4295 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4296 | { |
b99db1d3 TY |
4297 | struct kvm_memory_slot *memslot; |
4298 | gfn_t last_gfn; | |
4299 | int i; | |
6aa8b732 | 4300 | |
b99db1d3 TY |
4301 | memslot = id_to_memslot(kvm->memslots, slot); |
4302 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4303 | |
9d1beefb TY |
4304 | spin_lock(&kvm->mmu_lock); |
4305 | ||
b99db1d3 TY |
4306 | for (i = PT_PAGE_TABLE_LEVEL; |
4307 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4308 | unsigned long *rmapp; | |
4309 | unsigned long last_index, index; | |
6aa8b732 | 4310 | |
b99db1d3 TY |
4311 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4312 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4313 | |
b99db1d3 TY |
4314 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4315 | if (*rmapp) | |
4316 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e | 4317 | |
198c74f4 | 4318 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) |
6b81b05e | 4319 | cond_resched_lock(&kvm->mmu_lock); |
8234b22e | 4320 | } |
6aa8b732 | 4321 | } |
b99db1d3 | 4322 | |
9d1beefb | 4323 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
4324 | |
4325 | /* | |
4326 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
4327 | * which do tlb flush out of mmu-lock should be serialized by | |
4328 | * kvm->slots_lock otherwise tlb flush would be missed. | |
4329 | */ | |
4330 | lockdep_assert_held(&kvm->slots_lock); | |
4331 | ||
4332 | /* | |
4333 | * We can flush all the TLBs out of the mmu lock without TLB | |
4334 | * corruption since we just change the spte from writable to | |
4335 | * readonly so that we only need to care the case of changing | |
4336 | * spte from present to present (changing the spte from present | |
4337 | * to nonpresent will flush all the TLBs immediately), in other | |
4338 | * words, the only case we care is mmu_spte_update() where we | |
4339 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
4340 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
4341 | * on PT_WRITABLE_MASK anymore. | |
4342 | */ | |
4343 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 4344 | } |
37a7d8b0 | 4345 | |
e7d11c7a | 4346 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4347 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4348 | { | |
4349 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4350 | int batch = 0; |
5304b8d3 XG |
4351 | |
4352 | restart: | |
4353 | list_for_each_entry_safe_reverse(sp, node, | |
4354 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4355 | int ret; |
4356 | ||
5304b8d3 XG |
4357 | /* |
4358 | * No obsolete page exists before new created page since | |
4359 | * active_mmu_pages is the FIFO list. | |
4360 | */ | |
4361 | if (!is_obsolete_sp(kvm, sp)) | |
4362 | break; | |
4363 | ||
4364 | /* | |
5304b8d3 XG |
4365 | * Since we are reversely walking the list and the invalid |
4366 | * list will be moved to the head, skip the invalid page | |
4367 | * can help us to avoid the infinity list walking. | |
4368 | */ | |
4369 | if (sp->role.invalid) | |
4370 | continue; | |
4371 | ||
f34d251d XG |
4372 | /* |
4373 | * Need not flush tlb since we only zap the sp with invalid | |
4374 | * generation number. | |
4375 | */ | |
e7d11c7a | 4376 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4377 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4378 | batch = 0; |
5304b8d3 XG |
4379 | goto restart; |
4380 | } | |
4381 | ||
365c8868 XG |
4382 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4383 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4384 | batch += ret; |
4385 | ||
4386 | if (ret) | |
5304b8d3 XG |
4387 | goto restart; |
4388 | } | |
4389 | ||
f34d251d XG |
4390 | /* |
4391 | * Should flush tlb before free page tables since lockless-walking | |
4392 | * may use the pages. | |
4393 | */ | |
365c8868 | 4394 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4395 | } |
4396 | ||
4397 | /* | |
4398 | * Fast invalidate all shadow pages and use lock-break technique | |
4399 | * to zap obsolete pages. | |
4400 | * | |
4401 | * It's required when memslot is being deleted or VM is being | |
4402 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4403 | * not use any resource of the being-deleted slot or all slots | |
4404 | * after calling the function. | |
4405 | */ | |
4406 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4407 | { | |
4408 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4409 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4410 | kvm->arch.mmu_valid_gen++; |
4411 | ||
f34d251d XG |
4412 | /* |
4413 | * Notify all vcpus to reload its shadow page table | |
4414 | * and flush TLB. Then all vcpus will switch to new | |
4415 | * shadow page table with the new mmu_valid_gen. | |
4416 | * | |
4417 | * Note: we should do this under the protection of | |
4418 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4419 | * but miss tlb flush. | |
4420 | */ | |
4421 | kvm_reload_remote_mmus(kvm); | |
4422 | ||
5304b8d3 XG |
4423 | kvm_zap_obsolete_pages(kvm); |
4424 | spin_unlock(&kvm->mmu_lock); | |
4425 | } | |
4426 | ||
365c8868 XG |
4427 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4428 | { | |
4429 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4430 | } | |
4431 | ||
f8f55942 XG |
4432 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm) |
4433 | { | |
4434 | /* | |
4435 | * The very rare case: if the generation-number is round, | |
4436 | * zap all shadow pages. | |
f8f55942 | 4437 | */ |
ee3d1570 | 4438 | if (unlikely(kvm_current_mmio_generation(kvm) == 0)) { |
7a2e8aaf | 4439 | printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 4440 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 4441 | } |
f8f55942 XG |
4442 | } |
4443 | ||
70534a73 DC |
4444 | static unsigned long |
4445 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
4446 | { |
4447 | struct kvm *kvm; | |
1495f230 | 4448 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 4449 | unsigned long freed = 0; |
3ee16c81 | 4450 | |
2f303b74 | 4451 | spin_lock(&kvm_lock); |
3ee16c81 IE |
4452 | |
4453 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4454 | int idx; |
d98ba053 | 4455 | LIST_HEAD(invalid_list); |
3ee16c81 | 4456 | |
35f2d16b TY |
4457 | /* |
4458 | * Never scan more than sc->nr_to_scan VM instances. | |
4459 | * Will not hit this condition practically since we do not try | |
4460 | * to shrink more than one VM and it is very unlikely to see | |
4461 | * !n_used_mmu_pages so many times. | |
4462 | */ | |
4463 | if (!nr_to_scan--) | |
4464 | break; | |
19526396 GN |
4465 | /* |
4466 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4467 | * here. We may skip a VM instance errorneosly, but we do not | |
4468 | * want to shrink a VM that only started to populate its MMU | |
4469 | * anyway. | |
4470 | */ | |
365c8868 XG |
4471 | if (!kvm->arch.n_used_mmu_pages && |
4472 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4473 | continue; |
19526396 | 4474 | |
f656ce01 | 4475 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4476 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4477 | |
365c8868 XG |
4478 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4479 | kvm_mmu_commit_zap_page(kvm, | |
4480 | &kvm->arch.zapped_obsolete_pages); | |
4481 | goto unlock; | |
4482 | } | |
4483 | ||
70534a73 DC |
4484 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
4485 | freed++; | |
d98ba053 | 4486 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4487 | |
365c8868 | 4488 | unlock: |
3ee16c81 | 4489 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4490 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 4491 | |
70534a73 DC |
4492 | /* |
4493 | * unfair on small ones | |
4494 | * per-vm shrinkers cry out | |
4495 | * sadness comes quickly | |
4496 | */ | |
19526396 GN |
4497 | list_move_tail(&kvm->vm_list, &vm_list); |
4498 | break; | |
3ee16c81 | 4499 | } |
3ee16c81 | 4500 | |
2f303b74 | 4501 | spin_unlock(&kvm_lock); |
70534a73 | 4502 | return freed; |
70534a73 DC |
4503 | } |
4504 | ||
4505 | static unsigned long | |
4506 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
4507 | { | |
45221ab6 | 4508 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
4509 | } |
4510 | ||
4511 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
4512 | .count_objects = mmu_shrink_count, |
4513 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
4514 | .seeks = DEFAULT_SEEKS * 10, |
4515 | }; | |
4516 | ||
2ddfd20e | 4517 | static void mmu_destroy_caches(void) |
b5a33a75 | 4518 | { |
53c07b18 XG |
4519 | if (pte_list_desc_cache) |
4520 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4521 | if (mmu_page_header_cache) |
4522 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4523 | } |
4524 | ||
4525 | int kvm_mmu_module_init(void) | |
4526 | { | |
53c07b18 XG |
4527 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4528 | sizeof(struct pte_list_desc), | |
20c2df83 | 4529 | 0, 0, NULL); |
53c07b18 | 4530 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4531 | goto nomem; |
4532 | ||
d3d25b04 AK |
4533 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4534 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4535 | 0, 0, NULL); |
d3d25b04 AK |
4536 | if (!mmu_page_header_cache) |
4537 | goto nomem; | |
4538 | ||
45bf21a8 WY |
4539 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4540 | goto nomem; | |
4541 | ||
3ee16c81 IE |
4542 | register_shrinker(&mmu_shrinker); |
4543 | ||
b5a33a75 AK |
4544 | return 0; |
4545 | ||
4546 | nomem: | |
3ee16c81 | 4547 | mmu_destroy_caches(); |
b5a33a75 AK |
4548 | return -ENOMEM; |
4549 | } | |
4550 | ||
3ad82a7e ZX |
4551 | /* |
4552 | * Caculate mmu pages needed for kvm. | |
4553 | */ | |
4554 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4555 | { | |
3ad82a7e ZX |
4556 | unsigned int nr_mmu_pages; |
4557 | unsigned int nr_pages = 0; | |
bc6678a3 | 4558 | struct kvm_memslots *slots; |
be6ba0f0 | 4559 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4560 | |
90d83dc3 LJ |
4561 | slots = kvm_memslots(kvm); |
4562 | ||
be6ba0f0 XG |
4563 | kvm_for_each_memslot(memslot, slots) |
4564 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4565 | |
4566 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4567 | nr_mmu_pages = max(nr_mmu_pages, | |
4568 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4569 | ||
4570 | return nr_mmu_pages; | |
4571 | } | |
4572 | ||
94d8b056 MT |
4573 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4574 | { | |
4575 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4576 | u64 spte; |
94d8b056 MT |
4577 | int nr_sptes = 0; |
4578 | ||
37f6a4e2 MT |
4579 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
4580 | return nr_sptes; | |
4581 | ||
c2a2ac2b XG |
4582 | walk_shadow_page_lockless_begin(vcpu); |
4583 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4584 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4585 | nr_sptes++; |
c2a2ac2b | 4586 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4587 | break; |
4588 | } | |
c2a2ac2b | 4589 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4590 | |
4591 | return nr_sptes; | |
4592 | } | |
4593 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4594 | ||
c42fffe3 XG |
4595 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4596 | { | |
4597 | ASSERT(vcpu); | |
4598 | ||
95f93af4 | 4599 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
4600 | free_mmu_pages(vcpu); |
4601 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4602 | } |
4603 | ||
b034cf01 XG |
4604 | void kvm_mmu_module_exit(void) |
4605 | { | |
4606 | mmu_destroy_caches(); | |
4607 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4608 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4609 | mmu_audit_disable(); |
4610 | } |