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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 113 | |
6aa8b732 AK |
114 | #define PT64_INDEX(address, level)\ |
115 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
118 | #define PT32_LEVEL_BITS 10 | |
119 | ||
120 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 121 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 122 | |
e04da980 JR |
123 | #define PT32_LVL_OFFSET_MASK(level) \ |
124 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
126 | |
127 | #define PT32_INDEX(address, level)\ | |
128 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
129 | ||
130 | ||
27aba766 | 131 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
132 | #define PT64_DIR_BASE_ADDR_MASK \ |
133 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
134 | #define PT64_LVL_ADDR_MASK(level) \ |
135 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
136 | * PT64_LEVEL_BITS))) - 1)) | |
137 | #define PT64_LVL_OFFSET_MASK(level) \ | |
138 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
140 | |
141 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
142 | #define PT32_DIR_BASE_ADDR_MASK \ | |
143 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
144 | #define PT32_LVL_ADDR_MASK(level) \ |
145 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
146 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 147 | |
79539cec AK |
148 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
149 | | PT64_NX_MASK) | |
6aa8b732 | 150 | |
53c07b18 | 151 | #define PTE_LIST_EXT 4 |
cd4a4e53 | 152 | |
fe135d2c AK |
153 | #define ACC_EXEC_MASK 1 |
154 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
155 | #define ACC_USER_MASK PT_USER_MASK | |
156 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
157 | ||
90bb6fc5 AK |
158 | #include <trace/events/kvm.h> |
159 | ||
07420171 AK |
160 | #define CREATE_TRACE_POINTS |
161 | #include "mmutrace.h" | |
162 | ||
1403283a IE |
163 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
164 | ||
135f8c2b AK |
165 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
166 | ||
53c07b18 XG |
167 | struct pte_list_desc { |
168 | u64 *sptes[PTE_LIST_EXT]; | |
169 | struct pte_list_desc *more; | |
cd4a4e53 AK |
170 | }; |
171 | ||
2d11123a AK |
172 | struct kvm_shadow_walk_iterator { |
173 | u64 addr; | |
174 | hpa_t shadow_addr; | |
175 | int level; | |
176 | u64 *sptep; | |
177 | unsigned index; | |
178 | }; | |
179 | ||
180 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
181 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
182 | shadow_walk_okay(&(_walker)); \ | |
183 | shadow_walk_next(&(_walker))) | |
184 | ||
53c07b18 | 185 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 186 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 187 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 188 | |
c7addb90 AK |
189 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
190 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
191 | static u64 __read_mostly shadow_nx_mask; |
192 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
193 | static u64 __read_mostly shadow_user_mask; | |
194 | static u64 __read_mostly shadow_accessed_mask; | |
195 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 196 | |
82725b20 DE |
197 | static inline u64 rsvd_bits(int s, int e) |
198 | { | |
199 | return ((1ULL << (e - s + 1)) - 1) << s; | |
200 | } | |
201 | ||
c7addb90 AK |
202 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
203 | { | |
204 | shadow_trap_nonpresent_pte = trap_pte; | |
205 | shadow_notrap_nonpresent_pte = notrap_pte; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
208 | ||
7b52345e | 209 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 210 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
211 | { |
212 | shadow_user_mask = user_mask; | |
213 | shadow_accessed_mask = accessed_mask; | |
214 | shadow_dirty_mask = dirty_mask; | |
215 | shadow_nx_mask = nx_mask; | |
216 | shadow_x_mask = x_mask; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
219 | ||
6aa8b732 AK |
220 | static int is_cpuid_PSE36(void) |
221 | { | |
222 | return 1; | |
223 | } | |
224 | ||
73b1087e AK |
225 | static int is_nx(struct kvm_vcpu *vcpu) |
226 | { | |
f6801dff | 227 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
228 | } |
229 | ||
c7addb90 AK |
230 | static int is_shadow_present_pte(u64 pte) |
231 | { | |
c7addb90 AK |
232 | return pte != shadow_trap_nonpresent_pte |
233 | && pte != shadow_notrap_nonpresent_pte; | |
234 | } | |
235 | ||
05da4558 MT |
236 | static int is_large_pte(u64 pte) |
237 | { | |
238 | return pte & PT_PAGE_SIZE_MASK; | |
239 | } | |
240 | ||
43a3795a | 241 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 242 | { |
439e218a | 243 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
244 | } |
245 | ||
43a3795a | 246 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 247 | { |
4b1a80fa | 248 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
249 | } |
250 | ||
776e6633 MT |
251 | static int is_last_spte(u64 pte, int level) |
252 | { | |
253 | if (level == PT_PAGE_TABLE_LEVEL) | |
254 | return 1; | |
852e3c19 | 255 | if (is_large_pte(pte)) |
776e6633 MT |
256 | return 1; |
257 | return 0; | |
258 | } | |
259 | ||
35149e21 | 260 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 261 | { |
35149e21 | 262 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
263 | } |
264 | ||
da928521 AK |
265 | static gfn_t pse36_gfn_delta(u32 gpte) |
266 | { | |
267 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
268 | ||
269 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
270 | } | |
271 | ||
d555c333 | 272 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 273 | { |
7645e432 | 274 | set_64bit(sptep, spte); |
e663ee64 AK |
275 | } |
276 | ||
a9221dd5 AK |
277 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
278 | { | |
279 | #ifdef CONFIG_X86_64 | |
280 | return xchg(sptep, new_spte); | |
281 | #else | |
282 | u64 old_spte; | |
283 | ||
284 | do { | |
285 | old_spte = *sptep; | |
286 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
287 | ||
288 | return old_spte; | |
289 | #endif | |
290 | } | |
291 | ||
8672b721 XG |
292 | static bool spte_has_volatile_bits(u64 spte) |
293 | { | |
294 | if (!shadow_accessed_mask) | |
295 | return false; | |
296 | ||
297 | if (!is_shadow_present_pte(spte)) | |
298 | return false; | |
299 | ||
4132779b XG |
300 | if ((spte & shadow_accessed_mask) && |
301 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
302 | return false; |
303 | ||
304 | return true; | |
305 | } | |
306 | ||
4132779b XG |
307 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
308 | { | |
309 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
310 | } | |
311 | ||
b79b93f9 AK |
312 | static void update_spte(u64 *sptep, u64 new_spte) |
313 | { | |
4132779b XG |
314 | u64 mask, old_spte = *sptep; |
315 | ||
316 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 317 | |
4132779b XG |
318 | new_spte |= old_spte & shadow_dirty_mask; |
319 | ||
320 | mask = shadow_accessed_mask; | |
321 | if (is_writable_pte(old_spte)) | |
322 | mask |= shadow_dirty_mask; | |
323 | ||
324 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 325 | __set_spte(sptep, new_spte); |
4132779b | 326 | else |
b79b93f9 | 327 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
328 | |
329 | if (!shadow_accessed_mask) | |
330 | return; | |
331 | ||
332 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
333 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
334 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
335 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
336 | } |
337 | ||
e2dec939 | 338 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 339 | struct kmem_cache *base_cache, int min) |
714b93da AK |
340 | { |
341 | void *obj; | |
342 | ||
343 | if (cache->nobjs >= min) | |
e2dec939 | 344 | return 0; |
714b93da | 345 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 346 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 347 | if (!obj) |
e2dec939 | 348 | return -ENOMEM; |
714b93da AK |
349 | cache->objects[cache->nobjs++] = obj; |
350 | } | |
e2dec939 | 351 | return 0; |
714b93da AK |
352 | } |
353 | ||
e8ad9a70 XG |
354 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
355 | struct kmem_cache *cache) | |
714b93da AK |
356 | { |
357 | while (mc->nobjs) | |
e8ad9a70 | 358 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
359 | } |
360 | ||
c1158e63 | 361 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 362 | int min) |
c1158e63 | 363 | { |
842f22ed | 364 | void *page; |
c1158e63 AK |
365 | |
366 | if (cache->nobjs >= min) | |
367 | return 0; | |
368 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 369 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
370 | if (!page) |
371 | return -ENOMEM; | |
842f22ed | 372 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
373 | } |
374 | return 0; | |
375 | } | |
376 | ||
377 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
378 | { | |
379 | while (mc->nobjs) | |
c4d198d5 | 380 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
381 | } |
382 | ||
2e3e5882 | 383 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 384 | { |
e2dec939 AK |
385 | int r; |
386 | ||
53c07b18 | 387 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 388 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
389 | if (r) |
390 | goto out; | |
ad312c7c | 391 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
392 | if (r) |
393 | goto out; | |
ad312c7c | 394 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 395 | mmu_page_header_cache, 4); |
e2dec939 AK |
396 | out: |
397 | return r; | |
714b93da AK |
398 | } |
399 | ||
400 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
401 | { | |
53c07b18 XG |
402 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
403 | pte_list_desc_cache); | |
ad312c7c | 404 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
405 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
406 | mmu_page_header_cache); | |
714b93da AK |
407 | } |
408 | ||
409 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
410 | size_t size) | |
411 | { | |
412 | void *p; | |
413 | ||
414 | BUG_ON(!mc->nobjs); | |
415 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
416 | return p; |
417 | } | |
418 | ||
53c07b18 | 419 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 420 | { |
53c07b18 XG |
421 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
422 | sizeof(struct pte_list_desc)); | |
714b93da AK |
423 | } |
424 | ||
53c07b18 | 425 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 426 | { |
53c07b18 | 427 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
428 | } |
429 | ||
2032a93d LJ |
430 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
431 | { | |
432 | if (!sp->role.direct) | |
433 | return sp->gfns[index]; | |
434 | ||
435 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
436 | } | |
437 | ||
438 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
439 | { | |
440 | if (sp->role.direct) | |
441 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
442 | else | |
443 | sp->gfns[index] = gfn; | |
444 | } | |
445 | ||
05da4558 | 446 | /* |
d4dbf470 TY |
447 | * Return the pointer to the large page information for a given gfn, |
448 | * handling slots that are not large page aligned. | |
05da4558 | 449 | */ |
d4dbf470 TY |
450 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
451 | struct kvm_memory_slot *slot, | |
452 | int level) | |
05da4558 MT |
453 | { |
454 | unsigned long idx; | |
455 | ||
82855413 JR |
456 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
457 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d4dbf470 | 458 | return &slot->lpage_info[level - 2][idx]; |
05da4558 MT |
459 | } |
460 | ||
461 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
462 | { | |
d25797b2 | 463 | struct kvm_memory_slot *slot; |
d4dbf470 | 464 | struct kvm_lpage_info *linfo; |
d25797b2 | 465 | int i; |
05da4558 | 466 | |
a1f4d395 | 467 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
468 | for (i = PT_DIRECTORY_LEVEL; |
469 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
470 | linfo = lpage_info_slot(gfn, slot, i); |
471 | linfo->write_count += 1; | |
d25797b2 | 472 | } |
332b207d | 473 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
474 | } |
475 | ||
476 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
477 | { | |
d25797b2 | 478 | struct kvm_memory_slot *slot; |
d4dbf470 | 479 | struct kvm_lpage_info *linfo; |
d25797b2 | 480 | int i; |
05da4558 | 481 | |
a1f4d395 | 482 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
483 | for (i = PT_DIRECTORY_LEVEL; |
484 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
485 | linfo = lpage_info_slot(gfn, slot, i); |
486 | linfo->write_count -= 1; | |
487 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 488 | } |
332b207d | 489 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
490 | } |
491 | ||
d25797b2 JR |
492 | static int has_wrprotected_page(struct kvm *kvm, |
493 | gfn_t gfn, | |
494 | int level) | |
05da4558 | 495 | { |
2843099f | 496 | struct kvm_memory_slot *slot; |
d4dbf470 | 497 | struct kvm_lpage_info *linfo; |
05da4558 | 498 | |
a1f4d395 | 499 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 500 | if (slot) { |
d4dbf470 TY |
501 | linfo = lpage_info_slot(gfn, slot, level); |
502 | return linfo->write_count; | |
05da4558 MT |
503 | } |
504 | ||
505 | return 1; | |
506 | } | |
507 | ||
d25797b2 | 508 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 509 | { |
8f0b1ab6 | 510 | unsigned long page_size; |
d25797b2 | 511 | int i, ret = 0; |
05da4558 | 512 | |
8f0b1ab6 | 513 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 514 | |
d25797b2 JR |
515 | for (i = PT_PAGE_TABLE_LEVEL; |
516 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
517 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
518 | ret = i; | |
519 | else | |
520 | break; | |
521 | } | |
522 | ||
4c2155ce | 523 | return ret; |
05da4558 MT |
524 | } |
525 | ||
5d163b1c XG |
526 | static struct kvm_memory_slot * |
527 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
528 | bool no_dirty_log) | |
05da4558 MT |
529 | { |
530 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
531 | |
532 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
533 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
534 | (no_dirty_log && slot->dirty_bitmap)) | |
535 | slot = NULL; | |
536 | ||
537 | return slot; | |
538 | } | |
539 | ||
540 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
541 | { | |
a0a8eaba | 542 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
543 | } |
544 | ||
545 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
546 | { | |
547 | int host_level, level, max_level; | |
05da4558 | 548 | |
d25797b2 JR |
549 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
550 | ||
551 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
552 | return host_level; | |
553 | ||
878403b7 SY |
554 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
555 | kvm_x86_ops->get_lpage_level() : host_level; | |
556 | ||
557 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
558 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
559 | break; | |
d25797b2 JR |
560 | |
561 | return level - 1; | |
05da4558 MT |
562 | } |
563 | ||
290fc38d | 564 | /* |
53c07b18 | 565 | * Pte mapping structures: |
cd4a4e53 | 566 | * |
53c07b18 | 567 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 568 | * |
53c07b18 XG |
569 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
570 | * pte_list_desc containing more mappings. | |
53a27b39 | 571 | * |
53c07b18 | 572 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
573 | * the spte was not added. |
574 | * | |
cd4a4e53 | 575 | */ |
53c07b18 XG |
576 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
577 | unsigned long *pte_list) | |
cd4a4e53 | 578 | { |
53c07b18 | 579 | struct pte_list_desc *desc; |
53a27b39 | 580 | int i, count = 0; |
cd4a4e53 | 581 | |
53c07b18 XG |
582 | if (!*pte_list) { |
583 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
584 | *pte_list = (unsigned long)spte; | |
585 | } else if (!(*pte_list & 1)) { | |
586 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
587 | desc = mmu_alloc_pte_list_desc(vcpu); | |
588 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 589 | desc->sptes[1] = spte; |
53c07b18 | 590 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 591 | ++count; |
cd4a4e53 | 592 | } else { |
53c07b18 XG |
593 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
594 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
595 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 596 | desc = desc->more; |
53c07b18 | 597 | count += PTE_LIST_EXT; |
53a27b39 | 598 | } |
53c07b18 XG |
599 | if (desc->sptes[PTE_LIST_EXT-1]) { |
600 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
601 | desc = desc->more; |
602 | } | |
d555c333 | 603 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 604 | ++count; |
d555c333 | 605 | desc->sptes[i] = spte; |
cd4a4e53 | 606 | } |
53a27b39 | 607 | return count; |
cd4a4e53 AK |
608 | } |
609 | ||
53c07b18 XG |
610 | static u64 *pte_list_next(unsigned long *pte_list, u64 *spte) |
611 | { | |
612 | struct pte_list_desc *desc; | |
613 | u64 *prev_spte; | |
614 | int i; | |
615 | ||
616 | if (!*pte_list) | |
617 | return NULL; | |
618 | else if (!(*pte_list & 1)) { | |
619 | if (!spte) | |
620 | return (u64 *)*pte_list; | |
621 | return NULL; | |
622 | } | |
623 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
624 | prev_spte = NULL; | |
625 | while (desc) { | |
626 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { | |
627 | if (prev_spte == spte) | |
628 | return desc->sptes[i]; | |
629 | prev_spte = desc->sptes[i]; | |
630 | } | |
631 | desc = desc->more; | |
632 | } | |
633 | return NULL; | |
634 | } | |
635 | ||
636 | static void | |
637 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
638 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
639 | { |
640 | int j; | |
641 | ||
53c07b18 | 642 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 643 | ; |
d555c333 AK |
644 | desc->sptes[i] = desc->sptes[j]; |
645 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
646 | if (j != 0) |
647 | return; | |
648 | if (!prev_desc && !desc->more) | |
53c07b18 | 649 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
650 | else |
651 | if (prev_desc) | |
652 | prev_desc->more = desc->more; | |
653 | else | |
53c07b18 XG |
654 | *pte_list = (unsigned long)desc->more | 1; |
655 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
656 | } |
657 | ||
53c07b18 | 658 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 659 | { |
53c07b18 XG |
660 | struct pte_list_desc *desc; |
661 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
662 | int i; |
663 | ||
53c07b18 XG |
664 | if (!*pte_list) { |
665 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 666 | BUG(); |
53c07b18 XG |
667 | } else if (!(*pte_list & 1)) { |
668 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
669 | if ((u64 *)*pte_list != spte) { | |
670 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
671 | BUG(); |
672 | } | |
53c07b18 | 673 | *pte_list = 0; |
cd4a4e53 | 674 | } else { |
53c07b18 XG |
675 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
676 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
677 | prev_desc = NULL; |
678 | while (desc) { | |
53c07b18 | 679 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 680 | if (desc->sptes[i] == spte) { |
53c07b18 | 681 | pte_list_desc_remove_entry(pte_list, |
714b93da | 682 | desc, i, |
cd4a4e53 AK |
683 | prev_desc); |
684 | return; | |
685 | } | |
686 | prev_desc = desc; | |
687 | desc = desc->more; | |
688 | } | |
53c07b18 | 689 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
690 | BUG(); |
691 | } | |
692 | } | |
693 | ||
67052b35 XG |
694 | typedef void (*pte_list_walk_fn) (u64 *spte); |
695 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
696 | { | |
697 | struct pte_list_desc *desc; | |
698 | int i; | |
699 | ||
700 | if (!*pte_list) | |
701 | return; | |
702 | ||
703 | if (!(*pte_list & 1)) | |
704 | return fn((u64 *)*pte_list); | |
705 | ||
706 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
707 | while (desc) { | |
708 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
709 | fn(desc->sptes[i]); | |
710 | desc = desc->more; | |
711 | } | |
712 | } | |
713 | ||
53c07b18 XG |
714 | /* |
715 | * Take gfn and return the reverse mapping to it. | |
716 | */ | |
717 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
718 | { | |
719 | struct kvm_memory_slot *slot; | |
720 | struct kvm_lpage_info *linfo; | |
721 | ||
722 | slot = gfn_to_memslot(kvm, gfn); | |
723 | if (likely(level == PT_PAGE_TABLE_LEVEL)) | |
724 | return &slot->rmap[gfn - slot->base_gfn]; | |
725 | ||
726 | linfo = lpage_info_slot(gfn, slot, level); | |
727 | ||
728 | return &linfo->rmap_pde; | |
729 | } | |
730 | ||
731 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) | |
732 | { | |
733 | struct kvm_mmu_page *sp; | |
734 | unsigned long *rmapp; | |
735 | ||
53c07b18 XG |
736 | sp = page_header(__pa(spte)); |
737 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
738 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
739 | return pte_list_add(vcpu, spte, rmapp); | |
740 | } | |
741 | ||
742 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) | |
743 | { | |
744 | return pte_list_next(rmapp, spte); | |
745 | } | |
746 | ||
747 | static void rmap_remove(struct kvm *kvm, u64 *spte) | |
748 | { | |
749 | struct kvm_mmu_page *sp; | |
750 | gfn_t gfn; | |
751 | unsigned long *rmapp; | |
752 | ||
753 | sp = page_header(__pa(spte)); | |
754 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
755 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
756 | pte_list_remove(spte, rmapp); | |
757 | } | |
758 | ||
eb45fda4 | 759 | static int set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 760 | { |
ce061867 | 761 | pfn_t pfn; |
9a3aad70 XG |
762 | u64 old_spte = *sptep; |
763 | ||
8672b721 | 764 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 765 | __set_spte(sptep, new_spte); |
8672b721 | 766 | else |
9a3aad70 | 767 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 768 | |
a9221dd5 | 769 | if (!is_rmap_spte(old_spte)) |
eb45fda4 | 770 | return 0; |
8672b721 | 771 | |
a9221dd5 | 772 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 773 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 774 | kvm_set_pfn_accessed(pfn); |
4132779b | 775 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 776 | kvm_set_pfn_dirty(pfn); |
eb45fda4 | 777 | return 1; |
e4b502ea XG |
778 | } |
779 | ||
780 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
781 | { | |
eb45fda4 MT |
782 | if (set_spte_track_bits(sptep, new_spte)) |
783 | rmap_remove(kvm, sptep); | |
be38d276 AK |
784 | } |
785 | ||
b1a36821 | 786 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 787 | { |
290fc38d | 788 | unsigned long *rmapp; |
374cbac0 | 789 | u64 *spte; |
44ad9944 | 790 | int i, write_protected = 0; |
374cbac0 | 791 | |
44ad9944 | 792 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 793 | |
98348e95 IE |
794 | spte = rmap_next(kvm, rmapp, NULL); |
795 | while (spte) { | |
374cbac0 | 796 | BUG_ON(!spte); |
374cbac0 | 797 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 798 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 799 | if (is_writable_pte(*spte)) { |
b79b93f9 | 800 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
801 | write_protected = 1; |
802 | } | |
9647c14c | 803 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 804 | } |
855149aa | 805 | |
05da4558 | 806 | /* check for huge page mappings */ |
44ad9944 JR |
807 | for (i = PT_DIRECTORY_LEVEL; |
808 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
809 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
810 | spte = rmap_next(kvm, rmapp, NULL); | |
811 | while (spte) { | |
812 | BUG_ON(!spte); | |
813 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
814 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
815 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 816 | if (is_writable_pte(*spte)) { |
be38d276 AK |
817 | drop_spte(kvm, spte, |
818 | shadow_trap_nonpresent_pte); | |
44ad9944 | 819 | --kvm->stat.lpages; |
44ad9944 JR |
820 | spte = NULL; |
821 | write_protected = 1; | |
822 | } | |
823 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 824 | } |
05da4558 MT |
825 | } |
826 | ||
b1a36821 | 827 | return write_protected; |
374cbac0 AK |
828 | } |
829 | ||
8a8365c5 FD |
830 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
831 | unsigned long data) | |
e930bffe AA |
832 | { |
833 | u64 *spte; | |
834 | int need_tlb_flush = 0; | |
835 | ||
836 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
837 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
838 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 839 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
840 | need_tlb_flush = 1; |
841 | } | |
842 | return need_tlb_flush; | |
843 | } | |
844 | ||
8a8365c5 FD |
845 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
846 | unsigned long data) | |
3da0dd43 IE |
847 | { |
848 | int need_flush = 0; | |
e4b502ea | 849 | u64 *spte, new_spte; |
3da0dd43 IE |
850 | pte_t *ptep = (pte_t *)data; |
851 | pfn_t new_pfn; | |
852 | ||
853 | WARN_ON(pte_huge(*ptep)); | |
854 | new_pfn = pte_pfn(*ptep); | |
855 | spte = rmap_next(kvm, rmapp, NULL); | |
856 | while (spte) { | |
857 | BUG_ON(!is_shadow_present_pte(*spte)); | |
858 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
859 | need_flush = 1; | |
860 | if (pte_write(*ptep)) { | |
be38d276 | 861 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
862 | spte = rmap_next(kvm, rmapp, NULL); |
863 | } else { | |
864 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
865 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
866 | ||
867 | new_spte &= ~PT_WRITABLE_MASK; | |
868 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 869 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 870 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
871 | spte = rmap_next(kvm, rmapp, spte); |
872 | } | |
873 | } | |
874 | if (need_flush) | |
875 | kvm_flush_remote_tlbs(kvm); | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
8a8365c5 FD |
880 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
881 | unsigned long data, | |
3da0dd43 | 882 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 883 | unsigned long data)) |
e930bffe | 884 | { |
852e3c19 | 885 | int i, j; |
90bb6fc5 | 886 | int ret; |
e930bffe | 887 | int retval = 0; |
bc6678a3 MT |
888 | struct kvm_memslots *slots; |
889 | ||
90d83dc3 | 890 | slots = kvm_memslots(kvm); |
e930bffe | 891 | |
46a26bf5 MT |
892 | for (i = 0; i < slots->nmemslots; i++) { |
893 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
894 | unsigned long start = memslot->userspace_addr; |
895 | unsigned long end; | |
896 | ||
e930bffe AA |
897 | end = start + (memslot->npages << PAGE_SHIFT); |
898 | if (hva >= start && hva < end) { | |
899 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 900 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 901 | |
90bb6fc5 | 902 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
903 | |
904 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
905 | struct kvm_lpage_info *linfo; |
906 | ||
907 | linfo = lpage_info_slot(gfn, memslot, | |
908 | PT_DIRECTORY_LEVEL + j); | |
909 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 910 | } |
90bb6fc5 AK |
911 | trace_kvm_age_page(hva, memslot, ret); |
912 | retval |= ret; | |
e930bffe AA |
913 | } |
914 | } | |
915 | ||
916 | return retval; | |
917 | } | |
918 | ||
919 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
920 | { | |
3da0dd43 IE |
921 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
922 | } | |
923 | ||
924 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
925 | { | |
8a8365c5 | 926 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
927 | } |
928 | ||
8a8365c5 FD |
929 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
930 | unsigned long data) | |
e930bffe AA |
931 | { |
932 | u64 *spte; | |
933 | int young = 0; | |
934 | ||
6316e1c8 RR |
935 | /* |
936 | * Emulate the accessed bit for EPT, by checking if this page has | |
937 | * an EPT mapping, and clearing it if it does. On the next access, | |
938 | * a new EPT mapping will be established. | |
939 | * This has some overhead, but not as much as the cost of swapping | |
940 | * out actively used pages or breaking up actively used hugepages. | |
941 | */ | |
534e38b4 | 942 | if (!shadow_accessed_mask) |
6316e1c8 | 943 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 944 | |
e930bffe AA |
945 | spte = rmap_next(kvm, rmapp, NULL); |
946 | while (spte) { | |
947 | int _young; | |
948 | u64 _spte = *spte; | |
949 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
950 | _young = _spte & PT_ACCESSED_MASK; | |
951 | if (_young) { | |
952 | young = 1; | |
953 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
954 | } | |
955 | spte = rmap_next(kvm, rmapp, spte); | |
956 | } | |
957 | return young; | |
958 | } | |
959 | ||
8ee53820 AA |
960 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
961 | unsigned long data) | |
962 | { | |
963 | u64 *spte; | |
964 | int young = 0; | |
965 | ||
966 | /* | |
967 | * If there's no access bit in the secondary pte set by the | |
968 | * hardware it's up to gup-fast/gup to set the access bit in | |
969 | * the primary pte or in the page structure. | |
970 | */ | |
971 | if (!shadow_accessed_mask) | |
972 | goto out; | |
973 | ||
974 | spte = rmap_next(kvm, rmapp, NULL); | |
975 | while (spte) { | |
976 | u64 _spte = *spte; | |
977 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
978 | young = _spte & PT_ACCESSED_MASK; | |
979 | if (young) { | |
980 | young = 1; | |
981 | break; | |
982 | } | |
983 | spte = rmap_next(kvm, rmapp, spte); | |
984 | } | |
985 | out: | |
986 | return young; | |
987 | } | |
988 | ||
53a27b39 MT |
989 | #define RMAP_RECYCLE_THRESHOLD 1000 |
990 | ||
852e3c19 | 991 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
992 | { |
993 | unsigned long *rmapp; | |
852e3c19 JR |
994 | struct kvm_mmu_page *sp; |
995 | ||
996 | sp = page_header(__pa(spte)); | |
53a27b39 | 997 | |
852e3c19 | 998 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 999 | |
3da0dd43 | 1000 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1001 | kvm_flush_remote_tlbs(vcpu->kvm); |
1002 | } | |
1003 | ||
e930bffe AA |
1004 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1005 | { | |
3da0dd43 | 1006 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1007 | } |
1008 | ||
8ee53820 AA |
1009 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1010 | { | |
1011 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1012 | } | |
1013 | ||
d6c69ee9 | 1014 | #ifdef MMU_DEBUG |
47ad8e68 | 1015 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1016 | { |
139bdb2d AK |
1017 | u64 *pos; |
1018 | u64 *end; | |
1019 | ||
47ad8e68 | 1020 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1021 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1022 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1023 | pos, *pos); |
6aa8b732 | 1024 | return 0; |
139bdb2d | 1025 | } |
6aa8b732 AK |
1026 | return 1; |
1027 | } | |
d6c69ee9 | 1028 | #endif |
6aa8b732 | 1029 | |
45221ab6 DH |
1030 | /* |
1031 | * This value is the sum of all of the kvm instances's | |
1032 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1033 | * aggregate version in order to make the slab shrinker | |
1034 | * faster | |
1035 | */ | |
1036 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1037 | { | |
1038 | kvm->arch.n_used_mmu_pages += nr; | |
1039 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1040 | } | |
1041 | ||
aa6bd187 | 1042 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1043 | { |
4db35314 | 1044 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1045 | hlist_del(&sp->hash_link); |
4db35314 | 1046 | list_del(&sp->link); |
842f22ed | 1047 | free_page((unsigned long)sp->spt); |
2032a93d | 1048 | if (!sp->role.direct) |
842f22ed | 1049 | free_page((unsigned long)sp->gfns); |
e8ad9a70 | 1050 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1051 | } |
1052 | ||
cea0f0e7 AK |
1053 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1054 | { | |
1ae0a13d | 1055 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1056 | } |
1057 | ||
714b93da | 1058 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1059 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1060 | { |
cea0f0e7 AK |
1061 | if (!parent_pte) |
1062 | return; | |
cea0f0e7 | 1063 | |
67052b35 | 1064 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1065 | } |
1066 | ||
4db35314 | 1067 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1068 | u64 *parent_pte) |
1069 | { | |
67052b35 | 1070 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1071 | } |
1072 | ||
bcdd9a93 XG |
1073 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1074 | u64 *parent_pte) | |
1075 | { | |
1076 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1077 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); | |
1078 | } | |
1079 | ||
67052b35 XG |
1080 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1081 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1082 | { |
67052b35 XG |
1083 | struct kvm_mmu_page *sp; |
1084 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, | |
1085 | sizeof *sp); | |
1086 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
1087 | if (!direct) | |
1088 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1089 | PAGE_SIZE); | |
1090 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); | |
1091 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
1092 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); | |
1093 | sp->parent_ptes = 0; | |
1094 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1095 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1096 | return sp; | |
ad8cfbe3 MT |
1097 | } |
1098 | ||
67052b35 | 1099 | static void mark_unsync(u64 *spte); |
1047df1f | 1100 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1101 | { |
67052b35 | 1102 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1103 | } |
1104 | ||
67052b35 | 1105 | static void mark_unsync(u64 *spte) |
0074ff63 | 1106 | { |
67052b35 | 1107 | struct kvm_mmu_page *sp; |
1047df1f | 1108 | unsigned int index; |
0074ff63 | 1109 | |
67052b35 | 1110 | sp = page_header(__pa(spte)); |
1047df1f XG |
1111 | index = spte - sp->spt; |
1112 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1113 | return; |
1047df1f | 1114 | if (sp->unsync_children++) |
0074ff63 | 1115 | return; |
1047df1f | 1116 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1117 | } |
1118 | ||
d761a501 AK |
1119 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1120 | struct kvm_mmu_page *sp) | |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1125 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1126 | } | |
1127 | ||
e8bc217a | 1128 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1129 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1130 | { |
1131 | return 1; | |
1132 | } | |
1133 | ||
a7052897 MT |
1134 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1135 | { | |
1136 | } | |
1137 | ||
0f53b5b1 XG |
1138 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1139 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1140 | const void *pte) |
0f53b5b1 XG |
1141 | { |
1142 | WARN_ON(1); | |
1143 | } | |
1144 | ||
60c8aec6 MT |
1145 | #define KVM_PAGE_ARRAY_NR 16 |
1146 | ||
1147 | struct kvm_mmu_pages { | |
1148 | struct mmu_page_and_offset { | |
1149 | struct kvm_mmu_page *sp; | |
1150 | unsigned int idx; | |
1151 | } page[KVM_PAGE_ARRAY_NR]; | |
1152 | unsigned int nr; | |
1153 | }; | |
1154 | ||
0074ff63 MT |
1155 | #define for_each_unsync_children(bitmap, idx) \ |
1156 | for (idx = find_first_bit(bitmap, 512); \ | |
1157 | idx < 512; \ | |
1158 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1159 | ||
cded19f3 HE |
1160 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1161 | int idx) | |
4731d4c7 | 1162 | { |
60c8aec6 | 1163 | int i; |
4731d4c7 | 1164 | |
60c8aec6 MT |
1165 | if (sp->unsync) |
1166 | for (i=0; i < pvec->nr; i++) | |
1167 | if (pvec->page[i].sp == sp) | |
1168 | return 0; | |
1169 | ||
1170 | pvec->page[pvec->nr].sp = sp; | |
1171 | pvec->page[pvec->nr].idx = idx; | |
1172 | pvec->nr++; | |
1173 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1174 | } | |
1175 | ||
1176 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1177 | struct kvm_mmu_pages *pvec) | |
1178 | { | |
1179 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1180 | |
0074ff63 | 1181 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1182 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1183 | u64 ent = sp->spt[i]; |
1184 | ||
7a8f1a74 XG |
1185 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1186 | goto clear_child_bitmap; | |
1187 | ||
1188 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1189 | ||
1190 | if (child->unsync_children) { | |
1191 | if (mmu_pages_add(pvec, child, i)) | |
1192 | return -ENOSPC; | |
1193 | ||
1194 | ret = __mmu_unsync_walk(child, pvec); | |
1195 | if (!ret) | |
1196 | goto clear_child_bitmap; | |
1197 | else if (ret > 0) | |
1198 | nr_unsync_leaf += ret; | |
1199 | else | |
1200 | return ret; | |
1201 | } else if (child->unsync) { | |
1202 | nr_unsync_leaf++; | |
1203 | if (mmu_pages_add(pvec, child, i)) | |
1204 | return -ENOSPC; | |
1205 | } else | |
1206 | goto clear_child_bitmap; | |
1207 | ||
1208 | continue; | |
1209 | ||
1210 | clear_child_bitmap: | |
1211 | __clear_bit(i, sp->unsync_child_bitmap); | |
1212 | sp->unsync_children--; | |
1213 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1214 | } |
1215 | ||
4731d4c7 | 1216 | |
60c8aec6 MT |
1217 | return nr_unsync_leaf; |
1218 | } | |
1219 | ||
1220 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1221 | struct kvm_mmu_pages *pvec) | |
1222 | { | |
1223 | if (!sp->unsync_children) | |
1224 | return 0; | |
1225 | ||
1226 | mmu_pages_add(pvec, sp, 0); | |
1227 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1228 | } |
1229 | ||
4731d4c7 MT |
1230 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1231 | { | |
1232 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1233 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1234 | sp->unsync = 0; |
1235 | --kvm->stat.mmu_unsync; | |
1236 | } | |
1237 | ||
7775834a XG |
1238 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1239 | struct list_head *invalid_list); | |
1240 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1241 | struct list_head *invalid_list); | |
4731d4c7 | 1242 | |
f41d335a XG |
1243 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1244 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1245 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1246 | if ((sp)->gfn != (gfn)) {} else | |
1247 | ||
f41d335a XG |
1248 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1249 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1250 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1251 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1252 | (sp)->role.invalid) {} else | |
1253 | ||
f918b443 | 1254 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1255 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1256 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1257 | { |
5b7e0102 | 1258 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1259 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1260 | return 1; |
1261 | } | |
1262 | ||
f918b443 | 1263 | if (clear_unsync) |
1d9dc7e0 | 1264 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1265 | |
a4a8e6f7 | 1266 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1267 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1268 | return 1; |
1269 | } | |
1270 | ||
1271 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1272 | return 0; |
1273 | } | |
1274 | ||
1d9dc7e0 XG |
1275 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1276 | struct kvm_mmu_page *sp) | |
1277 | { | |
d98ba053 | 1278 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1279 | int ret; |
1280 | ||
d98ba053 | 1281 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1282 | if (ret) |
d98ba053 XG |
1283 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1284 | ||
1d9dc7e0 XG |
1285 | return ret; |
1286 | } | |
1287 | ||
d98ba053 XG |
1288 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1289 | struct list_head *invalid_list) | |
1d9dc7e0 | 1290 | { |
d98ba053 | 1291 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1292 | } |
1293 | ||
9f1a122f XG |
1294 | /* @gfn should be write-protected at the call site */ |
1295 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1296 | { | |
9f1a122f | 1297 | struct kvm_mmu_page *s; |
f41d335a | 1298 | struct hlist_node *node; |
d98ba053 | 1299 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1300 | bool flush = false; |
1301 | ||
f41d335a | 1302 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1303 | if (!s->unsync) |
9f1a122f XG |
1304 | continue; |
1305 | ||
1306 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1307 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1308 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1309 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1310 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1311 | continue; |
1312 | } | |
9f1a122f XG |
1313 | flush = true; |
1314 | } | |
1315 | ||
d98ba053 | 1316 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1317 | if (flush) |
1318 | kvm_mmu_flush_tlb(vcpu); | |
1319 | } | |
1320 | ||
60c8aec6 MT |
1321 | struct mmu_page_path { |
1322 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1323 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1324 | }; |
1325 | ||
60c8aec6 MT |
1326 | #define for_each_sp(pvec, sp, parents, i) \ |
1327 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1328 | sp = pvec.page[i].sp; \ | |
1329 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1330 | i = mmu_pages_next(&pvec, &parents, i)) | |
1331 | ||
cded19f3 HE |
1332 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1333 | struct mmu_page_path *parents, | |
1334 | int i) | |
60c8aec6 MT |
1335 | { |
1336 | int n; | |
1337 | ||
1338 | for (n = i+1; n < pvec->nr; n++) { | |
1339 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1340 | ||
1341 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1342 | parents->idx[0] = pvec->page[n].idx; | |
1343 | return n; | |
1344 | } | |
1345 | ||
1346 | parents->parent[sp->role.level-2] = sp; | |
1347 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1348 | } | |
1349 | ||
1350 | return n; | |
1351 | } | |
1352 | ||
cded19f3 | 1353 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1354 | { |
60c8aec6 MT |
1355 | struct kvm_mmu_page *sp; |
1356 | unsigned int level = 0; | |
1357 | ||
1358 | do { | |
1359 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1360 | |
60c8aec6 MT |
1361 | sp = parents->parent[level]; |
1362 | if (!sp) | |
1363 | return; | |
1364 | ||
1365 | --sp->unsync_children; | |
1366 | WARN_ON((int)sp->unsync_children < 0); | |
1367 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1368 | level++; | |
1369 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1370 | } |
1371 | ||
60c8aec6 MT |
1372 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1373 | struct mmu_page_path *parents, | |
1374 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1375 | { |
60c8aec6 MT |
1376 | parents->parent[parent->role.level-1] = NULL; |
1377 | pvec->nr = 0; | |
1378 | } | |
4731d4c7 | 1379 | |
60c8aec6 MT |
1380 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1381 | struct kvm_mmu_page *parent) | |
1382 | { | |
1383 | int i; | |
1384 | struct kvm_mmu_page *sp; | |
1385 | struct mmu_page_path parents; | |
1386 | struct kvm_mmu_pages pages; | |
d98ba053 | 1387 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1388 | |
1389 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1390 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1391 | int protected = 0; |
1392 | ||
1393 | for_each_sp(pages, sp, parents, i) | |
1394 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1395 | ||
1396 | if (protected) | |
1397 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1398 | ||
60c8aec6 | 1399 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1400 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1401 | mmu_pages_clear_parents(&parents); |
1402 | } | |
d98ba053 | 1403 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1404 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1405 | kvm_mmu_pages_init(parent, &parents, &pages); |
1406 | } | |
4731d4c7 MT |
1407 | } |
1408 | ||
cea0f0e7 AK |
1409 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1410 | gfn_t gfn, | |
1411 | gva_t gaddr, | |
1412 | unsigned level, | |
f6e2c02b | 1413 | int direct, |
41074d07 | 1414 | unsigned access, |
f7d9c7b7 | 1415 | u64 *parent_pte) |
cea0f0e7 AK |
1416 | { |
1417 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1418 | unsigned quadrant; |
9f1a122f | 1419 | struct kvm_mmu_page *sp; |
f41d335a | 1420 | struct hlist_node *node; |
9f1a122f | 1421 | bool need_sync = false; |
cea0f0e7 | 1422 | |
a770f6f2 | 1423 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1424 | role.level = level; |
f6e2c02b | 1425 | role.direct = direct; |
84b0c8c6 | 1426 | if (role.direct) |
5b7e0102 | 1427 | role.cr4_pae = 0; |
41074d07 | 1428 | role.access = access; |
c5a78f2b JR |
1429 | if (!vcpu->arch.mmu.direct_map |
1430 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1431 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1432 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1433 | role.quadrant = quadrant; | |
1434 | } | |
f41d335a | 1435 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1436 | if (!need_sync && sp->unsync) |
1437 | need_sync = true; | |
4731d4c7 | 1438 | |
7ae680eb XG |
1439 | if (sp->role.word != role.word) |
1440 | continue; | |
4731d4c7 | 1441 | |
7ae680eb XG |
1442 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1443 | break; | |
e02aa901 | 1444 | |
7ae680eb XG |
1445 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1446 | if (sp->unsync_children) { | |
a8eeb04a | 1447 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1448 | kvm_mmu_mark_parents_unsync(sp); |
1449 | } else if (sp->unsync) | |
1450 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1451 | |
7ae680eb XG |
1452 | trace_kvm_mmu_get_page(sp, false); |
1453 | return sp; | |
1454 | } | |
dfc5aa00 | 1455 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1456 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1457 | if (!sp) |
1458 | return sp; | |
4db35314 AK |
1459 | sp->gfn = gfn; |
1460 | sp->role = role; | |
7ae680eb XG |
1461 | hlist_add_head(&sp->hash_link, |
1462 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1463 | if (!direct) { |
b1a36821 MT |
1464 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1465 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1466 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1467 | kvm_sync_pages(vcpu, gfn); | |
1468 | ||
4731d4c7 MT |
1469 | account_shadowed(vcpu->kvm, gfn); |
1470 | } | |
131d8279 AK |
1471 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1472 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1473 | else | |
1474 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1475 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1476 | return sp; |
cea0f0e7 AK |
1477 | } |
1478 | ||
2d11123a AK |
1479 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1480 | struct kvm_vcpu *vcpu, u64 addr) | |
1481 | { | |
1482 | iterator->addr = addr; | |
1483 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1484 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1485 | |
1486 | if (iterator->level == PT64_ROOT_LEVEL && | |
1487 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1488 | !vcpu->arch.mmu.direct_map) | |
1489 | --iterator->level; | |
1490 | ||
2d11123a AK |
1491 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1492 | iterator->shadow_addr | |
1493 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1494 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1495 | --iterator->level; | |
1496 | if (!iterator->shadow_addr) | |
1497 | iterator->level = 0; | |
1498 | } | |
1499 | } | |
1500 | ||
1501 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1502 | { | |
1503 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1504 | return false; | |
4d88954d | 1505 | |
2d11123a AK |
1506 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1507 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1508 | return true; | |
1509 | } | |
1510 | ||
1511 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1512 | { | |
052331be XG |
1513 | if (is_last_spte(*iterator->sptep, iterator->level)) { |
1514 | iterator->level = 0; | |
1515 | return; | |
1516 | } | |
1517 | ||
2d11123a AK |
1518 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; |
1519 | --iterator->level; | |
1520 | } | |
1521 | ||
32ef26a3 AK |
1522 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1523 | { | |
1524 | u64 spte; | |
1525 | ||
1526 | spte = __pa(sp->spt) | |
1527 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1528 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1529 | __set_spte(sptep, spte); |
32ef26a3 AK |
1530 | } |
1531 | ||
a3aa51cf AK |
1532 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1533 | { | |
1534 | if (is_large_pte(*sptep)) { | |
1535 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1536 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1537 | } | |
1538 | } | |
1539 | ||
a357bd22 AK |
1540 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1541 | unsigned direct_access) | |
1542 | { | |
1543 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1544 | struct kvm_mmu_page *child; | |
1545 | ||
1546 | /* | |
1547 | * For the direct sp, if the guest pte's dirty bit | |
1548 | * changed form clean to dirty, it will corrupt the | |
1549 | * sp's access: allow writable in the read-only sp, | |
1550 | * so we should update the spte at this point to get | |
1551 | * a new sp with the correct access. | |
1552 | */ | |
1553 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1554 | if (child->role.access == direct_access) | |
1555 | return; | |
1556 | ||
bcdd9a93 | 1557 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1558 | kvm_flush_remote_tlbs(vcpu->kvm); |
1559 | } | |
1560 | } | |
1561 | ||
38e3b2b2 XG |
1562 | static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
1563 | u64 *spte) | |
1564 | { | |
1565 | u64 pte; | |
1566 | struct kvm_mmu_page *child; | |
1567 | ||
1568 | pte = *spte; | |
1569 | if (is_shadow_present_pte(pte)) { | |
1570 | if (is_last_spte(pte, sp->role.level)) | |
1571 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); | |
1572 | else { | |
1573 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 1574 | drop_parent_pte(child, spte); |
38e3b2b2 XG |
1575 | } |
1576 | } | |
1577 | __set_spte(spte, shadow_trap_nonpresent_pte); | |
1578 | if (is_large_pte(pte)) | |
1579 | --kvm->stat.lpages; | |
1580 | } | |
1581 | ||
90cb0529 | 1582 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1583 | struct kvm_mmu_page *sp) |
a436036b | 1584 | { |
697fe2e2 | 1585 | unsigned i; |
697fe2e2 | 1586 | |
38e3b2b2 XG |
1587 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1588 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
1589 | } |
1590 | ||
4db35314 | 1591 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1592 | { |
4db35314 | 1593 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1594 | } |
1595 | ||
12b7d28f AK |
1596 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1597 | { | |
1598 | int i; | |
988a2cae | 1599 | struct kvm_vcpu *vcpu; |
12b7d28f | 1600 | |
988a2cae GN |
1601 | kvm_for_each_vcpu(i, vcpu, kvm) |
1602 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1603 | } |
1604 | ||
31aa2b44 | 1605 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1606 | { |
1607 | u64 *parent_pte; | |
1608 | ||
bcdd9a93 XG |
1609 | while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL))) |
1610 | drop_parent_pte(sp, parent_pte); | |
31aa2b44 AK |
1611 | } |
1612 | ||
60c8aec6 | 1613 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1614 | struct kvm_mmu_page *parent, |
1615 | struct list_head *invalid_list) | |
4731d4c7 | 1616 | { |
60c8aec6 MT |
1617 | int i, zapped = 0; |
1618 | struct mmu_page_path parents; | |
1619 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1620 | |
60c8aec6 | 1621 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1622 | return 0; |
60c8aec6 MT |
1623 | |
1624 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1625 | while (mmu_unsync_walk(parent, &pages)) { | |
1626 | struct kvm_mmu_page *sp; | |
1627 | ||
1628 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1629 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1630 | mmu_pages_clear_parents(&parents); |
77662e00 | 1631 | zapped++; |
60c8aec6 | 1632 | } |
60c8aec6 MT |
1633 | kvm_mmu_pages_init(parent, &parents, &pages); |
1634 | } | |
1635 | ||
1636 | return zapped; | |
4731d4c7 MT |
1637 | } |
1638 | ||
7775834a XG |
1639 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1640 | struct list_head *invalid_list) | |
31aa2b44 | 1641 | { |
4731d4c7 | 1642 | int ret; |
f691fe1d | 1643 | |
7775834a | 1644 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1645 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1646 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1647 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1648 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1649 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1650 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1651 | if (sp->unsync) |
1652 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1653 | if (!sp->root_count) { |
54a4f023 GJ |
1654 | /* Count self */ |
1655 | ret++; | |
7775834a | 1656 | list_move(&sp->link, invalid_list); |
aa6bd187 | 1657 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 1658 | } else { |
5b5c6a5a | 1659 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1660 | kvm_reload_remote_mmus(kvm); |
1661 | } | |
7775834a XG |
1662 | |
1663 | sp->role.invalid = 1; | |
12b7d28f | 1664 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1665 | return ret; |
a436036b AK |
1666 | } |
1667 | ||
7775834a XG |
1668 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1669 | struct list_head *invalid_list) | |
1670 | { | |
1671 | struct kvm_mmu_page *sp; | |
1672 | ||
1673 | if (list_empty(invalid_list)) | |
1674 | return; | |
1675 | ||
1676 | kvm_flush_remote_tlbs(kvm); | |
1677 | ||
1678 | do { | |
1679 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1680 | WARN_ON(!sp->role.invalid || sp->root_count); | |
aa6bd187 | 1681 | kvm_mmu_free_page(sp); |
7775834a XG |
1682 | } while (!list_empty(invalid_list)); |
1683 | ||
1684 | } | |
1685 | ||
82ce2c96 IE |
1686 | /* |
1687 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1688 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1689 | */ |
49d5ca26 | 1690 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1691 | { |
d98ba053 | 1692 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1693 | /* |
1694 | * If we set the number of mmu pages to be smaller be than the | |
1695 | * number of actived pages , we must to free some mmu pages before we | |
1696 | * change the value | |
1697 | */ | |
1698 | ||
49d5ca26 DH |
1699 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1700 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1701 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1702 | struct kvm_mmu_page *page; |
1703 | ||
f05e70ac | 1704 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1705 | struct kvm_mmu_page, link); |
80b63faf | 1706 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 1707 | } |
aa6bd187 | 1708 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 1709 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1710 | } |
82ce2c96 | 1711 | |
49d5ca26 | 1712 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1713 | } |
1714 | ||
f67a46f4 | 1715 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1716 | { |
4db35314 | 1717 | struct kvm_mmu_page *sp; |
f41d335a | 1718 | struct hlist_node *node; |
d98ba053 | 1719 | LIST_HEAD(invalid_list); |
a436036b AK |
1720 | int r; |
1721 | ||
9ad17b10 | 1722 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1723 | r = 0; |
f41d335a XG |
1724 | |
1725 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1726 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1727 | sp->role.word); |
1728 | r = 1; | |
f41d335a | 1729 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1730 | } |
d98ba053 | 1731 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1732 | return r; |
cea0f0e7 AK |
1733 | } |
1734 | ||
f67a46f4 | 1735 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1736 | { |
4db35314 | 1737 | struct kvm_mmu_page *sp; |
f41d335a | 1738 | struct hlist_node *node; |
d98ba053 | 1739 | LIST_HEAD(invalid_list); |
97a0a01e | 1740 | |
f41d335a | 1741 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1742 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1743 | __func__, gfn, sp->role.word); |
f41d335a | 1744 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1745 | } |
d98ba053 | 1746 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1747 | } |
1748 | ||
38c335f1 | 1749 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1750 | { |
bc6678a3 | 1751 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1752 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1753 | |
291f26bc | 1754 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1755 | } |
1756 | ||
6844dec6 MT |
1757 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1758 | { | |
1759 | int i; | |
1760 | u64 *pt = sp->spt; | |
1761 | ||
1762 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1763 | return; | |
1764 | ||
1765 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1766 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1767 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1768 | } |
1769 | } | |
1770 | ||
74be52e3 SY |
1771 | /* |
1772 | * The function is based on mtrr_type_lookup() in | |
1773 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1774 | */ | |
1775 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1776 | u64 start, u64 end) | |
1777 | { | |
1778 | int i; | |
1779 | u64 base, mask; | |
1780 | u8 prev_match, curr_match; | |
1781 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1782 | ||
1783 | if (!mtrr_state->enabled) | |
1784 | return 0xFF; | |
1785 | ||
1786 | /* Make end inclusive end, instead of exclusive */ | |
1787 | end--; | |
1788 | ||
1789 | /* Look in fixed ranges. Just return the type as per start */ | |
1790 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1791 | int idx; | |
1792 | ||
1793 | if (start < 0x80000) { | |
1794 | idx = 0; | |
1795 | idx += (start >> 16); | |
1796 | return mtrr_state->fixed_ranges[idx]; | |
1797 | } else if (start < 0xC0000) { | |
1798 | idx = 1 * 8; | |
1799 | idx += ((start - 0x80000) >> 14); | |
1800 | return mtrr_state->fixed_ranges[idx]; | |
1801 | } else if (start < 0x1000000) { | |
1802 | idx = 3 * 8; | |
1803 | idx += ((start - 0xC0000) >> 12); | |
1804 | return mtrr_state->fixed_ranges[idx]; | |
1805 | } | |
1806 | } | |
1807 | ||
1808 | /* | |
1809 | * Look in variable ranges | |
1810 | * Look of multiple ranges matching this address and pick type | |
1811 | * as per MTRR precedence | |
1812 | */ | |
1813 | if (!(mtrr_state->enabled & 2)) | |
1814 | return mtrr_state->def_type; | |
1815 | ||
1816 | prev_match = 0xFF; | |
1817 | for (i = 0; i < num_var_ranges; ++i) { | |
1818 | unsigned short start_state, end_state; | |
1819 | ||
1820 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1821 | continue; | |
1822 | ||
1823 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1824 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1825 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1826 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1827 | ||
1828 | start_state = ((start & mask) == (base & mask)); | |
1829 | end_state = ((end & mask) == (base & mask)); | |
1830 | if (start_state != end_state) | |
1831 | return 0xFE; | |
1832 | ||
1833 | if ((start & mask) != (base & mask)) | |
1834 | continue; | |
1835 | ||
1836 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1837 | if (prev_match == 0xFF) { | |
1838 | prev_match = curr_match; | |
1839 | continue; | |
1840 | } | |
1841 | ||
1842 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1843 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1844 | return MTRR_TYPE_UNCACHABLE; | |
1845 | ||
1846 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1847 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1848 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1849 | curr_match == MTRR_TYPE_WRBACK)) { | |
1850 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1851 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1852 | } | |
1853 | ||
1854 | if (prev_match != curr_match) | |
1855 | return MTRR_TYPE_UNCACHABLE; | |
1856 | } | |
1857 | ||
1858 | if (prev_match != 0xFF) | |
1859 | return prev_match; | |
1860 | ||
1861 | return mtrr_state->def_type; | |
1862 | } | |
1863 | ||
4b12f0de | 1864 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1865 | { |
1866 | u8 mtrr; | |
1867 | ||
1868 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1869 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1870 | if (mtrr == 0xfe || mtrr == 0xff) | |
1871 | mtrr = MTRR_TYPE_WRBACK; | |
1872 | return mtrr; | |
1873 | } | |
4b12f0de | 1874 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1875 | |
9cf5cf5a XG |
1876 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1877 | { | |
1878 | trace_kvm_mmu_unsync_page(sp); | |
1879 | ++vcpu->kvm->stat.mmu_unsync; | |
1880 | sp->unsync = 1; | |
1881 | ||
1882 | kvm_mmu_mark_parents_unsync(sp); | |
1883 | mmu_convert_notrap(sp); | |
1884 | } | |
1885 | ||
1886 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1887 | { |
4731d4c7 | 1888 | struct kvm_mmu_page *s; |
f41d335a | 1889 | struct hlist_node *node; |
9cf5cf5a | 1890 | |
f41d335a | 1891 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1892 | if (s->unsync) |
4731d4c7 | 1893 | continue; |
9cf5cf5a XG |
1894 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1895 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1896 | } |
4731d4c7 MT |
1897 | } |
1898 | ||
1899 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1900 | bool can_unsync) | |
1901 | { | |
9cf5cf5a | 1902 | struct kvm_mmu_page *s; |
f41d335a | 1903 | struct hlist_node *node; |
9cf5cf5a XG |
1904 | bool need_unsync = false; |
1905 | ||
f41d335a | 1906 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1907 | if (!can_unsync) |
1908 | return 1; | |
1909 | ||
9cf5cf5a | 1910 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1911 | return 1; |
9cf5cf5a XG |
1912 | |
1913 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1914 | if (!oos_shadow) |
9cf5cf5a XG |
1915 | return 1; |
1916 | need_unsync = true; | |
1917 | } | |
4731d4c7 | 1918 | } |
9cf5cf5a XG |
1919 | if (need_unsync) |
1920 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1921 | return 0; |
1922 | } | |
1923 | ||
d555c333 | 1924 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1925 | unsigned pte_access, int user_fault, |
640d9b0d | 1926 | int write_fault, int level, |
c2d0ee46 | 1927 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 1928 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 1929 | { |
b330aa0c | 1930 | u64 spte, entry = *sptep; |
1e73f9dd | 1931 | int ret = 0; |
64d4d521 | 1932 | |
1c4f1fd6 AK |
1933 | /* |
1934 | * We don't set the accessed bit, since we sometimes want to see | |
1935 | * whether the guest actually used the pte (in order to detect | |
1936 | * demand paging). | |
1937 | */ | |
982c2565 | 1938 | spte = PT_PRESENT_MASK; |
947da538 | 1939 | if (!speculative) |
3201b5d9 | 1940 | spte |= shadow_accessed_mask; |
640d9b0d | 1941 | |
7b52345e SY |
1942 | if (pte_access & ACC_EXEC_MASK) |
1943 | spte |= shadow_x_mask; | |
1944 | else | |
1945 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1946 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1947 | spte |= shadow_user_mask; |
852e3c19 | 1948 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1949 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 1950 | if (tdp_enabled) |
4b12f0de SY |
1951 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
1952 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1953 | |
9bdbba13 | 1954 | if (host_writable) |
1403283a | 1955 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
1956 | else |
1957 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 1958 | |
35149e21 | 1959 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1960 | |
1961 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
1962 | || (!vcpu->arch.mmu.direct_map && write_fault |
1963 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1964 | |
852e3c19 JR |
1965 | if (level > PT_PAGE_TABLE_LEVEL && |
1966 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1967 | ret = 1; |
be38d276 AK |
1968 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
1969 | goto done; | |
38187c83 MT |
1970 | } |
1971 | ||
1c4f1fd6 | 1972 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1973 | |
c5a78f2b | 1974 | if (!vcpu->arch.mmu.direct_map |
411c588d | 1975 | && !(pte_access & ACC_WRITE_MASK)) { |
69325a12 | 1976 | spte &= ~PT_USER_MASK; |
411c588d AK |
1977 | /* |
1978 | * If we converted a user page to a kernel page, | |
1979 | * so that the kernel can write to it when cr0.wp=0, | |
1980 | * then we should prevent the kernel from executing it | |
1981 | * if SMEP is enabled. | |
1982 | */ | |
1983 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
1984 | spte |= PT64_NX_MASK; | |
1985 | } | |
69325a12 | 1986 | |
ecc5589f MT |
1987 | /* |
1988 | * Optimization: for pte sync, if spte was writable the hash | |
1989 | * lookup is unnecessary (and expensive). Write protection | |
1990 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1991 | * Same reasoning can be applied to dirty page accounting. | |
1992 | */ | |
8dae4445 | 1993 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
1994 | goto set_pte; |
1995 | ||
4731d4c7 | 1996 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 1997 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 1998 | __func__, gfn); |
1e73f9dd | 1999 | ret = 1; |
1c4f1fd6 | 2000 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2001 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2002 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2003 | } |
2004 | } | |
2005 | ||
1c4f1fd6 AK |
2006 | if (pte_access & ACC_WRITE_MASK) |
2007 | mark_page_dirty(vcpu->kvm, gfn); | |
2008 | ||
38187c83 | 2009 | set_pte: |
b79b93f9 | 2010 | update_spte(sptep, spte); |
b330aa0c XG |
2011 | /* |
2012 | * If we overwrite a writable spte with a read-only one we | |
2013 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2014 | * will find a read-only spte, even though the writable spte | |
2015 | * might be cached on a CPU's TLB. | |
2016 | */ | |
2017 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2018 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2019 | done: |
1e73f9dd MT |
2020 | return ret; |
2021 | } | |
2022 | ||
d555c333 | 2023 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2024 | unsigned pt_access, unsigned pte_access, |
640d9b0d | 2025 | int user_fault, int write_fault, |
b90a0e6c | 2026 | int *emulate, int level, gfn_t gfn, |
1403283a | 2027 | pfn_t pfn, bool speculative, |
9bdbba13 | 2028 | bool host_writable) |
1e73f9dd MT |
2029 | { |
2030 | int was_rmapped = 0; | |
53a27b39 | 2031 | int rmap_count; |
1e73f9dd MT |
2032 | |
2033 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2034 | " user_fault %d gfn %llx\n", |
d555c333 | 2035 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2036 | write_fault, user_fault, gfn); |
2037 | ||
d555c333 | 2038 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2039 | /* |
2040 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2041 | * the parent of the now unreachable PTE. | |
2042 | */ | |
852e3c19 JR |
2043 | if (level > PT_PAGE_TABLE_LEVEL && |
2044 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2045 | struct kvm_mmu_page *child; |
d555c333 | 2046 | u64 pte = *sptep; |
1e73f9dd MT |
2047 | |
2048 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2049 | drop_parent_pte(child, sptep); |
3be2264b | 2050 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2051 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2052 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2053 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2054 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2055 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2056 | } else |
2057 | was_rmapped = 1; | |
1e73f9dd | 2058 | } |
852e3c19 | 2059 | |
d555c333 | 2060 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
640d9b0d | 2061 | level, gfn, pfn, speculative, true, |
9bdbba13 | 2062 | host_writable)) { |
1e73f9dd | 2063 | if (write_fault) |
b90a0e6c | 2064 | *emulate = 1; |
5304efde | 2065 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2066 | } |
1e73f9dd | 2067 | |
d555c333 | 2068 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2069 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2070 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2071 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2072 | *sptep, sptep); | |
d555c333 | 2073 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2074 | ++vcpu->kvm->stat.lpages; |
2075 | ||
ffb61bb3 XG |
2076 | if (is_shadow_present_pte(*sptep)) { |
2077 | page_header_update_slot(vcpu->kvm, sptep, gfn); | |
2078 | if (!was_rmapped) { | |
2079 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2080 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2081 | rmap_recycle(vcpu, sptep, gfn); | |
2082 | } | |
1c4f1fd6 | 2083 | } |
9ed5520d | 2084 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2085 | if (speculative) { |
d555c333 | 2086 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2087 | vcpu->arch.last_pte_gfn = gfn; |
2088 | } | |
1c4f1fd6 AK |
2089 | } |
2090 | ||
6aa8b732 AK |
2091 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2092 | { | |
2093 | } | |
2094 | ||
957ed9ef XG |
2095 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2096 | bool no_dirty_log) | |
2097 | { | |
2098 | struct kvm_memory_slot *slot; | |
2099 | unsigned long hva; | |
2100 | ||
5d163b1c | 2101 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef XG |
2102 | if (!slot) { |
2103 | get_page(bad_page); | |
2104 | return page_to_pfn(bad_page); | |
2105 | } | |
2106 | ||
2107 | hva = gfn_to_hva_memslot(slot, gfn); | |
2108 | ||
2109 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2110 | } | |
2111 | ||
2112 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2113 | struct kvm_mmu_page *sp, | |
2114 | u64 *start, u64 *end) | |
2115 | { | |
2116 | struct page *pages[PTE_PREFETCH_NUM]; | |
2117 | unsigned access = sp->role.access; | |
2118 | int i, ret; | |
2119 | gfn_t gfn; | |
2120 | ||
2121 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2122 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2123 | return -1; |
2124 | ||
2125 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2126 | if (ret <= 0) | |
2127 | return -1; | |
2128 | ||
2129 | for (i = 0; i < ret; i++, gfn++, start++) | |
2130 | mmu_set_spte(vcpu, start, ACC_ALL, | |
640d9b0d | 2131 | access, 0, 0, NULL, |
957ed9ef XG |
2132 | sp->role.level, gfn, |
2133 | page_to_pfn(pages[i]), true, true); | |
2134 | ||
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2139 | struct kvm_mmu_page *sp, u64 *sptep) | |
2140 | { | |
2141 | u64 *spte, *start = NULL; | |
2142 | int i; | |
2143 | ||
2144 | WARN_ON(!sp->role.direct); | |
2145 | ||
2146 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2147 | spte = sp->spt + i; | |
2148 | ||
2149 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2150 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2151 | if (!start) | |
2152 | continue; | |
2153 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2154 | break; | |
2155 | start = NULL; | |
2156 | } else if (!start) | |
2157 | start = spte; | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2162 | { | |
2163 | struct kvm_mmu_page *sp; | |
2164 | ||
2165 | /* | |
2166 | * Since it's no accessed bit on EPT, it's no way to | |
2167 | * distinguish between actually accessed translations | |
2168 | * and prefetched, so disable pte prefetch if EPT is | |
2169 | * enabled. | |
2170 | */ | |
2171 | if (!shadow_accessed_mask) | |
2172 | return; | |
2173 | ||
2174 | sp = page_header(__pa(sptep)); | |
2175 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2176 | return; | |
2177 | ||
2178 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2179 | } | |
2180 | ||
9f652d21 | 2181 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2182 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2183 | bool prefault) | |
140754bc | 2184 | { |
9f652d21 | 2185 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2186 | struct kvm_mmu_page *sp; |
b90a0e6c | 2187 | int emulate = 0; |
140754bc | 2188 | gfn_t pseudo_gfn; |
6aa8b732 | 2189 | |
9f652d21 | 2190 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2191 | if (iterator.level == level) { |
612819c3 MT |
2192 | unsigned pte_access = ACC_ALL; |
2193 | ||
612819c3 | 2194 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
b90a0e6c | 2195 | 0, write, &emulate, |
2ec4739d | 2196 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2197 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2198 | ++vcpu->stat.pf_fixed; |
2199 | break; | |
6aa8b732 AK |
2200 | } |
2201 | ||
9f652d21 | 2202 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2203 | u64 base_addr = iterator.addr; |
2204 | ||
2205 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2206 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2207 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2208 | iterator.level - 1, | |
2209 | 1, ACC_ALL, iterator.sptep); | |
2210 | if (!sp) { | |
2211 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2212 | kvm_release_pfn_clean(pfn); | |
2213 | return -ENOMEM; | |
2214 | } | |
140754bc | 2215 | |
d555c333 AK |
2216 | __set_spte(iterator.sptep, |
2217 | __pa(sp->spt) | |
2218 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
33f91edb XG |
2219 | | shadow_user_mask | shadow_x_mask |
2220 | | shadow_accessed_mask); | |
9f652d21 AK |
2221 | } |
2222 | } | |
b90a0e6c | 2223 | return emulate; |
6aa8b732 AK |
2224 | } |
2225 | ||
77db5cbd | 2226 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2227 | { |
77db5cbd HY |
2228 | siginfo_t info; |
2229 | ||
2230 | info.si_signo = SIGBUS; | |
2231 | info.si_errno = 0; | |
2232 | info.si_code = BUS_MCEERR_AR; | |
2233 | info.si_addr = (void __user *)address; | |
2234 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2235 | |
77db5cbd | 2236 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2237 | } |
2238 | ||
bebb106a XG |
2239 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gva_t gva, |
2240 | unsigned access, gfn_t gfn, pfn_t pfn) | |
bf998156 HY |
2241 | { |
2242 | kvm_release_pfn_clean(pfn); | |
2243 | if (is_hwpoison_pfn(pfn)) { | |
bebb106a | 2244 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2245 | return 0; |
edba23e5 GN |
2246 | } else if (is_fault_pfn(pfn)) |
2247 | return -EFAULT; | |
2248 | ||
bebb106a | 2249 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
bf998156 HY |
2250 | return 1; |
2251 | } | |
2252 | ||
936a5fe6 AA |
2253 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2254 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2255 | { | |
2256 | pfn_t pfn = *pfnp; | |
2257 | gfn_t gfn = *gfnp; | |
2258 | int level = *levelp; | |
2259 | ||
2260 | /* | |
2261 | * Check if it's a transparent hugepage. If this would be an | |
2262 | * hugetlbfs page, level wouldn't be set to | |
2263 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2264 | * here. | |
2265 | */ | |
2266 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2267 | level == PT_PAGE_TABLE_LEVEL && | |
2268 | PageTransCompound(pfn_to_page(pfn)) && | |
2269 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2270 | unsigned long mask; | |
2271 | /* | |
2272 | * mmu_notifier_retry was successful and we hold the | |
2273 | * mmu_lock here, so the pmd can't become splitting | |
2274 | * from under us, and in turn | |
2275 | * __split_huge_page_refcount() can't run from under | |
2276 | * us and we can safely transfer the refcount from | |
2277 | * PG_tail to PG_head as we switch the pfn to tail to | |
2278 | * head. | |
2279 | */ | |
2280 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2281 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2282 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2283 | if (pfn & mask) { | |
2284 | gfn &= ~mask; | |
2285 | *gfnp = gfn; | |
2286 | kvm_release_pfn_clean(pfn); | |
2287 | pfn &= ~mask; | |
2288 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2289 | BUG(); | |
2290 | *pfnp = pfn; | |
2291 | } | |
2292 | } | |
2293 | } | |
2294 | ||
78b2c54a | 2295 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2296 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2297 | ||
2298 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2299 | bool prefault) |
10589a46 MT |
2300 | { |
2301 | int r; | |
852e3c19 | 2302 | int level; |
936a5fe6 | 2303 | int force_pt_level; |
35149e21 | 2304 | pfn_t pfn; |
e930bffe | 2305 | unsigned long mmu_seq; |
612819c3 | 2306 | bool map_writable; |
aaee2c94 | 2307 | |
936a5fe6 AA |
2308 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2309 | if (likely(!force_pt_level)) { | |
2310 | level = mapping_level(vcpu, gfn); | |
2311 | /* | |
2312 | * This path builds a PAE pagetable - so we can map | |
2313 | * 2mb pages at maximum. Therefore check if the level | |
2314 | * is larger than that. | |
2315 | */ | |
2316 | if (level > PT_DIRECTORY_LEVEL) | |
2317 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2318 | |
936a5fe6 AA |
2319 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2320 | } else | |
2321 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2322 | |
e930bffe | 2323 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2324 | smp_rmb(); |
060c2abe | 2325 | |
78b2c54a | 2326 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2327 | return 0; |
aaee2c94 | 2328 | |
d196e343 | 2329 | /* mmio */ |
bf998156 | 2330 | if (is_error_pfn(pfn)) |
bebb106a | 2331 | return kvm_handle_bad_page(vcpu, v, ACC_ALL, gfn, pfn); |
d196e343 | 2332 | |
aaee2c94 | 2333 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2334 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2335 | goto out_unlock; | |
eb787d10 | 2336 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2337 | if (likely(!force_pt_level)) |
2338 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2339 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2340 | prefault); | |
aaee2c94 MT |
2341 | spin_unlock(&vcpu->kvm->mmu_lock); |
2342 | ||
aaee2c94 | 2343 | |
10589a46 | 2344 | return r; |
e930bffe AA |
2345 | |
2346 | out_unlock: | |
2347 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2348 | kvm_release_pfn_clean(pfn); | |
2349 | return 0; | |
10589a46 MT |
2350 | } |
2351 | ||
2352 | ||
17ac10ad AK |
2353 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2354 | { | |
2355 | int i; | |
4db35314 | 2356 | struct kvm_mmu_page *sp; |
d98ba053 | 2357 | LIST_HEAD(invalid_list); |
17ac10ad | 2358 | |
ad312c7c | 2359 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2360 | return; |
aaee2c94 | 2361 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2362 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2363 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2364 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2365 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2366 | |
4db35314 AK |
2367 | sp = page_header(root); |
2368 | --sp->root_count; | |
d98ba053 XG |
2369 | if (!sp->root_count && sp->role.invalid) { |
2370 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2371 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2372 | } | |
ad312c7c | 2373 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2374 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2375 | return; |
2376 | } | |
17ac10ad | 2377 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2378 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2379 | |
417726a3 | 2380 | if (root) { |
417726a3 | 2381 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2382 | sp = page_header(root); |
2383 | --sp->root_count; | |
2e53d63a | 2384 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2385 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2386 | &invalid_list); | |
417726a3 | 2387 | } |
ad312c7c | 2388 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2389 | } |
d98ba053 | 2390 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2391 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2392 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2393 | } |
2394 | ||
8986ecc0 MT |
2395 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2396 | { | |
2397 | int ret = 0; | |
2398 | ||
2399 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2400 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2401 | ret = 1; |
2402 | } | |
2403 | ||
2404 | return ret; | |
2405 | } | |
2406 | ||
651dd37a JR |
2407 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2408 | { | |
2409 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2410 | unsigned i; |
651dd37a JR |
2411 | |
2412 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2413 | spin_lock(&vcpu->kvm->mmu_lock); | |
2414 | kvm_mmu_free_some_pages(vcpu); | |
2415 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2416 | 1, ACC_ALL, NULL); | |
2417 | ++sp->root_count; | |
2418 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2419 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2420 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2421 | for (i = 0; i < 4; ++i) { | |
2422 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2423 | ||
2424 | ASSERT(!VALID_PAGE(root)); | |
2425 | spin_lock(&vcpu->kvm->mmu_lock); | |
2426 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2427 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2428 | i << 30, | |
651dd37a JR |
2429 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2430 | NULL); | |
2431 | root = __pa(sp->spt); | |
2432 | ++sp->root_count; | |
2433 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2434 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2435 | } |
6292757f | 2436 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2437 | } else |
2438 | BUG(); | |
2439 | ||
2440 | return 0; | |
2441 | } | |
2442 | ||
2443 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2444 | { |
4db35314 | 2445 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2446 | u64 pdptr, pm_mask; |
2447 | gfn_t root_gfn; | |
2448 | int i; | |
3bb65a22 | 2449 | |
5777ed34 | 2450 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2451 | |
651dd37a JR |
2452 | if (mmu_check_root(vcpu, root_gfn)) |
2453 | return 1; | |
2454 | ||
2455 | /* | |
2456 | * Do we shadow a long mode page table? If so we need to | |
2457 | * write-protect the guests page table root. | |
2458 | */ | |
2459 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2460 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2461 | |
2462 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2463 | |
8facbbff | 2464 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2465 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2466 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2467 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2468 | root = __pa(sp->spt); |
2469 | ++sp->root_count; | |
8facbbff | 2470 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2471 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2472 | return 0; |
17ac10ad | 2473 | } |
f87f9288 | 2474 | |
651dd37a JR |
2475 | /* |
2476 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2477 | * or a PAE 3-level page table. In either case we need to be aware that |
2478 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2479 | */ |
81407ca5 JR |
2480 | pm_mask = PT_PRESENT_MASK; |
2481 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2482 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2483 | ||
17ac10ad | 2484 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2485 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2486 | |
2487 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2488 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2489 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2490 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2491 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2492 | continue; |
2493 | } | |
6de4f3ad | 2494 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2495 | if (mmu_check_root(vcpu, root_gfn)) |
2496 | return 1; | |
5a7388c2 | 2497 | } |
8facbbff | 2498 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2499 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2500 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2501 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2502 | ACC_ALL, NULL); |
4db35314 AK |
2503 | root = __pa(sp->spt); |
2504 | ++sp->root_count; | |
8facbbff AK |
2505 | spin_unlock(&vcpu->kvm->mmu_lock); |
2506 | ||
81407ca5 | 2507 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2508 | } |
6292757f | 2509 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2510 | |
2511 | /* | |
2512 | * If we shadow a 32 bit page table with a long mode page | |
2513 | * table we enter this path. | |
2514 | */ | |
2515 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2516 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2517 | /* | |
2518 | * The additional page necessary for this is only | |
2519 | * allocated on demand. | |
2520 | */ | |
2521 | ||
2522 | u64 *lm_root; | |
2523 | ||
2524 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2525 | if (lm_root == NULL) | |
2526 | return 1; | |
2527 | ||
2528 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2529 | ||
2530 | vcpu->arch.mmu.lm_root = lm_root; | |
2531 | } | |
2532 | ||
2533 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2534 | } | |
2535 | ||
8986ecc0 | 2536 | return 0; |
17ac10ad AK |
2537 | } |
2538 | ||
651dd37a JR |
2539 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2540 | { | |
2541 | if (vcpu->arch.mmu.direct_map) | |
2542 | return mmu_alloc_direct_roots(vcpu); | |
2543 | else | |
2544 | return mmu_alloc_shadow_roots(vcpu); | |
2545 | } | |
2546 | ||
0ba73cda MT |
2547 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2548 | { | |
2549 | int i; | |
2550 | struct kvm_mmu_page *sp; | |
2551 | ||
81407ca5 JR |
2552 | if (vcpu->arch.mmu.direct_map) |
2553 | return; | |
2554 | ||
0ba73cda MT |
2555 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2556 | return; | |
6903074c | 2557 | |
bebb106a | 2558 | vcpu_clear_mmio_info(vcpu, ~0ul); |
6903074c | 2559 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 2560 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2561 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2562 | sp = page_header(root); | |
2563 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2564 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2565 | return; |
2566 | } | |
2567 | for (i = 0; i < 4; ++i) { | |
2568 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2569 | ||
8986ecc0 | 2570 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2571 | root &= PT64_BASE_ADDR_MASK; |
2572 | sp = page_header(root); | |
2573 | mmu_sync_children(vcpu, sp); | |
2574 | } | |
2575 | } | |
6903074c | 2576 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2577 | } |
2578 | ||
2579 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2580 | { | |
2581 | spin_lock(&vcpu->kvm->mmu_lock); | |
2582 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2583 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2584 | } |
2585 | ||
1871c602 | 2586 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2587 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2588 | { |
ab9ae313 AK |
2589 | if (exception) |
2590 | exception->error_code = 0; | |
6aa8b732 AK |
2591 | return vaddr; |
2592 | } | |
2593 | ||
6539e738 | 2594 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2595 | u32 access, |
2596 | struct x86_exception *exception) | |
6539e738 | 2597 | { |
ab9ae313 AK |
2598 | if (exception) |
2599 | exception->error_code = 0; | |
6539e738 JR |
2600 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2601 | } | |
2602 | ||
6aa8b732 | 2603 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2604 | u32 error_code, bool prefault) |
6aa8b732 | 2605 | { |
e833240f | 2606 | gfn_t gfn; |
e2dec939 | 2607 | int r; |
6aa8b732 | 2608 | |
b8688d51 | 2609 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2610 | r = mmu_topup_memory_caches(vcpu); |
2611 | if (r) | |
2612 | return r; | |
714b93da | 2613 | |
6aa8b732 | 2614 | ASSERT(vcpu); |
ad312c7c | 2615 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2616 | |
e833240f | 2617 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2618 | |
e833240f | 2619 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2620 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2621 | } |
2622 | ||
7e1fbeac | 2623 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2624 | { |
2625 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2626 | |
7c90705b | 2627 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2628 | arch.gfn = gfn; |
c4806acd | 2629 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2630 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2631 | |
2632 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2633 | } | |
2634 | ||
2635 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2636 | { | |
2637 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2638 | kvm_event_needs_reinjection(vcpu))) | |
2639 | return false; | |
2640 | ||
2641 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2642 | } | |
2643 | ||
78b2c54a | 2644 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2645 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2646 | { |
2647 | bool async; | |
2648 | ||
612819c3 | 2649 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2650 | |
2651 | if (!async) | |
2652 | return false; /* *pfn has correct page already */ | |
2653 | ||
2654 | put_page(pfn_to_page(*pfn)); | |
2655 | ||
78b2c54a | 2656 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2657 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2658 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2659 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2660 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2661 | return true; | |
2662 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2663 | return true; | |
2664 | } | |
2665 | ||
612819c3 | 2666 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2667 | |
2668 | return false; | |
2669 | } | |
2670 | ||
56028d08 | 2671 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2672 | bool prefault) |
fb72d167 | 2673 | { |
35149e21 | 2674 | pfn_t pfn; |
fb72d167 | 2675 | int r; |
852e3c19 | 2676 | int level; |
936a5fe6 | 2677 | int force_pt_level; |
05da4558 | 2678 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2679 | unsigned long mmu_seq; |
612819c3 MT |
2680 | int write = error_code & PFERR_WRITE_MASK; |
2681 | bool map_writable; | |
fb72d167 JR |
2682 | |
2683 | ASSERT(vcpu); | |
2684 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2685 | ||
2686 | r = mmu_topup_memory_caches(vcpu); | |
2687 | if (r) | |
2688 | return r; | |
2689 | ||
936a5fe6 AA |
2690 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2691 | if (likely(!force_pt_level)) { | |
2692 | level = mapping_level(vcpu, gfn); | |
2693 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2694 | } else | |
2695 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 2696 | |
e930bffe | 2697 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2698 | smp_rmb(); |
af585b92 | 2699 | |
78b2c54a | 2700 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2701 | return 0; |
2702 | ||
2703 | /* mmio */ | |
bf998156 | 2704 | if (is_error_pfn(pfn)) |
bebb106a | 2705 | return kvm_handle_bad_page(vcpu, 0, 0, gfn, pfn); |
fb72d167 | 2706 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2707 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2708 | goto out_unlock; | |
fb72d167 | 2709 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2710 | if (likely(!force_pt_level)) |
2711 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 2712 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2713 | level, gfn, pfn, prefault); |
fb72d167 | 2714 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2715 | |
2716 | return r; | |
e930bffe AA |
2717 | |
2718 | out_unlock: | |
2719 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2720 | kvm_release_pfn_clean(pfn); | |
2721 | return 0; | |
fb72d167 JR |
2722 | } |
2723 | ||
6aa8b732 AK |
2724 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2725 | { | |
17ac10ad | 2726 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2727 | } |
2728 | ||
52fde8df JR |
2729 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2730 | struct kvm_mmu *context) | |
6aa8b732 | 2731 | { |
6aa8b732 AK |
2732 | context->new_cr3 = nonpaging_new_cr3; |
2733 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2734 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2735 | context->free = nonpaging_free; | |
c7addb90 | 2736 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2737 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2738 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2739 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 2740 | context->root_level = 0; |
6aa8b732 | 2741 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2742 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2743 | context->direct_map = true; |
2d48a985 | 2744 | context->nx = false; |
6aa8b732 AK |
2745 | return 0; |
2746 | } | |
2747 | ||
d835dfec | 2748 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2749 | { |
1165f5fe | 2750 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2751 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2752 | } |
2753 | ||
2754 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2755 | { | |
9f8fe504 | 2756 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 2757 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2758 | } |
2759 | ||
5777ed34 JR |
2760 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2761 | { | |
9f8fe504 | 2762 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
2763 | } |
2764 | ||
6389ee94 AK |
2765 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2766 | struct x86_exception *fault) | |
6aa8b732 | 2767 | { |
6389ee94 | 2768 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2769 | } |
2770 | ||
6aa8b732 AK |
2771 | static void paging_free(struct kvm_vcpu *vcpu) |
2772 | { | |
2773 | nonpaging_free(vcpu); | |
2774 | } | |
2775 | ||
3241f22d | 2776 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2777 | { |
2778 | int bit7; | |
2779 | ||
2780 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2781 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2782 | } |
2783 | ||
6aa8b732 AK |
2784 | #define PTTYPE 64 |
2785 | #include "paging_tmpl.h" | |
2786 | #undef PTTYPE | |
2787 | ||
2788 | #define PTTYPE 32 | |
2789 | #include "paging_tmpl.h" | |
2790 | #undef PTTYPE | |
2791 | ||
52fde8df JR |
2792 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2793 | struct kvm_mmu *context, | |
2794 | int level) | |
82725b20 | 2795 | { |
82725b20 DE |
2796 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2797 | u64 exb_bit_rsvd = 0; | |
2798 | ||
2d48a985 | 2799 | if (!context->nx) |
82725b20 DE |
2800 | exb_bit_rsvd = rsvd_bits(63, 63); |
2801 | switch (level) { | |
2802 | case PT32_ROOT_LEVEL: | |
2803 | /* no rsvd bits for 2 level 4K page table entries */ | |
2804 | context->rsvd_bits_mask[0][1] = 0; | |
2805 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2806 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2807 | ||
2808 | if (!is_pse(vcpu)) { | |
2809 | context->rsvd_bits_mask[1][1] = 0; | |
2810 | break; | |
2811 | } | |
2812 | ||
82725b20 DE |
2813 | if (is_cpuid_PSE36()) |
2814 | /* 36bits PSE 4MB page */ | |
2815 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2816 | else | |
2817 | /* 32 bits PSE 4MB page */ | |
2818 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2819 | break; |
2820 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2821 | context->rsvd_bits_mask[0][2] = |
2822 | rsvd_bits(maxphyaddr, 63) | | |
2823 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2824 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2825 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2826 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2827 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2828 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2829 | rsvd_bits(maxphyaddr, 62) | | |
2830 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2831 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2832 | break; |
2833 | case PT64_ROOT_LEVEL: | |
2834 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2835 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2836 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2837 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2838 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2839 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2840 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2841 | rsvd_bits(maxphyaddr, 51); | |
2842 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2843 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2844 | rsvd_bits(maxphyaddr, 51) | | |
2845 | rsvd_bits(13, 29); | |
82725b20 | 2846 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2847 | rsvd_bits(maxphyaddr, 51) | |
2848 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2849 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2850 | break; |
2851 | } | |
2852 | } | |
2853 | ||
52fde8df JR |
2854 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2855 | struct kvm_mmu *context, | |
2856 | int level) | |
6aa8b732 | 2857 | { |
2d48a985 JR |
2858 | context->nx = is_nx(vcpu); |
2859 | ||
52fde8df | 2860 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2861 | |
2862 | ASSERT(is_pae(vcpu)); | |
2863 | context->new_cr3 = paging_new_cr3; | |
2864 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2865 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2866 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2867 | context->sync_page = paging64_sync_page; |
a7052897 | 2868 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 2869 | context->update_pte = paging64_update_pte; |
6aa8b732 | 2870 | context->free = paging_free; |
17ac10ad AK |
2871 | context->root_level = level; |
2872 | context->shadow_root_level = level; | |
17c3ba9d | 2873 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2874 | context->direct_map = false; |
6aa8b732 AK |
2875 | return 0; |
2876 | } | |
2877 | ||
52fde8df JR |
2878 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2879 | struct kvm_mmu *context) | |
17ac10ad | 2880 | { |
52fde8df | 2881 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2882 | } |
2883 | ||
52fde8df JR |
2884 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2885 | struct kvm_mmu *context) | |
6aa8b732 | 2886 | { |
2d48a985 JR |
2887 | context->nx = false; |
2888 | ||
52fde8df | 2889 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2890 | |
2891 | context->new_cr3 = paging_new_cr3; | |
2892 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2893 | context->gva_to_gpa = paging32_gva_to_gpa; |
2894 | context->free = paging_free; | |
c7addb90 | 2895 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2896 | context->sync_page = paging32_sync_page; |
a7052897 | 2897 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 2898 | context->update_pte = paging32_update_pte; |
6aa8b732 AK |
2899 | context->root_level = PT32_ROOT_LEVEL; |
2900 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2901 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2902 | context->direct_map = false; |
6aa8b732 AK |
2903 | return 0; |
2904 | } | |
2905 | ||
52fde8df JR |
2906 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2907 | struct kvm_mmu *context) | |
6aa8b732 | 2908 | { |
52fde8df | 2909 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2910 | } |
2911 | ||
fb72d167 JR |
2912 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2913 | { | |
14dfe855 | 2914 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 2915 | |
c445f8ef | 2916 | context->base_role.word = 0; |
fb72d167 JR |
2917 | context->new_cr3 = nonpaging_new_cr3; |
2918 | context->page_fault = tdp_page_fault; | |
2919 | context->free = nonpaging_free; | |
2920 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2921 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2922 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 2923 | context->update_pte = nonpaging_update_pte; |
67253af5 | 2924 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2925 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2926 | context->direct_map = true; |
1c97f0a0 | 2927 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2928 | context->get_cr3 = get_cr3; |
cb659db8 | 2929 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 2930 | context->nx = is_nx(vcpu); |
fb72d167 JR |
2931 | |
2932 | if (!is_paging(vcpu)) { | |
2d48a985 | 2933 | context->nx = false; |
fb72d167 JR |
2934 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2935 | context->root_level = 0; | |
2936 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2937 | context->nx = is_nx(vcpu); |
52fde8df | 2938 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
2939 | context->gva_to_gpa = paging64_gva_to_gpa; |
2940 | context->root_level = PT64_ROOT_LEVEL; | |
2941 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2942 | context->nx = is_nx(vcpu); |
52fde8df | 2943 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2944 | context->gva_to_gpa = paging64_gva_to_gpa; |
2945 | context->root_level = PT32E_ROOT_LEVEL; | |
2946 | } else { | |
2d48a985 | 2947 | context->nx = false; |
52fde8df | 2948 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
2949 | context->gva_to_gpa = paging32_gva_to_gpa; |
2950 | context->root_level = PT32_ROOT_LEVEL; | |
2951 | } | |
2952 | ||
2953 | return 0; | |
2954 | } | |
2955 | ||
52fde8df | 2956 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 2957 | { |
a770f6f2 | 2958 | int r; |
411c588d | 2959 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 2960 | ASSERT(vcpu); |
ad312c7c | 2961 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2962 | |
2963 | if (!is_paging(vcpu)) | |
52fde8df | 2964 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 2965 | else if (is_long_mode(vcpu)) |
52fde8df | 2966 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 2967 | else if (is_pae(vcpu)) |
52fde8df | 2968 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 2969 | else |
52fde8df | 2970 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 2971 | |
5b7e0102 | 2972 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 2973 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
2974 | vcpu->arch.mmu.base_role.smep_andnot_wp |
2975 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
2976 | |
2977 | return r; | |
2978 | } | |
2979 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
2980 | ||
2981 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
2982 | { | |
14dfe855 | 2983 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 2984 | |
14dfe855 JR |
2985 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
2986 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
2987 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
2988 | |
2989 | return r; | |
6aa8b732 AK |
2990 | } |
2991 | ||
02f59dc9 JR |
2992 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
2993 | { | |
2994 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
2995 | ||
2996 | g_context->get_cr3 = get_cr3; | |
2997 | g_context->inject_page_fault = kvm_inject_page_fault; | |
2998 | ||
2999 | /* | |
3000 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3001 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3002 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3003 | * functions between mmu and nested_mmu are swapped. | |
3004 | */ | |
3005 | if (!is_paging(vcpu)) { | |
2d48a985 | 3006 | g_context->nx = false; |
02f59dc9 JR |
3007 | g_context->root_level = 0; |
3008 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3009 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3010 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3011 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
3012 | g_context->root_level = PT64_ROOT_LEVEL; | |
3013 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3014 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3015 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
3016 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
3017 | g_context->root_level = PT32E_ROOT_LEVEL; | |
3018 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
3019 | } else { | |
2d48a985 | 3020 | g_context->nx = false; |
02f59dc9 JR |
3021 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
3022 | g_context->root_level = PT32_ROOT_LEVEL; | |
3023 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
3024 | } | |
3025 | ||
3026 | return 0; | |
3027 | } | |
3028 | ||
fb72d167 JR |
3029 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3030 | { | |
02f59dc9 JR |
3031 | if (mmu_is_nested(vcpu)) |
3032 | return init_kvm_nested_mmu(vcpu); | |
3033 | else if (tdp_enabled) | |
fb72d167 JR |
3034 | return init_kvm_tdp_mmu(vcpu); |
3035 | else | |
3036 | return init_kvm_softmmu(vcpu); | |
3037 | } | |
3038 | ||
6aa8b732 AK |
3039 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3040 | { | |
3041 | ASSERT(vcpu); | |
62ad0755 SY |
3042 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3043 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3044 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3045 | } |
3046 | ||
3047 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3048 | { |
3049 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3050 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3051 | } |
8668a3c4 | 3052 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3053 | |
3054 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3055 | { |
714b93da AK |
3056 | int r; |
3057 | ||
e2dec939 | 3058 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3059 | if (r) |
3060 | goto out; | |
8986ecc0 | 3061 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3062 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3063 | mmu_sync_roots(vcpu); |
aaee2c94 | 3064 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3065 | if (r) |
3066 | goto out; | |
3662cb1c | 3067 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3068 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3069 | out: |
3070 | return r; | |
6aa8b732 | 3071 | } |
17c3ba9d AK |
3072 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3073 | ||
3074 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3075 | { | |
3076 | mmu_free_roots(vcpu); | |
3077 | } | |
4b16184c | 3078 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3079 | |
0028425f | 3080 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3081 | struct kvm_mmu_page *sp, u64 *spte, |
3082 | const void *new) | |
0028425f | 3083 | { |
30945387 | 3084 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3085 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3086 | return; | |
30945387 | 3087 | } |
0028425f | 3088 | |
4cee5764 | 3089 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3090 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3091 | } |
3092 | ||
79539cec AK |
3093 | static bool need_remote_flush(u64 old, u64 new) |
3094 | { | |
3095 | if (!is_shadow_present_pte(old)) | |
3096 | return false; | |
3097 | if (!is_shadow_present_pte(new)) | |
3098 | return true; | |
3099 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3100 | return true; | |
3101 | old ^= PT64_NX_MASK; | |
3102 | new ^= PT64_NX_MASK; | |
3103 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3104 | } | |
3105 | ||
0671a8e7 XG |
3106 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3107 | bool remote_flush, bool local_flush) | |
79539cec | 3108 | { |
0671a8e7 XG |
3109 | if (zap_page) |
3110 | return; | |
3111 | ||
3112 | if (remote_flush) | |
79539cec | 3113 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3114 | else if (local_flush) |
79539cec AK |
3115 | kvm_mmu_flush_tlb(vcpu); |
3116 | } | |
3117 | ||
12b7d28f AK |
3118 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3119 | { | |
ad312c7c | 3120 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3121 | |
7b52345e | 3122 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3123 | } |
3124 | ||
1b7fcd32 AK |
3125 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3126 | { | |
3127 | u64 *spte = vcpu->arch.last_pte_updated; | |
3128 | ||
3129 | if (spte | |
3130 | && vcpu->arch.last_pte_gfn == gfn | |
3131 | && shadow_accessed_mask | |
3132 | && !(*spte & shadow_accessed_mask) | |
3133 | && is_shadow_present_pte(*spte)) | |
3134 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3135 | } | |
3136 | ||
09072daf | 3137 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3138 | const u8 *new, int bytes, |
3139 | bool guest_initiated) | |
da4a00f0 | 3140 | { |
9b7a0325 | 3141 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3142 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3143 | struct kvm_mmu_page *sp; |
f41d335a | 3144 | struct hlist_node *node; |
d98ba053 | 3145 | LIST_HEAD(invalid_list); |
0f53b5b1 XG |
3146 | u64 entry, gentry, *spte; |
3147 | unsigned pte_size, page_offset, misaligned, quadrant, offset; | |
3148 | int level, npte, invlpg_counter, r, flooded = 0; | |
0671a8e7 XG |
3149 | bool remote_flush, local_flush, zap_page; |
3150 | ||
332b207d XG |
3151 | /* |
3152 | * If we don't have indirect shadow pages, it means no page is | |
3153 | * write-protected, so we can exit simply. | |
3154 | */ | |
3155 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3156 | return; | |
3157 | ||
0671a8e7 | 3158 | zap_page = remote_flush = local_flush = false; |
0f53b5b1 | 3159 | offset = offset_in_page(gpa); |
9b7a0325 | 3160 | |
b8688d51 | 3161 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3162 | |
08e850c6 | 3163 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3164 | |
3165 | /* | |
3166 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3167 | * as the current vcpu paging mode since we update the sptes only |
3168 | * when they have the same mode. | |
72016f3a | 3169 | */ |
08e850c6 | 3170 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3171 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3172 | if (is_pae(vcpu)) { |
3173 | gpa &= ~(gpa_t)7; | |
3174 | bytes = 8; | |
3175 | } | |
3176 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3177 | if (r) |
3178 | gentry = 0; | |
08e850c6 AK |
3179 | new = (const u8 *)&gentry; |
3180 | } | |
3181 | ||
3182 | switch (bytes) { | |
3183 | case 4: | |
3184 | gentry = *(const u32 *)new; | |
3185 | break; | |
3186 | case 8: | |
3187 | gentry = *(const u64 *)new; | |
3188 | break; | |
3189 | default: | |
3190 | gentry = 0; | |
3191 | break; | |
72016f3a AK |
3192 | } |
3193 | ||
aaee2c94 | 3194 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3195 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3196 | gentry = 0; | |
eb787d10 | 3197 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3198 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3199 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 | 3200 | if (guest_initiated) { |
1b7fd45c | 3201 | kvm_mmu_access_page(vcpu, gfn); |
ad218f85 MT |
3202 | if (gfn == vcpu->arch.last_pt_write_gfn |
3203 | && !last_updated_pte_accessed(vcpu)) { | |
3204 | ++vcpu->arch.last_pt_write_count; | |
3205 | if (vcpu->arch.last_pt_write_count >= 3) | |
3206 | flooded = 1; | |
3207 | } else { | |
3208 | vcpu->arch.last_pt_write_gfn = gfn; | |
3209 | vcpu->arch.last_pt_write_count = 1; | |
3210 | vcpu->arch.last_pte_updated = NULL; | |
3211 | } | |
86a5ba02 | 3212 | } |
3246af0e | 3213 | |
fa1de2bf | 3214 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3215 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3216 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3217 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3218 | misaligned |= bytes < 4; |
86a5ba02 | 3219 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3220 | /* |
3221 | * Misaligned accesses are too much trouble to fix | |
3222 | * up; also, they usually indicate a page is not used | |
3223 | * as a page table. | |
86a5ba02 AK |
3224 | * |
3225 | * If we're seeing too many writes to a page, | |
3226 | * it may no longer be a page table, or we may be | |
3227 | * forking, in which case it is better to unmap the | |
3228 | * page. | |
0e7bc4b9 AK |
3229 | */ |
3230 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3231 | gpa, bytes, sp->role.word); |
0671a8e7 | 3232 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3233 | &invalid_list); |
4cee5764 | 3234 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3235 | continue; |
3236 | } | |
9b7a0325 | 3237 | page_offset = offset; |
4db35314 | 3238 | level = sp->role.level; |
ac1b714e | 3239 | npte = 1; |
5b7e0102 | 3240 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3241 | page_offset <<= 1; /* 32->64 */ |
3242 | /* | |
3243 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3244 | * only 2MB. So we need to double the offset again | |
3245 | * and zap two pdes instead of one. | |
3246 | */ | |
3247 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3248 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3249 | page_offset <<= 1; |
3250 | npte = 2; | |
3251 | } | |
fce0657f | 3252 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3253 | page_offset &= ~PAGE_MASK; |
4db35314 | 3254 | if (quadrant != sp->role.quadrant) |
fce0657f | 3255 | continue; |
9b7a0325 | 3256 | } |
0671a8e7 | 3257 | local_flush = true; |
4db35314 | 3258 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3259 | while (npte--) { |
79539cec | 3260 | entry = *spte; |
38e3b2b2 | 3261 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3262 | if (gentry && |
3263 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3264 | & mask.word)) | |
7c562522 | 3265 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3266 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3267 | remote_flush = true; | |
ac1b714e | 3268 | ++spte; |
9b7a0325 | 3269 | } |
9b7a0325 | 3270 | } |
0671a8e7 | 3271 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3272 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3273 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3274 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3275 | } |
3276 | ||
a436036b AK |
3277 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3278 | { | |
10589a46 MT |
3279 | gpa_t gpa; |
3280 | int r; | |
a436036b | 3281 | |
c5a78f2b | 3282 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3283 | return 0; |
3284 | ||
1871c602 | 3285 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3286 | |
aaee2c94 | 3287 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3288 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3289 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3290 | return r; |
a436036b | 3291 | } |
577bdc49 | 3292 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3293 | |
22d95b12 | 3294 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3295 | { |
d98ba053 | 3296 | LIST_HEAD(invalid_list); |
103ad25a | 3297 | |
e0df7b9f | 3298 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3299 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3300 | struct kvm_mmu_page *sp; |
ebeace86 | 3301 | |
f05e70ac | 3302 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3303 | struct kvm_mmu_page, link); |
e0df7b9f | 3304 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 3305 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 3306 | } |
aa6bd187 | 3307 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 3308 | } |
ebeace86 | 3309 | |
dc25e89e AP |
3310 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3311 | void *insn, int insn_len) | |
3067714c AK |
3312 | { |
3313 | int r; | |
3314 | enum emulation_result er; | |
3315 | ||
56028d08 | 3316 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3317 | if (r < 0) |
3318 | goto out; | |
3319 | ||
3320 | if (!r) { | |
3321 | r = 1; | |
3322 | goto out; | |
3323 | } | |
3324 | ||
b733bfb5 AK |
3325 | r = mmu_topup_memory_caches(vcpu); |
3326 | if (r) | |
3327 | goto out; | |
3328 | ||
dc25e89e | 3329 | er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len); |
3067714c AK |
3330 | |
3331 | switch (er) { | |
3332 | case EMULATE_DONE: | |
3333 | return 1; | |
3334 | case EMULATE_DO_MMIO: | |
3335 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3336 | /* fall through */ |
3067714c | 3337 | case EMULATE_FAIL: |
3f5d18a9 | 3338 | return 0; |
3067714c AK |
3339 | default: |
3340 | BUG(); | |
3341 | } | |
3342 | out: | |
3067714c AK |
3343 | return r; |
3344 | } | |
3345 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3346 | ||
a7052897 MT |
3347 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3348 | { | |
a7052897 | 3349 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3350 | kvm_mmu_flush_tlb(vcpu); |
3351 | ++vcpu->stat.invlpg; | |
3352 | } | |
3353 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3354 | ||
18552672 JR |
3355 | void kvm_enable_tdp(void) |
3356 | { | |
3357 | tdp_enabled = true; | |
3358 | } | |
3359 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3360 | ||
5f4cb662 JR |
3361 | void kvm_disable_tdp(void) |
3362 | { | |
3363 | tdp_enabled = false; | |
3364 | } | |
3365 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3366 | ||
6aa8b732 AK |
3367 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3368 | { | |
ad312c7c | 3369 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3370 | if (vcpu->arch.mmu.lm_root != NULL) |
3371 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3372 | } |
3373 | ||
3374 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3375 | { | |
17ac10ad | 3376 | struct page *page; |
6aa8b732 AK |
3377 | int i; |
3378 | ||
3379 | ASSERT(vcpu); | |
3380 | ||
17ac10ad AK |
3381 | /* |
3382 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3383 | * Therefore we need to allocate shadow page tables in the first | |
3384 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3385 | */ | |
3386 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3387 | if (!page) | |
d7fa6ab2 WY |
3388 | return -ENOMEM; |
3389 | ||
ad312c7c | 3390 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3391 | for (i = 0; i < 4; ++i) |
ad312c7c | 3392 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3393 | |
6aa8b732 | 3394 | return 0; |
6aa8b732 AK |
3395 | } |
3396 | ||
8018c27b | 3397 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3398 | { |
6aa8b732 | 3399 | ASSERT(vcpu); |
ad312c7c | 3400 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3401 | |
8018c27b IM |
3402 | return alloc_mmu_pages(vcpu); |
3403 | } | |
6aa8b732 | 3404 | |
8018c27b IM |
3405 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3406 | { | |
3407 | ASSERT(vcpu); | |
ad312c7c | 3408 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3409 | |
8018c27b | 3410 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3411 | } |
3412 | ||
90cb0529 | 3413 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3414 | { |
4db35314 | 3415 | struct kvm_mmu_page *sp; |
6aa8b732 | 3416 | |
f05e70ac | 3417 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3418 | int i; |
3419 | u64 *pt; | |
3420 | ||
291f26bc | 3421 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3422 | continue; |
3423 | ||
4db35314 | 3424 | pt = sp->spt; |
8234b22e | 3425 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3426 | if (!is_shadow_present_pte(pt[i]) || |
3427 | !is_last_spte(pt[i], sp->role.level)) | |
3428 | continue; | |
3429 | ||
3430 | if (is_large_pte(pt[i])) { | |
8234b22e AK |
3431 | drop_spte(kvm, &pt[i], |
3432 | shadow_trap_nonpresent_pte); | |
3433 | --kvm->stat.lpages; | |
da8dc75f | 3434 | continue; |
8234b22e | 3435 | } |
da8dc75f | 3436 | |
6aa8b732 | 3437 | /* avoid RMW */ |
01c168ac | 3438 | if (is_writable_pte(pt[i])) |
700e1b12 | 3439 | update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK); |
8234b22e | 3440 | } |
6aa8b732 | 3441 | } |
171d595d | 3442 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3443 | } |
37a7d8b0 | 3444 | |
90cb0529 | 3445 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3446 | { |
4db35314 | 3447 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3448 | LIST_HEAD(invalid_list); |
e0fa826f | 3449 | |
aaee2c94 | 3450 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3451 | restart: |
f05e70ac | 3452 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3453 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3454 | goto restart; |
3455 | ||
d98ba053 | 3456 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3457 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3458 | } |
3459 | ||
d98ba053 XG |
3460 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3461 | struct list_head *invalid_list) | |
3ee16c81 IE |
3462 | { |
3463 | struct kvm_mmu_page *page; | |
3464 | ||
3465 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3466 | struct kvm_mmu_page, link); | |
d98ba053 | 3467 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3468 | } |
3469 | ||
1495f230 | 3470 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3471 | { |
3472 | struct kvm *kvm; | |
3473 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3474 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3475 | |
3476 | if (nr_to_scan == 0) | |
3477 | goto out; | |
3ee16c81 | 3478 | |
e935b837 | 3479 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3480 | |
3481 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3482 | int idx, freed_pages; |
d98ba053 | 3483 | LIST_HEAD(invalid_list); |
3ee16c81 | 3484 | |
f656ce01 | 3485 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3486 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3487 | if (!kvm_freed && nr_to_scan > 0 && |
3488 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3489 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3490 | &invalid_list); | |
3ee16c81 IE |
3491 | kvm_freed = kvm; |
3492 | } | |
3493 | nr_to_scan--; | |
3494 | ||
d98ba053 | 3495 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3496 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3497 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3498 | } |
3499 | if (kvm_freed) | |
3500 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3501 | ||
e935b837 | 3502 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3503 | |
45221ab6 DH |
3504 | out: |
3505 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3506 | } |
3507 | ||
3508 | static struct shrinker mmu_shrinker = { | |
3509 | .shrink = mmu_shrink, | |
3510 | .seeks = DEFAULT_SEEKS * 10, | |
3511 | }; | |
3512 | ||
2ddfd20e | 3513 | static void mmu_destroy_caches(void) |
b5a33a75 | 3514 | { |
53c07b18 XG |
3515 | if (pte_list_desc_cache) |
3516 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
3517 | if (mmu_page_header_cache) |
3518 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3519 | } |
3520 | ||
3521 | int kvm_mmu_module_init(void) | |
3522 | { | |
53c07b18 XG |
3523 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
3524 | sizeof(struct pte_list_desc), | |
20c2df83 | 3525 | 0, 0, NULL); |
53c07b18 | 3526 | if (!pte_list_desc_cache) |
b5a33a75 AK |
3527 | goto nomem; |
3528 | ||
d3d25b04 AK |
3529 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3530 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3531 | 0, 0, NULL); |
d3d25b04 AK |
3532 | if (!mmu_page_header_cache) |
3533 | goto nomem; | |
3534 | ||
45bf21a8 WY |
3535 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3536 | goto nomem; | |
3537 | ||
3ee16c81 IE |
3538 | register_shrinker(&mmu_shrinker); |
3539 | ||
b5a33a75 AK |
3540 | return 0; |
3541 | ||
3542 | nomem: | |
3ee16c81 | 3543 | mmu_destroy_caches(); |
b5a33a75 AK |
3544 | return -ENOMEM; |
3545 | } | |
3546 | ||
3ad82a7e ZX |
3547 | /* |
3548 | * Caculate mmu pages needed for kvm. | |
3549 | */ | |
3550 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3551 | { | |
3552 | int i; | |
3553 | unsigned int nr_mmu_pages; | |
3554 | unsigned int nr_pages = 0; | |
bc6678a3 | 3555 | struct kvm_memslots *slots; |
3ad82a7e | 3556 | |
90d83dc3 LJ |
3557 | slots = kvm_memslots(kvm); |
3558 | ||
bc6678a3 MT |
3559 | for (i = 0; i < slots->nmemslots; i++) |
3560 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3561 | |
3562 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3563 | nr_mmu_pages = max(nr_mmu_pages, | |
3564 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3565 | ||
3566 | return nr_mmu_pages; | |
3567 | } | |
3568 | ||
2f333bcb MT |
3569 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3570 | unsigned len) | |
3571 | { | |
3572 | if (len > buffer->len) | |
3573 | return NULL; | |
3574 | return buffer->ptr; | |
3575 | } | |
3576 | ||
3577 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3578 | unsigned len) | |
3579 | { | |
3580 | void *ret; | |
3581 | ||
3582 | ret = pv_mmu_peek_buffer(buffer, len); | |
3583 | if (!ret) | |
3584 | return ret; | |
3585 | buffer->ptr += len; | |
3586 | buffer->len -= len; | |
3587 | buffer->processed += len; | |
3588 | return ret; | |
3589 | } | |
3590 | ||
3591 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3592 | gpa_t addr, gpa_t value) | |
3593 | { | |
3594 | int bytes = 8; | |
3595 | int r; | |
3596 | ||
3597 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3598 | bytes = 4; | |
3599 | ||
3600 | r = mmu_topup_memory_caches(vcpu); | |
3601 | if (r) | |
3602 | return r; | |
3603 | ||
3200f405 | 3604 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3605 | return -EFAULT; |
3606 | ||
3607 | return 1; | |
3608 | } | |
3609 | ||
3610 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3611 | { | |
9f8fe504 | 3612 | (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu)); |
2f333bcb MT |
3613 | return 1; |
3614 | } | |
3615 | ||
3616 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3617 | { | |
3618 | spin_lock(&vcpu->kvm->mmu_lock); | |
3619 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3620 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3621 | return 1; | |
3622 | } | |
3623 | ||
3624 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3625 | struct kvm_pv_mmu_op_buffer *buffer) | |
3626 | { | |
3627 | struct kvm_mmu_op_header *header; | |
3628 | ||
3629 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3630 | if (!header) | |
3631 | return 0; | |
3632 | switch (header->op) { | |
3633 | case KVM_MMU_OP_WRITE_PTE: { | |
3634 | struct kvm_mmu_op_write_pte *wpte; | |
3635 | ||
3636 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3637 | if (!wpte) | |
3638 | return 0; | |
3639 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3640 | wpte->pte_val); | |
3641 | } | |
3642 | case KVM_MMU_OP_FLUSH_TLB: { | |
3643 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3644 | ||
3645 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3646 | if (!ftlb) | |
3647 | return 0; | |
3648 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3649 | } | |
3650 | case KVM_MMU_OP_RELEASE_PT: { | |
3651 | struct kvm_mmu_op_release_pt *rpt; | |
3652 | ||
3653 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3654 | if (!rpt) | |
3655 | return 0; | |
3656 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3657 | } | |
3658 | default: return 0; | |
3659 | } | |
3660 | } | |
3661 | ||
3662 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3663 | gpa_t addr, unsigned long *ret) | |
3664 | { | |
3665 | int r; | |
6ad18fba | 3666 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3667 | |
6ad18fba DH |
3668 | buffer->ptr = buffer->buf; |
3669 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3670 | buffer->processed = 0; | |
2f333bcb | 3671 | |
6ad18fba | 3672 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3673 | if (r) |
3674 | goto out; | |
3675 | ||
6ad18fba DH |
3676 | while (buffer->len) { |
3677 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3678 | if (r < 0) |
3679 | goto out; | |
3680 | if (r == 0) | |
3681 | break; | |
3682 | } | |
3683 | ||
3684 | r = 1; | |
3685 | out: | |
6ad18fba | 3686 | *ret = buffer->processed; |
2f333bcb MT |
3687 | return r; |
3688 | } | |
3689 | ||
94d8b056 MT |
3690 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3691 | { | |
3692 | struct kvm_shadow_walk_iterator iterator; | |
3693 | int nr_sptes = 0; | |
3694 | ||
3695 | spin_lock(&vcpu->kvm->mmu_lock); | |
3696 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3697 | sptes[iterator.level-1] = *iterator.sptep; | |
3698 | nr_sptes++; | |
3699 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3700 | break; | |
3701 | } | |
3702 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3703 | ||
3704 | return nr_sptes; | |
3705 | } | |
3706 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3707 | ||
c42fffe3 XG |
3708 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
3709 | { | |
3710 | ASSERT(vcpu); | |
3711 | ||
3712 | destroy_kvm_mmu(vcpu); | |
3713 | free_mmu_pages(vcpu); | |
3714 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
3715 | } |
3716 | ||
3717 | #ifdef CONFIG_KVM_MMU_AUDIT | |
3718 | #include "mmu_audit.c" | |
3719 | #else | |
3720 | static void mmu_audit_disable(void) { } | |
3721 | #endif | |
3722 | ||
3723 | void kvm_mmu_module_exit(void) | |
3724 | { | |
3725 | mmu_destroy_caches(); | |
3726 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
3727 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
3728 | mmu_audit_disable(); |
3729 | } |