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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
6aa8b732 AK |
93 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
53c07b18 | 138 | #define PTE_LIST_EXT 4 |
cd4a4e53 | 139 | |
fe135d2c AK |
140 | #define ACC_EXEC_MASK 1 |
141 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
142 | #define ACC_USER_MASK PT_USER_MASK | |
143 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
144 | ||
90bb6fc5 AK |
145 | #include <trace/events/kvm.h> |
146 | ||
07420171 AK |
147 | #define CREATE_TRACE_POINTS |
148 | #include "mmutrace.h" | |
149 | ||
1403283a IE |
150 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
151 | ||
135f8c2b AK |
152 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
153 | ||
53c07b18 XG |
154 | struct pte_list_desc { |
155 | u64 *sptes[PTE_LIST_EXT]; | |
156 | struct pte_list_desc *more; | |
cd4a4e53 AK |
157 | }; |
158 | ||
2d11123a AK |
159 | struct kvm_shadow_walk_iterator { |
160 | u64 addr; | |
161 | hpa_t shadow_addr; | |
2d11123a | 162 | u64 *sptep; |
dd3bfd59 | 163 | int level; |
2d11123a AK |
164 | unsigned index; |
165 | }; | |
166 | ||
167 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
168 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
169 | shadow_walk_okay(&(_walker)); \ | |
170 | shadow_walk_next(&(_walker))) | |
171 | ||
c2a2ac2b XG |
172 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
173 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
174 | shadow_walk_okay(&(_walker)) && \ | |
175 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
176 | __shadow_walk_next(&(_walker), spte)) | |
177 | ||
53c07b18 | 178 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 179 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 180 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 181 | |
7b52345e SY |
182 | static u64 __read_mostly shadow_nx_mask; |
183 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
184 | static u64 __read_mostly shadow_user_mask; | |
185 | static u64 __read_mostly shadow_accessed_mask; | |
186 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
187 | static u64 __read_mostly shadow_mmio_mask; |
188 | ||
189 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
190 | ||
191 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
192 | { | |
193 | shadow_mmio_mask = mmio_mask; | |
194 | } | |
195 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
196 | ||
197 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
198 | { | |
199 | access &= ACC_WRITE_MASK | ACC_USER_MASK; | |
200 | ||
4f022648 | 201 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
202 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
203 | } | |
204 | ||
205 | static bool is_mmio_spte(u64 spte) | |
206 | { | |
207 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
208 | } | |
209 | ||
210 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
211 | { | |
212 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
213 | } | |
214 | ||
215 | static unsigned get_mmio_spte_access(u64 spte) | |
216 | { | |
217 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
218 | } | |
219 | ||
220 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
221 | { | |
222 | if (unlikely(is_noslot_pfn(pfn))) { | |
223 | mark_mmio_spte(sptep, gfn, access); | |
224 | return true; | |
225 | } | |
226 | ||
227 | return false; | |
228 | } | |
c7addb90 | 229 | |
82725b20 DE |
230 | static inline u64 rsvd_bits(int s, int e) |
231 | { | |
232 | return ((1ULL << (e - s + 1)) - 1) << s; | |
233 | } | |
234 | ||
7b52345e | 235 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 236 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
237 | { |
238 | shadow_user_mask = user_mask; | |
239 | shadow_accessed_mask = accessed_mask; | |
240 | shadow_dirty_mask = dirty_mask; | |
241 | shadow_nx_mask = nx_mask; | |
242 | shadow_x_mask = x_mask; | |
243 | } | |
244 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
245 | ||
6aa8b732 AK |
246 | static int is_cpuid_PSE36(void) |
247 | { | |
248 | return 1; | |
249 | } | |
250 | ||
73b1087e AK |
251 | static int is_nx(struct kvm_vcpu *vcpu) |
252 | { | |
f6801dff | 253 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
254 | } |
255 | ||
c7addb90 AK |
256 | static int is_shadow_present_pte(u64 pte) |
257 | { | |
ce88decf | 258 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
259 | } |
260 | ||
05da4558 MT |
261 | static int is_large_pte(u64 pte) |
262 | { | |
263 | return pte & PT_PAGE_SIZE_MASK; | |
264 | } | |
265 | ||
43a3795a | 266 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 267 | { |
439e218a | 268 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
269 | } |
270 | ||
43a3795a | 271 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 272 | { |
4b1a80fa | 273 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
274 | } |
275 | ||
776e6633 MT |
276 | static int is_last_spte(u64 pte, int level) |
277 | { | |
278 | if (level == PT_PAGE_TABLE_LEVEL) | |
279 | return 1; | |
852e3c19 | 280 | if (is_large_pte(pte)) |
776e6633 MT |
281 | return 1; |
282 | return 0; | |
283 | } | |
284 | ||
35149e21 | 285 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 286 | { |
35149e21 | 287 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
288 | } |
289 | ||
da928521 AK |
290 | static gfn_t pse36_gfn_delta(u32 gpte) |
291 | { | |
292 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
293 | ||
294 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
295 | } | |
296 | ||
603e0651 | 297 | #ifdef CONFIG_X86_64 |
d555c333 | 298 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 299 | { |
603e0651 | 300 | *sptep = spte; |
e663ee64 AK |
301 | } |
302 | ||
603e0651 | 303 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 304 | { |
603e0651 XG |
305 | *sptep = spte; |
306 | } | |
307 | ||
308 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
309 | { | |
310 | return xchg(sptep, spte); | |
311 | } | |
c2a2ac2b XG |
312 | |
313 | static u64 __get_spte_lockless(u64 *sptep) | |
314 | { | |
315 | return ACCESS_ONCE(*sptep); | |
316 | } | |
ce88decf XG |
317 | |
318 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
319 | { | |
320 | /* It is valid if the spte is zapped. */ | |
321 | return spte == 0ull; | |
322 | } | |
a9221dd5 | 323 | #else |
603e0651 XG |
324 | union split_spte { |
325 | struct { | |
326 | u32 spte_low; | |
327 | u32 spte_high; | |
328 | }; | |
329 | u64 spte; | |
330 | }; | |
a9221dd5 | 331 | |
c2a2ac2b XG |
332 | static void count_spte_clear(u64 *sptep, u64 spte) |
333 | { | |
334 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
335 | ||
336 | if (is_shadow_present_pte(spte)) | |
337 | return; | |
338 | ||
339 | /* Ensure the spte is completely set before we increase the count */ | |
340 | smp_wmb(); | |
341 | sp->clear_spte_count++; | |
342 | } | |
343 | ||
603e0651 XG |
344 | static void __set_spte(u64 *sptep, u64 spte) |
345 | { | |
346 | union split_spte *ssptep, sspte; | |
a9221dd5 | 347 | |
603e0651 XG |
348 | ssptep = (union split_spte *)sptep; |
349 | sspte = (union split_spte)spte; | |
350 | ||
351 | ssptep->spte_high = sspte.spte_high; | |
352 | ||
353 | /* | |
354 | * If we map the spte from nonpresent to present, We should store | |
355 | * the high bits firstly, then set present bit, so cpu can not | |
356 | * fetch this spte while we are setting the spte. | |
357 | */ | |
358 | smp_wmb(); | |
359 | ||
360 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
361 | } |
362 | ||
603e0651 XG |
363 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
364 | { | |
365 | union split_spte *ssptep, sspte; | |
366 | ||
367 | ssptep = (union split_spte *)sptep; | |
368 | sspte = (union split_spte)spte; | |
369 | ||
370 | ssptep->spte_low = sspte.spte_low; | |
371 | ||
372 | /* | |
373 | * If we map the spte from present to nonpresent, we should clear | |
374 | * present bit firstly to avoid vcpu fetch the old high bits. | |
375 | */ | |
376 | smp_wmb(); | |
377 | ||
378 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 379 | count_spte_clear(sptep, spte); |
603e0651 XG |
380 | } |
381 | ||
382 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
383 | { | |
384 | union split_spte *ssptep, sspte, orig; | |
385 | ||
386 | ssptep = (union split_spte *)sptep; | |
387 | sspte = (union split_spte)spte; | |
388 | ||
389 | /* xchg acts as a barrier before the setting of the high bits */ | |
390 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
391 | orig.spte_high = ssptep->spte_high; |
392 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 393 | count_spte_clear(sptep, spte); |
603e0651 XG |
394 | |
395 | return orig.spte; | |
396 | } | |
c2a2ac2b XG |
397 | |
398 | /* | |
399 | * The idea using the light way get the spte on x86_32 guest is from | |
400 | * gup_get_pte(arch/x86/mm/gup.c). | |
401 | * The difference is we can not catch the spte tlb flush if we leave | |
402 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
403 | * is cleared. | |
404 | */ | |
405 | static u64 __get_spte_lockless(u64 *sptep) | |
406 | { | |
407 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
408 | union split_spte spte, *orig = (union split_spte *)sptep; | |
409 | int count; | |
410 | ||
411 | retry: | |
412 | count = sp->clear_spte_count; | |
413 | smp_rmb(); | |
414 | ||
415 | spte.spte_low = orig->spte_low; | |
416 | smp_rmb(); | |
417 | ||
418 | spte.spte_high = orig->spte_high; | |
419 | smp_rmb(); | |
420 | ||
421 | if (unlikely(spte.spte_low != orig->spte_low || | |
422 | count != sp->clear_spte_count)) | |
423 | goto retry; | |
424 | ||
425 | return spte.spte; | |
426 | } | |
ce88decf XG |
427 | |
428 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
429 | { | |
430 | union split_spte sspte = (union split_spte)spte; | |
431 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
432 | ||
433 | /* It is valid if the spte is zapped. */ | |
434 | if (spte == 0ull) | |
435 | return true; | |
436 | ||
437 | /* It is valid if the spte is being zapped. */ | |
438 | if (sspte.spte_low == 0ull && | |
439 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
440 | return true; | |
441 | ||
442 | return false; | |
443 | } | |
603e0651 XG |
444 | #endif |
445 | ||
8672b721 XG |
446 | static bool spte_has_volatile_bits(u64 spte) |
447 | { | |
448 | if (!shadow_accessed_mask) | |
449 | return false; | |
450 | ||
451 | if (!is_shadow_present_pte(spte)) | |
452 | return false; | |
453 | ||
4132779b XG |
454 | if ((spte & shadow_accessed_mask) && |
455 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
456 | return false; |
457 | ||
458 | return true; | |
459 | } | |
460 | ||
4132779b XG |
461 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
462 | { | |
463 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
464 | } | |
465 | ||
1df9f2dc XG |
466 | /* Rules for using mmu_spte_set: |
467 | * Set the sptep from nonpresent to present. | |
468 | * Note: the sptep being assigned *must* be either not present | |
469 | * or in a state where the hardware will not attempt to update | |
470 | * the spte. | |
471 | */ | |
472 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
473 | { | |
474 | WARN_ON(is_shadow_present_pte(*sptep)); | |
475 | __set_spte(sptep, new_spte); | |
476 | } | |
477 | ||
478 | /* Rules for using mmu_spte_update: | |
479 | * Update the state bits, it means the mapped pfn is not changged. | |
480 | */ | |
481 | static void mmu_spte_update(u64 *sptep, u64 new_spte) | |
b79b93f9 | 482 | { |
4132779b XG |
483 | u64 mask, old_spte = *sptep; |
484 | ||
485 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 486 | |
1df9f2dc XG |
487 | if (!is_shadow_present_pte(old_spte)) |
488 | return mmu_spte_set(sptep, new_spte); | |
489 | ||
4132779b XG |
490 | new_spte |= old_spte & shadow_dirty_mask; |
491 | ||
492 | mask = shadow_accessed_mask; | |
493 | if (is_writable_pte(old_spte)) | |
494 | mask |= shadow_dirty_mask; | |
495 | ||
496 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
603e0651 | 497 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 498 | else |
603e0651 | 499 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b XG |
500 | |
501 | if (!shadow_accessed_mask) | |
502 | return; | |
503 | ||
504 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
505 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
506 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
507 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
508 | } |
509 | ||
1df9f2dc XG |
510 | /* |
511 | * Rules for using mmu_spte_clear_track_bits: | |
512 | * It sets the sptep from present to nonpresent, and track the | |
513 | * state bits, it is used to clear the last level sptep. | |
514 | */ | |
515 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
516 | { | |
517 | pfn_t pfn; | |
518 | u64 old_spte = *sptep; | |
519 | ||
520 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 521 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 522 | else |
603e0651 | 523 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
524 | |
525 | if (!is_rmap_spte(old_spte)) | |
526 | return 0; | |
527 | ||
528 | pfn = spte_to_pfn(old_spte); | |
529 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) | |
530 | kvm_set_pfn_accessed(pfn); | |
531 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
532 | kvm_set_pfn_dirty(pfn); | |
533 | return 1; | |
534 | } | |
535 | ||
536 | /* | |
537 | * Rules for using mmu_spte_clear_no_track: | |
538 | * Directly clear spte without caring the state bits of sptep, | |
539 | * it is used to set the upper level spte. | |
540 | */ | |
541 | static void mmu_spte_clear_no_track(u64 *sptep) | |
542 | { | |
603e0651 | 543 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
544 | } |
545 | ||
c2a2ac2b XG |
546 | static u64 mmu_spte_get_lockless(u64 *sptep) |
547 | { | |
548 | return __get_spte_lockless(sptep); | |
549 | } | |
550 | ||
551 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
552 | { | |
553 | rcu_read_lock(); | |
554 | atomic_inc(&vcpu->kvm->arch.reader_counter); | |
555 | ||
556 | /* Increase the counter before walking shadow page table */ | |
557 | smp_mb__after_atomic_inc(); | |
558 | } | |
559 | ||
560 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
561 | { | |
562 | /* Decrease the counter after walking shadow page table finished */ | |
563 | smp_mb__before_atomic_dec(); | |
564 | atomic_dec(&vcpu->kvm->arch.reader_counter); | |
565 | rcu_read_unlock(); | |
566 | } | |
567 | ||
e2dec939 | 568 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 569 | struct kmem_cache *base_cache, int min) |
714b93da AK |
570 | { |
571 | void *obj; | |
572 | ||
573 | if (cache->nobjs >= min) | |
e2dec939 | 574 | return 0; |
714b93da | 575 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 576 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 577 | if (!obj) |
e2dec939 | 578 | return -ENOMEM; |
714b93da AK |
579 | cache->objects[cache->nobjs++] = obj; |
580 | } | |
e2dec939 | 581 | return 0; |
714b93da AK |
582 | } |
583 | ||
f759e2b4 XG |
584 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
585 | { | |
586 | return cache->nobjs; | |
587 | } | |
588 | ||
e8ad9a70 XG |
589 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
590 | struct kmem_cache *cache) | |
714b93da AK |
591 | { |
592 | while (mc->nobjs) | |
e8ad9a70 | 593 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
594 | } |
595 | ||
c1158e63 | 596 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 597 | int min) |
c1158e63 | 598 | { |
842f22ed | 599 | void *page; |
c1158e63 AK |
600 | |
601 | if (cache->nobjs >= min) | |
602 | return 0; | |
603 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 604 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
605 | if (!page) |
606 | return -ENOMEM; | |
842f22ed | 607 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
608 | } |
609 | return 0; | |
610 | } | |
611 | ||
612 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
613 | { | |
614 | while (mc->nobjs) | |
c4d198d5 | 615 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
616 | } |
617 | ||
2e3e5882 | 618 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 619 | { |
e2dec939 AK |
620 | int r; |
621 | ||
53c07b18 | 622 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 623 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
624 | if (r) |
625 | goto out; | |
ad312c7c | 626 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
627 | if (r) |
628 | goto out; | |
ad312c7c | 629 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 630 | mmu_page_header_cache, 4); |
e2dec939 AK |
631 | out: |
632 | return r; | |
714b93da AK |
633 | } |
634 | ||
635 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
636 | { | |
53c07b18 XG |
637 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
638 | pte_list_desc_cache); | |
ad312c7c | 639 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
640 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
641 | mmu_page_header_cache); | |
714b93da AK |
642 | } |
643 | ||
644 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
645 | size_t size) | |
646 | { | |
647 | void *p; | |
648 | ||
649 | BUG_ON(!mc->nobjs); | |
650 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
651 | return p; |
652 | } | |
653 | ||
53c07b18 | 654 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 655 | { |
53c07b18 XG |
656 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache, |
657 | sizeof(struct pte_list_desc)); | |
714b93da AK |
658 | } |
659 | ||
53c07b18 | 660 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 661 | { |
53c07b18 | 662 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
663 | } |
664 | ||
2032a93d LJ |
665 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
666 | { | |
667 | if (!sp->role.direct) | |
668 | return sp->gfns[index]; | |
669 | ||
670 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
671 | } | |
672 | ||
673 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
674 | { | |
675 | if (sp->role.direct) | |
676 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
677 | else | |
678 | sp->gfns[index] = gfn; | |
679 | } | |
680 | ||
05da4558 | 681 | /* |
d4dbf470 TY |
682 | * Return the pointer to the large page information for a given gfn, |
683 | * handling slots that are not large page aligned. | |
05da4558 | 684 | */ |
d4dbf470 TY |
685 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
686 | struct kvm_memory_slot *slot, | |
687 | int level) | |
05da4558 MT |
688 | { |
689 | unsigned long idx; | |
690 | ||
fb03cb6f | 691 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 692 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
693 | } |
694 | ||
695 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
696 | { | |
d25797b2 | 697 | struct kvm_memory_slot *slot; |
d4dbf470 | 698 | struct kvm_lpage_info *linfo; |
d25797b2 | 699 | int i; |
05da4558 | 700 | |
a1f4d395 | 701 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
702 | for (i = PT_DIRECTORY_LEVEL; |
703 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
704 | linfo = lpage_info_slot(gfn, slot, i); |
705 | linfo->write_count += 1; | |
d25797b2 | 706 | } |
332b207d | 707 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
708 | } |
709 | ||
710 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
711 | { | |
d25797b2 | 712 | struct kvm_memory_slot *slot; |
d4dbf470 | 713 | struct kvm_lpage_info *linfo; |
d25797b2 | 714 | int i; |
05da4558 | 715 | |
a1f4d395 | 716 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
717 | for (i = PT_DIRECTORY_LEVEL; |
718 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
719 | linfo = lpage_info_slot(gfn, slot, i); |
720 | linfo->write_count -= 1; | |
721 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 722 | } |
332b207d | 723 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
724 | } |
725 | ||
d25797b2 JR |
726 | static int has_wrprotected_page(struct kvm *kvm, |
727 | gfn_t gfn, | |
728 | int level) | |
05da4558 | 729 | { |
2843099f | 730 | struct kvm_memory_slot *slot; |
d4dbf470 | 731 | struct kvm_lpage_info *linfo; |
05da4558 | 732 | |
a1f4d395 | 733 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 734 | if (slot) { |
d4dbf470 TY |
735 | linfo = lpage_info_slot(gfn, slot, level); |
736 | return linfo->write_count; | |
05da4558 MT |
737 | } |
738 | ||
739 | return 1; | |
740 | } | |
741 | ||
d25797b2 | 742 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 743 | { |
8f0b1ab6 | 744 | unsigned long page_size; |
d25797b2 | 745 | int i, ret = 0; |
05da4558 | 746 | |
8f0b1ab6 | 747 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 748 | |
d25797b2 JR |
749 | for (i = PT_PAGE_TABLE_LEVEL; |
750 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
751 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
752 | ret = i; | |
753 | else | |
754 | break; | |
755 | } | |
756 | ||
4c2155ce | 757 | return ret; |
05da4558 MT |
758 | } |
759 | ||
5d163b1c XG |
760 | static struct kvm_memory_slot * |
761 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
762 | bool no_dirty_log) | |
05da4558 MT |
763 | { |
764 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
765 | |
766 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
767 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
768 | (no_dirty_log && slot->dirty_bitmap)) | |
769 | slot = NULL; | |
770 | ||
771 | return slot; | |
772 | } | |
773 | ||
774 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
775 | { | |
a0a8eaba | 776 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
777 | } |
778 | ||
779 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
780 | { | |
781 | int host_level, level, max_level; | |
05da4558 | 782 | |
d25797b2 JR |
783 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
784 | ||
785 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
786 | return host_level; | |
787 | ||
878403b7 SY |
788 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
789 | kvm_x86_ops->get_lpage_level() : host_level; | |
790 | ||
791 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
792 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
793 | break; | |
d25797b2 JR |
794 | |
795 | return level - 1; | |
05da4558 MT |
796 | } |
797 | ||
290fc38d | 798 | /* |
53c07b18 | 799 | * Pte mapping structures: |
cd4a4e53 | 800 | * |
53c07b18 | 801 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 802 | * |
53c07b18 XG |
803 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
804 | * pte_list_desc containing more mappings. | |
53a27b39 | 805 | * |
53c07b18 | 806 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
807 | * the spte was not added. |
808 | * | |
cd4a4e53 | 809 | */ |
53c07b18 XG |
810 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
811 | unsigned long *pte_list) | |
cd4a4e53 | 812 | { |
53c07b18 | 813 | struct pte_list_desc *desc; |
53a27b39 | 814 | int i, count = 0; |
cd4a4e53 | 815 | |
53c07b18 XG |
816 | if (!*pte_list) { |
817 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
818 | *pte_list = (unsigned long)spte; | |
819 | } else if (!(*pte_list & 1)) { | |
820 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
821 | desc = mmu_alloc_pte_list_desc(vcpu); | |
822 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 823 | desc->sptes[1] = spte; |
53c07b18 | 824 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 825 | ++count; |
cd4a4e53 | 826 | } else { |
53c07b18 XG |
827 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
828 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
829 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 830 | desc = desc->more; |
53c07b18 | 831 | count += PTE_LIST_EXT; |
53a27b39 | 832 | } |
53c07b18 XG |
833 | if (desc->sptes[PTE_LIST_EXT-1]) { |
834 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
835 | desc = desc->more; |
836 | } | |
d555c333 | 837 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 838 | ++count; |
d555c333 | 839 | desc->sptes[i] = spte; |
cd4a4e53 | 840 | } |
53a27b39 | 841 | return count; |
cd4a4e53 AK |
842 | } |
843 | ||
53c07b18 XG |
844 | static u64 *pte_list_next(unsigned long *pte_list, u64 *spte) |
845 | { | |
846 | struct pte_list_desc *desc; | |
847 | u64 *prev_spte; | |
848 | int i; | |
849 | ||
850 | if (!*pte_list) | |
851 | return NULL; | |
852 | else if (!(*pte_list & 1)) { | |
853 | if (!spte) | |
854 | return (u64 *)*pte_list; | |
855 | return NULL; | |
856 | } | |
857 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
858 | prev_spte = NULL; | |
859 | while (desc) { | |
860 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { | |
861 | if (prev_spte == spte) | |
862 | return desc->sptes[i]; | |
863 | prev_spte = desc->sptes[i]; | |
864 | } | |
865 | desc = desc->more; | |
866 | } | |
867 | return NULL; | |
868 | } | |
869 | ||
870 | static void | |
871 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
872 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
873 | { |
874 | int j; | |
875 | ||
53c07b18 | 876 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 877 | ; |
d555c333 AK |
878 | desc->sptes[i] = desc->sptes[j]; |
879 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
880 | if (j != 0) |
881 | return; | |
882 | if (!prev_desc && !desc->more) | |
53c07b18 | 883 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
884 | else |
885 | if (prev_desc) | |
886 | prev_desc->more = desc->more; | |
887 | else | |
53c07b18 XG |
888 | *pte_list = (unsigned long)desc->more | 1; |
889 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
890 | } |
891 | ||
53c07b18 | 892 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 893 | { |
53c07b18 XG |
894 | struct pte_list_desc *desc; |
895 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
896 | int i; |
897 | ||
53c07b18 XG |
898 | if (!*pte_list) { |
899 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 900 | BUG(); |
53c07b18 XG |
901 | } else if (!(*pte_list & 1)) { |
902 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
903 | if ((u64 *)*pte_list != spte) { | |
904 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
905 | BUG(); |
906 | } | |
53c07b18 | 907 | *pte_list = 0; |
cd4a4e53 | 908 | } else { |
53c07b18 XG |
909 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
910 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
911 | prev_desc = NULL; |
912 | while (desc) { | |
53c07b18 | 913 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 914 | if (desc->sptes[i] == spte) { |
53c07b18 | 915 | pte_list_desc_remove_entry(pte_list, |
714b93da | 916 | desc, i, |
cd4a4e53 AK |
917 | prev_desc); |
918 | return; | |
919 | } | |
920 | prev_desc = desc; | |
921 | desc = desc->more; | |
922 | } | |
53c07b18 | 923 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
924 | BUG(); |
925 | } | |
926 | } | |
927 | ||
67052b35 XG |
928 | typedef void (*pte_list_walk_fn) (u64 *spte); |
929 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
930 | { | |
931 | struct pte_list_desc *desc; | |
932 | int i; | |
933 | ||
934 | if (!*pte_list) | |
935 | return; | |
936 | ||
937 | if (!(*pte_list & 1)) | |
938 | return fn((u64 *)*pte_list); | |
939 | ||
940 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
941 | while (desc) { | |
942 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
943 | fn(desc->sptes[i]); | |
944 | desc = desc->more; | |
945 | } | |
946 | } | |
947 | ||
9373e2c0 | 948 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 949 | struct kvm_memory_slot *slot) |
53c07b18 | 950 | { |
53c07b18 XG |
951 | struct kvm_lpage_info *linfo; |
952 | ||
53c07b18 XG |
953 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
954 | return &slot->rmap[gfn - slot->base_gfn]; | |
955 | ||
956 | linfo = lpage_info_slot(gfn, slot, level); | |
53c07b18 XG |
957 | return &linfo->rmap_pde; |
958 | } | |
959 | ||
9b9b1492 TY |
960 | /* |
961 | * Take gfn and return the reverse mapping to it. | |
962 | */ | |
963 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
964 | { | |
965 | struct kvm_memory_slot *slot; | |
966 | ||
967 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 968 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
969 | } |
970 | ||
f759e2b4 XG |
971 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
972 | { | |
973 | struct kvm_mmu_memory_cache *cache; | |
974 | ||
975 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
976 | return mmu_memory_cache_free_objects(cache); | |
977 | } | |
978 | ||
53c07b18 XG |
979 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
980 | { | |
981 | struct kvm_mmu_page *sp; | |
982 | unsigned long *rmapp; | |
983 | ||
53c07b18 XG |
984 | sp = page_header(__pa(spte)); |
985 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
986 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
987 | return pte_list_add(vcpu, spte, rmapp); | |
988 | } | |
989 | ||
e4b35cc9 | 990 | static u64 *rmap_next(unsigned long *rmapp, u64 *spte) |
53c07b18 XG |
991 | { |
992 | return pte_list_next(rmapp, spte); | |
993 | } | |
994 | ||
995 | static void rmap_remove(struct kvm *kvm, u64 *spte) | |
996 | { | |
997 | struct kvm_mmu_page *sp; | |
998 | gfn_t gfn; | |
999 | unsigned long *rmapp; | |
1000 | ||
1001 | sp = page_header(__pa(spte)); | |
1002 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1003 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1004 | pte_list_remove(spte, rmapp); | |
1005 | } | |
1006 | ||
c3707958 | 1007 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1008 | { |
1df9f2dc | 1009 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1010 | rmap_remove(kvm, sptep); |
be38d276 AK |
1011 | } |
1012 | ||
a0ed4607 | 1013 | static int __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, int level) |
98348e95 | 1014 | { |
a0ed4607 TY |
1015 | u64 *spte = NULL; |
1016 | int write_protected = 0; | |
374cbac0 | 1017 | |
a0ed4607 | 1018 | while ((spte = rmap_next(rmapp, spte))) { |
374cbac0 | 1019 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 1020 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
a0ed4607 TY |
1021 | |
1022 | if (!is_writable_pte(*spte)) | |
1023 | continue; | |
1024 | ||
1025 | if (level == PT_PAGE_TABLE_LEVEL) { | |
1df9f2dc | 1026 | mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK); |
a0ed4607 TY |
1027 | } else { |
1028 | BUG_ON(!is_large_pte(*spte)); | |
1029 | drop_spte(kvm, spte); | |
1030 | --kvm->stat.lpages; | |
1031 | spte = NULL; | |
caa5b8a5 | 1032 | } |
a0ed4607 TY |
1033 | |
1034 | write_protected = 1; | |
374cbac0 | 1035 | } |
855149aa | 1036 | |
a0ed4607 TY |
1037 | return write_protected; |
1038 | } | |
1039 | ||
5dc99b23 TY |
1040 | /** |
1041 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1042 | * @kvm: kvm instance | |
1043 | * @slot: slot to protect | |
1044 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1045 | * @mask: indicates which pages we should protect | |
1046 | * | |
1047 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1048 | * logging we do not have any such mappings. | |
1049 | */ | |
1050 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1051 | struct kvm_memory_slot *slot, | |
1052 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1053 | { |
1054 | unsigned long *rmapp; | |
a0ed4607 | 1055 | |
5dc99b23 TY |
1056 | while (mask) { |
1057 | rmapp = &slot->rmap[gfn_offset + __ffs(mask)]; | |
1058 | __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL); | |
05da4558 | 1059 | |
5dc99b23 TY |
1060 | /* clear the first set bit */ |
1061 | mask &= mask - 1; | |
1062 | } | |
374cbac0 AK |
1063 | } |
1064 | ||
95d4c16c TY |
1065 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
1066 | { | |
1067 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1068 | unsigned long *rmapp; |
1069 | int i; | |
1070 | int write_protected = 0; | |
95d4c16c TY |
1071 | |
1072 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1073 | |
1074 | for (i = PT_PAGE_TABLE_LEVEL; | |
1075 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1076 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
1077 | write_protected |= __rmap_write_protect(kvm, rmapp, i); | |
1078 | } | |
1079 | ||
1080 | return write_protected; | |
95d4c16c TY |
1081 | } |
1082 | ||
8a8365c5 FD |
1083 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1084 | unsigned long data) | |
e930bffe AA |
1085 | { |
1086 | u64 *spte; | |
1087 | int need_tlb_flush = 0; | |
1088 | ||
e4b35cc9 | 1089 | while ((spte = rmap_next(rmapp, NULL))) { |
e930bffe AA |
1090 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
1091 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
c3707958 | 1092 | drop_spte(kvm, spte); |
e930bffe AA |
1093 | need_tlb_flush = 1; |
1094 | } | |
1095 | return need_tlb_flush; | |
1096 | } | |
1097 | ||
8a8365c5 FD |
1098 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1099 | unsigned long data) | |
3da0dd43 IE |
1100 | { |
1101 | int need_flush = 0; | |
e4b502ea | 1102 | u64 *spte, new_spte; |
3da0dd43 IE |
1103 | pte_t *ptep = (pte_t *)data; |
1104 | pfn_t new_pfn; | |
1105 | ||
1106 | WARN_ON(pte_huge(*ptep)); | |
1107 | new_pfn = pte_pfn(*ptep); | |
e4b35cc9 | 1108 | spte = rmap_next(rmapp, NULL); |
3da0dd43 IE |
1109 | while (spte) { |
1110 | BUG_ON(!is_shadow_present_pte(*spte)); | |
1111 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
1112 | need_flush = 1; | |
1113 | if (pte_write(*ptep)) { | |
c3707958 | 1114 | drop_spte(kvm, spte); |
e4b35cc9 | 1115 | spte = rmap_next(rmapp, NULL); |
3da0dd43 IE |
1116 | } else { |
1117 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
1118 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
1119 | ||
1120 | new_spte &= ~PT_WRITABLE_MASK; | |
1121 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1122 | new_spte &= ~shadow_accessed_mask; |
1df9f2dc XG |
1123 | mmu_spte_clear_track_bits(spte); |
1124 | mmu_spte_set(spte, new_spte); | |
e4b35cc9 | 1125 | spte = rmap_next(rmapp, spte); |
3da0dd43 IE |
1126 | } |
1127 | } | |
1128 | if (need_flush) | |
1129 | kvm_flush_remote_tlbs(kvm); | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
8a8365c5 FD |
1134 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1135 | unsigned long data, | |
3da0dd43 | 1136 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 1137 | unsigned long data)) |
e930bffe | 1138 | { |
be6ba0f0 | 1139 | int j; |
90bb6fc5 | 1140 | int ret; |
e930bffe | 1141 | int retval = 0; |
bc6678a3 | 1142 | struct kvm_memslots *slots; |
be6ba0f0 | 1143 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1144 | |
90d83dc3 | 1145 | slots = kvm_memslots(kvm); |
e930bffe | 1146 | |
be6ba0f0 | 1147 | kvm_for_each_memslot(memslot, slots) { |
e930bffe AA |
1148 | unsigned long start = memslot->userspace_addr; |
1149 | unsigned long end; | |
1150 | ||
e930bffe AA |
1151 | end = start + (memslot->npages << PAGE_SHIFT); |
1152 | if (hva >= start && hva < end) { | |
1153 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
d4dbf470 | 1154 | gfn_t gfn = memslot->base_gfn + gfn_offset; |
852e3c19 | 1155 | |
90bb6fc5 | 1156 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
1157 | |
1158 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
d4dbf470 TY |
1159 | struct kvm_lpage_info *linfo; |
1160 | ||
1161 | linfo = lpage_info_slot(gfn, memslot, | |
1162 | PT_DIRECTORY_LEVEL + j); | |
1163 | ret |= handler(kvm, &linfo->rmap_pde, data); | |
852e3c19 | 1164 | } |
90bb6fc5 AK |
1165 | trace_kvm_age_page(hva, memslot, ret); |
1166 | retval |= ret; | |
e930bffe AA |
1167 | } |
1168 | } | |
1169 | ||
1170 | return retval; | |
1171 | } | |
1172 | ||
1173 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1174 | { | |
3da0dd43 IE |
1175 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1176 | } | |
1177 | ||
1178 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
1179 | { | |
8a8365c5 | 1180 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1181 | } |
1182 | ||
8a8365c5 FD |
1183 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1184 | unsigned long data) | |
e930bffe AA |
1185 | { |
1186 | u64 *spte; | |
1187 | int young = 0; | |
1188 | ||
6316e1c8 RR |
1189 | /* |
1190 | * Emulate the accessed bit for EPT, by checking if this page has | |
1191 | * an EPT mapping, and clearing it if it does. On the next access, | |
1192 | * a new EPT mapping will be established. | |
1193 | * This has some overhead, but not as much as the cost of swapping | |
1194 | * out actively used pages or breaking up actively used hugepages. | |
1195 | */ | |
534e38b4 | 1196 | if (!shadow_accessed_mask) |
6316e1c8 | 1197 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 1198 | |
e4b35cc9 | 1199 | spte = rmap_next(rmapp, NULL); |
e930bffe AA |
1200 | while (spte) { |
1201 | int _young; | |
1202 | u64 _spte = *spte; | |
1203 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
1204 | _young = _spte & PT_ACCESSED_MASK; | |
1205 | if (_young) { | |
1206 | young = 1; | |
1207 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
1208 | } | |
e4b35cc9 | 1209 | spte = rmap_next(rmapp, spte); |
e930bffe AA |
1210 | } |
1211 | return young; | |
1212 | } | |
1213 | ||
8ee53820 AA |
1214 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
1215 | unsigned long data) | |
1216 | { | |
1217 | u64 *spte; | |
1218 | int young = 0; | |
1219 | ||
1220 | /* | |
1221 | * If there's no access bit in the secondary pte set by the | |
1222 | * hardware it's up to gup-fast/gup to set the access bit in | |
1223 | * the primary pte or in the page structure. | |
1224 | */ | |
1225 | if (!shadow_accessed_mask) | |
1226 | goto out; | |
1227 | ||
e4b35cc9 | 1228 | spte = rmap_next(rmapp, NULL); |
8ee53820 AA |
1229 | while (spte) { |
1230 | u64 _spte = *spte; | |
1231 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
1232 | young = _spte & PT_ACCESSED_MASK; | |
1233 | if (young) { | |
1234 | young = 1; | |
1235 | break; | |
1236 | } | |
e4b35cc9 | 1237 | spte = rmap_next(rmapp, spte); |
8ee53820 AA |
1238 | } |
1239 | out: | |
1240 | return young; | |
1241 | } | |
1242 | ||
53a27b39 MT |
1243 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1244 | ||
852e3c19 | 1245 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1246 | { |
1247 | unsigned long *rmapp; | |
852e3c19 JR |
1248 | struct kvm_mmu_page *sp; |
1249 | ||
1250 | sp = page_header(__pa(spte)); | |
53a27b39 | 1251 | |
852e3c19 | 1252 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1253 | |
3da0dd43 | 1254 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
1255 | kvm_flush_remote_tlbs(vcpu->kvm); |
1256 | } | |
1257 | ||
e930bffe AA |
1258 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1259 | { | |
3da0dd43 | 1260 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
1261 | } |
1262 | ||
8ee53820 AA |
1263 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1264 | { | |
1265 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1266 | } | |
1267 | ||
d6c69ee9 | 1268 | #ifdef MMU_DEBUG |
47ad8e68 | 1269 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1270 | { |
139bdb2d AK |
1271 | u64 *pos; |
1272 | u64 *end; | |
1273 | ||
47ad8e68 | 1274 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1275 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1276 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1277 | pos, *pos); |
6aa8b732 | 1278 | return 0; |
139bdb2d | 1279 | } |
6aa8b732 AK |
1280 | return 1; |
1281 | } | |
d6c69ee9 | 1282 | #endif |
6aa8b732 | 1283 | |
45221ab6 DH |
1284 | /* |
1285 | * This value is the sum of all of the kvm instances's | |
1286 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1287 | * aggregate version in order to make the slab shrinker | |
1288 | * faster | |
1289 | */ | |
1290 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1291 | { | |
1292 | kvm->arch.n_used_mmu_pages += nr; | |
1293 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1294 | } | |
1295 | ||
bd4c86ea XG |
1296 | /* |
1297 | * Remove the sp from shadow page cache, after call it, | |
1298 | * we can not find this sp from the cache, and the shadow | |
1299 | * page table is still valid. | |
1300 | * It should be under the protection of mmu lock. | |
1301 | */ | |
1302 | static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp) | |
260746c0 | 1303 | { |
4db35314 | 1304 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1305 | hlist_del(&sp->hash_link); |
2032a93d | 1306 | if (!sp->role.direct) |
842f22ed | 1307 | free_page((unsigned long)sp->gfns); |
bd4c86ea XG |
1308 | } |
1309 | ||
1310 | /* | |
1311 | * Free the shadow page table and the sp, we can do it | |
1312 | * out of the protection of mmu lock. | |
1313 | */ | |
1314 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) | |
1315 | { | |
1316 | list_del(&sp->link); | |
1317 | free_page((unsigned long)sp->spt); | |
e8ad9a70 | 1318 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1319 | } |
1320 | ||
cea0f0e7 AK |
1321 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1322 | { | |
1ae0a13d | 1323 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1324 | } |
1325 | ||
714b93da | 1326 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1327 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1328 | { |
cea0f0e7 AK |
1329 | if (!parent_pte) |
1330 | return; | |
cea0f0e7 | 1331 | |
67052b35 | 1332 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1333 | } |
1334 | ||
4db35314 | 1335 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1336 | u64 *parent_pte) |
1337 | { | |
67052b35 | 1338 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1339 | } |
1340 | ||
bcdd9a93 XG |
1341 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1342 | u64 *parent_pte) | |
1343 | { | |
1344 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1345 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1346 | } |
1347 | ||
67052b35 XG |
1348 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1349 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1350 | { |
67052b35 XG |
1351 | struct kvm_mmu_page *sp; |
1352 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, | |
1353 | sizeof *sp); | |
1354 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
1355 | if (!direct) | |
1356 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1357 | PAGE_SIZE); | |
1358 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); | |
1359 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
93a5cef0 | 1360 | bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM); |
67052b35 XG |
1361 | sp->parent_ptes = 0; |
1362 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1363 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1364 | return sp; | |
ad8cfbe3 MT |
1365 | } |
1366 | ||
67052b35 | 1367 | static void mark_unsync(u64 *spte); |
1047df1f | 1368 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1369 | { |
67052b35 | 1370 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1371 | } |
1372 | ||
67052b35 | 1373 | static void mark_unsync(u64 *spte) |
0074ff63 | 1374 | { |
67052b35 | 1375 | struct kvm_mmu_page *sp; |
1047df1f | 1376 | unsigned int index; |
0074ff63 | 1377 | |
67052b35 | 1378 | sp = page_header(__pa(spte)); |
1047df1f XG |
1379 | index = spte - sp->spt; |
1380 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1381 | return; |
1047df1f | 1382 | if (sp->unsync_children++) |
0074ff63 | 1383 | return; |
1047df1f | 1384 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1385 | } |
1386 | ||
e8bc217a | 1387 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1388 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1389 | { |
1390 | return 1; | |
1391 | } | |
1392 | ||
a7052897 MT |
1393 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1394 | { | |
1395 | } | |
1396 | ||
0f53b5b1 XG |
1397 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1398 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1399 | const void *pte) |
0f53b5b1 XG |
1400 | { |
1401 | WARN_ON(1); | |
1402 | } | |
1403 | ||
60c8aec6 MT |
1404 | #define KVM_PAGE_ARRAY_NR 16 |
1405 | ||
1406 | struct kvm_mmu_pages { | |
1407 | struct mmu_page_and_offset { | |
1408 | struct kvm_mmu_page *sp; | |
1409 | unsigned int idx; | |
1410 | } page[KVM_PAGE_ARRAY_NR]; | |
1411 | unsigned int nr; | |
1412 | }; | |
1413 | ||
cded19f3 HE |
1414 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1415 | int idx) | |
4731d4c7 | 1416 | { |
60c8aec6 | 1417 | int i; |
4731d4c7 | 1418 | |
60c8aec6 MT |
1419 | if (sp->unsync) |
1420 | for (i=0; i < pvec->nr; i++) | |
1421 | if (pvec->page[i].sp == sp) | |
1422 | return 0; | |
1423 | ||
1424 | pvec->page[pvec->nr].sp = sp; | |
1425 | pvec->page[pvec->nr].idx = idx; | |
1426 | pvec->nr++; | |
1427 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1428 | } | |
1429 | ||
1430 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1431 | struct kvm_mmu_pages *pvec) | |
1432 | { | |
1433 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1434 | |
37178b8b | 1435 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1436 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1437 | u64 ent = sp->spt[i]; |
1438 | ||
7a8f1a74 XG |
1439 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1440 | goto clear_child_bitmap; | |
1441 | ||
1442 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1443 | ||
1444 | if (child->unsync_children) { | |
1445 | if (mmu_pages_add(pvec, child, i)) | |
1446 | return -ENOSPC; | |
1447 | ||
1448 | ret = __mmu_unsync_walk(child, pvec); | |
1449 | if (!ret) | |
1450 | goto clear_child_bitmap; | |
1451 | else if (ret > 0) | |
1452 | nr_unsync_leaf += ret; | |
1453 | else | |
1454 | return ret; | |
1455 | } else if (child->unsync) { | |
1456 | nr_unsync_leaf++; | |
1457 | if (mmu_pages_add(pvec, child, i)) | |
1458 | return -ENOSPC; | |
1459 | } else | |
1460 | goto clear_child_bitmap; | |
1461 | ||
1462 | continue; | |
1463 | ||
1464 | clear_child_bitmap: | |
1465 | __clear_bit(i, sp->unsync_child_bitmap); | |
1466 | sp->unsync_children--; | |
1467 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1468 | } |
1469 | ||
4731d4c7 | 1470 | |
60c8aec6 MT |
1471 | return nr_unsync_leaf; |
1472 | } | |
1473 | ||
1474 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1475 | struct kvm_mmu_pages *pvec) | |
1476 | { | |
1477 | if (!sp->unsync_children) | |
1478 | return 0; | |
1479 | ||
1480 | mmu_pages_add(pvec, sp, 0); | |
1481 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1482 | } |
1483 | ||
4731d4c7 MT |
1484 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1485 | { | |
1486 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1487 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1488 | sp->unsync = 0; |
1489 | --kvm->stat.mmu_unsync; | |
1490 | } | |
1491 | ||
7775834a XG |
1492 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1493 | struct list_head *invalid_list); | |
1494 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1495 | struct list_head *invalid_list); | |
4731d4c7 | 1496 | |
f41d335a XG |
1497 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1498 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1499 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1500 | if ((sp)->gfn != (gfn)) {} else | |
1501 | ||
f41d335a XG |
1502 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1503 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1504 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1505 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1506 | (sp)->role.invalid) {} else | |
1507 | ||
f918b443 | 1508 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1509 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1510 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1511 | { |
5b7e0102 | 1512 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1513 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1514 | return 1; |
1515 | } | |
1516 | ||
f918b443 | 1517 | if (clear_unsync) |
1d9dc7e0 | 1518 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1519 | |
a4a8e6f7 | 1520 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1521 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1522 | return 1; |
1523 | } | |
1524 | ||
1525 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1526 | return 0; |
1527 | } | |
1528 | ||
1d9dc7e0 XG |
1529 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1530 | struct kvm_mmu_page *sp) | |
1531 | { | |
d98ba053 | 1532 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1533 | int ret; |
1534 | ||
d98ba053 | 1535 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1536 | if (ret) |
d98ba053 XG |
1537 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1538 | ||
1d9dc7e0 XG |
1539 | return ret; |
1540 | } | |
1541 | ||
e37fa785 XG |
1542 | #ifdef CONFIG_KVM_MMU_AUDIT |
1543 | #include "mmu_audit.c" | |
1544 | #else | |
1545 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1546 | static void mmu_audit_disable(void) { } | |
1547 | #endif | |
1548 | ||
d98ba053 XG |
1549 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1550 | struct list_head *invalid_list) | |
1d9dc7e0 | 1551 | { |
d98ba053 | 1552 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1553 | } |
1554 | ||
9f1a122f XG |
1555 | /* @gfn should be write-protected at the call site */ |
1556 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1557 | { | |
9f1a122f | 1558 | struct kvm_mmu_page *s; |
f41d335a | 1559 | struct hlist_node *node; |
d98ba053 | 1560 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1561 | bool flush = false; |
1562 | ||
f41d335a | 1563 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1564 | if (!s->unsync) |
9f1a122f XG |
1565 | continue; |
1566 | ||
1567 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1568 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1569 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1570 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1571 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1572 | continue; |
1573 | } | |
9f1a122f XG |
1574 | flush = true; |
1575 | } | |
1576 | ||
d98ba053 | 1577 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1578 | if (flush) |
1579 | kvm_mmu_flush_tlb(vcpu); | |
1580 | } | |
1581 | ||
60c8aec6 MT |
1582 | struct mmu_page_path { |
1583 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1584 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1585 | }; |
1586 | ||
60c8aec6 MT |
1587 | #define for_each_sp(pvec, sp, parents, i) \ |
1588 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1589 | sp = pvec.page[i].sp; \ | |
1590 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1591 | i = mmu_pages_next(&pvec, &parents, i)) | |
1592 | ||
cded19f3 HE |
1593 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1594 | struct mmu_page_path *parents, | |
1595 | int i) | |
60c8aec6 MT |
1596 | { |
1597 | int n; | |
1598 | ||
1599 | for (n = i+1; n < pvec->nr; n++) { | |
1600 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1601 | ||
1602 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1603 | parents->idx[0] = pvec->page[n].idx; | |
1604 | return n; | |
1605 | } | |
1606 | ||
1607 | parents->parent[sp->role.level-2] = sp; | |
1608 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1609 | } | |
1610 | ||
1611 | return n; | |
1612 | } | |
1613 | ||
cded19f3 | 1614 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1615 | { |
60c8aec6 MT |
1616 | struct kvm_mmu_page *sp; |
1617 | unsigned int level = 0; | |
1618 | ||
1619 | do { | |
1620 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1621 | |
60c8aec6 MT |
1622 | sp = parents->parent[level]; |
1623 | if (!sp) | |
1624 | return; | |
1625 | ||
1626 | --sp->unsync_children; | |
1627 | WARN_ON((int)sp->unsync_children < 0); | |
1628 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1629 | level++; | |
1630 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1631 | } |
1632 | ||
60c8aec6 MT |
1633 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1634 | struct mmu_page_path *parents, | |
1635 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1636 | { |
60c8aec6 MT |
1637 | parents->parent[parent->role.level-1] = NULL; |
1638 | pvec->nr = 0; | |
1639 | } | |
4731d4c7 | 1640 | |
60c8aec6 MT |
1641 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1642 | struct kvm_mmu_page *parent) | |
1643 | { | |
1644 | int i; | |
1645 | struct kvm_mmu_page *sp; | |
1646 | struct mmu_page_path parents; | |
1647 | struct kvm_mmu_pages pages; | |
d98ba053 | 1648 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1649 | |
1650 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1651 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1652 | int protected = 0; |
1653 | ||
1654 | for_each_sp(pages, sp, parents, i) | |
1655 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1656 | ||
1657 | if (protected) | |
1658 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1659 | ||
60c8aec6 | 1660 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1661 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1662 | mmu_pages_clear_parents(&parents); |
1663 | } | |
d98ba053 | 1664 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1665 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1666 | kvm_mmu_pages_init(parent, &parents, &pages); |
1667 | } | |
4731d4c7 MT |
1668 | } |
1669 | ||
c3707958 XG |
1670 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1671 | { | |
1672 | int i; | |
1673 | ||
1674 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1675 | sp->spt[i] = 0ull; | |
1676 | } | |
1677 | ||
a30f47cb XG |
1678 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1679 | { | |
1680 | sp->write_flooding_count = 0; | |
1681 | } | |
1682 | ||
1683 | static void clear_sp_write_flooding_count(u64 *spte) | |
1684 | { | |
1685 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1686 | ||
1687 | __clear_sp_write_flooding_count(sp); | |
1688 | } | |
1689 | ||
cea0f0e7 AK |
1690 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1691 | gfn_t gfn, | |
1692 | gva_t gaddr, | |
1693 | unsigned level, | |
f6e2c02b | 1694 | int direct, |
41074d07 | 1695 | unsigned access, |
f7d9c7b7 | 1696 | u64 *parent_pte) |
cea0f0e7 AK |
1697 | { |
1698 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1699 | unsigned quadrant; |
9f1a122f | 1700 | struct kvm_mmu_page *sp; |
f41d335a | 1701 | struct hlist_node *node; |
9f1a122f | 1702 | bool need_sync = false; |
cea0f0e7 | 1703 | |
a770f6f2 | 1704 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1705 | role.level = level; |
f6e2c02b | 1706 | role.direct = direct; |
84b0c8c6 | 1707 | if (role.direct) |
5b7e0102 | 1708 | role.cr4_pae = 0; |
41074d07 | 1709 | role.access = access; |
c5a78f2b JR |
1710 | if (!vcpu->arch.mmu.direct_map |
1711 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1712 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1713 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1714 | role.quadrant = quadrant; | |
1715 | } | |
f41d335a | 1716 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1717 | if (!need_sync && sp->unsync) |
1718 | need_sync = true; | |
4731d4c7 | 1719 | |
7ae680eb XG |
1720 | if (sp->role.word != role.word) |
1721 | continue; | |
4731d4c7 | 1722 | |
7ae680eb XG |
1723 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1724 | break; | |
e02aa901 | 1725 | |
7ae680eb XG |
1726 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1727 | if (sp->unsync_children) { | |
a8eeb04a | 1728 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1729 | kvm_mmu_mark_parents_unsync(sp); |
1730 | } else if (sp->unsync) | |
1731 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1732 | |
a30f47cb | 1733 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1734 | trace_kvm_mmu_get_page(sp, false); |
1735 | return sp; | |
1736 | } | |
dfc5aa00 | 1737 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1738 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1739 | if (!sp) |
1740 | return sp; | |
4db35314 AK |
1741 | sp->gfn = gfn; |
1742 | sp->role = role; | |
7ae680eb XG |
1743 | hlist_add_head(&sp->hash_link, |
1744 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1745 | if (!direct) { |
b1a36821 MT |
1746 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1747 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1748 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1749 | kvm_sync_pages(vcpu, gfn); | |
1750 | ||
4731d4c7 MT |
1751 | account_shadowed(vcpu->kvm, gfn); |
1752 | } | |
c3707958 | 1753 | init_shadow_page_table(sp); |
f691fe1d | 1754 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1755 | return sp; |
cea0f0e7 AK |
1756 | } |
1757 | ||
2d11123a AK |
1758 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1759 | struct kvm_vcpu *vcpu, u64 addr) | |
1760 | { | |
1761 | iterator->addr = addr; | |
1762 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1763 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1764 | |
1765 | if (iterator->level == PT64_ROOT_LEVEL && | |
1766 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1767 | !vcpu->arch.mmu.direct_map) | |
1768 | --iterator->level; | |
1769 | ||
2d11123a AK |
1770 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1771 | iterator->shadow_addr | |
1772 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1773 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1774 | --iterator->level; | |
1775 | if (!iterator->shadow_addr) | |
1776 | iterator->level = 0; | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1781 | { | |
1782 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1783 | return false; | |
4d88954d | 1784 | |
2d11123a AK |
1785 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1786 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1787 | return true; | |
1788 | } | |
1789 | ||
c2a2ac2b XG |
1790 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1791 | u64 spte) | |
2d11123a | 1792 | { |
c2a2ac2b | 1793 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1794 | iterator->level = 0; |
1795 | return; | |
1796 | } | |
1797 | ||
c2a2ac2b | 1798 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1799 | --iterator->level; |
1800 | } | |
1801 | ||
c2a2ac2b XG |
1802 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1803 | { | |
1804 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1805 | } | |
1806 | ||
32ef26a3 AK |
1807 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1808 | { | |
1809 | u64 spte; | |
1810 | ||
1811 | spte = __pa(sp->spt) | |
1812 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1813 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
1df9f2dc | 1814 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1815 | } |
1816 | ||
a3aa51cf AK |
1817 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1818 | { | |
1819 | if (is_large_pte(*sptep)) { | |
c3707958 | 1820 | drop_spte(vcpu->kvm, sptep); |
6addd1aa | 1821 | --vcpu->kvm->stat.lpages; |
a3aa51cf AK |
1822 | kvm_flush_remote_tlbs(vcpu->kvm); |
1823 | } | |
1824 | } | |
1825 | ||
a357bd22 AK |
1826 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1827 | unsigned direct_access) | |
1828 | { | |
1829 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1830 | struct kvm_mmu_page *child; | |
1831 | ||
1832 | /* | |
1833 | * For the direct sp, if the guest pte's dirty bit | |
1834 | * changed form clean to dirty, it will corrupt the | |
1835 | * sp's access: allow writable in the read-only sp, | |
1836 | * so we should update the spte at this point to get | |
1837 | * a new sp with the correct access. | |
1838 | */ | |
1839 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1840 | if (child->role.access == direct_access) | |
1841 | return; | |
1842 | ||
bcdd9a93 | 1843 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1844 | kvm_flush_remote_tlbs(vcpu->kvm); |
1845 | } | |
1846 | } | |
1847 | ||
505aef8f | 1848 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
1849 | u64 *spte) |
1850 | { | |
1851 | u64 pte; | |
1852 | struct kvm_mmu_page *child; | |
1853 | ||
1854 | pte = *spte; | |
1855 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 1856 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 1857 | drop_spte(kvm, spte); |
505aef8f XG |
1858 | if (is_large_pte(pte)) |
1859 | --kvm->stat.lpages; | |
1860 | } else { | |
38e3b2b2 | 1861 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 1862 | drop_parent_pte(child, spte); |
38e3b2b2 | 1863 | } |
505aef8f XG |
1864 | return true; |
1865 | } | |
1866 | ||
1867 | if (is_mmio_spte(pte)) | |
ce88decf | 1868 | mmu_spte_clear_no_track(spte); |
c3707958 | 1869 | |
505aef8f | 1870 | return false; |
38e3b2b2 XG |
1871 | } |
1872 | ||
90cb0529 | 1873 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1874 | struct kvm_mmu_page *sp) |
a436036b | 1875 | { |
697fe2e2 | 1876 | unsigned i; |
697fe2e2 | 1877 | |
38e3b2b2 XG |
1878 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
1879 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
1880 | } |
1881 | ||
4db35314 | 1882 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1883 | { |
4db35314 | 1884 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1885 | } |
1886 | ||
31aa2b44 | 1887 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1888 | { |
1889 | u64 *parent_pte; | |
1890 | ||
bcdd9a93 XG |
1891 | while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL))) |
1892 | drop_parent_pte(sp, parent_pte); | |
31aa2b44 AK |
1893 | } |
1894 | ||
60c8aec6 | 1895 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1896 | struct kvm_mmu_page *parent, |
1897 | struct list_head *invalid_list) | |
4731d4c7 | 1898 | { |
60c8aec6 MT |
1899 | int i, zapped = 0; |
1900 | struct mmu_page_path parents; | |
1901 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1902 | |
60c8aec6 | 1903 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1904 | return 0; |
60c8aec6 MT |
1905 | |
1906 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1907 | while (mmu_unsync_walk(parent, &pages)) { | |
1908 | struct kvm_mmu_page *sp; | |
1909 | ||
1910 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1911 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1912 | mmu_pages_clear_parents(&parents); |
77662e00 | 1913 | zapped++; |
60c8aec6 | 1914 | } |
60c8aec6 MT |
1915 | kvm_mmu_pages_init(parent, &parents, &pages); |
1916 | } | |
1917 | ||
1918 | return zapped; | |
4731d4c7 MT |
1919 | } |
1920 | ||
7775834a XG |
1921 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1922 | struct list_head *invalid_list) | |
31aa2b44 | 1923 | { |
4731d4c7 | 1924 | int ret; |
f691fe1d | 1925 | |
7775834a | 1926 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1927 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1928 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1929 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1930 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1931 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1932 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1933 | if (sp->unsync) |
1934 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1935 | if (!sp->root_count) { |
54a4f023 GJ |
1936 | /* Count self */ |
1937 | ret++; | |
7775834a | 1938 | list_move(&sp->link, invalid_list); |
aa6bd187 | 1939 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 1940 | } else { |
5b5c6a5a | 1941 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1942 | kvm_reload_remote_mmus(kvm); |
1943 | } | |
7775834a XG |
1944 | |
1945 | sp->role.invalid = 1; | |
4731d4c7 | 1946 | return ret; |
a436036b AK |
1947 | } |
1948 | ||
c2a2ac2b XG |
1949 | static void kvm_mmu_isolate_pages(struct list_head *invalid_list) |
1950 | { | |
1951 | struct kvm_mmu_page *sp; | |
1952 | ||
1953 | list_for_each_entry(sp, invalid_list, link) | |
1954 | kvm_mmu_isolate_page(sp); | |
1955 | } | |
1956 | ||
1957 | static void free_pages_rcu(struct rcu_head *head) | |
1958 | { | |
1959 | struct kvm_mmu_page *next, *sp; | |
1960 | ||
1961 | sp = container_of(head, struct kvm_mmu_page, rcu); | |
1962 | while (sp) { | |
1963 | if (!list_empty(&sp->link)) | |
1964 | next = list_first_entry(&sp->link, | |
1965 | struct kvm_mmu_page, link); | |
1966 | else | |
1967 | next = NULL; | |
1968 | kvm_mmu_free_page(sp); | |
1969 | sp = next; | |
1970 | } | |
1971 | } | |
1972 | ||
7775834a XG |
1973 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1974 | struct list_head *invalid_list) | |
1975 | { | |
1976 | struct kvm_mmu_page *sp; | |
1977 | ||
1978 | if (list_empty(invalid_list)) | |
1979 | return; | |
1980 | ||
1981 | kvm_flush_remote_tlbs(kvm); | |
1982 | ||
c2a2ac2b XG |
1983 | if (atomic_read(&kvm->arch.reader_counter)) { |
1984 | kvm_mmu_isolate_pages(invalid_list); | |
1985 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1986 | list_del_init(invalid_list); | |
4f022648 XG |
1987 | |
1988 | trace_kvm_mmu_delay_free_pages(sp); | |
c2a2ac2b XG |
1989 | call_rcu(&sp->rcu, free_pages_rcu); |
1990 | return; | |
1991 | } | |
1992 | ||
7775834a XG |
1993 | do { |
1994 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1995 | WARN_ON(!sp->role.invalid || sp->root_count); | |
bd4c86ea | 1996 | kvm_mmu_isolate_page(sp); |
aa6bd187 | 1997 | kvm_mmu_free_page(sp); |
7775834a XG |
1998 | } while (!list_empty(invalid_list)); |
1999 | ||
2000 | } | |
2001 | ||
82ce2c96 IE |
2002 | /* |
2003 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2004 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2005 | */ |
49d5ca26 | 2006 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2007 | { |
d98ba053 | 2008 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
2009 | /* |
2010 | * If we set the number of mmu pages to be smaller be than the | |
2011 | * number of actived pages , we must to free some mmu pages before we | |
2012 | * change the value | |
2013 | */ | |
2014 | ||
49d5ca26 DH |
2015 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
2016 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 2017 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
2018 | struct kvm_mmu_page *page; |
2019 | ||
f05e70ac | 2020 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 2021 | struct kvm_mmu_page, link); |
80b63faf | 2022 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 2023 | } |
aa6bd187 | 2024 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2025 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2026 | } |
82ce2c96 | 2027 | |
49d5ca26 | 2028 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
2029 | } |
2030 | ||
1cb3f3ae | 2031 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2032 | { |
4db35314 | 2033 | struct kvm_mmu_page *sp; |
f41d335a | 2034 | struct hlist_node *node; |
d98ba053 | 2035 | LIST_HEAD(invalid_list); |
a436036b AK |
2036 | int r; |
2037 | ||
9ad17b10 | 2038 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2039 | r = 0; |
1cb3f3ae | 2040 | spin_lock(&kvm->mmu_lock); |
f41d335a | 2041 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 2042 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2043 | sp->role.word); |
2044 | r = 1; | |
f41d335a | 2045 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2046 | } |
d98ba053 | 2047 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2048 | spin_unlock(&kvm->mmu_lock); |
2049 | ||
a436036b | 2050 | return r; |
cea0f0e7 | 2051 | } |
1cb3f3ae | 2052 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2053 | |
38c335f1 | 2054 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 2055 | { |
bc6678a3 | 2056 | int slot = memslot_id(kvm, gfn); |
4db35314 | 2057 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 2058 | |
291f26bc | 2059 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
2060 | } |
2061 | ||
74be52e3 SY |
2062 | /* |
2063 | * The function is based on mtrr_type_lookup() in | |
2064 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2065 | */ | |
2066 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2067 | u64 start, u64 end) | |
2068 | { | |
2069 | int i; | |
2070 | u64 base, mask; | |
2071 | u8 prev_match, curr_match; | |
2072 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2073 | ||
2074 | if (!mtrr_state->enabled) | |
2075 | return 0xFF; | |
2076 | ||
2077 | /* Make end inclusive end, instead of exclusive */ | |
2078 | end--; | |
2079 | ||
2080 | /* Look in fixed ranges. Just return the type as per start */ | |
2081 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2082 | int idx; | |
2083 | ||
2084 | if (start < 0x80000) { | |
2085 | idx = 0; | |
2086 | idx += (start >> 16); | |
2087 | return mtrr_state->fixed_ranges[idx]; | |
2088 | } else if (start < 0xC0000) { | |
2089 | idx = 1 * 8; | |
2090 | idx += ((start - 0x80000) >> 14); | |
2091 | return mtrr_state->fixed_ranges[idx]; | |
2092 | } else if (start < 0x1000000) { | |
2093 | idx = 3 * 8; | |
2094 | idx += ((start - 0xC0000) >> 12); | |
2095 | return mtrr_state->fixed_ranges[idx]; | |
2096 | } | |
2097 | } | |
2098 | ||
2099 | /* | |
2100 | * Look in variable ranges | |
2101 | * Look of multiple ranges matching this address and pick type | |
2102 | * as per MTRR precedence | |
2103 | */ | |
2104 | if (!(mtrr_state->enabled & 2)) | |
2105 | return mtrr_state->def_type; | |
2106 | ||
2107 | prev_match = 0xFF; | |
2108 | for (i = 0; i < num_var_ranges; ++i) { | |
2109 | unsigned short start_state, end_state; | |
2110 | ||
2111 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2112 | continue; | |
2113 | ||
2114 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2115 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2116 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2117 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2118 | ||
2119 | start_state = ((start & mask) == (base & mask)); | |
2120 | end_state = ((end & mask) == (base & mask)); | |
2121 | if (start_state != end_state) | |
2122 | return 0xFE; | |
2123 | ||
2124 | if ((start & mask) != (base & mask)) | |
2125 | continue; | |
2126 | ||
2127 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2128 | if (prev_match == 0xFF) { | |
2129 | prev_match = curr_match; | |
2130 | continue; | |
2131 | } | |
2132 | ||
2133 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2134 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2135 | return MTRR_TYPE_UNCACHABLE; | |
2136 | ||
2137 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2138 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2139 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2140 | curr_match == MTRR_TYPE_WRBACK)) { | |
2141 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2142 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2143 | } | |
2144 | ||
2145 | if (prev_match != curr_match) | |
2146 | return MTRR_TYPE_UNCACHABLE; | |
2147 | } | |
2148 | ||
2149 | if (prev_match != 0xFF) | |
2150 | return prev_match; | |
2151 | ||
2152 | return mtrr_state->def_type; | |
2153 | } | |
2154 | ||
4b12f0de | 2155 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2156 | { |
2157 | u8 mtrr; | |
2158 | ||
2159 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2160 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2161 | if (mtrr == 0xfe || mtrr == 0xff) | |
2162 | mtrr = MTRR_TYPE_WRBACK; | |
2163 | return mtrr; | |
2164 | } | |
4b12f0de | 2165 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2166 | |
9cf5cf5a XG |
2167 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2168 | { | |
2169 | trace_kvm_mmu_unsync_page(sp); | |
2170 | ++vcpu->kvm->stat.mmu_unsync; | |
2171 | sp->unsync = 1; | |
2172 | ||
2173 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2174 | } |
2175 | ||
2176 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2177 | { |
4731d4c7 | 2178 | struct kvm_mmu_page *s; |
f41d335a | 2179 | struct hlist_node *node; |
9cf5cf5a | 2180 | |
f41d335a | 2181 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 2182 | if (s->unsync) |
4731d4c7 | 2183 | continue; |
9cf5cf5a XG |
2184 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2185 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2186 | } |
4731d4c7 MT |
2187 | } |
2188 | ||
2189 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2190 | bool can_unsync) | |
2191 | { | |
9cf5cf5a | 2192 | struct kvm_mmu_page *s; |
f41d335a | 2193 | struct hlist_node *node; |
9cf5cf5a XG |
2194 | bool need_unsync = false; |
2195 | ||
f41d335a | 2196 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
2197 | if (!can_unsync) |
2198 | return 1; | |
2199 | ||
9cf5cf5a | 2200 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2201 | return 1; |
9cf5cf5a XG |
2202 | |
2203 | if (!need_unsync && !s->unsync) { | |
9cf5cf5a XG |
2204 | need_unsync = true; |
2205 | } | |
4731d4c7 | 2206 | } |
9cf5cf5a XG |
2207 | if (need_unsync) |
2208 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2209 | return 0; |
2210 | } | |
2211 | ||
d555c333 | 2212 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2213 | unsigned pte_access, int user_fault, |
640d9b0d | 2214 | int write_fault, int level, |
c2d0ee46 | 2215 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2216 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2217 | { |
b330aa0c | 2218 | u64 spte, entry = *sptep; |
1e73f9dd | 2219 | int ret = 0; |
64d4d521 | 2220 | |
ce88decf XG |
2221 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2222 | return 0; | |
2223 | ||
982c2565 | 2224 | spte = PT_PRESENT_MASK; |
947da538 | 2225 | if (!speculative) |
3201b5d9 | 2226 | spte |= shadow_accessed_mask; |
640d9b0d | 2227 | |
7b52345e SY |
2228 | if (pte_access & ACC_EXEC_MASK) |
2229 | spte |= shadow_x_mask; | |
2230 | else | |
2231 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 2232 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2233 | spte |= shadow_user_mask; |
852e3c19 | 2234 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2235 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2236 | if (tdp_enabled) |
4b12f0de SY |
2237 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2238 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2239 | |
9bdbba13 | 2240 | if (host_writable) |
1403283a | 2241 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2242 | else |
2243 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2244 | |
35149e21 | 2245 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
2246 | |
2247 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
2248 | || (!vcpu->arch.mmu.direct_map && write_fault |
2249 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2250 | |
852e3c19 JR |
2251 | if (level > PT_PAGE_TABLE_LEVEL && |
2252 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2253 | ret = 1; |
c3707958 | 2254 | drop_spte(vcpu->kvm, sptep); |
be38d276 | 2255 | goto done; |
38187c83 MT |
2256 | } |
2257 | ||
1c4f1fd6 | 2258 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2259 | |
c5a78f2b | 2260 | if (!vcpu->arch.mmu.direct_map |
411c588d | 2261 | && !(pte_access & ACC_WRITE_MASK)) { |
69325a12 | 2262 | spte &= ~PT_USER_MASK; |
411c588d AK |
2263 | /* |
2264 | * If we converted a user page to a kernel page, | |
2265 | * so that the kernel can write to it when cr0.wp=0, | |
2266 | * then we should prevent the kernel from executing it | |
2267 | * if SMEP is enabled. | |
2268 | */ | |
2269 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
2270 | spte |= PT64_NX_MASK; | |
2271 | } | |
69325a12 | 2272 | |
ecc5589f MT |
2273 | /* |
2274 | * Optimization: for pte sync, if spte was writable the hash | |
2275 | * lookup is unnecessary (and expensive). Write protection | |
2276 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2277 | * Same reasoning can be applied to dirty page accounting. | |
2278 | */ | |
8dae4445 | 2279 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2280 | goto set_pte; |
2281 | ||
4731d4c7 | 2282 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2283 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2284 | __func__, gfn); |
1e73f9dd | 2285 | ret = 1; |
1c4f1fd6 | 2286 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2287 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2288 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2289 | } |
2290 | } | |
2291 | ||
1c4f1fd6 AK |
2292 | if (pte_access & ACC_WRITE_MASK) |
2293 | mark_page_dirty(vcpu->kvm, gfn); | |
2294 | ||
38187c83 | 2295 | set_pte: |
1df9f2dc | 2296 | mmu_spte_update(sptep, spte); |
b330aa0c XG |
2297 | /* |
2298 | * If we overwrite a writable spte with a read-only one we | |
2299 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2300 | * will find a read-only spte, even though the writable spte | |
2301 | * might be cached on a CPU's TLB. | |
2302 | */ | |
2303 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2304 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2305 | done: |
1e73f9dd MT |
2306 | return ret; |
2307 | } | |
2308 | ||
d555c333 | 2309 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2310 | unsigned pt_access, unsigned pte_access, |
640d9b0d | 2311 | int user_fault, int write_fault, |
b90a0e6c | 2312 | int *emulate, int level, gfn_t gfn, |
1403283a | 2313 | pfn_t pfn, bool speculative, |
9bdbba13 | 2314 | bool host_writable) |
1e73f9dd MT |
2315 | { |
2316 | int was_rmapped = 0; | |
53a27b39 | 2317 | int rmap_count; |
1e73f9dd MT |
2318 | |
2319 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2320 | " user_fault %d gfn %llx\n", |
d555c333 | 2321 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2322 | write_fault, user_fault, gfn); |
2323 | ||
d555c333 | 2324 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2325 | /* |
2326 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2327 | * the parent of the now unreachable PTE. | |
2328 | */ | |
852e3c19 JR |
2329 | if (level > PT_PAGE_TABLE_LEVEL && |
2330 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2331 | struct kvm_mmu_page *child; |
d555c333 | 2332 | u64 pte = *sptep; |
1e73f9dd MT |
2333 | |
2334 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2335 | drop_parent_pte(child, sptep); |
3be2264b | 2336 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2337 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2338 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2339 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2340 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2341 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2342 | } else |
2343 | was_rmapped = 1; | |
1e73f9dd | 2344 | } |
852e3c19 | 2345 | |
d555c333 | 2346 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
640d9b0d | 2347 | level, gfn, pfn, speculative, true, |
9bdbba13 | 2348 | host_writable)) { |
1e73f9dd | 2349 | if (write_fault) |
b90a0e6c | 2350 | *emulate = 1; |
5304efde | 2351 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2352 | } |
1e73f9dd | 2353 | |
ce88decf XG |
2354 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2355 | *emulate = 1; | |
2356 | ||
d555c333 | 2357 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2358 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2359 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2360 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2361 | *sptep, sptep); | |
d555c333 | 2362 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2363 | ++vcpu->kvm->stat.lpages; |
2364 | ||
ffb61bb3 XG |
2365 | if (is_shadow_present_pte(*sptep)) { |
2366 | page_header_update_slot(vcpu->kvm, sptep, gfn); | |
2367 | if (!was_rmapped) { | |
2368 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2369 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2370 | rmap_recycle(vcpu, sptep, gfn); | |
2371 | } | |
1c4f1fd6 | 2372 | } |
9ed5520d | 2373 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2374 | } |
2375 | ||
6aa8b732 AK |
2376 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2377 | { | |
2378 | } | |
2379 | ||
957ed9ef XG |
2380 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2381 | bool no_dirty_log) | |
2382 | { | |
2383 | struct kvm_memory_slot *slot; | |
2384 | unsigned long hva; | |
2385 | ||
5d163b1c | 2386 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
957ed9ef | 2387 | if (!slot) { |
fce92dce XG |
2388 | get_page(fault_page); |
2389 | return page_to_pfn(fault_page); | |
957ed9ef XG |
2390 | } |
2391 | ||
2392 | hva = gfn_to_hva_memslot(slot, gfn); | |
2393 | ||
2394 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2395 | } | |
2396 | ||
2397 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2398 | struct kvm_mmu_page *sp, | |
2399 | u64 *start, u64 *end) | |
2400 | { | |
2401 | struct page *pages[PTE_PREFETCH_NUM]; | |
2402 | unsigned access = sp->role.access; | |
2403 | int i, ret; | |
2404 | gfn_t gfn; | |
2405 | ||
2406 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2407 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2408 | return -1; |
2409 | ||
2410 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2411 | if (ret <= 0) | |
2412 | return -1; | |
2413 | ||
2414 | for (i = 0; i < ret; i++, gfn++, start++) | |
2415 | mmu_set_spte(vcpu, start, ACC_ALL, | |
640d9b0d | 2416 | access, 0, 0, NULL, |
957ed9ef XG |
2417 | sp->role.level, gfn, |
2418 | page_to_pfn(pages[i]), true, true); | |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
2423 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2424 | struct kvm_mmu_page *sp, u64 *sptep) | |
2425 | { | |
2426 | u64 *spte, *start = NULL; | |
2427 | int i; | |
2428 | ||
2429 | WARN_ON(!sp->role.direct); | |
2430 | ||
2431 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2432 | spte = sp->spt + i; | |
2433 | ||
2434 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2435 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2436 | if (!start) |
2437 | continue; | |
2438 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2439 | break; | |
2440 | start = NULL; | |
2441 | } else if (!start) | |
2442 | start = spte; | |
2443 | } | |
2444 | } | |
2445 | ||
2446 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2447 | { | |
2448 | struct kvm_mmu_page *sp; | |
2449 | ||
2450 | /* | |
2451 | * Since it's no accessed bit on EPT, it's no way to | |
2452 | * distinguish between actually accessed translations | |
2453 | * and prefetched, so disable pte prefetch if EPT is | |
2454 | * enabled. | |
2455 | */ | |
2456 | if (!shadow_accessed_mask) | |
2457 | return; | |
2458 | ||
2459 | sp = page_header(__pa(sptep)); | |
2460 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2461 | return; | |
2462 | ||
2463 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2464 | } | |
2465 | ||
9f652d21 | 2466 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2467 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2468 | bool prefault) | |
140754bc | 2469 | { |
9f652d21 | 2470 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2471 | struct kvm_mmu_page *sp; |
b90a0e6c | 2472 | int emulate = 0; |
140754bc | 2473 | gfn_t pseudo_gfn; |
6aa8b732 | 2474 | |
9f652d21 | 2475 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2476 | if (iterator.level == level) { |
612819c3 MT |
2477 | unsigned pte_access = ACC_ALL; |
2478 | ||
612819c3 | 2479 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
b90a0e6c | 2480 | 0, write, &emulate, |
2ec4739d | 2481 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2482 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2483 | ++vcpu->stat.pf_fixed; |
2484 | break; | |
6aa8b732 AK |
2485 | } |
2486 | ||
c3707958 | 2487 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2488 | u64 base_addr = iterator.addr; |
2489 | ||
2490 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2491 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2492 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2493 | iterator.level - 1, | |
2494 | 1, ACC_ALL, iterator.sptep); | |
2495 | if (!sp) { | |
2496 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2497 | kvm_release_pfn_clean(pfn); | |
2498 | return -ENOMEM; | |
2499 | } | |
140754bc | 2500 | |
1df9f2dc XG |
2501 | mmu_spte_set(iterator.sptep, |
2502 | __pa(sp->spt) | |
2503 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2504 | | shadow_user_mask | shadow_x_mask | |
2505 | | shadow_accessed_mask); | |
9f652d21 AK |
2506 | } |
2507 | } | |
b90a0e6c | 2508 | return emulate; |
6aa8b732 AK |
2509 | } |
2510 | ||
77db5cbd | 2511 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2512 | { |
77db5cbd HY |
2513 | siginfo_t info; |
2514 | ||
2515 | info.si_signo = SIGBUS; | |
2516 | info.si_errno = 0; | |
2517 | info.si_code = BUS_MCEERR_AR; | |
2518 | info.si_addr = (void __user *)address; | |
2519 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2520 | |
77db5cbd | 2521 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2522 | } |
2523 | ||
d7c55201 | 2524 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 HY |
2525 | { |
2526 | kvm_release_pfn_clean(pfn); | |
2527 | if (is_hwpoison_pfn(pfn)) { | |
bebb106a | 2528 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2529 | return 0; |
d7c55201 | 2530 | } |
edba23e5 | 2531 | |
d7c55201 | 2532 | return -EFAULT; |
bf998156 HY |
2533 | } |
2534 | ||
936a5fe6 AA |
2535 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2536 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2537 | { | |
2538 | pfn_t pfn = *pfnp; | |
2539 | gfn_t gfn = *gfnp; | |
2540 | int level = *levelp; | |
2541 | ||
2542 | /* | |
2543 | * Check if it's a transparent hugepage. If this would be an | |
2544 | * hugetlbfs page, level wouldn't be set to | |
2545 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2546 | * here. | |
2547 | */ | |
2548 | if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && | |
2549 | level == PT_PAGE_TABLE_LEVEL && | |
2550 | PageTransCompound(pfn_to_page(pfn)) && | |
2551 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2552 | unsigned long mask; | |
2553 | /* | |
2554 | * mmu_notifier_retry was successful and we hold the | |
2555 | * mmu_lock here, so the pmd can't become splitting | |
2556 | * from under us, and in turn | |
2557 | * __split_huge_page_refcount() can't run from under | |
2558 | * us and we can safely transfer the refcount from | |
2559 | * PG_tail to PG_head as we switch the pfn to tail to | |
2560 | * head. | |
2561 | */ | |
2562 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2563 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2564 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2565 | if (pfn & mask) { | |
2566 | gfn &= ~mask; | |
2567 | *gfnp = gfn; | |
2568 | kvm_release_pfn_clean(pfn); | |
2569 | pfn &= ~mask; | |
2570 | if (!get_page_unless_zero(pfn_to_page(pfn))) | |
2571 | BUG(); | |
2572 | *pfnp = pfn; | |
2573 | } | |
2574 | } | |
2575 | } | |
2576 | ||
d7c55201 XG |
2577 | static bool mmu_invalid_pfn(pfn_t pfn) |
2578 | { | |
ce88decf | 2579 | return unlikely(is_invalid_pfn(pfn)); |
d7c55201 XG |
2580 | } |
2581 | ||
2582 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, | |
2583 | pfn_t pfn, unsigned access, int *ret_val) | |
2584 | { | |
2585 | bool ret = true; | |
2586 | ||
2587 | /* The pfn is invalid, report the error! */ | |
2588 | if (unlikely(is_invalid_pfn(pfn))) { | |
2589 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); | |
2590 | goto exit; | |
2591 | } | |
2592 | ||
ce88decf | 2593 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2594 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2595 | |
2596 | ret = false; | |
2597 | exit: | |
2598 | return ret; | |
2599 | } | |
2600 | ||
78b2c54a | 2601 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2602 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2603 | ||
2604 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2605 | bool prefault) |
10589a46 MT |
2606 | { |
2607 | int r; | |
852e3c19 | 2608 | int level; |
936a5fe6 | 2609 | int force_pt_level; |
35149e21 | 2610 | pfn_t pfn; |
e930bffe | 2611 | unsigned long mmu_seq; |
612819c3 | 2612 | bool map_writable; |
aaee2c94 | 2613 | |
936a5fe6 AA |
2614 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2615 | if (likely(!force_pt_level)) { | |
2616 | level = mapping_level(vcpu, gfn); | |
2617 | /* | |
2618 | * This path builds a PAE pagetable - so we can map | |
2619 | * 2mb pages at maximum. Therefore check if the level | |
2620 | * is larger than that. | |
2621 | */ | |
2622 | if (level > PT_DIRECTORY_LEVEL) | |
2623 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2624 | |
936a5fe6 AA |
2625 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2626 | } else | |
2627 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2628 | |
e930bffe | 2629 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2630 | smp_rmb(); |
060c2abe | 2631 | |
78b2c54a | 2632 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2633 | return 0; |
aaee2c94 | 2634 | |
d7c55201 XG |
2635 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2636 | return r; | |
d196e343 | 2637 | |
aaee2c94 | 2638 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2639 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2640 | goto out_unlock; | |
eb787d10 | 2641 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2642 | if (likely(!force_pt_level)) |
2643 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2644 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2645 | prefault); | |
aaee2c94 MT |
2646 | spin_unlock(&vcpu->kvm->mmu_lock); |
2647 | ||
aaee2c94 | 2648 | |
10589a46 | 2649 | return r; |
e930bffe AA |
2650 | |
2651 | out_unlock: | |
2652 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2653 | kvm_release_pfn_clean(pfn); | |
2654 | return 0; | |
10589a46 MT |
2655 | } |
2656 | ||
2657 | ||
17ac10ad AK |
2658 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2659 | { | |
2660 | int i; | |
4db35314 | 2661 | struct kvm_mmu_page *sp; |
d98ba053 | 2662 | LIST_HEAD(invalid_list); |
17ac10ad | 2663 | |
ad312c7c | 2664 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2665 | return; |
aaee2c94 | 2666 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2667 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2668 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2669 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2670 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2671 | |
4db35314 AK |
2672 | sp = page_header(root); |
2673 | --sp->root_count; | |
d98ba053 XG |
2674 | if (!sp->root_count && sp->role.invalid) { |
2675 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2676 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2677 | } | |
ad312c7c | 2678 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2679 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2680 | return; |
2681 | } | |
17ac10ad | 2682 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2683 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2684 | |
417726a3 | 2685 | if (root) { |
417726a3 | 2686 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2687 | sp = page_header(root); |
2688 | --sp->root_count; | |
2e53d63a | 2689 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2690 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2691 | &invalid_list); | |
417726a3 | 2692 | } |
ad312c7c | 2693 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2694 | } |
d98ba053 | 2695 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2696 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2697 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2698 | } |
2699 | ||
8986ecc0 MT |
2700 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2701 | { | |
2702 | int ret = 0; | |
2703 | ||
2704 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2705 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2706 | ret = 1; |
2707 | } | |
2708 | ||
2709 | return ret; | |
2710 | } | |
2711 | ||
651dd37a JR |
2712 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2713 | { | |
2714 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2715 | unsigned i; |
651dd37a JR |
2716 | |
2717 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2718 | spin_lock(&vcpu->kvm->mmu_lock); | |
2719 | kvm_mmu_free_some_pages(vcpu); | |
2720 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2721 | 1, ACC_ALL, NULL); | |
2722 | ++sp->root_count; | |
2723 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2724 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2725 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2726 | for (i = 0; i < 4; ++i) { | |
2727 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2728 | ||
2729 | ASSERT(!VALID_PAGE(root)); | |
2730 | spin_lock(&vcpu->kvm->mmu_lock); | |
2731 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2732 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2733 | i << 30, | |
651dd37a JR |
2734 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2735 | NULL); | |
2736 | root = __pa(sp->spt); | |
2737 | ++sp->root_count; | |
2738 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2739 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2740 | } |
6292757f | 2741 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2742 | } else |
2743 | BUG(); | |
2744 | ||
2745 | return 0; | |
2746 | } | |
2747 | ||
2748 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2749 | { |
4db35314 | 2750 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2751 | u64 pdptr, pm_mask; |
2752 | gfn_t root_gfn; | |
2753 | int i; | |
3bb65a22 | 2754 | |
5777ed34 | 2755 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2756 | |
651dd37a JR |
2757 | if (mmu_check_root(vcpu, root_gfn)) |
2758 | return 1; | |
2759 | ||
2760 | /* | |
2761 | * Do we shadow a long mode page table? If so we need to | |
2762 | * write-protect the guests page table root. | |
2763 | */ | |
2764 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2765 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2766 | |
2767 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2768 | |
8facbbff | 2769 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2770 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2771 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2772 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2773 | root = __pa(sp->spt); |
2774 | ++sp->root_count; | |
8facbbff | 2775 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2776 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2777 | return 0; |
17ac10ad | 2778 | } |
f87f9288 | 2779 | |
651dd37a JR |
2780 | /* |
2781 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2782 | * or a PAE 3-level page table. In either case we need to be aware that |
2783 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2784 | */ |
81407ca5 JR |
2785 | pm_mask = PT_PRESENT_MASK; |
2786 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2787 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2788 | ||
17ac10ad | 2789 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2790 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2791 | |
2792 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2793 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 2794 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 2795 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2796 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2797 | continue; |
2798 | } | |
6de4f3ad | 2799 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2800 | if (mmu_check_root(vcpu, root_gfn)) |
2801 | return 1; | |
5a7388c2 | 2802 | } |
8facbbff | 2803 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2804 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2805 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2806 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2807 | ACC_ALL, NULL); |
4db35314 AK |
2808 | root = __pa(sp->spt); |
2809 | ++sp->root_count; | |
8facbbff AK |
2810 | spin_unlock(&vcpu->kvm->mmu_lock); |
2811 | ||
81407ca5 | 2812 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2813 | } |
6292757f | 2814 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2815 | |
2816 | /* | |
2817 | * If we shadow a 32 bit page table with a long mode page | |
2818 | * table we enter this path. | |
2819 | */ | |
2820 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2821 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2822 | /* | |
2823 | * The additional page necessary for this is only | |
2824 | * allocated on demand. | |
2825 | */ | |
2826 | ||
2827 | u64 *lm_root; | |
2828 | ||
2829 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2830 | if (lm_root == NULL) | |
2831 | return 1; | |
2832 | ||
2833 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2834 | ||
2835 | vcpu->arch.mmu.lm_root = lm_root; | |
2836 | } | |
2837 | ||
2838 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2839 | } | |
2840 | ||
8986ecc0 | 2841 | return 0; |
17ac10ad AK |
2842 | } |
2843 | ||
651dd37a JR |
2844 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2845 | { | |
2846 | if (vcpu->arch.mmu.direct_map) | |
2847 | return mmu_alloc_direct_roots(vcpu); | |
2848 | else | |
2849 | return mmu_alloc_shadow_roots(vcpu); | |
2850 | } | |
2851 | ||
0ba73cda MT |
2852 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2853 | { | |
2854 | int i; | |
2855 | struct kvm_mmu_page *sp; | |
2856 | ||
81407ca5 JR |
2857 | if (vcpu->arch.mmu.direct_map) |
2858 | return; | |
2859 | ||
0ba73cda MT |
2860 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2861 | return; | |
6903074c | 2862 | |
bebb106a | 2863 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 2864 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 2865 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2866 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2867 | sp = page_header(root); | |
2868 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 2869 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2870 | return; |
2871 | } | |
2872 | for (i = 0; i < 4; ++i) { | |
2873 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2874 | ||
8986ecc0 | 2875 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2876 | root &= PT64_BASE_ADDR_MASK; |
2877 | sp = page_header(root); | |
2878 | mmu_sync_children(vcpu, sp); | |
2879 | } | |
2880 | } | |
0375f7fa | 2881 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2882 | } |
2883 | ||
2884 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2885 | { | |
2886 | spin_lock(&vcpu->kvm->mmu_lock); | |
2887 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2888 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2889 | } |
2890 | ||
1871c602 | 2891 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2892 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2893 | { |
ab9ae313 AK |
2894 | if (exception) |
2895 | exception->error_code = 0; | |
6aa8b732 AK |
2896 | return vaddr; |
2897 | } | |
2898 | ||
6539e738 | 2899 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2900 | u32 access, |
2901 | struct x86_exception *exception) | |
6539e738 | 2902 | { |
ab9ae313 AK |
2903 | if (exception) |
2904 | exception->error_code = 0; | |
6539e738 JR |
2905 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2906 | } | |
2907 | ||
ce88decf XG |
2908 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
2909 | { | |
2910 | if (direct) | |
2911 | return vcpu_match_mmio_gpa(vcpu, addr); | |
2912 | ||
2913 | return vcpu_match_mmio_gva(vcpu, addr); | |
2914 | } | |
2915 | ||
2916 | ||
2917 | /* | |
2918 | * On direct hosts, the last spte is only allows two states | |
2919 | * for mmio page fault: | |
2920 | * - It is the mmio spte | |
2921 | * - It is zapped or it is being zapped. | |
2922 | * | |
2923 | * This function completely checks the spte when the last spte | |
2924 | * is not the mmio spte. | |
2925 | */ | |
2926 | static bool check_direct_spte_mmio_pf(u64 spte) | |
2927 | { | |
2928 | return __check_direct_spte_mmio_pf(spte); | |
2929 | } | |
2930 | ||
2931 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
2932 | { | |
2933 | struct kvm_shadow_walk_iterator iterator; | |
2934 | u64 spte = 0ull; | |
2935 | ||
2936 | walk_shadow_page_lockless_begin(vcpu); | |
2937 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
2938 | if (!is_shadow_present_pte(spte)) | |
2939 | break; | |
2940 | walk_shadow_page_lockless_end(vcpu); | |
2941 | ||
2942 | return spte; | |
2943 | } | |
2944 | ||
2945 | /* | |
2946 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
2947 | * directly, return 0 to let CPU fault again on the address, -1 is | |
2948 | * returned if bug is detected. | |
2949 | */ | |
2950 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
2951 | { | |
2952 | u64 spte; | |
2953 | ||
2954 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
2955 | return 1; | |
2956 | ||
2957 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
2958 | ||
2959 | if (is_mmio_spte(spte)) { | |
2960 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
2961 | unsigned access = get_mmio_spte_access(spte); | |
2962 | ||
2963 | if (direct) | |
2964 | addr = 0; | |
4f022648 XG |
2965 | |
2966 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
2967 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
2968 | return 1; | |
2969 | } | |
2970 | ||
2971 | /* | |
2972 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
2973 | * it's a BUG if the gfn is not a mmio page. | |
2974 | */ | |
2975 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
2976 | return -1; | |
2977 | ||
2978 | /* | |
2979 | * If the page table is zapped by other cpus, let CPU fault again on | |
2980 | * the address. | |
2981 | */ | |
2982 | return 0; | |
2983 | } | |
2984 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
2985 | ||
2986 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
2987 | u32 error_code, bool direct) | |
2988 | { | |
2989 | int ret; | |
2990 | ||
2991 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
2992 | WARN_ON(ret < 0); | |
2993 | return ret; | |
2994 | } | |
2995 | ||
6aa8b732 | 2996 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2997 | u32 error_code, bool prefault) |
6aa8b732 | 2998 | { |
e833240f | 2999 | gfn_t gfn; |
e2dec939 | 3000 | int r; |
6aa8b732 | 3001 | |
b8688d51 | 3002 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3003 | |
3004 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3005 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3006 | ||
e2dec939 AK |
3007 | r = mmu_topup_memory_caches(vcpu); |
3008 | if (r) | |
3009 | return r; | |
714b93da | 3010 | |
6aa8b732 | 3011 | ASSERT(vcpu); |
ad312c7c | 3012 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3013 | |
e833240f | 3014 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3015 | |
e833240f | 3016 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 3017 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
3018 | } |
3019 | ||
7e1fbeac | 3020 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3021 | { |
3022 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3023 | |
7c90705b | 3024 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3025 | arch.gfn = gfn; |
c4806acd | 3026 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3027 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3028 | |
3029 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3030 | } | |
3031 | ||
3032 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3033 | { | |
3034 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3035 | kvm_event_needs_reinjection(vcpu))) | |
3036 | return false; | |
3037 | ||
3038 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3039 | } | |
3040 | ||
78b2c54a | 3041 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3042 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3043 | { |
3044 | bool async; | |
3045 | ||
612819c3 | 3046 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3047 | |
3048 | if (!async) | |
3049 | return false; /* *pfn has correct page already */ | |
3050 | ||
3051 | put_page(pfn_to_page(*pfn)); | |
3052 | ||
78b2c54a | 3053 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3054 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3055 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3056 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3057 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3058 | return true; | |
3059 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3060 | return true; | |
3061 | } | |
3062 | ||
612819c3 | 3063 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3064 | |
3065 | return false; | |
3066 | } | |
3067 | ||
56028d08 | 3068 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3069 | bool prefault) |
fb72d167 | 3070 | { |
35149e21 | 3071 | pfn_t pfn; |
fb72d167 | 3072 | int r; |
852e3c19 | 3073 | int level; |
936a5fe6 | 3074 | int force_pt_level; |
05da4558 | 3075 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3076 | unsigned long mmu_seq; |
612819c3 MT |
3077 | int write = error_code & PFERR_WRITE_MASK; |
3078 | bool map_writable; | |
fb72d167 JR |
3079 | |
3080 | ASSERT(vcpu); | |
3081 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3082 | ||
ce88decf XG |
3083 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3084 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3085 | ||
fb72d167 JR |
3086 | r = mmu_topup_memory_caches(vcpu); |
3087 | if (r) | |
3088 | return r; | |
3089 | ||
936a5fe6 AA |
3090 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3091 | if (likely(!force_pt_level)) { | |
3092 | level = mapping_level(vcpu, gfn); | |
3093 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3094 | } else | |
3095 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3096 | |
e930bffe | 3097 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3098 | smp_rmb(); |
af585b92 | 3099 | |
78b2c54a | 3100 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3101 | return 0; |
3102 | ||
d7c55201 XG |
3103 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3104 | return r; | |
3105 | ||
fb72d167 | 3106 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
3107 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
3108 | goto out_unlock; | |
fb72d167 | 3109 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
3110 | if (likely(!force_pt_level)) |
3111 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3112 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3113 | level, gfn, pfn, prefault); |
fb72d167 | 3114 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3115 | |
3116 | return r; | |
e930bffe AA |
3117 | |
3118 | out_unlock: | |
3119 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3120 | kvm_release_pfn_clean(pfn); | |
3121 | return 0; | |
fb72d167 JR |
3122 | } |
3123 | ||
6aa8b732 AK |
3124 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3125 | { | |
17ac10ad | 3126 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3127 | } |
3128 | ||
52fde8df JR |
3129 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3130 | struct kvm_mmu *context) | |
6aa8b732 | 3131 | { |
6aa8b732 AK |
3132 | context->new_cr3 = nonpaging_new_cr3; |
3133 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3134 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3135 | context->free = nonpaging_free; | |
e8bc217a | 3136 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3137 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3138 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3139 | context->root_level = 0; |
6aa8b732 | 3140 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3141 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3142 | context->direct_map = true; |
2d48a985 | 3143 | context->nx = false; |
6aa8b732 AK |
3144 | return 0; |
3145 | } | |
3146 | ||
d835dfec | 3147 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3148 | { |
1165f5fe | 3149 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3150 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3151 | } |
3152 | ||
3153 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3154 | { | |
9f8fe504 | 3155 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3156 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3157 | } |
3158 | ||
5777ed34 JR |
3159 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3160 | { | |
9f8fe504 | 3161 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3162 | } |
3163 | ||
6389ee94 AK |
3164 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3165 | struct x86_exception *fault) | |
6aa8b732 | 3166 | { |
6389ee94 | 3167 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3168 | } |
3169 | ||
6aa8b732 AK |
3170 | static void paging_free(struct kvm_vcpu *vcpu) |
3171 | { | |
3172 | nonpaging_free(vcpu); | |
3173 | } | |
3174 | ||
3241f22d | 3175 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
3176 | { |
3177 | int bit7; | |
3178 | ||
3179 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 3180 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
3181 | } |
3182 | ||
ce88decf XG |
3183 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3184 | int *nr_present) | |
3185 | { | |
3186 | if (unlikely(is_mmio_spte(*sptep))) { | |
3187 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3188 | mmu_spte_clear_no_track(sptep); | |
3189 | return true; | |
3190 | } | |
3191 | ||
3192 | (*nr_present)++; | |
3193 | mark_mmio_spte(sptep, gfn, access); | |
3194 | return true; | |
3195 | } | |
3196 | ||
3197 | return false; | |
3198 | } | |
3199 | ||
6aa8b732 AK |
3200 | #define PTTYPE 64 |
3201 | #include "paging_tmpl.h" | |
3202 | #undef PTTYPE | |
3203 | ||
3204 | #define PTTYPE 32 | |
3205 | #include "paging_tmpl.h" | |
3206 | #undef PTTYPE | |
3207 | ||
52fde8df | 3208 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3209 | struct kvm_mmu *context) |
82725b20 | 3210 | { |
82725b20 DE |
3211 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3212 | u64 exb_bit_rsvd = 0; | |
3213 | ||
2d48a985 | 3214 | if (!context->nx) |
82725b20 | 3215 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3216 | switch (context->root_level) { |
82725b20 DE |
3217 | case PT32_ROOT_LEVEL: |
3218 | /* no rsvd bits for 2 level 4K page table entries */ | |
3219 | context->rsvd_bits_mask[0][1] = 0; | |
3220 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3221 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3222 | ||
3223 | if (!is_pse(vcpu)) { | |
3224 | context->rsvd_bits_mask[1][1] = 0; | |
3225 | break; | |
3226 | } | |
3227 | ||
82725b20 DE |
3228 | if (is_cpuid_PSE36()) |
3229 | /* 36bits PSE 4MB page */ | |
3230 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3231 | else | |
3232 | /* 32 bits PSE 4MB page */ | |
3233 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3234 | break; |
3235 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3236 | context->rsvd_bits_mask[0][2] = |
3237 | rsvd_bits(maxphyaddr, 63) | | |
3238 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3239 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3240 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3241 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3242 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3243 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3244 | rsvd_bits(maxphyaddr, 62) | | |
3245 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3246 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3247 | break; |
3248 | case PT64_ROOT_LEVEL: | |
3249 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3250 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3251 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3252 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3253 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3254 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3255 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3256 | rsvd_bits(maxphyaddr, 51); | |
3257 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3258 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3259 | rsvd_bits(maxphyaddr, 51) | | |
3260 | rsvd_bits(13, 29); | |
82725b20 | 3261 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3262 | rsvd_bits(maxphyaddr, 51) | |
3263 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3264 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3265 | break; |
3266 | } | |
3267 | } | |
3268 | ||
52fde8df JR |
3269 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3270 | struct kvm_mmu *context, | |
3271 | int level) | |
6aa8b732 | 3272 | { |
2d48a985 | 3273 | context->nx = is_nx(vcpu); |
4d6931c3 | 3274 | context->root_level = level; |
2d48a985 | 3275 | |
4d6931c3 | 3276 | reset_rsvds_bits_mask(vcpu, context); |
6aa8b732 AK |
3277 | |
3278 | ASSERT(is_pae(vcpu)); | |
3279 | context->new_cr3 = paging_new_cr3; | |
3280 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3281 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3282 | context->sync_page = paging64_sync_page; |
a7052897 | 3283 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3284 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3285 | context->free = paging_free; |
17ac10ad | 3286 | context->shadow_root_level = level; |
17c3ba9d | 3287 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3288 | context->direct_map = false; |
6aa8b732 AK |
3289 | return 0; |
3290 | } | |
3291 | ||
52fde8df JR |
3292 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3293 | struct kvm_mmu *context) | |
17ac10ad | 3294 | { |
52fde8df | 3295 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3296 | } |
3297 | ||
52fde8df JR |
3298 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3299 | struct kvm_mmu *context) | |
6aa8b732 | 3300 | { |
2d48a985 | 3301 | context->nx = false; |
4d6931c3 | 3302 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3303 | |
4d6931c3 | 3304 | reset_rsvds_bits_mask(vcpu, context); |
6aa8b732 AK |
3305 | |
3306 | context->new_cr3 = paging_new_cr3; | |
3307 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3308 | context->gva_to_gpa = paging32_gva_to_gpa; |
3309 | context->free = paging_free; | |
e8bc217a | 3310 | context->sync_page = paging32_sync_page; |
a7052897 | 3311 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3312 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3313 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3314 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3315 | context->direct_map = false; |
6aa8b732 AK |
3316 | return 0; |
3317 | } | |
3318 | ||
52fde8df JR |
3319 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3320 | struct kvm_mmu *context) | |
6aa8b732 | 3321 | { |
52fde8df | 3322 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3323 | } |
3324 | ||
fb72d167 JR |
3325 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3326 | { | |
14dfe855 | 3327 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3328 | |
c445f8ef | 3329 | context->base_role.word = 0; |
fb72d167 JR |
3330 | context->new_cr3 = nonpaging_new_cr3; |
3331 | context->page_fault = tdp_page_fault; | |
3332 | context->free = nonpaging_free; | |
e8bc217a | 3333 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3334 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3335 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3336 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3337 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3338 | context->direct_map = true; |
1c97f0a0 | 3339 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3340 | context->get_cr3 = get_cr3; |
e4e517b4 | 3341 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3342 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3343 | |
3344 | if (!is_paging(vcpu)) { | |
2d48a985 | 3345 | context->nx = false; |
fb72d167 JR |
3346 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3347 | context->root_level = 0; | |
3348 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3349 | context->nx = is_nx(vcpu); |
fb72d167 | 3350 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3351 | reset_rsvds_bits_mask(vcpu, context); |
3352 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3353 | } else if (is_pae(vcpu)) { |
2d48a985 | 3354 | context->nx = is_nx(vcpu); |
fb72d167 | 3355 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3356 | reset_rsvds_bits_mask(vcpu, context); |
3357 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3358 | } else { |
2d48a985 | 3359 | context->nx = false; |
fb72d167 | 3360 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3361 | reset_rsvds_bits_mask(vcpu, context); |
3362 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3363 | } |
3364 | ||
3365 | return 0; | |
3366 | } | |
3367 | ||
52fde8df | 3368 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3369 | { |
a770f6f2 | 3370 | int r; |
411c588d | 3371 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3372 | ASSERT(vcpu); |
ad312c7c | 3373 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3374 | |
3375 | if (!is_paging(vcpu)) | |
52fde8df | 3376 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3377 | else if (is_long_mode(vcpu)) |
52fde8df | 3378 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3379 | else if (is_pae(vcpu)) |
52fde8df | 3380 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3381 | else |
52fde8df | 3382 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3383 | |
5b7e0102 | 3384 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3385 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3386 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3387 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3388 | |
3389 | return r; | |
3390 | } | |
3391 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3392 | ||
3393 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3394 | { | |
14dfe855 | 3395 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3396 | |
14dfe855 JR |
3397 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3398 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3399 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3400 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3401 | |
3402 | return r; | |
6aa8b732 AK |
3403 | } |
3404 | ||
02f59dc9 JR |
3405 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3406 | { | |
3407 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3408 | ||
3409 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3410 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3411 | g_context->inject_page_fault = kvm_inject_page_fault; |
3412 | ||
3413 | /* | |
3414 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3415 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3416 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3417 | * functions between mmu and nested_mmu are swapped. | |
3418 | */ | |
3419 | if (!is_paging(vcpu)) { | |
2d48a985 | 3420 | g_context->nx = false; |
02f59dc9 JR |
3421 | g_context->root_level = 0; |
3422 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3423 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3424 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3425 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3426 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3427 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3428 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3429 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3430 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3431 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3432 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3433 | } else { | |
2d48a985 | 3434 | g_context->nx = false; |
02f59dc9 | 3435 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3436 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3437 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3438 | } | |
3439 | ||
3440 | return 0; | |
3441 | } | |
3442 | ||
fb72d167 JR |
3443 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3444 | { | |
02f59dc9 JR |
3445 | if (mmu_is_nested(vcpu)) |
3446 | return init_kvm_nested_mmu(vcpu); | |
3447 | else if (tdp_enabled) | |
fb72d167 JR |
3448 | return init_kvm_tdp_mmu(vcpu); |
3449 | else | |
3450 | return init_kvm_softmmu(vcpu); | |
3451 | } | |
3452 | ||
6aa8b732 AK |
3453 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3454 | { | |
3455 | ASSERT(vcpu); | |
62ad0755 SY |
3456 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3457 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3458 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3459 | } |
3460 | ||
3461 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3462 | { |
3463 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3464 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3465 | } |
8668a3c4 | 3466 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3467 | |
3468 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3469 | { |
714b93da AK |
3470 | int r; |
3471 | ||
e2dec939 | 3472 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3473 | if (r) |
3474 | goto out; | |
8986ecc0 | 3475 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3476 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3477 | mmu_sync_roots(vcpu); |
aaee2c94 | 3478 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3479 | if (r) |
3480 | goto out; | |
3662cb1c | 3481 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3482 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3483 | out: |
3484 | return r; | |
6aa8b732 | 3485 | } |
17c3ba9d AK |
3486 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3487 | ||
3488 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3489 | { | |
3490 | mmu_free_roots(vcpu); | |
3491 | } | |
4b16184c | 3492 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3493 | |
0028425f | 3494 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3495 | struct kvm_mmu_page *sp, u64 *spte, |
3496 | const void *new) | |
0028425f | 3497 | { |
30945387 | 3498 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3499 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3500 | return; | |
30945387 | 3501 | } |
0028425f | 3502 | |
4cee5764 | 3503 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3504 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3505 | } |
3506 | ||
79539cec AK |
3507 | static bool need_remote_flush(u64 old, u64 new) |
3508 | { | |
3509 | if (!is_shadow_present_pte(old)) | |
3510 | return false; | |
3511 | if (!is_shadow_present_pte(new)) | |
3512 | return true; | |
3513 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3514 | return true; | |
3515 | old ^= PT64_NX_MASK; | |
3516 | new ^= PT64_NX_MASK; | |
3517 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3518 | } | |
3519 | ||
0671a8e7 XG |
3520 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3521 | bool remote_flush, bool local_flush) | |
79539cec | 3522 | { |
0671a8e7 XG |
3523 | if (zap_page) |
3524 | return; | |
3525 | ||
3526 | if (remote_flush) | |
79539cec | 3527 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3528 | else if (local_flush) |
79539cec AK |
3529 | kvm_mmu_flush_tlb(vcpu); |
3530 | } | |
3531 | ||
889e5cbc XG |
3532 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3533 | const u8 *new, int *bytes) | |
da4a00f0 | 3534 | { |
889e5cbc XG |
3535 | u64 gentry; |
3536 | int r; | |
72016f3a | 3537 | |
72016f3a AK |
3538 | /* |
3539 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3540 | * as the current vcpu paging mode since we update the sptes only |
3541 | * when they have the same mode. | |
72016f3a | 3542 | */ |
889e5cbc | 3543 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3544 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3545 | *gpa &= ~(gpa_t)7; |
3546 | *bytes = 8; | |
3547 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8)); | |
72016f3a AK |
3548 | if (r) |
3549 | gentry = 0; | |
08e850c6 AK |
3550 | new = (const u8 *)&gentry; |
3551 | } | |
3552 | ||
889e5cbc | 3553 | switch (*bytes) { |
08e850c6 AK |
3554 | case 4: |
3555 | gentry = *(const u32 *)new; | |
3556 | break; | |
3557 | case 8: | |
3558 | gentry = *(const u64 *)new; | |
3559 | break; | |
3560 | default: | |
3561 | gentry = 0; | |
3562 | break; | |
72016f3a AK |
3563 | } |
3564 | ||
889e5cbc XG |
3565 | return gentry; |
3566 | } | |
3567 | ||
3568 | /* | |
3569 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3570 | * or we may be forking, in which case it is better to unmap the page. | |
3571 | */ | |
a138fe75 | 3572 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3573 | { |
a30f47cb XG |
3574 | /* |
3575 | * Skip write-flooding detected for the sp whose level is 1, because | |
3576 | * it can become unsync, then the guest page is not write-protected. | |
3577 | */ | |
3578 | if (sp->role.level == 1) | |
3579 | return false; | |
3246af0e | 3580 | |
a30f47cb | 3581 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3582 | } |
3583 | ||
3584 | /* | |
3585 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3586 | * indicate a page is not used as a page table. | |
3587 | */ | |
3588 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3589 | int bytes) | |
3590 | { | |
3591 | unsigned offset, pte_size, misaligned; | |
3592 | ||
3593 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3594 | gpa, bytes, sp->role.word); | |
3595 | ||
3596 | offset = offset_in_page(gpa); | |
3597 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3598 | |
3599 | /* | |
3600 | * Sometimes, the OS only writes the last one bytes to update status | |
3601 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3602 | */ | |
3603 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3604 | return false; | |
3605 | ||
889e5cbc XG |
3606 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3607 | misaligned |= bytes < 4; | |
3608 | ||
3609 | return misaligned; | |
3610 | } | |
3611 | ||
3612 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3613 | { | |
3614 | unsigned page_offset, quadrant; | |
3615 | u64 *spte; | |
3616 | int level; | |
3617 | ||
3618 | page_offset = offset_in_page(gpa); | |
3619 | level = sp->role.level; | |
3620 | *nspte = 1; | |
3621 | if (!sp->role.cr4_pae) { | |
3622 | page_offset <<= 1; /* 32->64 */ | |
3623 | /* | |
3624 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3625 | * only 2MB. So we need to double the offset again | |
3626 | * and zap two pdes instead of one. | |
3627 | */ | |
3628 | if (level == PT32_ROOT_LEVEL) { | |
3629 | page_offset &= ~7; /* kill rounding error */ | |
3630 | page_offset <<= 1; | |
3631 | *nspte = 2; | |
3632 | } | |
3633 | quadrant = page_offset >> PAGE_SHIFT; | |
3634 | page_offset &= ~PAGE_MASK; | |
3635 | if (quadrant != sp->role.quadrant) | |
3636 | return NULL; | |
3637 | } | |
3638 | ||
3639 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3640 | return spte; | |
3641 | } | |
3642 | ||
3643 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3644 | const u8 *new, int bytes) | |
3645 | { | |
3646 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3647 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3648 | struct kvm_mmu_page *sp; | |
3649 | struct hlist_node *node; | |
3650 | LIST_HEAD(invalid_list); | |
3651 | u64 entry, gentry, *spte; | |
3652 | int npte; | |
a30f47cb | 3653 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3654 | |
3655 | /* | |
3656 | * If we don't have indirect shadow pages, it means no page is | |
3657 | * write-protected, so we can exit simply. | |
3658 | */ | |
3659 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3660 | return; | |
3661 | ||
3662 | zap_page = remote_flush = local_flush = false; | |
3663 | ||
3664 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3665 | ||
3666 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3667 | ||
3668 | /* | |
3669 | * No need to care whether allocation memory is successful | |
3670 | * or not since pte prefetch is skiped if it does not have | |
3671 | * enough objects in the cache. | |
3672 | */ | |
3673 | mmu_topup_memory_caches(vcpu); | |
3674 | ||
3675 | spin_lock(&vcpu->kvm->mmu_lock); | |
3676 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 3677 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 3678 | |
fa1de2bf | 3679 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3680 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
a30f47cb | 3681 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 3682 | detect_write_flooding(sp)) { |
0671a8e7 | 3683 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3684 | &invalid_list); |
4cee5764 | 3685 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3686 | continue; |
3687 | } | |
889e5cbc XG |
3688 | |
3689 | spte = get_written_sptes(sp, gpa, &npte); | |
3690 | if (!spte) | |
3691 | continue; | |
3692 | ||
0671a8e7 | 3693 | local_flush = true; |
ac1b714e | 3694 | while (npte--) { |
79539cec | 3695 | entry = *spte; |
38e3b2b2 | 3696 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
3697 | if (gentry && |
3698 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 3699 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 3700 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3701 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3702 | remote_flush = true; | |
ac1b714e | 3703 | ++spte; |
9b7a0325 | 3704 | } |
9b7a0325 | 3705 | } |
0671a8e7 | 3706 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3707 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 3708 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3709 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
3710 | } |
3711 | ||
a436036b AK |
3712 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3713 | { | |
10589a46 MT |
3714 | gpa_t gpa; |
3715 | int r; | |
a436036b | 3716 | |
c5a78f2b | 3717 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3718 | return 0; |
3719 | ||
1871c602 | 3720 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3721 | |
10589a46 | 3722 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 3723 | |
10589a46 | 3724 | return r; |
a436036b | 3725 | } |
577bdc49 | 3726 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3727 | |
22d95b12 | 3728 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3729 | { |
d98ba053 | 3730 | LIST_HEAD(invalid_list); |
103ad25a | 3731 | |
e0df7b9f | 3732 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3733 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3734 | struct kvm_mmu_page *sp; |
ebeace86 | 3735 | |
f05e70ac | 3736 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3737 | struct kvm_mmu_page, link); |
e0df7b9f | 3738 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 3739 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 3740 | } |
aa6bd187 | 3741 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 3742 | } |
ebeace86 | 3743 | |
1cb3f3ae XG |
3744 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
3745 | { | |
3746 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
3747 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3748 | ||
3749 | return vcpu_match_mmio_gva(vcpu, addr); | |
3750 | } | |
3751 | ||
dc25e89e AP |
3752 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
3753 | void *insn, int insn_len) | |
3067714c | 3754 | { |
1cb3f3ae | 3755 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
3756 | enum emulation_result er; |
3757 | ||
56028d08 | 3758 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3759 | if (r < 0) |
3760 | goto out; | |
3761 | ||
3762 | if (!r) { | |
3763 | r = 1; | |
3764 | goto out; | |
3765 | } | |
3766 | ||
1cb3f3ae XG |
3767 | if (is_mmio_page_fault(vcpu, cr2)) |
3768 | emulation_type = 0; | |
3769 | ||
3770 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
3771 | |
3772 | switch (er) { | |
3773 | case EMULATE_DONE: | |
3774 | return 1; | |
3775 | case EMULATE_DO_MMIO: | |
3776 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3777 | /* fall through */ |
3067714c | 3778 | case EMULATE_FAIL: |
3f5d18a9 | 3779 | return 0; |
3067714c AK |
3780 | default: |
3781 | BUG(); | |
3782 | } | |
3783 | out: | |
3067714c AK |
3784 | return r; |
3785 | } | |
3786 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3787 | ||
a7052897 MT |
3788 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3789 | { | |
a7052897 | 3790 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3791 | kvm_mmu_flush_tlb(vcpu); |
3792 | ++vcpu->stat.invlpg; | |
3793 | } | |
3794 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3795 | ||
18552672 JR |
3796 | void kvm_enable_tdp(void) |
3797 | { | |
3798 | tdp_enabled = true; | |
3799 | } | |
3800 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3801 | ||
5f4cb662 JR |
3802 | void kvm_disable_tdp(void) |
3803 | { | |
3804 | tdp_enabled = false; | |
3805 | } | |
3806 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3807 | ||
6aa8b732 AK |
3808 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3809 | { | |
ad312c7c | 3810 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3811 | if (vcpu->arch.mmu.lm_root != NULL) |
3812 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3813 | } |
3814 | ||
3815 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3816 | { | |
17ac10ad | 3817 | struct page *page; |
6aa8b732 AK |
3818 | int i; |
3819 | ||
3820 | ASSERT(vcpu); | |
3821 | ||
17ac10ad AK |
3822 | /* |
3823 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3824 | * Therefore we need to allocate shadow page tables in the first | |
3825 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3826 | */ | |
3827 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3828 | if (!page) | |
d7fa6ab2 WY |
3829 | return -ENOMEM; |
3830 | ||
ad312c7c | 3831 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3832 | for (i = 0; i < 4; ++i) |
ad312c7c | 3833 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3834 | |
6aa8b732 | 3835 | return 0; |
6aa8b732 AK |
3836 | } |
3837 | ||
8018c27b | 3838 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3839 | { |
6aa8b732 | 3840 | ASSERT(vcpu); |
e459e322 XG |
3841 | |
3842 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
3843 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
3844 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
3845 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 3846 | |
8018c27b IM |
3847 | return alloc_mmu_pages(vcpu); |
3848 | } | |
6aa8b732 | 3849 | |
8018c27b IM |
3850 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3851 | { | |
3852 | ASSERT(vcpu); | |
ad312c7c | 3853 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3854 | |
8018c27b | 3855 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3856 | } |
3857 | ||
90cb0529 | 3858 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3859 | { |
4db35314 | 3860 | struct kvm_mmu_page *sp; |
6aa8b732 | 3861 | |
f05e70ac | 3862 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3863 | int i; |
3864 | u64 *pt; | |
3865 | ||
291f26bc | 3866 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3867 | continue; |
3868 | ||
4db35314 | 3869 | pt = sp->spt; |
8234b22e | 3870 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
da8dc75f XG |
3871 | if (!is_shadow_present_pte(pt[i]) || |
3872 | !is_last_spte(pt[i], sp->role.level)) | |
3873 | continue; | |
3874 | ||
3875 | if (is_large_pte(pt[i])) { | |
c3707958 | 3876 | drop_spte(kvm, &pt[i]); |
8234b22e | 3877 | --kvm->stat.lpages; |
da8dc75f | 3878 | continue; |
8234b22e | 3879 | } |
da8dc75f | 3880 | |
6aa8b732 | 3881 | /* avoid RMW */ |
01c168ac | 3882 | if (is_writable_pte(pt[i])) |
1df9f2dc XG |
3883 | mmu_spte_update(&pt[i], |
3884 | pt[i] & ~PT_WRITABLE_MASK); | |
8234b22e | 3885 | } |
6aa8b732 | 3886 | } |
171d595d | 3887 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3888 | } |
37a7d8b0 | 3889 | |
90cb0529 | 3890 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3891 | { |
4db35314 | 3892 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3893 | LIST_HEAD(invalid_list); |
e0fa826f | 3894 | |
aaee2c94 | 3895 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3896 | restart: |
f05e70ac | 3897 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3898 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3899 | goto restart; |
3900 | ||
d98ba053 | 3901 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3902 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3903 | } |
3904 | ||
3d56cbdf JK |
3905 | static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3906 | struct list_head *invalid_list) | |
3ee16c81 IE |
3907 | { |
3908 | struct kvm_mmu_page *page; | |
3909 | ||
3910 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3911 | struct kvm_mmu_page, link); | |
3d56cbdf | 3912 | kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3913 | } |
3914 | ||
1495f230 | 3915 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
3916 | { |
3917 | struct kvm *kvm; | |
3918 | struct kvm *kvm_freed = NULL; | |
1495f230 | 3919 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
3920 | |
3921 | if (nr_to_scan == 0) | |
3922 | goto out; | |
3ee16c81 | 3923 | |
e935b837 | 3924 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
3925 | |
3926 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 3927 | int idx; |
d98ba053 | 3928 | LIST_HEAD(invalid_list); |
3ee16c81 | 3929 | |
f656ce01 | 3930 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3931 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3932 | if (!kvm_freed && nr_to_scan > 0 && |
3933 | kvm->arch.n_used_mmu_pages > 0) { | |
3d56cbdf JK |
3934 | kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3935 | &invalid_list); | |
3ee16c81 IE |
3936 | kvm_freed = kvm; |
3937 | } | |
3938 | nr_to_scan--; | |
3939 | ||
d98ba053 | 3940 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3941 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3942 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3943 | } |
3944 | if (kvm_freed) | |
3945 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3946 | ||
e935b837 | 3947 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 3948 | |
45221ab6 DH |
3949 | out: |
3950 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3951 | } |
3952 | ||
3953 | static struct shrinker mmu_shrinker = { | |
3954 | .shrink = mmu_shrink, | |
3955 | .seeks = DEFAULT_SEEKS * 10, | |
3956 | }; | |
3957 | ||
2ddfd20e | 3958 | static void mmu_destroy_caches(void) |
b5a33a75 | 3959 | { |
53c07b18 XG |
3960 | if (pte_list_desc_cache) |
3961 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
3962 | if (mmu_page_header_cache) |
3963 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3964 | } |
3965 | ||
3966 | int kvm_mmu_module_init(void) | |
3967 | { | |
53c07b18 XG |
3968 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
3969 | sizeof(struct pte_list_desc), | |
20c2df83 | 3970 | 0, 0, NULL); |
53c07b18 | 3971 | if (!pte_list_desc_cache) |
b5a33a75 AK |
3972 | goto nomem; |
3973 | ||
d3d25b04 AK |
3974 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3975 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3976 | 0, 0, NULL); |
d3d25b04 AK |
3977 | if (!mmu_page_header_cache) |
3978 | goto nomem; | |
3979 | ||
45bf21a8 WY |
3980 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3981 | goto nomem; | |
3982 | ||
3ee16c81 IE |
3983 | register_shrinker(&mmu_shrinker); |
3984 | ||
b5a33a75 AK |
3985 | return 0; |
3986 | ||
3987 | nomem: | |
3ee16c81 | 3988 | mmu_destroy_caches(); |
b5a33a75 AK |
3989 | return -ENOMEM; |
3990 | } | |
3991 | ||
3ad82a7e ZX |
3992 | /* |
3993 | * Caculate mmu pages needed for kvm. | |
3994 | */ | |
3995 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3996 | { | |
3ad82a7e ZX |
3997 | unsigned int nr_mmu_pages; |
3998 | unsigned int nr_pages = 0; | |
bc6678a3 | 3999 | struct kvm_memslots *slots; |
be6ba0f0 | 4000 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4001 | |
90d83dc3 LJ |
4002 | slots = kvm_memslots(kvm); |
4003 | ||
be6ba0f0 XG |
4004 | kvm_for_each_memslot(memslot, slots) |
4005 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4006 | |
4007 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4008 | nr_mmu_pages = max(nr_mmu_pages, | |
4009 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4010 | ||
4011 | return nr_mmu_pages; | |
4012 | } | |
4013 | ||
94d8b056 MT |
4014 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4015 | { | |
4016 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4017 | u64 spte; |
94d8b056 MT |
4018 | int nr_sptes = 0; |
4019 | ||
c2a2ac2b XG |
4020 | walk_shadow_page_lockless_begin(vcpu); |
4021 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4022 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4023 | nr_sptes++; |
c2a2ac2b | 4024 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4025 | break; |
4026 | } | |
c2a2ac2b | 4027 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4028 | |
4029 | return nr_sptes; | |
4030 | } | |
4031 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4032 | ||
c42fffe3 XG |
4033 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4034 | { | |
4035 | ASSERT(vcpu); | |
4036 | ||
4037 | destroy_kvm_mmu(vcpu); | |
4038 | free_mmu_pages(vcpu); | |
4039 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4040 | } |
4041 | ||
b034cf01 XG |
4042 | void kvm_mmu_module_exit(void) |
4043 | { | |
4044 | mmu_destroy_caches(); | |
4045 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4046 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4047 | mmu_audit_disable(); |
4048 | } |